From e8fb4e7d85d118fac3ef7d5163f5dcd7655adb4e Mon Sep 17 00:00:00 2001 From: Amilendra Kodithuwakku Date: Mon, 15 Sep 2025 15:42:47 +0100 Subject: [PATCH 01/12] Add intrinsics for the FEAT_SVE_AES2 feature introduced by the 2024 dpISA FEAT_SVE_AES2 adds 1) SVE multi-vector Advanced Encryption Standard (AES) instructions Instructions added: AESE, AESD, AESEMC and AESDIMC For each instruction there are two variants a) Two registers variant b) Four registers variant 2) SVE multi-vector 128-bit polynomial multiply long instructions Instructions added: PMULL and PMLAL FEAT_SSVE_AES implements the same instructions but when in streaming mode. --- main/acle.md | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/main/acle.md b/main/acle.md index 3b066e93..b9007fc9 100644 --- a/main/acle.md +++ b/main/acle.md @@ -465,6 +465,7 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin * Added feature test macro for FEAT_SSVE_FEXPA. * Added feature test macro for FEAT_CSSC. +* Added support for FEAT_SVE_AES2, FEAT_SSVE_AES intrinsics. ### References @@ -2147,6 +2148,15 @@ support for the SVE2 AES (FEAT_SVE_AES) instructions and if the associated ACLE intrinsics are available. This implies that `__ARM_FEATURE_AES` and `__ARM_FEATURE_SVE2` are both nonzero. +In addition, `__ARM_FEATURE_SVE2_AES2` is defined to `1` if there is hardware +support for the SVE2 AES2 (FEAT_SVE_AES2) instructions and if the associated +ACLE intrinsics are available. This implies that `__ARM_FEATURE_AES` +and `__ARM_FEATURE_SVE2` are both nonzero. + +`__ARM_FEATURE_SSVE_AES2` is defined to 1 if there is hardware support for +SVE2 AES2 (FEAT_SVE_AES2) instructions in Streaming SVE mode (FEAT_SSVE_AES) +and if the associated ACLE intrinsics are available. + #### SHA2 extension `__ARM_FEATURE_SHA2` is defined to 1 if the SHA1 & SHA2-256 Crypto @@ -2642,6 +2652,8 @@ be found in [[BA]](#BA). | [`__ARM_FEATURE_SVE_VECTOR_OPERATORS`](#scalable-vector-extension-sve) | Level of support for C and C++ operators on SVE predicate types | 1 | | [`__ARM_FEATURE_SVE2`](#sve2) | SVE version 2 (FEAT_SVE2) | 1 | | [`__ARM_FEATURE_SVE2_AES`](#aes-extension) | SVE2 support for the AES cryptographic extension (FEAT_SVE_AES) | 1 | +| [`__ARM_FEATURE_SVE2_AES2`](#aes-extension) | SVE2 support for the SVE multi-vector AES cryptographic extension (FEAT_SVE_AES2) | 1 | +| [`__ARM_FEATURE_SSVE_AES2`](#aes-extension) | SVE2 support for the SVE multi-vector AES cryptographic extension (FEAT_SSVE_AES) | 1 | | [`__ARM_FEATURE_SVE2_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | | [`__ARM_FEATURE_SSVE_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | | [`__ARM_FEATURE_SSVE_FEXPA`](#streaming-sve-fexpa-extension) | Streaming SVE FEXPA extension | 1 | @@ -9405,6 +9417,30 @@ to work with `svboolx2_t` and `svboolx4_t`. For example: svboolx2_t svundef2_b(); ``` +#### AESE, AESD, AESEMC, AESDIMC + +Multi-vector Advanced Encryption Standard instructions + +svuint8x2_t svaese[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); +svuint8x4_t svaese[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); +svuint8x2_t svaesd[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); +svuint8x4_t svaesd[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); +svuint8x2_t svaesemc[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); +svuint8x4_t svaesemc[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); +svuint8x2_t svaesdimc[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); +svuint8x4_t svaesdimc[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); + +#### PMULL, PMLAL + +Multi-vector 128-bit polynomial multiply long instructions + +``` c + // Variants are also available for: + // _s64x2, _f64x2 + svuint64x2_t svpmull[_u64x2](svuint64_t zn, svuint64_t zm); + svuint64x2_t svpmlal[_u64x2](svuint64_t zn, svuint64_t zm); + ``` + #### ADDQV, FADDQV Unsigned/FP add reduction of quadword vector segments. From 4505e29abc9f8c462f4bc1e0fca9c6becfdfa268 Mon Sep 17 00:00:00 2001 From: Amilendra Kodithuwakku Date: Tue, 7 Oct 2025 16:22:19 +0100 Subject: [PATCH 02/12] Fix the AES2 review comments. 1.__ARM_FEATURE_SSVE_AES2 -> __ARM_FEATURE_SSVE_AES 2. Move the intrinsics to their own section under SVE2 --- main/acle.md | 66 +++++++++++++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 29 deletions(-) diff --git a/main/acle.md b/main/acle.md index b9007fc9..6f4d770c 100644 --- a/main/acle.md +++ b/main/acle.md @@ -2150,10 +2150,9 @@ and `__ARM_FEATURE_SVE2` are both nonzero. In addition, `__ARM_FEATURE_SVE2_AES2` is defined to `1` if there is hardware support for the SVE2 AES2 (FEAT_SVE_AES2) instructions and if the associated -ACLE intrinsics are available. This implies that `__ARM_FEATURE_AES` -and `__ARM_FEATURE_SVE2` are both nonzero. +ACLE intrinsics are available. -`__ARM_FEATURE_SSVE_AES2` is defined to 1 if there is hardware support for +`__ARM_FEATURE_SSVE_AES` is defined to 1 if there is hardware support for SVE2 AES2 (FEAT_SVE_AES2) instructions in Streaming SVE mode (FEAT_SSVE_AES) and if the associated ACLE intrinsics are available. @@ -2652,8 +2651,8 @@ be found in [[BA]](#BA). | [`__ARM_FEATURE_SVE_VECTOR_OPERATORS`](#scalable-vector-extension-sve) | Level of support for C and C++ operators on SVE predicate types | 1 | | [`__ARM_FEATURE_SVE2`](#sve2) | SVE version 2 (FEAT_SVE2) | 1 | | [`__ARM_FEATURE_SVE2_AES`](#aes-extension) | SVE2 support for the AES cryptographic extension (FEAT_SVE_AES) | 1 | -| [`__ARM_FEATURE_SVE2_AES2`](#aes-extension) | SVE2 support for the SVE multi-vector AES cryptographic extension (FEAT_SVE_AES2) | 1 | -| [`__ARM_FEATURE_SSVE_AES2`](#aes-extension) | SVE2 support for the SVE multi-vector AES cryptographic extension (FEAT_SSVE_AES) | 1 | +| [`__ARM_FEATURE_SVE2_AES2`](#aes-extension) | SVE2 support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SVE_AES2) | 1 | +| [`__ARM_FEATURE_SSVE_AES`](#aes-extension) | SVE2 support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SSVE_AES) | 1 | | [`__ARM_FEATURE_SVE2_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | | [`__ARM_FEATURE_SSVE_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | | [`__ARM_FEATURE_SSVE_FEXPA`](#streaming-sve-fexpa-extension) | Streaming SVE FEXPA extension | 1 | @@ -9417,30 +9416,6 @@ to work with `svboolx2_t` and `svboolx4_t`. For example: svboolx2_t svundef2_b(); ``` -#### AESE, AESD, AESEMC, AESDIMC - -Multi-vector Advanced Encryption Standard instructions - -svuint8x2_t svaese[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); -svuint8x4_t svaese[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); -svuint8x2_t svaesd[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); -svuint8x4_t svaesd[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); -svuint8x2_t svaesemc[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); -svuint8x4_t svaesemc[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); -svuint8x2_t svaesdimc[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); -svuint8x4_t svaesdimc[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); - -#### PMULL, PMLAL - -Multi-vector 128-bit polynomial multiply long instructions - -``` c - // Variants are also available for: - // _s64x2, _f64x2 - svuint64x2_t svpmull[_u64x2](svuint64_t zn, svuint64_t zm); - svuint64x2_t svpmlal[_u64x2](svuint64_t zn, svuint64_t zm); - ``` - #### ADDQV, FADDQV Unsigned/FP add reduction of quadword vector segments. @@ -9748,6 +9723,39 @@ Lookup table read with 4-bit indices. svint16_t svluti4_lane[_s16_x2](svint16x2_t table, svuint8_t indices, uint64_t imm_idx); ``` +### SVE2 Multi-vector AES and 128-bit polynomial multiply long instructions + + +#### AESE, AESD, AESEMC, AESDIMC + +Multi-vector Advanced Encryption Standard instructions + +```c + // Only if __ARM_FEATURE_SVE2_AES2 != 0 or __ARM_FEATURE_SSVE_AES != 0 + + svuint8x2_t svaese[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); + svuint8x4_t svaese[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); + svuint8x2_t svaesd[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); + svuint8x4_t svaesd[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); + svuint8x2_t svaesemc[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); + svuint8x4_t svaesemc[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); + svuint8x2_t svaesdimc[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); + svuint8x4_t svaesdimc[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); +``` + +#### PMULL, PMLAL + +Multi-vector 128-bit polynomial multiply long instructions + +``` c + // Only if __ARM_FEATURE_SVE2_AES2 != 0 or __ARM_FEATURE_SSVE_AES != 0 + + // Variants are also available for: + // _s64x2, _f64x2 + svuint64x2_t svpmull[_u64x2](svuint64_t zn, svuint64_t zm); + svuint64x2_t svpmlal[_u64x2](svuint64_t zn, svuint64_t zm); + ``` + # SME language extensions and intrinsics The specification for SME is in From 961267413a6d288569d5ce4ec369cad4b5d101fa Mon Sep 17 00:00:00 2001 From: Amilendra Kodithuwakku Date: Fri, 10 Oct 2025 09:48:17 +0100 Subject: [PATCH 03/12] Add SVE2 AES2 support status (Alpha) to the content --- main/acle.md | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/main/acle.md b/main/acle.md index 6f4d770c..a1084b7a 100644 --- a/main/acle.md +++ b/main/acle.md @@ -465,7 +465,8 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin * Added feature test macro for FEAT_SSVE_FEXPA. * Added feature test macro for FEAT_CSSC. -* Added support for FEAT_SVE_AES2, FEAT_SSVE_AES intrinsics. +* Added [**Alpha**](#current-status-and-anticipated-changes) support + for FEAT_SVE_AES2, FEAT_SSVE_AES intrinsics. ### References @@ -2156,6 +2157,10 @@ ACLE intrinsics are available. SVE2 AES2 (FEAT_SVE_AES2) instructions in Streaming SVE mode (FEAT_SSVE_AES) and if the associated ACLE intrinsics are available. +The specification for SVE2 AES2 (FEAT_SVE_AES2, FEAT_SSVE_AES) instructions is in +[**Alpha** state](#current-status-and-anticipated-changes) and might change or be +extended in the future. + #### SHA2 extension `__ARM_FEATURE_SHA2` is defined to 1 if the SHA1 & SHA2-256 Crypto @@ -9725,6 +9730,9 @@ Lookup table read with 4-bit indices. ### SVE2 Multi-vector AES and 128-bit polynomial multiply long instructions +The specification for SVE2 Multi-vector AES and 128-bit polynomial multiply long instructions is in +[**Alpha** state](#current-status-and-anticipated-changes) and might change or be +extended in the future. #### AESE, AESD, AESEMC, AESDIMC From 1a26687300fde25eb8978480935dad8cea972d81 Mon Sep 17 00:00:00 2001 From: Amilendra Kodithuwakku Date: Fri, 10 Oct 2025 15:33:06 +0100 Subject: [PATCH 04/12] [PMLAL] Add svuint64x2_t zda which acts as both input/output --- main/acle.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/main/acle.md b/main/acle.md index a1084b7a..e32ef85f 100644 --- a/main/acle.md +++ b/main/acle.md @@ -9761,7 +9761,7 @@ Multi-vector 128-bit polynomial multiply long instructions // Variants are also available for: // _s64x2, _f64x2 svuint64x2_t svpmull[_u64x2](svuint64_t zn, svuint64_t zm); - svuint64x2_t svpmlal[_u64x2](svuint64_t zn, svuint64_t zm); + svuint64x2_t svpmlal[_u64x2](svuint64x2_t zda, svuint64_t zn, svuint64_t zm); ``` # SME language extensions and intrinsics From 3909c7470790eb1752908c9567c93d95ddde9cd8 Mon Sep 17 00:00:00 2001 From: Amilendra Kodithuwakku Date: Wed, 15 Oct 2025 13:28:18 +0100 Subject: [PATCH 05/12] Address further AES2 review comments - __ARM_FEATURE_SVE2_AES2 -> __ARM_FEATURE_SVE_AES2 - Add _lane prefix --- main/acle.md | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/main/acle.md b/main/acle.md index e32ef85f..b646d5df 100644 --- a/main/acle.md +++ b/main/acle.md @@ -2149,7 +2149,7 @@ support for the SVE2 AES (FEAT_SVE_AES) instructions and if the associated ACLE intrinsics are available. This implies that `__ARM_FEATURE_AES` and `__ARM_FEATURE_SVE2` are both nonzero. -In addition, `__ARM_FEATURE_SVE2_AES2` is defined to `1` if there is hardware +In addition, `__ARM_FEATURE_SVE_AES2` is defined to `1` if there is hardware support for the SVE2 AES2 (FEAT_SVE_AES2) instructions and if the associated ACLE intrinsics are available. @@ -2656,7 +2656,7 @@ be found in [[BA]](#BA). | [`__ARM_FEATURE_SVE_VECTOR_OPERATORS`](#scalable-vector-extension-sve) | Level of support for C and C++ operators on SVE predicate types | 1 | | [`__ARM_FEATURE_SVE2`](#sve2) | SVE version 2 (FEAT_SVE2) | 1 | | [`__ARM_FEATURE_SVE2_AES`](#aes-extension) | SVE2 support for the AES cryptographic extension (FEAT_SVE_AES) | 1 | -| [`__ARM_FEATURE_SVE2_AES2`](#aes-extension) | SVE2 support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SVE_AES2) | 1 | +| [`__ARM_FEATURE_SVE_AES2`](#aes-extension) | SVE2 support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SVE_AES2) | 1 | | [`__ARM_FEATURE_SSVE_AES`](#aes-extension) | SVE2 support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SSVE_AES) | 1 | | [`__ARM_FEATURE_SVE2_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | | [`__ARM_FEATURE_SSVE_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | @@ -9739,16 +9739,16 @@ extended in the future. Multi-vector Advanced Encryption Standard instructions ```c - // Only if __ARM_FEATURE_SVE2_AES2 != 0 or __ARM_FEATURE_SSVE_AES != 0 + // Only if __ARM_FEATURE_SVE_AES2 != 0 - svuint8x2_t svaese[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); - svuint8x4_t svaese[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); - svuint8x2_t svaesd[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); - svuint8x4_t svaesd[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); - svuint8x2_t svaesemc[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); - svuint8x4_t svaesemc[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); - svuint8x2_t svaesdimc[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); - svuint8x4_t svaesdimc[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); + svuint8x2_t svaese_lane[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); + svuint8x4_t svaese_lane[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); + svuint8x2_t svaesd_lane[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); + svuint8x4_t svaesd_lane[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); + svuint8x2_t svaesemc_lane[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); + svuint8x4_t svaesemc_lane[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); + svuint8x2_t svaesdimc_lane[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); + svuint8x4_t svaesdimc_lane[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); ``` #### PMULL, PMLAL @@ -9756,7 +9756,7 @@ Multi-vector Advanced Encryption Standard instructions Multi-vector 128-bit polynomial multiply long instructions ``` c - // Only if __ARM_FEATURE_SVE2_AES2 != 0 or __ARM_FEATURE_SSVE_AES != 0 + // Only if __ARM_FEATURE_SVE_AES2 != 0 // Variants are also available for: // _s64x2, _f64x2 From 91e71c0698620178aad4ac76884408a1fdede960 Mon Sep 17 00:00:00 2001 From: Amilendra Kodithuwakku Date: Thu, 16 Oct 2025 13:04:12 +0100 Subject: [PATCH 06/12] Fix Typos: SVE2 -> SVE --- main/acle.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/main/acle.md b/main/acle.md index b646d5df..1e07c76b 100644 --- a/main/acle.md +++ b/main/acle.md @@ -2150,14 +2150,14 @@ ACLE intrinsics are available. This implies that `__ARM_FEATURE_AES` and `__ARM_FEATURE_SVE2` are both nonzero. In addition, `__ARM_FEATURE_SVE_AES2` is defined to `1` if there is hardware -support for the SVE2 AES2 (FEAT_SVE_AES2) instructions and if the associated +support for the SVE AES2 (FEAT_SVE_AES2) instructions and if the associated ACLE intrinsics are available. `__ARM_FEATURE_SSVE_AES` is defined to 1 if there is hardware support for -SVE2 AES2 (FEAT_SVE_AES2) instructions in Streaming SVE mode (FEAT_SSVE_AES) +SVE AES2 (FEAT_SVE_AES2) instructions in Streaming SVE mode (FEAT_SSVE_AES) and if the associated ACLE intrinsics are available. -The specification for SVE2 AES2 (FEAT_SVE_AES2, FEAT_SSVE_AES) instructions is in +The specification for SVE AES2 (FEAT_SVE_AES2, FEAT_SSVE_AES) instructions is in [**Alpha** state](#current-status-and-anticipated-changes) and might change or be extended in the future. @@ -2656,8 +2656,8 @@ be found in [[BA]](#BA). | [`__ARM_FEATURE_SVE_VECTOR_OPERATORS`](#scalable-vector-extension-sve) | Level of support for C and C++ operators on SVE predicate types | 1 | | [`__ARM_FEATURE_SVE2`](#sve2) | SVE version 2 (FEAT_SVE2) | 1 | | [`__ARM_FEATURE_SVE2_AES`](#aes-extension) | SVE2 support for the AES cryptographic extension (FEAT_SVE_AES) | 1 | -| [`__ARM_FEATURE_SVE_AES2`](#aes-extension) | SVE2 support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SVE_AES2) | 1 | -| [`__ARM_FEATURE_SSVE_AES`](#aes-extension) | SVE2 support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SSVE_AES) | 1 | +| [`__ARM_FEATURE_SVE_AES2`](#aes-extension) | SVE support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SVE_AES2) | 1 | +| [`__ARM_FEATURE_SSVE_AES`](#aes-extension) | SVE support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SSVE_AES) | 1 | | [`__ARM_FEATURE_SVE2_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | | [`__ARM_FEATURE_SSVE_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | | [`__ARM_FEATURE_SSVE_FEXPA`](#streaming-sve-fexpa-extension) | Streaming SVE FEXPA extension | 1 | From cc7d01cd844b28fdaacbbb231e8ce111b2ea7971 Mon Sep 17 00:00:00 2001 From: Amilendra Kodithuwakku Date: Thu, 13 Nov 2025 11:31:57 +0000 Subject: [PATCH 07/12] Add [_n] optional suffix for PMULL, PMLAL intrinsics. Make _u64x2 non-optional for PMULL --- main/acle.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/main/acle.md b/main/acle.md index 1e07c76b..ea09f118 100644 --- a/main/acle.md +++ b/main/acle.md @@ -9760,8 +9760,11 @@ Multi-vector 128-bit polynomial multiply long instructions // Variants are also available for: // _s64x2, _f64x2 - svuint64x2_t svpmull[_u64x2](svuint64_t zn, svuint64_t zm); + svuint64x2_t svpmull_u64x2(svuint64_t zn, svuint64_t zm); + svuint64x2_t svpmull[_n]_u64x2(svuint64_t zn, uint64_t zm); + svuint64x2_t svpmlal[_u64x2](svuint64x2_t zda, svuint64_t zn, svuint64_t zm); + svuint64x2_t svpmlal[_n_u64x2](svuint64x2_t zda, svuint64_t zn, uint64_t zm); ``` # SME language extensions and intrinsics From e294d8f6fe7c736d90289fbc019bb7fda8cf8df4 Mon Sep 17 00:00:00 2001 From: Amilendra Kodithuwakku Date: Thu, 13 Nov 2025 12:31:06 +0000 Subject: [PATCH 08/12] Match parameter names with instruction operand names --- main/acle.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/main/acle.md b/main/acle.md index ea09f118..fc3ba3f9 100644 --- a/main/acle.md +++ b/main/acle.md @@ -9741,14 +9741,14 @@ Multi-vector Advanced Encryption Standard instructions ```c // Only if __ARM_FEATURE_SVE_AES2 != 0 - svuint8x2_t svaese_lane[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); - svuint8x4_t svaese_lane[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); - svuint8x2_t svaesd_lane[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); - svuint8x4_t svaesd_lane[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); - svuint8x2_t svaesemc_lane[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); - svuint8x4_t svaesemc_lane[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); - svuint8x2_t svaesdimc_lane[_u8_x2] (svuint8x2_t op1, svuint64_t op2, uint64_t index); - svuint8x4_t svaesdimc_lane[_u8_x4] (svuint8x4_t op1, svuint64_t op2, uint64_t index); + svuint8x2_t svaese_lane[_u8_x2] (svuint8x2_t zdn, svuint64_t zm, uint64_t index); + svuint8x4_t svaese_lane[_u8_x4] (svuint8x4_t zdn, svuint64_t zm, uint64_t index); + svuint8x2_t svaesd_lane[_u8_x2] (svuint8x2_t zdn, svuint64_t zm, uint64_t index); + svuint8x4_t svaesd_lane[_u8_x4] (svuint8x4_t zdn, svuint64_t zm, uint64_t index); + svuint8x2_t svaesemc_lane[_u8_x2] (svuint8x2_t zdn, svuint64_t zm, uint64_t index); + svuint8x4_t svaesemc_lane[_u8_x4] (svuint8x4_t zdn, svuint64_t zm, uint64_t index); + svuint8x2_t svaesdimc_lane[_u8_x2] (svuint8x2_t zdn, svuint64_t zm, uint64_t index); + svuint8x4_t svaesdimc_lane[_u8_x4] (svuint8x4_t zdn, svuint64_t zm, uint64_t index); ``` #### PMULL, PMLAL From e9d11c2e3c9f3b5cecd57ce2bc625a54c93727e1 Mon Sep 17 00:00:00 2001 From: Marian Lukac Date: Wed, 19 Nov 2025 11:31:55 +0000 Subject: [PATCH 09/12] Fix pmull/pmlal intrinsics --- main/acle.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/main/acle.md b/main/acle.md index fc3ba3f9..93dfd6a8 100644 --- a/main/acle.md +++ b/main/acle.md @@ -9760,11 +9760,11 @@ Multi-vector 128-bit polynomial multiply long instructions // Variants are also available for: // _s64x2, _f64x2 - svuint64x2_t svpmull_u64x2(svuint64_t zn, svuint64_t zm); - svuint64x2_t svpmull[_n]_u64x2(svuint64_t zn, uint64_t zm); + svuint64x2_t svpmull_pair[_u64_x2](svuint64_t zn, svuint64_t zm); + svuint64x2_t svpmull_pair[_n_u64_x2](svuint64_t zn, uint64_t zm); - svuint64x2_t svpmlal[_u64x2](svuint64x2_t zda, svuint64_t zn, svuint64_t zm); - svuint64x2_t svpmlal[_n_u64x2](svuint64x2_t zda, svuint64_t zn, uint64_t zm); + svuint64x2_t svpmlal_pair[_u64_x2](svuint64x2_t zda, svuint64_t zn, svuint64_t zm); + svuint64x2_t svpmlal_pair[_n_u64_x2](svuint64x2_t zda, svuint64_t zn, uint64_t zm); ``` # SME language extensions and intrinsics From 3fbc4e29e20f4415b2d060ca9230693115b17709 Mon Sep 17 00:00:00 2001 From: Marian Lukac Date: Mon, 1 Dec 2025 12:45:55 +0000 Subject: [PATCH 10/12] remove wrong pmull pmlal variants --- main/acle.md | 2 -- 1 file changed, 2 deletions(-) diff --git a/main/acle.md b/main/acle.md index 93dfd6a8..2f955911 100644 --- a/main/acle.md +++ b/main/acle.md @@ -9758,8 +9758,6 @@ Multi-vector 128-bit polynomial multiply long instructions ``` c // Only if __ARM_FEATURE_SVE_AES2 != 0 - // Variants are also available for: - // _s64x2, _f64x2 svuint64x2_t svpmull_pair[_u64_x2](svuint64_t zn, svuint64_t zm); svuint64x2_t svpmull_pair[_n_u64_x2](svuint64_t zn, uint64_t zm); From f782d8ba713e1ba3c85c4f4fa038fc3fa149d0a3 Mon Sep 17 00:00:00 2001 From: Marian Lukac Date: Mon, 1 Dec 2025 16:05:39 +0000 Subject: [PATCH 11/12] Adjust feat definition --- main/acle.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/main/acle.md b/main/acle.md index 2f955911..a75673a5 100644 --- a/main/acle.md +++ b/main/acle.md @@ -2657,7 +2657,7 @@ be found in [[BA]](#BA). | [`__ARM_FEATURE_SVE2`](#sve2) | SVE version 2 (FEAT_SVE2) | 1 | | [`__ARM_FEATURE_SVE2_AES`](#aes-extension) | SVE2 support for the AES cryptographic extension (FEAT_SVE_AES) | 1 | | [`__ARM_FEATURE_SVE_AES2`](#aes-extension) | SVE support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SVE_AES2) | 1 | -| [`__ARM_FEATURE_SSVE_AES`](#aes-extension) | SVE support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SSVE_AES) | 1 | +| [`__ARM_FEATURE_SSVE_AES`](#aes-extension) | Streaming SVE support for the multi-vector AES cryptographic and 128-bit polynomial multiply long extension (FEAT_SSVE_AES) | 1 | | [`__ARM_FEATURE_SVE2_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | | [`__ARM_FEATURE_SSVE_BITPERM`](#bit-permute-extension) | SVE2 bit permute extension | 1 | | [`__ARM_FEATURE_SSVE_FEXPA`](#streaming-sve-fexpa-extension) | Streaming SVE FEXPA extension | 1 | From 2adfa867d4e04d9dcdebbb84220ec3734cccfe61 Mon Sep 17 00:00:00 2001 From: Marian Lukac Date: Mon, 1 Dec 2025 16:35:42 +0000 Subject: [PATCH 12/12] added full stops --- main/acle.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/main/acle.md b/main/acle.md index a75673a5..bce18741 100644 --- a/main/acle.md +++ b/main/acle.md @@ -9736,7 +9736,7 @@ extended in the future. #### AESE, AESD, AESEMC, AESDIMC -Multi-vector Advanced Encryption Standard instructions +Multi-vector Advanced Encryption Standard instructions. ```c // Only if __ARM_FEATURE_SVE_AES2 != 0 @@ -9753,7 +9753,7 @@ Multi-vector Advanced Encryption Standard instructions #### PMULL, PMLAL -Multi-vector 128-bit polynomial multiply long instructions +Multi-vector 128-bit polynomial multiply long instructions. ``` c // Only if __ARM_FEATURE_SVE_AES2 != 0