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<li>Working in a team of two to implement a functional 32-bit RISC-V core on a Nexys A7 FPGA with AXI and JTAG interfaces for communication and debugging.</li>
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<h3className="font-bold text-lg">Sparse Matrix Multiplication Optimization in C</h3>
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<spanclassName="text-sm flex-shrink-0">Feb 2025 – May 2025</span>
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<spanclassName="text-sm flex-shrink-0">Feb – May 2025</span>
<li>Investigated low-level sparse matrix multiplication design by implementing custom COO and CRS format matrix structures, randomized generation functions, and both serial &multithreadedmultiplicationfunctions.</li>
<li>Developed and manufactured a bike theft detection device prototype utilizing a Raspberry Pi, IMU, GPS data, cellular connectivity, and embedded camera.</li>
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