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<li>Facilitated learning in four undergraduate engineering courses (80+ students) by aiding students in completing coursework including lab work, homework, and exam preparation.</li>
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<li>Assisted students during lab sessions in modeling chip components and architecture with Verilog on FPGAs; labs ranged from creating simple muxes to multistage CPU pipelines with forwarding, hazard detection, etc.</li>
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<li>Aided students in completing coursework including lab work, homework, and exam preparation.</li>
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<li>Assisted students during computer architecture labs utilizing MIPS assembly, Verilog, and Vivado; labs ranged from writing MIPS assembly to building multistage CPU pipelines with forwarding, hazard detection, etc.</li>
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<li>Developed grading criteria and provided detailed feedback on homework, labs, and exams in collaboration with professors.</li>
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</ul>
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@@ -84,6 +97,36 @@ const CV = () => {
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{/* BU TA Role - Removed borders/padding/shadows */}
<spanclassName="text-sm flex-shrink-0">Jan 2024 – May 2024</span>
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</div>
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{/* Changed text-green to inherit black */}
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<pclassName="text-md">Boston University Dept. of Electrical and Computer Engineering | Boston, MA</p>
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<ulclassName="list-disc ml-5 space-y-1 text-sm">
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<li>Aided students in completing coursework including lab work, homework, and exam preparation.</li>
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<li>Assisted students during lab sessions in modeling chip components with Verilog on FPGAs; labs ranged from creating simple muxes to creating custom games for an Artix A7 FPGA.</li>
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<li>Developed grading criteria and provided detailed feedback on homework, labs, and exams in collaboration with professors.</li>
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</ul>
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</div>
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{/* BU TA Role - Removed borders/padding/shadows */}
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