From bfe57ea6777673d08cb4ac92894e916eeec46342 Mon Sep 17 00:00:00 2001 From: Prakriti Gupta Date: Mon, 9 Mar 2026 13:17:44 -0700 Subject: [PATCH] Add KPF wdl source files --- src/kpf/kpf.cds | 42 ++ src/kpf/kpf.conf | 22 + src/kpf/kpf.def | 94 +++++ src/kpf/kpf.mod | 107 +++++ src/kpf/kpf.modes | 4 + src/kpf/kpf.seq | 188 +++++++++ src/kpf/kpf.signals | 121 ++++++ src/kpf/kpf.system | 41 ++ src/kpf/kpf.waveform | 938 +++++++++++++++++++++++++++++++++++++++++ src/kpf/kpfReadPixel.h | 36 ++ 10 files changed, 1593 insertions(+) create mode 100644 src/kpf/kpf.cds create mode 100644 src/kpf/kpf.conf create mode 100644 src/kpf/kpf.def create mode 100644 src/kpf/kpf.mod create mode 100644 src/kpf/kpf.modes create mode 100644 src/kpf/kpf.seq create mode 100644 src/kpf/kpf.signals create mode 100644 src/kpf/kpf.system create mode 100644 src/kpf/kpf.waveform create mode 100644 src/kpf/kpfReadPixel.h diff --git a/src/kpf/kpf.cds b/src/kpf/kpf.cds new file mode 100644 index 0000000..6a1ff22 --- /dev/null +++ b/src/kpf/kpf.cds @@ -0,0 +1,42 @@ +/* -*- C -*- */ +/** --------------------------------------------------------------------------- + * @file kpf.cds + * @brief CDS/Deinterlace parameters for KPF instrument + */ + +BIGBUF=_ARCHON_FRAMEBUFS +FRAMEMODE=_ARCHON_FRAMEMODE +LINECOUNT=_LINES_PER_TAP /* _CDS_LINES_PER_TAP */ +PIXELCOUNT=_PIXELS_PER_TAP /* _CDS_PIXELS_PER_TAP */ +RAWENABLE=_RAW_ENABLE +RAWENDLINE=_RAW_ENDLINE +RAWSAMPLES=_RAW_SAMPLES +RAWSEL=_RAW_SELECT +RAWSTARTLINE=_RAW_STARTLINE +RAWSTARTPIXEL=_RAW_STARTPIXEL +SAMPLEMODE=_ARCHON_SAMPLE_MODE +SHP1=_FIRST_RESET_SAMPLE +SHP2=_LAST_RESET_SAMPLE +SHD1=_FIRST_VIDEO_SAMPLE +SHD2=_LAST_VIDEO_SAMPLE +TAPLINE0="AD1L,1,100" +TAPLINE1="AD2R,1,100" +TAPLINE2="AD3L,1,100" +TAPLINE3="AD4R,1,100" +TAPLINE4="" +TAPLINE5="" +TAPLINE6="" +TAPLINE7="" +TAPLINE8="" +TAPLINE9="" +TAPLINE10="" +TAPLINE11="" +TAPLINE12="" +TAPLINE13="" +TAPLINE14="" +TAPLINE15="" +TAPLINES=4 +TRIGOUTFORCE=0 +TRIGOUTINVERT=0 +TRIGOUTLEVEL=0 +TRIGOUTPOWER=1 diff --git a/src/kpf/kpf.conf b/src/kpf/kpf.conf new file mode 100644 index 0000000..57d70c4 --- /dev/null +++ b/src/kpf/kpf.conf @@ -0,0 +1,22 @@ +/** --------------------------------------------------------------------------- + * @file kpf.conf + * @brief WDL configuration file for KPF project + * @author Stephen Kaye + * @date 2019-04-19 (created) + * @modified + * + * This file needs to identify the following four files: + * WAVEFORM_FILE = + * SYSTEM_FILE = + * SIGNAL_FILE = + * SEQUENCE_FILE = + * + */ + +INCLUDE_FILE = "kpf.def" /* #defines and usage are self contained */ +CDS_FILE = "kpf.cds" /* uses #defines from .def file */ +SIGNAL_FILE = "kpf.signals" /* #defines and usage are self contained */ +WAVEFORM_FILE = "kpf.waveform" /* uses #defines from .def and .signals */ +SEQUENCE_FILE = "kpf.seq" /* uses #defines from .def and .waveform */ +MODULE_FILE = "kpf.mod" /* #defines and usage are self contained */ +MODE_FILE = "kpf.modes" \ No newline at end of file diff --git a/src/kpf/kpf.def b/src/kpf/kpf.def new file mode 100644 index 0000000..a48940b --- /dev/null +++ b/src/kpf/kpf.def @@ -0,0 +1,94 @@ +/** -*- C -*- --------------------------------------------------------------------------- + * use "#define" to define user macros used within the Archon files, + * i.e. within the .script, .states, .cds, or .modules files + * Do not edit or remove the following line. + */ + +/** --------------------------------------------------------------------------- + * Various configuration modes + */ +#define _SER_PATTERN_PIXELS_REAL 2 /* Num real pixels to clock */ +#define _SER_PATTERN_PIXELS_NOP 2 /* Num dummy pixels */ + +#define _SHDEL 470 /* miliseconds to delay before readout to allow shutter to close */ /* Add to 30 ms to turn the amps back on so we have a total delay time of 500 ms for shutter close */ + +/** --------------------------------------------------------------------------- + * CDS-Deinterlace options + */ +#define _SKIP_LINES 0 /*0*/ +#define _SERIALPRESCAN 4 +#define _SERIALOVERSCAN 30 /* Use overscan for intial tests */ +#define _PARALLELOVERSCAN 50 /* Use overscan for initial tests */ +#defeval _IMAGEROWS #eval 4080/2 /* Value from CCD data sheet (quadrant) */ +#defeval _IMAGECOLS #eval 4080/2 /* Value from CCD data sheet (quadrant) */ +#defeval _IDLE_LINES #eval _SKIP_LINES + _IMAGEROWS + +/* Are these lines for raw data? Keep, but comment out */ +/*#define _RAW_LINES 2 */ +/*#defeval _CDS_LINES_PER_TAP 2 *//*#eval _IMAGEROWS + _PARALLELOVERSCAN - _SKIP_LINES*/ +/*#defeval _CDS_PIXELS_PER_TAP 2 *//*#eval _IMAGECOLS + _SERIALPRESCAN + _SERIALOVERSCAN*/ /*3272*/ /*3072*/ + +#defeval _LINES_PER_TAP #eval _IMAGEROWS + _PARALLELOVERSCAN - _SKIP_LINES +#defeval _PIXELS_PER_TAP #eval _IMAGECOLS + _SERIALPRESCAN + _SERIALOVERSCAN /*3272*/ /*3072*/ + +/* This is for concurrent clocking, but need to divide by 3 since only 3 parallel phases */ +#defeval _PIXBYTHREE #eval (_IMAGECOLS + _SERIALPRESCAN + _SERIALOVERSCAN)/3 +#defeval NumReads #eval (_SERIALPRESCAN + _IMAGECOLS + _SERIALOVERSCAN)/3 - 1 /* Number of reads in concurrent clocking */ + + +/* The following define the pixel time and the width of some clocks */ +#define PixelT 84 /* Full pixel time */ +#define RGsettleT 17 /* Settling Time for the reset gate */ +#define SWsettleT 16 /* Settling Time for the summing well (charge dump) */ + +#define _FIRST_RESET_SAMPLE #eval RGsettleT /* Start sampling after reset gate settling */ +#define _LAST_RESET_SAMPLE #eval PixelT/2 - 1 /* End sampling at half of the pixel time */ +#define _FIRST_VIDEO_SAMPLE #eval PixelT/2 - 1 + SWsettleT /* Start sampling after summing well settling */ +#define _LAST_VIDEO_SAMPLE #eval PixelT - 1 /* End sampling at the end of the pixel time */ + +#define _ARCHON_SAMPLE_MODE 1 /* 0=16bit, 1=32bit */ +#define _ARCHON_FRAMEMODE 2 /* 0=top, 1=bottom, 2=split */ +#define _ARCHON_FRAMEBUFS 0 /* 0=3x512MB, 1=2x768MB, I.E. "BIGBUF" */ + +/* This is information for raw sampling mode */ +#define _RAW_ENABLE 0 /* 0=no, 1=yes */ +#define _RAW_STARTLINE 0 /* first line of raw data, 0-65535 */ +#define _RAW_ENDLINE 10 /* last line of raw data, 0-65535 */ +#define _RAW_STARTPIXEL 0 +#define _RAW_SAMPLES 25600 +#define _RAW_SELECT 3 /* AD channel for raw data capture, 0-15 */ + +/** --------------------------------------------------------------------------- + * Define clock voltage levels here (units are Volts) + */ +/* ____________________ + * Clock voltage and the biases will be hard coded for the parallel low clock, + * but calculated for the other clocks. This is due to the data sheet advising + * bias and clock levels with respect to parallel clock level low */ + +/* Clocks */ +#define _SER_CLOCK_LOW -5.0 +#define _SER1_CLOCK_LOW -5.0 +#define _SER2_CLOCK_LOW -5.0 +#define _SER3_CLOCK_LOW -5.0 +#define _SER1_CLOCK_HIGH 5.0 +#define _SER2_CLOCK_HIGH 5.0 +#define _SER3_CLOCK_HIGH 5.0 +#define _SER_CLOCK_HIGH 5.0 + +#define _SER_CLOCK_RCV 8.0 /* This is when charge goes from parallel to serial register */ + +#define _PAR_CLOCK_IDLE_LOW -9.0 +#define _PAR_CLOCK_IDLE_HIGH 3.0 + +#define _PAR_CLOCK_EXP_LOW -9.0 /* Default to parallel clock levels for now */ +#define _PAR_CLOCK_EXP_HIGH 3.0 + +#define _PAR_CLOCK_LOW -9.0 +#define _PAR_CLOCK_HIGH 3.0 +#define _PAR_CLOCK_HIGHEST 3.0 + +#define _PAR_LASTGATE_HIGH 3.0 + +#define _TG_CLOCK_LOW -9.0 +#define _TG_CLOCK_HIGH 3.0 diff --git a/src/kpf/kpf.mod b/src/kpf/kpf.mod new file mode 100644 index 0000000..87ee985 --- /dev/null +++ b/src/kpf/kpf.mod @@ -0,0 +1,107 @@ +/** -*- C -*- **/ + +#define Iphi_slew_fast 100 /*100*/ +#define Iphi_slew_slow 10 /*10*/ +#define Rphi_slew_fast 500 /* 500 was too fast */ +#define Rphi_slew_slow 29.508 /*33*/ + +#define TG_slew_fast 500 +#define TG_slew_slow 10 + +#define BIAS_slew_fast 100 +#define BIAS_slew_slow 50 + +#define DG_slew_fast 100 +#define DG_slew_slow 50 + +#define OutputDrain 30.5 + +#define OutputGate 2.5 + +#define ResetDrain 18 + +#define ResetGateHi 8 +#define SummingWellHi 5 + + +SLOT 3 lvds { + DIO 1 [0,0]; + DIO 2 [0,0]; + DIO 3 [0,0]; + DIO 4 [0,0]; + DIOPOWER = 0; +} + +SLOT 4 driver { + DRV 1 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 2 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 3 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 4 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 5 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 6 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 7 [BIAS_slew_fast,BIAS_slew_slow,1]; + DRV 8 [BIAS_slew_fast,BIAS_slew_slow,1]; +} + +SLOT 5 ad { + CLAMP 1 = 1.5; + CLAMP 2 = 1.5; + CLAMP 3 = 1.5; + CLAMP 4 = 1.5; + PREAMPGAIN = low; +} + +SLOT 9 hvbias { + HVLC 1 [15,0]; /* Reset Drain a */ + HVLC 2 [15,0]; /* Reset Drain b */ + HVLC 3 [15,0]; /* Reset Drain c */ + HVLC 4 [15,0]; /* Reset Drain d */ + HVLC 5 [0,0]; /* Spare */ + HVLC 6 [0,0]; /* Spare */ + HVLC 7 [0,0]; /* Spare */ + HVLC 8 [0,0]; /* Spare */ + HVLC 9 [0,0]; /* Spare */ + HVLC 10 [0,0]; /* Spare */ + HVLC 11 [ResetGateHi,0]; /* Reset Gate High Rail */ + HVLC 12 [SummingWellHi,0]; /* Summing Well High Rail */ + HVLC 13 [0,0]; /* Spare */ + HVLC 14 [0,0]; /* Spare */ + HVLC 15 [0,0]; /* Spare */ + HVLC 16 [0,0]; /* Spare */ + HVLC 17 [0,0]; /* Spare */ + HVLC 18 [0,0]; /* Spare */ + HVLC 19 [0,0]; /* Spare */ + HVLC 20 [0,0]; /* Spare */ + HVLC 21 [0,0]; /* Spare */ + HVLC 22 [0,0]; /* Spare */ + HVLC 23 [0,0]; /* Spare */ + HVLC 24 [0,0]; /* Dump Drain All Quads */ + HVHC 1 [0,10,0,1]; /* Spare */ + HVHC 2 [0,10,0,1]; /* Spare */ + HVHC 3 [24,100,0,1]; /* Output Drain Top Left (a) */ + HVHC 4 [24,100,0,1]; /* Output Drain Top Right (b) */ + HVHC 5 [24,100,0,1]; /* Output Drain Bottom Right (c) */ + HVHC 6 [24,100,0,1]; /* Output Drain Bottom Left (d) */ +} + +SLOT 10 driver { + DRV 1 [Iphi_slew_fast,Iphi_slew_slow,1]; + DRV 2 [Iphi_slew_fast,Iphi_slew_slow,1]; + DRV 3 [Iphi_slew_fast,Iphi_slew_slow,1]; + DRV 4 [Iphi_slew_fast,Iphi_slew_slow,1]; + DRV 5 [Iphi_slew_fast,Iphi_slew_slow,1]; + DRV 6 [Iphi_slew_fast,Iphi_slew_slow,1]; + DRV 7 [TG_slew_fast,TG_slew_slow,1]; + DRV 8 [TG_slew_fast,TG_slew_slow,1]; +} + +SLOT 11 driver { + DRV 1 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 2 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 3 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 4 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 5 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 6 [Rphi_slew_fast,Rphi_slew_slow,1]; + DRV 7 [DG_slew_fast,DG_slew_slow,1]; + DRV 8 [BIAS_slew_fast,BIAS_slew_slow,1]; +} diff --git a/src/kpf/kpf.modes b/src/kpf/kpf.modes new file mode 100644 index 0000000..f4c3038 --- /dev/null +++ b/src/kpf/kpf.modes @@ -0,0 +1,4 @@ +[MODE_DEFAULT] +ARCH:NUM_CCDS=1 +ARCH:AMPS_PER_CCD_HORI=2 +ARCH:AMPS_PER_CCD_VERT=2 diff --git a/src/kpf/kpf.seq b/src/kpf/kpf.seq new file mode 100644 index 0000000..d22fbb6 --- /dev/null +++ b/src/kpf/kpf.seq @@ -0,0 +1,188 @@ +/* -*- C -*- */ +/** --------------------------------------------------------------------------- + * @file ztf_science.seq + * @brief sequence file for ZTF + * @author Stephen Kaye + * @date 2016-04-07 + * @modified 2016-04-07 SK + * + */ + +/** --------------------------------------------------------------------------- + * parameter definitions + * syntax: param paramname=value +*/ + +param exptime=0 +param Expose=0 +param Abort=0 +param ShutterEnable=1 +param shutdelay=_SHDEL +/* These are for vicd to know the size of the image. vicd will not be used */ +param SerialPrescan=_SERIALPRESCAN +param SerialOverscan=_SERIALOVERSCAN +param ParallelOverscan=_PARALLELOVERSCAN +param ImageCols=_IMAGECOLS +param ImageRows=_IMAGEROWS +/* The above are use by vicd. vicd will not be used */ +param SplitLines=_LINES_PER_TAP +param Lines=_LINES_PER_TAP +param Pixels=_PIXELS_PER_TAP +param PxByFour=_PIXBYFOUR +param IdleLines=_IDLE_LINES + +/** --------------------------------------------------------------------------- + * @fn MAIN + * @brief the main loop. MAIN is implicitly an infinite loop. + * + */ +SEQUENCE Start { + wCloseShutter(); + SerialReceiving(); /* Put serials at nominal voltages */ + SynchedLineTransfer(); /* Put parallels at nominal voltages */ + + /* Start with a reset of the sense node and clamping to that level */ + wReset(); + Wait1us(); + wUnsetReset(); + ADClamp(); + Wait1us(); + ADClamp_(); + + /*wDumpGateOn();*/ + /*wParallelInversion();*/ + /*wDumpGateOff();*/ /* suppresses the waffle pattern */ + Idling(IdleLines); /* clears the residual badness */ +} + +SEQUENCE WaitForExpose { + Abort--; + if Expose DoExpose(); + Idling(); + /*wCloseShutter();*/ /* For ramped illumination */ + /*DoScienceReadout();*/ /***/ + /*return;*/ /***/ + GOTO WaitForExpose(); +} + +/** --------------------------------------------------------------------------- + * @fn Idling + * @brief Idle sequence to push one parallel line and read the full serial register + */ +SEQUENCE Idling { + ReadLineConcurrently(); + + /*SynchedLineTransfer();*/ /* Idle... to invert parallel shifting */ + /*TPixel(Pixels);*/ + /* Now go to nominal clock levels for the serial */ + SerialReceiving(); + + /* Do a reset sequence */ + wReset(); + Wait1us(); + wUnsetReset(); + ADClamp(); + Wait1us(); + ADClamp_(); + + return; +} + +/** --------------------------------------------------------------------------- + * @fn DoExpose + * @brief start an exposure + * + */ +SEQUENCE DoExpose { + Expose--; + SetParallelExpose(); + if ShutterEnable OpenShutter(); // don't even try to open shutter unless enabled + if exptime MilliSec(exptime); + wCloseShutter(); + if exptime DoShutterDelay(shutdelay); + DoScienceReadout(); + return; +} + +SEQUENCE OpenShutter { + if exptime wOpenShutter(); // only fire open shutter waveform for non-zero exposure times + return; +} + +SEQUENCE MilliSec { + Wait1ms(); /* This is a placeholder 1ms routine - Need to fix up */ + if Abort GOTO DoAbort(); /* This is the test for an abort */ + return; +} + +SEQUENCE DoAbort { + Abort--; + GOTO WaitForExpose(); +} + +SEQUENCE DoShutterDelay { + Wait1ms(); + return; +} + +SEQUENCE DoScienceReadout { + SetParallelTransfer(); /* 0.01 us*/ + SetParallelTransferConcurrent(); /* Move Integrated charge to AB3 and CD4 here */ + TPixel(Pixels); /* initial serial sweepout */ + SerialReceiving(); /* 0.21 us*/ + +/* Do a clamp and reset since things were sitting during exposure and waiting for readout */ +/* This is an attempt to make the first line the same as other lines */ + wReset(); + Wait1us(); + wUnsetReset(); /* Do we move this until the end of the BLC and ADC Clamps? */ + ADClamp(); + Wait1us(); + ADClamp_(); + + wFrame(); /* 0.01 us*/ + ScienceRead(SplitLines); /*3257.65 us*/ + SerialReceiving(); /* Put serial clocks in ready for charge state after readout */ + return; /***/ +} + + +SEQUENCE ScienceRead { + /* Commented out due to concurrent clocking */ + /*SynchedLineTransfer();*/ /* Parallel shift */ + wLine(); + /* Replaces SynchedLineTransfer for concurrent clocking */ + ReadLineConcurrently(); + + /* The first pixel is a junk pixel and then we get the dark pixels, not sure why */ + /* To avoid the junk pixel try putting in one PixelShift before reading pixels */ + /* PixelShift is the same as TPixel except no control signals, therefore, no conversion */ + /*InitialClock2Low(); + TPixel(Pixels);*/ + + SerialReceiving(); /* This puts phase 1 and 2 high and reset gate high */ + /* Need a final reset so that we clamp on a reset level and not + on a charge signal level */ + wReset(); + Wait1us(); + wUnsetReset(); /* Do we move this until the end of the BLC and ADC Clamps? */ + ADClamp(); + Wait1us(); + ADClamp_(); + + return; +} + +SEQUENCE ReadLineConcurrently { + LoadSerialRegister(); + InitialClock2Low(); /* After receiving charge get it under 1 phase */ + P23to34(); /* Charge under AB3,AB4 CD4,CD1 */ + TPixel(NumReads); + P34to41(); /* Charge under AB4,AB1 CD1,CD2 */ + TPixel(NumReads); + P41to12(); /* Charge under AB1,AB2 CD2,CD3 */ + TPixel(NumReads); + P12to23(); /* Charge under AB2,AB3 CD3,CD4 */ + TPixel(NumReads); + return; +} diff --git a/src/kpf/kpf.signals b/src/kpf/kpf.signals new file mode 100644 index 0000000..17e0649 --- /dev/null +++ b/src/kpf/kpf.signals @@ -0,0 +1,121 @@ +/* -*- C -*- */ +/** --------------------------------------------------------------------------- + * @file wasp.signals + * @brief WaSP signal names and module/channel assignments + * + * syntax: + * + * #define signallabel slot : channel + * + * where signallabel is any ASCII text string to identify the signal name + * slot is the slot number containing the module, + * channel is the channel number on the module + * + * Combinations of signals can also be made by creating a comma-separated + * list enclosed in square brackets as follows: + * + * #define newlabel [ signallabel, signallabel [, signallabel] ] + * + * where newlabel is any ASCII text string to define a new signal + * signallabel is any signal already defined above + * + * any number can be combined in a comma-separated list between square brackets, + * or a single signal can be defined in square brackets to effectively asign + * a different name to the signal + * + */ + +#define SHUTTER 0 : 1 /* INT signal from the backplane - controls the shutter */ +#define FRAME 0 : 2 /* FRAME signal from the backplane */ +#define LINE 0 : 3 /* LINE signal from the backplane */ +#define PIXEL 0 : 4 /* PIXEL signal from the backplane */ + +#define RGClock 3 : 1 /* Reset Gate */ +#define SWClock 3 : 2 /* Summing Well */ +#define LL1 3 : 3 /* Loopback logic 1 */ +#define LL2 3 : 4 /* Loopback logic 2 */ +#define LL3 3 : 9 /* Loopback logic 3 */ +#define LL4 3 : 10 /* Loopback logic 4 */ +#define LL5 3 : 11 /* Loopback logic 5 */ + +#define S3a 4 : 1 /* Serial phase 3 Px (Top left) */ +#define S2a 4 : 2 /* Serial phase 2 Px (Top left) */ +#define S1a 4 : 3 /* Serial phase 1 Px (Top left) */ +#define S1b 4 : 4 /* Serial phase 1 Px (Top right) */ +#define S2b 4 : 5 /* Serial phase 2 Px (Top right) */ +#define S3b 4 : 6 /* Serial phase 3 Px (Top right) */ +#define OTG 4 : 7 /* Output Transfer Gate - DC Voltage (all quads) */ +#define SW_LOW 4 : 8 /* Summing Well Low rail voltage - DC Voltage */ + +#define AD5 5 : 1 /* AD board in slot 5. Access to the clamp */ + +/* These are the biases which can now be commanded in states */ +#define RDa 9 : 1 /* Reset Drain Px (Top left) */ +#define RDb 9 : 2 /* Reset Drain Px (Top right) */ +#define RDc 9 : 3 /* Reset Drain Py (Bottom right) */ +#define RDd 9 : 4 /* Reset Drain Py (Bottom left) */ +#define SC 9 : 6 /* Scupper Voltage - All Quads */ +#define RG_HIGH 9 : 11 /* Reset Gate High Rail - All Quads */ +#define SW_HIGH 9 : 12 /* Summing Well High Rail - All Quads */ +#define DD 9 : 25 /* Dump Drain - All Quads */ +#define ODa 9 : 27 /* Output Drain Px (Top left) */ +#define ODb 9 : 28 /* Output Drain Px (Top right) */ +#define ODc 9 : 29 /* Output Drain Py (Bottom right) */ +#define ODd 9 : 30 /* Output Drain Py (Bottom left) */ + + +#define A1x 10 : 1 /* Parallel Phase 1 Px (Top) */ +#define A2x 10 : 2 /* Parallel Phase 2 Px (Top) */ +#define A3x 10 : 3 /* Parallel Phase 3 Px (Top) */ +#define A1y 10 : 4 /* Parallel Phase 1 Py (Bottom) */ +#define A2y 10 : 5 /* Parallel Phase 2 Py (Bottom) */ +#define A3y 10 : 6 /* Parallel Phase 3 Py (Bottom) */ +#define T1 10 : 7 /* Transfer Gate 1 - Px and Py (Top and Bottom) */ +#define T2 10 : 8 /* Transfer Gate 2 - Px and Py (Top and Bottom) */ + +#define S3c 11 : 1 /* Serial phase 3 Py (Bottom right) */ +#define S2c 11 : 2 /* Serial phase 2 Py (Bottom right) */ +#define S1c 11 : 3 /* Serial phase 1 Py (Bottom right) */ +#define S3d 11 : 4 /* Serial phase 3 Py (Bottom left) */ +#define S2d 11 : 5 /* Serial phase 2 Py (Bottom left) */ +#define S1d 11 : 6 /* Serial phase 1 Py (Bottom left) */ +#define DG 11 : 7 /* Dump Gate - All Quadrants */ +#define RG_LOW 11 : 8 /* Reset Gate low rail - All Quadrants */ + +#define SplitClock1 [S1a,S1b,S1c,S1d] +#define SplitClock2 [S2a,S2b,S2c,S3d] +#define SplitClock3 [S3a,S3b,S3c,S3d] + +#define RightSClock1 [S1a,S1b,S1c,S1d] +#define RightSClock2 [S3a,S2b,S3c,S2d] +#define RightSClock3 [S2a,S3b,S2c,S3d] + +#define LeftSClock1 [S1a,S1b,S1c,S1d] +#define LeftSClock2 [S2a,S3b,S2c,S3d] +#define LeftSClock3 [S3a,S2b,S3c,S2d] + +#define ADCCLAMP [AD5] + +/* Select amplifiers in use here: */ +#define Ampa 1 +#define Ampb 1 +#define Ampc 1 +#define Ampd 1 + +#if ((Ampa || Ampb) && (Ampc || Ampd)) /* Split frame clocking */ +#define P1 [A1x,A1y] +#define P2 [A2x,A2y] +#define P3 [A3x,A3y] +#endif + +#if ((AmpE || AmpF) && !(AmpG || AmpH)) /* Full frame downwards */ +#define P1 [A1x,A1y] +#define P2 [A3x,A2y] +#define P3 [A2x,A3y] +#endif + +#if (!(AmpE || AmpF) && (AmpG || AmpH)) /* Full frame upwards */ +#define P1 [A1x,A1y] +#define P2 [A2x,A3y] +#define P3 [A3x,A2y] +#endif diff --git a/src/kpf/kpf.system b/src/kpf/kpf.system new file mode 100644 index 0000000..0c33866 --- /dev/null +++ b/src/kpf/kpf.system @@ -0,0 +1,41 @@ +[SYSTEM] +BACKPLANE_ID=0000000000000000 +BACKPLANE_REV=0 +BACKPLANE_TYPE=1 +BACKPLANE_VERSION=0.0.0 +MOD3_ID=0000000000000000 +MOD3_REV=0 +MOD3_VERSION=0.0.0 +MOD3_TYPE=10 +MOD4_ID=0000000000000000 +MOD4_REV=0 +MOD4_VERSION=0.0.0 +MOD4_TYPE=1 +MOD5_ID=0000000000000000 +MOD5_REV=0 +MOD5_VERSION=0.0.0 +MOD5_TYPE=2 +MOD6_ID=0000000000000000 +MOD6_REV=0 +MOD6_VERSION=0.0.0 +MOD6_TYPE=2 +MOD7_ID=0000000000000000 +MOD7_REV=0 +MOD7_VERSION=0.0.0 +MOD7_TYPE=2 +MOD8_ID=0000000000000000 +MOD8_REV=0 +MOD8_VERSION=0.0.0 +MOD8_TYPE=2 +MOD9_ID=0000000000000000 +MOD9_REV=0 +MOD9_VERSION=0.0.0 +MOD9_TYPE=4 +MOD10_ID=0000000000000000 +MOD10_REV=0 +MOD10_VERSION=0.0.0 +MOD10_TYPE=1 +MOD11_ID=0000000000000000 +MOD11_REV=0 +MOD11_VERSION=0.0.0 +MOD11_TYPE=1 diff --git a/src/kpf/kpf.waveform b/src/kpf/kpf.waveform new file mode 100644 index 0000000..4ae15b3 --- /dev/null +++ b/src/kpf/kpf.waveform @@ -0,0 +1,938 @@ +/* -*- C -*- */ +/** --------------------------------------------------------------------------- + * @file ztf_science.wav + * @brief ZTF timing file, rules for waveform generation and scripting + * + * syntax (is case sensitive): + * + * WAVEFORM waveformlabel { rules } + * + * where rules (enclosed in curly braces) are as follows: + * + * [time]: [=timelabel] SET signallabel TO level; + * + * time: at least one time label is required, followed by colon + * (if omitted then SET... lines are all at the same time as previous time) + * arithmetic operations are allowed for time + * units are allowed to follow numbers, E.G. ns, us, ms + * ".+" means to add to the previous time + * + * =timelabel is an optional label for this time, which can be used elsewhere + * + * SET signallabel TO level; + * is required and must end with a semi-colon + * signallabel and level can be defined anywhere + * + */ + + +#define clockfreq 100000000 /* 100 MHz master clock frequency in Hz */ +#define sec *(clockfreq) /* clock cycles per second */ +#define ms *(clockfreq/1000) /* clock cycles per millisec */ +#define us *(clockfreq/1000000) /* clock cycles per microsec */ +#define ns *(clockfreq/10000000) /* clock cycles per nanosecond */ +#define clicks *(clockfreq/100000000) /* clock cycles per nanosecond */ + +/* Timing defines */ +/* Generic timing parameters */ +#define TICK #eval 1 clicks /* 10 nsec */ +#define 1ms #eval 99997 clicks /* 999 usec */ +#define 1us #eval 1 us +#define 2us #eval 2 us +#define 20us #eval 20 us +#define 25us #eval 25 us +#define 10ms #eval 10 ms +#define 10us #eval 10 us + +/* Science timing parameters */ +#define TDRT #eval 50 us /* 25 usec */ +#define TOI #eval 50 us /* Science parallel time slice */ + +#define TDX #eval 10 clicks /* 20 nsec */ +#define TWDX #eval 10 clicks /* 400 nsec */ +#define TR1 60 /* Time delay after serial phase 1 100 ns */ +#define TR3 60 /* Time delay after serial phase 3 800 ns */ +#define S2TORESET #eval 20 clicks /* serial 2 phase to reset timing */ + +#define RGDELAY #eval 4 us /* 4 usec */ +#define RGWIDTH #eval 2 us /* 2 usec */ + +#define SC2WIDTH 30 + +/* Transfer gate pulse width */ +#define TD2 #eval 10 us + +/* Smooth pixel clocking */ +#define T_ScienceSmoothPixel 122 /*#eval 1us*/ +#define Rsettle 25 /* reset settling time */ +#define SWsettle 5 /* summing well settling time */ +#define T_ScienceSmoothPixel13 #eval T_ScienceSmoothPixel/3 +#define T_ScienceSmoothPixel23 #eval T_ScienceSmoothPixel/3*2 +#define SW_ScienceSmoothPixel #eval (T_ScienceSmoothPixel + Rsettle - SWsettle)/2 +#define TRST 10 + +/* Science timing fast parameters */ +/* Science timing parameters */ +#define FTDX #eval 10 clicks /* 100 nsec */ +#define FTWDX #eval 10 clicks /* 100 nsec */ +#define FTR1 30 /*Time delay after serial phase 1 [x10ns]*/ /*Charge level length*/ +#define FTR3 30 /* Want to change this to 40 for a longer reset level*/ /*Time delay after serial phase 3 [x10ns]*/ /*Reset level length*/ +#define FS2TORESET #eval 20 clicks /* 200 nsec serial 2 phase to reset timing */ + +#define OVERLAP #eval 10 clicks /* overlap the serial clocks by 100 ns */ +/* Guider timing parameters */ +#define PDELAY #eval 20 us /* 20 usec used by Tim's Leach code */ + /* Use as a first approximation of */ + /* timing */ +#define SDELAY #eval 1 us /* 1 usec used by Tim's Leach Code */ +#define SWDELAY #eval 1.12 us /* 1.12 usec used by Tim's Leach code */ + +/* Fake signal parameters */ +#define HALFPIX #eval 256 clicks /* 500 ns */ + + +/* Logical state defines */ +#define OPEN 1 /* Real shutter opens when low 1 */ +#define CLOSE 0 /* Real shutter closes when high 0 */ +#define High 1 +#define Low 0 + +#define leftClamped 0 /* This is set if the Archon clamp is left clamped */ +#define PhiRHigh 1 /* ZTF pin driver does not invert like the WaSP Pin Driver */ +#define PhiRLow 0 + +#define SWPhiHigh 1 +#define SWPhiLow 0 + +/* Logical state defines */ +#define HI 1 +#define LO 0 + + +WAVEFORM Wait1ms { + 1ms: RETURN; +} + +WAVEFORM Wait1us { + 1us: RETURN; +} + +WAVEFORM Wait25us { + +25us: RETURN; +} + +WAVEFORM SyncParallel { + 0: SET CD3 TO _PAR_CLOCK_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_HIGH, FAST; + SET CD2 TO _PAR_CLOCK_HIGH, FAST; + SET CD1 TO _PAR_CLOCK_LOW, FAST; + .+TDRT: SET CD3 TO _PAR_CLOCK_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_HIGH, FAST; + SET CD2 TO _PAR_CLOCK_LOW, FAST; + SET CD1 TO _PAR_CLOCK_LOW, FAST; +} + +WAVEFORM wParallelInversion { + 0: SET CD1 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET CD2 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET CD3 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET CD4 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET AB1 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET AB2 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET AB3 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET AB4 TO _PAR_CLOCK_IDLE_LOW, FAST; +} + +WAVEFORM wAllSerialLow { + 0: SET SClock1 TO _SER_CLOCK_LOW, FAST; + SET SClock2 TO _SER_CLOCK_LOW, FAST; + SET SClock3 TO _SER_CLOCK_LOW, FAST; +} + +WAVEFORM SerialReceiving { + 0: SET SClock2 TO _SER_CLOCK_RCV, FAST; + SET SClock1 TO _SER_CLOCK_RCV, FAST; + SET SClock3 TO _SER_CLOCK_LOW, FAST; + .+S2TORESET: SET RGClock TO PhiRHigh; +} + +/* The waveform is spread out with no overlapping clocks */ +WAVEFORM OldSerialOutputClocking { + 0: SET SClock2 TO _SER_CLOCK_LOW, FAST; + SET SClock1 TO _SER_CLOCK_HIGH, FAST; + .+S2TORESET: SET RGClock TO PhiRHigh; + .+TWDX: SET SWClock TO SWPhiHigh; + SET SClock3 TO _SER_CLOCK_HIGH; + SET SClock1 TO _SER_CLOCK_LOW; + .+TDX: SET RGClock TO PhiRLow; + .+TICK: SET PIXEL TO High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; + .+TR3: SET SWClock TO SWPhiLow; + SET SClock3 TO _SER_CLOCK_LOW, FAST; + SET SClock2 TO _SER_CLOCK_HIGH, FAST; + .+TR1: SET NOP TO Low; +} + +WAVEFORM SerialOutputClocking { + 0: =resetreset SET RGClock TO PhiRHigh; + SET SClock2 TO _SER_CLOCK_LOW, FAST; + .+TWDX: SET SWClock TO SWPhiHigh; + SET SClock3 TO _SER_CLOCK_HIGH, FAST; + SET SClock1 TO _SER_CLOCK_LOW, FAST; + .+TDX: SET RGClock TO PhiRLow; + .+TICK: SET PIXEL TO High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; + .+TR3: =chargelevel SET SWClock TO SWPhiLow; + SET SClock3 TO _SER_CLOCK_LOW, FAST; + SET SClock2 TO _SER_CLOCK_HIGH, FAST; + .+SC2WIDTH: = dmz SET SClock1 TO _SER_CLOCK_HIGH, FAST; + SET SClock2 TO _SER_CLOCK_LOW, FAST; + chargelevel+TR1: RETURN; +} + + +/* No overlapping clocks */ +WAVEFORM SlowSerialOutputClocking { + 2: SET PIXEL To High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; + .+2us: SET SClock1 TO _SER_CLOCK_HIGH, FAST; + .+2us: SET SClock2 TO _SER_CLOCK_LOW, FAST; + .+2us: SET RGClock TO PhiRHigh; + .+2us: SET SWClock TO SWPhiHigh; + .+2us: SET SClock3 TO _SER_CLOCK_HIGH, FAST; + .+2us: SET SClock1 TO _SER_CLOCK_LOW, FAST; + .+2us: SET RGClock TO PhiRLow; + .+2us: SET SClock2 TO _SER_CLOCK_HIGH, FAST; + .+2us: SET SWClock TO SWPhiLow; + .+2us: SET SClock3 TO _SER_CLOCK_LOW, FAST; + .+2us: SET NOP TO Low; +} + +/* Science timing parameters */ +/*#define FTDX #eval 10 clicks Time between SW high and the Reset gate going low - Let's try to minimize +/*#define FTWDX #eval 10 clicks Separates Reset gate going high and summing well going high - seems this could be simultaneous +/*#define FTR1 40 /*Time delay after serial phase 1 [x10ns]*/ +/*#define FTR3 40 /*Time delay after serial phase 3 [x10ns]*/ +/*#define FS2TORESET #eval 20 clicks /* 200 nsec serial 2 phase to reset timing */ +/**/ + +/* Correct pixel speed */ +/* On Monday move the pixel click to the beginning of the waveform */ +WAVEFORM FastSerialOutputClocking { + 0: SET RGClock TO PhiRHigh; + 20: SET RGClock TO PhiRLow; + FTWDX: SET SWClock TO SWPhiHigh; + SET SClock3 TO _SER3_CLOCK_HIGH, FAST; + SET SClock1 TO _SER1_CLOCK_LOW, FAST; +/* .+FTDX: SET RGClock TO PhiRLow;*/ /* This only needs to be 10 ns */ + .+FTDX+TICK: SET PIXEL TO High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; + .+FTR3: SET SWClock TO SWPhiLow; + SET SClock3 TO _SER3_CLOCK_LOW, FAST; + SET SClock2 TO _SER2_CLOCK_HIGH, FAST; + .+FTR1: SET SClock2 TO _SER2_CLOCK_LOW, FAST; + SET SClock1 TO _SER1_CLOCK_HIGH, FAST; + .+FS2TORESET: RETURN; +} + +WAVEFORM InlineSerialReceiving { + 0: SET RGClock TO PhiRHigh; + .+10: SET RGClock TO PhiRLow; +} + +WAVEFORM SmoothSerialOutputClocking { + 0: SET RGClock TO PhiRHigh; + SET SClock1 TO _SER_CLOCK_LOW, SLOW; + SET SClock3 TO _SER_CLOCK_HIGH, SLOW; + SET SWClock TO SWPhiHigh; + SET PIXEL TO High; +.+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; +.+TRST: SET RGClock TO PhiRLow; +T_ScienceSmoothPixel13: SET SClock2 TO _SER_CLOCK_HIGH, SLOW; + SET SClock3 TO _SER_CLOCK_LOW, SLOW; +SW_ScienceSmoothPixel: SET SWClock TO SWPhiLow; +T_ScienceSmoothPixel23: SET SClock2 TO _SER_CLOCK_LOW, SLOW; + SET SClock1 TO _SER_CLOCK_HIGH, SLOW; +T_ScienceSmoothPixel: RETURN; +} + + +/* Overlapped Phases */ +WAVEFORM OverlapSerialOutputClocking { + 0: SET SClock1 TO _SER_CLOCK_HIGH, FAST; + .+OVERLAP: SET SClock2 TO _SER_CLOCK_LOW, FAST; + .+FS2TORESET: SET RGClock TO PhiRHigh; + .+FTWDX: SET SWClock TO SWPhiHigh; + SET SClock3 TO _SER_CLOCK_HIGH, FAST; + .+OVERLAP: SET SClock1 TO _SER_CLOCK_LOW, FAST; + .+FTDX: SET RGClock TO PhiRLow; + .+TICK: SET PIXEL TO High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; + .+FTR3: SET SClock2 TO _SER_CLOCK_HIGH, FAST; + .+OVERLAP: SET SWClock TO SWPhiLow; + SET SClock3 TO _SER_CLOCK_LOW, FAST; + .+FTR1: RETURN; +} + + +/* Slowed pixel */ +WAVEFORM SerialOutputClocking { + 0: SET SClock2 TO _SER_CLOCK_LOW, FAST; + SET SClock1 TO _SER_CLOCK_HIGH, FAST; + .+S2TORESET: SET RGClock TO PhiRHigh; + .+TWDX: SET SWClock TO SWPhiHigh; + SET SClock3 TO _SER_CLOCK_HIGH, FAST; + SET SClock1 TO _SER_CLOCK_LOW, FAST; + .+TDX: SET RGClock TO PhiRLow; + .+TICK: SET PIXEL TO High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; + .+TR3: SET SWClock TO SWPhiLow; + SET SClock3 TO _SER_CLOCK_LOW, FAST; + SET SClock2 TO _SER_CLOCK_HIGH, FAST; + .+TR1: RETURN; +} + + +WAVEFORM DummySerialOutputClocking { + 0: SET NOP TO High; + .+FS2TORESET: SET NOP TO High; + .+FTWDX: SET NOP TO High; + .+FTDX: SET NOP TO High; + .+TICK: SET PIXEL TO High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; + .+FTR3: SET NOP TO High; + .+FTR1: RETURN; +} + +/* No overlapping clocks */ +/*WAVEFORM RawPixel { +/* 2: SET PIXEL To High; +/* .+TICK: SET PIXEL TO Low; +/* SET FRAME TO Low; +/* SET LINE TO Low; +/* .+2us: SET SClock1 TO _SER_CLOCK_HIGH, FAST; +/* .+2us: SET SClock2 TO _SER_CLOCK_LOW, FAST; +/* .+2us: SET RGClock TO PhiRHigh; +/* .+2us: SET SWClock TO SWPhiHigh; +/* .+2us: SET SClock3 TO _SER_CLOCK_HIGH, FAST; +/* .+2us: SET SClock1 TO _SER_CLOCK_LOW, FAST; +/* .+2us: SET RGClock TO PhiRLow; +/* .+2us: SET SClock2 TO _SER_CLOCK_HIGH, FAST; +/* .+2us: SET SWClock TO SWPhiLow; +/* .+2us: SET SClock3 TO _SER_CLOCK_LOW, FAST; +/* .+2us: SET NOP TO Low; +/*} +/**/ + +/*WAVEFORM RawPixel { +/* 0: SET NOP TO High; +/* /* .+OVERLAP: SET NOP TO High;*/ +/* .+FS2TORESET: SET NOP TO High; +/* .+FTWDX: SET NOP TO High; +/* .+FTDX: SET NOP TO High; +/* .+TICK: SET PIXEL TO High; +/* .+TICK: SET PIXEL TO Low; +/* SET FRAME TO Low; +/* SET LINE TO Low; +/* .+FTR3: SET NOP TO High; +/* /* .+OVERLAP: SET NOP TO High;*/ +/* .+FTR1: RETURN; +/*} +/**/ + +WAVEFORM RawPixel { + PixelT: RETURN; +} + + +WAVEFORM RightSerialOutputClocking { + 0: SET RightSClock2 TO _SER_CLOCK_LOW, FAST; + SET RightSClock1 TO _SER_CLOCK_HIGH, FAST; + .+FS2TORESET: SET RGClock TO PhiRHigh; + .+FTWDX: SET SWClock TO SWPhiHigh; + SET RightSClock3 TO _SER_CLOCK_HIGH, FAST; + SET RightSClock1 TO _SER_CLOCK_LOW, FAST; + .+FTDX: SET RGClock TO PhiRLow; + .+TICK: SET PIXEL TO High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; + .+FTR3: SET SWClock TO SWPhiLow; + SET RightSClock3 TO _SER_CLOCK_LOW, FAST; + SET RightSClock2 TO _SER_CLOCK_HIGH, FAST; + .+FTR1: SET NOP TO Low; +} + +WAVEFORM wReset { + 0: SET RGClock TO PhiRHigh; +} + +WAVEFORM wUnsetReset { + 0: SET RGClock TO PhiRLow; +} + +WAVEFORM wSumWell { + 0: SET SumW TO SumWHigh; +} + +WAVEFORM wUnsetSumWell { + 0: SET SumW TO SumWLow; +} + + +WAVEFORM LeftSerialOutputClocking { + 0: SET LeftSClock2 TO _SER_CLOCK_LOW, FAST; + SET LeftSClock1 TO _SER_CLOCK_HIGH, FAST; + .+FS2TORESET: SET RGClock TO PhiRHigh; + .+FTWDX: SET SWClock TO SWPhiHigh; + SET LeftSClock3 TO _SER_CLOCK_HIGH, FAST; + SET LeftSClock1 TO _SER_CLOCK_LOW, FAST; + .+FTDX: SET RGClock TO PhiRLow; + .+TICK: SET PIXEL TO High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; + .+FTR3: SET SWClock TO SWPhiLow; + SET LeftSClock3 TO _SER_CLOCK_LOW, FAST; + SET LeftSClock2 TO _SER_CLOCK_HIGH, FAST; + .+FTR1: SET NOP TO Low; +} + + +WAVEFORM DoLineTransfer { + 0: SET CD3 TO _PAR_CLOCK_HIGH, FAST; + SET AB4 TO _PAR_CLOCK_LOW, FAST; + SET CD4 TO _PAR_CLOCK_HIGH, FAST; + SET AB3 TO _PAR_CLOCK_HIGH, FAST; + SET CD2 TO _PAR_CLOCK_LOW, FAST; + SET AB1 TO _PAR_CLOCK_LOW, FAST; + SET CD1 TO _PAR_CLOCK_LOW, FAST; + SET AB2 TO _PAR_CLOCK_HIGH, FAST; + .+TOI: SET AB4 TO _PAR_CLOCK_HIGH, FAST; + SET CD1 TO _PAR_CLOCK_HIGH, FAST; + SET TGClock TO _TG_CLOCK_HIGH, FAST; + .+TOI: SET CD3 TO _PAR_CLOCK_LOW, FAST; + SET AB2 TO _PAR_CLOCK_LOW, FAST; + .+TOI: SET CD2 TO _PAR_CLOCK_HIGH, FAST; + SET AB1 TO _PAR_CLOCK_HIGH, FAST; + .+TOI: SET CD4 TO _PAR_CLOCK_LOW, FAST; + SET AB3 TO _PAR_CLOCK_LOW, FAST; + .+TOI: SET CD3 TO _PAR_CLOCK_HIGH, FAST; + SET AB2 TO _PAR_CLOCK_HIGH, FAST; + .+TOI: SET AB4 TO _PAR_CLOCK_LOW, FAST; + SET CD1 TO _PAR_CLOCK_LOW, FAST; + SET TGClock TO _TG_CLOCK_LOW, FAST; + .+TOI: SET AB3 TO _PAR_CLOCK_HIGH, FAST; + .+TOI: SET AB1 TO _PAR_CLOCK_LOW, FAST; +} + + +/* Data sheet Parallel Transfer */ +/*WAVEFORM SynchedLineTransfer { +/* +TDRT: SET CD3 TO _PAR_CLOCK_HIGH, FAST; +/* SET CD4 TO _PAR_CLOCK_HIGH, FAST; +/* SET CD2 TO _PAR_CLOCK_HIGH, FAST; +/* SET CD1 TO _PAR_CLOCK_LOW, FAST; +/* .+TOI: SET CD3 TO _PAR_CLOCK_HIGH, FAST; +/* SET CD4 TO _PAR_CLOCK_HIGH, FAST; +/* SET CD2 TO _PAR_CLOCK_LOW, FAST; +/* SET CD1 TO _PAR_CLOCK_LOW, FAST; +/* .+TOI: SET AB4 TO _PAR_CLOCK_HIGH, FAST; +/* SET CD1 TO _PAR_CLOCK_HIGH, FAST; +/* SET TGClock TO _TG_CLOCK_HIGH, FAST; +/* .+TOI: SET CD3 TO _PAR_CLOCK_LOW, FAST; +/* SET AB2 TO _PAR_CLOCK_LOW, FAST; +/* .+TOI: SET CD2 TO _PAR_CLOCK_HIGH, FAST; +/* SET AB1 TO _PAR_CLOCK_HIGH, FAST; +/* .+TOI: SET CD4 TO _PAR_CLOCK_LOW, FAST; +/* SET AB3 TO _PAR_CLOCK_LOW, FAST; +/* .+TOI: SET CD3 TO _PAR_CLOCK_HIGH, FAST; +/* SET AB2 TO _PAR_CLOCK_HIGH, FAST; +/* .+TOI: SET AB4 TO _PAR_CLOCK_LOW, FAST; +/* SET CD1 TO _PAR_CLOCK_LOW, FAST; +/* SET TGClock TO _TG_CLOCK_LOW, FAST; +/* .+TOI: SET AB3 TO _PAR_CLOCK_HIGH, FAST; +/* .+TOI: SET AB1 TO _PAR_CLOCK_LOW, FAST; +/* .+TOI: RETURN; /* We need a 25 us delay between the end of a parallel and begin serial */ +/*} +/**/ + +/* Tim Parallel Transfer */ +WAVEFORM SynchedLineTransfer { +25us: SET CD1 TO _PAR_CLOCK_LOW, SLOW; + SET CD2 TO _PAR_CLOCK_HIGH, SLOW; + SET CD3 TO _PAR_CLOCK_HIGH, SLOW; + SET CD4 TO _PAR_CLOCK_HIGH, SLOW; + SET AB4 TO _PAR_CLOCK_HIGH, SLOW; + SET AB3 TO _PAR_CLOCK_HIGH, SLOW; + SET AB2 TO _PAR_CLOCK_HIGH, SLOW; + SET AB1 TO _PAR_CLOCK_LOW, SLOW; + SET TGClock TO _TG_CLOCK_LOW, SLOW; +.+TDRT: SET TGClock TO _TG_CLOCK_HIGH, SLOW; +.+TOI: SET CD2 TO _PAR_CLOCK_LOW, SLOW; + SET AB2 TO _PAR_CLOCK_LOW, SLOW; + .+TOI: SET CD1 TO _PAR_CLOCK_HIGH, SLOW; + SET AB1 TO _PAR_CLOCK_HIGH, SLOW; +.+TOI: SET CD3 TO _PAR_CLOCK_LOW, SLOW; + SET AB3 TO _PAR_CLOCK_LOW, SLOW; + .+TOI: SET CD2 TO _PAR_CLOCK_HIGH, SLOW; + SET AB2 TO _PAR_CLOCK_HIGH, SLOW; +.+TOI: SET CD4 TO _PAR_CLOCK_LOW, SLOW; + SET AB4 TO _PAR_CLOCK_LOW, SLOW; + SET TGClock TO _TG_CLOCK_LOW, SLOW; +.+TOI: SET CD3 TO _PAR_CLOCK_HIGH, SLOW; + SET AB3 TO _PAR_CLOCK_HIGH, SLOW; +.+TOI: SET CD1 TO _PAR_CLOCK_LOW, SLOW; + SET AB1 TO _PAR_CLOCK_LOW, SLOW; +.+TOI: SET CD4 TO _PAR_CLOCK_HIGH, SLOW; + SET AB4 TO _PAR_CLOCK_HIGH, SLOW; +.+25us: RETURN; +} +/**/ +/* This gets rid of the last bright line in the image */ +WAVEFORM SynchedLineTransferNEW { +25us: SET CD1 TO _PAR_CLOCK_LOW, SLOW; + SET CD2 TO _PAR_CLOCK_HIGH, SLOW; + SET CD3 TO _PAR_CLOCK_HIGH, SLOW; + SET CD4 TO _PAR_CLOCK_HIGH, SLOW; + SET AB4 TO _PAR_CLOCK_LOW, SLOW; + SET AB3 TO _PAR_CLOCK_HIGH, SLOW; + SET AB2 TO _PAR_CLOCK_HIGH, SLOW; + SET AB1 TO _PAR_CLOCK_HIGH, SLOW; + SET TGClock TO _TG_CLOCK_LOW, SLOW; +.+TDRT: SET TGClock TO _TG_CLOCK_HIGH, SLOW; +.+TOI: SET CD2 TO _PAR_CLOCK_LOW, SLOW; + SET AB1 TO _PAR_CLOCK_LOW, SLOW; + .+TOI: SET CD1 TO _PAR_CLOCK_HIGH, SLOW; + SET AB4 TO _PAR_CLOCK_HIGH, SLOW; +.+TOI: SET CD3 TO _PAR_CLOCK_LOW, SLOW; + SET AB2 TO _PAR_CLOCK_LOW, SLOW; + .+TOI: SET CD2 TO _PAR_CLOCK_HIGH, SLOW; + SET AB1 TO _PAR_CLOCK_HIGH, SLOW; +.+TOI: SET CD4 TO _PAR_CLOCK_LOW, SLOW; + SET AB3 TO _PAR_CLOCK_LOW, SLOW; + SET TGClock TO _TG_CLOCK_LOW, SLOW; +.+TOI: SET CD3 TO _PAR_CLOCK_HIGH, SLOW; + SET AB2 TO _PAR_CLOCK_HIGH, SLOW; +.+TOI: SET CD1 TO _PAR_CLOCK_LOW, SLOW; + SET AB4 TO _PAR_CLOCK_LOW, SLOW; +.+TOI: SET CD4 TO _PAR_CLOCK_HIGH, SLOW; + SET AB3 TO _PAR_CLOCK_HIGH, SLOW; +.+25us: RETURN; +} + + + +WAVEFORM SetParallelExposeUneven { + 0: SET CD1 TO _PAR_CLOCK_EXP_LOW, SLOW; + SET CD2 TO _PAR_CLOCK_EXP_HIGH, SLOW; + SET CD3 TO _PAR_CLOCK_EXP_HIGH, SLOW; + SET CD4 TO _PAR_CLOCK_EXP_HIGH, SLOW; + SET AB4 TO _PAR_CLOCK_EXP_HIGH, SLOW; + SET AB3 TO _PAR_CLOCK_EXP_HIGH, SLOW; + SET AB2 TO _PAR_CLOCK_EXP_HIGH, SLOW; + SET AB1 TO _PAR_CLOCK_EXP_LOW, SLOW; + +} + +WAVEFORM SetParallelTransfer { +0: SET CD1 TO _PAR_CLOCK_LOW, FAST; + SET CD2 TO _PAR_CLOCK_HIGH, FAST; + SET CD3 TO _PAR_CLOCK_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_HIGH, FAST; + SET AB4 TO _PAR_CLOCK_LOW, FAST; + SET AB3 TO _PAR_CLOCK_HIGH, FAST; + SET AB2 TO _PAR_CLOCK_HIGH, FAST; + SET AB1 TO _PAR_CLOCK_HIGH, FAST; +} + +WAVEFORM SetParallelExpose { + 0: SET CD1 TO _PAR_CLOCK_EXP_LOW, FAST; + SET CD2 TO _PAR_CLOCK_EXP_HIGH, FAST; + SET CD3 TO _PAR_CLOCK_EXP_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_EXP_HIGH, FAST; + SET AB4 TO _PAR_CLOCK_EXP_LOW, FAST; + SET AB3 TO _PAR_CLOCK_EXP_HIGH, FAST; + SET AB2 TO _PAR_CLOCK_EXP_HIGH, FAST; + SET AB1 TO _PAR_CLOCK_EXP_HIGH, FAST; + +} + +WAVEFORM SetParallelTransferConcurrent { + 0: SET CD1 TO _PAR_CLOCK_LOW, FAST; + SET CD2 TO _PAR_CLOCK_HIGH, FAST; + SET CD3 TO _PAR_CLOCK_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_HIGH, FAST; + SET AB4 TO _PAR_CLOCK_LOW, FAST; + SET AB3 TO _PAR_CLOCK_HIGH, FAST; + SET AB2 TO _PAR_CLOCK_HIGH, FAST; + SET AB1 TO _PAR_CLOCK_HIGH, FAST; + .+TOI: SET CD2 TO _PAR_CLOCK_LOW, FAST; + SET AB1 TO _PAR_CLOCK_LOW, FAST; /* charge under CD3,CD4 and AB2,AB3 */ +} /* We are now ready for the Load Serial */ + + +/*WAVEFORM InvSynchedLineTransfer { +/*0: SET CD1 TO _INVPAR_CLOCK_LOW, SLOW; +/* SET CD2 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET CD3 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET CD4 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET AB4 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET AB3 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET AB2 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET AB1 TO _INVPAR_CLOCK_LOW, SLOW; +/* SET TGClock TO _TG_CLOCK_LOW, SLOW; +/*.+TDRT: SET TGClock TO _TG_CLOCK_HIGH, SLOW; +/*.+TOI: SET CD2 TO _INVPAR_CLOCK_LOW, SLOW; +/* SET AB2 TO _INVPAR_CLOCK_LOW, SLOW; +/* .+TOI: SET CD1 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET AB1 TO _INVPAR_CLOCK_HIGH, SLOW; +/*.+TOI: SET CD3 TO _INVPAR_CLOCK_LOW, SLOW; +/* SET AB3 TO _INVPAR_CLOCK_LOW, SLOW; +/* .+TOI: SET CD2 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET AB2 TO _INVPAR_CLOCK_HIGH, SLOW; +/*.+TOI: SET CD4 TO _INVPAR_CLOCK_LOW, SLOW; +/* SET AB4 TO _INVPAR_CLOCK_LOW, SLOW; +/* SET TGClock TO _TG_CLOCK_LOW, SLOW; +/*.+TOI: SET CD3 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET AB3 TO _INVPAR_CLOCK_HIGH, SLOW; +/*.+TOI: SET CD1 TO _INVPAR_CLOCK_LOW, SLOW; +/* SET AB1 TO _INVPAR_CLOCK_LOW, SLOW; +/* +/*.+TOI: SET CD4 TO _INVPAR_CLOCK_HIGH, SLOW; +/* SET AB4 TO _INVPAR_CLOCK_HIGH, SLOW; +/*} +*/ + + +WAVEFORM DummyLineTransfer { + 0: SET NOP TO High; + .+TDRT: SET NOP TO High; + .+TOI: SET NOP TO High; + .+TOI: SET NOP TO High; + .+TOI: SET NOP TO High; + .+TOI: SET NOP TO High; + .+TOI: SET NOP TO High; + .+TOI: SET NOP TO High; + .+TOI: SET NOP TO High; + .+TOI: SET NOP TO High; +} + +/* used by nullClocking and .... */ +WAVEFORM IdleSynchedLineTransfer { + 0: SET CD3 TO _PAR_CLOCK_IDLE_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_IDLE_HIGH, FAST; + SET CD2 TO _PAR_CLOCK_IDLE_HIGH, FAST; + SET CD1 TO _PAR_CLOCK_IDLE_LOW, FAST; + .+TDRT: SET CD3 TO _PAR_CLOCK_IDLE_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_IDLE_HIGH, FAST; + SET CD2 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET CD1 TO _PAR_CLOCK_IDLE_LOW, FAST; + .+TOI: SET AB4 TO _PAR_CLOCK_IDLE_HIGH, FAST; + SET CD1 TO _PAR_CLOCK_IDLE_HIGH, FAST; + SET TGClock TO _TG_CLOCK_HIGH, FAST; + .+TOI: SET CD3 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET AB2 TO _PAR_CLOCK_IDLE_LOW, FAST; + .+TOI: SET CD2 TO _PAR_CLOCK_IDLE_HIGH, FAST; + SET AB1 TO _PAR_CLOCK_IDLE_HIGH, FAST; + .+TOI: SET CD4 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET AB3 TO _PAR_CLOCK_IDLE_LOW, FAST; + .+TOI: SET CD3 TO _PAR_CLOCK_IDLE_HIGH, FAST; + SET AB2 TO _PAR_CLOCK_IDLE_HIGH, FAST; + .+TOI: SET AB4 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET CD1 TO _PAR_CLOCK_IDLE_LOW, FAST; + SET TGClock TO _TG_CLOCK_LOW, FAST; + .+TOI: SET AB3 TO _PAR_CLOCK_IDLE_HIGH, FAST; + .+TOI: SET AB1 TO _PAR_CLOCK_IDLE_LOW, FAST; +} + + +/* Up is defined as toward G-H amplifiers */ +WAVEFORM ParallelUp { +0: SET CD3 TO _PAR_CLOCK_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_HIGH, FAST; + SET CD2 TO _PAR_CLOCK_HIGH, FAST; + SET CD1 TO _PAR_CLOCK_LOW, FAST; + .+TDRT: SET CD3 TO _PAR_CLOCK_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_HIGH, FAST; + SET CD2 TO _PAR_CLOCK_LOW, FAST; + SET CD1 TO _PAR_CLOCK_LOW, FAST; + .+TOI: SET AB1 TO _PAR_CLOCK_HIGH, FAST; /* reverse sub AB1 for AB4 */ + SET CD1 TO _PAR_CLOCK_HIGH, FAST; + SET TGClock TO _TG_CLOCK_HIGH, FAST; + .+TOI: SET CD3 TO _PAR_CLOCK_LOW, FAST; + SET AB3 TO _PAR_CLOCK_LOW, FAST; /* reverse sub AB3 for AB2 */ + .+TOI: SET CD2 TO _PAR_CLOCK_HIGH, FAST; + SET AB4 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub AB4 for AB1 */ + .+TOI: SET CD4 TO _PAR_CLOCK_LOW, FAST; + SET AB2 TO _PAR_CLOCK_LOW, FAST; /* reverse sub AB2 for AB3 */ + .+TOI: SET CD3 TO _PAR_CLOCK_HIGH, FAST; + SET AB3 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub AB3 for AB2 */ + .+TOI: SET AB1 TO _PAR_CLOCK_LOW, FAST; /* reverse sub AB1 for AB4 */ + SET CD1 TO _PAR_CLOCK_LOW, FAST; + SET TGClock TO _TG_CLOCK_LOW, FAST; + .+TOI: SET AB2 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub AB2 for AB3 */ + .+TOI: SET AB4 TO _PAR_CLOCK_LOW, FAST; /* reverse sub AB4 for AB1 */ +} + +/* Down is defined as toward E-F amplifiers */ +WAVEFORM ParallelDown { + 0: SET CD2 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub CD2 for CD3 */ + SET CD1 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub CD1 for CD4 */ + SET CD3 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub CD3 for CD2 */ + SET CD4 TO _PAR_CLOCK_LOW, FAST; /* reverse sub CD4 for CD1 */ + .+TDRT: SET CD2 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub CD2 for CD3 */ + SET CD1 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub CD1 for CD4 */ + SET CD3 TO _PAR_CLOCK_LOW, FAST; /* reverse sub CD3 for CD2 */ + SET CD4 TO _PAR_CLOCK_LOW, FAST; /* reverse sub CD4 for CD1 */ + .+TOI: SET AB4 TO _PAR_CLOCK_HIGH, FAST; + SET CD4 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub CD4 for CD1 */ + SET TGClock TO _TG_CLOCK_HIGH, FAST; + .+TOI: SET CD2 TO _PAR_CLOCK_LOW, FAST; /* reverse sub CD2 for CD3 */ + SET AB2 TO _PAR_CLOCK_LOW, FAST; + .+TOI: SET CD3 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub CD3 for CD2 */ + SET AB1 TO _PAR_CLOCK_HIGH, FAST; + .+TOI: SET CD1 TO _PAR_CLOCK_LOW, FAST; /* reverse sub CD1 for CD4 */ + SET AB3 TO _PAR_CLOCK_LOW, FAST; + .+TOI: SET CD2 TO _PAR_CLOCK_HIGH, FAST;/* reverse sub CD2 for CD3 */ + SET AB2 TO _PAR_CLOCK_HIGH, FAST; + .+TOI: SET AB4 TO _PAR_CLOCK_LOW, FAST; + SET CD4 TO _PAR_CLOCK_LOW, FAST; /* reverse sub CD4 for CD1 */ + SET TGClock TO _TG_CLOCK_LOW, FAST; + .+TOI: SET AB3 TO _PAR_CLOCK_HIGH, FAST; + .+TOI: SET AB1 TO _PAR_CLOCK_LOW, FAST; +} + +/* This is where the concurrent clocking waveforms begin */ + +/* This is 7.01 us */ +WAVEFORM fastTGa { + 0: SET TGClock TO _TG_CLOCK_HIGH, FAST; + + SET CD4 TO _PAR_LASTGATE_HIGH, FAST; + SET AB3 TO _PAR_LASTGATE_HIGH, FAST; + + SET AB4 TO _PAR_CLOCK_LOW, SLOW; + SET CD1 TO _PAR_CLOCK_LOW, SLOW; + SET CD2 TO _PAR_CLOCK_LOW, SLOW; + SET CD3 TO _PAR_CLOCK_HIGH, SLOW; + SET AB1 TO _PAR_CLOCK_LOW, SLOW; + SET AB2 TO _PAR_CLOCK_HIGH, SLOW; + .+TD2: SET TGClock TO _TG_CLOCK_LOW, FAST; + SET CD4 TO _PAR_CLOCK_HIGH, FAST; + SET AB3 TO _PAR_CLOCK_HIGH, FAST; + + SET AB4 TO _PAR_CLOCK_HIGH, SLOW; + SET AB2 TO _PAR_CLOCK_LOW, SLOW; + SET CD1 TO _PAR_CLOCK_HIGH, SLOW; + SET CD3 TO _PAR_CLOCK_LOW, SLOW; +} + +/* 0.01 us */ +WAVEFORM step1a { +0: SET AB1 TO _PAR_CLOCK_HIGH, SLOW; + SET AB3 TO _PAR_CLOCK_LOW, SLOW; + SET CD2 TO _PAR_CLOCK_HIGH, SLOW; + SET CD4 TO _PAR_CLOCK_LOW, SLOW; +} + +/* 0.01 us */ +WAVEFORM step2a { +0: SET AB2 TO _PAR_CLOCK_HIGH, SLOW; + SET AB4 TO _PAR_CLOCK_LOW, SLOW; + SET CD3 TO _PAR_CLOCK_HIGH, SLOW; + SET CD1 TO _PAR_CLOCK_LOW, SLOW; +} + +/* 0.01 us */ +WAVEFORM step3a { +0: SET AB3 TO _PAR_CLOCK_HIGH, SLOW; + SET AB1 TO _PAR_CLOCK_LOW, SLOW; + SET CD4 TO _PAR_CLOCK_HIGH, SLOW; + SET CD2 TO _PAR_CLOCK_LOW, SLOW; +} + + +/*****************************************/ +/* Here are the control signal waveforms */ +/*****************************************/ + +WAVEFORM wOpenShutter { + 0: SET SHUTTER TO OPEN; +} +WAVEFORM wCloseShutter { + 0: SET SHUTTER TO CLOSE; +} +WAVEFORM wFrame { + 0: SET FRAME TO High; +} +WAVEFORM wLine { + 0: SET LINE TO High; +} +WAVEFORM wLine_triggered { + 0: SET SHUTTER TO OPEN; + 2000: SET SHUTTER TO CLOSE; + SET LINE TO High; + +} +WAVEFORM wPixel { + 0: SET PIXEL TO High; + .+TICK: SET PIXEL TO Low; + SET FRAME TO Low; + SET LINE TO Low; +} + +WAVEFORM ADClamp { + 0: SET AD5 TO High; +} + +WAVEFORM ADClamp_ { + 0: SET AD5 TO leftClamped; +} + +/* Magic board comm waveforms */ +// TXFRCLK is in signals +/*#define HBIT 25 +/* +/*WAVEFORM LatchEnable { +/*0: set TXFRCLK to LO; +/* set LATCH_ENABLE to HI; +/*.+ HBIT: set TXFRCLK to HI; +/*.+ HBIT: RETURN; +/*} +/* +/*WAVEFORM LatchDisable { +/*0: set TXFRCLK to LO; +/* set LATCH_ENABLE to LO; +/*.+ HBIT: set TXFRCLK to HI; +/*.+ HBIT: RETURN; +/*} +/* +/**//* pull up resistor makes hi signal lo bit and vice versa */ +/* +/*WAVEFORM WriteLoBit { +/*0: set TXFRCLK to LO; +/* set SREGOUT to HI; +/*.+ HBIT: set TXFRCLK to HI; +/*.+ HBIT: set SREGOUT to LO; +/*} +/* +/*WAVEFORM WriteHiBit { +/*0: set TXFRCLK to LO; +/* set SREGOUT to LO; +/*.+ HBIT: set TXFRCLK to HI; +/*.+ HBIT: set SREGOUT to HI; +/*} +/**/ + +/*WAVEFORM wTrigHi { +/* 0: SET TRIG TO HI; +/*} +/*WAVEFORM wTrigLo { +/* 0: SET TRIG TO LO; +/*} +/**/ +WAVEFORM wIdle { +} + +#define TGwidth 10us +#define TGsettle 10us +#define BLCwidth 1000 +#define BLCsettle 1000 +#define ADCclampT 1000 + +/* SW slow slew rate 20 */ +/* P* slow slew rate 0.015 */ +/* S* slow slew rate 34 */ /* This is PixelT/3 */ + +/* Parameterized timing */ +#define RefSamples #eval PixelT/2 /* Half pixel time, when charge is dumped on sense node */ +#define RGT 8 /* Width of the reset gate pulse 200ns */ /* Static */ +#define SWslewT 3 /* Want SW to go high ASAP so minimize this 30ns */ /* Static, but use for SW slow slew */ + + + + +WAVEFORM LoadSerialRegister { + 0: SET TGClock TO _TG_CLOCK_HIGH, SLOW; + TGwidth: SET TGClock TO _TG_CLOCK_LOW, SLOW; + .+TGsettle: RETURN; +} + + + +WAVEFORM TPixel { + #include kpfReadPixel.h +} + + +/* From two phase receiving to hold charge in 1 phase before moving */ +WAVEFORM InitialClock2Low { + 0: SET SClock2 TO _SER_CLOCK_LOW, FAST; + .+1us: RETURN; +} + +/* This is the same as TPixel, but there are no control signals, so the pixel won't get converted */ +WAVEFORM PixelShift { + 0: SET RGClock TO PhiRHigh; + RGT: SET RGClock TO PhiRLow; + RefSamples: =ChgDump SET SWClock TO SWPhiLow; + /*.+SWsettleT:*/ /* Need this in the CDS parameters */ /* Signal samples start here */ + /*.+SigSamples: = PixelT*/ /* Need in CDS parameters .+SWsettleT + PixelT */ + /* SW starts going high again as soon as charge dump has completed * +* so rise time is as long as possible, even extending into next pixel! */ + ChgDump+SWslewT: SET SWClock TO SWPhiHigh; + +/* Coincident Sx edges are spread equally throughout pixel. * +* NB: Sx Slew Time must be set elsewhere to Tpixel/3. * +* Charge is stored on S2 initially */ + + 0: SET SClock3 TO _SER_CLOCK_HIGH, SLOW; + SET SClock1 TO _SER_CLOCK_LOW, SLOW; +.+PixelT/3: SET SClock2 TO _SER_CLOCK_HIGH, SLOW; + SET SClock3 TO _SER_CLOCK_LOW, SLOW; +.+PixelT/3: SET SClock1 TO _SER_CLOCK_HIGH, SLOW; + SET SClock2 TO _SER_CLOCK_LOW, SLOW; +.+PixelT/3: RETURN; +} + +WAVEFORM P23to34 { + 0: SET P4 TO _PAR_CLOCK_HIGH, SLOW; /* AB4, CD1 */ + SET P2 TO _PAR_CLOCK_LOW, SLOW; /* AB2, CD3 */ + #include ReadPixel.h +} + +WAVEFORM P34to41 { + 0: SET P1 TO _PAR_CLOCK_HIGH, SLOW; /* AB1, CD2 */ + SET P3 TO _PAR_CLOCK_LOW, SLOW; /* AB3, CD4 */ + #include ReadPixel.h +} + +WAVEFORM P41to12 { + 0: SET P2 TO _PAR_CLOCK_HIGH, SLOW; /* AB2, CD3 */ + SET P4 TO _PAR_CLOCK_LOW, SLOW; /* AB4, CD1 */ + #include ReadPixel.h +} + +WAVEFORM P12to23 { + 0: SET P3 TO _PAR_CLOCK_HIGH, SLOW; /* AB3, CD4 */ + SET P1 TO _PAR_CLOCK_LOW, SLOW; /* AB1, CD2 */ + #include ReadPixel.h +} + diff --git a/src/kpf/kpfReadPixel.h b/src/kpf/kpfReadPixel.h new file mode 100644 index 0000000..a75eccf --- /dev/null +++ b/src/kpf/kpfReadPixel.h @@ -0,0 +1,36 @@ +/* SW and Sx slew rates are critical. * +* Calculate from amplitude and time automatically * +* CDS sampling should also be tied to constants below. */ + +/* Control signals mark start of pixel for CDS sample timing */ +/* Pixel time = RG + RGsettle + RefSamples +SWsettle + SigSamples */ +/* We have always seen a 6 sample offset */ +/* so starting the pixel counter on 8 doesn't seem that unusual. */ +/* Not understood, though */ + 8: SET PIXEL TO High; + .+1: SET PIXEL TO Low; + SET LINE TO Low; + SET FRAME TO Low; + + 0: SET PhiR TO PhiRHigh; + RGT: SET PhiR TO PhiRLow; + RefSamples: =ChgDump SET SWClock TO SWPhiLow; + /*.+SWsettleT:*/ /* Need this in the CDS parameters */ /* Signal samples start here */ + /*.+SigSamples: = PixelT*/ /* Need in CDS parameters .+SWsettleT + PixelT */ + /* SW starts going high again as soon as charge dump has completed * +* so rise time is as long as possible, even extending into next pixel! */ + ChgDump+SWslewT: SET SWClock TO SWPhiHigh; + +/* Coincident Sx edges are spread equally throughout pixel. * +* NB: Sx Slew Time must be set elsewhere to Tpixel/3. * +* Charge is stored on S2 initially */ + +0: SET SClock3 TO _SER_CLOCK_HIGH, FAST; /*SLOW;*/ + SET SClock1 TO _SER_CLOCK_LOW, SLOW; +.+PixelT/3: SET SClock2 TO _SER_CLOCK_HIGH, FAST; /*SLOW;*/ + SET SClock3 TO _SER_CLOCK_LOW, SLOW; +.+PixelT/3: SET SClock1 TO _SER_CLOCK_HIGH, FAST; /*SLOW;*/ + SET SClock2 TO _SER_CLOCK_LOW, SLOW; +.+PixelT/3: RETURN; + +