Adding a Verilog example using PicoSoC

Signed-off-by: gatecat <gatecat@ds0.me>

Author: gatecat

.github/workflows/main.yaml

@@ -23,10 +23,12 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        design: ['mcu_soc', 'minimal']
+        design: ['mcu_soc', 'minimal', 'picosoc_verilog']
     steps:
       - name: Check out source code
         uses: actions/checkout@v4
+        with: 
+          submodules: true
 
       - uses: actions/setup-python@v4
         with:
@@ -56,10 +58,12 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        design: ['mcu_soc', 'minimal']
+        design: ['mcu_soc', 'minimal', 'picosoc_verilog']
     steps:
       - name: Check out source code
         uses: actions/checkout@v4
+        with: 
+          submodules: true
 
       - name: Set up PDM
         uses: pdm-project/setup-pdm@v4

.gitignore

@@ -19,6 +19,7 @@ __pycache__/
 /build
 /mcu_soc/build
 /minimal/build
+/picosoc_verilog/build
 
 # testbenches
 *.vcd

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "picosoc_verilog/design/picorv32"]
+	path = picosoc_verilog/design/picorv32
+	url = https://github.com/YosysHQ/picorv32

pdm.lock

@@ -0,0 +1,4 @@
+# PicoSoC (Verilog)
+
+This example design shows how an existing Verilog design (picosoc) can be wrapped in a minimal layer of Amaranth and submitted to the ChipFlow platform.
+

picosoc_verilog/README.md

@@ -0,0 +1,43 @@
+[chipflow]
+project_name = "chipflow-examples-picosoc"
+
+[chipflow.top]
+soc = "design.design:MySoC"
+
+[chipflow.steps]
+software = "design.steps.software:MySoftwareStep"
+
+[chipflow.clocks]
+default = 'sys_clk'
+
+[chipflow.resets]
+default = 'sys_rst_n'
+
+[chipflow.silicon]
+process = "ihp_sg13g2"
+package = "pga144"
+
+[chipflow.silicon.pads]
+# System
+sys_clk   = { type = "clock", loc = "114" }
+sys_rst_n = { type = "reset", loc = "115" }
+
+[chipflow.silicon.power]
+dvss0        = { type = "power",  loc =   "1" }
+dvdd0        = { type = "ground", loc =   "9" }
+vss0         = { type = "power",  loc =  "17" }
+vdd0         = { type = "ground", loc =  "25" }
+dvss1        = { type = "power",  loc =  "33" }
+dvdd1        = { type = "ground", loc =  "41" }
+vss1         = { type = "power",  loc =  "49" }
+vdd1         = { type = "ground", loc =  "57" }
+dvss2        = { type = "power",  loc =  "65" }
+dvdd2        = { type = "ground", loc =  "73" }
+vss2         = { type = "power",  loc =  "81" }
+vdd2         = { type = "ground", loc =  "89" }
+dvss3        = { type = "power",  loc =  "97" }
+dvdd3        = { type = "ground", loc = "105" }
+vss3         = { type = "power",  loc = "113" }
+vdd3         = { type = "ground", loc = "121" }
+dvss4        = { type = "power",  loc = "129" }
+dvdd4        = { type = "ground", loc = "137" }

picosoc_verilog/chipflow.toml

@@ -0,0 +1,99 @@
+import os
+
+from chipflow_lib.platforms.sim import SimPlatform
+
+from amaranth import Module, Instance, ClockSignal, ResetSignal
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out, flipped, connect
+
+from chipflow_lib.platforms import InputIOSignature, OutputIOSignature, BidirIOSignature
+
+__all__ = ["MySoC"]
+
+# Define signatures for the top level interface types
+class _QSPISignature(wiring.Signature):
+    def __init__(self):
+        super().__init__({
+            "clk": Out(OutputIOSignature(1)),
+            "csn": Out(OutputIOSignature(1)),
+            "d": Out(BidirIOSignature(4, all_have_oe=True)),
+        })
+
+class _UARTSignature(wiring.Signature):
+    def __init__(self):
+        super().__init__({
+            "tx": Out(OutputIOSignature(1)),
+            "rx": Out(InputIOSignature(1)),
+        })
+
+class _GPIOSignature(wiring.Signature):
+    def __init__(self, pin_count=1):
+        if pin_count > 32:
+            raise ValueError(f"Pin pin_count must be lesser than or equal to 32, not {pin_count}")
+        super().__init__({
+            "gpio": Out(BidirIOSignature(pin_count, all_have_oe=True))
+        })
+
+class MySoC(wiring.Component):
+    def __init__(self):
+        # Top level interfaces
+
+        super().__init__({
+            "flash": Out(_QSPISignature()),
+            "uart_0": Out(_UARTSignature()),
+            "gpio_0": Out(_GPIOSignature(pin_count=8)),
+        })
+
+    def elaborate(self, platform):
+        m = Module()
+
+        base = os.path.dirname(__file__)
+
+        verilog_sources = [
+            f"{base}/picosoc_asic_top.v",
+            f"{base}/picorv32/picosoc/spimemio.v",
+            f"{base}/picorv32/picosoc/simpleuart.v",
+            f"{base}/picorv32/picosoc/picosoc.v",
+            f"{base}/picorv32/picorv32.v",
+        ]
+
+        for verilog_file in verilog_sources:
+            with open(verilog_file, 'r') as f:
+                platform.add_file(verilog_file, f)
+
+        m.submodules.soc = soc = Instance("picosoc_asic_top",
+            # Clock and reset
+            i_clk=ClockSignal(),
+            i_resetn=~ResetSignal(),
+
+            # UART
+            o_ser_tx=self.uart_0.tx.o,
+            i_ser_rx=self.uart_0.rx.i,
+
+            # SPI flash
+            o_flash_csb=self.flash.csn.o,
+            o_flash_clk=self.flash.clk.o,
+
+            o_flash_io0_oe=self.flash.d.oe[0],
+            o_flash_io1_oe=self.flash.d.oe[1],
+            o_flash_io2_oe=self.flash.d.oe[2],
+            o_flash_io3_oe=self.flash.d.oe[3],
+
+            o_flash_io0_do=self.flash.d.o[0],
+            o_flash_io1_do=self.flash.d.o[1],
+            o_flash_io2_do=self.flash.d.o[2],
+            o_flash_io3_do=self.flash.d.o[3],
+
+            i_flash_io0_di=self.flash.d.i[0],
+            i_flash_io1_di=self.flash.d.i[1],
+            i_flash_io2_di=self.flash.d.i[2],
+            i_flash_io3_di=self.flash.d.i[3],
+
+            # LEDs
+            o_leds=self.gpio_0.gpio.o
+        )
+
+        # Hardwire GPIO to output enabled
+        m.d.comb += self.gpio_0.gpio.oe.eq(0xFF)
+
+        return m