Revert "reverted minimal/design/design.py"

This reverts commit d2ce849.

Author: robtaylor

minimal/design/design.py

@@ -15,7 +15,7 @@
 
 from minerva.core import Minerva
 
-from chipflow_lib.platforms import InputIOSignature, OutputIOSignature
+from chipflow_lib.platforms import InputIOSignature, OutputIOSignature, BidirIOSignature, Sky130DriveMode
 # from .ips.pdm import PDMPeripheral
 
 __all__ = ["MySoC"]
@@ -29,6 +29,7 @@ def __init__(self):
             "flash": Out(QSPIFlash.Signature()),
             "uart_0": Out(UARTPeripheral.Signature()),
             "gpio_0": Out(GPIOPeripheral.Signature(pin_count=8)),
+            "gpio_open_drain": Out(GPIOPeripheral.Signature(pin_count=4, sky130_drive_mode=Sky130DriveMode.OPEN_DRAIN_STRONG_UP))
         })
 
         # Memory regions:
@@ -42,7 +43,7 @@ def __init__(self):
         self.csr_base          = 0xb0000000
         self.csr_spiflash_base = 0xb0000000
 
-        self.csr_gpio_base     = 0xb1000000
+        self.csr_gpio_base    = 0xb1000000
         self.csr_uart_base     = 0xb2000000
         self.csr_soc_id_base   = 0xb4000000
 
@@ -98,11 +99,18 @@ def elaborate(self, platform):
         m.submodules.sram = sram
 
         # GPIOs
-        m.submodules.gpio = gpio = GPIOPeripheral(pin_count=8)
-        csr_decoder.add(gpio.bus, name="gpio_0", addr=self.csr_gpio_base - self.csr_base)
+        m.submodules.gpio0 = gpio0 = GPIOPeripheral(pin_count=8)
+        csr_decoder.add(gpio0.bus, name="gpio_0", addr=self.csr_gpio_base - self.csr_base)
         sw.add_periph("gpio", "GPIO_0", self.csr_gpio_base)
 
-        connect(m, flipped(self.gpio_0), gpio.pins)
+        connect(m, flipped(self.gpio_0), gpio0.pins)
+
+        m.submodules.gpio_open_drain = gpio_open_drain = GPIOPeripheral(pin_count=4)
+        csr_decoder.add(gpio_open_drain.bus, name="gpio_open_drain", addr=self.csr_gpio_base + self.periph_offset - self.csr_base)
+        sw.add_periph("gpio", "GPIO_OPEN_DRAIN", self.csr_gpio_base + self.periph_offset)
+
+        connect(m, flipped(self.gpio_open_drain), gpio_open_drain.pins)
+
 
         # UART
         m.submodules.uart = uart = UARTPeripheral(init_divisor=int(25e6//115200), addr_width=5)