Synthesizing with yosys fails (missing OSER10)

[darkstar]

Trying to synthesize the generated Verilog with yosys fails:

$ yosys -p "read_verilog TangNano9k.v; synth_gowin -json TangNano9k.json"
...
2.2.2. Analyzing design hierarchy..
Top module:  \TangNano9k
Used module:     \PatternExample
Used module:         \HVSync
Used module:     \HdmiTx
Used module:         \Oser10Module
Used module:         \Rgb2Tmds
Used module:             \TMDSEncoder
Used module:     \Gowin_rPLL
ERROR: Module `\OSER10' referenced in module `\Oser10Module' in cell `\osr10' is not part of the design.

[Martoni]

Good idea !
I never tested with yosys for synthesis, nether nextpnr for place & route.
I think that serdes buffer are not supported yet under yosys.