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update setup.py
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setup.py

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@@ -17,6 +17,7 @@ def read(filename):
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version=version,
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description='Cycle-Accurate Hardware Simulation Framework on Abstract FPGA Platforms',
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long_description=read('README.md'),
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keywords = 'FPGA,Verilog HDL,Memory System Abstraction,IP-core,AMBA AXI4, FPGA-based Rapid Prototyping, Cycle-Accurate Simulation',
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author='Shinya Takamaeda-Yamazaki',
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author_email='shinya.takamaeda_at_gmail_com',
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license="Apache License 2.0",

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