Revert "drm/amdgpu: Force order between a read and write to the same address"

kentrussell · kentrussell · commit cc2d8659760f · 2023-12-06T11:04:51.000-05:00
This reverts commit fbfca2c. Reason for revert: Deferred to 6.0.1 apparently Change-Id: I7eec212d29a97658a6076080e23c7c6b08b2316a
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -89,10 +89,6 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
 
-static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
-	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
-};
-
 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
 {
 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
@@ -308,10 +304,6 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
 	default:
 		break;
 	}
-	soc15_program_register_sequence(adev,
-					golden_settings_gc_11_0,
-					(const u32)ARRAY_SIZE(golden_settings_gc_11_0));
-
 }
 
 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
@@ -6369,8 +6369,6 @@
 #define regTCP_INVALIDATE_BASE_IDX                                                                      1
 #define regTCP_STATUS                                                                                   0x19a1
 #define regTCP_STATUS_BASE_IDX                                                                          1
-#define regTCP_CNTL                                                                                     0x19a2
-#define regTCP_CNTL_BASE_IDX                                                                            1
 #define regTCP_CNTL2                                                                                    0x19a3
 #define regTCP_CNTL2_BASE_IDX                                                                           1
 #define regTCP_DEBUG_INDEX                                                                              0x19a5

Original file line number	Diff line number	Diff line change
`@@ -89,10 +89,6 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");`
`89`	`89`	`MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");`
`90`	`90`	`MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");`
`91`	`91`
`92`		`-static const struct soc15_reg_golden golden_settings_gc_11_0[] = {`
`93`		`- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)`
`94`		`-};`
`95`		`-`
`96`	`92`	`static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =`
`97`	`93`	`{`
`98`	`94`	`SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),`
`@@ -308,10 +304,6 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)`
`308`	`304`	`default:`
`309`	`305`	`break;`
`310`	`306`	`}`
`311`		`- soc15_program_register_sequence(adev,`
`312`		`- golden_settings_gc_11_0,`
`313`		`- (const u32)ARRAY_SIZE(golden_settings_gc_11_0));`
`314`		`-`
`315`	`307`	`}`
`316`	`308`
`317`	`309`	`static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,`