Using netgen to generate ".sim" files from ".spice" netlists

[mhajimorad]

Hi,

I have created a circuit schematic in xschem using the sky130 PDK, and am trying to use netgen to generate a ".sim" file from xschem's created ".spice file". The intended purpose of the ".sim" file is to allow my students to use IRSIM to verify the switching behavior of transistor-based schematics.

Upon launching netgen, I have tried to open xschem's created ".spice" file using commands like
readnet spice my_netlist.spice

But I obtain messages like call to undefined subcircuit sky130...

And when I try to include the path to the spice models in the ".spice" netlist file itself, netgen gives a large number of errors.

Any tips/suggestions on how I can use netgen to generate ".sim" files from xschem produced sky130 spice netlist files?

Thank you!

[RTimothyEdwards]

Netgen's ability to switch between formats is rather far behind in development at this point. The problem here is that to deal with multiple types of transistors and devices declared as subcircuits, I switched from using "n" and "p" records in the .sim file to using "x" records. However, the "x" records still refer to devices of a specific type like nFETs and pFETs, and have a pin order that is specific to the .sim file. It is not possible to know what kind of a device is represented by "x" without a definition somewhere; that definition is given in the ".prm" files for IRSIM in the PDK. But that file and file format is unknown to netgen. I would need to write an extension to netgen; essentially a separate read routine to read a .prm file and use it to define all of the subcircuit types, and then it would know how to write out the .sim file. I don't think that would be particularly hard to do.

[mhajimorad]

@RTimothyEdwards , thank you for your message!

Do you know by chance whether the extension you had referenced is something that can be done sometime in the near future? I simply ask because it will greatly help with the planning of the curriculum/labs of our introductory VLSI course.

Thank you!

[RTimothyEdwards]

I'm trying to figure out when I can get it done. When do you need it by?

[mhajimorad]

@RTimothyEdwards ,

If possible, in the next month or so? I was hoping to learn the different steps involved in getting xschem/netgen/irsim to communicate with each other by Thanksgiving at the latest, so that I can have students work with these tools after Thanksgiving.

[RTimothyEdwards]

@mhajimorad : It should be available now from the opencircuitdesign.com repository, or tomorrow if you want to get it from github. You will need updates to both netgen and IRSIM.

Once you update, you can convert a SPICE netlist to .sim by running these commands in netgen:

set filenum [readnet prm /usr/local/share/pdk/sky130A/libs.tech/irsim/sky130A_tt_nom_27.prm]
readnet spice mynetlist.spice $filenum
writenet sim mynetlist.spice

This will result in a file mynetlist.sim which should be simulatable with IRSIM. (Note that the above statements assume that open_pdks has installed the sky130 PDK into the default location /usr/local/share/pdk/.)

The main things I did were to define a routine to read the ".prm" file and use the "device" records to associate all the device names with component types, and then extend the .sim file writing routine to write out the subcircuit x components if the subcircuits correspond to names present in the .prm file. It also properly scales device length and width, and handles device multiplicity.

It's quite possible I have missed something, since I used only one fairly simple example to test. It should be possible to convert hierarchical SPICE netlists by flattening them within netgen, but I have not tried it. If you have any problems, please let me know.

[mhajimorad]

@RTimothyEdwards ,

Thank you so much for the quick update!

Upon installing the updated netgen from opencircuitdesign.com , I receive the following message after running your first command in netgen.

More specifically, after entering
set filenum [readnet prm /usr/local/share/pdk/sky130A/libs.tech/irsim/sky130A_tt_nom_27.prm]

I receive the message
bad format "prm": must be automatic, ext, extflat, sim, ntk, spice, verilog, netgen, actel, or xilinx

[RTimothyEdwards]

"on opencircuitdesign" means you need to do a git clone from the site, not download the tarball. The updated version is 1.5.261. (IRSIM version is 9.7.118).

[RTimothyEdwards]

The tarball is automatically generated at the same time as the github mirror is updated, which happens overnight.

[mhajimorad]

@RTimothyEdwards ,

Thank you! I was able to download the updated versions.

So far, I have tried to test a simple CMOS inverter implemented in sky130. The generated .SIM file reads as follows:

| units: 20000	tech: scmos
x OUT IN GND GND l=30 w=200 x=0 y=0 sky130_fd_pr__nfet_01v8
x OUT IN VDD VDD l=30 w=200 x=0 y=0 sky130_fd_pr__pfet_01v8

Upon launching IRSIM (loading prm file in the process) and typing the following sequence continually yields undefined for node OUT:

% h VDD
% l GND
% l IN
% watchnode OUT
% s
% h IN
% s
% l IN
% s

Is there something that I am doing wrong?

[RTimothyEdwards]

@mhajimorad : I am going to have to rethink something here. . . the pins are being output in the order they were read from the SPICE file, but .sim files use order G-S-D-B for FETs while SPICE uses order D-G-S-B. I will need to fix that.

[RTimothyEdwards]

@mhajimorad : It should be fixed now. Thanks for the feedback!
Make sure that for your inverter example, the output reads "x IN OUT GND GND" and "x IN OUT VDD VDD".

[mhajimorad]

@RTimothyEdwards ,

Thank you!

So that I can also test/confirm some xschem schematics that contain multiple levels of hierarchy (which lead to SPICE netlists with multiple levels of SUBCKT definitions), you had mentioned something about "flattening" in netgen.

To flatten a SPICE netlist, are there sequences of netgen commands you recommend to be entered? I assume these would go after the readnet and before the writenet commands?

Thank you again!

[RTimothyEdwards]

@mhajimorad : I had to push another correction to netgen to get the flattening to work correctly (netgen version 1.5.262).
With the update, here's a simple test using the Efabless caravel repository from https://github.com/efabless/caravel. After using xschem to write the netlist of simple_por.sch into simple_por.sim, run netgen and issue the following commands:

set filenum [readnet prm $PDK_ROOT/sky130A/libs.tech/irsim/sky130A_tt_nom_27.prm]
readnet spice $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice $filenum
readnet spice simple_por.spice $filenum
flatten simple_por
writenet sim simple_por

This is probably not a great example to use because it is an analog circuit and is not simulatable in IRSIM, but hopefully that shows several things, such as how to read in netlists from the PDK library (for the several standard cells instantiated in the schematic) and how to flatten the design and write the flattened netlist out to .sim format.

[mhajimorad]

@RTimothyEdwards ,

Thank you for your message.

I did try an example from xschem's "xschemrc" file, where the circuit contains CMOS NAND and NOT circuits drawn in a hierarchical fashion. I have attached the SPICE file that xschem produces.

I subsequently used the latest version of netgen to produce a SIM file, using the following commands

set filenum [readnet prm $PDK_ROOT/sky130A/libs.tech/irsim/sky130A_tt_nom_27.prm]
readnet spice my_netlist.spice $filenum
flatten my_netlist.spice
writenet sim my_netlist.spice

I did receive subckt undefined messages after the second line, but I am guessing this is why we subsequently run the "flatten" command afterward on the third line. In case it is of interest, I have also attached the produced SIM file. Upon testing the SIM file in IRSIM, the circuit appears to correctly simulate.

Before testing additional example circuits that have more levels of hierarchy, I just wanted to confirm that things look okay with the SIM file.

Thank you for all of your help!

sky130_cmos_nand_inverter.spice.txt
sky130_cmos_nand_inverter.sim.txt

[RTimothyEdwards]

I have gotten rid of most of the "undefined" messages, but there are a few device types that are not in the PRM file. I was thinking that probably there is a better way to handle the device types through the setup file instead of reading the PRM file, but it's something I'll need to code.

Your example files look good. Let me know if you have any other issues.