Possible problem with verilog port processing

[d-m-bailey]

netgen 1.5.276

I intended to add vssd1_ext, vssd2_ext, vccd1_ext and vccd2_ext ports to the gl verilog for caravel chip_io.v. However, after copying vccd2_pad in the port list, I forgot to change it to vccd2_ext.

module chip_io(vddio_pad, vddio_pad2, vssio_pad, vssio_pad2, vccd_pad, vssd_pad, vdda_pad, vssa_pad, vdda1_pad, vdda1_pad2, vdda2_pad, vssa1_pad, vssa1_pad2, vssa2_pad, vccd1_pad, vccd1_ext, vccd2_pad, vccd2_pad, vssd1_pad, vssd1_ext, vssd2_pad, vssd2_ext, vddio, vssio, vccd

There are 2 vccd2_pad ports and no vccd2_ext port.

Later in the file, I did explicitly define

  inout vccd2_ext;
  wire vccd2_ext;

netgen does not flag an undefined port error for vccd2_ext.

I think that netgen should check the port list and the port direction declaration and flag an error if either is missing.