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1. Parameterized-FIFO Parameterized-FIFO Public

   Parameterized FIFO Design in Verilog using Vivado

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2. 3-Stage-ALU-Pipeline-Processor 3-Stage-ALU-Pipeline-Processor Public

   🚀 Verilog-based 3-stage pipelined ALU processor supporting ADD, SUB, AND, OR, MUL (Booth’s), and DIV (Restoring) operations.

3. aes-apb-ctr aes-apb-ctr Public

   An AES-128 encryption module in CTR mode with APB interface, implemented in Verilog for FPGA-based secure data communication systems.

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