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__init__.py
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2055 lines (1915 loc) · 104 KB
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import enum
import json
import math
from pathlib import Path
from typing import Optional, Tuple, List
import binaryninja
from binaryninja import Architecture, RegisterInfo, InstructionInfo, InstructionTextToken, \
InstructionTextTokenType, BinaryViewType, Endianness, BranchType, lowlevelil, \
LowLevelILLabel, LowLevelILFunction, LLIL_TEMP, FlagRole, LowLevelILOperation, \
FlagWriteTypeName, FlagType, ILRegisterType, IntrinsicInfo, Type, \
IntrinsicInput, CallingConvention, Platform, ILRegister, Workflow, AnalysisContext, \
Activity, LowLevelILInstruction, LowLevelILSetReg, LowLevelILAdd, ILSourceLocation, \
TypeLibrary, BinaryView, LowLevelILFlagCondition, SemanticGroupType
from binaryninja.lowlevelil import ExpressionIndex, ILFlag, InstructionIndex, \
LowLevelILConst, LowLevelILReg
from binaryninja.warp import WarpContainer
"""
Example Architecture for the Quark[1] VM architecture
Demonstrating plugin support for:
* Disassembly
* Control Flow
* Patching
* Assembly
* Lifting
* Semantic Flags
* Calling Conventions
* Platform Types
* Type Libraries
* WARP Signatures
Described in detail in our three-part blog series:
1. https://binary.ninja/2026/02/20/quark-platform-part-1.html
2. https://binary.ninja/2026/02/26/quark-platform-part-2.html
3. https://binary.ninja/2026/03/04/quark-platform-part-3.html
"""
# ----------------------------------------------------------------------------------------
# Helper Functions
def rol(i, n):
"""
Rotate i32 left
:param i: Integer to rotate
:param n: Number of bits to rotate
:return: Rotated value
"""
return ((i << n) & 0xffffffff) | (i >> (32 - n))
def ror(i, n):
"""
Rotate i32 right
:param i: Integer to rotate
:param n: Number of bits to rotate
:return: Rotated value
"""
return (i >> n) | ((i << (32 - n)) & 0xffffffff)
def i32(i):
"""
Convert u32 to i32 via 2's complement
:param i: Integer to convert
:return: `i` but if it was > 0x80000000 then negative and 2's complement
"""
if i >= 0x80000000:
return -(0x100000000 - (i & 0xffffffff))
return i & 0x7fffffff
# ----------------------------------------------------------------------------------------
# Opcodes
class QuarkOpcode(enum.IntEnum):
ldb = 0x0
ldh = 0x1
ldw = 0x2
ldmw = 0x3
stb = 0x4
sth = 0x5
stw = 0x6
stmw = 0x7
ldbu = 0x8
ldhu = 0x9
ldwu = 0xa
ldmwu = 0xb
stbu = 0xc
sthu = 0xd
stwu = 0xe
stmwu = 0xf
ldsxb = 0x10
ldsxh = 0x11
ldsxbu = 0x12
ldsxhu = 0x13
ldi = 0x14
ldih = 0x15
jmp = 0x16
call = 0x17
add = 0x18
sub = 0x19
addx = 0x1a
subx = 0x1b
mulx = 0x1c
imulx = 0x1d
mul = 0x1e
integer_group = 0x1f # See QuarkIntegerOpcode below
div = 0x20
idiv = 0x21
mod = 0x22
imod = 0x23
and_ = 0x24
or_ = 0x25
xor = 0x26
sar = 0x27
shl = 0x28
shr = 0x29
rol = 0x2a
ror = 0x2b
syscall = 0x2c
cmp = 0x2d # See QuarkCompareOpcode below
icmp = 0x2e
# These are all unimplemented by defined by the spec
# fcmp = 0x2f
# ldfs = 0x30
# ldfd = 0x31
# stfs = 0x32
# stfd = 0x33
# ldfsu = 0x34
# ldfdu = 0x35
# stfsu = 0x36
# stfdu = 0x37
# fadd = 0x38
# fsub = 0x39
# fmul = 0x3a
# fdiv = 0x3b
# fmod = 0x3c
# fpow = 0x3d
# flog = 0x3e
# float_group = 0x3f
class QuarkIntegerOpcode(enum.IntEnum):
mov = 0x0
xchg = 0x1
sxb = 0x2
sxh = 0x3
swaph = 0x4
swapw = 0x5
call = 0x6
neg = 0x8
not_ = 0x9
zxb = 0xa
zxh = 0xb
ldcr = 0xe
stcr = 0xf
syscall = 0x10
setcc = 0x18
clrcc = 0x19
notcc = 0x1a
movcc = 0x1b
andcc = 0x1c
orcc = 0x1d
xorcc = 0x1e
# Unimplemented but defined
bp = 0x1f
class QuarkCompareOpcode(enum.IntEnum):
lt = 0
le = 1
ge = 2
gt = 3
eq = 4
ne = 5
nz = 6
z = 7
# ----------------------------------------------------------------------------------------
# Instruction format and decoding/encoding
class QuarkInstruction:
def __init__(self, instr: int):
self.instr = instr
def __repr__(self):
return f"QuarkInstruction({self.cond=} {self.op=} {self.a=} {self.b=} {self.c=} {self.d=} {self.imm5=} {self.imm11=} {self.imm17=} {self.imm22=} {self.immhi=} {self.smallimm=} {self.largeimm=})"
@property
def cond(self):
return self.instr >> 28
@cond.setter
def cond(self, cond):
self.instr = (self.instr & 0b0000_1111_1111_1111_1111_1111_1111_1111) | ((cond & 0xf) << 28)
@property
def op(self):
return (self.instr >> 22) & 0x3f
@op.setter
def op(self, op):
self.instr = (self.instr & 0b1111_0000_0011_1111_1111_1111_1111_1111) | ((op & 0x3f) << 22)
@property
def a(self):
return (self.instr >> 17) & 0x1f
@a.setter
def a(self, a):
self.instr = (self.instr & 0b1111_1111_1100_0001_1111_1111_1111_1111) | ((a & 0x1f) << 17)
@property
def b(self):
return (self.instr >> 12) & 0x1f
@b.setter
def b(self, b):
self.instr = (self.instr & 0b1111_1111_1111_1110_0000_1111_1111_1111) | ((b & 0x1f) << 12)
@property
def c(self):
return (self.instr >> 5) & 0x1f
@c.setter
def c(self, c):
self.instr = (self.instr & 0b1111_1111_1111_1111_1111_1100_0001_1111) | ((c & 0x1f) << 5)
@property
def d(self):
return self.instr & 0x1f
@d.setter
def d(self, d):
self.instr = (self.instr & 0b1111_1111_1111_1111_1111_1111_1110_0000) | (d & 0x1f)
@property
def imm5(self):
if self.instr & 0x10:
return (self.instr & 0x1f) | 0xffffffe0
return self.instr & 0x1f
@imm5.setter
def imm5(self, imm5):
if imm5 < 0:
# 2s complement with 32 bit
imm5 = 0x100000000 + imm5
self.instr = (self.instr & 0b1111_1111_1111_1111_1111_1111_1110_0000) | (imm5 & 0x1f)
@property
def imm11(self):
if self.instr & 0x400:
return (self.instr & 0x7ff) | 0xfffff800
return self.instr & 0x7ff
@imm11.setter
def imm11(self, imm11):
if imm11 < 0:
imm11 = 0x100000000 + imm11
self.instr = (self.instr & 0b1111_1111_1111_1111_1111_1000_0000_0000) | (imm11 & 0x7ff)
@property
def imm17(self):
if self.instr & 0x10000:
return (self.instr & 0x1ffff) | 0xfffe0000
return self.instr & 0x1ffff
@imm17.setter
def imm17(self, imm17):
if imm17 < 0:
imm17 = 0x100000000 + imm17
self.instr = (self.instr & 0b1111_1111_1111_1110_0000_0000_0000_0000) | (imm17 & 0x1ffff)
@property
def imm22(self):
if self.instr & 0x200000:
return (self.instr & 0x3fffff) | 0xffc00000
return self.instr & 0x3fffff
@imm22.setter
def imm22(self, imm22):
if imm22 < 0:
imm22 = 0x100000000 + imm22
self.instr = (self.instr & 0b1111_1111_1100_0000_0000_0000_0000_0000) | (imm22 & 0x3fffff)
@property
def immhi(self):
return (self.instr & 0xffff) << 16
@immhi.setter
def immhi(self, immhi):
self.instr = (self.instr & 0b1111_1111_1111_1111_0000_0000_0000_0000) | ((immhi & 0xffff0000) >> 16)
@property
def smallimm(self):
return True if self.instr & 0x400 else False
@smallimm.setter
def smallimm(self, smallimm):
self.instr = (self.instr & 0b1111_1111_1111_1111_1111_1011_1111_1111) | (0x400 if smallimm else 0)
@property
def largeimm(self):
return True if self.instr & 0x800 else False
@largeimm.setter
def largeimm(self, largeimm):
self.instr = (self.instr & 0b1111_1111_1111_1111_1111_0111_1111_1111) | (0x800 if largeimm else 0)
# ----------------------------------------------------------------------------------------
# Architecture
class QuarkArch(Architecture):
name = "Quark"
endianness = Endianness.LittleEndian
address_size = 4
default_int_size = 4
instr_alignment = 1 # Indirect calls can be unaligned
max_instr_length = 4
regs = {
'sp': RegisterInfo('sp', 4),
'r1': RegisterInfo('r1', 4),
'r2': RegisterInfo('r2', 4),
'r3': RegisterInfo('r3', 4),
'r4': RegisterInfo('r4', 4),
'r5': RegisterInfo('r5', 4),
'r6': RegisterInfo('r6', 4),
'r7': RegisterInfo('r7', 4),
'r8': RegisterInfo('r8', 4),
'r9': RegisterInfo('r9', 4),
'r10': RegisterInfo('r10', 4),
'r11': RegisterInfo('r11', 4),
'r12': RegisterInfo('r12', 4),
'r13': RegisterInfo('r13', 4),
'r14': RegisterInfo('r14', 4),
'r15': RegisterInfo('r15', 4),
'r16': RegisterInfo('r16', 4),
'r17': RegisterInfo('r17', 4),
'r18': RegisterInfo('r18', 4),
'r19': RegisterInfo('r19', 4),
'r20': RegisterInfo('r20', 4),
'r21': RegisterInfo('r21', 4),
'r22': RegisterInfo('r22', 4),
'r23': RegisterInfo('r23', 4),
'r24': RegisterInfo('r24', 4),
'r25': RegisterInfo('r25', 4),
'r26': RegisterInfo('r26', 4),
'r27': RegisterInfo('r27', 4),
'r28': RegisterInfo('r28', 4),
'r29': RegisterInfo('r29', 4),
'lr': RegisterInfo('lr', 4),
# No ip register. It's handled special
'syscall_num': RegisterInfo('syscall_num', 4),
}
flags = [
'cc0', 'cc1', 'cc2', 'cc3',
]
flag_roles = {
# All flags are special, since none are reserved for specific behaviors
'cc0': FlagRole.SpecialFlagRole,
'cc1': FlagRole.SpecialFlagRole,
'cc2': FlagRole.SpecialFlagRole,
'cc3': FlagRole.SpecialFlagRole,
}
semantic_flag_classes = [
'cmp.lt', 'cmp.le', 'cmp.ge', 'cmp.gt',
'icmp.lt', 'icmp.le', 'icmp.ge', 'icmp.gt',
'eq', 'ne', 'z', 'nz',
]
semantic_flag_groups = [
# Flags are only ever read one at a time
'cc0',
'cc1',
'cc2',
'cc3',
]
flags_required_for_semantic_flag_group = {
'cc0': ['cc0'],
'cc1': ['cc1'],
'cc2': ['cc2'],
'cc3': ['cc3'],
}
flag_conditions_for_semantic_flag_group = {
'cc0': {
'cmp.lt': LowLevelILFlagCondition.LLFC_ULT,
'cmp.le': LowLevelILFlagCondition.LLFC_ULE,
'cmp.ge': LowLevelILFlagCondition.LLFC_UGE,
'cmp.gt': LowLevelILFlagCondition.LLFC_UGT,
'icmp.lt': LowLevelILFlagCondition.LLFC_SLT,
'icmp.le': LowLevelILFlagCondition.LLFC_SLE,
'icmp.ge': LowLevelILFlagCondition.LLFC_SGE,
'icmp.gt': LowLevelILFlagCondition.LLFC_SGT,
'eq': LowLevelILFlagCondition.LLFC_E,
'ne': LowLevelILFlagCondition.LLFC_NE,
},
'cc1': {
'cmp.lt': LowLevelILFlagCondition.LLFC_ULT,
'cmp.le': LowLevelILFlagCondition.LLFC_ULE,
'cmp.ge': LowLevelILFlagCondition.LLFC_UGE,
'cmp.gt': LowLevelILFlagCondition.LLFC_UGT,
'icmp.lt': LowLevelILFlagCondition.LLFC_SLT,
'icmp.le': LowLevelILFlagCondition.LLFC_SLE,
'icmp.ge': LowLevelILFlagCondition.LLFC_SGE,
'icmp.gt': LowLevelILFlagCondition.LLFC_SGT,
'eq': LowLevelILFlagCondition.LLFC_E,
'ne': LowLevelILFlagCondition.LLFC_NE,
},
'cc2': {
'cmp.lt': LowLevelILFlagCondition.LLFC_ULT,
'cmp.le': LowLevelILFlagCondition.LLFC_ULE,
'cmp.ge': LowLevelILFlagCondition.LLFC_UGE,
'cmp.gt': LowLevelILFlagCondition.LLFC_UGT,
'icmp.lt': LowLevelILFlagCondition.LLFC_SLT,
'icmp.le': LowLevelILFlagCondition.LLFC_SLE,
'icmp.ge': LowLevelILFlagCondition.LLFC_SGE,
'icmp.gt': LowLevelILFlagCondition.LLFC_SGT,
'eq': LowLevelILFlagCondition.LLFC_E,
'ne': LowLevelILFlagCondition.LLFC_NE,
},
'cc3': {
'cmp.lt': LowLevelILFlagCondition.LLFC_ULT,
'cmp.le': LowLevelILFlagCondition.LLFC_ULE,
'cmp.ge': LowLevelILFlagCondition.LLFC_UGE,
'cmp.gt': LowLevelILFlagCondition.LLFC_UGT,
'icmp.lt': LowLevelILFlagCondition.LLFC_SLT,
'icmp.le': LowLevelILFlagCondition.LLFC_SLE,
'icmp.ge': LowLevelILFlagCondition.LLFC_SGE,
'icmp.gt': LowLevelILFlagCondition.LLFC_SGT,
'eq': LowLevelILFlagCondition.LLFC_E,
'ne': LowLevelILFlagCondition.LLFC_NE,
},
}
semantic_class_for_flag_write_type = {
'cmp.lt.cc0': 'cmp.lt', 'cmp.le.cc0': 'cmp.le', 'cmp.ge.cc0': 'cmp.ge', 'cmp.gt.cc0': 'cmp.gt', 'cmp.eq.cc0': 'eq', 'cmp.ne.cc0': 'ne', 'cmp.z.cc0': 'z', 'cmp.nz.cc0': 'nz',
'icmp.lt.cc0': 'icmp.lt', 'icmp.le.cc0': 'icmp.le', 'icmp.ge.cc0': 'icmp.ge', 'icmp.gt.cc0': 'icmp.gt', 'icmp.eq.cc0': 'eq', 'icmp.ne.cc0': 'ne', 'icmp.z.cc0': 'z', 'icmp.nz.cc0': 'nz',
'cmp.lt.cc1': 'cmp.lt', 'cmp.le.cc1': 'cmp.le', 'cmp.ge.cc1': 'cmp.ge', 'cmp.gt.cc1': 'cmp.gt', 'cmp.eq.cc1': 'eq', 'cmp.ne.cc1': 'ne', 'cmp.z.cc1': 'z', 'cmp.nz.cc1': 'nz',
'icmp.lt.cc1': 'icmp.lt', 'icmp.le.cc1': 'icmp.le', 'icmp.ge.cc1': 'icmp.ge', 'icmp.gt.cc1': 'icmp.gt', 'icmp.eq.cc1': 'eq', 'icmp.ne.cc1': 'ne', 'icmp.z.cc1': 'z', 'icmp.nz.cc1': 'nz',
'cmp.lt.cc2': 'cmp.lt', 'cmp.le.cc2': 'cmp.le', 'cmp.ge.cc2': 'cmp.ge', 'cmp.gt.cc2': 'cmp.gt', 'cmp.eq.cc2': 'eq', 'cmp.ne.cc2': 'ne', 'cmp.z.cc2': 'z', 'cmp.nz.cc2': 'nz',
'icmp.lt.cc2': 'icmp.lt', 'icmp.le.cc2': 'icmp.le', 'icmp.ge.cc2': 'icmp.ge', 'icmp.gt.cc2': 'icmp.gt', 'icmp.eq.cc2': 'eq', 'icmp.ne.cc2': 'ne', 'icmp.z.cc2': 'z', 'icmp.nz.cc2': 'nz',
'cmp.lt.cc3': 'cmp.lt', 'cmp.le.cc3': 'cmp.le', 'cmp.ge.cc3': 'cmp.ge', 'cmp.gt.cc3': 'cmp.gt', 'cmp.eq.cc3': 'eq', 'cmp.ne.cc3': 'ne', 'cmp.z.cc3': 'z', 'cmp.nz.cc3': 'nz',
'icmp.lt.cc3': 'icmp.lt', 'icmp.le.cc3': 'icmp.le', 'icmp.ge.cc3': 'icmp.ge', 'icmp.gt.cc3': 'icmp.gt', 'icmp.eq.cc3': 'eq', 'icmp.ne.cc3': 'ne', 'icmp.z.cc3': 'z', 'icmp.nz.cc3': 'nz',
}
flag_write_types = {
# Each of the 8 unsigned comparisons that could affect cc0
'cmp.lt.cc0', 'cmp.le.cc0', 'cmp.ge.cc0', 'cmp.gt.cc0', 'cmp.eq.cc0', 'cmp.ne.cc0', 'cmp.z.cc0', 'cmp.nz.cc0',
# Same thing for the signed comparisons
'icmp.lt.cc0', 'icmp.le.cc0', 'icmp.ge.cc0', 'icmp.gt.cc0', 'icmp.eq.cc0', 'icmp.ne.cc0', 'icmp.z.cc0', 'icmp.nz.cc0',
# Same thing for the other flags
'cmp.lt.cc1', 'cmp.le.cc1', 'cmp.ge.cc1', 'cmp.gt.cc1', 'cmp.eq.cc1', 'cmp.ne.cc1', 'cmp.z.cc1', 'cmp.nz.cc1',
'icmp.lt.cc1', 'icmp.le.cc1', 'icmp.ge.cc1', 'icmp.gt.cc1', 'icmp.eq.cc1', 'icmp.ne.cc1', 'icmp.z.cc1', 'icmp.nz.cc1',
'cmp.lt.cc2', 'cmp.le.cc2', 'cmp.ge.cc2', 'cmp.gt.cc2', 'cmp.eq.cc2', 'cmp.ne.cc2', 'cmp.z.cc2', 'cmp.nz.cc2',
'icmp.lt.cc2', 'icmp.le.cc2', 'icmp.ge.cc2', 'icmp.gt.cc2', 'icmp.eq.cc2', 'icmp.ne.cc2', 'icmp.z.cc2', 'icmp.nz.cc2',
'cmp.lt.cc3', 'cmp.le.cc3', 'cmp.ge.cc3', 'cmp.gt.cc3', 'cmp.eq.cc3', 'cmp.ne.cc3', 'cmp.z.cc3', 'cmp.nz.cc3',
'icmp.lt.cc3', 'icmp.le.cc3', 'icmp.ge.cc3', 'icmp.gt.cc3', 'icmp.eq.cc3', 'icmp.ne.cc3', 'icmp.z.cc3', 'icmp.nz.cc3',
# And addx, which has its own special behavior
'addx'
}
flags_written_by_flag_write_type = {
# Each of these comparisons only affects one flag at a time
'cmp.lt.cc0': ['cc0'], 'cmp.le.cc0': ['cc0'], 'cmp.ge.cc0': ['cc0'], 'cmp.gt.cc0': ['cc0'], 'cmp.eq.cc0': ['cc0'], 'cmp.ne.cc0': ['cc0'], 'cmp.z.cc0': ['cc0'], 'cmp.nz.cc0': ['cc0'],
'icmp.lt.cc0': ['cc0'], 'icmp.le.cc0': ['cc0'], 'icmp.ge.cc0': ['cc0'], 'icmp.gt.cc0': ['cc0'], 'icmp.eq.cc0': ['cc0'], 'icmp.ne.cc0': ['cc0'], 'icmp.z.cc0': ['cc0'], 'icmp.nz.cc0': ['cc0'],
'cmp.lt.cc1': ['cc1'], 'cmp.le.cc1': ['cc1'], 'cmp.ge.cc1': ['cc1'], 'cmp.gt.cc1': ['cc1'], 'cmp.eq.cc1': ['cc1'], 'cmp.ne.cc1': ['cc1'], 'cmp.z.cc1': ['cc1'], 'cmp.nz.cc1': ['cc1'],
'icmp.lt.cc1': ['cc1'], 'icmp.le.cc1': ['cc1'], 'icmp.ge.cc1': ['cc1'], 'icmp.gt.cc1': ['cc1'], 'icmp.eq.cc1': ['cc1'], 'icmp.ne.cc1': ['cc1'], 'icmp.z.cc1': ['cc1'], 'icmp.nz.cc1': ['cc1'],
'cmp.lt.cc2': ['cc2'], 'cmp.le.cc2': ['cc2'], 'cmp.ge.cc2': ['cc2'], 'cmp.gt.cc2': ['cc2'], 'cmp.eq.cc2': ['cc2'], 'cmp.ne.cc2': ['cc2'], 'cmp.z.cc2': ['cc2'], 'cmp.nz.cc2': ['cc2'],
'icmp.lt.cc2': ['cc2'], 'icmp.le.cc2': ['cc2'], 'icmp.ge.cc2': ['cc2'], 'icmp.gt.cc2': ['cc2'], 'icmp.eq.cc2': ['cc2'], 'icmp.ne.cc2': ['cc2'], 'icmp.z.cc2': ['cc2'], 'icmp.nz.cc2': ['cc2'],
'cmp.lt.cc3': ['cc3'], 'cmp.le.cc3': ['cc3'], 'cmp.ge.cc3': ['cc3'], 'cmp.gt.cc3': ['cc3'], 'cmp.eq.cc3': ['cc3'], 'cmp.ne.cc3': ['cc3'], 'cmp.z.cc3': ['cc3'], 'cmp.nz.cc3': ['cc3'],
'icmp.lt.cc3': ['cc3'], 'icmp.le.cc3': ['cc3'], 'icmp.ge.cc3': ['cc3'], 'icmp.gt.cc3': ['cc3'], 'icmp.eq.cc3': ['cc3'], 'icmp.ne.cc3': ['cc3'], 'icmp.z.cc3': ['cc3'], 'icmp.nz.cc3': ['cc3'],
# addx always modifies the cc3 flag
'addx': ['cc3']
}
stack_pointer = 'sp'
link_reg = 'lr'
intrinsics = {
'__byteswaph': IntrinsicInfo(
# Inputs
[IntrinsicInput(Type.int(2, False), 'input')],
# Outputs
[Type.int(4, False)]
),
'__byteswapw': IntrinsicInfo([IntrinsicInput(Type.int(4, False), 'input')], [Type.int(4, False)]),
}
ip_reg_index = 31
# ------------------------------------------------------------------------------------
# Control Flow
def get_instruction_info(self, data: bytes, addr: int) -> Optional[InstructionInfo]:
info = QuarkInstruction(int.from_bytes(data, 'little'))
try:
op = QuarkOpcode(info.op)
except ValueError:
print(f"Invalid opcode {info.op:#x} at {addr:#x} {data}")
return None
result = InstructionInfo()
result.length = 4
# Technically, every instruction with a conditional bit *can* jump
# but only handle the ones that are actually jump instructions here.
# The others will be figured out when lifting
match op:
case QuarkOpcode.jmp:
if info.cond & 8:
if info.cond & 1: # Jump if condition is met
result.add_branch(BranchType.TrueBranch, addr + 4 + i32(info.imm22 << 2))
result.add_branch(BranchType.FalseBranch, addr + 4)
else: # Jump if condition is NOT met
result.add_branch(BranchType.TrueBranch, addr + 4)
result.add_branch(BranchType.FalseBranch, addr + 4 + i32(info.imm22 << 2))
else: # Unconditional jump
result.add_branch(BranchType.UnconditionalBranch, addr + 4 + i32(info.imm22 << 2))
case QuarkOpcode.call: # Call relative
result.add_branch(BranchType.CallDestination, addr + 4 + i32(info.imm22 << 2))
case QuarkOpcode.syscall:
result.add_branch(BranchType.SystemCall)
case QuarkOpcode.integer_group:
int_op = QuarkIntegerOpcode(info.b)
match int_op:
case QuarkIntegerOpcode.mov:
# Move to ip is a jump
# Could have included all other instructions that write to ip
if info.a == self.ip_reg_index:
result.add_branch(BranchType.IndirectBranch)
case QuarkIntegerOpcode.call: # Indirect call
result.add_branch(BranchType.CallDestination)
case QuarkIntegerOpcode.syscall:
result.add_branch(BranchType.SystemCall)
return result
# ------------------------------------------------------------------------------------
# Disassembly
def get_instruction_text(self, data: bytes, addr: int) -> Optional[Tuple[List['function.InstructionTextToken'], int]]:
info = QuarkInstruction(int.from_bytes(data, 'little'))
try:
op = QuarkOpcode(info.op)
except ValueError:
print(f"Invalid opcode {info.op:#x} at {addr:#x} {data}")
return None
tokens = []
# Conditional instructions start with `if ccX`
if info.cond & 8:
if info.cond & 1:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.TextToken, "if"),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, f"cc{(info.cond >> 1) & 3}"),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
])
else:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.TextToken, "if"),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.OperationToken, "!"),
InstructionTextToken(InstructionTextTokenType.RegisterToken, f"cc{(info.cond >> 1) & 3}"),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
])
elif info.cond & 1:
# Could replace entire instruction with `nop` but this lets us see what was there
tokens.extend([
InstructionTextToken(InstructionTextTokenType.TextToken, "skip"),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
])
def reg_name(reg):
"""
Convert register index to name
:param reg: Register index from instruction
:return: Register name
"""
if reg == self.ip_reg_index:
return "ip"
return self.get_reg_name(reg)
def cval_tokens(plus: bool, zero: bool, signed: bool):
"""
Get tokens for cval addressing mode
:param plus: If a + should be prepended, to match - being prepended for negative constants
:param zero: If empty cval should return a token for 0
:param signed: If integers should decode as signed with 2's complement i32s
:return: List of tokens to insert into disassembly
"""
if info.largeimm:
if info.imm11 == 0:
if not zero:
return []
else:
if plus:
return [
InstructionTextToken(InstructionTextTokenType.OperationToken, f"+"),
InstructionTextToken(InstructionTextTokenType.IntegerToken, "0", value=0),
]
else:
return [
InstructionTextToken(InstructionTextTokenType.IntegerToken, "0", value=0),
]
elif i32(info.imm11) > 0 or not signed:
if plus:
return [
InstructionTextToken(InstructionTextTokenType.OperationToken, f"+"),
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{info.imm11:#x}", value=info.imm11),
]
else:
return [
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{info.imm11:#x}", value=info.imm11),
]
else:
if plus:
return [
InstructionTextToken(InstructionTextTokenType.OperationToken, f"-"),
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{-i32(info.imm11):#x}", value=i32(info.imm11)),
]
else:
return [
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{i32(info.imm11):#x}", value=i32(info.imm11)),
]
elif info.smallimm:
# Never seen this used in practice but the interpreter supports it
cval = rol(info.imm5, info.d)
if cval == 0:
if not zero:
return []
else:
if plus:
return [
InstructionTextToken(InstructionTextTokenType.OperationToken, f"+"),
InstructionTextToken(InstructionTextTokenType.IntegerToken, "0", value=0),
]
else:
return [
InstructionTextToken(InstructionTextTokenType.IntegerToken, "0", value=0),
]
elif cval > 0 or not signed:
if plus:
return [
InstructionTextToken(InstructionTextTokenType.OperationToken, f"+"),
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{cval:#x}", value=cval),
]
else:
return [
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{cval:#x}", value=cval),
]
else:
if plus:
return [
InstructionTextToken(InstructionTextTokenType.OperationToken, f"-"),
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{i32(cval):#x}", value=-i32(cval)),
]
else:
return [
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{cval:#x}", value=cval),
]
else:
if info.d == 0:
if plus:
return [
InstructionTextToken(InstructionTextTokenType.OperationToken, f"+"),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.c)),
]
else:
return [
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.c)),
]
else:
if plus:
return [
InstructionTextToken(InstructionTextTokenType.OperationToken, f"+"),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.c)),
InstructionTextToken(InstructionTextTokenType.OperationToken, f"*"),
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{2**info.d}", value=2**info.d),
]
else:
return [
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.c)),
InstructionTextToken(InstructionTextTokenType.OperationToken, f"*"),
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{2**info.d}", value=2**info.d),
]
match op:
case QuarkOpcode.ldb | QuarkOpcode.ldh | QuarkOpcode.ldw | QuarkOpcode.ldbu | QuarkOpcode.ldhu | QuarkOpcode.ldwu | QuarkOpcode.ldsxb | QuarkOpcode.ldsxh | QuarkOpcode.ldsxbu | QuarkOpcode.ldsxhu:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.BraceToken, "["),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
*cval_tokens(plus=True, zero=False, signed=True),
InstructionTextToken(InstructionTextTokenType.BraceToken, "]"),
])
case QuarkOpcode.ldmw | QuarkOpcode.ldmwu:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.TextToken, ".."),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(30)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.BraceToken, "["),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
*cval_tokens(plus=True, zero=False, signed=True),
InstructionTextToken(InstructionTextTokenType.BraceToken, "]"),
])
case QuarkOpcode.ldi:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{info.imm17:#x}", value=info.imm17),
])
case QuarkOpcode.ldih:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{info.immhi:#x}", value=info.immhi),
])
case QuarkOpcode.stb | QuarkOpcode.sth | QuarkOpcode.stw | QuarkOpcode.stbu | QuarkOpcode.sthu | QuarkOpcode.stwu:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.BraceToken, "["),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
*cval_tokens(plus=True, zero=False, signed=True),
InstructionTextToken(InstructionTextTokenType.BraceToken, "]"),
InstructionTextToken(InstructionTextTokenType.TextToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
])
case QuarkOpcode.stmw | QuarkOpcode.stmwu:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.BraceToken, "["),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
*cval_tokens(plus=True, zero=False, signed=True),
InstructionTextToken(InstructionTextTokenType.BraceToken, "]"),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.TextToken, ".."),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(30)),
])
case QuarkOpcode.jmp | QuarkOpcode.call:
dest = addr + 4 + i32(info.imm22 << 2)
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.PossibleAddressToken, f"{dest:#x}", value=dest),
])
case QuarkOpcode.add | QuarkOpcode.sub | QuarkOpcode.mul | QuarkOpcode.div | QuarkOpcode.idiv | QuarkOpcode.mod | QuarkOpcode.imod:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
*cval_tokens(plus=False, zero=True, signed=True),
])
case QuarkOpcode.xor | QuarkOpcode.sar | QuarkOpcode.shl | QuarkOpcode.shr | QuarkOpcode.rol | QuarkOpcode.ror:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
*cval_tokens(plus=False, zero=True, signed=False),
])
# Gets its own to handle "and" being a reserved keyword
case QuarkOpcode.and_:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, "and"),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
*cval_tokens(plus=False, zero=True, signed=False),
])
# Same as and_
case QuarkOpcode.or_:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, "or"),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
*cval_tokens(plus=False, zero=True, signed=False),
])
case QuarkOpcode.addx | QuarkOpcode.subx:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
*cval_tokens(plus=False, zero=True, signed=True),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, 'cc3'),
])
case QuarkOpcode.mulx | QuarkOpcode.imulx:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.d)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ":"),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.b)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.c)),
])
case QuarkOpcode.syscall:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.IntegerToken, f"{info.imm22}", value=info.imm22),
])
case QuarkOpcode.integer_group:
int_op = QuarkIntegerOpcode(info.b)
match int_op:
case QuarkIntegerOpcode.mov:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, int_op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
*cval_tokens(plus=False, zero=False, signed=True),
])
case QuarkIntegerOpcode.xchg | QuarkIntegerOpcode.sxb | QuarkIntegerOpcode.sxh | QuarkIntegerOpcode.swaph | QuarkIntegerOpcode.swapw | QuarkIntegerOpcode.neg | QuarkIntegerOpcode.zxb | QuarkIntegerOpcode.zxh:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, int_op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.c)),
])
# Gets its own to handle "not" being a reserved keyword
case QuarkIntegerOpcode.not_:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, "not"),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.c)),
])
case QuarkIntegerOpcode.call:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, int_op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
])
case QuarkIntegerOpcode.syscall:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, int_op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
])
case QuarkIntegerOpcode.ldcr | QuarkIntegerOpcode.stcr:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, int_op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
])
case QuarkIntegerOpcode.setcc | QuarkIntegerOpcode.clrcc:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, int_op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, f"cc{(info.a & 3)}"),
])
case QuarkIntegerOpcode.notcc | QuarkIntegerOpcode.movcc:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, int_op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, f"cc{(info.a & 3)}"),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, f"cc{(info.c & 3)}"),
])
case QuarkIntegerOpcode.andcc | QuarkIntegerOpcode.orcc | QuarkIntegerOpcode.xorcc:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, int_op.name),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, f"cc{(info.a & 3)}"),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, f"cc{(info.c & 3)}"),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, f"cc{(info.d & 3)}"),
])
case QuarkIntegerOpcode.bp:
tokens.extend([
InstructionTextToken(InstructionTextTokenType.InstructionToken, int_op.name),
])
case _:
tokens.extend([InstructionTextToken(InstructionTextTokenType.InstructionToken, "??")])
case QuarkOpcode.cmp | QuarkOpcode.icmp:
cmp_op = QuarkCompareOpcode(info.b & 7)
tokens.extend([
# cmp.lt.cc0
InstructionTextToken(InstructionTextTokenType.InstructionToken, f"{op.name}.{cmp_op.name}."),
InstructionTextToken(InstructionTextTokenType.RegisterToken, f"cc{info.b >> 3}"),
InstructionTextToken(InstructionTextTokenType.TextToken, " "),
InstructionTextToken(InstructionTextTokenType.RegisterToken, reg_name(info.a)),
InstructionTextToken(InstructionTextTokenType.OperandSeparatorToken, ", "),
*cval_tokens(plus=False, zero=True, signed=True),
])
case _:
tokens.extend([InstructionTextToken(InstructionTextTokenType.InstructionToken, "??")])
return tokens, 4
# ------------------------------------------------------------------------------------
# Lifting
def get_instruction_low_level_il(self, data: bytes, addr: int, il: LowLevelILFunction) -> Optional[int]:
info = QuarkInstruction(int.from_bytes(data, 'little'))
try:
op = QuarkOpcode(info.op)
except ValueError:
print(f"Invalid opcode {info.op:#x} at {addr:#x} {data}")
return None
# Get name of register in `a` component of instruction
def ra():
# sanity: make sure we don't lift anything that references ip directly
assert info.a != self.ip_reg_index, "Can't handle ip"
return il.arch.get_reg_name(info.a)
def rb():
assert info.b != self.ip_reg_index, "Can't handle ip"
return il.arch.get_reg_name(info.b)
def rc():
assert info.c != self.ip_reg_index, "Can't handle ip"
return il.arch.get_reg_name(info.c)
def rd():
assert info.d != self.ip_reg_index, "Can't handle ip"
return il.arch.get_reg_name(info.d)
# Get expression to get the register in `a` component of instruction
def ra_expr():
# Special case ip register by emitting a constant with its value
if info.a == self.ip_reg_index: # ip
return il.const(4, addr + 4)
return il.reg(4, il.arch.get_reg_name(info.a))
def rb_expr():
if info.b == self.ip_reg_index: # ip
return il.const(4, addr + 4)
return il.reg(4, il.arch.get_reg_name(info.b))
def rc_expr():
if info.c == self.ip_reg_index: # ip
return il.const(4, addr + 4)
return il.reg(4, il.arch.get_reg_name(info.c))
def rd_expr():
if info.d == self.ip_reg_index: # ip
return il.const(4, addr + 4)
return il.reg(4, il.arch.get_reg_name(info.d))
# Addressing modes
def cval():
if info.largeimm:
return il.const(4, info.imm11)
elif info.smallimm:
return il.const(4, rol(info.imm5, info.d))
else:
if info.d == 0:
return rc_expr()
# Temp is probably overkill here, but maybe it will save us from the x86 problem
# of foo = *(bar + (baz * 8)) being annoying to pattern match
il.append(il.set_reg(4, LLIL_TEMP(0), il.shift_left(4, rc_expr(), il.const(4, info.d))))
return il.reg(4, LLIL_TEMP(0))
# Since any instruction can write to any register (including IP), we need to handle
# potentially causing a jump at any point
# Uses the same signature as il.set_reg for easy find+replace
def set_reg_or_jmp(size, reg, value):
if reg == self.ip_reg_index:
return il.jump(value)
else:
return il.set_reg(size, reg, value)
after = None