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VERA rendering pipeline is not properly documented #286

@stople

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@stople

I would like some documentation regarding how the VERA pipeline works.

Based on what I found regarding sprites in the VERA programming guide, I THINK the order is:

  • Background
  • Layer0
  • Layer1

Sprites can be rendered at these locations:

  • Disabled
  • Between background and layer0
  • Between layer0 and layer1
  • In front of layer1

For sprites within the same location, sprites with its properties at a lower address in ram is rendered on top of sprites with its properties higher in ram.

The background itself, is defined by the "Border Color" (DC_BORDER) register.

Once this is confirmed (or corrected), I think this info belongs somewhere inside the VERA Programmer's reference.

In addition to this, I suggest to document how the different screen modes uses the layers, since users may want to start with a screen mode, and do VERA config on top of it. Not sure where this implementation detail should be documented though. I think this info may be in the same category as the memory map describing HOW the x16 stores data in video ram, and thus, I think these details should be stored the same place.

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