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ARM_Cortex_M.md

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ARM

ARM as a company make Architecture, sell the Architecture and companies like STM, TI uses these architectures to develop their own chips and release them into market.

ARM Architectures

  • A-Class
    • Application grade Arch
    • Used to run OS (linux, Mac), and also runs applications like chrome
  • R-Class
    • Used in Real time systems (time-constrant applications)
  • M-Class
    • Used in microcontrollers, single targeted applications
    • Arch is simple (RISC based arch / load and store arch)

Architecture vs Micro-Architecture

  • Simple specification of what CPU should do or behave is called Architecture
  • Implementation of the Arch is called Micro-Architecture
flowchart RL
subgraph B[Memory]
	C[Instruction]
	D[Data]
end
A[CPU] -- Store --> D
D -- Load --> A
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To learn/Master a CPU we need to understand below all models

flowchart TD
   A(CPU) --> B((Programmer's Model))
   A --> C((Exception Model))
   A --> D((Memory Model))
   A --> E((Debug Model))
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  • Programmer's Model - Details out mode of operation of cpu & internal registers
  • Exception Model - Exception is internal to cpu
  • Memory Model - Imagination about how cpu interact with memory, talks about features

ARM Cortex-M series

GPRs

  • GPRs General Purpose registers, data will be loaded into these GPRs while computation
  • We have 16 GPRs (R0 - R15)
  • R13 - Stack Pointer - Holds the address of the last stacked item in memory
  • R14 - Link Register - Stores address where CPU comeback to after exe of function
  • R15 - Program Counter - Pointing to the addressof next instruction to fetch

Special Registers

  • xPSR - Program status register (have 3 internal register)
    • EPSR
    • APSR
    • IPSR
    • Result is union of all three
  • Control Reg used to control privilage's and control which stack pointer to use
  • Status reg is to capture, whether output is -ve or +ve or zero or overflow happend or not

CPU modes

CPU will work in 2 modes

  • Thread Mode - Normal function run
  • Handler Mode - When Int or Exceptions occur runs in this mode

CPU also have 2 access modes

  • Privilage - In this mode, it can access control and status registers
  • Non-Privilage - It can't access control and status registers

Handler mode always privilage, but Thread mode it can be Privilaged or Non-Privilaged. Booting always starts with Privilage state in Thread mode

Note - D-flipflops are used as memory