RGMII PHY with fixed link

[dorotheapfeiffer]

Dear all,

I'm trying to use the verilog ethernet (amazing firmware btw) RGMII MAC together with a Marvell 88E1512 PHY and a SFP module, similar to the setups described in the posts below. The MAC connects via the RGMII interface to the 88E151 PHY, and then the SERDES interface of the PHY connects to the SFP:

https://support.xilinx.com/s/question/0D54U00006tcP1kSAE/marvell-88e1512-sfp-mode?language=en_US
https://support.xilinx.com/s/question/0D52E00006hpjuESAQ/rgmii-to-1000basex-using-88e1512?language=en_US

It appears that the only way to get it working with this particular PHY chip is to use a fixed link. Since the users in the two posts use a Zynq they can just set the fixed link in their device tree.

My question is now how to use a fixed link with the RGMII MAC of verilog ethernet. I do not see any setting to turn auto negotiation off. The speed of the link is determined via the RGMII interface using counters. I need to have 1000GBs full-duplex for the link to work. If I check the output register speed of module eth_mac_1g_rgmii_fifo
[https://github.com/alexforencich/verilog-ethernet/blob/master/rtl/eth_mac_1g_rgmii_fifo.v] it correctly shows the value b'10 or 2, which is 1000GBs. But when reading via MDIO the registers of my 88E1512, it indicates that the link is down.

Is there a way to turn auto-negotiation off and force a fixed link ? Any help and suggestions welcome!

Cheers

Dorothea

[alexforencich]

You'll probably have to poke the PHY via MDIO. I recommend taking a look at the VCU118 design - the PHY on that board can't be pin-strapped into the correct configuration for SGMII to work, so there is a state machine to perform the appropriate register writes on startup.

[dorotheapfeiffer]

Hi Alex,

thanks a lot for your answer. The board designer did not provide the proper 1.8V to the 88E1512, which explained some of the issues. I followed your suggestion to program via MDIO the PHY registers, and manage to get link up (according to the status register of the PHY). But the pinging does not work, wireshark shows that the ARP request does not find the board. My firmware does support pinging, tested with other boards.

Any idea where to start to debug this problem? If I enable test packages on the RGMII interface via the PHY chip, the MAC on the FPGA receives them. So the RX part between PHY chip and MAC seems to work.

Cheers

Dorothea

[dorotheapfeiffer]

The problem is solved. Although the Marvell 88E1512 adds internal delays, it is necessary to delay RXD and RXD_CTL. After disabling the 90 degree clock option for the 125 MHz, everything works.