Auto PR: Differences detected (#25)

Co-authored-by: GitHub Actions <actions@github.com>

Author: github-actions[bot]

catalog/list.json

@@ -1,5 +1,5 @@
 {
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+    "num": 186,
     "designs": [
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@@ -4532,12 +4532,12 @@
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             "device_part": "A5ED065BB32AE6SR0",
             "description": "Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
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+            "rich_description": "<p>Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png\"/></p>",
             "category": "Memory",
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             "documentations": [],
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         },
@@ -4610,7 +4610,7 @@
             "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 5 FPGA.",
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             "category": "Machine Learning",
-            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_g/tinyml_liteRT/img/block_diagram.png",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_g/tinyml_liteRT",
             "downloadUrl": "agilex5_niosv_g_tinyml_liteRT.zip",
             "documentations": [],
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@@ -4629,10 +4629,10 @@
             "description": "This design demonstrates the baseline Golden Hardware Reference Design (GHRD) for a Nios® V/m processor with basic bare minimum peripherals required for any application execution for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.",
             "rich_description": "<p>This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel-IO and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.1.1/niosv_m/niosv_m_baseline_ghrd/img/baseling_ghrd_block_design.png\"/></p>",
             "category": "GHRD",
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+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_m/niosv_m_baseline_ghrd",
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@@ -5166,6 +5166,42 @@
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             "Q_GITHUB_RELEASE": "QPDS25.1_REL_GSRD_PR",
             "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 3 FPGA - Nios® V/m Baseline Golden Hardware Reference Design (GHRD)",
+            "source": "GitHub",
+            "family": "Agilex 3",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex™ 3 FPGA C-Series 135 (M16A) A3CW135BM16AE6S",
+            "device_part": "A3CW135BM16AE6S",
+            "description": "This design demonstrates the Baseline Golden Hardware Reference Design (GHRD) for a Nios® V/m processor with basic bare minimum peripherals required for any application execution",
+            "rich_description": "<p>This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel- IO and System ID peripheral core. </p><p>The objective of the design is to accomplish data transfer between the processor and on chip memory. </p><h6>Note: The sof (binary) generation is not supported for Agilex 3 devices starting from Quartus 25.1.1 version. Hence, you will observe \"sof not generated\" critical warning while compiling this design.</h6><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex3e-nios-ed/rel/25.1.1/niosv_m/baseline_ghrd/img/baseline_ghrd_block_design.png\"/></p>",
+            "category": "GHRD",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_m/baseline_ghrd/docs/Nios_Vm_Processor_Baseline_GHRD_Design_on_Agilex_3_FPGA.md",
+            "downloadUrl": "agilex3_niosv_m_baseline_ghrd.zip",
+            "documentations": [],
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+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 3 FPGA - Nios® V/m Baseline Golden Hardware Reference Design (GHRD)",
+            "source": "GitHub",
+            "family": "Agilex 3",
+            "quartus_version": "25.1.0",
+            "devkit": "Agilex™ 3 FPGA C-Series 135 (M16A) A3CW135BM16AE6S",
+            "device_part": "A3CW135BM16AE6S",
+            "description": "This design demonstrates the Baseline Golden Hardware Reference Design (GHRD) for a Nios® V/m processor with basic bare minimum peripherals required for any application execution",
+            "rich_description": "<p>This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel- IO and System ID peripheral core. </p><p>The objective of the design is to accomplish data transfer between the processor and on chip memory. </p><h6>Note: The sof (binary) generation is not supported for Agilex 3 devices on Quartus 25.1 version. Hence, you will observe \"sof not generated\" critical warning while compiling this design.</h6><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex3e-nios-ed/rel/25.1.0/niosv_m/baseline_ghrd/img/baseline_ghrd_block_design.png\"/></p>",
+            "category": "GHRD",
+            "url": "https://github.com/altera-fpga/agilex3e-nios-ed/releases/download/25.1-v1.0/agilex3_niosv_m_baseline_ghrd.zip",
+            "downloadUrl": "agilex3_niosv_m_baseline_ghrd.zip",
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex3e-nios-ed/releases/assets/247410476",
+            "Q_GITHUB_RELEASE": "25.1.0-v1.0",
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     "force_always_regenerate": []