Auto PR: Differences detected (#30)

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catalog/list.json

@@ -4348,7 +4348,7 @@
             "device_part": "AGFB014R24B2E2V",
             "description": "Nios® V/g Processor-based custom instruction Cyclic Redundancy Check (CRC) example design on the Agilex® 7 FPGA.",
             "rich_description": "<p>A Processing Engine (PE) that performs the Cyclic Redundancy Check (CRC) algorithm is connected to the Nios® V/g processor using the custom instruction interface</p><p>The current version of the Nios® V/g processor custom instruction interface supports operations up-to 32-Bit. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_crc/img/niosv_ci_example.png\"/></p>",
-            "category": "Web Server",
+            "category": "Custom Instruction",
             "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_crc/docs/Nios_Vg_Processor_CI_CRC_Design_on_Agilex_7_FPGA.md",
             "downloadUrl": "agilex7_niosv_g_ci_crc.zip",
             "documentations": [],
@@ -4367,7 +4367,7 @@
             "device_part": "AGFB014R24B2E2V",
             "description": "Nios® V/g Processor-based custom instruction example design on the Agilex® 7 FPGA.",
             "rich_description": "<p>A Processing Engine (PE) that performs basic arithmetic and logical computations is connected to the Nios® V/g processor using the custom instruction interface. </p><p>The current version of the Nios® V/g processor custom instruction interface supports operations up-to 32-Bit. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_basic_operations/img/niosv_ci_example.png\"/></p>",
-            "category": "Custom Instruction",
+            "category": "",
             "url": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.1.1/agf014ea-dev-devkit/niosv_g/ci_basic_operations/docs/Nios_Vg_Processor_CI_Basic_Operations_Design_on_Agilex_7_FPGA.md",
             "downloadUrl": "agilex7_ci_basic_operations.zip",
             "documentations": [],
@@ -5521,7 +5521,7 @@
             "description": "This design demonstrates the Baseline Golden Hardware Reference Design (GHRD) for a Nios® V/m processor with basic bare minimum peripherals required for any application execution",
             "rich_description": "<p>This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel- IO and System ID peripheral core. </p><p>The objective of the design is to accomplish data transfer between the processor and on chip memory. </p><h6>Note: The sof (binary) generation is not supported for Agilex 3 devices starting from Quartus 25.1.1 version. Hence, you will observe \"sof not generated\" critical warning while compiling this design.</h6><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex3e-nios-ed/rel/25.1.1/niosv_m/baseline_ghrd/img/baseline_ghrd_block_design.png\"/></p>",
             "category": "GHRD",
-            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_m/baseline_ghrd/docs/Nios_Vm_Processor_Baseline_GHRD_Design_on_Agilex_3_FPGA.md",
+            "url": "https://github.com/altera-fpga/agilex3e-nios-ed/blob/rel/25.1.1/niosv_m/baseline_ghrd/docs/Nios_Vm_Processor_Baseline_GHRD_Design_on_Agilex_3_FPGA.md",
             "downloadUrl": "agilex3_niosv_m_baseline_ghrd.zip",
             "documentations": [],
             "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex3e-nios-ed/releases/assets/290820587",