From 6cdbed89b886fd5f715f225207d9a62029a422e6 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 10 Nov 2025 11:03:46 +0200 Subject: [PATCH] testbenches: Removed broken testbenches - Broken testbenches have their respective dev branch Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/data_offload_2/Makefile | 47 --- testbenches/ip/data_offload_2/cfgs/cfg0.tcl | 29 -- testbenches/ip/data_offload_2/cfgs/cfg1.tcl | 29 -- testbenches/ip/data_offload_2/cfgs/cfg2.tcl | 29 -- testbenches/ip/data_offload_2/cfgs/cfg3.tcl | 30 -- testbenches/ip/data_offload_2/cfgs/cfg4.tcl | 29 -- .../ip/data_offload_2/cfgs/cfg5_hbm.tcl | 31 -- .../data_offload_2/cfgs/cfg5_hbm_cyclic.tcl | 31 -- .../ip/data_offload_2/cfgs/common_cfg.tcl | 69 ---- .../ip/data_offload_2/data_offload_pkg.sv | 112 ----- .../ip/data_offload_2/do_scoreboard.sv | 217 ---------- testbenches/ip/data_offload_2/environment.sv | 189 --------- testbenches/ip/data_offload_2/system_bd.tcl | 243 ----------- .../ip/data_offload_2/system_project.tcl | 44 -- testbenches/ip/data_offload_2/system_tb.sv | 55 --- .../ip/data_offload_2/tests/test_program.sv | 190 --------- .../data_offload_2/tests/test_program_sync.sv | 197 --------- testbenches/ip/data_offload_2/waves/cfg0.wcfg | 288 ------------- testbenches/ip/data_offload_2/waves/cfg1.wcfg | 271 ------------ testbenches/ip/data_offload_2/waves/cfg2.wcfg | 279 ------------- testbenches/ip/data_offload_2/waves/cfg3.wcfg | 387 ------------------ testbenches/ip/data_offload_2/waves/cfg4.wcfg | 36 -- testbenches/ip/hbm/Makefile | 38 -- testbenches/ip/hbm/README.md | 27 -- testbenches/ip/hbm/cfgs/cfg1.tcl | 8 - testbenches/ip/hbm/system_bd.tcl | 161 -------- testbenches/ip/hbm/system_project.tcl | 30 -- testbenches/ip/hbm/system_tb.sv | 44 -- testbenches/ip/hbm/tests/test_program.sv | 173 -------- testbenches/ip/hbm/waves/cfg1.wcfg | 61 --- .../ad_quadmxfe1_ebz/tests/test_dma.sv | 335 --------------- .../tests/test_program_64b66b.sv | 333 --------------- 32 files changed, 4042 deletions(-) delete mode 100644 testbenches/ip/data_offload_2/Makefile delete mode 100644 testbenches/ip/data_offload_2/cfgs/cfg0.tcl delete mode 100644 testbenches/ip/data_offload_2/cfgs/cfg1.tcl delete mode 100644 testbenches/ip/data_offload_2/cfgs/cfg2.tcl delete mode 100644 testbenches/ip/data_offload_2/cfgs/cfg3.tcl delete mode 100644 testbenches/ip/data_offload_2/cfgs/cfg4.tcl delete mode 100644 testbenches/ip/data_offload_2/cfgs/cfg5_hbm.tcl delete mode 100644 testbenches/ip/data_offload_2/cfgs/cfg5_hbm_cyclic.tcl delete mode 100644 testbenches/ip/data_offload_2/cfgs/common_cfg.tcl delete mode 100644 testbenches/ip/data_offload_2/data_offload_pkg.sv delete mode 100644 testbenches/ip/data_offload_2/do_scoreboard.sv delete mode 100644 testbenches/ip/data_offload_2/environment.sv delete mode 100644 testbenches/ip/data_offload_2/system_bd.tcl delete mode 100644 testbenches/ip/data_offload_2/system_project.tcl delete mode 100644 testbenches/ip/data_offload_2/system_tb.sv delete mode 100644 testbenches/ip/data_offload_2/tests/test_program.sv delete mode 100644 testbenches/ip/data_offload_2/tests/test_program_sync.sv delete mode 100644 testbenches/ip/data_offload_2/waves/cfg0.wcfg delete mode 100644 testbenches/ip/data_offload_2/waves/cfg1.wcfg delete mode 100644 testbenches/ip/data_offload_2/waves/cfg2.wcfg delete mode 100644 testbenches/ip/data_offload_2/waves/cfg3.wcfg delete mode 100644 testbenches/ip/data_offload_2/waves/cfg4.wcfg delete mode 100644 testbenches/ip/hbm/Makefile delete mode 100644 testbenches/ip/hbm/README.md delete mode 100644 testbenches/ip/hbm/cfgs/cfg1.tcl delete mode 100644 testbenches/ip/hbm/system_bd.tcl delete mode 100644 testbenches/ip/hbm/system_project.tcl delete mode 100644 testbenches/ip/hbm/system_tb.sv delete mode 100644 testbenches/ip/hbm/tests/test_program.sv delete mode 100644 testbenches/ip/hbm/waves/cfg1.wcfg delete mode 100644 testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv delete mode 100644 testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv diff --git a/testbenches/ip/data_offload_2/Makefile b/testbenches/ip/data_offload_2/Makefile deleted file mode 100644 index 9b6d87416..000000000 --- a/testbenches/ip/data_offload_2/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -#################################################################################### -#################################################################################### -## Copyright (C) 2021 Analog Devices, Inc. -#################################################################################### -#################################################################################### - -# Makeincludes -include ../../../scripts/make_tb_path.mk -include $(ADI_TB_DIR)/library/includes/Makeinclude_axis.mk - -# Remaining test-bench dependencies except test programs -SV_DEPS += do_scoreboard.sv -SV_DEPS += environment.sv -SV_DEPS += data_offload_pkg.sv - -ENV_DEPS += cfgs/common_cfg.tcl - -LIB_DEPS := util_cdc -LIB_DEPS += util_axis_fifo -LIB_DEPS += util_do_ram -LIB_DEPS += axi_dmac -LIB_DEPS += data_offload -LIB_DEPS += util_hbm - -# list of test programs -TP := $(notdir $(basename $(wildcard tests/*.sv))) - -# config files should have the following format -# cfg__.tcl -CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) - -# List of tests and configuration combinations that has to be run -# Format is: : -TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP))) - -include $(ADI_TB_DIR)/scripts/project-sim.mk - -# usage: -# -# run specific test on a specific configuration in gui mode -# make CFG= TST= MODE=gui -# -# run all test from a configuration -# make - -#################################################################################### -#################################################################################### diff --git a/testbenches/ip/data_offload_2/cfgs/cfg0.tcl b/testbenches/ip/data_offload_2/cfgs/cfg0.tcl deleted file mode 100644 index 85f0f15b2..000000000 --- a/testbenches/ip/data_offload_2/cfgs/cfg0.tcl +++ /dev/null @@ -1,29 +0,0 @@ -# TX / oneshot -global ad_project_params - -set ad_project_params(DATA_PATH_WIDTH) 16 ; ## 16 bytes - -set ad_project_params(MEM_TYPE) 0 ; ## Internal storage (BRAM) -set ad_project_params(PATH_TYPE) 1 ; ## TX -set ad_project_params(OFFLOAD_SIZE) 1024 ; ## 1 KiB -set ad_project_params(OFFLOAD_SRC_DWIDTH) 128 ; ## Source data width -set ad_project_params(OFFLOAD_DST_DWIDTH) 128 ; ## Destination data width -set ad_project_params(OFFLOAD_ONESHOT) 1 ; ## Enable oneshot mode - -set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 512 ; ## PLDDR's AXI4 interface data width - -set ad_project_params(SRC_CLOCK_FREQ) 250000000 ; ## Source clock frequency in Hz -set ad_project_params(DST_CLOCK_FREQ) 300000000 ; ## Destination clock frequency in Hz - -set ad_project_params(SRC_TRANSFERS_INITIAL_COUNT) 20 ; ## Count of transfers initially queued up. - ; ## These will be transferred back to back -set ad_project_params(SRC_TRANSFERS_LENGTH) 512 ; ## Transfer length -set ad_project_params(SRC_TRANSFERS_DELAY) 10000 ; ## Delay in ns before the next batch is queued -set ad_project_params(SRC_TRANSFERS_DELAYED_COUNT) 1 ; ## Count of transfers queued in second batch - -set ad_project_params(DST_READY_MODE) XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE -set ad_project_params(DST_READY_HIGH) 1 -set ad_project_params(DST_READY_LOW) 3 - -set ad_project_params(TIME_TO_WAIT) 1500 ; ## Delay after queuing the second batch - ; ## before exiting the simulation diff --git a/testbenches/ip/data_offload_2/cfgs/cfg1.tcl b/testbenches/ip/data_offload_2/cfgs/cfg1.tcl deleted file mode 100644 index 13e02e94f..000000000 --- a/testbenches/ip/data_offload_2/cfgs/cfg1.tcl +++ /dev/null @@ -1,29 +0,0 @@ -# TX / oneshot / oscillating ready -global ad_project_params - -set ad_project_params(DATA_PATH_WIDTH) 16 ; ## 16 bytes - -set ad_project_params(MEM_TYPE) 0 ; ## Internal storage (BRAM) -set ad_project_params(PATH_TYPE) 1 ; ## TX -set ad_project_params(OFFLOAD_SIZE) 1024 ; ## 1 KiB -set ad_project_params(OFFLOAD_SRC_DWIDTH) 128 ; ## Source data width -set ad_project_params(OFFLOAD_DST_DWIDTH) 128 ; ## Destination data width -set ad_project_params(OFFLOAD_ONESHOT) 1 ; ## Enable oneshot mode - -set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 512 ; ## PLDDR's AXI4 interface data width - -set ad_project_params(SRC_CLOCK_FREQ) 250000000 ; ## Source clock frequency in Hz -set ad_project_params(DST_CLOCK_FREQ) 300000000 ; ## Destination clock frequency in Hz - -set ad_project_params(SRC_TRANSFERS_INITIAL_COUNT) 20 ; ## Count of transfers initially queued up. - ; ## These will be transferred back to back -set ad_project_params(SRC_TRANSFERS_LENGTH) 512 ; ## Transfer length -set ad_project_params(SRC_TRANSFERS_DELAY) 20000 ; ## Delay in ns before the next batch is queued -set ad_project_params(SRC_TRANSFERS_DELAYED_COUNT) 1 ; ## Count of transfers queued in second batch - -set ad_project_params(DST_READY_MODE) XIL_AXI4STREAM_READY_GEN_OSC -set ad_project_params(DST_READY_HIGH) 1 -set ad_project_params(DST_READY_LOW) 3 - -set ad_project_params(TIME_TO_WAIT) 10000 ; ## Delay after queuing the second batch - ; ## before exiting the simulation diff --git a/testbenches/ip/data_offload_2/cfgs/cfg2.tcl b/testbenches/ip/data_offload_2/cfgs/cfg2.tcl deleted file mode 100644 index 2fe7c7703..000000000 --- a/testbenches/ip/data_offload_2/cfgs/cfg2.tcl +++ /dev/null @@ -1,29 +0,0 @@ -# TX / cyclic -global ad_project_params - -set ad_project_params(DATA_PATH_WIDTH) 16 ; ## 16 bytes - -set ad_project_params(MEM_TYPE) 0 ; ## Internal storage (BRAM) -set ad_project_params(PATH_TYPE) 1 ; ## TX -set ad_project_params(OFFLOAD_SIZE) 1024 ; ## 1 KiB -set ad_project_params(OFFLOAD_SRC_DWIDTH) 128 ; ## Source data width -set ad_project_params(OFFLOAD_DST_DWIDTH) 128 ; ## Destination data width -set ad_project_params(OFFLOAD_ONESHOT) 0 ; ## Enable cyclic mode - -set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 512 ; ## PLDDR's AXI4 interface data width - -set ad_project_params(SRC_CLOCK_FREQ) 250000000 ; ## Source clock frequency in Hz -set ad_project_params(DST_CLOCK_FREQ) 300000000 ; ## Destination clock frequency in Hz - -set ad_project_params(SRC_TRANSFERS_INITIAL_COUNT) 1 ; ## Count of transfers initially queued up. - ; ## These will be transferred back to back -set ad_project_params(SRC_TRANSFERS_LENGTH) 512 ; ## Transfer length -set ad_project_params(SRC_TRANSFERS_DELAY) 10000 ; ## Delay in ns before the next batch is queued -set ad_project_params(SRC_TRANSFERS_DELAYED_COUNT) 1 ; ## Count of transfers queued in second batch - -set ad_project_params(DST_READY_MODE) XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE -set ad_project_params(DST_READY_HIGH) 1 -set ad_project_params(DST_READY_LOW) 3 - -set ad_project_params(TIME_TO_WAIT) 1500 ; ## Delay after queuing the second batch - ; ## before exiting the simulation diff --git a/testbenches/ip/data_offload_2/cfgs/cfg3.tcl b/testbenches/ip/data_offload_2/cfgs/cfg3.tcl deleted file mode 100644 index 75cb07828..000000000 --- a/testbenches/ip/data_offload_2/cfgs/cfg3.tcl +++ /dev/null @@ -1,30 +0,0 @@ -# RX / 50% transfer length -global ad_project_params - -set ad_project_params(DATA_PATH_WIDTH) 16 ; ## 16 bytes - -set ad_project_params(MEM_TYPE) 0 ; ## Internal storage (BRAM) -set ad_project_params(PATH_TYPE) 0 ; ## RX -set ad_project_params(OFFLOAD_SIZE) 1024 ; ## 1 KiB -set ad_project_params(OFFLOAD_TRANSFER_LENGTH) 512 ; ## 512 bytes -set ad_project_params(OFFLOAD_SRC_DWIDTH) 128 ; ## Source data width -set ad_project_params(OFFLOAD_DST_DWIDTH) 128 ; ## Destination data width -set ad_project_params(OFFLOAD_ONESHOT) 1 ; ## Enable oneshot mode - -set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 512 ; ## PLDDR's AXI4 interface data width - -set ad_project_params(SRC_CLOCK_FREQ) 250000000 ; ## Source clock frequency in Hz -set ad_project_params(DST_CLOCK_FREQ) 300000000 ; ## Destination clock frequency in Hz - -set ad_project_params(SRC_TRANSFERS_INITIAL_COUNT) 2 ; ## Count of transfers initially queued up. - ; ## These will be transferred back to back -set ad_project_params(SRC_TRANSFERS_LENGTH) 1048576 ; ## Transfer length -set ad_project_params(SRC_TRANSFERS_DELAY) 10000 ; ## Delay in ns before the next batch is queued -set ad_project_params(SRC_TRANSFERS_DELAYED_COUNT) 1 ; ## Count of transfers queued in second batch - -set ad_project_params(DST_READY_MODE) XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE -set ad_project_params(DST_READY_HIGH) 1 -set ad_project_params(DST_READY_LOW) 0 - -set ad_project_params(TIME_TO_WAIT) 1500 ; ## Delay after queuing the second batch - ; ## before exiting the simulation diff --git a/testbenches/ip/data_offload_2/cfgs/cfg4.tcl b/testbenches/ip/data_offload_2/cfgs/cfg4.tcl deleted file mode 100644 index f3089964a..000000000 --- a/testbenches/ip/data_offload_2/cfgs/cfg4.tcl +++ /dev/null @@ -1,29 +0,0 @@ -# TX / oneshot / 100% transfer length -global ad_project_params - -set ad_project_params(DATA_PATH_WIDTH) 16 ; ## 16 bytes - -set ad_project_params(MEM_TYPE) 0 ; ## Internal storage (BRAM) -set ad_project_params(PATH_TYPE) 1 ; ## TX -set ad_project_params(OFFLOAD_SIZE) 1024 ; ## 1 KiB -set ad_project_params(OFFLOAD_SRC_DWIDTH) 128 ; ## Source data width -set ad_project_params(OFFLOAD_DST_DWIDTH) 128 ; ## Destination data width -set ad_project_params(OFFLOAD_ONESHOT) 1 ; ## Enable oneshot mode - -set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 512 ; ## PLDDR's AXI4 interface data width - -set ad_project_params(SRC_CLOCK_FREQ) 250000000 ; ## Source clock frequency in Hz -set ad_project_params(DST_CLOCK_FREQ) 300000000 ; ## Destination clock frequency in Hz - -set ad_project_params(SRC_TRANSFERS_INITIAL_COUNT) 20 ; ## Count of transfers initially queued up. - ; ## These will be transferred back to back -set ad_project_params(SRC_TRANSFERS_LENGTH) 1024 ; ## Transfer length -set ad_project_params(SRC_TRANSFERS_DELAY) 10000 ; ## Delay in ns before the next batch is queued -set ad_project_params(SRC_TRANSFERS_DELAYED_COUNT) 1 ; ## Count of transfers queued in second batch - -set ad_project_params(DST_READY_MODE) XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE -set ad_project_params(DST_READY_HIGH) 1 -set ad_project_params(DST_READY_LOW) 0 - -set ad_project_params(TIME_TO_WAIT) 1500 ; ## Delay after queuing the second batch - ; ## before exiting the simulation diff --git a/testbenches/ip/data_offload_2/cfgs/cfg5_hbm.tcl b/testbenches/ip/data_offload_2/cfgs/cfg5_hbm.tcl deleted file mode 100644 index fd3384b29..000000000 --- a/testbenches/ip/data_offload_2/cfgs/cfg5_hbm.tcl +++ /dev/null @@ -1,31 +0,0 @@ -# TX / oneshot -global ad_project_params - -set ad_project_params(DATA_PATH_WIDTH) 16 ; ## 16 bytes - -set ad_project_params(MEM_TYPE) 2 ; ## External storage (HBM) -set ad_project_params(PATH_TYPE) 1 ; ## TX -set ad_project_params(OFFLOAD_SIZE) [expr 4*256*1024*1024] ; ## 4 segments of 256MB -set ad_project_params(OFFLOAD_SRC_DWIDTH) 1024 ; ## Source data width -set ad_project_params(OFFLOAD_DST_DWIDTH) 1024 ; ## Destination data width -set ad_project_params(OFFLOAD_ONESHOT) 1 ; ## Enable oneshot mode - -set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 256 ; ## HBM's AXI3 interface data width - -set ad_project_params(SRC_CLOCK_FREQ) 250000000 ; ## Source clock frequency in Hz -set ad_project_params(DST_CLOCK_FREQ) 300000000 ; ## Destination clock frequency in Hz - -set ad_project_params(SRC_TRANSFERS_INITIAL_COUNT) 20 ; ## Count of transfers initially queued up. - ; ## These will be transferred back to back -set ad_project_params(SRC_TRANSFERS_LENGTH) 512 ; ## Transfer length -set ad_project_params(SRC_TRANSFERS_DELAY) 10000 ; ## Delay in ns before the next batch is queued -set ad_project_params(SRC_TRANSFERS_DELAYED_COUNT) 1 ; ## Count of transfers queued in second batch - -set ad_project_params(DST_READY_MODE) XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE -set ad_project_params(DST_READY_HIGH) 1 -set ad_project_params(DST_READY_LOW) 3 - -set ad_project_params(TIME_TO_WAIT) 40000 ; ## Delay after queuing the second batch - ; ## before exiting the simulation - -set ad_project_params(OFFLOAD_TRANSFER_LENGTH) 4096 diff --git a/testbenches/ip/data_offload_2/cfgs/cfg5_hbm_cyclic.tcl b/testbenches/ip/data_offload_2/cfgs/cfg5_hbm_cyclic.tcl deleted file mode 100644 index 5e765218f..000000000 --- a/testbenches/ip/data_offload_2/cfgs/cfg5_hbm_cyclic.tcl +++ /dev/null @@ -1,31 +0,0 @@ -# TX / oneshot -global ad_project_params - -set ad_project_params(DATA_PATH_WIDTH) 16 ; ## 16 bytes - -set ad_project_params(MEM_TYPE) 2 ; ## External storage (HBM) -set ad_project_params(PATH_TYPE) 1 ; ## TX -set ad_project_params(OFFLOAD_SIZE) [expr 4*256*1024*1024] ; ## 4 segments of 256MB -set ad_project_params(OFFLOAD_SRC_DWIDTH) 1024 ; ## Source data width -set ad_project_params(OFFLOAD_DST_DWIDTH) 1024 ; ## Destination data width -set ad_project_params(OFFLOAD_ONESHOT) 0 ; ## Enable oneshot mode - -set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 256 ; ## PLDDR's AXI4 interface data width - -set ad_project_params(SRC_CLOCK_FREQ) 250000000 ; ## Source clock frequency in Hz -set ad_project_params(DST_CLOCK_FREQ) 300000000 ; ## Destination clock frequency in Hz - -set ad_project_params(SRC_TRANSFERS_INITIAL_COUNT) 20 ; ## Count of transfers initially queued up. - ; ## These will be transferred back to back -set ad_project_params(SRC_TRANSFERS_LENGTH) 512 ; ## Transfer length -set ad_project_params(SRC_TRANSFERS_DELAY) 10000 ; ## Delay in ns before the next batch is queued -set ad_project_params(SRC_TRANSFERS_DELAYED_COUNT) 1 ; ## Count of transfers queued in second batch - -set ad_project_params(DST_READY_MODE) XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE -set ad_project_params(DST_READY_HIGH) 1 -set ad_project_params(DST_READY_LOW) 3 - -set ad_project_params(TIME_TO_WAIT) 40000 ; ## Delay after queuing the second batch - ; ## before exiting the simulation - -set ad_project_params(OFFLOAD_TRANSFER_LENGTH) 4096 diff --git a/testbenches/ip/data_offload_2/cfgs/common_cfg.tcl b/testbenches/ip/data_offload_2/cfgs/common_cfg.tcl deleted file mode 100644 index ebd94059d..000000000 --- a/testbenches/ip/data_offload_2/cfgs/common_cfg.tcl +++ /dev/null @@ -1,69 +0,0 @@ -# Common setting, these can be overwritten in test specific config files - -# all clocks, user can overwrite these values in the test configuration files (e.g. cfg1/tcl) - -set src_clk_cfg [list \ - CONFIG.FREQ_HZ {250000000} -] - -set dst_clk_cfg [list \ - CONFIG.FREQ_HZ {250000000} -] - -set sys_clk_cfg [list \ - CONFIG.FREQ_HZ {100000000} -] - -set ddr_clk_cfg [list \ - CONFIG.FREQ_HZ {200000000} -] - -# axi lite management port -set mng_axi_vip_cfg [ list \ - CONFIG.ADDR_WIDTH {32} \ - CONFIG.ARUSER_WIDTH {0} \ - CONFIG.AWUSER_WIDTH {0} \ - CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {32} \ - CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {0} \ - CONFIG.HAS_CACHE {0} \ - CONFIG.HAS_LOCK {0} \ - CONFIG.HAS_PROT {1} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {1} \ - CONFIG.ID_WIDTH {0} \ - CONFIG.INTERFACE_MODE {MASTER} \ - CONFIG.PROTOCOL {AXI4LITE} \ - CONFIG.READ_WRITE_MODE {READ_WRITE} \ - CONFIG.RUSER_BITS_PER_BYTE {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.SUPPORTS_NARROW {0} \ - CONFIG.WUSER_BITS_PER_BYTE {0} \ - CONFIG.WUSER_WIDTH {0} \ -] - -# Device side VIPs - -set dst_s_axis_vip_cfg [ list \ - CONFIG.INTERFACE_MODE {SLAVE} \ -] - -set src_pt_axis_vip_cfg [ list \ - CONFIG.INTERFACE_MODE {PASS_THROUGH} \ -] - -set src_m_axis_vip_cfg [list \ - CONFIG.INTERFACE_MODE {MASTER} \ - CONFIG.HAS_TREADY {1} \ - CONFIG.HAS_TLAST {0} \ -] - -set dst_pt_axis_vip_cfg [list \ - CONFIG.INTERFACE_MODE {PASS_THROUGH} \ - CONFIG.HAS_TREADY {1} \ - CONFIG.HAS_TLAST {0} \ -] - diff --git a/testbenches/ip/data_offload_2/data_offload_pkg.sv b/testbenches/ip/data_offload_2/data_offload_pkg.sv deleted file mode 100644 index b92e646b9..000000000 --- a/testbenches/ip/data_offload_2/data_offload_pkg.sv +++ /dev/null @@ -1,112 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - - -`include "utils.svh" - -`define DO_ADDR_VERSION 32'h00000 -`define DO_ADDR_ID 32'h00004 -`define DO_ADDR_SCRATCH 32'h00008 -`define DO_ADDR_MAGIC 32'h0000C -`define DO_ADDR_MEM_TYPE 32'h00010 -`define DO_ADDR_MEM_SIZE_LSB 32'h00014 -`define DO_ADDR_MEM_SIZE_MSB 32'h00018 -`define DO_ADDR_TRANSFER_LENGTH 32'h0001C -`define DO_ADDR_DDR_CALIB_DONE 32'h00080 -`define DO_ADDR_CONTROL_1 32'h00084 -`define DO_ADDR_CONTROL_2 32'h00088 -`define DO_ADDR_SYNC 32'h00100 -`define DO_ADDR_SYNC_CONFIG 32'h00104 -`define DO_ADDR_DBG_FSM 32'h00200 -`define DO_ADDR_DBG_SMP_LSB_COUNTER 32'h00204 -`define DO_ADDR_DBG_SMP_MSB_COUNTER 32'h00208 - -`define DO_CORE_VERSION 32'h00000100 -`define DO_CORE_MAGIC 32'h44414F46 - -package data_offload_pkg; - - import axi_vip_pkg::*; - import m_axi_sequencer_pkg::*; - import logger_pkg::*; - - class data_offload; - m_axi_sequencer_base bus; - xil_axi_ulong base_address; - - bit [1:0] reg_control; - - function new (m_axi_sequencer_base bus, xil_axi_ulong base_address); - this.bus = bus; - this.base_address = base_address; - endfunction - - task set_oneshot(input bit oneshot); - this.reg_control[1] = oneshot; - this.bus.RegWrite32(this.base_address + `DO_ADDR_CONTROL_2, {30'b0, this.reg_control}); - endtask : set_oneshot; - - task set_bypass(input bit bypass); - this.reg_control[0] = bypass; - this.bus.RegWrite32(this.base_address + `DO_ADDR_CONTROL_2, {30'b0, this.reg_control}); - endtask : set_bypass; - - task set_resetn(input bit resetn); - this.bus.RegWrite32(this.base_address + `DO_ADDR_CONTROL_1, {31'b0, resetn}); - endtask : set_resetn; - - task set_transfer_length(input bit [33:0] length); - if (length & 34'h3f) begin - // Transfer length not divisble by 64 - `FATAL(("data_offload: Attempted to set transfer_length %x mod 64 != 0!", length)); - end - `INFO(("data_offload: Writing transfer length! %x", length), ADI_VERBOSITY_LOW); - this.bus.RegWrite32(this.base_address + `DO_ADDR_TRANSFER_LENGTH, length >> 6); - endtask : set_transfer_length; - - task set_sync_config(input bit [1:0] sync_config); - if (sync_config == 3) - `FATAL(("data_offload: Invalid sync_config mode 3 requested!")); - - this.bus.RegWrite32(this.base_address + `DO_ADDR_SYNC_CONFIG, {30'h0, sync_config}); - endtask : set_sync_config; - - task trigger_sync(); - this.bus.RegWrite32(this.base_address + `DO_ADDR_SYNC_CONFIG, 32'h1); - endtask : trigger_sync; - - endclass - -endpackage diff --git a/testbenches/ip/data_offload_2/do_scoreboard.sv b/testbenches/ip/data_offload_2/do_scoreboard.sv deleted file mode 100644 index e00640c87..000000000 --- a/testbenches/ip/data_offload_2/do_scoreboard.sv +++ /dev/null @@ -1,217 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2021 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - - -`include "utils.svh" - -package do_scoreboard_pkg; - - import xil_common_vip_pkg::*; - import axi4stream_vip_pkg::*; - import axi_vip_pkg::*; - import logger_pkg::*; - - class do_scoreboard extends xil_component; - - typedef enum bit { CYCLIC=0, ONESHOT } do_mode_t; - do_mode_t do_mode; - - typedef enum bit { RX=0, TX } path_type_t; - path_type_t path_type; - - bit reading = 1'b0; - semaphore reading_lock; - - // List of analysis ports from the monitors - xil_analysis_port #(axi4stream_monitor_transaction) src_axis_ap; - xil_analysis_port #(axi4stream_monitor_transaction) dst_axis_ap; - - // transaction queues (because the source and sink interface can have - // different widths, byte streams are used) - logic [7:0] byte_stream [$]; - - int transfer_size; - - // counters and synchronizers - bit enabled; - event end_of_first_cycle; - - // constructor - function new(input string name); - super.new(name); - this.enabled = 0; - - this.do_mode = CYCLIC; - this.path_type = RX; - this.transfer_size = 0; - - reading_lock = new(1); - endfunction /* new */ - - // connect the analysis ports of the monitor to the scoreboard - function void set_ports( - xil_analysis_port #(axi4stream_monitor_transaction) src_axis_ap, - xil_analysis_port #(axi4stream_monitor_transaction) dst_axis_ap); - this.src_axis_ap = src_axis_ap; - this.dst_axis_ap = dst_axis_ap; - endfunction /* set_ports */ - - // run task - task run(); - if (this.path_type == TX) begin - fork - this.enabled = 1; - get_src_transaction(); - get_dst_transaction(); - join_none - end - endtask /* run */ - - function void set_oneshot(input bit do_mode); - if (!this.enabled) begin - this.do_mode = do_mode_t'(do_mode); - end else begin - `FATAL(("ERROR Scoreboard: Can not configure oneshot mode while scoreboard is running.")); - end - endfunction - - function void set_path_type(input bit path_type); - if (!this.enabled) begin - this.path_type = path_type_t'(path_type); - end else begin - `FATAL(("ERROR Scoreboard: Can not configure path type while scoreboard is running!")); - end - endfunction - - function bit get_oneshot(); - return this.do_mode; - endfunction - - function bit get_path_type(); - return this.path_type; - endfunction - - task get_src_transaction(); - - axi4stream_transaction transaction; - xil_axi4stream_data_beat data_beat; - int num_bytes; - - forever begin - if (this.src_axis_ap.get_item_cnt() > 0) begin - `INFO(("Caught a TX AXI4 stream transaction: %d", this.src_axis_ap.get_item_cnt()), ADI_VERBOSITY_LOW); - this.src_axis_ap.get(transaction); - // all bytes from a beat are valid - num_bytes = transaction.get_data_width()/8; - data_beat = transaction.get_data_beat(); - - reading_lock.get(); - - if (reading == 1 && this.do_mode == CYCLIC) - this.byte_stream.delete(); - - reading = 0; - reading_lock.put(); - - for (int j=0; j 0) begin - `INFO(("Caught a RX AXI4 stream transaction: %d", this.dst_axis_ap.get_item_cnt()), ADI_VERBOSITY_LOW); - this.dst_axis_ap.get(transaction); - // all bytes from a beat are valid - num_bytes = transaction.get_data_width()/8; - data_beat = transaction.get_data_beat(); - - reading_lock.get(); - reading = 1; - reading_lock.put(); - - if (this.byte_stream.size() == 0) begin - `FATAL(("ERROR: Received unexpected transfer - is the data_offload running cyclically?")); - continue; - end - - for (int j=0; j 0) begin - `FATAL(("ERROR: Not all samples have arrived yet!")); - end else begin - `INFO(("Scoreboard passed!"), ADI_VERBOSITY_LOW); - end - end - endfunction /* post_tx_test */ - - endclass - -endpackage diff --git a/testbenches/ip/data_offload_2/environment.sv b/testbenches/ip/data_offload_2/environment.sv deleted file mode 100644 index c2eae4d85..000000000 --- a/testbenches/ip/data_offload_2/environment.sv +++ /dev/null @@ -1,189 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2021 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - - -`include "utils.svh" - -package environment_pkg; - - import m_axi_sequencer_pkg::*; - import m_axis_sequencer_pkg::*; - import s_axis_sequencer_pkg::*; - import do_scoreboard_pkg::*; - - import logger_pkg::*; - - import axi_vip_pkg::*; - import axi4stream_vip_pkg::*; - import `PKGIFY(test_harness, mng_axi)::*; - import `PKGIFY(test_harness, src_axis)::*; - import `PKGIFY(test_harness, dst_axis)::*; - - class environment; - - // agents and sequencers - `AGENT(test_harness, mng_axi, mst_t) mng_agent; - `AGENT(test_harness, src_axis, mst_t) src_axis_agent; - `AGENT(test_harness, dst_axis, slv_t) dst_axis_agent; - - m_axi_sequencer #(`AGENT(test_harness, mng_axi, mst_t)) mng; - m_axis_sequencer #(`AGENT(test_harness, src_axis, mst_t), - `AXIS_VIP_PARAMS(test_harness, src_axis) - ) src_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, dst_axis, slv_t)) dst_axis_seq; - - do_scoreboard scoreboard; - - //============================================================================ - // Constructor - //============================================================================ - function new ( - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi)) mng_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, src_axis)) src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, dst_axis)) dst_axis_vip_if - ); - - // creating the agents - mng_agent = new("AXI Manager Agent", mng_vip_if); - src_axis_agent = new("Source AXI Stream Agent", src_axis_vip_if); - dst_axis_agent = new("Destination AXI Stream Agent", dst_axis_vip_if); - - // create sequencers - mng = new("AXI Manager Sequencer", mng_agent); - src_axis_seq = new("Source AXI Stream Sequencer", src_axis_agent); - dst_axis_seq = new("Destination AXI Stream Sequencer", dst_axis_agent); - - scoreboard = new("do_scoreboard"); - - endfunction - - //============================================================================ - // Start environment - // - Connect all the agents to the scoreboard - // - Start the agents - //============================================================================ - task start(); - - // start agents, one by one - mng_agent.start_master(); - src_axis_agent.start_master(); - dst_axis_agent.start_slave(); - - scoreboard.set_ports(src_axis_agent.monitor.item_collected_port, - dst_axis_agent.monitor.item_collected_port); - - - endtask - - //============================================================================ - // Start the test - // - start the RX scoreboard and sequencer - // - start the TX scoreboard and sequencer - // - setup the RX DMA - // - setup the TX DMA - //============================================================================ - task test(); - fork - - src_axis_seq.run(); - dst_axis_seq.run(); - - scoreboard.run(); - - // adc_stream_gen(); - - join_none - endtask - - - //============================================================================ - // Generate a data stream as an ADC - // - // - clock to data rate ratio is 1 - // - //============================================================================ - - axi4stream_transaction rx_transaction; - int data_rate_ratio = 1; - - task adc_stream_gen(); - - forever begin - if (src_axis_agent.driver.is_driver_idle) begin - rx_transaction = src_axis_agent.driver.create_transaction(""); - TRANSACTION_FAIL: assert(rx_transaction.randomize()); - rx_transaction.set_delay(data_rate_ratio - 1); - src_axis_agent.driver.send(rx_transaction); - `INFO(("Sent new transaction to ADC driver"), ADI_VERBOSITY_LOW); - #0ps; - end else begin - #1step; - end - end - - endtask - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - // Evaluate the scoreboard's results - fork - scoreboard.post_test(); - join - endtask - - //============================================================================ - // Run subroutine - //============================================================================ - task run; - //pre_test(); - test(); - endtask - - //============================================================================ - // Stop subroutine - //============================================================================ - task stop; - src_axis_seq.stop(); - src_axis_agent.stop_master(); - dst_axis_agent.stop_slave(); - mng_agent.stop_master(); - post_test(); - endtask - - endclass - -endpackage diff --git a/testbenches/ip/data_offload_2/system_bd.tcl b/testbenches/ip/data_offload_2/system_bd.tcl deleted file mode 100644 index 63249fe8a..000000000 --- a/testbenches/ip/data_offload_2/system_bd.tcl +++ /dev/null @@ -1,243 +0,0 @@ -global ad_project_params - -source "$ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl" - -## DUT configuration - -set data_path_width $ad_project_params(DATA_PATH_WIDTH) - -set path_type $ad_project_params(PATH_TYPE) -set offload_mem_type $ad_project_params(MEM_TYPE) -set offload_size $ad_project_params(OFFLOAD_SIZE) -set offload_src_dwidth $ad_project_params(OFFLOAD_SRC_DWIDTH) -set offload_dst_dwidth $ad_project_params(OFFLOAD_DST_DWIDTH) -set offload_oneshot $ad_project_params(OFFLOAD_ONESHOT) - -set ext_mem_axi_data_width $ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) - -set src_clock_freq $ad_project_params(SRC_CLOCK_FREQ) -set dst_clock_freq $ad_project_params(DST_CLOCK_FREQ) -set mem_clock_freq 300000000 - -set dst_ready_mode $ad_project_params(DST_READY_MODE) -set dst_ready_high $ad_project_params(DST_READY_HIGH) -set dst_ready_low $ad_project_params(DST_READY_LOW) - -set src_transfers_initial_count $ad_project_params(SRC_TRANSFERS_INITIAL_COUNT) -set src_transfers_length $ad_project_params(SRC_TRANSFERS_LENGTH) -set src_transfers_delay $ad_project_params(SRC_TRANSFERS_DELAY) -set src_transfers_delayed_count $ad_project_params(SRC_TRANSFERS_DELAYED_COUNT) - -set time_to_wait $ad_project_params(TIME_TO_WAIT) - -## Define passthrough - -if {[info exists ad_project_params(OFFLOAD_TRANSFER_LENGTH)]} { - set offload_transfer_length $ad_project_params(OFFLOAD_TRANSFER_LENGTH) - adi_sim_add_define "OFFLOAD_TRANSFER_LENGTH=$offload_transfer_length" -} -adi_sim_add_define "OFFLOAD_PATH_TYPE=$path_type" -adi_sim_add_define "DST_READY_MODE=$dst_ready_mode" -adi_sim_add_define "DST_READY_HIGH=$dst_ready_high" -adi_sim_add_define "DST_READY_LOW=$dst_ready_low" -adi_sim_add_define "SRC_TRANSFERS_INITIAL_COUNT=$src_transfers_initial_count" -adi_sim_add_define "SRC_TRANSFERS_LENGTH=$src_transfers_length" -adi_sim_add_define "SRC_TRANSFERS_DELAY=$src_transfers_delay" -adi_sim_add_define "SRC_TRANSFERS_DELAYED_COUNT=$src_transfers_delayed_count" -adi_sim_add_define "TIME_TO_WAIT=$time_to_wait" -adi_sim_add_define "OFFLOAD_ONESHOT=$offload_oneshot" - -################################################################################ -# Create interface ports -- clocks and resets -################################################################################ - -# system clock/reset - -ad_ip_instance clk_vip sys_clk_vip -adi_sim_add_define "SYS_CLK=sys_clk_vip" -ad_ip_parameter sys_clk_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter sys_clk_vip CONFIG.FREQ_HZ {100000000} - -ad_ip_instance rst_vip sys_rst_vip -adi_sim_add_define "SYS_RST=sys_rst_vip" -ad_ip_parameter sys_rst_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter sys_rst_vip CONFIG.RST_POLARITY {ACTIVE_LOW} -ad_ip_parameter sys_rst_vip CONFIG.ASYNCHRONOUS {NO} - -ad_connect sys_clk_vip/clk_out sys_rst_vip/sync_clk - -################################################################################ -# DUTs - Data Offload and its DMA's -################################################################################ - -ad_data_offload_create DUT \ - $path_type \ - $offload_mem_type \ - $offload_size \ - $offload_src_dwidth \ - $offload_dst_dwidth \ - $ext_mem_axi_data_width \ - - -create_bd_port -dir I -type data init_req -ad_connect init_req DUT/init_req - -create_bd_port -dir I -type data sync_ext -ad_connect sync_ext DUT/sync_ext - -################################################################################ -# mng_axi - AXI4 VIP for configuration -################################################################################ - -ad_ip_instance axi_vip mng_axi -adi_sim_add_define "MNG_AXI=mng_axi" -set_property -dict [list CONFIG.ADDR_WIDTH {32} \ - CONFIG.ARUSER_WIDTH {0} \ - CONFIG.AWUSER_WIDTH {0} \ - CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {32} \ - CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {0} \ - CONFIG.HAS_CACHE {0} \ - CONFIG.HAS_LOCK {0} \ - CONFIG.HAS_PROT {1} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {1} \ - CONFIG.ID_WIDTH {0} \ - CONFIG.INTERFACE_MODE {MASTER} \ - CONFIG.PROTOCOL {AXI4LITE} \ - CONFIG.READ_WRITE_MODE {READ_WRITE} \ - CONFIG.RUSER_BITS_PER_BYTE {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.SUPPORTS_NARROW {0} \ - CONFIG.WUSER_BITS_PER_BYTE {0} \ - CONFIG.WUSER_WIDTH {0}] [get_bd_cells mng_axi] - -# Connect AXI VIP to DUT - -ad_connect DUT/s_axi mng_axi/M_AXI - -ad_connect sys_clk_vip/clk_out DUT/s_axi_aclk -ad_connect sys_clk_vip/clk_out mng_axi/aclk - -ad_connect sys_rst_vip/rst_out DUT/s_axi_aresetn -ad_connect sys_rst_vip/rst_out mng_axi/aresetn - -# Create address segments - -create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 \ - [get_bd_addr_spaces mng_axi/Master_AXI] \ - [get_bd_addr_segs DUT/i_data_offload/s_axi/axi_lite] \ - SEG_data_offload_0_axi_lite -adi_sim_add_define "DOFF_BA=[format "%d" 0x44A00000]" - -# source clock/reset - -ad_ip_instance clk_vip src_clk_vip -adi_sim_add_define "SRC_CLK=src_clk_vip" -ad_ip_parameter src_clk_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter src_clk_vip CONFIG.FREQ_HZ $src_clock_freq - -ad_ip_instance rst_vip src_rst_vip -adi_sim_add_define "SRC_RST=src_rst_vip" -ad_ip_parameter src_rst_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter src_rst_vip CONFIG.RST_POLARITY {ACTIVE_LOW} -ad_ip_parameter src_rst_vip CONFIG.ASYNCHRONOUS {NO} -ad_connect src_clk_vip/clk_out src_rst_vip/sync_clk - -# destination clock/reset - -ad_ip_instance clk_vip dst_clk_vip -adi_sim_add_define "DST_CLK=dst_clk_vip" -ad_ip_parameter dst_clk_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter dst_clk_vip CONFIG.FREQ_HZ $dst_clock_freq - -ad_ip_instance rst_vip dst_rst_vip -adi_sim_add_define "DST_RST=dst_rst_vip" -ad_ip_parameter dst_rst_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter dst_rst_vip CONFIG.RST_POLARITY {ACTIVE_LOW} -ad_ip_parameter dst_rst_vip CONFIG.ASYNCHRONOUS {NO} -ad_connect dst_clk_vip/clk_out dst_rst_vip/sync_clk - -# DDR/HBM clock/reset - -ad_ip_instance clk_vip mem_clk_vip -adi_sim_add_define "MEM_CLK=mem_clk_vip" -ad_ip_parameter mem_clk_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter mem_clk_vip CONFIG.FREQ_HZ $mem_clock_freq - -create_bd_port -dir I mem_rst_n - - - -################################################################################ -# src_m_axis_vip - Master AXIS VIP for source interface -################################################################################ - -ad_ip_instance axi4stream_vip src_axis -adi_sim_add_define "SRC_AXIS=src_axis" -ad_ip_parameter src_axis CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter src_axis CONFIG.HAS_TREADY {1} -ad_ip_parameter src_axis CONFIG.HAS_TLAST {1} -ad_ip_parameter src_axis CONFIG.TDATA_NUM_BYTES [expr $offload_src_dwidth/8] - -ad_connect src_clk_vip/clk_out src_axis/aclk -ad_connect src_rst_vip/rst_out src_axis/aresetn - -ad_connect src_clk_vip/clk_out DUT/s_axis_aclk -ad_connect src_rst_vip/rst_out DUT/s_axis_aresetn - -ad_connect src_axis/m_axis DUT/s_axis -# Always assert tready for RX tests -if !$path_type { - ad_connect src_axis/m_axis_tready VCC -} - -if $offload_mem_type { - ad_connect DUT/i_data_offload/ddr_calib_done VCC -} - -################################################################################ -# dst_s_axis_vip - Slave AXIS VIP for destination interface -################################################################################ - -ad_ip_instance axi4stream_vip dst_axis -adi_sim_add_define "DST_AXIS=dst_axis" -ad_ip_parameter dst_axis CONFIG.INTERFACE_MODE {SLAVE} -ad_ip_parameter dst_axis CONFIG.TDATA_NUM_BYTES [expr $offload_dst_dwidth/8] -ad_ip_parameter dst_axis CONFIG.HAS_TLAST {1} - -ad_connect dst_clk_vip/clk_out dst_axis/aclk -ad_connect dst_rst_vip/rst_out dst_axis/aresetn - -ad_connect dst_clk_vip/clk_out DUT/m_axis_aclk -ad_connect dst_rst_vip/rst_out DUT/m_axis_aresetn - -ad_connect DUT/m_axis dst_axis/s_axis - -if {$offload_mem_type == 2} { - - source $ad_hdl_dir/library/util_hbm/scripts/adi_util_hbm.tcl - - set hbm_clk mem_clk_vip/clk_out - set hbm_reset mem_rst_n - - global hbm_sim - set hbm_sim 1 - ad_create_hbm HBM_VIP - - ad_connect_hbm HBM_VIP DUT/storage_unit $hbm_clk $hbm_reset - - #ad_connect HBM_VIP/HBM_REF_CLK_0 $sys_cpu_clk - #ad_connect HBM_VIP/APB_0_PCLK $sys_cpu_clk - - assign_bd_address - set num_m [get_property CONFIG.NUM_M [get_bd_cells /DUT/storage_unit]] - for {set i 0} {$i < $num_m} {incr i} { - set_property offset 0x00000000 [get_bd_addr_segs DUT/storage_unit/MAXI_${i}/SEG_HBM_VIP_Reg] - set_property range 4G [get_bd_addr_segs DUT/storage_unit/MAXI_${i}/SEG_HBM_VIP_Reg] - } - -} diff --git a/testbenches/ip/data_offload_2/system_project.tcl b/testbenches/ip/data_offload_2/system_project.tcl deleted file mode 100644 index 73eb0e12e..000000000 --- a/testbenches/ip/data_offload_2/system_project.tcl +++ /dev/null @@ -1,44 +0,0 @@ -source ../../../scripts/adi_sim.tcl - -if {$argc < 1} { - puts "Expecting at least one argument that specifies the test configuration" - set cfg_file cfg2.tcl - #exit 1 -} else { - set cfg_file [lindex $argv 0] -} - -global ad_project_params - -# Disable default harness -set ad_project_params(CUSTOM_HARNESS) 1 - -# Read common configuration file -source "cfgs/common_cfg.tcl" -# Read configuration file with topology information -source "cfgs/${cfg_file}" - -# Set the project name -set project_name [file rootname $cfg_file] - -# Create the project -#set bd_design_name "test_harness" -set part "xczu9eg-ffvb1156-2-e" - -adi_sim_project_xilinx $project_name $part - -source $ad_tb_dir/library/includes/sp_include_axis.tcl - -# Add test files to the project -adi_sim_project_files [list \ - "environment.sv" \ - "tests/test_program.sv" \ - "tests/test_program_sync.sv" \ - "do_scoreboard.sv" \ - "data_offload_pkg.sv" \ -] - -#set a default test program -adi_sim_add_define "TEST_PROGRAM=test_program" - -adi_sim_generate $project_name diff --git a/testbenches/ip/data_offload_2/system_tb.sv b/testbenches/ip/data_offload_2/system_tb.sv deleted file mode 100644 index f24516530..000000000 --- a/testbenches/ip/data_offload_2/system_tb.sv +++ /dev/null @@ -1,55 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2021 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - - -`include "utils.svh" - -module system_tb(); - - wire init_req; - wire sync_ext; - - `TEST_PROGRAM test( - .init_req (init_req), - .sync_ext (sync_ext), - .mem_rst_n (mem_rst_n) - ); - test_harness `TH ( - .init_req (init_req), - .sync_ext (sync_ext), - .mem_rst_n (mem_rst_n) - ); - -endmodule diff --git a/testbenches/ip/data_offload_2/tests/test_program.sv b/testbenches/ip/data_offload_2/tests/test_program.sv deleted file mode 100644 index 84f1323c3..000000000 --- a/testbenches/ip/data_offload_2/tests/test_program.sv +++ /dev/null @@ -1,190 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`include "utils.svh" - -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; -import m_axis_sequencer_pkg::*; -import logger_pkg::*; - -import environment_pkg::*; -import data_offload_pkg::*; - -`ifdef HBM_AXI -import `PKGIFY(test_harness, HBM_VIP)::*; -`endif - -//============================================================================= -// Register Maps -//============================================================================= - -module test_program( - output reg init_req = 1'b0, - output reg sync_ext = 1'b0, - output reg mem_rst_n = 1'b0 -); - - //declaring environment instance - environment env; - xil_axi4stream_ready_gen_policy_t dac_mode; - - data_offload dut; - - `ifdef HBM_AXI - `AGENT(test_harness, HBM_VIP, slv_mem_t) hbm_axi_agent; - `endif - - initial begin - //creating environment - env = new(`TH.`MNG_AXI.inst.IF, - `TH.`SRC_AXIS.inst.IF, - `TH.`DST_AXIS.inst.IF - ); - - dut = new(env.mng, `DOFF_BA); - - //========================================================================= - // Setup generator/monitor stubs - //========================================================================= - - env.src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - for (int i = 0; i < `SRC_TRANSFERS_INITIAL_COUNT; i++) - env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); // Only gen TLAST in TX path - - env.dst_axis_seq.set_mode(`DST_READY_MODE); - env.dst_axis_seq.set_high_time(`DST_READY_HIGH); - env.dst_axis_seq.set_low_time(`DST_READY_LOW); - - //========================================================================= - - setLoggerVerbosity(ADI_VERBOSITY_NONE); - - env.scoreboard.set_oneshot(`OFFLOAD_ONESHOT); - env.scoreboard.set_path_type(`OFFLOAD_PATH_TYPE); - - start_clocks(); - sys_reset(); - - env.start(); - - `ifdef HBM_AXI - if (`MEM_TYPE == 2) begin - hbm_axi_agent = new("AXI HBM stub agent", `TH.`HBM_AXI.inst.IF); - hbm_axi_agent.start_slave(); - end - `endif - - `INFO(("Bring up IP from reset."), ADI_VERBOSITY_LOW); - systemBringUp(); - - env.src_axis_seq.start(); - - // Start the ADC/DAC stubs - `INFO(("Call the run() ..."), ADI_VERBOSITY_LOW); - env.run(); - - init_req <= 1'b1; - - if (!`OFFLOAD_ONESHOT) begin - env.src_axis_seq.wait_empty_descriptor_queue(); - init_req <= 1'b0; - end - - #((`SRC_TRANSFERS_DELAY)*1ns); - - init_req <= 1'b1; - - #100ns; - - for (int i = 0; i < `SRC_TRANSFERS_DELAYED_COUNT; i++) - env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); - - if (!`OFFLOAD_ONESHOT) begin - env.src_axis_seq.wait_empty_descriptor_queue(); - init_req <= 1'b0; - end - - #((`TIME_TO_WAIT)*1ns); - - env.stop(); - - stop_clocks(); - - `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); - $finish(); - - end - - task start_clocks(); - `TH.`SRC_CLK.inst.IF.start_clock(); - `TH.`DST_CLK.inst.IF.start_clock(); - `TH.`SYS_CLK.inst.IF.start_clock(); - `TH.`MEM_CLK.inst.IF.start_clock(); - endtask - - task stop_clocks(); - `TH.`SRC_CLK.inst.IF.stop_clock(); - `TH.`DST_CLK.inst.IF.stop_clock(); - `TH.`SYS_CLK.inst.IF.stop_clock(); - `TH.`MEM_CLK.inst.IF.stop_clock(); - endtask - - task sys_reset(); - `TH.`SRC_RST.inst.IF.assert_reset(); - `TH.`DST_RST.inst.IF.assert_reset(); - `TH.`SYS_RST.inst.IF.assert_reset(); - - #500ns; - `TH.`SRC_RST.inst.IF.deassert_reset(); - `TH.`DST_RST.inst.IF.deassert_reset(); - `TH.`SYS_RST.inst.IF.deassert_reset(); - mem_rst_n = 1'b1; - endtask - - task systemBringUp(); - // bring up the Data Offload instances from reset - `INFO(("Bring up TX Data Offload"), ADI_VERBOSITY_LOW); - - dut.set_oneshot(`OFFLOAD_ONESHOT); - -`ifdef OFFLOAD_TRANSFER_LENGTH - dut.set_transfer_length(`OFFLOAD_TRANSFER_LENGTH); -`endif - - dut.set_resetn(1'b1); - endtask - -endmodule diff --git a/testbenches/ip/data_offload_2/tests/test_program_sync.sv b/testbenches/ip/data_offload_2/tests/test_program_sync.sv deleted file mode 100644 index 5297a38eb..000000000 --- a/testbenches/ip/data_offload_2/tests/test_program_sync.sv +++ /dev/null @@ -1,197 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`include "utils.svh" - -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; -import m_axis_sequencer_pkg::*; -import logger_pkg::*; - -import environment_pkg::*; -import data_offload_pkg::*; - -//============================================================================= -// Register Maps -//============================================================================= - -module test_program_sync ( - output reg init_req = 1'b0, - output reg sync_ext = 1'b0, - output reg mem_rst_n = 1'b0 -); - - //declaring environment instance - environment env; - xil_axi4stream_ready_gen_policy_t dac_mode; - - data_offload dut; - - initial begin - //creating environment - env = new(`TH.`MNG_AXI.inst.IF, - `TH.`SRC_AXIS.inst.IF, - `TH.`DST_AXIS.inst.IF - ); - - dut = new(env.mng, `DOFF_BA); - - //========================================================================= - // Setup generator/monitor stubs - //========================================================================= - - env.src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, 1, 0); - - env.dst_axis_seq.set_mode(`DST_READY_MODE); - env.dst_axis_seq.set_high_time(`DST_READY_HIGH); - env.dst_axis_seq.set_low_time(`DST_READY_LOW); - - //========================================================================= - - setLoggerVerbosity(ADI_VERBOSITY_NONE); - - env.scoreboard.set_oneshot(1); - - start_clocks(); - sys_reset(); - - env.start(); - - `INFO(("Bring up IP from reset."), ADI_VERBOSITY_LOW); - systemBringUp(); - - env.src_axis_seq.start(); - - // Start the ADC/DAC stubs - `INFO(("Call the run() ..."), ADI_VERBOSITY_LOW); - env.run(); - - init_req <= 1'b1; - - // @env.src_axis_seq.queue_empty; - // init_req <= 1'b0; - #100ns; - - - sync_ext <= 1'b1; - @(posedge `TH.`DST_CLK.clk_out); - @(posedge `TH.`DST_CLK.clk_out); - sync_ext <= 1'b0; - #1000ns; - - sync_ext <= 1'b1; - @(posedge `TH.`DST_CLK.clk_out); - @(posedge `TH.`DST_CLK.clk_out); - sync_ext <= 1'b0; - #1000ns; - - sync_ext <= 1'b1; - @(posedge `TH.`DST_CLK.clk_out); - @(posedge `TH.`DST_CLK.clk_out); - sync_ext <= 1'b0; - #1000ns; - - // init_req <= 1'b1; - - sync_ext <= 1'b1; - @(posedge `TH.`DST_CLK.clk_out); - @(posedge `TH.`DST_CLK.clk_out); - - sync_ext <= 1'b0; - #1000ns; - - #((`SRC_TRANSFERS_DELAY)*1ns); - - - //init_req <= 1'b1; - #100ns; - // env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, 1, 0); - - // @env.src_axis_seq.queue_empty; - // init_req <= 1'b0; - - #300ns; - sync_ext <= 1'b1; - @(posedge `TH.`DST_CLK.clk_out); - sync_ext <= 1'b0; - - #((`TIME_TO_WAIT)*1ns); - - env.stop(); - - stop_clocks(); - - `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); - $finish(); - - end - - task start_clocks(); - `TH.`SRC_CLK.inst.IF.start_clock(); - `TH.`DST_CLK.inst.IF.start_clock(); - `TH.`SYS_CLK.inst.IF.start_clock(); - endtask - - task stop_clocks(); - `TH.`SRC_CLK.inst.IF.stop_clock(); - `TH.`DST_CLK.inst.IF.stop_clock(); - `TH.`SYS_CLK.inst.IF.stop_clock(); - endtask - - task sys_reset(); - `TH.`SRC_RST.inst.IF.assert_reset(); - `TH.`DST_RST.inst.IF.assert_reset(); - `TH.`SYS_RST.inst.IF.assert_reset(); - - #500ns; - `TH.`SRC_RST.inst.IF.deassert_reset(); - `TH.`DST_RST.inst.IF.deassert_reset(); - `TH.`SYS_RST.inst.IF.deassert_reset(); - endtask - - task systemBringUp(); - // bring up the Data Offload instances from reset - `INFO(("Bring up TX Data Offload"), ADI_VERBOSITY_LOW); - - dut.set_oneshot(0); - dut.set_sync_config(1); // Hardware Sync - - // dut.set_transfer_length(`TRANSFER_LENGTH); - - dut.set_resetn(1'b1); - endtask - -endmodule diff --git a/testbenches/ip/data_offload_2/waves/cfg0.wcfg b/testbenches/ip/data_offload_2/waves/cfg0.wcfg deleted file mode 100644 index 9906ad31c..000000000 --- a/testbenches/ip/data_offload_2/waves/cfg0.wcfg +++ /dev/null @@ -1,288 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - s_axi_aclk - s_axi_aclk - - - s_axi_aresetn - s_axi_aresetn - - - s_axi_awvalid - s_axi_awvalid - - - s_axi_awaddr[15:0] - s_axi_awaddr[15:0] - - - s_axi_awprot[2:0] - s_axi_awprot[2:0] - - - s_axi_awready - s_axi_awready - - - s_axi_wvalid - s_axi_wvalid - - - s_axi_wdata[31:0] - s_axi_wdata[31:0] - - - s_axi_wstrb[3:0] - s_axi_wstrb[3:0] - - - s_axi_wready - s_axi_wready - - - s_axi_bvalid - s_axi_bvalid - - - s_axi_bresp[1:0] - s_axi_bresp[1:0] - - - s_axi_bready - s_axi_bready - - - s_axi_arvalid - s_axi_arvalid - - - s_axi_araddr[15:0] - s_axi_araddr[15:0] - - - s_axi_arprot[2:0] - s_axi_arprot[2:0] - - - s_axi_arready - s_axi_arready - - - s_axi_rvalid - s_axi_rvalid - - - s_axi_rready - s_axi_rready - - - s_axi_rresp[1:0] - s_axi_rresp[1:0] - - - s_axi_rdata[31:0] - s_axi_rdata[31:0] - - - s_axis_aclk - s_axis_aclk - - - s_axis_aresetn - s_axis_aresetn - - - s_axis_ready - s_axis_ready - - - s_axis_valid - s_axis_valid - - - s_axis_data[127:0] - s_axis_data[127:0] - - - s_axis_last - s_axis_last - - - s_axis_tkeep[15:0] - s_axis_tkeep[15:0] - - - m_axis_aclk - m_axis_aclk - - - m_axis_aresetn - m_axis_aresetn - - - m_axis_ready - m_axis_ready - - - m_axis_valid - m_axis_valid - - - m_axis_data[127:0] - m_axis_data[127:0] - - - m_axis_last - m_axis_last - - - m_axis_tkeep[15:0] - m_axis_tkeep[15:0] - - - init_req - init_req - - - init_ack - init_ack - - - sync_ext - sync_ext - - - fifo_src_wen - fifo_src_wen - - - fifo_src_resetn - fifo_src_resetn - - - fifo_src_waddr[5:0] - fifo_src_waddr[5:0] - - - fifo_src_wdata[127:0] - fifo_src_wdata[127:0] - - - fifo_src_wlast - fifo_src_wlast - - - fifo_dst_ren - fifo_dst_ren - - - fifo_dst_ready - fifo_dst_ready - - - fifo_dst_resetn - fifo_dst_resetn - - - fifo_dst_raddr[5:0] - fifo_dst_raddr[5:0] - - - fifo_dst_rdata[127:0] - fifo_dst_rdata[127:0] - - - ddr_calib_done - ddr_calib_done - - - m_axis - m_axis - true - STYLE_ENUM_TRANSACTION - fff,fff=blank - true - #00E600 - /system_tb/test_harness/DUT/i_data_offload/m_axis.streamWaveData - 2 - /system_tb/test_harness/DUT/i_data_offload/m_axis.linkStarve - #99E600 - /system_tb/test_harness/DUT/i_data_offload/m_axis.linkStall - #E64C00 - /system_tb/test_harness/DUT/i_data_offload/m_axis.streamTooltipData - - - - s_axi - s_axi - - - true - STYLE_ENUM_TRANSACTION - fff,fff=blank - true - #00E600 - /system_tb/test_harness/DUT/i_data_offload/s_axis.streamWaveData - 2 - /system_tb/test_harness/DUT/i_data_offload/s_axis.linkStarve - #99E600 - /system_tb/test_harness/DUT/i_data_offload/s_axis.linkStall - #E64C00 - /system_tb/test_harness/DUT/i_data_offload/s_axis.streamTooltipData - s_axis - s_axis - - - - wr_fsm_state[1:0] - wr_fsm_state[1:0] - - - rd_fsm_state[1:0] - rd_fsm_state[1:0] - - - init_req - init_req - - - wr_isempty_s - wr_isempty_s - - - wr_full - wr_full - - diff --git a/testbenches/ip/data_offload_2/waves/cfg1.wcfg b/testbenches/ip/data_offload_2/waves/cfg1.wcfg deleted file mode 100644 index fe3763c0a..000000000 --- a/testbenches/ip/data_offload_2/waves/cfg1.wcfg +++ /dev/null @@ -1,271 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - s_axi_aclk - s_axi_aclk - - - s_axi_aresetn - s_axi_aresetn - - - s_axi_awvalid - s_axi_awvalid - - - s_axi_awaddr[15:0] - s_axi_awaddr[15:0] - - - s_axi_awprot[2:0] - s_axi_awprot[2:0] - - - s_axi_awready - s_axi_awready - - - s_axi_wvalid - s_axi_wvalid - - - s_axi_wdata[31:0] - s_axi_wdata[31:0] - - - s_axi_wstrb[3:0] - s_axi_wstrb[3:0] - - - s_axi_wready - s_axi_wready - - - s_axi_bvalid - s_axi_bvalid - - - s_axi_bresp[1:0] - s_axi_bresp[1:0] - - - s_axi_bready - s_axi_bready - - - s_axi_arvalid - s_axi_arvalid - - - s_axi_araddr[15:0] - s_axi_araddr[15:0] - - - s_axi_arprot[2:0] - s_axi_arprot[2:0] - - - s_axi_arready - s_axi_arready - - - s_axi_rvalid - s_axi_rvalid - - - s_axi_rready - s_axi_rready - - - s_axi_rresp[1:0] - s_axi_rresp[1:0] - - - s_axi_rdata[31:0] - s_axi_rdata[31:0] - - - s_axis_aclk - s_axis_aclk - - - s_axis_aresetn - s_axis_aresetn - - - s_axis_ready - s_axis_ready - - - s_axis_valid - s_axis_valid - - - s_axis_data[127:0] - s_axis_data[127:0] - - - s_axis_last - s_axis_last - - - s_axis_tkeep[15:0] - s_axis_tkeep[15:0] - - - m_axis_aclk - m_axis_aclk - - - m_axis_aresetn - m_axis_aresetn - - - m_axis_ready - m_axis_ready - - - m_axis_valid - m_axis_valid - - - m_axis_data[127:0] - m_axis_data[127:0] - - - m_axis_last - m_axis_last - - - m_axis_tkeep[15:0] - m_axis_tkeep[15:0] - - - init_req - init_req - - - init_ack - init_ack - - - sync_ext - sync_ext - - - fifo_src_wen - fifo_src_wen - - - fifo_src_resetn - fifo_src_resetn - - - fifo_src_waddr[5:0] - fifo_src_waddr[5:0] - - - fifo_src_wdata[127:0] - fifo_src_wdata[127:0] - - - fifo_src_wlast - fifo_src_wlast - - - fifo_dst_ren - fifo_dst_ren - - - fifo_dst_ready - fifo_dst_ready - - - fifo_dst_resetn - fifo_dst_resetn - - - fifo_dst_raddr[5:0] - fifo_dst_raddr[5:0] - - - fifo_dst_rdata[127:0] - fifo_dst_rdata[127:0] - - - ddr_calib_done - ddr_calib_done - - - true - STYLE_ENUM_TRANSACTION - fff,fff=blank - true - #00E600 - /system_tb/test_harness/DUT/i_data_offload/m_axis.streamWaveData - 2 - /system_tb/test_harness/DUT/i_data_offload/m_axis.linkStarve - #99E600 - /system_tb/test_harness/DUT/i_data_offload/m_axis.linkStall - #E64C00 - /system_tb/test_harness/DUT/i_data_offload/m_axis.streamTooltipData - m_axis - m_axis - - - - s_axi - s_axi - - - true - STYLE_ENUM_TRANSACTION - fff,fff=blank - true - #00E600 - /system_tb/test_harness/DUT/i_data_offload/s_axis.streamWaveData - 2 - /system_tb/test_harness/DUT/i_data_offload/s_axis.linkStarve - #99E600 - /system_tb/test_harness/DUT/i_data_offload/s_axis.linkStall - #E64C00 - /system_tb/test_harness/DUT/i_data_offload/s_axis.streamTooltipData - s_axis - s_axis - - - diff --git a/testbenches/ip/data_offload_2/waves/cfg2.wcfg b/testbenches/ip/data_offload_2/waves/cfg2.wcfg deleted file mode 100644 index 10d704334..000000000 --- a/testbenches/ip/data_offload_2/waves/cfg2.wcfg +++ /dev/null @@ -1,279 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - init_req - init_req - - - sync_ext - sync_ext - - - s_axi_aclk - s_axi_aclk - - - s_axi_aresetn - s_axi_aresetn - - - s_axi_awvalid - s_axi_awvalid - - - s_axi_awaddr[15:0] - s_axi_awaddr[15:0] - - - s_axi_awprot[2:0] - s_axi_awprot[2:0] - - - s_axi_awready - s_axi_awready - - - s_axi_wvalid - s_axi_wvalid - - - s_axi_wdata[31:0] - s_axi_wdata[31:0] - - - s_axi_wstrb[3:0] - s_axi_wstrb[3:0] - - - s_axi_wready - s_axi_wready - - - s_axi_bvalid - s_axi_bvalid - - - s_axi_bresp[1:0] - s_axi_bresp[1:0] - - - s_axi_bready - s_axi_bready - - - s_axi_arvalid - s_axi_arvalid - - - s_axi_araddr[15:0] - s_axi_araddr[15:0] - - - s_axi_arprot[2:0] - s_axi_arprot[2:0] - - - s_axi_arready - s_axi_arready - - - s_axi_rvalid - s_axi_rvalid - - - s_axi_rready - s_axi_rready - - - s_axi_rresp[1:0] - s_axi_rresp[1:0] - - - s_axi_rdata[31:0] - s_axi_rdata[31:0] - - - s_axis_aclk - s_axis_aclk - - - s_axis_aresetn - s_axis_aresetn - - - s_axis_ready - s_axis_ready - - - s_axis_valid - s_axis_valid - - - s_axis_data[127:0] - s_axis_data[127:0] - - - s_axis_last - s_axis_last - - - s_axis_tkeep[15:0] - s_axis_tkeep[15:0] - - - m_axis_aclk - m_axis_aclk - - - m_axis_aresetn - m_axis_aresetn - - - m_axis_ready - m_axis_ready - - - m_axis_valid - m_axis_valid - - - m_axis_data[127:0] - m_axis_data[127:0] - - - m_axis_last - m_axis_last - - - m_axis_tkeep[15:0] - m_axis_tkeep[15:0] - - - init_req - init_req - - - init_ack - init_ack - - - sync_ext - sync_ext - - - fifo_src_wen - fifo_src_wen - - - fifo_src_resetn - fifo_src_resetn - - - fifo_src_waddr[5:0] - fifo_src_waddr[5:0] - - - fifo_src_wdata[127:0] - fifo_src_wdata[127:0] - - - fifo_src_wlast - fifo_src_wlast - - - fifo_dst_ren - fifo_dst_ren - - - fifo_dst_ready - fifo_dst_ready - - - fifo_dst_resetn - fifo_dst_resetn - - - fifo_dst_raddr[5:0] - fifo_dst_raddr[5:0] - - - fifo_dst_rdata[127:0] - fifo_dst_rdata[127:0] - - - ddr_calib_done - ddr_calib_done - - - true - STYLE_ENUM_TRANSACTION - fff,fff=blank - true - #00E600 - /system_tb/test_harness/DUT/i_data_offload/m_axis.streamWaveData - 2 - /system_tb/test_harness/DUT/i_data_offload/m_axis.linkStarve - #99E600 - /system_tb/test_harness/DUT/i_data_offload/m_axis.linkStall - #E64C00 - /system_tb/test_harness/DUT/i_data_offload/m_axis.streamTooltipData - m_axis - m_axis - - - - s_axi - s_axi - - - true - STYLE_ENUM_TRANSACTION - fff,fff=blank - true - #00E600 - /system_tb/test_harness/DUT/i_data_offload/s_axis.streamWaveData - 2 - /system_tb/test_harness/DUT/i_data_offload/s_axis.linkStarve - #99E600 - /system_tb/test_harness/DUT/i_data_offload/s_axis.linkStall - #E64C00 - /system_tb/test_harness/DUT/i_data_offload/s_axis.streamTooltipData - s_axis - s_axis - - - diff --git a/testbenches/ip/data_offload_2/waves/cfg3.wcfg b/testbenches/ip/data_offload_2/waves/cfg3.wcfg deleted file mode 100644 index 216a075a4..000000000 --- a/testbenches/ip/data_offload_2/waves/cfg3.wcfg +++ /dev/null @@ -1,387 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - init_ack - init_ack - - - init_req - init_req - - - m_axis_aclk - m_axis_aclk - - - m_axis_aresetn - m_axis_aresetn - - - m_axis_tdata[127:0] - m_axis_tdata[127:0] - - - m_axis_tkeep[15:0] - m_axis_tkeep[15:0] - - - m_axis_tlast[0:0] - m_axis_tlast[0:0] - - - m_axis_tready[0:0] - m_axis_tready[0:0] - - - m_axis_tvalid[0:0] - m_axis_tvalid[0:0] - - - s_axi_aclk - s_axi_aclk - - - s_axi_araddr[31:0] - s_axi_araddr[31:0] - - - s_axi_aresetn - s_axi_aresetn - - - s_axi_arprot[2:0] - s_axi_arprot[2:0] - - - s_axi_arready - s_axi_arready - - - s_axi_arvalid - s_axi_arvalid - - - s_axi_awaddr[31:0] - s_axi_awaddr[31:0] - - - s_axi_awprot[2:0] - s_axi_awprot[2:0] - - - s_axi_awready - s_axi_awready - - - s_axi_awvalid - s_axi_awvalid - - - s_axi_bready - s_axi_bready - - - s_axi_bresp[1:0] - s_axi_bresp[1:0] - - - s_axi_bvalid - s_axi_bvalid - - - s_axi_rdata[31:0] - s_axi_rdata[31:0] - - - s_axi_rready - s_axi_rready - - - s_axi_rresp[1:0] - s_axi_rresp[1:0] - - - s_axi_rvalid - s_axi_rvalid - - - s_axi_wdata[31:0] - s_axi_wdata[31:0] - - - s_axi_wready - s_axi_wready - - - s_axi_wstrb[3:0] - s_axi_wstrb[3:0] - - - s_axi_wvalid - s_axi_wvalid - - - s_axis_aclk - s_axis_aclk - - - s_axis_aresetn - s_axis_aresetn - - - s_axis_tdata[127:0] - s_axis_tdata[127:0] - - - s_axis_tlast[0:0] - s_axis_tlast[0:0] - - - s_axis_tready[0:0] - s_axis_tready[0:0] - - - s_axis_tvalid[0:0] - s_axis_tvalid[0:0] - - - sync_ext - sync_ext - - - Net - Net - - - Net1 - Net1 - - - VCC_1_dout[0:0] - VCC_1_dout[0:0] - - - i_data_offload_fifo_dst_raddr[5:0] - i_data_offload_fifo_dst_raddr[5:0] - - - i_data_offload_fifo_dst_ren - i_data_offload_fifo_dst_ren - - - i_data_offload_fifo_src_waddr[5:0] - i_data_offload_fifo_src_waddr[5:0] - - - i_data_offload_fifo_src_wdata[127:0] - i_data_offload_fifo_src_wdata[127:0] - - - i_data_offload_fifo_src_wen - i_data_offload_fifo_src_wen - - - i_data_offload_init_ack - i_data_offload_init_ack - - - i_data_offload_m_axis_TDATA[127:0] - i_data_offload_m_axis_TDATA[127:0] - - - i_data_offload_m_axis_TKEEP[15:0] - i_data_offload_m_axis_TKEEP[15:0] - - - i_data_offload_m_axis_TLAST - i_data_offload_m_axis_TLAST - - - i_data_offload_m_axis_TREADY[0:0] - i_data_offload_m_axis_TREADY[0:0] - - - i_data_offload_m_axis_TVALID - i_data_offload_m_axis_TVALID - - - init_req_1 - init_req_1 - - - m_axis_aresetn_1 - m_axis_aresetn_1 - - - s_axi_1_ARADDR[31:0] - s_axi_1_ARADDR[31:0] - - - s_axi_1_ARPROT[2:0] - s_axi_1_ARPROT[2:0] - - - s_axi_1_ARREADY - s_axi_1_ARREADY - - - s_axi_1_ARVALID - s_axi_1_ARVALID - - - s_axi_1_AWADDR[31:0] - s_axi_1_AWADDR[31:0] - - - s_axi_1_AWPROT[2:0] - s_axi_1_AWPROT[2:0] - - - s_axi_1_AWREADY - s_axi_1_AWREADY - - - s_axi_1_AWVALID - s_axi_1_AWVALID - - - s_axi_1_BREADY - s_axi_1_BREADY - - - s_axi_1_BRESP[1:0] - s_axi_1_BRESP[1:0] - - - s_axi_1_BVALID - s_axi_1_BVALID - - - s_axi_1_RDATA[31:0] - s_axi_1_RDATA[31:0] - - - s_axi_1_RREADY - s_axi_1_RREADY - - - s_axi_1_RRESP[1:0] - s_axi_1_RRESP[1:0] - - - s_axi_1_RVALID - s_axi_1_RVALID - - - s_axi_1_WDATA[31:0] - s_axi_1_WDATA[31:0] - - - s_axi_1_WREADY - s_axi_1_WREADY - - - s_axi_1_WSTRB[3:0] - s_axi_1_WSTRB[3:0] - - - s_axi_1_WVALID - s_axi_1_WVALID - - - s_axi_aclk_1 - s_axi_aclk_1 - - - s_axi_aresetn_1 - s_axi_aresetn_1 - - - s_axis_1_TDATA[127:0] - s_axis_1_TDATA[127:0] - - - s_axis_1_TLAST[0:0] - s_axis_1_TLAST[0:0] - - - s_axis_1_TREADY - s_axis_1_TREADY - - - s_axis_1_TVALID[0:0] - s_axis_1_TVALID[0:0] - - - s_axis_aresetn_1 - s_axis_aresetn_1 - - - storage_unit_doutb[127:0] - storage_unit_doutb[127:0] - - - sync_ext_1 - sync_ext_1 - - - m_axis - m_axis - - - s_axi - s_axi - - - true - STYLE_ENUM_TRANSACTION - fff,fff=blank - true - #00E600 - /system_tb/test_harness/DUT/s_axis.streamWaveData - 2 - /system_tb/test_harness/DUT/s_axis.linkStarve - #99E600 - /system_tb/test_harness/DUT/s_axis.linkStall - #E64C00 - /system_tb/test_harness/DUT/s_axis.streamTooltipData - s_axis - s_axis - - - diff --git a/testbenches/ip/data_offload_2/waves/cfg4.wcfg b/testbenches/ip/data_offload_2/waves/cfg4.wcfg deleted file mode 100644 index 49a9a2cdc..000000000 --- a/testbenches/ip/data_offload_2/waves/cfg4.wcfg +++ /dev/null @@ -1,36 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/testbenches/ip/hbm/Makefile b/testbenches/ip/hbm/Makefile deleted file mode 100644 index 6bf500da4..000000000 --- a/testbenches/ip/hbm/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -#################################################################################### -#################################################################################### -## Copyright (C) 2018 Analog Devices, Inc. -#################################################################################### -#################################################################################### - -# Makeincludes -include ../../../scripts/make_tb_path.mk -include $(ADI_TB_DIR)/library/includes/Makeinclude_axis.mk -include $(ADI_TB_DIR)/library/includes/Makeinclude_dmac.mk - -# Remaining test-bench dependencies except test programs -LIB_DEPS += axi_dmac -LIB_DEPS += util_hbm - -# list of test programs -TP := $(notdir $(basename $(wildcard tests/*.sv))) - -# config files should have the following format -# cfg__.tcl -CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) - -# List of tests and configuration combinations that has to be run -# Format is: : -TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP))) - -include $(ADI_TB_DIR)/scripts/project-sim.mk - -# usage: -# -# run specific test on a specific configuration in gui mode -# make CFG= TST= MODE=gui -# -# run all test from a configuration -# make - -#################################################################################### -#################################################################################### diff --git a/testbenches/ip/hbm/README.md b/testbenches/ip/hbm/README.md deleted file mode 100644 index f1495cb4e..000000000 --- a/testbenches/ip/hbm/README.md +++ /dev/null @@ -1,27 +0,0 @@ -Usage : - -Run all tests in batch mode: - - make - - -Run all tests in GUI mode: - - make MODE=gui - - -Run specific test on a specific configuration in gui mode: - - make CFG= TST= MODE=gui - - -Run all test from a configuration: - - make - - -Where: - - * is a file from the cfgs directory without the tcl extension of format cfg\* - * is a file from the tests directory without the tcl extension - diff --git a/testbenches/ip/hbm/cfgs/cfg1.tcl b/testbenches/ip/hbm/cfgs/cfg1.tcl deleted file mode 100644 index c88c42fb4..000000000 --- a/testbenches/ip/hbm/cfgs/cfg1.tcl +++ /dev/null @@ -1,8 +0,0 @@ -global ad_project_params - -set ad_project_params(DATA_PATH_WIDTH) 16 ; ## 16 bytes - -set ad_project_params(SRC_CLOCK_FREQ) 250000000 ; ## Source clock frequency in Hz -set ad_project_params(DST_CLOCK_FREQ) 300000000 ; ## Destination clock frequency in Hz - - diff --git a/testbenches/ip/hbm/system_bd.tcl b/testbenches/ip/hbm/system_bd.tcl deleted file mode 100644 index 331538417..000000000 --- a/testbenches/ip/hbm/system_bd.tcl +++ /dev/null @@ -1,161 +0,0 @@ -# *************************************************************************** -# *************************************************************************** -# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. -# -# In this HDL repository, there are many different and unique modules, consisting -# of various HDL (Verilog or VHDL) components. The individual modules are -# developed independently, and may be accompanied by separate and unique license -# terms. -# -# The user should read each of these license terms, and understand the -# freedoms and responsibilities that he or she has by using this source/core. -# -# This core is distributed in the hope that it will be useful, but WITHOUT ANY -# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -# A PARTICULAR PURPOSE. -# -# Redistribution and use of source or resulting binaries, with or without modification -# of this file, are permitted under one of the following two license terms: -# -# 1. The GNU General Public License version 2 as published by the -# Free Software Foundation, which can be found in the top level directory -# of this repository (LICENSE_GPL2), and also online at: -# -# -# OR -# -# 2. An ADI specific BSD license, which can be found in the top level directory -# of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -# This will allow to generate bit files and not release the source code, -# as long as it attaches to an ADI device. -# -# *************************************************************************** -# *************************************************************************** - -global ad_project_params - -source $ad_hdl_dir/library/util_hbm/scripts/adi_util_hbm.tcl - -# hbm clk/reset -ad_ip_instance clk_vip hbm_clk_vip [ list \ - INTERFACE_MODE {MASTER} \ - FREQ_HZ 250000000 \ -] -adi_sim_add_define "HBM_CLK=hbm_clk_vip" - -set hbm_clk hbm_clk_vip/clk_out - -ad_ip_instance rst_vip hbm_rst_vip -adi_sim_add_define "HBM_RST=hbm_rst_vip" -ad_ip_parameter hbm_rst_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter hbm_rst_vip CONFIG.RST_POLARITY {ACTIVE_LOW} -ad_ip_parameter hbm_rst_vip CONFIG.ASYNCHRONOUS {NO} -ad_connect hbm_clk_vip/clk_out hbm_rst_vip/sync_clk -set hbm_reset hbm_rst_vip/rst_out - -## DUT configuration - -set src_clock_freq $ad_project_params(SRC_CLOCK_FREQ) -set dst_clock_freq $ad_project_params(DST_CLOCK_FREQ) - -set data_path_width $ad_project_params(DATA_PATH_WIDTH) - -set rx_tx_n 1 -set src_width 1024 -set dst_width 1024 -set mem_size [expr 4*1024*1024*1024] - -global hbm_sim - - -set hbm_sim 1 ; # 0 - Actual HBM ; Requires 3rd party sim tool - # 1 - AXI VIP - -# ------------------ -# -# Blocks under test -# -# ------------------ - -ad_create_hbm HBM -ad_create_util_hbm DUT $rx_tx_n $src_width $dst_width $mem_size -ad_ip_parameter DUT CONFIG.AXI_PROTOCOL 1 - -ad_connect_hbm HBM DUT $hbm_clk $hbm_reset - -if {$hbm_sim == 0} { - ad_connect HBM/HBM_REF_CLK_0 $sys_cpu_clk - ad_connect HBM/APB_0_PCLK $sys_cpu_clk -} - - -# ------------------ -# -# Test harness -# -# ------------------ -# source clock/reset - -ad_ip_instance clk_vip src_clk_vip -adi_sim_add_define "SRC_CLK=src_clk_vip" -ad_ip_parameter src_clk_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter src_clk_vip CONFIG.FREQ_HZ $src_clock_freq - -ad_ip_instance rst_vip src_rst_vip -adi_sim_add_define "SRC_RST=src_rst_vip" -ad_ip_parameter src_rst_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter src_rst_vip CONFIG.RST_POLARITY {ACTIVE_LOW} -ad_ip_parameter src_rst_vip CONFIG.ASYNCHRONOUS {NO} -ad_connect src_clk_vip/clk_out src_rst_vip/sync_clk - -# destination clock/reset - -ad_ip_instance clk_vip dst_clk_vip -adi_sim_add_define "DST_CLK=dst_clk_vip" -ad_ip_parameter dst_clk_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter dst_clk_vip CONFIG.FREQ_HZ $dst_clock_freq - -ad_ip_instance rst_vip dst_rst_vip -adi_sim_add_define "DST_RST=dst_rst_vip" -ad_ip_parameter dst_rst_vip CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter dst_rst_vip CONFIG.RST_POLARITY {ACTIVE_LOW} -ad_ip_parameter dst_rst_vip CONFIG.ASYNCHRONOUS {NO} -ad_connect dst_clk_vip/clk_out dst_rst_vip/sync_clk - - -################################################################################ -# src_m_axis_vip - Master AXIS VIP for source interface -################################################################################ - -ad_ip_instance axi4stream_vip src_axis -adi_sim_add_define "SRC_AXIS=src_axis" -ad_ip_parameter src_axis CONFIG.INTERFACE_MODE {MASTER} -ad_ip_parameter src_axis CONFIG.HAS_TREADY {1} -ad_ip_parameter src_axis CONFIG.HAS_TLAST {1} -ad_ip_parameter src_axis CONFIG.TDATA_NUM_BYTES $data_path_width - -ad_connect src_clk_vip/clk_out src_axis/aclk -ad_connect src_rst_vip/rst_out src_axis/aresetn - -ad_connect src_clk_vip/clk_out DUT/s_axis_aclk - -ad_connect src_axis/m_axis DUT/s_axis - -################################################################################ -# dst_s_axis_vip - Slave AXIS VIP for destination interface -################################################################################ - -ad_ip_instance axi4stream_vip dst_axis -adi_sim_add_define "DST_AXIS=dst_axis" -ad_ip_parameter dst_axis CONFIG.INTERFACE_MODE {SLAVE} -ad_ip_parameter dst_axis CONFIG.TDATA_NUM_BYTES $data_path_width -ad_ip_parameter dst_axis CONFIG.HAS_TLAST {1} - -ad_connect dst_clk_vip/clk_out dst_axis/aclk -ad_connect dst_rst_vip/rst_out dst_axis/aresetn - -ad_connect dst_clk_vip/clk_out DUT/m_axis_aclk - -ad_connect DUT/m_axis dst_axis/s_axis - diff --git a/testbenches/ip/hbm/system_project.tcl b/testbenches/ip/hbm/system_project.tcl deleted file mode 100644 index 054c52207..000000000 --- a/testbenches/ip/hbm/system_project.tcl +++ /dev/null @@ -1,30 +0,0 @@ -source ../../../scripts/adi_sim.tcl - -if {$argc < 1} { - puts "Expecting at least one argument that specifies the test configuration" - exit 1 -} else { - set cfg_file [lindex $argv 0] -} - -# Read config file -source "cfgs/${cfg_file}" - -# Set the project name -set project_name [file rootname $cfg_file] - -# Create the project -adi_sim_project_xilinx $project_name "xcvu37p-fsvh2892-2L-e" - -source $ad_tb_dir/library/includes/sp_include_axis.tcl -source $ad_tb_dir/library/includes/sp_include_dmac.tcl - -# Add test files to the project -adi_sim_project_files [list \ - "tests/test_program.sv" \ -] - -#set a default test program -adi_sim_add_define "TEST_PROGRAM=test_program" - -adi_sim_generate $project_name diff --git a/testbenches/ip/hbm/system_tb.sv b/testbenches/ip/hbm/system_tb.sv deleted file mode 100644 index 05a64755d..000000000 --- a/testbenches/ip/hbm/system_tb.sv +++ /dev/null @@ -1,44 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2014-2018 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`include "utils.svh" - -module system_tb(); - - `TEST_PROGRAM test(); - - test_harness `TH (); - -endmodule diff --git a/testbenches/ip/hbm/tests/test_program.sv b/testbenches/ip/hbm/tests/test_program.sv deleted file mode 100644 index 0f8b66ccf..000000000 --- a/testbenches/ip/hbm/tests/test_program.sv +++ /dev/null @@ -1,173 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2014-2018 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`include "utils.svh" - -import test_harness_env_pkg::*; -import adi_axi_agent_pkg::*; -import adi_regmap_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; -import logger_pkg::*; -import adi_regmap_dmac_pkg::*; - -import `PKGIFY(test_harness, mng_axi_vip)::*; -import `PKGIFY(test_harness, ddr_axi_vip)::*; - -`define RX_DMA 32'h7c42_0000 -`define TX_DMA 32'h7c43_0000 -`define DDR_BASE 32'h8000_0000 - -program test_program; - - timeunit 1ns; - timeprecision 1ps; - - test_harness_env base_env; - - adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; - adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; - - bit [31:0] src_addr; - - initial begin - - //creating environment - base_env = new( - .name("Base Environment"), - .sys_clk_vip_if(`TH.`SYS_CLK.inst.IF), - .dma_clk_vip_if(`TH.`DMA_CLK.inst.IF), - .ddr_clk_vip_if(`TH.`DDR_CLK.inst.IF), - .sys_rst_vip_if(`TH.`SYS_RST.inst.IF), - .irq_base_address(`IRQ_C_BA), - .irq_vip_if(`TH.`IRQ.inst.inst.IF.vif)); - - mng = new("", `TH.`MNG_AXI.inst.IF); - ddr = new("", `TH.`DDR_AXI.inst.IF); - - `LINK(mng, base_env, mng) - `LINK(ddr, base_env, ddr) - - setLoggerVerbosity(ADI_VERBOSITY_NONE); - - base_env.start(); - `TH.`HBM_CLK.inst.IF.start_clock(); - base_env.sys_reset(); - -// // ------------------------------------------------------- -// // Test TX DMA and RX DMA in loopback -// // ------------------------------------------------------- -// -// // Init test data -// for (int i=0;i<2048*2 ;i=i+2) begin -// base_env.ddr.slave_sequencer.BackdoorWrite32(`DDR_BASE+src_addr+i*2,(((i+1)) << 16) | i ,'hF); -// end -// -// do_transfer( -// .src_addr(`DDR_BASE+'h0000), -// .dest_addr(`DDR_BASE+'h2000), -// .length('h1000) -// ); -// -// #20us; -// -// check_data( -// .src_addr(`DDR_BASE+'h0000), -// .dest_addr(`DDR_BASE+'h2000), -// .length('h1000) -// ); - - base_env.stop(); - `TH.`HBM_CLK.inst.IF.stop_clock(); - - `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); - $finish(); - - end - -// task do_transfer(bit [31:0] src_addr, -// bit [31:0] dest_addr, -// bit [31:0] length); -// -// // Configure TX DMA -// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_CONTROL), -// `SET_dmac_CONTROL_ENABLE(1)); -// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_FLAGS), -// `SET_dmac_FLAGS_TLAST(32'h00000006)); -// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_X_LENGTH), -// `SET_dmac_X_LENGTH_X_LENGTH(length-1)); -// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_SRC_ADDRESS), -// `SET_dmac_SRC_ADDRESS_SRC_ADDRESS(src_addr)); -// base_env.mng.master_sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), -// `SET_dmac_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); -// -// // Configure RX DMA -// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_CONTROL), -// `SET_dmac_CONTROL_ENABLE(1)); -// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_FLAGS), -// `SET_dmac_FLAGS_TLAST(32'h00000006)); -// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_X_LENGTH), -// `SET_dmac_X_LENGTH_X_LENGTH(length-1)); -// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_DEST_ADDRESS), -// `SET_dmac_DEST_ADDRESS_DEST_ADDRESS(dest_addr)); -// base_env.mng.master_sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), -// `SET_dmac_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); -// endtask -// -// -// // Check captured data -// task check_data(bit [31:0] src_addr, -// bit [31:0] dest_addr, -// bit [31:0] length); -// -// bit [31:0] current_dest_address; -// bit [31:0] current_src_address; -// bit [31:0] captured_word; -// bit [31:0] reference_word; -// -// for (int i=0;i - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - m_src_axi - m_src_axi - true - STYLE_ENUM_TRANSACTION - 0=blank 1=#D399FF 2=pink - 0=blank;1=Read;2=Write;3=Read/Write - true - turquoise - /system_tb/test_harness/dut_tx_dma/m_src_axi.readWriteSummary - UNSIGNEDDECRADIX - 36 - - - m_axis - m_axis - - - s_axis - s_axis - - - m_dest_axi - m_dest_axi - - - S_AXI - S_AXI - - diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv deleted file mode 100644 index ad9c8fda4..000000000 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv +++ /dev/null @@ -1,335 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2014-2018 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`include "utils.svh" - -import test_harness_env_pkg::*; -import adi_axi_agent_pkg::*; -import adi_regmap_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; -import logger_pkg::*; -import adi_regmap_dmac_pkg::*; -import adi_regmap_jesd_tx_pkg::*; -import adi_regmap_jesd_rx_pkg::*; -import adi_regmap_common_pkg::*; -import adi_regmap_dac_pkg::*; -import adi_regmap_adc_pkg::*; - -import `PKGIFY(test_harness, mng_axi_vip)::*; -import `PKGIFY(test_harness, ddr_axi_vip)::*; - -parameter RX_OUT_BYTES = (`RX_JESD_F % 3 != 0) ? (`JESD_MODE == "64B66B") ? 8 : 4 - : (`JESD_MODE == "64B66B") ? 12 : 6; -parameter TX_OUT_BYTES = (`TX_JESD_F % 3 != 0) ? (`JESD_MODE == "64B66B") ? 8 : 4 - : (`JESD_MODE == "64B66B") ? 12 : 6; - -`define CH_COUNT 4 - -program test_dma; - - timeunit 1ns; - timeprecision 1ps; - - test_harness_env base_env; - - adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; - adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; - - bit [31:0] link_clk_freq; - bit [31:0] device_clk_freq; - bit [31:0] sysref_freq; - int data_path_width; - int tpl_data_path_width; - - bit [31:0] lane_rate_khz = `RX_LANE_RATE*1000000; - longint lane_rate = lane_rate_khz*1000; - - reg timed_out; - - initial begin - - // There is no SYNC in 64B66B - int ref_sync_status = (`JESD_MODE != "64B66B"); - - // create environment - base_env = new( - .name("Base Environment"), - .sys_clk_vip_if(`TH.`SYS_CLK.inst.IF), - .dma_clk_vip_if(`TH.`DMA_CLK.inst.IF), - .ddr_clk_vip_if(`TH.`DDR_CLK.inst.IF), - .sys_rst_vip_if(`TH.`SYS_RST.inst.IF), - .irq_base_address(`IRQ_C_BA), - .irq_vip_if(`TH.`IRQ.inst.inst.IF.vif)); - - mng = new("", `TH.`MNG_AXI.inst.IF); - ddr = new("", `TH.`DDR_AXI.inst.IF); - - `LINK(mng, base_env, mng) - `LINK(ddr, base_env, ddr) - - setLoggerVerbosity(ADI_VERBOSITY_NONE); - - base_env.start(); - base_env.sys_reset(); - - if (`JESD_MODE != "64B66B") begin - link_clk_freq = lane_rate/40; - data_path_width = 4; - tpl_data_path_width = (`RX_JESD_NP==12) ? 6 : 4; - end else begin - link_clk_freq = lane_rate/66; - data_path_width = 8; - tpl_data_path_width = (`RX_JESD_NP==12) ? 12 : 8; - end - device_clk_freq = link_clk_freq * data_path_width / tpl_data_path_width; - sysref_freq = link_clk_freq*data_path_width/(`RX_JESD_K*`RX_JESD_F); - - `TH.`REF_CLK.inst.IF.set_clk_frq(.user_frequency(`REF_CLK_RATE*1000000)); - `TH.`DEVICE_CLK.inst.IF.set_clk_frq(.user_frequency(device_clk_freq)); - `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(sysref_freq)); - - `TH.`DRP_CLK.inst.IF.start_clock(); - `TH.`REF_CLK.inst.IF.start_clock(); - `TH.`DEVICE_CLK.inst.IF.start_clock(); - `TH.`SYSREF_CLK.inst.IF.start_clock(); - - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset(); - - #100ns; - `TH.`SYS_RST.inst.IF.deassert_reset(); - - #1us; - - // ------------------------------------------------------- - // Test DAC FIFO path - // ------------------------------------------------------- - - // Init test data - // - for (int i=0;i<1024;i=i+2) begin - base_env.ddr.slave_sequencer.BackdoorWrite32(`DDR_BA+i*2, - ((((i+1) % 1024)<<16) <<4) | ((i % 1024) << 4) , - 4'b1111); - end - - // Configure TX DMA - - base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), - `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), - `SET_DMAC_X_LENGTH_X_LENGTH(32'h00000FFF)); - base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), - `SET_DMAC_FLAGS_CYCLIC(1)); - base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), - `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA+32'h00000000)); - base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), - `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - - - // Configure Transport Layer to send DMA data on CH0-CH_COUNT-1 - for (int i=0;i<`CH_COUNT;i=i+1) begin - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+((30'h0106+('h10*i))<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); - // Enable Rx channel - base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+((30'h0100+('h10*i))<<2), - `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); - end - - - // Pull out TPL cores from reset - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_RSTN), - `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+GetAddrs(ADC_COMMON_REG_RSTN), - `SET_ADC_COMMON_REG_RSTN_RSTN(1)); - - // Sync DDS cores - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+GetAddrs(DAC_COMMON_REG_CNTRL_1), - `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); - - // - // Configure TX Link Layer - // - - //LINK DISABLE - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), - `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); - //SYSREFCONF - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_CONF), - `SET_JESD_TX_SYSREF_CONF_SYSREF_DISABLE(0)); - //CONF0 - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF0), - `SET_JESD_TX_LINK_CONF0_OCTETS_PER_FRAME(`TX_JESD_F-1) | - `SET_JESD_TX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`TX_JESD_F*`TX_JESD_K-1)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF4), - `SET_JESD_TX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`TX_JESD_F*`TX_JESD_K)/TX_OUT_BYTES-1)); - //CONF1 - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_CONF1), - `SET_JESD_TX_LINK_CONF1_SCRAMBLER_DISABLE(0)); - //LINK ENABLE - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), - `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); - // - // Configure RX Link Layer - // - - //LINK DISABLE - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), - `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - //SYSREFCONF - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_CONF), - `SET_JESD_RX_SYSREF_CONF_SYSREF_DISABLE(0)); - //CONF0 - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF0), - `SET_JESD_RX_LINK_CONF0_OCTETS_PER_FRAME(`RX_JESD_F-1) | - `SET_JESD_RX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`RX_JESD_F*`RX_JESD_K-1)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF4), - `SET_JESD_RX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`RX_JESD_F*`RX_JESD_K)/RX_OUT_BYTES-1)); - //CONF1 - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_CONF1), - `SET_JESD_RX_LINK_CONF1_DESCRAMBLER_DISABLE(0)); - //LINK ENABLE - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), - `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - - //XCVR INIT - //REG CTRL - if (`JESD_MODE != "64B66B") begin - base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA+32'h0020,32'h00001004); // RXOUTCLK uses DIV2 - base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA+32'h0020,32'h00001004); - - base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA+32'h0010,32'h00000001); - base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA+32'h0010,32'h00000001); - end - - // Wait until link is up - fork : timeout_f - begin - #25us; - `FATAL(("Link bringup wait Timeout")); - timed_out = '1; - end - join_none - wait(`TH.axi_mxfe_rx_jesd.rx.inst.buffer_release_n === 1'b0 || timed_out); - disable timeout_f; - - //Read status back - // Check SYSREF_STATUS - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_STATUS), - `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_STATUS), - `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - // Check if in DATA state and SYNC is 1 - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), - `SET_JESD_TX_LINK_STATUS_STATUS_STATE('h3)); - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), - `SET_JESD_TX_LINK_STATUS_STATUS_STATE('h3) | - `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(ref_sync_status)); - // Configure RX DMA - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), - `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), - `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), - `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003FF)); - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), - `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00001000)); - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), - `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - #5us; - for (int i=0;i<`CH_COUNT;i=i+1) begin - // Disable Rx channels - base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+((30'h0100+('h10*i))<<2), 32'h0000000); - end - #5us; - - check_captured_data( - .address (`DDR_BA+'h00001000), - .length (1024), - .step (1), - .max_sample(512) - ); - - //LINK DISABLE - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_DISABLE), - `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_DISABLE), - `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); - - - #2us; - - base_env.stop(); - - `TH.`DRP_CLK.inst.IF.stop_clock(); - `TH.`REF_CLK.inst.IF.stop_clock(); - `TH.`DEVICE_CLK.inst.IF.stop_clock(); - `TH.`SYSREF_CLK.inst.IF.stop_clock(); - - `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); - $finish(); - - end - - // Check captured data against incremental pattern based on first sample - // Pattern should be contiguous - task check_captured_data(bit [31:0] address, - int length = 1024, - int step = 1, - int max_sample = 2048 - ); - - bit [31:0] current_address; - bit [31:0] captured_word; - bit [31:0] reference_word; - bit [15:0] first; - - for (int i=0;i -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`include "utils.svh" - -import test_harness_env_pkg::*; -import adi_axi_agent_pkg::*; -import adi_regmap_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; -import logger_pkg::*; -import adi_regmap_dmac_pkg::*; -import adi_regmap_jesd_tx_pkg::*; -import adi_regmap_jesd_rx_pkg::*; -import adi_regmap_common_pkg::*; -import adi_regmap_dac_pkg::*; -import adi_regmap_adc_pkg::*; - -import `PKGIFY(test_harness, mng_axi_vip)::*; -import `PKGIFY(test_harness, ddr_axi_vip)::*; - -`define PHY121 32'h44A4_0000 -`define PHY125 32'h44A5_0000 - - -program test_program_64b66b; - - timeunit 1ns; - timeprecision 1ps; - - test_harness_env base_env; - - adi_axi_master_agent #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip)) mng; - adi_axi_slave_mem_agent #(`AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) ddr; - - int tmp; - - initial begin - - // create environment - base_env = new( - .name("Base Environment"), - .sys_clk_vip_if(`TH.`SYS_CLK.inst.IF), - .dma_clk_vip_if(`TH.`DMA_CLK.inst.IF), - .ddr_clk_vip_if(`TH.`DDR_CLK.inst.IF), - .sys_rst_vip_if(`TH.`SYS_RST.inst.IF), - .irq_base_address(`IRQ_C_BA), - .irq_vip_if(`TH.`IRQ.inst.inst.IF.vif)); - - mng = new("", `TH.`MNG_AXI.inst.IF); - ddr = new("", `TH.`DDR_AXI.inst.IF); - - `LINK(mng, base_env, mng) - `LINK(ddr, base_env, ddr) - - `TH.`DEVICE_CLK.inst.IF.start_clock(); - `TH.`REF_CLK.inst.IF.start_clock(); - `TH.`DRP_CLK.inst.IF.start_clock(); - `TH.`SYSREF_CLK.inst.IF.start_clock(); - - setLoggerVerbosity(ADI_VERBOSITY_NONE); - - base_env.start(); - base_env.sys_reset(); - - #1us; - base_env.mng.master_sequencer.RegRead32(`DAC_TPL_BA+'h0c,tmp); - `INFO(("DAC TPL CONFIG is %h",tmp), ADI_VERBOSITY_LOW); - base_env.mng.master_sequencer.RegRead32(`DAC_TPL_BA+'h418,tmp); - `INFO(("DAC TPL CH0 SEL is %h",tmp), ADI_VERBOSITY_LOW); - base_env.mng.master_sequencer.RegRead32(`DAC_TPL_BA+'h458,tmp); - `INFO(("DAC TPL CH1 SEL is %h",tmp), ADI_VERBOSITY_LOW); - - base_env.mng.master_sequencer.RegRead32(`RX_DMA_BA+32'h0010,tmp); - `INFO(("RX_DMA_BA interface setup is %h",tmp), ADI_VERBOSITY_LOW); - base_env.mng.master_sequencer.RegRead32(`TX_DMA_BA+32'h0010,tmp); - `INFO(("TX_DMA_BA interface setup is %h",tmp), ADI_VERBOSITY_LOW); - - // ------------------------------------------------------- - // Test DDS path - // ------------------------------------------------------- - - // Configure Transport Layer for DDS - // - - // Enable Rx channel CH0 - base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+(30'h0100<<2), - `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); - // Enable Rx channel CH31 - base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+(30'h02F0<<2), - `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); - - // Enable Rx channel CH63 - base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA+(30'h04F0<<2), - `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); - - // Select DDS as source CH0 - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h0106<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); - // Configure tone amplitude and frequency CH0 - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h0100<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h4000)); - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h0101<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h28f5)); - // Select DDS as source CH31 - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h02F6<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); - // Select DDS as source CH63 - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h04F6<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); - // Configure tone amplitude and frequency CH31 - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h02F0<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h4000)); - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h02F1<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h3333)); - // Configure tone amplitude and frequency CH63 - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h04F0<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(16'h02ff)); - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + (30'h04F1<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0020)); - - // Arm external sync - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), - `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); - base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_CNTRL), - `SET_ADC_COMMON_REG_CNTRL_SYNC(1)); - - - // Configure RX DMA - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), - `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), - `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003FF)); - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), - `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), - `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), - `SET_ADC_COMMON_REG_RSTN_RSTN(1)); - // Sync DDS cores - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), - `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); - - // - // Configure Link Layer - // - - //LINK DISABLE - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), - `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), - `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); - - //SYSREFCONF - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_CONF), - `SET_JESD_RX_SYSREF_CONF_SYSREF_DISABLE(0)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_CONF), - `SET_JESD_TX_SYSREF_CONF_SYSREF_DISABLE(0)); - //CONF0 - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF0), - `SET_JESD_TX_LINK_CONF0_OCTETS_PER_FRAME('h3) | - `SET_JESD_TX_LINK_CONF0_OCTETS_PER_MULTIFRAME('hff)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF0), - `SET_JESD_RX_LINK_CONF0_OCTETS_PER_FRAME('h3) | - `SET_JESD_RX_LINK_CONF0_OCTETS_PER_MULTIFRAME('hff)); - - //CONF1 - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF1), - `SET_JESD_TX_LINK_CONF1_SCRAMBLER_DISABLE(0)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF1), - `SET_JESD_RX_LINK_CONF1_DESCRAMBLER_DISABLE(0)); - //LINK ENABLE - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), - `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), - `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); - //enable near end loopback -// for (int i=0;i<8;i++) begin -// base_env.mng.master_sequencer.RegWrite32(`PHY121+32'h0024, i); -// base_env.mng.master_sequencer.RegWrite32(`PHY121+32'h041c, 32'h00000001); -// base_env.mng.master_sequencer.RegWrite32(`PHY125+32'h0024, i); -// base_env.mng.master_sequencer.RegWrite32(`PHY125+32'h041c, 32'h00000001); -// end - - //XCVR INIT - //REG CTRL -// base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA+32'h0020,32'h00001004); // RXOUTCLK uses DIV2 -// base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA+32'h0020,32'h00001004); - -// base_env.mng.master_sequencer.RegWrite32(`RX_XCVR_BA+32'h0010,32'h00000001); -// base_env.mng.master_sequencer.RegWrite32(`TX_XCVR_BA+32'h0010,32'h00000001); - - #35us; - - //Read status back - // Check SYSREF_STATUS - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_STATUS), - `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_STATUS), - `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); - - // Check if in DATA state - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), - `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), - `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); - - //LINK DISABLE - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), - `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), - `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - - // ------------------------------------------------------- - // Test DAC FIFO path - // ------------------------------------------------------- - - // Init test data - // - - for (int i=0;i<1024;i=i+2) begin - base_env.ddr.slave_sequencer.BackdoorWrite32(i*2,(((i+1)*16) << 16) | (i*16) ,15); - end - - // Arm external sync - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), - `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); - base_env.mng.master_sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_CNTRL), - `SET_ADC_COMMON_REG_CNTRL_SYNC(1)); - - // Configure RX DMA - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), - `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), - `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003FF)); - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), - `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - // Configure TX DMA - base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), - `SET_DMAC_CONTROL_ENABLE(1)); - base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), - `SET_DMAC_FLAGS_TLAST(1)); - base_env.mng.master_sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), - `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003FF)); - base_env.mng.master_sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), - `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - - - #5us; - - // Configure Transport Layer for DMA CH0 - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+(30'h0106<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); - // Configure Transport Layer for DMA CH31 - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+(30'h02F6<<2), - `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); - - // Enable broadcast of channel 0 to all others - for (int i = 1; i < 31; i++) begin - base_env.mng.master_sequencer.RegWrite32(`DAC_TPL_BA+((30'h0106<<2)+(i*'h40)), 32'h00010000); - end - - #1us; - - //LINK ENABLE - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), - `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); - base_env.mng.master_sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), - `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - - #35us; - - //Read status back - // Check SYSREF_STATUS - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_SYSREF_STATUS), - `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_SYSREF_STATUS), - `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); - #1us; - - // Check if in DATA state - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), - `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - base_env.mng.master_sequencer.RegReadVerify32(`AXI_JESD_TX_BA+GetAddrs(JESD_TX_LINK_STATUS), - `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); - #2us; - - base_env.stop(); - - `TH.`DRP_CLK.inst.IF.stop_clock(); - `TH.`REF_CLK.inst.IF.stop_clock(); - `TH.`DEVICE_CLK.inst.IF.stop_clock(); - `TH.`SYSREF_CLK.inst.IF.stop_clock(); - - `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); - $finish(); - - end - -endprogram