How to possibly fix the missing cell instruction disassembly ?

[scorpion81]

"Some cell specific instructions are currently not supported in Ghidra, these are the vector store/get lvlx etc, these appear in games and may break decompilation currently."

Which instructions are currently not supported in detail ? And is it possible to fix that by a ghidra extension or would you need to modifiy the core functionality for this ? Saw there are a few cspec and other files in the processor/powerpc subdirectory. Which ones would need to have which instructions added ?

I am currently struggeling a bit to disassemble a ps3 binary completely in ghidra utilizing the ps3 analyzer scripts as mentioned in the readme.
It looks like instruction opcodes 7D 80, 7D A0, 7C 00, 7C 20, 7C A0, 7C C0 and 7C F4 are affected. Are those the vector store/get instructions ?

If that is fixable locally either in the core of ghidra and / or an extension... could you give some hints what to change in order to fix it ?

[clienthax]

anything missing from the sleigh file, you'd have to refer to the cell documentation to confirm

[idmus00]

Here are some sleigh definitions for a few of the missing instructions, these aren't proper definitions but should allow Ghidra to translate the opcodes into pseudo-function calls and continue disassembly.

define pcodeop loadVectorLeftIndexed;
define pcodeop loadVectorLeftIndexedLast;
define pcodeop loadVectorRightIndexed;
define pcodeop loadVectorRightIndexedLast;
define pcodeop storeVectorLeftIndexed;
define pcodeop storeVectorLeftIndexedLast;
define pcodeop storeVectorRightIndexed;
define pcodeop storeVectorRightIndexedLast;

:lvlx vrD,RA_OR_ZERO,B			is OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=519 & Rc=0 {
	vrD = loadVectorLeftIndexed(RA_OR_ZERO,B);
}

:lvlxl vrD,RA_OR_ZERO,B			is OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=775 & Rc=0 {
	vrD = loadVectorLeftIndexedLast(RA_OR_ZERO,B);
}

:lvrx vrD,RA_OR_ZERO,B			is OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=551 & Rc=0 {
	vrD = loadVectorRightIndexed(RA_OR_ZERO,B);
}

:lvrxl vrD,RA_OR_ZERO,B			is OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=807 & Rc=0 {
	vrD = loadVectorRightIndexedLast(RA_OR_ZERO,B);
}

:stvlx vrS,RA_OR_ZERO,B			is OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=647 & Rc=0 {
  EA:$(REGISTER_SIZE) = RA_OR_ZERO + B;
	*[ram]:1 EA = storeVectorLeftIndexed(vrS, RA_OR_ZERO,B);
}

:stvlxl vrS,RA_OR_ZERO,B			is OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=903 & Rc=0 {
	EA:$(REGISTER_SIZE) = RA_OR_ZERO + B;
	*[ram]:1 EA = storeVectorLeftIndexedLast(vrS, RA_OR_ZERO,B);
}

:stvrx vrS,RA_OR_ZERO,B			is OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=679 & Rc=0 {
	EA:$(REGISTER_SIZE) = RA_OR_ZERO + B;
	*[ram]:1 EA = storeVectorRightIndexed(vrS, RA_OR_ZERO,B);
}

:stvrxl vrS,RA_OR_ZERO,B			is OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=935 & Rc=0 {
	EA:$(REGISTER_SIZE) = RA_OR_ZERO + B;
	*[ram]:1 EA = storeVectorRightIndexedLast(vrS, RA_OR_ZERO,B);
}

If you don't want / know how to create a new sleigh spec you can just append them to Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_be.slaspec, comment out the definitions for stvepx and stvepxl in ppc_isa.sinc, then compile the sleigh spec by running support/sleigh Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_be.