Run on an FPGA?

[mithro]

Have you tested Lizard on an FPGA at all? What type of resource usage do you think it would use? (How big is the number of gates in the ASIC flow?)

[cbatten]

We have pushed lizard through an ASIC toolflow for using FreePDK45 and the Nangate cells. The final MEng report that has a great deal of implementation detail on Lizard -- the report is linked from the README. I do think @orangeturtle739 and @wizard97 pushed it through Vivado but I think that was mainly for linting purposes. @orangeturtle739 and @wizard97 did you collect area stats from Vivado?

[wizard97]

You can push it through vivado targeting one of Xilinx's larger FPGAs by using the makefile in the fpga directory. Right now it only goes through synthesis because there are too many top-level io pins for Lizard's 2 64 bit memory ports. One needs to add a memory controller to the design to connect to these two memory ports. Last I checked, synthesis takes about 15k slice LUTs with the default parameters in config.py. The majority of resources end up being for synthesizing the data flow unit which holds the register file and the snapshot tables.

[mithro]

@wizard97 - Would you be interested in trying to add Lizard to LiteX so we could compare it to other RISC-V CPUs we support?

LiteX is an FPGA SoC generator that supports a wide range of FPGA boards and platforms. It currently support multiple soft-cpus, including multiple RISC-V implementations. You can find the details about supported CPUs on this wiki page -> https://github.com/enjoy-digital/litex/wiki/Soft-CPU

It would be awesome to see Lizard in the LiteX system. It would let us very easily compare the resource usage of Lizard to Black-Parrot, Rocket and VexRISCV.

LiteX-BuildEnv is my environment which uses LiteX to create images for many different FPGA boards. It supports Zephyr, Linux, Micropython and bare metal firmware.

You can find a diagram of this below;

There is also a Linux on LiteX VexRISCV repository which would be cool to port to use Lizard as an alternative option.

You can find the existing CPUs at https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu
Rocket is probably the closest configuration which can be found at https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/rocket/core.py

[orangeturtle739]

We are looking at litex. Also, Lizard does not support the privileged ISA, so cannot run Linux.

[mithro]

So, looks like it'll just be Bare Metal, Zephyr and MicroPython then?