From 891d849c6c43928be878dea3af5ffa4160a6bf5e Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 04:25:54 +0200 Subject: [PATCH 01/75] arch: Initial data structures for describing CPUID outputs These data structures will be used when generating CPU profiles and some are also necessary when applying a pre-generated profile. Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- arch/src/x86_64/cpuid_definitions/mod.rs | 96 ++++++++++++++++++++++++ arch/src/x86_64/mod.rs | 4 +- 2 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 arch/src/x86_64/cpuid_definitions/mod.rs diff --git a/arch/src/x86_64/cpuid_definitions/mod.rs b/arch/src/x86_64/cpuid_definitions/mod.rs new file mode 100644 index 0000000000..cc4fc911e9 --- /dev/null +++ b/arch/src/x86_64/cpuid_definitions/mod.rs @@ -0,0 +1,96 @@ +use std::ops::RangeInclusive; + +use serde::{Deserialize, Serialize}; + +use crate::x86_64::CpuidReg; + +/// Parameters for inspecting CPUID definitions. +#[derive(Debug, Clone, Eq, PartialEq, Serialize, Deserialize)] +pub struct Parameters { + // The leaf (EAX) parameter used with the CPUID instruction + pub leaf: u32, + // The sub-leaf (ECX) parameter used with the CPUID instruction + pub sub_leaf: RangeInclusive, + // The register we are interested in inspecting which gets filled by the CPUID instruction + pub register: CpuidReg, +} + +/// Describes a policy for how the corresponding CPUID data should be considered when building +/// a CPU profile. +#[derive(Debug, Copy, Clone, Eq, PartialEq)] +pub enum ProfilePolicy { + /// Store the corresponding data when building the CPU profile. + /// + /// When the CPU profile gets utilized the corresponding data will be set into the modified + /// CPUID instruction(s). + Inherit, + /// Ignore the corresponding data when building the CPU profile. + /// + /// When the CPU profile gets utilized the corresponding data will then instead get + /// extracted from the host. + /// + /// This variant is typically set for data that has no effect on migration compatibility, + /// but there may be some exceptions such as data which is necessary to run the VM at all, + /// but must coincide with whatever is on the host. + Passthrough, + /// Set the following hardcoded value in the CPU profile. + /// + /// This variant is typically used for features/values that don't work well with live migration (even when using the exact same physical CPU model) + Overwrite(u32), +} + +/// Describes how values within a CPUID output on two different hosts must relate to another in order for live-migration to be considered acceptable. +#[derive(Debug, Copy, Clone, Eq, PartialEq)] +pub enum MigrationCompatibilityRequirement { + /// The value must be equal. + Eq, + /// The target host must have at least the same bits set. + ContainsBits, + /// The target's value must be greater or equal to the source's. + GtEq, + /// The target's value must be less than or equal to the source's. + LtEq, + /// The value does not have to be compared. + Ignore, +} + +/// A description of a range of bits in a register populated by the CPUID instruction with specific parameters. +#[derive(Clone, Copy)] +pub struct ValueDefinition { + /// A short name for the value obtainable through CPUID + pub short: &'static str, + /// A description of the value obtainable through CPUID + pub description: &'static str, + /// The range of bits in the output register corresponding to this feature or value. + pub bits_range: (u8, u8), + /// The policy corresponding to this value when building CPU profiles. + pub policy: ProfilePolicy, + pub migration_compatibility_req: MigrationCompatibilityRequirement, +} + +/// Describes values within a register populated by the CPUID instruction with specific parameters. +/// +/// NOTE: The only way to interact with this value (beyond this crate) is via the const [`Self::as_slice()`](Self::as_slice) method. +pub struct ValueDefinitions(&'static [ValueDefinition]); +impl ValueDefinitions { + /// Constructor permitting less than 32 entries. + const fn new(cpuid_descriptions: &'static [ValueDefinition]) -> Self { + Self(cpuid_descriptions) + } + /// Converts this into a slice representation. This is the only way to read values of this type. + /// + // Altough, not necessary we prefer to annotate lifetimes in this case in order to simplify satefy analysis + pub const fn as_slice(&self) -> &'static [ValueDefinition] { + self.0 + } +} + +/// Describes multiple CPUID outputs. +/// +/// Each wraped [`ValueDefinitions`] corresponds to the given [`Parameters`] in the same tuple. +/// +// TODO: Consider introducing a const as_slice method to make it impossible for the parameter -> value definitions +// constraints being broken. +pub struct CpuidDefinitions( + pub [(Parameters, ValueDefinitions); NUM_PARAMETERS], +); diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index 648220e070..7edb0d03ab 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -7,6 +7,7 @@ // Use of this source code is governed by a BSD-style license that can be // found in the LICENSE-BSD-3-Clause file. use std::sync::Arc; +pub mod cpuid_definitions; pub mod interrupts; pub mod layout; mod mpspec; @@ -20,6 +21,7 @@ use linux_loader::loader::bootparam::{boot_params, setup_header}; use linux_loader::loader::elf::start_info::{ hvm_memmap_table_entry, hvm_modlist_entry, hvm_start_info, }; +use serde::{Deserialize, Serialize}; use thiserror::Error; use vm_memory::{ Address, Bytes, GuestAddress, GuestAddressSpace, GuestMemory, GuestMemoryAtomic, @@ -181,7 +183,7 @@ pub fn get_max_x2apic_id(topology: (u16, u16, u16, u16)) -> u32 { ) } -#[derive(Copy, Clone, Debug)] +#[derive(Copy, Clone, Debug, PartialEq, Eq, Serialize, Deserialize)] pub enum CpuidReg { EAX, EBX, From 664200c11464aba9d7736e64c670723e6c6c1728 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 04:39:38 +0200 Subject: [PATCH 02/75] hypervisor: Implement common traits for HypervisorType and CpuVendor We want CPU profiles to keep a record of the hypervisor type and cpu vendor that they are intended to work with. This is made more convenient if all of these types implement common traits (used for serialization). Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- hypervisor/src/cpu.rs | 2 +- hypervisor/src/lib.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hypervisor/src/cpu.rs b/hypervisor/src/cpu.rs index 519b99f567..251da88dc4 100644 --- a/hypervisor/src/cpu.rs +++ b/hypervisor/src/cpu.rs @@ -30,7 +30,7 @@ use crate::kvm::{TdxExitDetails, TdxExitStatus}; use crate::{CpuState, MpState, StandardRegisters}; #[cfg(target_arch = "x86_64")] -#[derive(Copy, Clone, Default)] +#[derive(Debug, Copy, Clone, Default, serde::Serialize, serde::Deserialize)] pub enum CpuVendor { #[default] Unknown, diff --git a/hypervisor/src/lib.rs b/hypervisor/src/lib.rs index 205691a421..3d980f0902 100644 --- a/hypervisor/src/lib.rs +++ b/hypervisor/src/lib.rs @@ -69,7 +69,7 @@ pub use vm::{ pub use crate::hypervisor::{Hypervisor, HypervisorError}; -#[derive(Debug, Copy, Clone)] +#[derive(Debug, Copy, Clone, serde::Serialize, serde::Deserialize)] pub enum HypervisorType { #[cfg(feature = "kvm")] Kvm, From 62bc2dd9ac424ffd024466e0b80526bfcb5fb40b Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 04:53:57 +0200 Subject: [PATCH 03/75] arch: CpuProfile data structures We introduce essential data structures together with basic functionality that is necessary to apply a CPU profile to a host. Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- arch/src/lib.rs | 30 ++++++++ arch/src/x86_64/cpu_profile.rs | 129 +++++++++++++++++++++++++++++++++ arch/src/x86_64/mod.rs | 1 + 3 files changed, 160 insertions(+) create mode 100644 arch/src/x86_64/cpu_profile.rs diff --git a/arch/src/lib.rs b/arch/src/lib.rs index 36fa20f13c..e5795d2585 100644 --- a/arch/src/lib.rs +++ b/arch/src/lib.rs @@ -11,10 +11,15 @@ #[macro_use] extern crate log; +#[cfg(target_arch = "x86_64")] +pub use crate::x86_64::cpu_profile::CpuProfile; + use std::collections::BTreeMap; +use std::str::FromStr; use std::sync::Arc; use std::{fmt, result}; +use serde::de::IntoDeserializer; use serde::{Deserialize, Serialize}; use thiserror::Error; @@ -56,6 +61,31 @@ pub enum Error { /// Type for returning public functions outcome. pub type Result = result::Result; +// If the target_arch is x86_64 we import CpuProfile from the x86_64 module, otherwise we +// declare it here. +#[cfg(not(target_arch = "x86_64"))] +#[derive(Debug, Default, Clone, Copy, PartialEq, Eq, serde::Serialize, serde::Deserialize)] +#[serde(rename_all = "kebab-case")] +/// A [`CpuProfile`] is a mechanism for ensuring live migration compatibility +/// between host's with potentially different CPU models. +pub enum CpuProfile { + #[default] + Host, +} + +impl FromStr for CpuProfile { + type Err = serde::de::value::Error; + fn from_str(s: &str) -> result::Result { + // Should accept both plain strings, and strings surrounded by `"`. + let normalized = s + .strip_prefix('"') + .unwrap_or(s) + .strip_suffix('"') + .unwrap_or(s); + Self::deserialize(normalized.into_deserializer()) + } +} + /// Type for memory region types. #[derive(Clone, Copy, PartialEq, Eq, Debug, Serialize, Deserialize)] pub enum RegionType { diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs new file mode 100644 index 0000000000..c1e9e5cbd1 --- /dev/null +++ b/arch/src/x86_64/cpu_profile.rs @@ -0,0 +1,129 @@ +use crate::x86_64::{CpuidReg, cpuid_definitions::Parameters}; +use hypervisor::arch::x86::CpuIdEntry; +use hypervisor::{CpuVendor, HypervisorType}; +use serde::{Deserialize, Serialize}; + +#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize, Default)] +#[serde(rename_all = "kebab-case")] +#[allow(non_camel_case_types)] +/// A [`CpuProfile`] is a mechanism for ensuring live migration compatibility +/// between host's with potentially different CPU models. +pub enum CpuProfile { + #[default] + Host, + /// Work in progress profile to test on when developing. + //TODO: Replace this with a feature gated x86-64-v1 variant that all x86_64 host's should satisfy. + // Having such a variant would be good for testing in CI, but should not become part of the shipped + // cloud hypervisor. + DevLaptop, +} + +impl CpuProfile { + // We can only generate CPU profiles for the KVM hypervisor for the time being. + #[cfg(feature = "kvm")] + pub(in crate::x86_64) fn data(&self) -> Option { + match self { + Self::Host => None, + Self::DevLaptop => todo!(), + } + } + + #[cfg(not(feature = "kvm"))] + pub(in crate::x86_64) fn data(&self) -> Option { + unimplemented!() + } +} + +/// Every [`CpuProfile`] different from `Host` has associated [`CpuProfileData`]. +/// +/// New constructors of this struct may only be generated through the CHV CLI (when built from source with +/// the `cpu-profile-generation` feature) which other hosts may then attempt to load in order to +/// increase the likelyhood of successful live migrations among all hosts that opted in to the given +/// CPU profile. +#[derive(Debug, Clone, Serialize, Deserialize)] +#[allow(dead_code)] +pub struct CpuProfileData { + /// The hypervisor used when generating this CPU profile. + pub(in crate::x86_64) hypervisor: HypervisorType, + /// The vendor of the CPU belonging to the host that generated this CPU profile. + pub(in crate::x86_64) cpu_vendor: CpuVendor, + /// Adjustments necessary to become compatible with the desired target. + pub(in crate::x86_64) adjustments: Vec<(Parameters, CpuidOutputRegisterAdjustments)>, + /// The result of adjusting the target host's default supported CPUID entries according + /// to CPU profile policy. + pub(in crate::x86_64) compatibility_target: Vec, +} + +/* TODO: The [`CpuProfile`] struct will likely need a few more iterations. The following +sections should explain why: + +# MSR restrictions + +CPU profiles also need to restrict which MSRs may be manipulated by the guest as various physical CPUs +can have differing supported MSRs. + +The CPU profile will thus necessarily need to contain some data related to MSR restrictions. That will +be taken care of in a follow up MR. + +# Raw hardware CPUID for advanced opt-in features + +Some more advanced CPU Features may either not be present when prompting the hypervisor for supported CPUID +enries (especially if this is done with the hypervisor in its default configuration), or may otherwise be +declared to be overwritten by all CPU profiles (as a safest default). + +We may still want to let users opt-in to using such features if permitted by the hardware and hypervisor +however. Hence we may also want the `CpuProfile` to contain all CPUID entries obtained directly from the +hardware of the host the profile was built from. + +This hardware information can then later be used on other hosts running under this pre-generated CPU +profile whenever the user wants to opt-in to more advanced CPU futures. If we can determine that the +feature is satisfied by both the hypervisor, the hardware of the host generating the profile, and the +current host then this should preserve live migration compatibility (unless the feature in inherently +incompatible with live migration of course). +*/ + +/// Used for adjusting an entire cpuid output register (EAX, EBX, ECX or EDX) +#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)] +pub(super) struct CpuidOutputRegisterAdjustments { + pub(in crate::x86_64) replacements: u32, + /// Used to zero out the area `replacements` occupy. This mask is not necessarily !replacements, as replacements may pack values of different types (i.e. it is wrong to think of it as a bitset conceptually speaking). + pub(in crate::x86_64) mask: u32, +} +impl CpuidOutputRegisterAdjustments { + pub(in crate::x86_64) fn adjust(self, cpuid_output_register: &mut u32) { + let temp_register_copy = *cpuid_output_register; + let replacements_area_masked_in_temp_copy = temp_register_copy & self.mask; + *cpuid_output_register = replacements_area_masked_in_temp_copy | self.replacements; + } + + pub(in crate::x86_64) fn adjust_cpuid_entries( + mut cpuid: Vec, + adjustments: &[(Parameters, Self)], + ) -> Vec { + for entry in &mut cpuid { + for (reg, reg_value) in [ + (CpuidReg::EAX, &mut entry.eax), + (CpuidReg::EBX, &mut entry.ebx), + (CpuidReg::ECX, &mut entry.ecx), + (CpuidReg::EDX, &mut entry.edx), + ] { + // Get the adjustment corresponding to the entry's function/leaf and index/sub-leaf for each of the register. If no such + // adjustment is found we use the trivial adjustment (leading to the register being zeroed out entirely). + let adjustment = adjustments + .iter() + .find_map(|(param, adjustment)| { + ((param.leaf == entry.function) + & param.sub_leaf.contains(&entry.index) + & (param.register == reg)) + .then_some(*adjustment) + }) + .unwrap_or(CpuidOutputRegisterAdjustments { + mask: 0, + replacements: 0, + }); + adjustment.adjust(reg_value); + } + } + cpuid + } +} diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index 7edb0d03ab..c8d7d49f2a 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -7,6 +7,7 @@ // Use of this source code is governed by a BSD-style license that can be // found in the LICENSE-BSD-3-Clause file. use std::sync::Arc; +pub mod cpu_profile; pub mod cpuid_definitions; pub mod interrupts; pub mod layout; From 0fd99c29bfa2130fc354b07284130b7cbb1b8d7d Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 05:34:22 +0200 Subject: [PATCH 04/75] misc: Make CPU profile part of various configs We integrate the CPU profile into the various configs that ultimately get set by the user. This quickly ends up involving multiple files, luckily Rust helps us find which ones via compilation errors. Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- arch/src/x86_64/mod.rs | 3 ++- src/main.rs | 1 + vmm/src/config.rs | 9 +++++++++ vmm/src/cpu.rs | 1 + vmm/src/lib.rs | 21 +++++++++++++++++---- vmm/src/vm.rs | 15 +++++++++------ vmm/src/vm_config.rs | 4 ++++ 7 files changed, 43 insertions(+), 11 deletions(-) diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index c8d7d49f2a..7ee535472d 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -29,7 +29,7 @@ use vm_memory::{ GuestMemoryRegion, }; -use crate::{GuestMemoryMmap, InitramfsConfig, RegionType}; +use crate::{CpuProfile, GuestMemoryMmap, InitramfsConfig, RegionType}; mod smbios; use std::arch::x86_64; #[cfg(feature = "tdx")] @@ -87,6 +87,7 @@ pub struct CpuidConfig { #[cfg(feature = "tdx")] pub tdx: bool, pub amx: bool, + pub profile: CpuProfile, } #[derive(Debug, Error)] diff --git a/src/main.rs b/src/main.rs index d096f28cb1..ef6b43ae8d 100644 --- a/src/main.rs +++ b/src/main.rs @@ -961,6 +961,7 @@ mod unit_tests { max_phys_bits: 46, affinity: None, features: CpuFeatures::default(), + profile: Default::default(), }, memory: MemoryConfig { size: 536_870_912, diff --git a/vmm/src/config.rs b/vmm/src/config.rs index 00d26ec881..6881b11216 100644 --- a/vmm/src/config.rs +++ b/vmm/src/config.rs @@ -11,6 +11,7 @@ use std::path::PathBuf; use std::result; use std::str::FromStr; +use arch::CpuProfile; use clap::ArgMatches; use option_parser::{ ByteSized, IntegerList, OptionParser, OptionParserError, StringList, Toggle, Tuple, @@ -597,6 +598,7 @@ impl CpusConfig { .add("kvm_hyperv") .add("max_phys_bits") .add("affinity") + .add("profile") .add("features"); parser.parse(cpus).map_err(Error::ParseCpus)?; @@ -629,6 +631,12 @@ impl CpusConfig { }) .collect() }); + + let profile = parser + .convert::("profile") + .map_err(Error::ParseCpus)? + .unwrap_or_default(); + let features_list = parser .convert::("features") .map_err(Error::ParseCpus)? @@ -660,6 +668,7 @@ impl CpusConfig { max_phys_bits, affinity, features, + profile, }) } } diff --git a/vmm/src/cpu.rs b/vmm/src/cpu.rs index ebdfbf478c..416bce5d45 100644 --- a/vmm/src/cpu.rs +++ b/vmm/src/cpu.rs @@ -812,6 +812,7 @@ impl CpuManager { #[cfg(feature = "tdx")] tdx, amx: self.config.features.amx, + profile: self.config.profile, }, ) .map_err(Error::CommonCpuId)? diff --git a/vmm/src/lib.rs b/vmm/src/lib.rs index 7ec33a23df..52d799797a 100644 --- a/vmm/src/lib.rs +++ b/vmm/src/lib.rs @@ -2149,17 +2149,26 @@ impl Vmm { ))); }; - let amx = vm_config.lock().unwrap().cpus.features.amx; - let phys_bits = - vm::physical_bits(&hypervisor, vm_config.lock().unwrap().cpus.max_phys_bits); + let (amx, phys_bits, profile, kvm_hyperv) = { + let guard = vm_config.lock().unwrap(); + let amx = guard.cpus.features.amx; + let max_phys_bits = guard.cpus.max_phys_bits; + let profile = guard.cpus.profile; + let kvm_hyperv = guard.cpus.kvm_hyperv; + // Drop lock before function call + core::mem::drop(guard); + let phys_bits = vm::physical_bits(&hypervisor, max_phys_bits); + (amx, phys_bits, profile, kvm_hyperv) + }; arch::generate_common_cpuid( &hypervisor, &arch::CpuidConfig { phys_bits, - kvm_hyperv: vm_config.lock().unwrap().cpus.kvm_hyperv, + kvm_hyperv, #[cfg(feature = "tdx")] tdx: false, amx, + profile, }, ) .map_err(|e| { @@ -2283,6 +2292,7 @@ impl Vmm { #[cfg(feature = "tdx")] tdx: false, amx: vm_config.cpus.features.amx, + profile: vm_config.cpus.profile, }, ) .map_err(|e| { @@ -3410,6 +3420,8 @@ const DEVICE_MANAGER_SNAPSHOT_ID: &str = "device-manager"; #[cfg(test)] mod unit_tests { + use arch::CpuProfile; + use super::*; #[cfg(target_arch = "x86_64")] use crate::vm_config::DebugConsoleConfig; @@ -3443,6 +3455,7 @@ mod unit_tests { max_phys_bits: 46, affinity: None, features: CpuFeatures::default(), + profile: CpuProfile::default(), }, memory: MemoryConfig { size: 536_870_912, diff --git a/vmm/src/vm.rs b/vmm/src/vm.rs index a776d0d943..aa981e226b 100644 --- a/vmm/src/vm.rs +++ b/vmm/src/vm.rs @@ -2893,19 +2893,22 @@ impl Snapshottable for Vm { #[cfg(all(feature = "kvm", target_arch = "x86_64"))] let common_cpuid = { - let amx = self.config.lock().unwrap().cpus.features.amx; - let phys_bits = physical_bits( - &self.hypervisor, - self.config.lock().unwrap().cpus.max_phys_bits, - ); + let guard = self.config.lock().unwrap(); + let amx = guard.cpus.features.amx; + let phys_bits = physical_bits(&self.hypervisor, guard.cpus.max_phys_bits); + let kvm_hyperv = guard.cpus.kvm_hyperv; + let profile = guard.cpus.profile; + // Drop the guard before function call + core::mem::drop(guard); arch::generate_common_cpuid( &self.hypervisor, &arch::CpuidConfig { phys_bits, - kvm_hyperv: self.config.lock().unwrap().cpus.kvm_hyperv, + kvm_hyperv, #[cfg(feature = "tdx")] tdx: false, amx, + profile, }, ) .map_err(|e| { diff --git a/vmm/src/vm_config.rs b/vmm/src/vm_config.rs index d7062e29ea..f7c9b4559b 100644 --- a/vmm/src/vm_config.rs +++ b/vmm/src/vm_config.rs @@ -8,6 +8,7 @@ use std::path::{Path, PathBuf}; use std::str::FromStr; use std::{fs, result}; +use arch::CpuProfile; use net_util::MacAddr; use serde::{Deserialize, Serialize}; use thiserror::Error; @@ -68,6 +69,8 @@ pub struct CpusConfig { pub affinity: Option>, #[serde(default)] pub features: CpuFeatures, + #[serde(default)] + pub profile: CpuProfile, } pub const DEFAULT_VCPUS: u32 = 1; @@ -82,6 +85,7 @@ impl Default for CpusConfig { max_phys_bits: DEFAULT_MAX_PHYS_BITS, affinity: None, features: CpuFeatures::default(), + profile: CpuProfile::default(), } } } From 4e0664b3d39778c4a981ac4d73d3af5c18fbd044 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 05:48:14 +0200 Subject: [PATCH 05/75] arch: Apply CPU profile (if any) when generating common CPUID If a CPU profile is configured it should result in guests seeing a restricted subset of CPUID. This is what we finally achieve in this commit. Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- arch/src/x86_64/mod.rs | 333 ++++++++++++++++++++++++----------------- 1 file changed, 197 insertions(+), 136 deletions(-) diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index 7ee535472d..f8f2e9e95a 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -16,6 +16,7 @@ mod mptable; pub mod regs; use std::mem; +use anyhow::Context; use hypervisor::arch::x86::{CPUID_FLAG_VALID_INDEX, CpuIdEntry}; use hypervisor::{CpuVendor, HypervisorCpuError, HypervisorError}; use linux_loader::loader::bootparam::{boot_params, setup_header}; @@ -29,6 +30,7 @@ use vm_memory::{ GuestMemoryRegion, }; +use crate::x86_64::cpu_profile::CpuidOutputRegisterAdjustments; use crate::{CpuProfile, GuestMemoryMmap, InitramfsConfig, RegionType}; mod smbios; use std::arch::x86_64; @@ -128,6 +130,10 @@ pub enum Error { #[error("Error getting supported CPUID through the hypervisor API")] CpuidGetSupported(#[source] HypervisorError), + /// Error when attempting to apply a CPU profile during common CPUID generation. + #[error("The desired CPU profile cannot be utilized due to an incompatibility issue")] + CpuProfileIncompatibility(#[source] anyhow::Error), + /// Error populating CPUID with KVM HyperV emulation details #[error("Error populating CPUID with KVM HyperV emulation details")] CpuidKvmHyperV(#[source] vmm_sys_util::fam::Error), @@ -283,7 +289,7 @@ impl CpuidPatch { } } - pub fn patch_cpuid(cpuid: &mut [CpuIdEntry], patches: Vec) { + pub fn patch_cpuid(cpuid: &mut [CpuIdEntry], patches: &[CpuidPatch]) { for entry in cpuid { for patch in patches.iter() { if entry.function == patch.function && entry.index == patch.index { @@ -615,167 +621,222 @@ pub fn generate_common_cpuid( }); } - // Supported CPUID - let mut cpuid = hypervisor + // Supported CPUID according to the host and hypervisor + let mut host_cpuid = hypervisor .get_supported_cpuid() .map_err(Error::CpuidGetSupported)?; - CpuidPatch::patch_cpuid(&mut cpuid, cpuid_patches); - - #[cfg(feature = "tdx")] - let tdx_capabilities = if config.tdx { - let caps = hypervisor - .tdx_capabilities() - .map_err(Error::TdxCapabilities)?; - info!("TDX capabilities {:#?}", caps); - Some(caps) - } else { - None + let use_custom_profile = config.profile != CpuProfile::Host; + // Obtain cpuid entries that are adjusted to the specified CPU profile and the cpuid entries of the compatibility target + // TODO: Try to write this in a clearer way + let (mut host_adjusted_to_profile, mut compatibility_target_cpuid) = { + config + .profile + .data() + .map(|profile_data| { + ( + Some(CpuidOutputRegisterAdjustments::adjust_cpuid_entries( + host_cpuid.clone(), + &profile_data.adjustments, + )), + Some(profile_data.compatibility_target), + ) + }) + .unwrap_or((None, None)) }; - // Update some existing CPUID - for entry in cpuid.as_mut_slice().iter_mut() { - match entry.function { - // Clear AMX related bits if the AMX feature is not enabled - 0x7 => { - if !config.amx && entry.index == 0 { - entry.edx &= !((1 << AMX_BF16) | (1 << AMX_TILE) | (1 << AMX_INT8)) - } + // We now make the modifications according to the config parameters to each of the cpuid entries + // declared above and then perform a compatibility check. + for cpuid_optiion in [ + Some(&mut host_cpuid), + host_adjusted_to_profile.as_mut(), + compatibility_target_cpuid.as_mut(), + ] { + let Some(mut cpuid) = cpuid_optiion else { + break; + }; + CpuidPatch::patch_cpuid(&mut cpuid, &cpuid_patches); + + #[cfg(feature = "tdx")] + let tdx_capabilities = if config.tdx { + if use_custom_profile { + // TODO: Enable TDX as an opt-in feature for custom CPU profiles as well. + return Err(Error::CpuProfileIncompatibility(anyhow::anyhow!( + "tdx capabilities are currently not supported for custom CPU profiles" + )) + .into()); } - 0xd => - { - #[cfg(feature = "tdx")] - if let Some(caps) = &tdx_capabilities { - let xcr0_mask: u64 = 0x82ff; - let xss_mask: u64 = !xcr0_mask; - if entry.index == 0 { - entry.eax &= (caps.xfam_fixed0 as u32) & (xcr0_mask as u32); - entry.eax |= (caps.xfam_fixed1 as u32) & (xcr0_mask as u32); - entry.edx &= ((caps.xfam_fixed0 & xcr0_mask) >> 32) as u32; - entry.edx |= ((caps.xfam_fixed1 & xcr0_mask) >> 32) as u32; - } else if entry.index == 1 { - entry.ecx &= (caps.xfam_fixed0 as u32) & (xss_mask as u32); - entry.ecx |= (caps.xfam_fixed1 as u32) & (xss_mask as u32); - entry.edx &= ((caps.xfam_fixed0 & xss_mask) >> 32) as u32; - entry.edx |= ((caps.xfam_fixed1 & xss_mask) >> 32) as u32; + let caps = hypervisor + .tdx_capabilities() + .map_err(Error::TdxCapabilities)?; + info!("TDX capabilities {:#?}", caps); + Some(caps) + } else { + None + }; + + // Update some existing CPUID + for entry in cpuid.as_mut_slice().iter_mut() { + match entry.function { + // Clear AMX related bits if the AMX feature is not enabled + 0x7 => { + if !config.amx && entry.index == 0 { + entry.edx &= !((1 << AMX_BF16) | (1 << AMX_TILE) | (1 << AMX_INT8)) } } - } - // Copy host L1 cache details if not populated by KVM - 0x8000_0005 => { - if entry.eax == 0 && entry.ebx == 0 && entry.ecx == 0 && entry.edx == 0 { - // SAFETY: cpuid called with valid leaves - if unsafe { std::arch::x86_64::__cpuid(0x8000_0000).eax } >= 0x8000_0005 { + 0xd => + { + #[cfg(feature = "tdx")] + if let Some(caps) = &tdx_capabilities { + let xcr0_mask: u64 = 0x82ff; + let xss_mask: u64 = !xcr0_mask; + if entry.index == 0 { + entry.eax &= (caps.xfam_fixed0 as u32) & (xcr0_mask as u32); + entry.eax |= (caps.xfam_fixed1 as u32) & (xcr0_mask as u32); + entry.edx &= ((caps.xfam_fixed0 & xcr0_mask) >> 32) as u32; + entry.edx |= ((caps.xfam_fixed1 & xcr0_mask) >> 32) as u32; + } else if entry.index == 1 { + entry.ecx &= (caps.xfam_fixed0 as u32) & (xss_mask as u32); + entry.ecx |= (caps.xfam_fixed1 as u32) & (xss_mask as u32); + entry.edx &= ((caps.xfam_fixed0 & xss_mask) >> 32) as u32; + entry.edx |= ((caps.xfam_fixed1 & xss_mask) >> 32) as u32; + } + } + } + // Copy host L1 cache details if not populated by KVM + 0x8000_0005 => { + if entry.eax == 0 && entry.ebx == 0 && entry.ecx == 0 && entry.edx == 0 { // SAFETY: cpuid called with valid leaves - let leaf = unsafe { std::arch::x86_64::__cpuid(0x8000_0005) }; - entry.eax = leaf.eax; - entry.ebx = leaf.ebx; - entry.ecx = leaf.ecx; - entry.edx = leaf.edx; + if unsafe { std::arch::x86_64::__cpuid(0x8000_0000).eax } >= 0x8000_0005 { + // SAFETY: cpuid called with valid leaves + let leaf = unsafe { std::arch::x86_64::__cpuid(0x8000_0005) }; + entry.eax = leaf.eax; + entry.ebx = leaf.ebx; + entry.ecx = leaf.ecx; + entry.edx = leaf.edx; + } } } - } - // Copy host L2 cache details if not populated by KVM - 0x8000_0006 => { - if entry.eax == 0 && entry.ebx == 0 && entry.ecx == 0 && entry.edx == 0 { - // SAFETY: cpuid called with valid leaves - if unsafe { std::arch::x86_64::__cpuid(0x8000_0000).eax } >= 0x8000_0006 { + // Copy host L2 cache details if not populated by KVM + 0x8000_0006 => { + if entry.eax == 0 && entry.ebx == 0 && entry.ecx == 0 && entry.edx == 0 { // SAFETY: cpuid called with valid leaves - let leaf = unsafe { std::arch::x86_64::__cpuid(0x8000_0006) }; - entry.eax = leaf.eax; - entry.ebx = leaf.ebx; - entry.ecx = leaf.ecx; - entry.edx = leaf.edx; + if unsafe { std::arch::x86_64::__cpuid(0x8000_0000).eax } >= 0x8000_0006 { + // SAFETY: cpuid called with valid leaves + let leaf = unsafe { std::arch::x86_64::__cpuid(0x8000_0006) }; + entry.eax = leaf.eax; + entry.ebx = leaf.ebx; + entry.ecx = leaf.ecx; + entry.edx = leaf.edx; + } } } - } - // Set CPU physical bits - 0x8000_0008 => { - entry.eax = (entry.eax & 0xffff_ff00) | (config.phys_bits as u32 & 0xff); - } - 0x4000_0001 => { - // Enable KVM_FEATURE_MSI_EXT_DEST_ID. This allows the guest to target - // device interrupts to cpus with APIC IDs > 254 without interrupt remapping. - entry.eax |= 1 << KVM_FEATURE_MSI_EXT_DEST_ID; - - // These features are not supported by TDX - #[cfg(feature = "tdx")] - if config.tdx { - entry.eax &= !((1 << KVM_FEATURE_CLOCKSOURCE_BIT) - | (1 << KVM_FEATURE_CLOCKSOURCE2_BIT) - | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) - | (1 << KVM_FEATURE_ASYNC_PF_BIT) - | (1 << KVM_FEATURE_ASYNC_PF_VMEXIT_BIT) - | (1 << KVM_FEATURE_STEAL_TIME_BIT)) + // Set CPU physical bits + 0x8000_0008 => { + entry.eax = (entry.eax & 0xffff_ff00) | (config.phys_bits as u32 & 0xff); } + 0x4000_0001 => { + // Enable KVM_FEATURE_MSI_EXT_DEST_ID. This allows the guest to target + // device interrupts to cpus with APIC IDs > 254 without interrupt remapping. + entry.eax |= 1 << KVM_FEATURE_MSI_EXT_DEST_ID; + + // These features are not supported by TDX + #[cfg(feature = "tdx")] + if config.tdx { + entry.eax &= !((1 << KVM_FEATURE_CLOCKSOURCE_BIT) + | (1 << KVM_FEATURE_CLOCKSOURCE2_BIT) + | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) + | (1 << KVM_FEATURE_ASYNC_PF_BIT) + | (1 << KVM_FEATURE_ASYNC_PF_VMEXIT_BIT) + | (1 << KVM_FEATURE_STEAL_TIME_BIT)) + } + } + _ => {} } - _ => {} } - } - // Copy CPU identification string - for i in 0x8000_0002..=0x8000_0004 { - cpuid.retain(|c| c.function != i); - // SAFETY: call cpuid with valid leaves - let leaf = unsafe { std::arch::x86_64::__cpuid(i) }; - cpuid.push(CpuIdEntry { - function: i, - eax: leaf.eax, - ebx: leaf.ebx, - ecx: leaf.ecx, - edx: leaf.edx, - ..Default::default() - }); - } + // Copy CPU identification string + /* + TODO: Do we want to do this in the case of CPU profiles? + */ + for i in 0x8000_0002..=0x8000_0004 { + cpuid.retain(|c| c.function != i); + // SAFETY: call cpuid with valid leaves + let leaf = unsafe { std::arch::x86_64::__cpuid(i) }; + cpuid.push(CpuIdEntry { + function: i, + eax: leaf.eax, + ebx: leaf.ebx, + ecx: leaf.ecx, + edx: leaf.edx, + ..Default::default() + }); + } - if config.kvm_hyperv { - // Remove conflicting entries - cpuid.retain(|c| c.function != 0x4000_0000); - cpuid.retain(|c| c.function != 0x4000_0001); - // See "Hypervisor Top Level Functional Specification" for details - // Compliance with "Hv#1" requires leaves up to 0x4000_000a - cpuid.push(CpuIdEntry { - function: 0x40000000, - eax: 0x4000000a, // Maximum cpuid leaf - ebx: 0x756e694c, // "Linu" - ecx: 0x564b2078, // "x KV" - edx: 0x7648204d, // "M Hv" - ..Default::default() - }); - cpuid.push(CpuIdEntry { - function: 0x40000001, - eax: 0x31237648, // "Hv#1" - ..Default::default() - }); - cpuid.push(CpuIdEntry { - function: 0x40000002, - eax: 0x3839, // "Build number" - ebx: 0xa0000, // "Version" - ..Default::default() - }); - cpuid.push(CpuIdEntry { - function: 0x4000_0003, - eax: (1 << 1) // AccessPartitionReferenceCounter + if config.kvm_hyperv { + // Remove conflicting entries + cpuid.retain(|c| c.function != 0x4000_0000); + cpuid.retain(|c| c.function != 0x4000_0001); + // See "Hypervisor Top Level Functional Specification" for details + // Compliance with "Hv#1" requires leaves up to 0x4000_000a + cpuid.push(CpuIdEntry { + function: 0x40000000, + eax: 0x4000000a, // Maximum cpuid leaf + ebx: 0x756e694c, // "Linu" + ecx: 0x564b2078, // "x KV" + edx: 0x7648204d, // "M Hv" + ..Default::default() + }); + cpuid.push(CpuIdEntry { + function: 0x40000001, + eax: 0x31237648, // "Hv#1" + ..Default::default() + }); + cpuid.push(CpuIdEntry { + function: 0x40000002, + eax: 0x3839, // "Build number" + ebx: 0xa0000, // "Version" + ..Default::default() + }); + cpuid.push(CpuIdEntry { + function: 0x4000_0003, + eax: (1 << 1) // AccessPartitionReferenceCounter | (1 << 2) // AccessSynicRegs | (1 << 3) // AccessSyntheticTimerRegs | (1 << 9), // AccessPartitionReferenceTsc - edx: 1 << 3, // CPU dynamic partitioning - ..Default::default() - }); - cpuid.push(CpuIdEntry { - function: 0x4000_0004, - eax: 1 << 5, // Recommend relaxed timing - ..Default::default() - }); - for i in 0x4000_0005..=0x4000_000a { + edx: 1 << 3, // CPU dynamic partitioning + ..Default::default() + }); cpuid.push(CpuIdEntry { - function: i, + function: 0x4000_0004, + eax: 1 << 5, // Recommend relaxed timing ..Default::default() }); + for i in 0x4000_0005..=0x4000_000a { + cpuid.push(CpuIdEntry { + function: i, + ..Default::default() + }); + } } } - - Ok(cpuid) + if !use_custom_profile { + Ok(host_cpuid) + } else { + // Final compatibility checks to ensure that the CPUID values we return are compatible both with the CPU profile and the host we are currently running on. + let host_adjusted_to_profile = host_adjusted_to_profile.expect("The profile adjusted cpuid entries should exist as we checked that we have a custom CPU profile"); + let target_compatible_cpuid = compatibility_target_cpuid.expect("The target_compatible_cpuid entries should exist as we checked that we have a custom CPU profile"); + // Check that the host's cpuid is indeed compatible with the adjusted profile. This is not by construction. + + CpuidFeatureEntry::check_cpuid_compatibility(&host_adjusted_to_profile, &host_cpuid).context("Unable to adjust the host to the CPU profile. The resulting cpuid is not compatible with the host's cpuid entries").map_err(Error::CpuProfileIncompatibility)?; + // Check that the compatibility target's cpuid is compatible with the adjusted host's (the converse is satisfied by construction). + // The adjusted host will always have a CPUID that is compatible with the compatibility target (in terms of live migration requirements), but the other direction needs to be checked. + CpuidFeatureEntry::check_cpuid_compatibility( + &target_compatible_cpuid, + &host_adjusted_to_profile, + ).context("The CPU profile's compatibility target has non-trivial CPUID entries not found on this host").map_err(Error::CpuProfileIncompatibility)?; + Ok(host_adjusted_to_profile) + } } pub fn configure_vcpu( @@ -1419,7 +1480,7 @@ fn update_cpuid_topology( edx_bit: Some(28), }, ]; - CpuidPatch::patch_cpuid(cpuid, cpuid_patches); + CpuidPatch::patch_cpuid(cpuid, &cpuid_patches); CpuidPatch::set_cpuid_reg( cpuid, 0x8000_0008, From 222862a9462bd86f5fc93091b56c767591ee1d2f Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 05:59:59 +0200 Subject: [PATCH 06/75] arch: Profile generation logic We want to generate CPU profiles by running a CLI tool on the host that is to be the profile's compatibility target. This commit prepares for such a tool by introducing most of the generation logic, but the necessary dependencies will be introduced in a follow up commit. Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- Cargo.lock | 1 + arch/Cargo.toml | 4 + arch/src/x86_64/cpu_profile_generation.rs | 187 ++++++++++++++++++++++ arch/src/x86_64/mod.rs | 2 + 4 files changed, 194 insertions(+) create mode 100644 arch/src/x86_64/cpu_profile_generation.rs diff --git a/Cargo.lock b/Cargo.lock index 1989a0e18b..998dfb6f3c 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -115,6 +115,7 @@ dependencies = [ "linux-loader", "log", "serde", + "serde_json", "thiserror 2.0.12", "uuid", "vm-fdt", diff --git a/arch/Cargo.toml b/arch/Cargo.toml index 804be793d0..9f98d55e24 100644 --- a/arch/Cargo.toml +++ b/arch/Cargo.toml @@ -10,6 +10,8 @@ fw_cfg = [] kvm = ["hypervisor/kvm"] sev_snp = [] tdx = [] +# Currently cpu profiles can only be generated with KVM +cpu_profile_generation = ["kvm"] [dependencies] anyhow = { workspace = true } @@ -19,6 +21,8 @@ libc = { workspace = true } linux-loader = { workspace = true, features = ["bzimage", "elf", "pe"] } log = { workspace = true } serde = { workspace = true, features = ["derive", "rc"] } +# We currently use this for (de-)serializing CPU profile data +serde_json = { workspace = true } thiserror = { workspace = true } uuid = { workspace = true } vm-memory = { workspace = true, features = ["backend-bitmap", "backend-mmap"] } diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs new file mode 100644 index 0000000000..a06dc238ef --- /dev/null +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -0,0 +1,187 @@ +use crate::x86_64::CpuidReg; +#[cfg(feature = "kvm")] +use crate::x86_64::cpuid_definitions::CpuidDefinitions; +use crate::x86_64::{ + CpuidOutputRegisterAdjustments, + cpu_profile::CpuProfileData, + cpuid_definitions::{Parameters, ProfilePolicy}, +}; + +use anyhow::Context; +use hypervisor::CpuVendor; +use hypervisor::Hypervisor; +use hypervisor::HypervisorType; +use hypervisor::arch::x86::CpuIdEntry; +use std::io::Write; +use std::ops::RangeInclusive; + +/// Computes [`CpuProfileData`] based on the given sorted vector of CPUID entries, hypervisor type, cpu_vendor +/// and cpuid_definitions. +/// +/// The computed [`CpuProfileData`] is then converted to a string representation, embeddable as Rust code, which is +/// then written by the given `writer`. +/// +// TODO: Consider making a snapshot test or two for this function. +fn generate_cpu_profile_data_with( + hypervisor_type: HypervisorType, + cpu_vendor: CpuVendor, + supported_cpuid_sorted: Vec, + processor_cpuid_definitions: &CpuidDefinitions, + hypervisor_cpuid_definitions: &CpuidDefinitions, + mut writer: &mut impl Write, +) -> anyhow::Result<()> { + let mut adjustments: Vec<(Parameters, CpuidOutputRegisterAdjustments)> = Vec::new(); + + for (parameter, values) in processor_cpuid_definitions + .0 + .iter() + .chain(hypervisor_cpuid_definitions.0.iter()) + { + for (sub_leaf_range, maybe_matching_register_output_value) in + extract_parameter_matches(parameter, &supported_cpuid_sorted) + { + // If the compatibility target (current host) has multiple sub-leaves matching the parameter's range + // then we want to specialize: + let mut mask: u32 = 0; + let mut replacements: u32 = 0; + for value in values.as_slice() { + // Reality check on the bit range listed in `value` + { + assert!(value.bits_range.0 <= value.bits_range.1); + assert!(value.bits_range.1 < 32); + } + + match value.policy { + ProfilePolicy::Passthrough => { + // The profile should take whatever we get from the host, hence there is no adjustment, but our + // mask needs to retain all bits in the range of bits corresponding to this value + let (first_bit_pos, last_bit_pos) = value.bits_range; + mask |= bit_range_mask(first_bit_pos, last_bit_pos); + } + ProfilePolicy::Overwrite(overwrite_value) => { + replacements |= overwrite_value << value.bits_range.0; + } + ProfilePolicy::Inherit => { + // The value is supposed to be obtained from the compatibility target if it exists + let (first_bit_pos, last_bit_pos) = value.bits_range; + if let Some(matching_register_value) = maybe_matching_register_output_value + { + let extraction_mask = bit_range_mask(first_bit_pos, last_bit_pos); + let value = matching_register_value & extraction_mask; + replacements |= value; + } + } + } + } + adjustments.push(( + Parameters { + leaf: parameter.leaf, + sub_leaf: sub_leaf_range, + register: parameter.register, + }, + CpuidOutputRegisterAdjustments { mask, replacements }, + )); + } + } + + let compatibility_target_cpuid = + CpuidOutputRegisterAdjustments::adjust_cpuid_entries(supported_cpuid_sorted, &adjustments); + + let profile_data = CpuProfileData { + hypervisor: hypervisor_type, + cpu_vendor, + adjustments, + compatibility_target: compatibility_target_cpuid, + }; + + serde_json::to_writer(&mut writer, &profile_data) + .context("failed to serialize the generated profile data to the given writer")?; + writer + .flush() + .context("CPU profile generation failed: Unable to flush cpu profile data") +} + +/// Get the supported CPUID entries from the hypervisor and make sure that they are sorted by function and index +fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result> { + hypervisor + .get_supported_cpuid() + .context("CPU profile data generation failed") + .map(sort_entries) +} + +fn sort_entries(mut cpuid: Vec) -> Vec { + cpuid.sort_by(|entry, other_entry| { + let fn_cmp = entry.function.cmp(&other_entry.function); + if fn_cmp == core::cmp::Ordering::Equal { + entry.index.cmp(&other_entry.index) + } else { + fn_cmp + } + }); + cpuid +} +/// Returns a `u32` where each bit between `first_bit_pos` and `last_bit_pos` is set (including both ends) and all other bits are 0. +fn bit_range_mask(first_bit_pos: u8, last_bit_pos: u8) -> u32 { + let ones_until_last_bit_pos = u32::MAX >> (32 - last_bit_pos - 1); + let ones_until_but_not_including_first_bit_pos = (1_u32 << first_bit_pos) - 1; + let mask = ones_until_last_bit_pos & (!ones_until_but_not_including_first_bit_pos); + // Reality checks + { + assert_eq!( + u8::try_from(mask.count_ones()).unwrap(), + (last_bit_pos - first_bit_pos) + 1 + ); + assert_eq!( + mask.checked_shr(u32::from(last_bit_pos) + 1).unwrap_or(0), + 0 + ); + assert_eq!(u8::try_from(mask.trailing_zeros()).unwrap(), first_bit_pos); + } + mask +} + +/// Returns a vector of exact parameter matches ((sub_leaf ..= sub_leaf), register_value) interleaved by +/// the sub_leaf ranges specified by `param` that did not match any cpuid entry. +fn extract_parameter_matches( + param: &Parameters, + supported_cpuid_sorted: &[CpuIdEntry], +) -> Vec<(RangeInclusive, Option)> { + let register_value = |entry: &CpuIdEntry| -> u32 { + match param.register { + CpuidReg::EAX => entry.eax, + CpuidReg::EBX => entry.ebx, + CpuidReg::ECX => entry.ecx, + CpuidReg::EDX => entry.edx, + } + }; + let mut out = Vec::new(); + let param_range = param.sub_leaf.clone(); + let mut range_for_consideration = param_range.clone(); + let range_end = *range_for_consideration.end(); + for sub_leaf_entry in supported_cpuid_sorted + .iter() + .filter(|entry| entry.function == param.leaf && param_range.contains(&entry.index)) + { + let matching_subleaf = sub_leaf_entry.index; + + // If we are in the middle of the range, it means there is no entry matching the first few sub-leaves within the range + let current_range_start = *range_for_consideration.start(); + if current_range_start < matching_subleaf { + let range_not_matching = RangeInclusive::new(current_range_start, matching_subleaf - 1); + out.push((range_not_matching, None)); + } + + out.push(( + RangeInclusive::new(matching_subleaf, matching_subleaf), + Some(register_value(sub_leaf_entry)), + )); + if matching_subleaf == range_end { + return out; + } + // Update range_for_consideration: Note that we must have index + 1 <= range_end + range_for_consideration = RangeInclusive::new(matching_subleaf + 1, range_end); + } + // We did not find the last entry within the range hence we push the final range for consideration together with no matching register value + out.push((range_for_consideration, None)); + out +} diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index f8f2e9e95a..b7c82afbc0 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -8,6 +8,8 @@ // found in the LICENSE-BSD-3-Clause file. use std::sync::Arc; pub mod cpu_profile; +#[cfg(feature = "cpu_profile_generation")] +pub mod cpu_profile_generation; pub mod cpuid_definitions; pub mod interrupts; pub mod layout; From 3816b3ab0793e51289904f3d24d366df7f319d15 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 06:13:32 +0200 Subject: [PATCH 07/75] arch: CPUID definitions: intel & kvm We prepare for CPU profile generation by introducing the missing dependencies: The CPUID definitions declaring what to do with the CPUIDs we obtain from the compatibility target (the host CPU we want to become live-migration compatible with). Note that the "short", description and migration compatibility requirement fields will not be used in this PR, but they are there to help reviewers and auditors understand why certain profile policies are set. Furthermore these additional fields could become useful in the future. The migration compatibility requirements could for instance be used to generate more thorough live migration checks, and the short and long descriptions could be utilized for better diagnostics. Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- .../x86_64/cpuid_definitions/hypervisor.rs | 228 +++ arch/src/x86_64/cpuid_definitions/intel.rs | 1814 +++++++++++++++++ arch/src/x86_64/cpuid_definitions/mod.rs | 8 +- 3 files changed, 2049 insertions(+), 1 deletion(-) create mode 100644 arch/src/x86_64/cpuid_definitions/hypervisor.rs create mode 100644 arch/src/x86_64/cpuid_definitions/intel.rs diff --git a/arch/src/x86_64/cpuid_definitions/hypervisor.rs b/arch/src/x86_64/cpuid_definitions/hypervisor.rs new file mode 100644 index 0000000000..889d6a8605 --- /dev/null +++ b/arch/src/x86_64/cpuid_definitions/hypervisor.rs @@ -0,0 +1,228 @@ +//! This module contains CPUID definitions with leaves in the range reserved for hypervisors (0x4000_0000, 0x4FFF_FFFF). + +use std::ops::RangeInclusive; + +use crate::x86_64::CpuidReg; +use crate::x86_64::cpuid_definitions::{ + CpuidDefinitions, MigrationCompatibilityRequirement, Parameters, ProfilePolicy, + ValueDefinition, ValueDefinitions, +}; + +/// CPUID features defined for the KVM hypervisor. +/// +/// See https://www.kernel.org/doc/html/latest/virt/kvm/x86/cpuid.html +pub const KVM_CPUID_DEFINITIONS: CpuidDefinitions<6> = const { + CpuidDefinitions([ + //===================================================================== + // KVM CPUID Signature + // =================================================================== + ( + Parameters { + leaf: 0x4000_0000, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "max_hypervisor_leaf", + description: "The maximum valid leaf between 0x4000_0000 and 0x4FFF_FFF", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x4000_0000, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "hypervisor_string_ebx", + description: "Part of the hypervisor string", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0x4000_0000, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "hypervisor_string_ecx", + description: "Part of the hypervisor string", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0x4000_0000, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "hypervisor_string_edx", + description: "Part of the hypervisor string", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + //===================================================================== + // KVM CPUID Features + // =================================================================== + ( + Parameters { + leaf: 0x4000_0001, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "kvm_feature_clocksource", + description: "kvmclock available at MSRs 0x11 and 0x12", + bits_range: (0, 0), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_nop_io_delay", + description: "Not necessary to perform delays on PIO operations", + bits_range: (1, 1), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_mmu_op", + description: "Deprecated", + bits_range: (2, 2), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_clocksource2", + description: "kvmclock available at MSRs 0x4b564d00 and 0x4b564d01", + bits_range: (3, 3), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_async_pf", + description: "async pf can be enabled by writing to MSR 0x4b564d02", + bits_range: (4, 4), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_steal_time", + description: "steal time can be enabled by writing to msr 0x4b564d03", + bits_range: (5, 5), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_pv_eoi", + description: "paravirtualized end of interrupt handler can be enabled by writing to msr 0x4b564d04", + bits_range: (6, 6), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_pv_unhalt", + description: "guest checks this feature bit before enabling paravirtualized spinlock support", + bits_range: (7, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_pv_tlb_flush", + description: "guest checks this feature bit before enabling paravirtualized tlb flush", + bits_range: (9, 9), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_async_pf_vmexit", + description: "paravirtualized async PF VM EXIT can be enabled by setting bit 2 when writing to msr 0x4b564d02", + bits_range: (10, 10), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_pv_send_ipi", + description: "guest checks this feature bit before enabling paravirtualized send IPIs", + bits_range: (11, 11), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_poll_control", + description: "host-side polling on HLT can be disabled by writing to msr 0x4b564d05.", + bits_range: (12, 12), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_pv_sched_yield", + description: "guest checks this feature bit before using paravirtualized sched yield.", + bits_range: (13, 13), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_async_pf_int", + description: "guest checks this feature bit before using the second async pf control msr 0x4b564d06 and async pf acknowledgment msr 0x4b564d07.", + bits_range: (14, 14), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_msi_ext_dest_id", + description: "guest checks this feature bit before using extended destination ID bits in MSI address bits 11-5.", + bits_range: (15, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_hc_map_gpa_range", + description: "guest checks this feature bit before using the map gpa range hypercall to notify the page state change", + bits_range: (16, 16), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_migration_control", + description: "guest checks this feature bit before using MSR_KVM_MIGRATION_CONTROL", + bits_range: (17, 17), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "kvm_feature_clocksource_stable_bit", + description: "host will warn if no guest-side per-cpu warps are expected in kvmclock", + bits_range: (24, 24), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x4000_0001, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "kvm_hints_realtime", + description: "guest checks this feature bit to determine that vCPUs are never preempted for an unlimited time allowing optimizations", + bits_range: (0, 0), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + ]) +}; diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs new file mode 100644 index 0000000000..90c6ef506e --- /dev/null +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -0,0 +1,1814 @@ +//! This module contains CPUID definitions for Intel CPUs. +use std::ops::RangeInclusive; + +use super::{ValueDefinition, ValueDefinitions, CpuidDefinitions, CpuidReg, MigrationCompatibilityRequirement, Parameters, ProfilePolicy}; + +pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { + CpuidDefinitions([ + + // ========================================================================================= + // Basic CPUID Information + // ========================================================================================= + ( + Parameters{ leaf: 0x0, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "max_std_leaf", description: "Maximum Input value for Basic CPUID Information", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + ( + Parameters{ leaf: 0x0, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_vendorid_0", description: "CPU vendor ID string bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0x0, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_vendorid_2", description: "CPU vendor ID string bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq}, + ]) + ), + + ( + Parameters{ leaf: 0x0, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_vendorid_1", description: "CPU vendor ID string bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq}, + ]) + ), + + // TODO: Do we really want to inherit these values from the corresponding CPU, or should we zero it out or set something else here? + ( + Parameters{ leaf: 0x1, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "stepping", description: "Stepping ID", bits_range: (0, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "base_model", description: "Base CPU model ID", bits_range: (4, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "base_family_id", description: "Base CPU family ID", bits_range: (8, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "cpu_type", description: "CPU type", bits_range: (12, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "ext_model", description: "Extended CPU model ID", bits_range: (16, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "ext_family", description: "Extended CPU family ID", bits_range: (20, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x1, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "brand_id", description: "Brand index", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "clflush_size", description: "CLFLUSH instruction cache line size", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + // TODO: The logical CPU count may be relevant for live migration whenever pinning has been set up, but the pinning setup needs to make these checks and we don't set a general requirement here (at least for now) + ValueDefinition{ short: "n_logical_cpu", description: "Logical CPU count", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + // TODO: Not sure about which policy to set for local_apic_id + ValueDefinition{ short: "local_apic_id", description: "Initial local APIC physical ID", bits_range: (24, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x1, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "sse3", description: "Streaming SIMD Extensions 3 (SSE3)", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pclmulqdq", description: "PCLMULQDQ instruction support", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + // TODO: This seems to be debug related hence we set it to 0 for CPU profiles. Is this a good choice? + ValueDefinition{ short: "dtes64", description: "64-bit DS save area", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Perhaps there should be some CHV feature for opting in to enabling this for non-host CPU profiles? + ValueDefinition{ short: "monitor", description: "MONITOR/MWAIT support", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ds_cpl", description: "CPL Qualified Debug Store", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + // TODO: Is this a good default? Might be useful for nested virtualization ... + ValueDefinition{ short: "vmx", description: "Virtual Machine Extensions", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: We choose to disable it for all CPU profiles for now. It is also not set for any CPU model in QEMU from what we can tell. + ValueDefinition{ short: "smx", description: "Safer Mode Extensions", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "est", description: "Enhanced Intel SpeedStep", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "tm2", description: "Thermal Monitor 2", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ssse3", description: "Supplemental SSE3", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: It seems like this can only have performance implications, and nothing else. It would probably also be OK to ignore this when checking migration compatibility + ValueDefinition{ short: "cid", description: "L1 Context ID", bits_range: (10, 10), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "sdbg", description: "Silicon Debug", bits_range: (11, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "fma", description: "FMA extensions using YMM state", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cx16", description: "CMPXCHG16B instruction support", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xtpr", description: "xTPR Update Control", bits_range: (14, 14), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pdcm", description: "Perfmon and Debug Capability", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pcid", description: "Process-context identifiers", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "dca", description: "Direct Cache Access", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "sse4_1", description: "SSE4.1", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "sse4_2", description: "SSE4.2", bits_range: (20, 20), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Needs special support from KVM (See: https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-cpuid) and must be setup separately. I think this may be on by default in QEMU for all models? + // Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? + ValueDefinition{ short: "x2apic", description: "X2APIC support", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "movbe", description: "MOVBE instruction support", bits_range: (22, 22), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "popcnt", description: "POPCNT instruction support", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Needs special support from KVM (See: https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-cpuid) and must be setup separately (NOTE: CHV is currently setting this unconditionally though. why?) + // Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? + ValueDefinition{ short: "tsc_deadline_timer", description: "APIC timer one-shot operation", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "aes", description: "AES instructions", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xsave", description: "XSAVE (and related instructions) support", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Seems to no longer be supported by QEMU, but is by KVM? We disable this for now. + ValueDefinition{ short: "osxsave", description: "XSAVE (and related instructions) are enabled by OS", bits_range: (27, 27), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx", description: "AVX instructions support", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "f16c", description: "Half-precision floating-point conversion support", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "rdrand", description: "RDRAND instruction support", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "guest_status", description: "System is running as guest; (para-)virtualized system", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x1, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "fpu", description: "Floating-Point Unit on-chip (x87)", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "vme", description: "Virtual-8086 Mode Extensions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "de", description: "Debugging Extensions", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pse", description: "Page Size Extension", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Does this also need special handling like TSC_DEADLINE_TIMER? + ValueDefinition{ short: "tsc", description: "Time Stamp Counter", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "msr", description: "Model-Specific Registers (RDMSR and WRMSR support)", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pae", description: "Physical Address Extensions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "mce", description: "Machine Check Exception", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cx8", description: "CMPXCHG8B instruction", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Does this also require special handling like x2apic? + ValueDefinition{ short: "apic", description: "APIC on-chip", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "sep", description: "SYSENTER, SYSEXIT, and associated MSRs", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "mtrr", description: "Memory Type Range Registers", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pge", description: "Page Global Extensions", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "mca", description: "Machine Check Architecture", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cmov", description: "Conditional Move Instruction", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pat", description: "Page Attribute Table", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pse36", description: "Page Size Extension (36-bit)", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pn", description: "Processor Serial Number", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Could an untrusted guest potentially slow down other guests with this feature? + ValueDefinition{ short: "clflush", description: "CLFLUSH instruction", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "dts", description: "Debug Store", bits_range: (21, 21), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "acpi", description: "Thermal monitor and clock control", bits_range: (22, 22), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: MMX is deprecated as far as we know. Should we consider setting this to 0 by default for all CPU profiles? + ValueDefinition{ short: "mmx", description: "MMX instructions", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "fxsr", description: "FXSAVE and FXRSTOR instructions", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "sse", description: "SSE instructions", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "sse2", description: "SSE2 instructions", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure if we should support self snoop for CPU profiles. Qemu does though... + ValueDefinition{ short: "ss", description: "Self Snoop", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Perhaps this needs to be configured purely through CPU features/Options instead? (Also seems to be related to CPU topology) + ValueDefinition{ short: "htt", description: "Hyper-threading", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "tm", description: "Thermal Monitor", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not really sure what the default should be for PBE. It seems like it is something that needs to be enabled via the IA32_MISC_ENABLE MSR hence perhaps this should be set via CPU features? + ValueDefinition{ short: "pbe", description: "Pending Break Enable", bits_range: (31, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // ========================================================================================= + // Cache and TLB Information + // ========================================================================================= + ( + Parameters{ leaf: 0x2, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "iteration_count", description: "Number of times this leaf must be queried", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc1", description: "Descriptor #1", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc2", description: "Descriptor #2", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc3", description: "Descriptor #3", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "eax_invalid", description: "Descriptors 1-3 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ]) + ), + + ( + Parameters{ leaf: 0x2, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "desc4", description: "Descriptor #4", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc5", description: "Descriptor #5", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc6", description: "Descriptor #6", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc7", description: "Descriptor #7", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "ebx_invalid", description: "Descriptors 4-7 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ]) + ), + + ( + Parameters{ leaf: 0x2, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "desc8", description: "Descriptor #8", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc9", description: "Descriptor #9", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc10", description: "Descriptor #10", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc11", description: "Descriptor #11", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "ecx_invalid", description: "Descriptors 8-11 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ]) + ), + + ( + Parameters{ leaf: 0x2, sub_leaf: RangeInclusive::new(0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "desc12", description: "Descriptor #12", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc13", description: "Descriptor #13", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc14", description: "Descriptor #14", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "desc15", description: "Descriptor #15", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ValueDefinition{ short: "edx_invalid", description: "Descriptors 12-15 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ]) + ), + // ========================================================================================= + // Deterministic Cache Parameters + // ========================================================================================= + ( + Parameters{ leaf: 0x4, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cache_type", description: "Cache type field", bits_range: (0, 4), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "cache_level", description: "Cache level (1-based)", bits_range: (5, 7), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + // TODO: Could there be a problem migrating from a CPU with self-initializing cache to one without? + ValueDefinition{ short: "cache_self_init", description: "Self-initializing cache level", bits_range: (8, 8), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "fully_associative", description: "Fully-associative cache", bits_range: (9, 9), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "num_threads_sharing", description: "Number logical CPUs sharing this cache", bits_range: (14, 25), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "num_cores_on_die", description: "Number of cores in the physical package", bits_range: (26, 31), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x4, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cache_linesize", description: "System coherency line size (0-based)", bits_range: (0, 11), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "cache_npartitions", description: "Physical line partitions (0-based)", bits_range: (12, 21), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "cache_nways", description: "Ways of associativity (0-based)", bits_range: (22, 31), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x4, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cache_nsets", description: "Cache number of sets (0-based)", bits_range: (0, 30), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x4, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "wbinvd_rll_no_guarantee", description: "WBINVD/INVD not guaranteed for Remote Lower-Level caches", bits_range: (0, 0), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "ll_inclusive", description: "Cache is inclusive of Lower-Level caches", bits_range: (1, 1), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "complex_indexing", description: "Not a direct-mapped cache (complex function)", bits_range: (2, 2), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // ========================================================================================= + // MONITOR/MWAIT + // ========================================================================================= + + ( + Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + // TODO: Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? + ValueDefinition{ short: "min_mon_size", description: "Smallest monitor-line size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::LtEq }, + ]) + ), + + ( + Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + // TODO: Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? + ValueDefinition{ short: "max_mon_size", description: "Largest monitor-line size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + ( + Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "mwait_ext", description: "Enumeration of MONITOR/MWAIT extensions is supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? + ValueDefinition{ short: "mwait_irq_break", description: "Interrupts as a break-event for MWAIT is supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "n_c0_substates", description: "Number of C0 sub C-states supported using MWAIT", bits_range: (0, 3), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c1_substates", description: "Number of C1 sub C-states supported using MWAIT", bits_range: (4, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c2_substates", description: "Number of C2 sub C-states supported using MWAIT", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c3_substates", description: "Number of C3 sub C-states supported using MWAIT", bits_range: (12, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c4_substates", description: "Number of C4 sub C-states supported using MWAIT", bits_range: (16, 19), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c5_substates", description: "Number of C5 sub C-states supported using MWAIT", bits_range: (20, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c6_substates", description: "Number of C6 sub C-states supported using MWAIT", bits_range: (24, 27), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c7_substates", description: "Number of C7 sub C-states supported using MWAIT", bits_range: (28, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // ========================================================================================= + // Thermal and Power Management + // ========================================================================================= + + ( + Parameters{ leaf: 0x6, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "dtherm", description: "Digital temperature sensor", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "turbo_boost", description: "Intel Turbo Boost", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "arat", description: "Always-Running APIC Timer (not affected by p-state)", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "pln", description: "Power Limit Notification (PLN) event", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ecmd", description: "Clock modulation duty cycle extension", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pts", description: "Package thermal management", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp", description: "HWP (Hardware P-states) base registers are supported", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp_notify", description: "HWP notification (IA32_HWP_INTERRUPT MSR)", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp_act_window", description: "HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported", bits_range: (9, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp_epp", description: "HWP Energy Performance Preference", bits_range: (10, 10), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp_pkg_req", description: "HWP Package Level Request", bits_range: (11, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hdc_base_regs", description: "HDC base registers are supported", bits_range: (13, 13), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "turbo_boost_3_0", description: "Intel Turbo Boost Max 3.0", bits_range: (14, 14), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp_capabilities", description: "HWP Highest Performance change", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp_peci_override", description: "HWP PECI override", bits_range: (16, 16), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp_flexible", description: "Flexible HWP", bits_range: (17, 17), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp_fast", description: "IA32_HWP_REQUEST MSR fast access mode", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hfi", description: "HW_FEEDBACK MSRs supported", bits_range: (19, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hwp_ignore_idle", description: "Ignoring idle logical CPU HWP req is supported", bits_range: (20, 20), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "thread_director", description: "Intel thread director support", bits_range: (23, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "therm_interrupt_bit25", description: "IA32_THERM_INTERRUPT MSR bit 25 is supported", bits_range: (24, 24), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x6, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + // TODO: Do we perhaps need some requirement for migration compatibility here? + ValueDefinition{ short: "n_therm_thresholds", description: "Digital thermometer thresholds", bits_range: (0, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x6, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "aperfmperf", description: "MPERF/APERF MSRs (effective frequency interface)", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "epb", description: "IA32_ENERGY_PERF_BIAS MSR support", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about the defaults for this one, but I think since we have disabled thread director support (0x6 EAX bit 23) we can probably just passthrough whatever here and. Not sure about migration compatibility (for the Host profile) though. + ValueDefinition{ short: "thrd_director_nclasses", description: "Number of classes, Intel thread director", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x6, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "perfcap_reporting", description: "Performance capability reporting", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "encap_reporting", description: "Energy efficiency capability reporting", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "feedback_sz", description: "Feedback interface structure size, in 4K pages", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "this_lcpu_hwfdbk_idx", description: "This logical CPU hardware feedback interface index", bits_range: (16, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // =================================================================================================================== + // Structured Extended Feature Flags Enumeration Main Leaf + // =================================================================================================================== + + ( + Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "leaf7_n_subleaves", description: "Number of leaf 0x7 subleaves", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + ( + Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "fsgsbase", description: "FSBASE/GSBASE read/write support", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "tsc_adjust", description: "IA32_TSC_ADJUST MSR supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // SGX is deprecated so we disable it unconditionally for all CPU profiles + ValueDefinition{ short: "sgx", description: "Intel SGX (Software Guard Extensions)", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "bmi1", description: "Bit manipulation extensions group 1", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TSX related which is riddled with CVEs + ValueDefinition{ short: "hle", description: "Hardware Lock Elision", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx2", description: "AVX2 instruction set", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + /*The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). + + Keep in mind however that in my limited understanding this isn't about enabling or disabling a feature, but it describes critical behaviour. + Hence I am wondering whether it should be a hard error if the host does not have this bit set, but the desired CPU profile does? */ + ValueDefinition{ short: "fdp_excptn_only", description: "FPU Data Pointer updated only on x87 exceptions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "smep", description: "Supervisor Mode Execution Protection", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "bmi2", description: "Bit manipulation extensions group 2", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "erms", description: "Enhanced REP MOVSB/STOSB", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + /* + The instruction enabled by this seems rather powerful. Are we sure that doesn't have security implications? + I included this because it seems like QEMU does (to the best of my understanding). + */ + ValueDefinition{ short: "invpcid", description: "INVPCID instruction (Invalidate Processor Context ID)", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // This is TSX related from what I can tell. TSX is riddled with CVEs hence we disable this + ValueDefinition{ short: "rtm", description: "Intel restricted transactional memory", bits_range: (11, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "rdt_m", description: "Supports Intel Resource Director Technology Monitoring Capability if 1", bits_range: (12, 12), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). TODO: Is it OK to just set this to 1? + ValueDefinition{ short: "zero_fcs_fds", description: "Deprecates FPU CS and FPU DS values if 1", bits_range: (13, 13), policy: ProfilePolicy::Overwrite(1), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // This has been deprecated + ValueDefinition{ short: "mpx", description: "Intel memory protection extensions", bits_range: (14, 14), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // This might be useful for certain high performance applications, but it also seems like a rather niche and advanced feature. QEMU does also not automatically enable this from what we can tell. + // TODO: Should we make this OPT-IN? + ValueDefinition{ short: "rdt_a", description: "Intel RDT-A. Supports Intel Resource Director Technology Allocation Capability if 1", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Do the wider avx512 zmm registers work out of the box when the hardware supports it? + ValueDefinition{ short: "avx512f", description: "AVX-512 foundation instructions", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512dq", description: "AVX-512 double/quadword instructions", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "rdseed", description: "RDSEED instruction", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "adx", description: "ADCX/ADOX instructions", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "smap", description: "Supervisor mode access prevention", bits_range: (20, 20), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512ifma", description: "AVX-512 integer fused multiply add", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "clflushopt", description: "CLFLUSHOPT instruction", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "clwb", description: "CLWB instruction", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "intel_pt", description: "Intel processor trace", bits_range: (25, 25), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512pf", description: "AVX-512 prefetch instructions", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512er", description: "AVX-512 exponent/reciprocal instructions", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512cd", description: "AVX-512 conflict detection instructions", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "sha_ni", description: "SHA/SHA256 instructions", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512bw", description: "AVX-512 byte/word instructions", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512vl", description: "AVX-512 VL (128/256 vector length) extensions", bits_range: (31, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "prefetchwt1", description: "PREFETCHWT1 (Intel Xeon Phi only)", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512vbmi", description: "AVX-512 Vector byte manipulation instructions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + // Also set by QEMU for CPU models from what we can tell + ValueDefinition{ short: "umip", description: "User mode instruction protection", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + // Also set by QEMU for CPU models from what we can tell + ValueDefinition{ short: "pku", description: "Protection keys for user-space", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // Presumably this is set by the OS? TODO: Set applicability of the migration check to never + ValueDefinition{ short: "ospke", description: "OS protection keys enable", bits_range: (4, 4), policy: ProfilePolicy::Passthrough , migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // QEMU seems to set this unconditionally whenever KVM supports it (TODO: Would it be best to also set this unconditionally?) + ValueDefinition{ short: "waitpkg", description: "WAITPKG instructions", bits_range: (5, 5), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "avx512_vbmi2", description: "AVX-512 vector byte manipulation instructions group 2", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: This may be useful for nested virtualization? Perhaps it should be opt-in rather than unconditionally disabled? + ValueDefinition{ short: "cet_ss", description: "CET shadow stack features", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "gfni", description: "Galois field new instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "vaes", description: "Vector AES instructions", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "vpclmulqdq", description: "VPCLMULQDQ 256-bit instruction support", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512_vnni", description: "Vector neural network instructions", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512_bitalg", description: "AVX-512 bitwise algorithms", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // Seems to be TDX related which is experimental in CHV. We disable this for CPU profiles for now, but could potentially add it as an opt-in feature eventually. + ValueDefinition{ short: "tme", description: "Intel total memory encryption", bits_range: (13, 13), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + + ValueDefinition{ short: "avx512_vpopcntdq", description: "AVX-512: POPCNT for vectors of DWORD/QWORD", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "la57", description: "57-bit linear addresses (five-level paging)", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MMX is deprecated, but we should perhaps still check for equality here when migrating + ValueDefinition{ short: "mawau_val_lm", description: "BNDLDX/BNDSTX MAWAU value in 64-bit mode", bits_range: (17, 21), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "rdpid", description: "RDPID instruction", bits_range: (22, 22), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + // We leave key locker support out for CPU profiles for the time being. We may want this to be opt-in in the future though + ValueDefinition{ short: "key_locker", description: "Intel key locker support", bits_range: (23, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "bus_lock_detect", description: "OS bus-lock detection", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + /* + TODO: Should this be off by default? Can untrusted guests potentially abuse this to slow down other guests? + According to https://www.felixcloutier.com/x86/cldemote : + > On processors which do not support the CLDEMOTE instruction (including legacy hardware) the instruction will be treated as a NOP. + This suggests that is should even be fine to migrate from a host with this feature to one which does not have it. + TODO: Set migrationcheck applicability to never + */ + ValueDefinition{ short: "cldemote", description: "CLDEMOTE instruction", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "movdiri", description: "MOVDIRI instruction", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "movdir64b", description: "MOVDIR64B instruction", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + /* + This could be important for nested virtualization and perhaps for certain other applications. It does not seem to be enabled for CPU models in QEMU however, hence we + also leave it out for now, but should reconsider if/how to add it in the future. + */ + ValueDefinition{ short: "enqcmd", description: "Enqueue stores supported (ENQCMD{,S})", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // SGX support is deprecated so we disable it unconditionally for CPU profiles + ValueDefinition{ short: "sgx_lc", description: "Intel SGX launch configuration", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + /* + I was not able to find much information on this feature. It seems like QEMU can emulate it, but does not set if for any available CPU model as far as I can tell. + It also seems to be mainly relevant for hosts and not guests (except perhaps for nested virtualization). + */ + ValueDefinition{ short: "pks", description: "Protection keys for supervisor-mode pages", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + // SGX is deprecated + ValueDefinition{ short: "sgx_keys", description: "Intel SGX attestation services", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512_4vnniw", description: "AVX-512 neural network instructions (Intel Xeon Phi only?)", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512_4fmaps", description: "AVX-512 multiply accumulation single precision (Intel Xeon Phi only?)", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "fsrm", description: "Fast short REP MOV", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: To me this seems very powerful and I am wondering if it can be abused by guests. Is it indeed right to disable this for all CPU profiles as I expect we should? + ValueDefinition{ short: "uintr", description: "CPU supports user interrupts", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512_vp2intersect", description: "VP2INTERSECT{D,Q} instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: This seems to be CVE related and we should investigate this more thoroughly + ValueDefinition{ + short: "srdbs_ctrl", + description: "SRBDS mitigation MSR available: If 1, enumerates support for the IA32_MCU_OPT_CTRL MSR and indicates that its bit 0 (RNGDS_MITG_DIS) is also supported.", + bits_range: (9, 9), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits + }, + // TODO: This seems to be CVE related and should be checked more carefully: See https://www.kernel.org/doc/html/next/x86/mds.html#microarchitectural-data-sampling-mds-mitigation + ValueDefinition{ short: "md_clear", description: "VERW MD_CLEAR microcode support", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: This seems to be CVE related and should be checked more carefully + ValueDefinition{ short: "rtm_always_abort", description: "XBEGIN (RTM transaction) always aborts", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: This seems to be CVE related and should be checked more carefully + ValueDefinition{ short: "tsx_force_abort", description: "MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "serialize", description: "SERIALIZE instruction", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure what to set here. I am guessing CPU profiles should not exist for hybrid CPUs in the first place (at least not for now). + ValueDefinition{ short: "hybrid_cpu", description: "The CPU is identified as a 'hybrid part'", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: This is TSX related which is riddled with CVEs. We should carefully decide what to do with regards to this feature. + ValueDefinition{ short: "tsxldtrk", description: "TSX suspend/resume load address tracking", bits_range: (16, 16), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // Seems rather complex. We disable it unconditionally for CPU profiles for now. + // TODO: Remember to set any other pconfig dependency to ony apply if this is set + ValueDefinition{ short: "pconfig", description: "PCONFIG instruction", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // Seems to be mainly useful for debugging and monitoring, which are classes of features we tend to avoid advertising to the guest. + ValueDefinition{ short: "arch_lbr", description: "Intel architectural LBRs", bits_range: (19, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure if this is the best default, but QEMU also seems to disable this for CPU models + ValueDefinition{ short: "ibt", description: "CET indirect branch tracking", bits_range: (20, 20), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_bf16", description: "AMX-BF16: tile bfloat16 support", bits_range: (22, 22), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512_fp16", description: "AVX-512 FP16 instructions", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_tile", description: "AMX-TILE: tile architecture support", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "amx_int8", description: "AMX-INT8: tile 8-bit integer support", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Seems to be CVE related and should be checked more thoroughly + ValueDefinition{ short: "spec_ctrl", description: "Speculation Control (IBRS/IBPB: indirect branch restrictions)", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: This is CVE related and should be checked more thoroughly + ValueDefinition{ short: "intel_stibp", description: "Single thread indirect branch predictors", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Is it a good default to leave this out for CPU profiles. Do we perhaps need an option to opt-in? + ValueDefinition{ short: "flush_l1d", description: "FLUSH L1D cache: IA32_FLUSH_CMD MSR", bits_range: (28, 28), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Really not sure what policies to set for this one + ValueDefinition{ short: "arch_capabilities", description: "Intel IA32_ARCH_CAPABILITIES MSR", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Is this a good default for CPU profiles? + ValueDefinition{ short: "core_capabilities", description: "IA32_CORE_CAPABILITIES MSR", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Spectre related. Should be checked carefully + ValueDefinition{ short: "spec_ctrl_ssbd", description: "Speculative store bypass disable", bits_range: (31, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Structured Extended Feature Flags Enumeration Sub-Leaf 1 + // =================================================================================================================== + ( + Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "sha512", description: "SHA-512 extensions", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "sm3", description: "SM3 instructions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "sm4", description: "SM4 instructions", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // RAO-INT is deprecated and removed from most compilers as far as we are aware + ValueDefinition{ short: "RAO-INT", description: "RAO-INT instructions", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx_vnni", description: "AVX-VNNI instructions", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx512_bf16", description: "AVX-512 bfloat16 instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + /* + Not set in QEMU from what we can tell, but according seems to be fine to expose this to guests + if we understood https://www.phoronix.com/news/Intel-Linux-LASS-KVM correctly. It is also + our understanding that this feature can enable guests opting in to more security (possibly at the cost of some performance). + */ + ValueDefinition{ short: "lass", description: "Linear address space separation", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cmpccxadd", description: "CMPccXADD instructions", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "arch_perfmon_ext", description: "ArchPerfmonExt: leaf 0x23 is supported", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "fzrm", description: "Fast zero-length REP MOVSB", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "fsrs", description: "Fast short REP STOSB", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "fsrc", description: "Fast Short REP CMPSB/SCASB", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // Not sure if not setting this is a good default. It is our understanding that QEMU doesn't enable this for CPU models, but CHV does set this unconditionally for all guests? + ValueDefinition{ short: "fred", description: "FRED: Flexible return and event delivery transitions", bits_range: (17, 17), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // Not sure if not setting this is a good default. It is our understanding that QEMU doesn't enable this for CPU models, but CHV does set this unconditionally for all guests? + ValueDefinition{ short: "lkgs", description: "LKGS: Load 'kernel' (userspace) GS", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // QEMU also seems to not set this for CPU models + ValueDefinition{ short: "wrmsrns", description: "WRMSRNS instruction (WRMSR-non-serializing)", bits_range: (19, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "nmi_src", description: "NMI-source reporting with FRED event data", bits_range: (20, 20), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "amx_fp16", description: "AMX-FP16: FP16 tile operations", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "hreset", description: "History reset support", bits_range: (22, 22), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx_ifma", description: "Integer fused multiply add", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // Seems to be related to spectre and should be checked carefully + ValueDefinition{ short: "lam", description: "Linear address masking", bits_range: (26, 26), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure if not setting this is the best default. I think that is also what QEMU does though. + ValueDefinition{ short: "rd_wr_msrlist", description: "RDMSRLIST/WRMSRLIST instructions", bits_range: (27, 27), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about this one + ValueDefinition{ short: "invd_disable_post_bios_done", description: "If 1, supports INVD execution prevention after BIOS Done", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: This feature does not exist yet as far as we know + ValueDefinition{ short: "movrs", description: "MOVRS", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + // TODO: Is disabling this a good default for CPU profiles? + ValueDefinition{ short: "intel_ppin", description: "Protected processor inventory number (PPIN{,_CTL} MSRs)", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // We zero this out for CPU profiles for the time being + ValueDefinition{ short: "pbndkb", description: "PBNDKB instruction supported and enumerates the existence of the IA32_TSE_CAPABILITY MSR", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // TODO: Missing entry for (0x7, 1, ECX) + // + // TODO: Double check the AVX VNNI instructions + ( + Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "avx_vnni_int8", description: "AVX-VNNI-INT8 instructions", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx_ne_convert", description: "AVX-NE-CONVERT instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the value will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinition{ short: "amx_complex", description: "AMX-COMPLEX instructions (starting from Granite Rapids)", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "avx_vnni_int16", description: "AVX-VNNI-INT16 instructions", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about this one. TODO: THe current policy is probably wrong .. + ValueDefinition{ short: "utmr", description: "If 1, supports user-timer events", bits_range: (13, 13), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "prefetchit_0_1", description: "PREFETCHIT0/1 instructions", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + + ValueDefinition{ short: "user_msr", description: "If 1, supports the URDMSR and UWRMSR instructions", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + // TODO: Check which policy to use + ValueDefinition{ short: "uiret_uif", description: "If 1, UIRET sets UIF to the value of bit 1 of the RFLAGS image loaded from the stack", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + // TODO: Not sure about this one + ValueDefinition{ short: "cet_sss", description: "CET supervisor shadow stacks safe to use", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "avx10", description: "If 1, supports the Intel AVX10 instructions and indicates the presence of leaf 0x24", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "apx_f", description: "If 1, the processor provides foundational support for Intel Advanced Performance Extensions", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Should this perhaps be opt-in ? + ValueDefinition{ short: "mwait", description: "If 1, MWAIT is supported even if (0x1 ECX bit 3 (monitor) is enumerated as 0)", bits_range: (23, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "slsm", description: "If 1, indicates bit 0 of the IA32_INTEGRITY_STATUS MSR is supported. Bit 0 of this MSR indicates whether static lockstep is active on this logical processor", bits_range: (24, 24), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Structured Extended Feature Flags Enumeration Sub-Leaf 2 + // =================================================================================================================== + ( + Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + // TODO: Not sure about this one + ValueDefinition{ short: "intel_psfd", description: "If 1, indicates bit 7 of the IA32_SPEC_CTRL_MSR is supported. Bit 7 of this MSR disables fast store forwarding predictor without disabling speculative store bypass", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about this one and consider adding a better description + ValueDefinition{ short: "ipred_ctrl", description: "MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about this one and consider adding a better description + ValueDefinition{ short: "rrsba_ctrl", description: "MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about this one and consider adding a better description + ValueDefinition{ short: "ddp_ctrl", description: "MSR bit IA32_SPEC_CTRL.DDPD_U", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about this one and consider adding a better description + ValueDefinition{ short: "bhi_ctrl", description: "MSR bit IA32_SPEC_CTRL.BHI_DIS_S", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about this one and consider adding a better description + ValueDefinition{ short: "mcdt_no", description: "MCDT mitigation not needed", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about this one and consider adding a better description + ValueDefinition{ short: "uclock_disable", description: "UC-lock disable is supported", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ]) + ), + + // =================================================================================================================== + // Direct Cache Access Information + // =================================================================================================================== + ( + Parameters{ leaf: 0x9, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + // TODO: Can this be used to check whether DCA is enabled? (or should one not rely on this and use another feature flag?) + ValueDefinition{ short: "dca_enabled_in_bios", description: "DCA is enabled in BIOS", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ]) + ), + + // =================================================================================================================== + // Architectural Performance Monitoring + // =================================================================================================================== + // We will just zero out everything to do with PMU for CPU profiles and require equality for migration to be considered compatible (for the time being). + ( + Parameters{ leaf: 0xa, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pmu_version", description: "Performance monitoring unit version ID", bits_range: (0, 7), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "pmu_n_gcounters", description: "Number of general PMU counters per logical CPU", bits_range: (8, 15), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "pmu_gcounters_nbits", description: "Bitwidth of PMU general counters", bits_range: (16, 23), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "pmu_cpuid_ebx_bits", description: "Length of leaf 0xa EBX bit vector", bits_range: (24, 31), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0xa, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "no_core_cycle_evt", description: "Core cycle event not available", bits_range: (0, 0), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "no_insn_retired_evt", description: "Instruction retired event not available", bits_range: (1, 1), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "no_refcycle_evt", description: "Reference cycles event not available", bits_range: (2, 2), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "no_llc_ref_evt", description: "LLC-reference event not available", bits_range: (3, 3), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "no_llc_miss_evt", description: "LLC-misses event not available", bits_range: (4, 4), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "no_br_insn_ret_evt", description: "Branch instruction retired event not available", bits_range: (5, 5), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "no_br_mispredict_evt", description: "Branch mispredict retired event not available", bits_range: (6, 6), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "no_td_slots_evt", description: "Topdown slots event not available", bits_range: (7, 7), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0xa, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pmu_fcounters_bitmap", description: "Fixed-function PMU counters support bitmap", bits_range: (0, 31), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0xa, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pmu_n_fcounters", description: "Number of fixed PMU counters", bits_range: (0, 4), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "pmu_fcounters_nbits", description: "Bitwidth of PMU fixed counters", bits_range: (5, 12), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "anythread_depr", description: "AnyThread deprecation", bits_range: (15, 15), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + // =================================================================================================================== + // Extended Topology Enumeration + // =================================================================================================================== + + // Leaf 0xB must be set by CHV itself (and do all necessary checks) hence we can ignore checking for migration compatibility here + ( + Parameters{ leaf: 0xb, sub_leaf:RangeInclusive::new( 0, u32::MAX), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "x2apic_id_shift", description: "Bit width of this level (previous levels inclusive)", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // Set by VMM/user provided config + ( + Parameters{ leaf: 0xb, sub_leaf:RangeInclusive::new( 0, u32::MAX), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "domain_lcpus_count", description: "Logical CPUs count across all instances of this domain", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // Set by VMM/user provided config + ( + Parameters{ leaf: 0xb, sub_leaf:RangeInclusive::new( 0, u32::MAX), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "domain_nr", description: "This domain level (subleaf ID)", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "domain_type", description: "This domain type", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // Set by VMM/user provided config + ( + Parameters{ leaf: 0xb, sub_leaf:RangeInclusive::new( 0, u32::MAX), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "x2apic_id", description: "x2APIC ID of current logical CPU", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // =================================================================================================================== + // Processor Extended State Enumeration Main Leaf + // =================================================================================================================== + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "xcr0_x87", description: "XCR0.X87 (bit 0) supported", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xcr0_sse", description: "XCR0.SEE (bit 1) supported", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xcr0_avx", description: "XCR0.AVX (bit 2) supported", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MPX is deprecated + ValueDefinition{ short: "xcr0_mpx_bndregs", description: "XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MPX is deprecated + ValueDefinition{ short: "xcr0_mpx_bndcsr", description: "XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xcr0_avx512_opmask", description: "XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xcr0_avx512_zmm_hi256", description: "XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xcr0_avx512_hi16_zmm", description: "XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure which profile policy to apply here + ValueDefinition{ short: "xcr0_ia32_xss", description: "XCR0.IA32_XSS (bit 8) used for IA32_XSS", bits_range: (8, 8), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xcr0_pkru", description: "XCR0.PKRU (bit 9) supported (XSAVE PKRU registers)", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about this (could this be relevant for CVE mitigations?) + ValueDefinition{ short: "xcr0_ia32_xss_bits", description: "XCR0.IA32_XSS (bit 10 - 16) used for IA32_XSS", bits_range: (10, 16), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinition{ short: "xcr0_tileconfig", description: "XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinition{ short: "xcr0_tiledata", description: "XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA)", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + // We don't need migration compatibility requirements here since we check for each individual state component + ValueDefinition{ short: "xsave_sz_xcr0_enabled", description: "XSAVE/XRSTOR area byte size, for XCR0 enabled features", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + // We don't need migration compatibility requirements here since we check for each individual state component + ValueDefinition{ short: "xsave_sz_max", description: "XSAVE/XRSTOR area max byte size, all CPU features", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "xcr0_upper_bits", description: "Reports the valid bit fields of the upper 32 bits of the XCR0 register", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + // =================================================================================================================== + // Processor Extended State Enumeration Sub-leaf 1 + // =================================================================================================================== + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "xsaveopt", description: "XSAVEOPT instruction", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xsavec", description: "XSAVEC instruction", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "xgetbv1", description: "XGETBV instruction with ECX = 1", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Can this have security implications in terms of supervisor state getting exposed? + ValueDefinition{ short: "xsaves", description: "XSAVES/XRSTORS instructions (and XSS MSR)", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bitssthat userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinition{ short: "xfd", description: "Extended feature disable support", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + /*NOTE: This will depend on which CPU features (in CHV) are enabled and pre-computation can potentially lead to a combinatorial explosion. Luckily we can deal with each component (and its size) separately, hence we can just passthrough whatever we get from the host here.*/ + ValueDefinition{ short: "xsave_sz_xcr0_xmms_enabled", description: "XSAVE area size, all XCR0 and IA32_XSS features enabled", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::ECX }, + /* Reports the supported bits of the lower IA32_XSS MSR. IA32_XSS[n] can be set to 1 only if ECX[n] = 1*/ + ValueDefinitions::new(&[ + // TODO: Not sure what profile policy to set here + ValueDefinition{ short: "xcr0_7bits", description: "Used for XCR0", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + // TODO: Not sure about the profile pilicy here + ValueDefinition{ short: "xss_pt", description: "PT state, supported", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure what profile policy to set here + ValueDefinition{ short: "xcr0_bit9", description: "Used for XCR0", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about the profile pilicy here + ValueDefinition{ short: "xss_pasid", description: "PASID state, supported", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about the profile pilicy here + ValueDefinition{ short: "xss_cet_u", description: "CET user state, supported", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about the profile pilicy here + ValueDefinition{ short: "xss_cet_p", description: "CET supervisor state, supported", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about the profile pilicy here + ValueDefinition{ short: "xss_hdc", description: "HDC state, supported", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about the profile pilicy here + ValueDefinition{ short: "xss_uintr", description: "UINTR state, supported", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about the profile pilicy here + ValueDefinition{ short: "xss_lbr", description: "LBR state, supported", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure about the profile pilicy here + ValueDefinition{ short: "xss_hwp", description: "HWP state, supported", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not sure what profile policy to set here + ValueDefinition{ short: "xcr0_bits", description: "Used for XCR0", bits_range: (17, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EDX }, + /* Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32 ] can be set to 1 only if EDX[n] = 1*/ + ValueDefinitions::new(&[ + // TODO: Not sure what profile policy to set here + ValueDefinition{ short: "ia32_xss_upper", description: " Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32 ] can be set to 1 only if EDX[n] = 1", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Processor Extended State Enumeration Sub-leaves + // =================================================================================================================== + + /* LEAF 0xd sub-leaf n >=2 : + If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 ≤ n ≤ 31) is + invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 ≤ n ≤ 63) + is invalid if sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32]. + + */ + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 2, 63), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "xsave_sz", description: "Size of save area for subleaf-N feature, in bytes", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 2, 63), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "xsave_offset", description: "Offset of save area for subleaf-N feature, in bytes", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 2, 63), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "is_xss_bit", description: "Subleaf N describes an XSS bit, otherwise XCR0 bit", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "compacted_xsave_64byte_aligned", description: "When compacted, subleaf-N feature XSAVE area is 64-byte aligned", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + // TODO: This may depend on the "amx" feature? + ValueDefinition{ short: "xfd_faulting", description: "Indicates support for xfd faulting", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + // =================================================================================================================== + // Intel Resource Director Technology Monitoring Enumeration + // =================================================================================================================== + + ( + Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "core_rmid_max", description: "RMID max, within this core, all types (0-based)", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + ( + Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + // TODO: Not sure about the short name (generated by the x86-cpuid.org tool). What is cqm_llc? + ValueDefinition{ short: "cqm_llc", description: "Supports L3 Cache Intel RDT Monitoring if 1", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ]) + ), + + // =================================================================================================================== + // Intel Resource Director Technology Monitoring Enumeration Sub-leaf 1 + // =================================================================================================================== + ( + Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, + // TODO: Not sure about the migration policy + ValueDefinitions::new(&[ + ValueDefinition{ short: "l3c_qm_bitwidth", description: "L3 QoS-monitoring counter bitwidth (24-based)", bits_range: (0, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "l3c_qm_overflow_bit", description: "QM_CTR MSR bit 61 is an overflow bit", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "l3c_qm_non_cpu_agent", description: "If 1, indicates the presence of non-CPU agent Intel RDT CTM support", bits_range: (9, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "l3c_qm_non_cpu_agent", description: "If 1, indicates the presence of non-CPU agent Intel RDT MBM support", bits_range: (10, 10), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, + // TODO: Not sure about the migration policy + ValueDefinitions::new(&[ + ValueDefinition{ short: "l3c_qm_conver_factor", description: "QM_CTR MSR conversion factor to bytes", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::ECX }, + // TODO: Not sure about the migration policy + ValueDefinitions::new(&[ + ValueDefinition{ short: "l3c_qm_rmid_max", description: "L3 QoS-monitoring max RMID", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + ( + Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cqm_occup_llc", description: "L3 QoS occupancy monitoring supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cqm_mbm_total", description: "L3 QoS total bandwidth monitoring supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cqm_mbm_local", description: "L3 QoS local bandwidth monitoring supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration + // =================================================================================================================== + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + //TODO: These features may be good for increased performance. Perhaps there needs to be some mechanism to opt-in for non-host CPU profiles? + ValueDefinitions::new(&[ + ValueDefinition{ short: "cat_l3", description: "L3 Cache Allocation Technology supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "cat_l2", description: "L2 Cache Allocation Technology supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "mba", description: "Memory Bandwidth Allocation supported", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 1) + // =================================================================================================================== + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cat_cbm_len", description: "L3_CAT capacity bitmask length, minus-one notation", bits_range: (0, 4), policy:ProfilePolicy::Passthrough /* TODO: ? */, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore /* TODO: ? */ }, + ]) + ), + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cat_units_bitmap", description: "L3_CAT bitmap of allocation units", bits_range: (0, 31), policy:ProfilePolicy::Passthrough /* TODO: ? */, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore /* TODO: ? */}, + ]) + ), + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::ECX }, + //TODO: These feature may be good for increased performance. Perhaps there needs to be some mechanism to opt-in for non-host CPU profiles? + ValueDefinitions::new(&[ + ValueDefinition{ short: "l3_cat_non_cpu_agents", description: "L3_CAT for non-CPU agent is supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cdp_l3", description: "L3/L2_CAT CDP (Code and Data Prioritization)", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cat_sparse_1s", description: "L3/L2_CAT non-contiguous 1s value supported", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EDX }, + // TODO: We might need some way to opt in to use Intel cache allocation technology in guests with non-host CPU profiles. + ValueDefinitions::new(&[ + ValueDefinition {short: "cat_cos_max", description: "Highest COS number supported for this ResID", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq } + ]) + ), + + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 2) + // =================================================================================================================== + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cat_cbm_len", description: "L2_CAT capacity bitmask length, minus-one notation", bits_range: (0, 4), policy:ProfilePolicy::Passthrough /* TODO: ? */, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore /* TODO: ? */ }, + ]) + ), + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cat_units_bitmap", description: "L2_CAT bitmap of allocation units", bits_range: (0, 31), policy:ProfilePolicy::Passthrough /* TODO: ? */, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore /* TODO: ? */}, + ]) + ), + + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition {short: "cat_cos_max", description: "Highest COS number supported for this ResID", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq } + ]) + ), + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::ECX }, + // TODO: We might need some way to opt in to use Intel cache allocation technology in guests with non-host CPU profiles. + ValueDefinitions::new(&[ + ValueDefinition{ short: "cdp_l2", description: "L2_CAT CDP (Code and Data Prioritization)", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cat_sparse_1s", description: "L2_CAT non-contiguous 1s value supported", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 3) + // =================================================================================================================== + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 3, 3), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + // TODO: We might need some way to opt in to use Intel MBA technology in guests with non-host CPU profiles. + ValueDefinition{ short: "mba_max_delay", description: "Max MBA throttling value; minus-one notation", bits_range: (0, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 3, 3), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "per_thread_mba", description: "Per-thread MBA controls are supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "mba_delay_linear", description: "Delay values are linear", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 3, 3), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "mba_cos_max", description: "MBA max Class of Service supported", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 5) + // =================================================================================================================== + // + // TODO: We may want to have some way to opt-in to use Intel RDT for guests with non-host CPU profiles. + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "core_max_throttle", description: "Max Core throttling level supported by the corresponding ResID", bits_range: (0, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + // TODO: Not sure about the short name + ValueDefinition{ short: "core_scope", description: "If 1, indicates the logical processor scope of the IA32_QoS_Core_BW_Thrtl_n MSRs. Other values are reserved", bits_range: (8, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cba_delay_linear", description: "The response of the bandwidth control is approximately linear", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "core_cos_max", description: "Core max Class of Service supported", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + // SGX is already disabled and deprecated so we don't need to worry about leaf 0x12 and its subleaves + + // =================================================================================================================== + // Intel Processor Trace Enumeration Main Leaf + // =================================================================================================================== + + ( + Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pt_max_subleaf", description: "Maximum leaf 0x14 subleaf", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + ( + Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cr3_filtering", description: "IA32_RTIT_CR3_MATCH is accessible", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "psb_cyc", description: "Configurable PSB and cycle-accurate mode", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ip_filtering", description: "IP/TraceStop filtering; Warm-reset PT MSRs preservation", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "mtc_timing", description: "MTC timing packet; COFI-based packets suppression", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "ptwrite", description: "PTWRITE support", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "power_event_trace", description: "Power Event Trace support", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "psb_pmi_preserve", description: "PSB and PMI preservation support", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "event_trace", description: "Event Trace packet generation through IA32_RTIT_CTL.EventEn", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "tnt_disable", description: "TNT packet generation disable through IA32_RTIT_CTL.DisTNT", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "topa_output", description: "ToPA output scheme support", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "topa_multiple_entries", description: "ToPA tables can hold multiple entries", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "single_range_output", description: "Single-range output scheme supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "trance_transport_output", description: "Trace Transport subsystem output support", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ip_payloads_lip", description: "IP payloads have LIP values (CS base included)", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Intel Processor Trace Enumeration Sub-leaf 1 + // =================================================================================================================== + + ( + Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "num_address_ranges", description: "Filtering number of configurable Address Ranges", bits_range: (0, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "mtc_periods_bmp", description: "Bitmap of supported MTC period encodings", bits_range: (16, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cycle_thresholds_bmp", description: "Bitmap of supported Cycle Threshold encodings", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "psb_periods_bmp", description: "Bitmap of supported Configurable PSB frequency encodings", bits_range: (16, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Time Stamp Counter and Core Crystal Clock Information + // =================================================================================================================== + + // TODO: Apparently these clock frequencies can be set by KVM. Would it perhaps make sense to set them to the same as the physical CPU the profile corresponds to? Or is it best to just pass through whatever we get from the host here? + ( + Parameters{ leaf: 0x15, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "tsc_denominator", description: "Denominator of the TSC/'core crystal clock' ratio", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ]) + ), + + ( + Parameters{ leaf: 0x15, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "tsc_numerator", description: "Numerator of the TSC/'core crystal clock' ratio", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x15, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_crystal_hz", description: "Core crystal clock nominal frequency, in Hz", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ]) + ), + + // =================================================================================================================== + // Processor Frequency Information + // =================================================================================================================== + + ( + Parameters{ leaf: 0x16, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_base_mhz", description: "Processor base frequency, in MHz", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x16, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_max_mhz", description: "Processor max frequency, in MHz", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x16, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "bus_mhz", description: "Bus reference frequency, in MHz", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // =================================================================================================================== + // System-On-Chip Vendor Attribute Enumeration Main Leaf + // =================================================================================================================== + + // System-On-Chip should probably not be supported for CPU profiles for the foreseeable feature. + ( + Parameters{ leaf: 0x17, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "soc_max_subleaf", description: "Maximum leaf 0x17 subleaf", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + // =================================================================================================================== + // Deterministic Address Translation Parameters + // =================================================================================================================== + + // TODO: Check that we can indeed ignore migration compatibility checks for this leaf + ( + Parameters{ leaf: 0x18, sub_leaf: RangeInclusive::new(0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "tlb_max_subleaf", description: "Maximum leaf 0x18 subleaf", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x18, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "tlb_4k_page", description: "TLB 4KB-page entries supported", bits_range: (0, 0), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "tlb_2m_page", description: "TLB 2MB-page entries supported", bits_range: (1, 1), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "tlb_4m_page", description: "TLB 4MB-page entries supported", bits_range: (2, 2), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "tlb_1g_page", description: "TLB 1GB-page entries supported", bits_range: (3, 3), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "hard_partitioning", description: "(Hard/Soft) partitioning between logical CPUs sharing this structure", bits_range: (8, 10), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_way_associative", description: "Ways of associativity", bits_range: (16, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x18, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "n_sets", description: "Number of sets", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x18, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "tlb_type", description: "Translation cache type (TLB type)", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "tlb_cache_level", description: "Translation cache level (1-based)", bits_range: (5, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "is_fully_associative", description: "Fully-associative structure", bits_range: (8, 8), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "tlb_max_addressible_ids", description: "Max number of addressable IDs for logical CPUs sharing this TLB - 1", bits_range: (14, 25), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // We don't support key locker for now (leaf 0x19): Hence we zero out leaf 0x19 for CPU profiles (and don't check it for migration compatibility) + // We zero LEAF 0x1A (Native Model ID Enumeration) out for CPU profiles (and don't check it for migration compatibility) + // LEAF 0x1B (PCONFIG) is zeroed out for CPU profiles for now (and we don't check it for migration compatibility) + + // =================================================================================================================== + // Last Branch Records Information + // =================================================================================================================== + + ( + Parameters{ leaf: 0x1c, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "lbr_depth_8", description: "Max stack depth (number of LBR entries) = 8", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_depth_16", description: "Max stack depth (number of LBR entries) = 16", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_depth_24", description: "Max stack depth (number of LBR entries) = 24", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_depth_32", description: "Max stack depth (number of LBR entries) = 32", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_depth_40", description: "Max stack depth (number of LBR entries) = 40", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_depth_48", description: "Max stack depth (number of LBR entries) = 48", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_depth_56", description: "Max stack depth (number of LBR entries) = 56", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_depth_64", description: "Max stack depth (number of LBR entries) = 64", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_deep_c_reset", description: "LBRs maybe cleared on MWAIT C-state > C1", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_ip_is_lip", description: "LBR IP contain Last IP, otherwise effective IP", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ]) + ), + + ( + Parameters{ leaf: 0x1c, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "lbr_cpl", description: "CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_branch_filter", description: "Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_call_stack", description: "Call-stack mode (IA32_LBR_CTL[3] = 1) supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ]) + ), + + ( + Parameters{ leaf: 0x1c, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "lbr_mispredict", description: "Branch misprediction bit supported (IA32_LBR_x_INFO[63])", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "lbr_timed_lbr", description: "Timed LBRs (CPU cycles since last LBR entry) supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_branch_type", description: "Branch type field (IA32_LBR_INFO_x[59:56]) supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ValueDefinition{ short: "lbr_events_gpc_bmp", description: "LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters", bits_range: (16, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ]) + ), + + // =================================================================================================================== + // Tile Information Main Leaf + // =================================================================================================================== + // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. + ( + Parameters{ leaf: 0x1d, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "amx_max_palette", description: "Highest palette ID / subleaf ID", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq}, + ]) + ), + + // =================================================================================================================== + // Tile Palette 1 Sub-leaf + // =================================================================================================================== + // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. + ( + Parameters{ leaf: 0x1d, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "amx_palette_size", description: "AMX palette total tiles size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq /* require equality as this can impact XSAVE */ }, + ValueDefinition{ short: "amx_tile_size", description: "AMX single tile's size, in bytes", bits_range: (16, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0x1d, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "amx_tile_row_size", description: "AMX tile single row's size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "amx_palette_nr_tiles", description: "AMX palette number of tiles", bits_range: (16, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq /* Can affect XSAVE hence require equality here */}, + ]) + ), + + ( + Parameters{ leaf: 0x1d, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "amx_tile_nr_rows", description: "AMX tile max number of rows", bits_range: (0, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + // =================================================================================================================== + // TMUL Information Main Leaf + // =================================================================================================================== + // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. + ( + Parameters{ leaf: 0x1e, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition {short: "tmul_info_max", description: "Reports the maximum number of sub-leaves that are supported in leaf 0x1e", bits_range: (0,31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq} + ]) + ), + + ( + Parameters{ leaf: 0x1e, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "tmul_maxk", description: "TMUL unit maximum height, K (rows or columns)", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq /* TODO: OR should we go with Eq? */ }, + ValueDefinition{ short: "tmul_maxn", description: "TMUL unit maximum SIMD dimension, N (column bytes)", bits_range: (8, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq /* TODO: Or should we go with Eq? */ }, + ]) + ), + + // =================================================================================================================== + // TMUL Information Sub-leaf 1 + // =================================================================================================================== + // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. + ( + Parameters{ leaf: 0x1e, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinitions::new(&[ + ValueDefinition{ short: "amx_int8", description: "If 1, the processor supports tile computational operations on 8-bit integers", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_bf16", description: "If 1, the processor supports tile computational operations on bfloat16 numbers", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_complex", description: "If 1, the processor supports the AMX-COMPLEX instructions", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_fp16", description: "If 1, the processor supports tile computational operations on FP16 numbers", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_fp8", description: "If 1, the processor supports tile computational operations on FP8 numbers", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_transpose", description: "If 1, the processor supports the AMX-TRANSPOSE instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_tf32", description: "If 1, the processor supports the AMX-TF32 (FP19) instructions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_avx512", description: "If 1, the processor supports the AMX-AVX512 instructions", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "amx_movrs", description: "If 1, the processor supports the AMX-MOVRS instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // V2 Extended Topology Enumeration + // =================================================================================================================== + + // We can ignore checking migration compatibility for the 0x1f leaf because these values must be set by CHV itself which should do all relevant checks + ( + Parameters{ leaf: 0x1f, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "x2apic_id_shift", description: "Bit width of this level (previous levels inclusive)", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x1f, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "domain_lcpus_count", description: "Logical CPUs count across all instances of this domain", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x1f, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "domain_level", description: "This domain level (subleaf ID)", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "domain_type", description: "This domain type", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x1f, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "x2apic_id", description: "x2APIC ID of current logical CPU", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + // =================================================================================================================== + // Processor History Reset + // =================================================================================================================== + ( + Parameters{ leaf: 0x20, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "hreset_nr_subleaves", description: "CPUID 0x20 max subleaf + 1", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + ( + Parameters{ leaf: 0x20, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "hreset_thread_director", description: "HRESET of Intel thread director is supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // TDX + // =================================================================================================================== + + // TDX is not supported by CPU profiles for now. We just zero out this leaf for CPU profiles for the time being. + ( + Parameters{ leaf: 0x21, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "tdx_vendorid_0", description: "TDX vendor ID string bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0x21, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "tdx_vendorid_2", description: "CPU vendor ID string bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + ( + Parameters{ leaf: 0x21, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "tdx_vendorid_1", description: "CPU vendor ID string bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ]) + ), + + // =================================================================================================================== + // Architectural Performance Monitoring Extended Main Leaf + // =================================================================================================================== + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "subleaf_0", description: "If 1, subleaf 0 exists", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "subleaf_1", description: "If 1, subleaf 1 exists", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "subleaf_2", description: "If 1, subleaf 2 exists", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "subleaf_3", description: "If 1, subleaf 3 exists", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "subleaf_4", description: "If 1, subleaf 4 exists", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ + short: "subleaf_5", + description: "If 1, subleaf 5 exists. The processor suppots Architectural PEBS. The IA32_PEBS_BASE and IA32_PEBS_INDEX MSRs exist", + bits_range: (5, 5), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits + }, + ]) + ), + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "unitmask2", description: "IA32_PERFEVTSELx MSRs UnitMask2 is supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "eq_bit", description: "equal flag in the IA32_PERFEVTSELx MSR is supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "RDPMC_USR_DISABLE", description: "RDPMC_USR_DISABLE", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + // TODO: Not sure about migration compatibility + ValueDefinition{ + short: "num_slots_per_cycle", + description: "Number of slots per cycle. This number can be multiplied by the number of cycles (from CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.CORE or IA32_FIXED_CTR1) to determine the total number of slots", + bits_range: (0, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq + }, + ]) + ), + + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 1 + // =================================================================================================================== + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pmu_gp_counters_bitmap", description: "General-purpose PMU counters bitmap", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pmu_f_counters_bitmap", description: "Fixed PMU counters bitmap", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 2 + // =================================================================================================================== + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pmu_acr_bitmap", description: "Bitmap of Auto Counter Reload (ACR) general-purpose counters that can be reloaded", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 3 + // =================================================================================================================== + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 3, 3), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "core_cycles_evt", description: "Core cycles event supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "insn_retired_evt", description: "Instructions retired event supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ref_cycles_evt", description: "Reference cycles event supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "llc_refs_evt", description: "Last-level cache references event supported", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "llc_misses_evt", description: "Last-level cache misses event supported", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "br_insn_ret_evt", description: "Branch instruction retired event supported", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "br_mispr_evt", description: "Branch mispredict retired event supported", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "td_slots_evt", description: "Topdown slots event supported", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "td_backend_bound_evt", description: "Topdown backend bound event supported", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "td_bad_spec_evt", description: "Topdown bad speculation event supported", bits_range: (9, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "td_frontend_bound_evt", description: "Topdown frontend bound event supported", bits_range: (10, 10), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "td_retiring_evt", description: "Topdown retiring event support", bits_range: (11, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "lbr_inserts", description: "LBR support", bits_range: (12, 12), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 4 + // =================================================================================================================== + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 4, 4), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "allow_in_record", description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition{ short: "cntr", description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", bits_range: (0, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition{ short: "lbr", description: "LBR group and both bits [41:40] are available", bits_range: (8, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition{ short: "xer", description: "These bits correspond to XER group bits [55:49]", bits_range: (17, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "grp", description: "If 1, the GRP group is available", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "aux", description: "If 1, the AUX group is available", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 4, 4), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "allow_in_record", description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition{ short: "cntr", description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", bits_range: (0, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition{ short: "lbr", description: "LBR group and both bits [41:40] are available", bits_range: (8, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition{ short: "xer", description: "These bits correspond to XER group bits [55:49]", bits_range: (17, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "grp", description: "If 1, the GRP group is available", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "aux", description: "If 1, the AUX group is available", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 5 + // =================================================================================================================== + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "architectural_pebs_counters", description: "General-purpose counters support Architectural PEBS. Bit vector of general-purpose counters for which the Architectural PEBS mechanism is available", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ]) + ), + + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pebs_pdist_counters", description: "General-purpose counters for which PEBS support PDIST", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ]) + ), + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pebs_fixed_function_counters", description: "Fixed-function counters support Architectural PEBS. Bit vector of fixed-function counters for which the Architectural PEBS mechanism is available. If ECX[x] == 1, then the IA32_PMC_FXm_CFG_C MSR is available, and PEBS is supported", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ]) + ), + + ( + Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "pebs_fixed_function_pdist_counters", description: "Fixed-function counters for which PEBS supports PDIST", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + ]) + ), + + // =================================================================================================================== + // Converged Vector ISA Main Leaf + // =================================================================================================================== + + ( + Parameters{ leaf: 0x24, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "converged_vector_isa_max_sub_leaves", description: "Reports the maximum number of sub-leaves that are supported in leaf 0x24", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq}, + ]) + ), + + ( + Parameters{ leaf: 0x24, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "avx_10_version", description: "Reports the intel AVX10 Converged Vector ISA version", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq}, + ValueDefinition{ short: "avx_10_lengths", description: "Reserved at 111", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + ]) + ), + + // Hypervisor reserved CPUID leaves are set elsewhere + + // =================================================================================================================== + // Extended Function CPUID Information + // =================================================================================================================== + + ( + Parameters{ leaf: 0x80000000, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "max_ext_leaf", description: "Maximum extended CPUID leaf supported", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, + ]) + ), + + ( + Parameters{ leaf: 0x80000000, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_vendorid_0", description: "Vendor ID string bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000000, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_vendorid_2", description: "Vendor ID string bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000000, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_vendorid_1", description: "Vendor ID string bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000001, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + // TODO: Would inherit be better than passthrough? Currently CHV manually copies these over from the host ... + ValueDefinitions::new(&[ + ValueDefinition{ short: "e_stepping_id", description: "Stepping ID", bits_range: (0, 3), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "e_base_model", description: "Base processor model", bits_range: (4, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "e_base_family", description: "Base processor family", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "e_base_type", description: "Base processor type (Transmeta)", bits_range: (12, 13), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "e_ext_model", description: "Extended processor model", bits_range: (16, 19), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "e_ext_family", description: "Extended processor family", bits_range: (20, 27), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000001, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "brand_id", description: "Brand ID", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "pkg_type", description: "Package type", bits_range: (28, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000001, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "lahf_lm", description: "LAHF and SAHF in 64-bit mode", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "lzcnt", description: "LZCNT advanced bit manipulation", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "prefetchw", description: "3DNow PREFETCH/PREFETCHW support", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x80000001, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "syscall", description: "SYSCALL and SYSRET instructions", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "nx", description: "Execute Disable Bit available", bits_range: (20, 20), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "pdpe1gb", description: "1-GB large page support", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Should this perhaps be overwritten to 0 and require opt-in via a feature? + ValueDefinition{ short: "rdtscp", description: "RDTSCP instruction and IA32_TSC_AUX are available", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "lm", description: "Long mode (x86-64, 64-bit support)", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + // TODO: Would it be better to inherit these for the CPU profile (or zero it out entirely?) + ( + Parameters{ leaf: 0x80000002, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_0", description: "CPU brand ID string, bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000002, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_1", description: "CPU brand ID string, bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000002, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_2", description: "CPU brand ID string, bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000002, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_3", description: "CPU brand ID string, bytes 12 - 15", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000003, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_4", description: "CPU brand ID string bytes, 16 - 19", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000003, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_5", description: "CPU brand ID string bytes, 20 - 23", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000003, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_6", description: "CPU brand ID string bytes, 24 - 27", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000003, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_7", description: "CPU brand ID string bytes, 28 - 31", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000004, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_8", description: "CPU brand ID string, bytes 32 - 35", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000004, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_9", description: "CPU brand ID string, bytes 36 - 39", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000004, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_10", description: "CPU brand ID string, bytes 40 - 43", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000004, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "cpu_brandid_11", description: "CPU brand ID string, bytes 44 - 47", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000006, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "l2_line_size", description: "L2 cache line size, in bytes", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "l2_nlines", description: "L2 cache number of lines per tag", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "l2_assoc", description: "L2 cache associativity", bits_range: (12, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "l2_size_kb", description: "L2 cache size, in KB", bits_range: (16, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + // EAX, EBX and ECX of 0x8000_0007 are all reserved (=0) on Intel + + ( + Parameters{ leaf: 0x80000007, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, + ValueDefinitions::new(&[ + // TODO: We may want some mechanism to let users opt-in to using an invariant TSC provided by the hardware (when available). + ValueDefinition{ short: "constant_tsc", description: "TSC ticks at constant rate across all P and C states", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ), + + ( + Parameters{ leaf: 0x80000008, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "phys_addr_bits", description: "Max physical address bits", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "virt_addr_bits", description: "Max virtual address bits", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "guest_phys_addr_bits", description: "Max nested-paging guest physical address bits", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ]) + ), + + ( + Parameters{ leaf: 0x80000008, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, + ValueDefinitions::new(&[ + ValueDefinition{ short: "wbnoinvd", description: "WBNOINVD supported", bits_range: (9, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ]) + ) + ]) +}; + diff --git a/arch/src/x86_64/cpuid_definitions/mod.rs b/arch/src/x86_64/cpuid_definitions/mod.rs index cc4fc911e9..5af714fd54 100644 --- a/arch/src/x86_64/cpuid_definitions/mod.rs +++ b/arch/src/x86_64/cpuid_definitions/mod.rs @@ -4,6 +4,9 @@ use serde::{Deserialize, Serialize}; use crate::x86_64::CpuidReg; +pub mod hypervisor; +pub mod intel; + /// Parameters for inspecting CPUID definitions. #[derive(Debug, Clone, Eq, PartialEq, Serialize, Deserialize)] pub struct Parameters { @@ -73,8 +76,11 @@ pub struct ValueDefinition { /// NOTE: The only way to interact with this value (beyond this crate) is via the const [`Self::as_slice()`](Self::as_slice) method. pub struct ValueDefinitions(&'static [ValueDefinition]); impl ValueDefinitions { - /// Constructor permitting less than 32 entries. + /// Constructor permitting at most 32 entries. const fn new(cpuid_descriptions: &'static [ValueDefinition]) -> Self { + // Note that this function is only called within this module, at compile time, hence it is fine to have some + // additional sanity checks such as the following assert. + assert!(cpuid_descriptions.len() <= 32); Self(cpuid_descriptions) } /// Converts this into a slice representation. This is the only way to read values of this type. From 36a0311a95d6928ff9bc2235ca0706466d10f160 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 07:25:20 +0200 Subject: [PATCH 08/75] hypervisor: Derive Eq for HypervisorType and CpuVendor Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- hypervisor/src/cpu.rs | 2 +- hypervisor/src/lib.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hypervisor/src/cpu.rs b/hypervisor/src/cpu.rs index 251da88dc4..bfd24f12e8 100644 --- a/hypervisor/src/cpu.rs +++ b/hypervisor/src/cpu.rs @@ -30,7 +30,7 @@ use crate::kvm::{TdxExitDetails, TdxExitStatus}; use crate::{CpuState, MpState, StandardRegisters}; #[cfg(target_arch = "x86_64")] -#[derive(Debug, Copy, Clone, Default, serde::Serialize, serde::Deserialize)] +#[derive(Debug, Copy, Clone, Default, serde::Serialize, serde::Deserialize, Eq, PartialEq)] pub enum CpuVendor { #[default] Unknown, diff --git a/hypervisor/src/lib.rs b/hypervisor/src/lib.rs index 3d980f0902..2e653708c5 100644 --- a/hypervisor/src/lib.rs +++ b/hypervisor/src/lib.rs @@ -69,7 +69,7 @@ pub use vm::{ pub use crate::hypervisor::{Hypervisor, HypervisorError}; -#[derive(Debug, Copy, Clone, serde::Serialize, serde::Deserialize)] +#[derive(Debug, Copy, Clone, serde::Serialize, serde::Deserialize, PartialEq, Eq)] pub enum HypervisorType { #[cfg(feature = "kvm")] Kvm, From 3dc3f8b48f48aa715407b9b6010d46087066b70a Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 07:35:20 +0200 Subject: [PATCH 09/75] cpu-profile-generation: CPU profile generation CLI This commit introduces a CLI for generating a CPU profile closely matching the CPU of the machine the CLI is executed on. The idea is to have a simple way to add more CPU profiles corresponding to physical CPUs. Note however that with the current setup one still needs a little bit of manual work to integrate the generated CPU profile data into cloud hypervisor itself. Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- arch/Cargo.toml | 6 ++++ arch/src/bin/generate-cpu-profile.rs | 14 +++++++++ arch/src/x86_64/cpu_profile_generation.rs | 36 ++++++++++++++++++++++- 3 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 arch/src/bin/generate-cpu-profile.rs diff --git a/arch/Cargo.toml b/arch/Cargo.toml index 9f98d55e24..68da4e4bf5 100644 --- a/arch/Cargo.toml +++ b/arch/Cargo.toml @@ -4,6 +4,12 @@ edition.workspace = true name = "arch" version = "0.1.0" +# TODO: Consider making this a binary of the main package instead +[[bin]] +name = "generate-cpu-profile" +path = "src/bin/generate-cpu-profile.rs" +required-features = ["cpu_profile_generation"] + [features] default = [] fw_cfg = [] diff --git a/arch/src/bin/generate-cpu-profile.rs b/arch/src/bin/generate-cpu-profile.rs new file mode 100644 index 0000000000..693467e142 --- /dev/null +++ b/arch/src/bin/generate-cpu-profile.rs @@ -0,0 +1,14 @@ +use anyhow::Context; +use std::io::BufWriter; +#[cfg(all( + target_arch = "x86_64", + feature = "cpu_profile_generation", + feature = "kvm" +))] +fn main() -> anyhow::Result<()> { + let hypervisor = hypervisor::new().context("Could not obtain hypervisor")?; + // TODO: Consider letting the user provide a file path as a target instead of writing to stdout. + // The way it is now should be sufficient for a PoC however. + let writer = BufWriter::new(std::io::stdout().lock()); + arch::x86_64::cpu_profile_generation::generate_profile_data(writer, hypervisor.as_ref()) +} diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index a06dc238ef..9b604f9e43 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -4,7 +4,10 @@ use crate::x86_64::cpuid_definitions::CpuidDefinitions; use crate::x86_64::{ CpuidOutputRegisterAdjustments, cpu_profile::CpuProfileData, - cpuid_definitions::{Parameters, ProfilePolicy}, + cpuid_definitions::{ + Parameters, ProfilePolicy, hypervisor::KVM_CPUID_DEFINITIONS, + intel::INTEL_CPUID_DEFINITIONS, + }, }; use anyhow::Context; @@ -15,6 +18,37 @@ use hypervisor::arch::x86::CpuIdEntry; use std::io::Write; use std::ops::RangeInclusive; +/// Generate CPU profile data and convert it to a string, embeddable as Rust code, which is +/// written to the given `writer` (e.g. a File). +// +// NOTE: The MVP only works with KVM as the hypervisor and Intel CPUs. +#[cfg(feature = "kvm")] +pub fn generate_profile_data( + mut writer: impl Write, + hypervisor: &dyn Hypervisor, +) -> anyhow::Result<()> { + let cpu_vendor = hypervisor.get_cpu_vendor(); + if cpu_vendor != CpuVendor::Intel { + unimplemented!("CPU profiles can only be generated for Intel CPUs at this point in time"); + } + let hypervisor_type = hypervisor.hypervisor_type(); + // This is just a reality check. + if hypervisor_type != HypervisorType::Kvm { + unimplemented!( + "CPU profiles can only be generated when using KVM as the hypervisor at this point in time" + ); + } + let supported_cpuid_sorted = supported_cpuid_sorted(hypervisor)?; + generate_cpu_profile_data_with( + hypervisor_type, + cpu_vendor, + supported_cpuid_sorted, + &INTEL_CPUID_DEFINITIONS, + &KVM_CPUID_DEFINITIONS, + &mut writer, + ) +} + /// Computes [`CpuProfileData`] based on the given sorted vector of CPUID entries, hypervisor type, cpu_vendor /// and cpuid_definitions. /// From 851d19ccfdc4195f4f3bf6a05b5e4e9dae636dc4 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 07:51:36 +0200 Subject: [PATCH 10/75] arch: Temporarily add a CPU profile for local testing We complete the DevelopmentLaptop CPU profile which we can now use for some simple local (non automated) testing. This profile is not intended to be upstreamed and should be replaced with more realistic (and useful) CPU profiles ASAP. Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- arch/src/x86_64/cpu_profile.rs | 14 +++++++++++++- arch/src/x86_64/cpu_profiles/dev_profile.json | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) create mode 100644 arch/src/x86_64/cpu_profiles/dev_profile.json diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index c1e9e5cbd1..5c5264c947 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -24,7 +24,19 @@ impl CpuProfile { pub(in crate::x86_64) fn data(&self) -> Option { match self { Self::Host => None, - Self::DevLaptop => todo!(), + Self::DevLaptop => { + /* + We only use this for local testing when developing the PoC. We should + introduce some proper CPU profiles ASAP! We should also have a better + profile for testing that can run in CI one idea would be running the + profile generation CLI on a qemu VM configured for the kvm64 CPU model or + something like that. + */ + Some( + serde_json::from_slice(include_bytes!("cpu_profiles/dev_profile.json")) + .expect("should be able to deserialize pre-generated data"), + ) + } } } diff --git a/arch/src/x86_64/cpu_profiles/dev_profile.json b/arch/src/x86_64/cpu_profiles/dev_profile.json new file mode 100644 index 0000000000..1484ce6bcc --- /dev/null +++ b/arch/src/x86_64/cpu_profiles/dev_profile.json @@ -0,0 +1 @@ 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Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- arch/src/x86_64/cpu_profile.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index 5c5264c947..9f0edc9885 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -34,6 +34,9 @@ impl CpuProfile { */ Some( serde_json::from_slice(include_bytes!("cpu_profiles/dev_profile.json")) + .inspect_err(|e| { + error!("BUG: could not deserialize CPU profile. Got error: {:?}", e) + }) .expect("should be able to deserialize pre-generated data"), ) } From 2bfc8b8f21e9c5ea427a94d24ed8069e10cad82d Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 7 Oct 2025 08:21:16 +0200 Subject: [PATCH 12/75] arch: Check for CPU Vendor compatibility with CPU profile When generating the common CPUID we utilize a CPU profile if given, but the current compatibility checks don't check that the CPU vendors between the current host and the compatibility target coincide. Hence we introduce this extra check here. We are happy to have it as a stand alone check for now, but we should consider making this part of the check_cpuid_compatibility function in the future. Signed-Off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- arch/src/x86_64/mod.rs | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index b7c82afbc0..41de9355b4 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -18,7 +18,7 @@ mod mptable; pub mod regs; use std::mem; -use anyhow::Context; +use anyhow::{Context, anyhow}; use hypervisor::arch::x86::{CPUID_FLAG_VALID_INDEX, CpuIdEntry}; use hypervisor::{CpuVendor, HypervisorCpuError, HypervisorError}; use linux_loader::loader::bootparam::{boot_params, setup_header}; @@ -631,7 +631,7 @@ pub fn generate_common_cpuid( let use_custom_profile = config.profile != CpuProfile::Host; // Obtain cpuid entries that are adjusted to the specified CPU profile and the cpuid entries of the compatibility target // TODO: Try to write this in a clearer way - let (mut host_adjusted_to_profile, mut compatibility_target_cpuid) = { + let (mut host_adjusted_to_profile, mut compatibility_target_cpuid, profile_cpu_vendor) = { config .profile .data() @@ -642,11 +642,23 @@ pub fn generate_common_cpuid( &profile_data.adjustments, )), Some(profile_data.compatibility_target), + Some(profile_data.cpu_vendor), ) }) - .unwrap_or((None, None)) + .unwrap_or((None, None, None)) }; + // There should be relatively few cases where live migration can succeed between hosts from different + // CPU vendors and making our checks account for that possibility would complicate things substantially. + // We thus require that the host's cpu vendor matches the one used to generate the CPU profile. + if let Some(profile_cpu_vendor) = profile_cpu_vendor + && profile_cpu_vendor != hypervisor.get_cpu_vendor() + { + return Err(Error::CpuProfileIncompatibility(anyhow!( + "Unable to utilize CPU profile: CPU vendor mismatch detected" + )) + .into()); + } // We now make the modifications according to the config parameters to each of the cpuid entries // declared above and then perform a compatibility check. for cpuid_optiion in [ @@ -654,10 +666,10 @@ pub fn generate_common_cpuid( host_adjusted_to_profile.as_mut(), compatibility_target_cpuid.as_mut(), ] { - let Some(mut cpuid) = cpuid_optiion else { + let Some(cpuid) = cpuid_optiion else { break; }; - CpuidPatch::patch_cpuid(&mut cpuid, &cpuid_patches); + CpuidPatch::patch_cpuid(cpuid, &cpuid_patches); #[cfg(feature = "tdx")] let tdx_capabilities = if config.tdx { From 9b3e7f3d84b20ce36a7dbe5c43a764005ae21c25 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Wed, 29 Oct 2025 14:59:17 +0100 Subject: [PATCH 13/75] Add skylake profile --- arch/src/x86_64/cpu_profile.rs | 8 ++++++++ arch/src/x86_64/cpu_profiles/skylake-profile.json | 1 + 2 files changed, 9 insertions(+) create mode 100644 arch/src/x86_64/cpu_profiles/skylake-profile.json diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index 9f0edc9885..c5e4ad5ca3 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -16,6 +16,7 @@ pub enum CpuProfile { // Having such a variant would be good for testing in CI, but should not become part of the shipped // cloud hypervisor. DevLaptop, + Skylake, } impl CpuProfile { @@ -40,6 +41,13 @@ impl CpuProfile { .expect("should be able to deserialize pre-generated data"), ) } + Self::Skylake => Some( + serde_json::from_slice(include_bytes!("cpu_profiles/skylake-profile.json")) + .inspect_err(|e| { + error!("BUG: could not deserialize CPU profile. Got error: {:?}", e) + }) + .expect("should be able to deserialize pre-generated data"), + ), } } diff --git a/arch/src/x86_64/cpu_profiles/skylake-profile.json b/arch/src/x86_64/cpu_profiles/skylake-profile.json new file mode 100644 index 0000000000..ec458c2aed --- /dev/null +++ b/arch/src/x86_64/cpu_profiles/skylake-profile.json @@ -0,0 +1 @@ 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DevLaptop, Skylake, + SapphireRapids, } impl CpuProfile { @@ -48,6 +49,13 @@ impl CpuProfile { }) .expect("should be able to deserialize pre-generated data"), ), + Self::SapphireRapids => Some( + serde_json::from_slice(include_bytes!("cpu_profiles/sapphire-rapids.json")) + .inspect_err(|e| { + error!("BUG: could not deserialize CPU profile. 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TODO: Set applicability of the migration check to never ValueDefinition{ short: "ospke", description: "OS protection keys enable", bits_range: (4, 4), policy: ProfilePolicy::Passthrough , migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // QEMU seems to set this unconditionally whenever KVM supports it (TODO: Would it be best to also set this unconditionally?) - ValueDefinition{ short: "waitpkg", description: "WAITPKG instructions", bits_range: (5, 5), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + // TODO: QEMU seems to set this unconditionally whenever KVM supports it (TODO: Would it be best to set this unconditionally?) + ValueDefinition{ short: "waitpkg", description: "WAITPKG instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, ValueDefinition{ short: "avx512_vbmi2", description: "AVX-512 vector byte manipulation instructions group 2", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: This may be useful for nested virtualization? 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"Brand index", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, ValueDefinition{ short: "clflush_size", description: "CLFLUSH instruction cache line size", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, // TODO: The logical CPU count may be relevant for live migration whenever pinning has been set up, but the pinning setup needs to make these checks and we don't set a general requirement here (at least for now) ValueDefinition{ short: "n_logical_cpu", description: "Logical CPU count", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, From b9a177f12302940d991191cf35ae5fb451471b02 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Wed, 12 Nov 2025 10:52:22 +0100 Subject: [PATCH 19/75] Update policy for local apic --- arch/src/x86_64/cpuid_definitions/intel.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index 353aa20490..03d03717fb 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -54,10 +54,10 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinitions::new(&[ ValueDefinition{ short: "brand_id", description: "Brand index", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, ValueDefinition{ short: "clflush_size", description: "CLFLUSH instruction cache line size", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - // TODO: The logical CPU count may be relevant for live migration whenever pinning has been set up, but the pinning setup needs to make these checks and we don't set a general requirement here (at least for now) - ValueDefinition{ short: "n_logical_cpu", description: "Logical CPU count", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - // TODO: Not sure about which policy to set for local_apic_id - ValueDefinition{ short: "local_apic_id", description: "Initial local APIC physical ID", bits_range: (24, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + // This is set by cloud hypervisor + ValueDefinition{ short: "n_logical_cpu", description: "Logical CPU count", bits_range: (16, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + // This is set by cloud hypervisor + ValueDefinition{ short: "local_apic_id", description: "Initial local APIC physical ID", bits_range: (24, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, ]) ), From e4e02b77df79c5109139ce3050c8a3a84e5bf97b Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Wed, 12 Nov 2025 11:37:50 +0100 Subject: [PATCH 20/75] Leaf 0x1 updates --- arch/src/x86_64/cpuid_definitions/intel.rs | 43 ++++++++++------------ 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index 03d03717fb..1d11410233 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -66,44 +66,43 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinitions::new(&[ ValueDefinition{ short: "sse3", description: "Streaming SIMD Extensions 3 (SSE3)", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "pclmulqdq", description: "PCLMULQDQ instruction support", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - // TODO: This seems to be debug related hence we set it to 0 for CPU profiles. Is this a good choice? ValueDefinition{ short: "dtes64", description: "64-bit DS save area", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Perhaps there should be some CHV feature for opting in to enabling this for non-host CPU profiles? ValueDefinition{ short: "monitor", description: "MONITOR/MWAIT support", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "ds_cpl", description: "CPL Qualified Debug Store", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - // TODO: Is this a good default? Might be useful for nested virtualization ... - ValueDefinition{ short: "vmx", description: "Virtual Machine Extensions", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: We choose to disable it for all CPU profiles for now. It is also not set for any CPU model in QEMU from what we can tell. + // TODO: Ideally configurable by the user (host must have this otherwise CHV will not run) + ValueDefinition{ short: "vmx", description: "Virtual Machine Extensions", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(1), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "smx", description: "Safer Mode Extensions", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "est", description: "Enhanced Intel SpeedStep", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "tm2", description: "Thermal Monitor 2", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "ssse3", description: "Supplemental SSE3", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: It seems like this can only have performance implications, and nothing else. It would probably also be OK to ignore this when checking migration compatibility - ValueDefinition{ short: "cid", description: "L1 Context ID", bits_range: (10, 10), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related + ValueDefinition{ short: "cnxt_id", description: "L1 Context ID", bits_range: (10, 10), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "sdbg", description: "Silicon Debug", bits_range: (11, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "fma", description: "FMA extensions using YMM state", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "cx16", description: "CMPXCHG16B instruction support", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related ValueDefinition{ short: "xtpr", description: "xTPR Update Control", bits_range: (14, 14), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pdcm", description: "Perfmon and Debug Capability", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related + ValueDefinition{ short: "pdcm", description: "Perfmon and Debug Capability", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "pcid", description: "Process-context identifiers", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "dca", description: "Direct Cache Access", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "dca", description: "Direct Cache Access", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "sse4_1", description: "SSE4.1", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "sse4_2", description: "SSE4.2", bits_range: (20, 20), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Needs special support from KVM (See: https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-cpuid) and must be setup separately. I think this may be on by default in QEMU for all models? - // Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? - ValueDefinition{ short: "x2apic", description: "X2APIC support", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // Set by Cloud hypervisor + ValueDefinition{ short: "x2apic", description: "X2APIC support", bits_range: (21, 21), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "movbe", description: "MOVBE instruction support", bits_range: (22, 22), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "popcnt", description: "POPCNT instruction support", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Needs special support from KVM (See: https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-cpuid) and must be setup separately (NOTE: CHV is currently setting this unconditionally though. why?) - // Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? - ValueDefinition{ short: "tsc_deadline_timer", description: "APIC timer one-shot operation", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // Set by Cloud hypervisor + ValueDefinition{ short: "tsc_deadline_timer", description: "APIC timer one-shot operation", bits_range: (24, 24), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "aes", description: "AES instructions", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "xsave", description: "XSAVE (and related instructions) support", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Seems to no longer be supported by QEMU, but is by KVM? We disable this for now. - ValueDefinition{ short: "osxsave", description: "XSAVE (and related instructions) are enabled by OS", bits_range: (27, 27), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "osxsave", description: "XSAVE (and related instructions) are enabled by OS", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "avx", description: "AVX instructions support", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "f16c", description: "Half-precision floating-point conversion support", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "rdrand", description: "RDRAND instruction support", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: If set by CHV set to 0 and write comment ValueDefinition{ short: "guest_status", description: "System is running as guest; (para-)virtualized system", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ]) ), @@ -113,7 +112,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinitions::new(&[ ValueDefinition{ short: "fpu", description: "Floating-Point Unit on-chip (x87)", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "vme", description: "Virtual-8086 Mode Extensions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "de", description: "Debugging Extensions", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "de", description: "Debugging Extensions", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "pse", description: "Page Size Extension", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Does this also need special handling like TSC_DEADLINE_TIMER? ValueDefinition{ short: "tsc", description: "Time Stamp Counter", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, @@ -121,8 +120,8 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinition{ short: "pae", description: "Physical Address Extensions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "mce", description: "Machine Check Exception", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "cx8", description: "CMPXCHG8B instruction", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Does this also require special handling like x2apic? ValueDefinition{ short: "apic", description: "APIC on-chip", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related (maybe not necessary to look into which ones) ValueDefinition{ short: "sep", description: "SYSENTER, SYSEXIT, and associated MSRs", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "mtrr", description: "Memory Type Range Registers", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "pge", description: "Page Global Extensions", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, @@ -130,19 +129,15 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinition{ short: "cmov", description: "Conditional Move Instruction", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "pat", description: "Page Attribute Table", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "pse36", description: "Page Size Extension (36-bit)", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pn", description: "Processor Serial Number", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Could an untrusted guest potentially slow down other guests with this feature? - ValueDefinition{ short: "clflush", description: "CLFLUSH instruction", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "dts", description: "Debug Store", bits_range: (21, 21), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "psn", description: "Processor Serial Number", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "clfsh", description: "CLFLUSH instruction", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ds", description: "Debug Store", bits_range: (21, 21), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "acpi", description: "Thermal monitor and clock control", bits_range: (22, 22), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: MMX is deprecated as far as we know. Should we consider setting this to 0 by default for all CPU profiles? ValueDefinition{ short: "mmx", description: "MMX instructions", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "fxsr", description: "FXSAVE and FXRSTOR instructions", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "sse", description: "SSE instructions", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "sse2", description: "SSE2 instructions", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure if we should support self snoop for CPU profiles. Qemu does though... ValueDefinition{ short: "ss", description: "Self Snoop", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Perhaps this needs to be configured purely through CPU features/Options instead? (Also seems to be related to CPU topology) ValueDefinition{ short: "htt", description: "Hyper-threading", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "tm", description: "Thermal Monitor", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, From 2384066de38492cbcc22b44aeb8e57f27003b7e9 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Wed, 12 Nov 2025 13:34:40 +0100 Subject: [PATCH 21/75] leaf 0x5 --- arch/src/x86_64/cpuid_definitions/intel.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index 1d11410233..5ff33767f0 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -142,7 +142,8 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinition{ short: "tm", description: "Thermal Monitor", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Not really sure what the default should be for PBE. It seems like it is something that needs to be enabled via the IA32_MISC_ENABLE MSR hence perhaps this should be set via CPU features? - ValueDefinition{ short: "pbe", description: "Pending Break Enable", bits_range: (31, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related + ValueDefinition{ short: "pbe", description: "Pending Break Enable", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ]) ), From dc64e0df33717c54f2b7bda6e81ddf8df0b48b7f Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Wed, 12 Nov 2025 14:22:40 +0100 Subject: [PATCH 22/75] leaf 0x7 sub-leaf 0 --- arch/src/x86_64/cpuid_definitions/intel.rs | 105 +++++++++------------ 1 file changed, 47 insertions(+), 58 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index 5ff33767f0..e794a66bc4 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -241,7 +241,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ( Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, ValueDefinitions::new(&[ - // TODO: Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? ValueDefinition{ short: "min_mon_size", description: "Smallest monitor-line size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::LtEq }, ]) ), @@ -249,7 +248,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ( Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, ValueDefinitions::new(&[ - // TODO: Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? ValueDefinition{ short: "max_mon_size", description: "Largest monitor-line size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, ]) ), @@ -258,7 +256,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, ValueDefinitions::new(&[ ValueDefinition{ short: "mwait_ext", description: "Enumeration of MONITOR/MWAIT extensions is supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Perhaps there should be some CHV feature to opt-in to this for non-host cpu profiles? ValueDefinition{ short: "mwait_irq_break", description: "Interrupts as a break-event for MWAIT is supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ]) ), @@ -266,14 +263,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ( Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, ValueDefinitions::new(&[ - ValueDefinition{ short: "n_c0_substates", description: "Number of C0 sub C-states supported using MWAIT", bits_range: (0, 3), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c1_substates", description: "Number of C1 sub C-states supported using MWAIT", bits_range: (4, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c2_substates", description: "Number of C2 sub C-states supported using MWAIT", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c3_substates", description: "Number of C3 sub C-states supported using MWAIT", bits_range: (12, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c4_substates", description: "Number of C4 sub C-states supported using MWAIT", bits_range: (16, 19), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c5_substates", description: "Number of C5 sub C-states supported using MWAIT", bits_range: (20, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c6_substates", description: "Number of C6 sub C-states supported using MWAIT", bits_range: (24, 27), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c7_substates", description: "Number of C7 sub C-states supported using MWAIT", bits_range: (28, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c0_substates", description: "Number of C0 sub C-states supported using MWAIT", bits_range: (0, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c1_substates", description: "Number of C1 sub C-states supported using MWAIT", bits_range: (4, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c2_substates", description: "Number of C2 sub C-states supported using MWAIT", bits_range: (8, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c3_substates", description: "Number of C3 sub C-states supported using MWAIT", bits_range: (12, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c4_substates", description: "Number of C4 sub C-states supported using MWAIT", bits_range: (16, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c5_substates", description: "Number of C5 sub C-states supported using MWAIT", bits_range: (20, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c6_substates", description: "Number of C6 sub C-states supported using MWAIT", bits_range: (24, 27), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "n_c7_substates", description: "Number of C7 sub C-states supported using MWAIT", bits_range: (28, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, ]) ), @@ -319,10 +316,11 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ( Parameters{ leaf: 0x6, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, ValueDefinitions::new(&[ + // MSR related ValueDefinition{ short: "aperfmperf", description: "MPERF/APERF MSRs (effective frequency interface)", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related ValueDefinition{ short: "epb", description: "IA32_ENERGY_PERF_BIAS MSR support", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about the defaults for this one, but I think since we have disabled thread director support (0x6 EAX bit 23) we can probably just passthrough whatever here and. Not sure about migration compatibility (for the Host profile) though. - ValueDefinition{ short: "thrd_director_nclasses", description: "Number of classes, Intel thread director", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "thrd_director_nclasses", description: "Number of classes, Intel thread director", bits_range: (8, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, ]) ), @@ -331,8 +329,8 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinitions::new(&[ ValueDefinition{ short: "perfcap_reporting", description: "Performance capability reporting", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "encap_reporting", description: "Energy efficiency capability reporting", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "feedback_sz", description: "Feedback interface structure size, in 4K pages", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "this_lcpu_hwfdbk_idx", description: "This logical CPU hardware feedback interface index", bits_range: (16, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "feedback_sz", description: "Feedback interface structure size, in 4K pages", bits_range: (8, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, + ValueDefinition{ short: "this_lcpu_hwfdbk_idx", description: "This logical CPU hardware feedback interface index", bits_range: (16, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, ]) ), @@ -351,17 +349,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, ValueDefinitions::new(&[ ValueDefinition{ short: "fsgsbase", description: "FSBASE/GSBASE read/write support", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "tsc_adjust", description: "IA32_TSC_ADJUST MSR supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related + ValueDefinition{ short: "tsc_adjust", description: "IA32_TSC_ADJUST MSR supported", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // SGX is deprecated so we disable it unconditionally for all CPU profiles ValueDefinition{ short: "sgx", description: "Intel SGX (Software Guard Extensions)", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, ValueDefinition{ short: "bmi1", description: "Bit manipulation extensions group 1", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TSX related which is riddled with CVEs - ValueDefinition{ short: "hle", description: "Hardware Lock Elision", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TSX related which is riddled with CVEs. Consider two profiles, or making it opt-in/out. QEMU always has a CPU model with and without TSX. + ValueDefinition{ short: "hle", description: "Hardware Lock Elision", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "avx2", description: "AVX2 instruction set", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, /*The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). Keep in mind however that in my limited understanding this isn't about enabling or disabling a feature, but it describes critical behaviour. - Hence I am wondering whether it should be a hard error if the host does not have this bit set, but the desired CPU profile does? */ + Hence I am wondering whether it should be a hard error if the host does not have this bit set, but the desired CPU profile does? + + TODO: Check what KVM_GET_SUPPORTED_CPUID actually gives here (on the Skylake server) + */ ValueDefinition{ short: "fdp_excptn_only", description: "FPU Data Pointer updated only on x87 exceptions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "smep", description: "Supervisor Mode Execution Protection", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "bmi2", description: "Bit manipulation extensions group 2", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, @@ -371,8 +373,8 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { I included this because it seems like QEMU does (to the best of my understanding). */ ValueDefinition{ short: "invpcid", description: "INVPCID instruction (Invalidate Processor Context ID)", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // This is TSX related from what I can tell. TSX is riddled with CVEs hence we disable this - ValueDefinition{ short: "rtm", description: "Intel restricted transactional memory", bits_range: (11, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // This is TSX related from what I can tell. TSX is riddled with CVEs: Consider two profiles (one with it disabled) or an opt-in/out feature. + ValueDefinition{ short: "rtm", description: "Intel restricted transactional memory", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "rdt_m", description: "Supports Intel Resource Director Technology Monitoring Capability if 1", bits_range: (12, 12), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). TODO: Is it OK to just set this to 1? ValueDefinition{ short: "zero_fcs_fds", description: "Deprecates FPU CS and FPU DS values if 1", bits_range: (13, 13), policy: ProfilePolicy::Overwrite(1), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, @@ -409,13 +411,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinition{ short: "umip", description: "User mode instruction protection", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, // Also set by QEMU for CPU models from what we can tell ValueDefinition{ short: "pku", description: "Protection keys for user-space", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Presumably this is set by the OS? TODO: Set applicability of the migration check to never - ValueDefinition{ short: "ospke", description: "OS protection keys enable", bits_range: (4, 4), policy: ProfilePolicy::Passthrough , migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ospke", description: "OS protection keys enable", bits_range: (4, 4), policy: ProfilePolicy::Inherit , migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: QEMU seems to set this unconditionally whenever KVM supports it (TODO: Would it be best to set this unconditionally?) ValueDefinition{ short: "waitpkg", description: "WAITPKG instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, ValueDefinition{ short: "avx512_vbmi2", description: "AVX-512 vector byte manipulation instructions group 2", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: This may be useful for nested virtualization? Perhaps it should be opt-in rather than unconditionally disabled? - ValueDefinition{ short: "cet_ss", description: "CET shadow stack features", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "cet_ss", description: "CET shadow stack features", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "gfni", description: "Galois field new instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "vaes", description: "Vector AES instructions", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "vpclmulqdq", description: "VPCLMULQDQ 256-bit instruction support", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, @@ -427,34 +428,22 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinition{ short: "avx512_vpopcntdq", description: "AVX-512: POPCNT for vectors of DWORD/QWORD", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "la57", description: "57-bit linear addresses (five-level paging)", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MMX is deprecated, but we should perhaps still check for equality here when migrating - ValueDefinition{ short: "mawau_val_lm", description: "BNDLDX/BNDSTX MAWAU value in 64-bit mode", bits_range: (17, 21), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "mawau_val_lm", description: "BNDLDX/BNDSTX MAWAU value in 64-bit mode", bits_range: (17, 21), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + // MSR related ValueDefinition{ short: "rdpid", description: "RDPID instruction", bits_range: (22, 22), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, // We leave key locker support out for CPU profiles for the time being. We may want this to be opt-in in the future though ValueDefinition{ short: "key_locker", description: "Intel key locker support", bits_range: (23, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, ValueDefinition{ short: "bus_lock_detect", description: "OS bus-lock detection", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - /* - TODO: Should this be off by default? Can untrusted guests potentially abuse this to slow down other guests? - According to https://www.felixcloutier.com/x86/cldemote : - > On processors which do not support the CLDEMOTE instruction (including legacy hardware) the instruction will be treated as a NOP. - This suggests that is should even be fine to migrate from a host with this feature to one which does not have it. - TODO: Set migrationcheck applicability to never - */ + ValueDefinition{ short: "cldemote", description: "CLDEMOTE instruction", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "movdiri", description: "MOVDIRI instruction", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "movdir64b", description: "MOVDIR64B instruction", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - /* - This could be important for nested virtualization and perhaps for certain other applications. It does not seem to be enabled for CPU models in QEMU however, hence we - also leave it out for now, but should reconsider if/how to add it in the future. - */ + ValueDefinition{ short: "enqcmd", description: "Enqueue stores supported (ENQCMD{,S})", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // SGX support is deprecated so we disable it unconditionally for CPU profiles ValueDefinition{ short: "sgx_lc", description: "Intel SGX launch configuration", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - /* - I was not able to find much information on this feature. It seems like QEMU can emulate it, but does not set if for any available CPU model as far as I can tell. - It also seems to be mainly relevant for hosts and not guests (except perhaps for nested virtualization). - */ + ValueDefinition{ short: "pks", description: "Protection keys for supervisor-mode pages", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ]) ), @@ -467,10 +456,10 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinition{ short: "avx512_4vnniw", description: "AVX-512 neural network instructions (Intel Xeon Phi only?)", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "avx512_4fmaps", description: "AVX-512 multiply accumulation single precision (Intel Xeon Phi only?)", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "fsrm", description: "Fast short REP MOV", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: To me this seems very powerful and I am wondering if it can be abused by guests. Is it indeed right to disable this for all CPU profiles as I expect we should? + ValueDefinition{ short: "uintr", description: "CPU supports user interrupts", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "avx512_vp2intersect", description: "VP2INTERSECT{D,Q} instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: This seems to be CVE related and we should investigate this more thoroughly + // MSR related ValueDefinition{ short: "srdbs_ctrl", description: "SRBDS mitigation MSR available: If 1, enumerates support for the IA32_MCU_OPT_CTRL MSR and indicates that its bit 0 (RNGDS_MITG_DIS) is also supported.", @@ -478,40 +467,40 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: This seems to be CVE related and should be checked more carefully: See https://www.kernel.org/doc/html/next/x86/mds.html#microarchitectural-data-sampling-mds-mitigation + ValueDefinition{ short: "md_clear", description: "VERW MD_CLEAR microcode support", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: This seems to be CVE related and should be checked more carefully + ValueDefinition{ short: "rtm_always_abort", description: "XBEGIN (RTM transaction) always aborts", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: This seems to be CVE related and should be checked more carefully + ValueDefinition{ short: "tsx_force_abort", description: "MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "serialize", description: "SERIALIZE instruction", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure what to set here. I am guessing CPU profiles should not exist for hybrid CPUs in the first place (at least not for now). + ValueDefinition{ short: "hybrid_cpu", description: "The CPU is identified as a 'hybrid part'", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: This is TSX related which is riddled with CVEs. We should carefully decide what to do with regards to this feature. ValueDefinition{ short: "tsxldtrk", description: "TSX suspend/resume load address tracking", bits_range: (16, 16), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Seems rather complex. We disable it unconditionally for CPU profiles for now. - // TODO: Remember to set any other pconfig dependency to ony apply if this is set + // Might be relevant for confidential computing ValueDefinition{ short: "pconfig", description: "PCONFIG instruction", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Seems to be mainly useful for debugging and monitoring, which are classes of features we tend to avoid advertising to the guest. + // MSR related ValueDefinition{ short: "arch_lbr", description: "Intel architectural LBRs", bits_range: (19, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Not sure if this is the best default, but QEMU also seems to disable this for CPU models - ValueDefinition{ short: "ibt", description: "CET indirect branch tracking", bits_range: (20, 20), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ibt", description: "CET indirect branch tracking", bits_range: (20, 20), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "amx_bf16", description: "AMX-BF16: tile bfloat16 support", bits_range: (22, 22), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "avx512_fp16", description: "AVX-512 FP16 instructions", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "amx_tile", description: "AMX-TILE: tile architecture support", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "amx_int8", description: "AMX-INT8: tile 8-bit integer support", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Seems to be CVE related and should be checked more thoroughly + // MSR related ValueDefinition{ short: "spec_ctrl", description: "Speculation Control (IBRS/IBPB: indirect branch restrictions)", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: This is CVE related and should be checked more thoroughly + // MSR related ValueDefinition{ short: "intel_stibp", description: "Single thread indirect branch predictors", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Is it a good default to leave this out for CPU profiles. Do we perhaps need an option to opt-in? - ValueDefinition{ short: "flush_l1d", description: "FLUSH L1D cache: IA32_FLUSH_CMD MSR", bits_range: (28, 28), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Really not sure what policies to set for this one + // MSR related + ValueDefinition{ short: "flush_l1d", description: "FLUSH L1D cache: IA32_FLUSH_CMD MSR", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related ValueDefinition{ short: "arch_capabilities", description: "Intel IA32_ARCH_CAPABILITIES MSR", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Is this a good default for CPU profiles? + // MSR related ValueDefinition{ short: "core_capabilities", description: "IA32_CORE_CAPABILITIES MSR", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Spectre related. Should be checked carefully + // MSR related ValueDefinition{ short: "spec_ctrl_ssbd", description: "Speculative store bypass disable", bits_range: (31, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ]) ), From b67e6a1f9dd79cd80c0f79476d971d5e904fa5c0 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Wed, 12 Nov 2025 14:55:55 +0100 Subject: [PATCH 23/75] Leaf 0x7 --- arch/src/x86_64/cpuid_definitions/intel.rs | 64 +++++++++++----------- 1 file changed, 33 insertions(+), 31 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index e794a66bc4..6841b4b506 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -529,42 +529,43 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinition{ short: "fzrm", description: "Fast zero-length REP MOVSB", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "fsrs", description: "Fast short REP STOSB", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "fsrc", description: "Fast Short REP CMPSB/SCASB", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Not sure if not setting this is a good default. It is our understanding that QEMU doesn't enable this for CPU models, but CHV does set this unconditionally for all guests? - ValueDefinition{ short: "fred", description: "FRED: Flexible return and event delivery transitions", bits_range: (17, 17), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Not sure if not setting this is a good default. It is our understanding that QEMU doesn't enable this for CPU models, but CHV does set this unconditionally for all guests? - ValueDefinition{ short: "lkgs", description: "LKGS: Load 'kernel' (userspace) GS", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // QEMU also seems to not set this for CPU models - ValueDefinition{ short: "wrmsrns", description: "WRMSRNS instruction (WRMSR-non-serializing)", bits_range: (19, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "fred", description: "FRED: Flexible return and event delivery transitions", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "lkgs", description: "LKGS: Load 'kernel' (userspace) GS", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "wrmsrns", description: "WRMSRNS instruction (WRMSR-non-serializing)", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "nmi_src", description: "NMI-source reporting with FRED event data", bits_range: (20, 20), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "amx_fp16", description: "AMX-FP16: FP16 tile operations", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "hreset", description: "History reset support", bits_range: (22, 22), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "avx_ifma", description: "Integer fused multiply add", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Seems to be related to spectre and should be checked carefully - ValueDefinition{ short: "lam", description: "Linear address masking", bits_range: (26, 26), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure if not setting this is the best default. I think that is also what QEMU does though. - ValueDefinition{ short: "rd_wr_msrlist", description: "RDMSRLIST/WRMSRLIST instructions", bits_range: (27, 27), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about this one - ValueDefinition{ short: "invd_disable_post_bios_done", description: "If 1, supports INVD execution prevention after BIOS Done", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: This feature does not exist yet as far as we know - ValueDefinition{ short: "movrs", description: "MOVRS", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "lam", description: "Linear address masking", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "rd_wr_msrlist", description: "RDMSRLIST/WRMSRLIST instructions", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "invd_disable_post_bios_done", description: "If 1, supports INVD execution prevention after BIOS Done", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "movrs", description: "MOVRS", bits_range: (31, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ]) ), ( Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, ValueDefinitions::new(&[ - // TODO: Is disabling this a good default for CPU profiles? + ValueDefinition{ short: "intel_ppin", description: "Protected processor inventory number (PPIN{,_CTL} MSRs)", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // We zero this out for CPU profiles for the time being + + // MSR related ValueDefinition{ short: "pbndkb", description: "PBNDKB instruction supported and enumerates the existence of the IA32_TSE_CAPABILITY MSR", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ]) ), // TODO: Missing entry for (0x7, 1, ECX) + // Make the whole register zero though // - // TODO: Double check the AVX VNNI instructions ( Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EDX }, ValueDefinitions::new(&[ @@ -573,20 +574,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the value will be zeroed out if the user has not opted in for "amx" via CpuFeatures. ValueDefinition{ short: "amx_complex", description: "AMX-COMPLEX instructions (starting from Granite Rapids)", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "avx_vnni_int16", description: "AVX-VNNI-INT16 instructions", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about this one. TODO: THe current policy is probably wrong .. - ValueDefinition{ short: "utmr", description: "If 1, supports user-timer events", bits_range: (13, 13), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + + ValueDefinition{ short: "utmr", description: "If 1, supports user-timer events", bits_range: (13, 13), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, ValueDefinition{ short: "prefetchit_0_1", description: "PREFETCHIT0/1 instructions", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + // MSR related + ValueDefinition{ short: "user_msr", description: "If 1, supports the URDMSR and UWRMSR instructions", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, + + ValueDefinition{ short: "uiret_uif", description: "If 1, UIRET sets UIF to the value of bit 1 of the RFLAGS image loaded from the stack", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "user_msr", description: "If 1, supports the URDMSR and UWRMSR instructions", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - // TODO: Check which policy to use - ValueDefinition{ short: "uiret_uif", description: "If 1, UIRET sets UIF to the value of bit 1 of the RFLAGS image loaded from the stack", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - // TODO: Not sure about this one ValueDefinition{ short: "cet_sss", description: "CET supervisor shadow stacks safe to use", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "avx10", description: "If 1, supports the Intel AVX10 instructions and indicates the presence of leaf 0x24", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "apx_f", description: "If 1, the processor provides foundational support for Intel Advanced Performance Extensions", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Should this perhaps be opt-in ? + ValueDefinition{ short: "mwait", description: "If 1, MWAIT is supported even if (0x1 ECX bit 3 (monitor) is enumerated as 0)", bits_range: (23, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related ValueDefinition{ short: "slsm", description: "If 1, indicates bit 0 of the IA32_INTEGRITY_STATUS MSR is supported. Bit 0 of this MSR indicates whether static lockstep is active on this logical processor", bits_range: (24, 24), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ]) ), @@ -597,19 +599,19 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ( Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EDX }, ValueDefinitions::new(&[ - // TODO: Not sure about this one + // MSR related ValueDefinition{ short: "intel_psfd", description: "If 1, indicates bit 7 of the IA32_SPEC_CTRL_MSR is supported. Bit 7 of this MSR disables fast store forwarding predictor without disabling speculative store bypass", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about this one and consider adding a better description + // MSR related ValueDefinition{ short: "ipred_ctrl", description: "MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about this one and consider adding a better description + // MSR related ValueDefinition{ short: "rrsba_ctrl", description: "MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about this one and consider adding a better description + // MSR related ValueDefinition{ short: "ddp_ctrl", description: "MSR bit IA32_SPEC_CTRL.DDPD_U", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about this one and consider adding a better description + // MSR related ValueDefinition{ short: "bhi_ctrl", description: "MSR bit IA32_SPEC_CTRL.BHI_DIS_S", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about this one and consider adding a better description + // MSR related ValueDefinition{ short: "mcdt_no", description: "MCDT mitigation not needed", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about this one and consider adding a better description + // MSR related ValueDefinition{ short: "uclock_disable", description: "UC-lock disable is supported", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, ]) ), From 68d8b7f147c3cd63b77a02126d34e8d18b5dc34f Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Wed, 12 Nov 2025 15:37:37 +0100 Subject: [PATCH 24/75] More fixes --- arch/src/x86_64/cpuid_definitions/intel.rs | 26 +++++++++++++--------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index 6841b4b506..1bee0036ed 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -622,8 +622,8 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ( Parameters{ leaf: 0x9, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, ValueDefinitions::new(&[ - // TODO: Can this be used to check whether DCA is enabled? (or should one not rely on this and use another feature flag?) - ValueDefinition{ short: "dca_enabled_in_bios", description: "DCA is enabled in BIOS", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, + // MSR related + ValueDefinition{ short: "dca_cap_msr_value", description: "Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1f8H)", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, ]) ), @@ -631,6 +631,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { // Architectural Performance Monitoring // =================================================================================================================== // We will just zero out everything to do with PMU for CPU profiles and require equality for migration to be considered compatible (for the time being). + // TODO: Left for another day ( Parameters{ leaf: 0xa, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, ValueDefinitions::new(&[ @@ -676,6 +677,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { // =================================================================================================================== // Leaf 0xB must be set by CHV itself (and do all necessary checks) hence we can ignore checking for migration compatibility here + // TODO: Set by cloud hypervisor. Set this to 0 with a comment that CHV will set it instead. ( Parameters{ leaf: 0xb, sub_leaf:RangeInclusive::new( 0, u32::MAX), register: CpuidReg::EAX }, ValueDefinitions::new(&[ @@ -711,7 +713,8 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { // =================================================================================================================== // Processor Extended State Enumeration Main Leaf // =================================================================================================================== - + // TODO: Figure out properly when to use Inherit vs Passthrough + // TODO: Check that CHV checks for migration compatibility here ( Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, ValueDefinitions::new(&[ @@ -725,11 +728,11 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinition{ short: "xcr0_avx512_opmask", description: "XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "xcr0_avx512_zmm_hi256", description: "XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "xcr0_avx512_hi16_zmm", description: "XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure which profile policy to apply here - ValueDefinition{ short: "xcr0_ia32_xss", description: "XCR0.IA32_XSS (bit 8) used for IA32_XSS", bits_range: (8, 8), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // MSR related + ValueDefinition{ short: "xcr0_ia32_xss", description: "XCR0.IA32_XSS (bit 8) used for IA32_XSS", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "xcr0_pkru", description: "XCR0.PKRU (bit 9) supported (XSAVE PKRU registers)", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about this (could this be relevant for CVE mitigations?) - ValueDefinition{ short: "xcr0_ia32_xss_bits", description: "XCR0.IA32_XSS (bit 10 - 16) used for IA32_XSS", bits_range: (10, 16), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + + ValueDefinition{ short: "xcr0_ia32_xss_bits", description: "XCR0.IA32_XSS (bit 10 - 16) used for IA32_XSS", bits_range: (10, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. ValueDefinition{ short: "xcr0_tileconfig", description: "XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. @@ -740,7 +743,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ( Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, ValueDefinitions::new(&[ - // We don't need migration compatibility requirements here since we check for each individual state component + // TODO: Check if CHV checks 0xd for migration compatibility already ValueDefinition{ short: "xsave_sz_xcr0_enabled", description: "XSAVE/XRSTOR area byte size, for XCR0 enabled features", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, ]) ), @@ -756,7 +759,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ( Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, ValueDefinitions::new(&[ - ValueDefinition{ short: "xcr0_upper_bits", description: "Reports the valid bit fields of the upper 32 bits of the XCR0 register", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, + ValueDefinition{ short: "xcr0_upper_bits", description: "Reports the valid bit fields of the upper 32 bits of the XCR0 register", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, ]) ), @@ -1589,7 +1592,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ( Parameters{ leaf: 0x24, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, ValueDefinitions::new(&[ - ValueDefinition{ short: "converged_vector_isa_max_sub_leaves", description: "Reports the maximum number of sub-leaves that are supported in leaf 0x24", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq}, + ValueDefinition{ short: "converged_vector_isa_max_sub_leaves", description: "Reports the maximum number of sub-leaves that are supported in leaf 0x24", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq}, ]) ), @@ -1777,7 +1780,8 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { Parameters{ leaf: 0x80000007, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, ValueDefinitions::new(&[ // TODO: We may want some mechanism to let users opt-in to using an invariant TSC provided by the hardware (when available). - ValueDefinition{ short: "constant_tsc", description: "TSC ticks at constant rate across all P and C states", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Probably unconditionally set by CHV + ValueDefinition{ short: "constant_tsc", description: "TSC ticks at constant rate across all P and C states", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ]) ), From bd5ccc784b170c61391f8d3b97362a5758af9370 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Wed, 12 Nov 2025 16:32:58 +0100 Subject: [PATCH 25/75] Update sapphire rapids profile --- arch/src/x86_64/cpu_profiles/sapphire-rapids.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/src/x86_64/cpu_profiles/sapphire-rapids.json b/arch/src/x86_64/cpu_profiles/sapphire-rapids.json index 7c06169bb2..7b6fb9244a 100644 --- a/arch/src/x86_64/cpu_profiles/sapphire-rapids.json +++ b/arch/src/x86_64/cpu_profiles/sapphire-rapids.json @@ -1 +1 @@ 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"SSE instructions", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "sse2", description: "SSE2 instructions", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ss", description: "Self Snoop", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "ss", description: "Self Snoop", bits_range: (27, 27), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "htt", description: "Hyper-threading", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "tm", description: "Thermal Monitor", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, @@ -364,7 +364,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { TODO: Check what KVM_GET_SUPPORTED_CPUID actually gives here (on the Skylake server) */ - ValueDefinition{ short: "fdp_excptn_only", description: "FPU Data Pointer updated only on x87 exceptions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "fdp_excptn_only", description: "FPU Data Pointer updated only on x87 exceptions", bits_range: (6, 6), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "smep", description: "Supervisor Mode Execution Protection", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "bmi2", description: "Bit manipulation extensions group 2", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "erms", description: "Enhanced REP MOVSB/STOSB", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, @@ -377,7 +377,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { ValueDefinition{ short: "rtm", description: "Intel restricted transactional memory", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "rdt_m", description: "Supports Intel Resource Director Technology Monitoring Capability if 1", bits_range: (12, 12), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). TODO: Is it OK to just set this to 1? - ValueDefinition{ short: "zero_fcs_fds", description: "Deprecates FPU CS and FPU DS values if 1", bits_range: (13, 13), policy: ProfilePolicy::Overwrite(1), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "zero_fcs_fds", description: "Deprecates FPU CS and FPU DS values if 1", bits_range: (13, 13), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // This has been deprecated ValueDefinition{ short: "mpx", description: "Intel memory protection extensions", bits_range: (14, 14), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // This might be useful for certain high performance applications, but it also seems like a rather niche and advanced feature. QEMU does also not automatically enable this from what we can tell. @@ -468,7 +468,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "md_clear", description: "VERW MD_CLEAR microcode support", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "md_clear", description: "VERW MD_CLEAR microcode support", bits_range: (10, 10), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, ValueDefinition{ short: "rtm_always_abort", description: "XBEGIN (RTM transaction) always aborts", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, @@ -493,9 +493,9 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { // MSR related ValueDefinition{ short: "spec_ctrl", description: "Speculation Control (IBRS/IBPB: indirect branch restrictions)", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // MSR related - ValueDefinition{ short: "intel_stibp", description: "Single thread indirect branch predictors", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "intel_stibp", description: "Single thread indirect branch predictors", bits_range: (27, 27), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // MSR related - ValueDefinition{ short: "flush_l1d", description: "FLUSH L1D cache: IA32_FLUSH_CMD MSR", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + ValueDefinition{ short: "flush_l1d", description: "FLUSH L1D cache: IA32_FLUSH_CMD MSR", bits_range: (28, 28), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // MSR related ValueDefinition{ short: "arch_capabilities", description: "Intel IA32_ARCH_CAPABILITIES MSR", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // MSR related diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index 41de9355b4..58e91812aa 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -839,16 +839,24 @@ pub fn generate_common_cpuid( } else { // Final compatibility checks to ensure that the CPUID values we return are compatible both with the CPU profile and the host we are currently running on. let host_adjusted_to_profile = host_adjusted_to_profile.expect("The profile adjusted cpuid entries should exist as we checked that we have a custom CPU profile"); - let target_compatible_cpuid = compatibility_target_cpuid.expect("The target_compatible_cpuid entries should exist as we checked that we have a custom CPU profile"); + // TODO: Remove + // let target_compatible_cpuid = compatibility_target_cpuid.expect("The target_compatible_cpuid entries should exist as we checked that we have a custom CPU profile"); + // Check that the host's cpuid is indeed compatible with the adjusted profile. This is not by construction. + info!("checking compatibility between host adjusted to profile and the host itself"); CpuidFeatureEntry::check_cpuid_compatibility(&host_adjusted_to_profile, &host_cpuid).context("Unable to adjust the host to the CPU profile. The resulting cpuid is not compatible with the host's cpuid entries").map_err(Error::CpuProfileIncompatibility)?; + /* + info!( + "checking compatibility between the compatibility target's cpuid and the host adjusted to profile" + ); // Check that the compatibility target's cpuid is compatible with the adjusted host's (the converse is satisfied by construction). // The adjusted host will always have a CPUID that is compatible with the compatibility target (in terms of live migration requirements), but the other direction needs to be checked. CpuidFeatureEntry::check_cpuid_compatibility( &target_compatible_cpuid, &host_adjusted_to_profile, ).context("The CPU profile's compatibility target has non-trivial CPUID entries not found on this host").map_err(Error::CpuProfileIncompatibility)?; + */ Ok(host_adjusted_to_profile) } } From 9e6cd6dc0fa27dcef900cf7c4a4b6eee584e3de3 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 14 Nov 2025 13:30:00 +0100 Subject: [PATCH 28/75] Remove compatibility target. Still need to regenerate profiles --- arch/src/x86_64/cpu_profile.rs | 38 ++++++++++++++++++++--- arch/src/x86_64/cpu_profile_generation.rs | 4 --- arch/src/x86_64/mod.rs | 32 +++++-------------- 3 files changed, 41 insertions(+), 33 deletions(-) diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index 8ab929e1dc..fef7167a4b 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -80,9 +80,6 @@ pub struct CpuProfileData { pub(in crate::x86_64) cpu_vendor: CpuVendor, /// Adjustments necessary to become compatible with the desired target. pub(in crate::x86_64) adjustments: Vec<(Parameters, CpuidOutputRegisterAdjustments)>, - /// The result of adjusting the target host's default supported CPUID entries according - /// to CPU profile policy. - pub(in crate::x86_64) compatibility_target: Vec, } /* TODO: The [`CpuProfile`] struct will likely need a few more iterations. The following @@ -130,7 +127,7 @@ impl CpuidOutputRegisterAdjustments { pub(in crate::x86_64) fn adjust_cpuid_entries( mut cpuid: Vec, adjustments: &[(Parameters, Self)], - ) -> Vec { + ) -> Result, MissingCpuidEntriesError> { for entry in &mut cpuid { for (reg, reg_value) in [ (CpuidReg::EAX, &mut entry.eax), @@ -155,6 +152,37 @@ impl CpuidOutputRegisterAdjustments { adjustment.adjust(reg_value); } } - cpuid + // Check that we found every value that was supposed to be replaced with something else than 0 + let mut missing_entry = false; + for (param, adjustment) in adjustments { + if adjustment.replacements == 0 { + continue; + } + if !cpuid.iter().any(|entry| { + (entry.function == param.leaf) && (param.sub_leaf.contains(&entry.index)) + }) { + error!( + "cannot adjust CPU profile. No entry found matching the required parameters: {:?}", + param + ); + missing_entry = true; + } + } + if missing_entry { + Err(MissingCpuidEntriesError) + } else { + Ok(cpuid) + } } } + +#[derive(Debug)] +pub(in crate::x86_64) struct MissingCpuidEntriesError; + +impl core::fmt::Display for MissingCpuidEntriesError { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.write_str("Required CPUID entries not found") + } +} + +impl core::error::Error for MissingCpuidEntriesError {} diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 9b604f9e43..67479cab3e 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -118,14 +118,10 @@ fn generate_cpu_profile_data_with( } } - let compatibility_target_cpuid = - CpuidOutputRegisterAdjustments::adjust_cpuid_entries(supported_cpuid_sorted, &adjustments); - let profile_data = CpuProfileData { hypervisor: hypervisor_type, cpu_vendor, adjustments, - compatibility_target: compatibility_target_cpuid, }; serde_json::to_writer(&mut writer, &profile_data) diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index 58e91812aa..2eff8e9ba8 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -631,22 +631,24 @@ pub fn generate_common_cpuid( let use_custom_profile = config.profile != CpuProfile::Host; // Obtain cpuid entries that are adjusted to the specified CPU profile and the cpuid entries of the compatibility target // TODO: Try to write this in a clearer way - let (mut host_adjusted_to_profile, mut compatibility_target_cpuid, profile_cpu_vendor) = { + let (host_adjusted_to_profile, profile_cpu_vendor) = { config .profile .data() .map(|profile_data| { ( - Some(CpuidOutputRegisterAdjustments::adjust_cpuid_entries( + CpuidOutputRegisterAdjustments::adjust_cpuid_entries( host_cpuid.clone(), &profile_data.adjustments, - )), - Some(profile_data.compatibility_target), + ) + .map(Some), Some(profile_data.cpu_vendor), ) }) - .unwrap_or((None, None, None)) + .unwrap_or((Ok(None), None)) }; + let mut host_adjusted_to_profile = + host_adjusted_to_profile.map_err(|e| Error::CpuProfileIncompatibility(e.into()))?; // There should be relatively few cases where live migration can succeed between hosts from different // CPU vendors and making our checks account for that possibility would complicate things substantially. @@ -661,11 +663,7 @@ pub fn generate_common_cpuid( } // We now make the modifications according to the config parameters to each of the cpuid entries // declared above and then perform a compatibility check. - for cpuid_optiion in [ - Some(&mut host_cpuid), - host_adjusted_to_profile.as_mut(), - compatibility_target_cpuid.as_mut(), - ] { + for cpuid_optiion in [Some(&mut host_cpuid), host_adjusted_to_profile.as_mut()] { let Some(cpuid) = cpuid_optiion else { break; }; @@ -839,24 +837,10 @@ pub fn generate_common_cpuid( } else { // Final compatibility checks to ensure that the CPUID values we return are compatible both with the CPU profile and the host we are currently running on. let host_adjusted_to_profile = host_adjusted_to_profile.expect("The profile adjusted cpuid entries should exist as we checked that we have a custom CPU profile"); - // TODO: Remove - // let target_compatible_cpuid = compatibility_target_cpuid.expect("The target_compatible_cpuid entries should exist as we checked that we have a custom CPU profile"); // Check that the host's cpuid is indeed compatible with the adjusted profile. This is not by construction. - info!("checking compatibility between host adjusted to profile and the host itself"); CpuidFeatureEntry::check_cpuid_compatibility(&host_adjusted_to_profile, &host_cpuid).context("Unable to adjust the host to the CPU profile. The resulting cpuid is not compatible with the host's cpuid entries").map_err(Error::CpuProfileIncompatibility)?; - /* - info!( - "checking compatibility between the compatibility target's cpuid and the host adjusted to profile" - ); - // Check that the compatibility target's cpuid is compatible with the adjusted host's (the converse is satisfied by construction). - // The adjusted host will always have a CPUID that is compatible with the compatibility target (in terms of live migration requirements), but the other direction needs to be checked. - CpuidFeatureEntry::check_cpuid_compatibility( - &target_compatible_cpuid, - &host_adjusted_to_profile, - ).context("The CPU profile's compatibility target has non-trivial CPUID entries not found on this host").map_err(Error::CpuProfileIncompatibility)?; - */ Ok(host_adjusted_to_profile) } } From bf43d0243d43f81dae7ef6c83e52be591e3db1c8 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 14 Nov 2025 13:34:20 +0100 Subject: [PATCH 29/75] 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\ No newline at end of file From 356009a61fe13036b7982f5e544cca3192b86bb0 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 17 Nov 2025 15:15:06 +0100 Subject: [PATCH 31/75] x --- arch/src/x86_64/mod.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index 2eff8e9ba8..414b88270b 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -528,7 +528,11 @@ impl CpuidFeatureEntry { CpuidCompatibleCheck::BitwiseSubset => { let different_feature_bits = src_vm_feature ^ dest_vm_feature; let src_vm_feature_bits_only = different_feature_bits & src_vm_feature; - src_vm_feature_bits_only == 0 + let is_subset = src_vm_feature_bits_only == 0; + if !is_subset { + todo!(); + } + is_subset } CpuidCompatibleCheck::Equal => src_vm_feature == dest_vm_feature, CpuidCompatibleCheck::NumNotGreater => src_vm_feature <= dest_vm_feature, From 7afd3e7be67bba32dc72dc551b0725bf44d1342b Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 17 Nov 2025 15:49:56 +0100 Subject: [PATCH 32/75] Log more information about the bits that fail the cpuid compatibility check --- arch/src/x86_64/cpuid_definitions/intel.rs | 7067 +++++++++++++++----- arch/src/x86_64/cpuid_definitions/mod.rs | 2 +- arch/src/x86_64/mod.rs | 40 +- 3 files changed, 5306 insertions(+), 1803 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index ce41cb2193..fd796f6152 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -1,1805 +1,5270 @@ -//! This module contains CPUID definitions for Intel CPUs. +//! This module contains CPUID definitions for Intel CPUs. use std::ops::RangeInclusive; -use super::{ValueDefinition, ValueDefinitions, CpuidDefinitions, CpuidReg, MigrationCompatibilityRequirement, Parameters, ProfilePolicy}; +use super::{ + CpuidDefinitions, CpuidReg, MigrationCompatibilityRequirement, Parameters, ProfilePolicy, + ValueDefinition, ValueDefinitions, +}; pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { - CpuidDefinitions([ - - // ========================================================================================= - // Basic CPUID Information - // ========================================================================================= - ( - Parameters{ leaf: 0x0, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "max_std_leaf", description: "Maximum Input value for Basic CPUID Information", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - ( - Parameters{ leaf: 0x0, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_vendorid_0", description: "CPU vendor ID string bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0x0, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_vendorid_2", description: "CPU vendor ID string bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq}, - ]) - ), - - ( - Parameters{ leaf: 0x0, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_vendorid_1", description: "CPU vendor ID string bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq}, - ]) - ), - - // TODO: Do we really want to inherit these values from the corresponding CPU, or should we zero it out or set something else here? - ( - Parameters{ leaf: 0x1, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "stepping", description: "Stepping ID", bits_range: (0, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "base_model", description: "Base CPU model ID", bits_range: (4, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "base_family_id", description: "Base CPU family ID", bits_range: (8, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "cpu_type", description: "CPU type", bits_range: (12, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "ext_model", description: "Extended CPU model ID", bits_range: (16, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "ext_family", description: "Extended CPU family ID", bits_range: (20, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x1, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "brand_id", description: "Brand index", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "clflush_size", description: "CLFLUSH instruction cache line size", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - // This is set by cloud hypervisor - ValueDefinition{ short: "n_logical_cpu", description: "Logical CPU count", bits_range: (16, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - // This is set by cloud hypervisor - ValueDefinition{ short: "local_apic_id", description: "Initial local APIC physical ID", bits_range: (24, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x1, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "sse3", description: "Streaming SIMD Extensions 3 (SSE3)", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pclmulqdq", description: "PCLMULQDQ instruction support", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "dtes64", description: "64-bit DS save area", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Perhaps there should be some CHV feature for opting in to enabling this for non-host CPU profiles? - ValueDefinition{ short: "monitor", description: "MONITOR/MWAIT support", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ds_cpl", description: "CPL Qualified Debug Store", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - // TODO: Ideally configurable by the user (host must have this otherwise CHV will not run) - ValueDefinition{ short: "vmx", description: "Virtual Machine Extensions", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(1), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "smx", description: "Safer Mode Extensions", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "est", description: "Enhanced Intel SpeedStep", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "tm2", description: "Thermal Monitor 2", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ssse3", description: "Supplemental SSE3", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "cnxt_id", description: "L1 Context ID", bits_range: (10, 10), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "sdbg", description: "Silicon Debug", bits_range: (11, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "fma", description: "FMA extensions using YMM state", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "cx16", description: "CMPXCHG16B instruction support", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "xtpr", description: "xTPR Update Control", bits_range: (14, 14), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "pdcm", description: "Perfmon and Debug Capability", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pcid", description: "Process-context identifiers", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "dca", description: "Direct Cache Access", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "sse4_1", description: "SSE4.1", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "sse4_2", description: "SSE4.2", bits_range: (20, 20), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Set by Cloud hypervisor - ValueDefinition{ short: "x2apic", description: "X2APIC support", bits_range: (21, 21), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "movbe", description: "MOVBE instruction support", bits_range: (22, 22), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "popcnt", description: "POPCNT instruction support", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Set by Cloud hypervisor - ValueDefinition{ short: "tsc_deadline_timer", description: "APIC timer one-shot operation", bits_range: (24, 24), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "aes", description: "AES instructions", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "xsave", description: "XSAVE (and related instructions) support", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Seems to no longer be supported by QEMU, but is by KVM? We disable this for now. - ValueDefinition{ short: "osxsave", description: "XSAVE (and related instructions) are enabled by OS", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx", description: "AVX instructions support", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "f16c", description: "Half-precision floating-point conversion support", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "rdrand", description: "RDRAND instruction support", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: If set by CHV set to 0 and write comment - ValueDefinition{ short: "guest_status", description: "System is running as guest; (para-)virtualized system", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x1, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "fpu", description: "Floating-Point Unit on-chip (x87)", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "vme", description: "Virtual-8086 Mode Extensions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "de", description: "Debugging Extensions", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pse", description: "Page Size Extension", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Does this also need special handling like TSC_DEADLINE_TIMER? - ValueDefinition{ short: "tsc", description: "Time Stamp Counter", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "msr", description: "Model-Specific Registers (RDMSR and WRMSR support)", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pae", description: "Physical Address Extensions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "mce", description: "Machine Check Exception", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "cx8", description: "CMPXCHG8B instruction", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "apic", description: "APIC on-chip", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related (maybe not necessary to look into which ones) - ValueDefinition{ short: "sep", description: "SYSENTER, SYSEXIT, and associated MSRs", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "mtrr", description: "Memory Type Range Registers", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pge", description: "Page Global Extensions", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "mca", description: "Machine Check Architecture", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "cmov", description: "Conditional Move Instruction", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pat", description: "Page Attribute Table", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pse36", description: "Page Size Extension (36-bit)", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "psn", description: "Processor Serial Number", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "clfsh", description: "CLFLUSH instruction", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ds", description: "Debug Store", bits_range: (21, 21), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "acpi", description: "Thermal monitor and clock control", bits_range: (22, 22), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "mmx", description: "MMX instructions", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "fxsr", description: "FXSAVE and FXRSTOR instructions", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "sse", description: "SSE instructions", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "sse2", description: "SSE2 instructions", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ss", description: "Self Snoop", bits_range: (27, 27), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "htt", description: "Hyper-threading", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "tm", description: "Thermal Monitor", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not really sure what the default should be for PBE. It seems like it is something that needs to be enabled via the IA32_MISC_ENABLE MSR hence perhaps this should be set via CPU features? - // MSR related - ValueDefinition{ short: "pbe", description: "Pending Break Enable", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // ========================================================================================= - // Cache and TLB Information - // ========================================================================================= - ( - Parameters{ leaf: 0x2, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "iteration_count", description: "Number of times this leaf must be queried", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc1", description: "Descriptor #1", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc2", description: "Descriptor #2", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc3", description: "Descriptor #3", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "eax_invalid", description: "Descriptors 1-3 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ]) - ), - - ( - Parameters{ leaf: 0x2, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "desc4", description: "Descriptor #4", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc5", description: "Descriptor #5", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc6", description: "Descriptor #6", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc7", description: "Descriptor #7", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "ebx_invalid", description: "Descriptors 4-7 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ]) - ), - - ( - Parameters{ leaf: 0x2, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "desc8", description: "Descriptor #8", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc9", description: "Descriptor #9", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc10", description: "Descriptor #10", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc11", description: "Descriptor #11", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "ecx_invalid", description: "Descriptors 8-11 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ]) - ), - - ( - Parameters{ leaf: 0x2, sub_leaf: RangeInclusive::new(0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "desc12", description: "Descriptor #12", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc13", description: "Descriptor #13", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc14", description: "Descriptor #14", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "desc15", description: "Descriptor #15", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ValueDefinition{ short: "edx_invalid", description: "Descriptors 12-15 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ]) - ), - // ========================================================================================= - // Deterministic Cache Parameters - // ========================================================================================= - ( - Parameters{ leaf: 0x4, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cache_type", description: "Cache type field", bits_range: (0, 4), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "cache_level", description: "Cache level (1-based)", bits_range: (5, 7), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - // TODO: Could there be a problem migrating from a CPU with self-initializing cache to one without? - ValueDefinition{ short: "cache_self_init", description: "Self-initializing cache level", bits_range: (8, 8), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "fully_associative", description: "Fully-associative cache", bits_range: (9, 9), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "num_threads_sharing", description: "Number logical CPUs sharing this cache", bits_range: (14, 25), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "num_cores_on_die", description: "Number of cores in the physical package", bits_range: (26, 31), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x4, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cache_linesize", description: "System coherency line size (0-based)", bits_range: (0, 11), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "cache_npartitions", description: "Physical line partitions (0-based)", bits_range: (12, 21), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "cache_nways", description: "Ways of associativity (0-based)", bits_range: (22, 31), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x4, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cache_nsets", description: "Cache number of sets (0-based)", bits_range: (0, 30), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x4, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "wbinvd_rll_no_guarantee", description: "WBINVD/INVD not guaranteed for Remote Lower-Level caches", bits_range: (0, 0), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "ll_inclusive", description: "Cache is inclusive of Lower-Level caches", bits_range: (1, 1), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "complex_indexing", description: "Not a direct-mapped cache (complex function)", bits_range: (2, 2), policy:ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // ========================================================================================= - // MONITOR/MWAIT - // ========================================================================================= - - ( - Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "min_mon_size", description: "Smallest monitor-line size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::LtEq }, - ]) - ), - - ( - Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "max_mon_size", description: "Largest monitor-line size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - ( - Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "mwait_ext", description: "Enumeration of MONITOR/MWAIT extensions is supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "mwait_irq_break", description: "Interrupts as a break-event for MWAIT is supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x5, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "n_c0_substates", description: "Number of C0 sub C-states supported using MWAIT", bits_range: (0, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c1_substates", description: "Number of C1 sub C-states supported using MWAIT", bits_range: (4, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c2_substates", description: "Number of C2 sub C-states supported using MWAIT", bits_range: (8, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c3_substates", description: "Number of C3 sub C-states supported using MWAIT", bits_range: (12, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c4_substates", description: "Number of C4 sub C-states supported using MWAIT", bits_range: (16, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c5_substates", description: "Number of C5 sub C-states supported using MWAIT", bits_range: (20, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c6_substates", description: "Number of C6 sub C-states supported using MWAIT", bits_range: (24, 27), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_c7_substates", description: "Number of C7 sub C-states supported using MWAIT", bits_range: (28, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // ========================================================================================= - // Thermal and Power Management - // ========================================================================================= - - ( - Parameters{ leaf: 0x6, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "dtherm", description: "Digital temperature sensor", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "turbo_boost", description: "Intel Turbo Boost", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "arat", description: "Always-Running APIC Timer (not affected by p-state)", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "pln", description: "Power Limit Notification (PLN) event", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ecmd", description: "Clock modulation duty cycle extension", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pts", description: "Package thermal management", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp", description: "HWP (Hardware P-states) base registers are supported", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp_notify", description: "HWP notification (IA32_HWP_INTERRUPT MSR)", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp_act_window", description: "HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported", bits_range: (9, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp_epp", description: "HWP Energy Performance Preference", bits_range: (10, 10), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp_pkg_req", description: "HWP Package Level Request", bits_range: (11, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hdc_base_regs", description: "HDC base registers are supported", bits_range: (13, 13), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "turbo_boost_3_0", description: "Intel Turbo Boost Max 3.0", bits_range: (14, 14), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp_capabilities", description: "HWP Highest Performance change", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp_peci_override", description: "HWP PECI override", bits_range: (16, 16), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp_flexible", description: "Flexible HWP", bits_range: (17, 17), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp_fast", description: "IA32_HWP_REQUEST MSR fast access mode", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hfi", description: "HW_FEEDBACK MSRs supported", bits_range: (19, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hwp_ignore_idle", description: "Ignoring idle logical CPU HWP req is supported", bits_range: (20, 20), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "thread_director", description: "Intel thread director support", bits_range: (23, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "therm_interrupt_bit25", description: "IA32_THERM_INTERRUPT MSR bit 25 is supported", bits_range: (24, 24), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x6, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - // TODO: Do we perhaps need some requirement for migration compatibility here? - ValueDefinition{ short: "n_therm_thresholds", description: "Digital thermometer thresholds", bits_range: (0, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x6, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - // MSR related - ValueDefinition{ short: "aperfmperf", description: "MPERF/APERF MSRs (effective frequency interface)", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "epb", description: "IA32_ENERGY_PERF_BIAS MSR support", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "thrd_director_nclasses", description: "Number of classes, Intel thread director", bits_range: (8, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x6, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "perfcap_reporting", description: "Performance capability reporting", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "encap_reporting", description: "Energy efficiency capability reporting", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "feedback_sz", description: "Feedback interface structure size, in 4K pages", bits_range: (8, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "this_lcpu_hwfdbk_idx", description: "This logical CPU hardware feedback interface index", bits_range: (16, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // =================================================================================================================== - // Structured Extended Feature Flags Enumeration Main Leaf - // =================================================================================================================== - - ( - Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "leaf7_n_subleaves", description: "Number of leaf 0x7 subleaves", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - ( - Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "fsgsbase", description: "FSBASE/GSBASE read/write support", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "tsc_adjust", description: "IA32_TSC_ADJUST MSR supported", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // SGX is deprecated so we disable it unconditionally for all CPU profiles - ValueDefinition{ short: "sgx", description: "Intel SGX (Software Guard Extensions)", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "bmi1", description: "Bit manipulation extensions group 1", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TSX related which is riddled with CVEs. Consider two profiles, or making it opt-in/out. QEMU always has a CPU model with and without TSX. - ValueDefinition{ short: "hle", description: "Hardware Lock Elision", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx2", description: "AVX2 instruction set", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - /*The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). - - Keep in mind however that in my limited understanding this isn't about enabling or disabling a feature, but it describes critical behaviour. - Hence I am wondering whether it should be a hard error if the host does not have this bit set, but the desired CPU profile does? - - TODO: Check what KVM_GET_SUPPORTED_CPUID actually gives here (on the Skylake server) - */ - ValueDefinition{ short: "fdp_excptn_only", description: "FPU Data Pointer updated only on x87 exceptions", bits_range: (6, 6), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "smep", description: "Supervisor Mode Execution Protection", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "bmi2", description: "Bit manipulation extensions group 2", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "erms", description: "Enhanced REP MOVSB/STOSB", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - /* - The instruction enabled by this seems rather powerful. Are we sure that doesn't have security implications? - I included this because it seems like QEMU does (to the best of my understanding). - */ - ValueDefinition{ short: "invpcid", description: "INVPCID instruction (Invalidate Processor Context ID)", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // This is TSX related from what I can tell. TSX is riddled with CVEs: Consider two profiles (one with it disabled) or an opt-in/out feature. - ValueDefinition{ short: "rtm", description: "Intel restricted transactional memory", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "rdt_m", description: "Supports Intel Resource Director Technology Monitoring Capability if 1", bits_range: (12, 12), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). TODO: Is it OK to just set this to 1? - ValueDefinition{ short: "zero_fcs_fds", description: "Deprecates FPU CS and FPU DS values if 1", bits_range: (13, 13), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // This has been deprecated - ValueDefinition{ short: "mpx", description: "Intel memory protection extensions", bits_range: (14, 14), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // This might be useful for certain high performance applications, but it also seems like a rather niche and advanced feature. QEMU does also not automatically enable this from what we can tell. - // TODO: Should we make this OPT-IN? - ValueDefinition{ short: "rdt_a", description: "Intel RDT-A. Supports Intel Resource Director Technology Allocation Capability if 1", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Do the wider avx512 zmm registers work out of the box when the hardware supports it? - ValueDefinition{ short: "avx512f", description: "AVX-512 foundation instructions", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512dq", description: "AVX-512 double/quadword instructions", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "rdseed", description: "RDSEED instruction", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "adx", description: "ADCX/ADOX instructions", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "smap", description: "Supervisor mode access prevention", bits_range: (20, 20), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512ifma", description: "AVX-512 integer fused multiply add", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "clflushopt", description: "CLFLUSHOPT instruction", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "clwb", description: "CLWB instruction", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "intel_pt", description: "Intel processor trace", bits_range: (25, 25), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512pf", description: "AVX-512 prefetch instructions", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512er", description: "AVX-512 exponent/reciprocal instructions", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512cd", description: "AVX-512 conflict detection instructions", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "sha_ni", description: "SHA/SHA256 instructions", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512bw", description: "AVX-512 byte/word instructions", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512vl", description: "AVX-512 VL (128/256 vector length) extensions", bits_range: (31, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "prefetchwt1", description: "PREFETCHWT1 (Intel Xeon Phi only)", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512vbmi", description: "AVX-512 Vector byte manipulation instructions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - // Also set by QEMU for CPU models from what we can tell - ValueDefinition{ short: "umip", description: "User mode instruction protection", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - // Also set by QEMU for CPU models from what we can tell - ValueDefinition{ short: "pku", description: "Protection keys for user-space", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ospke", description: "OS protection keys enable", bits_range: (4, 4), policy: ProfilePolicy::Inherit , migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: QEMU seems to set this unconditionally whenever KVM supports it (TODO: Would it be best to set this unconditionally?) - ValueDefinition{ short: "waitpkg", description: "WAITPKG instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "avx512_vbmi2", description: "AVX-512 vector byte manipulation instructions group 2", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: This may be useful for nested virtualization? Perhaps it should be opt-in rather than unconditionally disabled? - ValueDefinition{ short: "cet_ss", description: "CET shadow stack features", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "gfni", description: "Galois field new instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "vaes", description: "Vector AES instructions", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "vpclmulqdq", description: "VPCLMULQDQ 256-bit instruction support", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512_vnni", description: "Vector neural network instructions", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512_bitalg", description: "AVX-512 bitwise algorithms", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Seems to be TDX related which is experimental in CHV. We disable this for CPU profiles for now, but could potentially add it as an opt-in feature eventually. - ValueDefinition{ short: "tme", description: "Intel total memory encryption", bits_range: (13, 13), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - - ValueDefinition{ short: "avx512_vpopcntdq", description: "AVX-512: POPCNT for vectors of DWORD/QWORD", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "la57", description: "57-bit linear addresses (five-level paging)", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "mawau_val_lm", description: "BNDLDX/BNDSTX MAWAU value in 64-bit mode", bits_range: (17, 21), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - // MSR related - ValueDefinition{ short: "rdpid", description: "RDPID instruction", bits_range: (22, 22), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - // We leave key locker support out for CPU profiles for the time being. We may want this to be opt-in in the future though - ValueDefinition{ short: "key_locker", description: "Intel key locker support", bits_range: (23, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "bus_lock_detect", description: "OS bus-lock detection", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "cldemote", description: "CLDEMOTE instruction", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "movdiri", description: "MOVDIRI instruction", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "movdir64b", description: "MOVDIR64B instruction", bits_range: (28, 28), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "enqcmd", description: "Enqueue stores supported (ENQCMD{,S})", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // SGX support is deprecated so we disable it unconditionally for CPU profiles - ValueDefinition{ short: "sgx_lc", description: "Intel SGX launch configuration", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "pks", description: "Protection keys for supervisor-mode pages", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - // SGX is deprecated - ValueDefinition{ short: "sgx_keys", description: "Intel SGX attestation services", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512_4vnniw", description: "AVX-512 neural network instructions (Intel Xeon Phi only?)", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512_4fmaps", description: "AVX-512 multiply accumulation single precision (Intel Xeon Phi only?)", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "fsrm", description: "Fast short REP MOV", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "uintr", description: "CPU supports user interrupts", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512_vp2intersect", description: "VP2INTERSECT{D,Q} instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ - short: "srdbs_ctrl", - description: "SRBDS mitigation MSR available: If 1, enumerates support for the IA32_MCU_OPT_CTRL MSR and indicates that its bit 0 (RNGDS_MITG_DIS) is also supported.", - bits_range: (9, 9), - policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits - }, - - ValueDefinition{ short: "md_clear", description: "VERW MD_CLEAR microcode support", bits_range: (10, 10), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "rtm_always_abort", description: "XBEGIN (RTM transaction) always aborts", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "tsx_force_abort", description: "MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "serialize", description: "SERIALIZE instruction", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "hybrid_cpu", description: "The CPU is identified as a 'hybrid part'", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: This is TSX related which is riddled with CVEs. We should carefully decide what to do with regards to this feature. - ValueDefinition{ short: "tsxldtrk", description: "TSX suspend/resume load address tracking", bits_range: (16, 16), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // Might be relevant for confidential computing - ValueDefinition{ short: "pconfig", description: "PCONFIG instruction", bits_range: (18, 18), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "arch_lbr", description: "Intel architectural LBRs", bits_range: (19, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure if this is the best default, but QEMU also seems to disable this for CPU models - ValueDefinition{ short: "ibt", description: "CET indirect branch tracking", bits_range: (20, 20), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_bf16", description: "AMX-BF16: tile bfloat16 support", bits_range: (22, 22), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512_fp16", description: "AVX-512 FP16 instructions", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_tile", description: "AMX-TILE: tile architecture support", bits_range: (24, 24), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "amx_int8", description: "AMX-INT8: tile 8-bit integer support", bits_range: (25, 25), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "spec_ctrl", description: "Speculation Control (IBRS/IBPB: indirect branch restrictions)", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "intel_stibp", description: "Single thread indirect branch predictors", bits_range: (27, 27), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "flush_l1d", description: "FLUSH L1D cache: IA32_FLUSH_CMD MSR", bits_range: (28, 28), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "arch_capabilities", description: "Intel IA32_ARCH_CAPABILITIES MSR", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "core_capabilities", description: "IA32_CORE_CAPABILITIES MSR", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "spec_ctrl_ssbd", description: "Speculative store bypass disable", bits_range: (31, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Structured Extended Feature Flags Enumeration Sub-Leaf 1 - // =================================================================================================================== - ( - Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "sha512", description: "SHA-512 extensions", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "sm3", description: "SM3 instructions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "sm4", description: "SM4 instructions", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // RAO-INT is deprecated and removed from most compilers as far as we are aware - ValueDefinition{ short: "RAO-INT", description: "RAO-INT instructions", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx_vnni", description: "AVX-VNNI instructions", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx512_bf16", description: "AVX-512 bfloat16 instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - /* - Not set in QEMU from what we can tell, but according seems to be fine to expose this to guests - if we understood https://www.phoronix.com/news/Intel-Linux-LASS-KVM correctly. It is also - our understanding that this feature can enable guests opting in to more security (possibly at the cost of some performance). - */ - ValueDefinition{ short: "lass", description: "Linear address space separation", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "cmpccxadd", description: "CMPccXADD instructions", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "arch_perfmon_ext", description: "ArchPerfmonExt: leaf 0x23 is supported", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "fzrm", description: "Fast zero-length REP MOVSB", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "fsrs", description: "Fast short REP STOSB", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "fsrc", description: "Fast Short REP CMPSB/SCASB", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "fred", description: "FRED: Flexible return and event delivery transitions", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "lkgs", description: "LKGS: Load 'kernel' (userspace) GS", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "wrmsrns", description: "WRMSRNS instruction (WRMSR-non-serializing)", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "nmi_src", description: "NMI-source reporting with FRED event data", bits_range: (20, 20), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "amx_fp16", description: "AMX-FP16: FP16 tile operations", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "hreset", description: "History reset support", bits_range: (22, 22), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx_ifma", description: "Integer fused multiply add", bits_range: (23, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "lam", description: "Linear address masking", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "rd_wr_msrlist", description: "RDMSRLIST/WRMSRLIST instructions", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "invd_disable_post_bios_done", description: "If 1, supports INVD execution prevention after BIOS Done", bits_range: (30, 30), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "movrs", description: "MOVRS", bits_range: (31, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - - ValueDefinition{ short: "intel_ppin", description: "Protected processor inventory number (PPIN{,_CTL} MSRs)", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - // MSR related - ValueDefinition{ short: "pbndkb", description: "PBNDKB instruction supported and enumerates the existence of the IA32_TSE_CAPABILITY MSR", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // TODO: Missing entry for (0x7, 1, ECX) - // Make the whole register zero though - // - ( - Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "avx_vnni_int8", description: "AVX-VNNI-INT8 instructions", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx_ne_convert", description: "AVX-NE-CONVERT instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the value will be zeroed out if the user has not opted in for "amx" via CpuFeatures. - ValueDefinition{ short: "amx_complex", description: "AMX-COMPLEX instructions (starting from Granite Rapids)", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "avx_vnni_int16", description: "AVX-VNNI-INT16 instructions", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "utmr", description: "If 1, supports user-timer events", bits_range: (13, 13), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "prefetchit_0_1", description: "PREFETCHIT0/1 instructions", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - // MSR related - ValueDefinition{ short: "user_msr", description: "If 1, supports the URDMSR and UWRMSR instructions", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - - ValueDefinition{ short: "uiret_uif", description: "If 1, UIRET sets UIF to the value of bit 1 of the RFLAGS image loaded from the stack", bits_range: (15, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - - ValueDefinition{ short: "cet_sss", description: "CET supervisor shadow stacks safe to use", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "avx10", description: "If 1, supports the Intel AVX10 instructions and indicates the presence of leaf 0x24", bits_range: (19, 19), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "apx_f", description: "If 1, the processor provides foundational support for Intel Advanced Performance Extensions", bits_range: (21, 21), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "mwait", description: "If 1, MWAIT is supported even if (0x1 ECX bit 3 (monitor) is enumerated as 0)", bits_range: (23, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "slsm", description: "If 1, indicates bit 0 of the IA32_INTEGRITY_STATUS MSR is supported. Bit 0 of this MSR indicates whether static lockstep is active on this logical processor", bits_range: (24, 24), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Structured Extended Feature Flags Enumeration Sub-Leaf 2 - // =================================================================================================================== - ( - Parameters{ leaf: 0x7, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - // MSR related - ValueDefinition{ short: "intel_psfd", description: "If 1, indicates bit 7 of the IA32_SPEC_CTRL_MSR is supported. Bit 7 of this MSR disables fast store forwarding predictor without disabling speculative store bypass", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "ipred_ctrl", description: "MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "rrsba_ctrl", description: "MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "ddp_ctrl", description: "MSR bit IA32_SPEC_CTRL.DDPD_U", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "bhi_ctrl", description: "MSR bit IA32_SPEC_CTRL.BHI_DIS_S", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "mcdt_no", description: "MCDT mitigation not needed", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "uclock_disable", description: "UC-lock disable is supported", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ]) - ), - - // =================================================================================================================== - // Direct Cache Access Information - // =================================================================================================================== - ( - Parameters{ leaf: 0x9, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - // MSR related - ValueDefinition{ short: "dca_cap_msr_value", description: "Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1f8H)", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ]) - ), - - // =================================================================================================================== - // Architectural Performance Monitoring - // =================================================================================================================== - // We will just zero out everything to do with PMU for CPU profiles and require equality for migration to be considered compatible (for the time being). - // TODO: Left for another day - ( - Parameters{ leaf: 0xa, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pmu_version", description: "Performance monitoring unit version ID", bits_range: (0, 7), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "pmu_n_gcounters", description: "Number of general PMU counters per logical CPU", bits_range: (8, 15), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "pmu_gcounters_nbits", description: "Bitwidth of PMU general counters", bits_range: (16, 23), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "pmu_cpuid_ebx_bits", description: "Length of leaf 0xa EBX bit vector", bits_range: (24, 31), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0xa, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "no_core_cycle_evt", description: "Core cycle event not available", bits_range: (0, 0), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "no_insn_retired_evt", description: "Instruction retired event not available", bits_range: (1, 1), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "no_refcycle_evt", description: "Reference cycles event not available", bits_range: (2, 2), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "no_llc_ref_evt", description: "LLC-reference event not available", bits_range: (3, 3), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "no_llc_miss_evt", description: "LLC-misses event not available", bits_range: (4, 4), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "no_br_insn_ret_evt", description: "Branch instruction retired event not available", bits_range: (5, 5), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "no_br_mispredict_evt", description: "Branch mispredict retired event not available", bits_range: (6, 6), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "no_td_slots_evt", description: "Topdown slots event not available", bits_range: (7, 7), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0xa, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pmu_fcounters_bitmap", description: "Fixed-function PMU counters support bitmap", bits_range: (0, 31), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0xa, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pmu_n_fcounters", description: "Number of fixed PMU counters", bits_range: (0, 4), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "pmu_fcounters_nbits", description: "Bitwidth of PMU fixed counters", bits_range: (5, 12), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "anythread_depr", description: "AnyThread deprecation", bits_range: (15, 15), policy:ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - // =================================================================================================================== - // Extended Topology Enumeration - // =================================================================================================================== - - // Leaf 0xB must be set by CHV itself (and do all necessary checks) hence we can ignore checking for migration compatibility here - // TODO: Set by cloud hypervisor. Set this to 0 with a comment that CHV will set it instead. - ( - Parameters{ leaf: 0xb, sub_leaf:RangeInclusive::new( 0, u32::MAX), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "x2apic_id_shift", description: "Bit width of this level (previous levels inclusive)", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // Set by VMM/user provided config - ( - Parameters{ leaf: 0xb, sub_leaf:RangeInclusive::new( 0, u32::MAX), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "domain_lcpus_count", description: "Logical CPUs count across all instances of this domain", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // Set by VMM/user provided config - ( - Parameters{ leaf: 0xb, sub_leaf:RangeInclusive::new( 0, u32::MAX), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "domain_nr", description: "This domain level (subleaf ID)", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "domain_type", description: "This domain type", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // Set by VMM/user provided config - ( - Parameters{ leaf: 0xb, sub_leaf:RangeInclusive::new( 0, u32::MAX), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "x2apic_id", description: "x2APIC ID of current logical CPU", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // =================================================================================================================== - // Processor Extended State Enumeration Main Leaf - // =================================================================================================================== - // TODO: Figure out properly when to use Inherit vs Passthrough - // TODO: Check that CHV checks for migration compatibility here - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "xcr0_x87", description: "XCR0.X87 (bit 0) supported", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "xcr0_sse", description: "XCR0.SEE (bit 1) supported", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "xcr0_avx", description: "XCR0.AVX (bit 2) supported", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MPX is deprecated - ValueDefinition{ short: "xcr0_mpx_bndregs", description: "XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MPX is deprecated - ValueDefinition{ short: "xcr0_mpx_bndcsr", description: "XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "xcr0_avx512_opmask", description: "XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "xcr0_avx512_zmm_hi256", description: "XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "xcr0_avx512_hi16_zmm", description: "XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // MSR related - ValueDefinition{ short: "xcr0_ia32_xss", description: "XCR0.IA32_XSS (bit 8) used for IA32_XSS", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "xcr0_pkru", description: "XCR0.PKRU (bit 9) supported (XSAVE PKRU registers)", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - ValueDefinition{ short: "xcr0_ia32_xss_bits", description: "XCR0.IA32_XSS (bit 10 - 16) used for IA32_XSS", bits_range: (10, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. - ValueDefinition{ short: "xcr0_tileconfig", description: "XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)", bits_range: (17, 17), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. - ValueDefinition{ short: "xcr0_tiledata", description: "XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA)", bits_range: (18, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - // TODO: Check if CHV checks 0xd for migration compatibility already - ValueDefinition{ short: "xsave_sz_xcr0_enabled", description: "XSAVE/XRSTOR area byte size, for XCR0 enabled features", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - // We don't need migration compatibility requirements here since we check for each individual state component - ValueDefinition{ short: "xsave_sz_max", description: "XSAVE/XRSTOR area max byte size, all CPU features", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "xcr0_upper_bits", description: "Reports the valid bit fields of the upper 32 bits of the XCR0 register", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - // =================================================================================================================== - // Processor Extended State Enumeration Sub-leaf 1 - // =================================================================================================================== - - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "xsaveopt", description: "XSAVEOPT instruction", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "xsavec", description: "XSAVEC instruction", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "xgetbv1", description: "XGETBV instruction with ECX = 1", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Can this have security implications in terms of supervisor state getting exposed? - ValueDefinition{ short: "xsaves", description: "XSAVES/XRSTORS instructions (and XSS MSR)", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - - // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bitssthat userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. - ValueDefinition{ short: "xfd", description: "Extended feature disable support", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - /*NOTE: This will depend on which CPU features (in CHV) are enabled and pre-computation can potentially lead to a combinatorial explosion. Luckily we can deal with each component (and its size) separately, hence we can just passthrough whatever we get from the host here.*/ - ValueDefinition{ short: "xsave_sz_xcr0_xmms_enabled", description: "XSAVE area size, all XCR0 and IA32_XSS features enabled", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::ECX }, - /* Reports the supported bits of the lower IA32_XSS MSR. IA32_XSS[n] can be set to 1 only if ECX[n] = 1*/ - ValueDefinitions::new(&[ - // TODO: Not sure what profile policy to set here - ValueDefinition{ short: "xcr0_7bits", description: "Used for XCR0", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - // TODO: Not sure about the profile pilicy here - ValueDefinition{ short: "xss_pt", description: "PT state, supported", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure what profile policy to set here - ValueDefinition{ short: "xcr0_bit9", description: "Used for XCR0", bits_range: (9, 9), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about the profile pilicy here - ValueDefinition{ short: "xss_pasid", description: "PASID state, supported", bits_range: (10, 10), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about the profile pilicy here - ValueDefinition{ short: "xss_cet_u", description: "CET user state, supported", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about the profile pilicy here - ValueDefinition{ short: "xss_cet_p", description: "CET supervisor state, supported", bits_range: (12, 12), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about the profile pilicy here - ValueDefinition{ short: "xss_hdc", description: "HDC state, supported", bits_range: (13, 13), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about the profile pilicy here - ValueDefinition{ short: "xss_uintr", description: "UINTR state, supported", bits_range: (14, 14), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about the profile pilicy here - ValueDefinition{ short: "xss_lbr", description: "LBR state, supported", bits_range: (15, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure about the profile pilicy here - ValueDefinition{ short: "xss_hwp", description: "HWP state, supported", bits_range: (16, 16), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Not sure what profile policy to set here - ValueDefinition{ short: "xcr0_bits", description: "Used for XCR0", bits_range: (17, 18), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EDX }, - /* Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32 ] can be set to 1 only if EDX[n] = 1*/ - ValueDefinitions::new(&[ - // TODO: Not sure what profile policy to set here - ValueDefinition{ short: "ia32_xss_upper", description: " Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32 ] can be set to 1 only if EDX[n] = 1", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Processor Extended State Enumeration Sub-leaves - // =================================================================================================================== - - /* LEAF 0xd sub-leaf n >=2 : - If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 ≤ n ≤ 31) is - invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 ≤ n ≤ 63) - is invalid if sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32]. - - */ - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 2, 63), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "xsave_sz", description: "Size of save area for subleaf-N feature, in bytes", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 2, 63), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "xsave_offset", description: "Offset of save area for subleaf-N feature, in bytes", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0xd, sub_leaf:RangeInclusive::new( 2, 63), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "is_xss_bit", description: "Subleaf N describes an XSS bit, otherwise XCR0 bit", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "compacted_xsave_64byte_aligned", description: "When compacted, subleaf-N feature XSAVE area is 64-byte aligned", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - // TODO: This may depend on the "amx" feature? - ValueDefinition{ short: "xfd_faulting", description: "Indicates support for xfd faulting", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - // =================================================================================================================== - // Intel Resource Director Technology Monitoring Enumeration - // =================================================================================================================== - - ( - Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "core_rmid_max", description: "RMID max, within this core, all types (0-based)", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - ( - Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - // TODO: Not sure about the short name (generated by the x86-cpuid.org tool). What is cqm_llc? - ValueDefinition{ short: "cqm_llc", description: "Supports L3 Cache Intel RDT Monitoring if 1", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ]) - ), - - // =================================================================================================================== - // Intel Resource Director Technology Monitoring Enumeration Sub-leaf 1 - // =================================================================================================================== - ( - Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, - // TODO: Not sure about the migration policy - ValueDefinitions::new(&[ - ValueDefinition{ short: "l3c_qm_bitwidth", description: "L3 QoS-monitoring counter bitwidth (24-based)", bits_range: (0, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "l3c_qm_overflow_bit", description: "QM_CTR MSR bit 61 is an overflow bit", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "l3c_qm_non_cpu_agent", description: "If 1, indicates the presence of non-CPU agent Intel RDT CTM support", bits_range: (9, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "l3c_qm_non_cpu_agent", description: "If 1, indicates the presence of non-CPU agent Intel RDT MBM support", bits_range: (10, 10), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, - // TODO: Not sure about the migration policy - ValueDefinitions::new(&[ - ValueDefinition{ short: "l3c_qm_conver_factor", description: "QM_CTR MSR conversion factor to bytes", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::ECX }, - // TODO: Not sure about the migration policy - ValueDefinitions::new(&[ - ValueDefinition{ short: "l3c_qm_rmid_max", description: "L3 QoS-monitoring max RMID", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - ( - Parameters{ leaf: 0xf, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cqm_occup_llc", description: "L3 QoS occupancy monitoring supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "cqm_mbm_total", description: "L3 QoS total bandwidth monitoring supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "cqm_mbm_local", description: "L3 QoS local bandwidth monitoring supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Intel Resource Director Technology Allocation Enumeration - // =================================================================================================================== - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - //TODO: These features may be good for increased performance. Perhaps there needs to be some mechanism to opt-in for non-host CPU profiles? - ValueDefinitions::new(&[ - ValueDefinition{ short: "cat_l3", description: "L3 Cache Allocation Technology supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "cat_l2", description: "L2 Cache Allocation Technology supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "mba", description: "Memory Bandwidth Allocation supported", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - // =================================================================================================================== - // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 1) - // =================================================================================================================== - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cat_cbm_len", description: "L3_CAT capacity bitmask length, minus-one notation", bits_range: (0, 4), policy:ProfilePolicy::Passthrough /* TODO: ? */, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore /* TODO: ? */ }, - ]) - ), - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cat_units_bitmap", description: "L3_CAT bitmap of allocation units", bits_range: (0, 31), policy:ProfilePolicy::Passthrough /* TODO: ? */, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore /* TODO: ? */}, - ]) - ), - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::ECX }, - //TODO: These feature may be good for increased performance. Perhaps there needs to be some mechanism to opt-in for non-host CPU profiles? - ValueDefinitions::new(&[ - ValueDefinition{ short: "l3_cat_non_cpu_agents", description: "L3_CAT for non-CPU agent is supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "cdp_l3", description: "L3/L2_CAT CDP (Code and Data Prioritization)", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "cat_sparse_1s", description: "L3/L2_CAT non-contiguous 1s value supported", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EDX }, - // TODO: We might need some way to opt in to use Intel cache allocation technology in guests with non-host CPU profiles. - ValueDefinitions::new(&[ - ValueDefinition {short: "cat_cos_max", description: "Highest COS number supported for this ResID", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq } - ]) - ), - - // =================================================================================================================== - // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 2) - // =================================================================================================================== - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cat_cbm_len", description: "L2_CAT capacity bitmask length, minus-one notation", bits_range: (0, 4), policy:ProfilePolicy::Passthrough /* TODO: ? */, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore /* TODO: ? */ }, - ]) - ), - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cat_units_bitmap", description: "L2_CAT bitmap of allocation units", bits_range: (0, 31), policy:ProfilePolicy::Passthrough /* TODO: ? */, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore /* TODO: ? */}, - ]) - ), - - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition {short: "cat_cos_max", description: "Highest COS number supported for this ResID", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq } - ]) - ), - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::ECX }, - // TODO: We might need some way to opt in to use Intel cache allocation technology in guests with non-host CPU profiles. - ValueDefinitions::new(&[ - ValueDefinition{ short: "cdp_l2", description: "L2_CAT CDP (Code and Data Prioritization)", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "cat_sparse_1s", description: "L2_CAT non-contiguous 1s value supported", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 3) - // =================================================================================================================== - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 3, 3), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - // TODO: We might need some way to opt in to use Intel MBA technology in guests with non-host CPU profiles. - ValueDefinition{ short: "mba_max_delay", description: "Max MBA throttling value; minus-one notation", bits_range: (0, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 3, 3), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "per_thread_mba", description: "Per-thread MBA controls are supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "mba_delay_linear", description: "Delay values are linear", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 3, 3), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "mba_cos_max", description: "MBA max Class of Service supported", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - // =================================================================================================================== - // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 5) - // =================================================================================================================== - // - // TODO: We may want to have some way to opt-in to use Intel RDT for guests with non-host CPU profiles. - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "core_max_throttle", description: "Max Core throttling level supported by the corresponding ResID", bits_range: (0, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - // TODO: Not sure about the short name - ValueDefinition{ short: "core_scope", description: "If 1, indicates the logical processor scope of the IA32_QoS_Core_BW_Thrtl_n MSRs. Other values are reserved", bits_range: (8, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cba_delay_linear", description: "The response of the bandwidth control is approximately linear", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0x10, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "core_cos_max", description: "Core max Class of Service supported", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - // SGX is already disabled and deprecated so we don't need to worry about leaf 0x12 and its subleaves - - // =================================================================================================================== - // Intel Processor Trace Enumeration Main Leaf - // =================================================================================================================== - - ( - Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pt_max_subleaf", description: "Maximum leaf 0x14 subleaf", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - ( - Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cr3_filtering", description: "IA32_RTIT_CR3_MATCH is accessible", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "psb_cyc", description: "Configurable PSB and cycle-accurate mode", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ip_filtering", description: "IP/TraceStop filtering; Warm-reset PT MSRs preservation", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "mtc_timing", description: "MTC timing packet; COFI-based packets suppression", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "ptwrite", description: "PTWRITE support", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "power_event_trace", description: "Power Event Trace support", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "psb_pmi_preserve", description: "PSB and PMI preservation support", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "event_trace", description: "Event Trace packet generation through IA32_RTIT_CTL.EventEn", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "tnt_disable", description: "TNT packet generation disable through IA32_RTIT_CTL.DisTNT", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "topa_output", description: "ToPA output scheme support", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "topa_multiple_entries", description: "ToPA tables can hold multiple entries", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "single_range_output", description: "Single-range output scheme supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "trance_transport_output", description: "Trace Transport subsystem output support", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ip_payloads_lip", description: "IP payloads have LIP values (CS base included)", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Intel Processor Trace Enumeration Sub-leaf 1 - // =================================================================================================================== - - ( - Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "num_address_ranges", description: "Filtering number of configurable Address Ranges", bits_range: (0, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "mtc_periods_bmp", description: "Bitmap of supported MTC period encodings", bits_range: (16, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x14, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cycle_thresholds_bmp", description: "Bitmap of supported Cycle Threshold encodings", bits_range: (0, 15), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "psb_periods_bmp", description: "Bitmap of supported Configurable PSB frequency encodings", bits_range: (16, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Time Stamp Counter and Core Crystal Clock Information - // =================================================================================================================== - - // TODO: Apparently these clock frequencies can be set by KVM. Would it perhaps make sense to set them to the same as the physical CPU the profile corresponds to? Or is it best to just pass through whatever we get from the host here? - ( - Parameters{ leaf: 0x15, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "tsc_denominator", description: "Denominator of the TSC/'core crystal clock' ratio", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ]) - ), - - ( - Parameters{ leaf: 0x15, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "tsc_numerator", description: "Numerator of the TSC/'core crystal clock' ratio", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x15, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_crystal_hz", description: "Core crystal clock nominal frequency, in Hz", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ]) - ), - - // =================================================================================================================== - // Processor Frequency Information - // =================================================================================================================== - - ( - Parameters{ leaf: 0x16, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_base_mhz", description: "Processor base frequency, in MHz", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x16, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_max_mhz", description: "Processor max frequency, in MHz", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x16, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "bus_mhz", description: "Bus reference frequency, in MHz", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // =================================================================================================================== - // System-On-Chip Vendor Attribute Enumeration Main Leaf - // =================================================================================================================== - - // System-On-Chip should probably not be supported for CPU profiles for the foreseeable feature. - ( - Parameters{ leaf: 0x17, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "soc_max_subleaf", description: "Maximum leaf 0x17 subleaf", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - // =================================================================================================================== - // Deterministic Address Translation Parameters - // =================================================================================================================== - - // TODO: Check that we can indeed ignore migration compatibility checks for this leaf - ( - Parameters{ leaf: 0x18, sub_leaf: RangeInclusive::new(0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "tlb_max_subleaf", description: "Maximum leaf 0x18 subleaf", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x18, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "tlb_4k_page", description: "TLB 4KB-page entries supported", bits_range: (0, 0), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "tlb_2m_page", description: "TLB 2MB-page entries supported", bits_range: (1, 1), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "tlb_4m_page", description: "TLB 4MB-page entries supported", bits_range: (2, 2), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "tlb_1g_page", description: "TLB 1GB-page entries supported", bits_range: (3, 3), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "hard_partitioning", description: "(Hard/Soft) partitioning between logical CPUs sharing this structure", bits_range: (8, 10), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "n_way_associative", description: "Ways of associativity", bits_range: (16, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x18, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "n_sets", description: "Number of sets", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x18, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "tlb_type", description: "Translation cache type (TLB type)", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "tlb_cache_level", description: "Translation cache level (1-based)", bits_range: (5, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "is_fully_associative", description: "Fully-associative structure", bits_range: (8, 8), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "tlb_max_addressible_ids", description: "Max number of addressable IDs for logical CPUs sharing this TLB - 1", bits_range: (14, 25), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // We don't support key locker for now (leaf 0x19): Hence we zero out leaf 0x19 for CPU profiles (and don't check it for migration compatibility) - // We zero LEAF 0x1A (Native Model ID Enumeration) out for CPU profiles (and don't check it for migration compatibility) - // LEAF 0x1B (PCONFIG) is zeroed out for CPU profiles for now (and we don't check it for migration compatibility) - - // =================================================================================================================== - // Last Branch Records Information - // =================================================================================================================== - - ( - Parameters{ leaf: 0x1c, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "lbr_depth_8", description: "Max stack depth (number of LBR entries) = 8", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_depth_16", description: "Max stack depth (number of LBR entries) = 16", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_depth_24", description: "Max stack depth (number of LBR entries) = 24", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_depth_32", description: "Max stack depth (number of LBR entries) = 32", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_depth_40", description: "Max stack depth (number of LBR entries) = 40", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_depth_48", description: "Max stack depth (number of LBR entries) = 48", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_depth_56", description: "Max stack depth (number of LBR entries) = 56", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_depth_64", description: "Max stack depth (number of LBR entries) = 64", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_deep_c_reset", description: "LBRs maybe cleared on MWAIT C-state > C1", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_ip_is_lip", description: "LBR IP contain Last IP, otherwise effective IP", bits_range: (31, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ]) - ), - - ( - Parameters{ leaf: 0x1c, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "lbr_cpl", description: "CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_branch_filter", description: "Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_call_stack", description: "Call-stack mode (IA32_LBR_CTL[3] = 1) supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ]) - ), - - ( - Parameters{ leaf: 0x1c, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "lbr_mispredict", description: "Branch misprediction bit supported (IA32_LBR_x_INFO[63])", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "lbr_timed_lbr", description: "Timed LBRs (CPU cycles since last LBR entry) supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_branch_type", description: "Branch type field (IA32_LBR_INFO_x[59:56]) supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ValueDefinition{ short: "lbr_events_gpc_bmp", description: "LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters", bits_range: (16, 19), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ]) - ), - - // =================================================================================================================== - // Tile Information Main Leaf - // =================================================================================================================== - // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. - ( - Parameters{ leaf: 0x1d, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "amx_max_palette", description: "Highest palette ID / subleaf ID", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq}, - ]) - ), - - // =================================================================================================================== - // Tile Palette 1 Sub-leaf - // =================================================================================================================== - // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. - ( - Parameters{ leaf: 0x1d, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "amx_palette_size", description: "AMX palette total tiles size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq /* require equality as this can impact XSAVE */ }, - ValueDefinition{ short: "amx_tile_size", description: "AMX single tile's size, in bytes", bits_range: (16, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0x1d, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "amx_tile_row_size", description: "AMX tile single row's size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "amx_palette_nr_tiles", description: "AMX palette number of tiles", bits_range: (16, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq /* Can affect XSAVE hence require equality here */}, - ]) - ), - - ( - Parameters{ leaf: 0x1d, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "amx_tile_nr_rows", description: "AMX tile max number of rows", bits_range: (0, 15), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - // =================================================================================================================== - // TMUL Information Main Leaf - // =================================================================================================================== - // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. - ( - Parameters{ leaf: 0x1e, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition {short: "tmul_info_max", description: "Reports the maximum number of sub-leaves that are supported in leaf 0x1e", bits_range: (0,31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq} - ]) - ), - - ( - Parameters{ leaf: 0x1e, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "tmul_maxk", description: "TMUL unit maximum height, K (rows or columns)", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq /* TODO: OR should we go with Eq? */ }, - ValueDefinition{ short: "tmul_maxn", description: "TMUL unit maximum SIMD dimension, N (column bytes)", bits_range: (8, 23), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq /* TODO: Or should we go with Eq? */ }, - ]) - ), - - // =================================================================================================================== - // TMUL Information Sub-leaf 1 - // =================================================================================================================== - // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. - ( - Parameters{ leaf: 0x1e, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, - // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. - ValueDefinitions::new(&[ - ValueDefinition{ short: "amx_int8", description: "If 1, the processor supports tile computational operations on 8-bit integers", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_bf16", description: "If 1, the processor supports tile computational operations on bfloat16 numbers", bits_range: (1, 1), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_complex", description: "If 1, the processor supports the AMX-COMPLEX instructions", bits_range: (2, 2), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_fp16", description: "If 1, the processor supports tile computational operations on FP16 numbers", bits_range: (3, 3), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_fp8", description: "If 1, the processor supports tile computational operations on FP8 numbers", bits_range: (4, 4), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_transpose", description: "If 1, the processor supports the AMX-TRANSPOSE instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_tf32", description: "If 1, the processor supports the AMX-TF32 (FP19) instructions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_avx512", description: "If 1, the processor supports the AMX-AVX512 instructions", bits_range: (7, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "amx_movrs", description: "If 1, the processor supports the AMX-MOVRS instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // V2 Extended Topology Enumeration - // =================================================================================================================== - - // We can ignore checking migration compatibility for the 0x1f leaf because these values must be set by CHV itself which should do all relevant checks - ( - Parameters{ leaf: 0x1f, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "x2apic_id_shift", description: "Bit width of this level (previous levels inclusive)", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x1f, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "domain_lcpus_count", description: "Logical CPUs count across all instances of this domain", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x1f, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "domain_level", description: "This domain level (subleaf ID)", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "domain_type", description: "This domain type", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x1f, sub_leaf: RangeInclusive::new(0, u32::MAX), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "x2apic_id", description: "x2APIC ID of current logical CPU", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - // =================================================================================================================== - // Processor History Reset - // =================================================================================================================== - ( - Parameters{ leaf: 0x20, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "hreset_nr_subleaves", description: "CPUID 0x20 max subleaf + 1", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - ( - Parameters{ leaf: 0x20, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "hreset_thread_director", description: "HRESET of Intel thread director is supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // TDX - // =================================================================================================================== - - // TDX is not supported by CPU profiles for now. We just zero out this leaf for CPU profiles for the time being. - ( - Parameters{ leaf: 0x21, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "tdx_vendorid_0", description: "TDX vendor ID string bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0x21, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "tdx_vendorid_2", description: "CPU vendor ID string bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - ( - Parameters{ leaf: 0x21, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "tdx_vendorid_1", description: "CPU vendor ID string bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ]) - ), - - // =================================================================================================================== - // Architectural Performance Monitoring Extended Main Leaf - // =================================================================================================================== - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "subleaf_0", description: "If 1, subleaf 0 exists", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "subleaf_1", description: "If 1, subleaf 1 exists", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "subleaf_2", description: "If 1, subleaf 2 exists", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "subleaf_3", description: "If 1, subleaf 3 exists", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "subleaf_4", description: "If 1, subleaf 4 exists", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ - short: "subleaf_5", - description: "If 1, subleaf 5 exists. The processor suppots Architectural PEBS. The IA32_PEBS_BASE and IA32_PEBS_INDEX MSRs exist", - bits_range: (5, 5), - policy: ProfilePolicy::Overwrite(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits - }, - ]) - ), - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "unitmask2", description: "IA32_PERFEVTSELx MSRs UnitMask2 is supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "eq_bit", description: "equal flag in the IA32_PERFEVTSELx MSR is supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "RDPMC_USR_DISABLE", description: "RDPMC_USR_DISABLE", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - // TODO: Not sure about migration compatibility - ValueDefinition{ - short: "num_slots_per_cycle", - description: "Number of slots per cycle. This number can be multiplied by the number of cycles (from CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.CORE or IA32_FIXED_CTR1) to determine the total number of slots", - bits_range: (0, 7), - policy: ProfilePolicy::Overwrite(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq - }, - ]) - ), - - // =================================================================================================================== - // Architectural Performance Monitoring Extended Sub-leaf 1 - // =================================================================================================================== - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pmu_gp_counters_bitmap", description: "General-purpose PMU counters bitmap", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 1, 1), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pmu_f_counters_bitmap", description: "Fixed PMU counters bitmap", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Architectural Performance Monitoring Extended Sub-leaf 2 - // =================================================================================================================== - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 2, 2), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pmu_acr_bitmap", description: "Bitmap of Auto Counter Reload (ACR) general-purpose counters that can be reloaded", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Architectural Performance Monitoring Extended Sub-leaf 3 - // =================================================================================================================== - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 3, 3), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "core_cycles_evt", description: "Core cycles event supported", bits_range: (0, 0), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "insn_retired_evt", description: "Instructions retired event supported", bits_range: (1, 1), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "ref_cycles_evt", description: "Reference cycles event supported", bits_range: (2, 2), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "llc_refs_evt", description: "Last-level cache references event supported", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "llc_misses_evt", description: "Last-level cache misses event supported", bits_range: (4, 4), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "br_insn_ret_evt", description: "Branch instruction retired event supported", bits_range: (5, 5), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "br_mispr_evt", description: "Branch mispredict retired event supported", bits_range: (6, 6), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "td_slots_evt", description: "Topdown slots event supported", bits_range: (7, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "td_backend_bound_evt", description: "Topdown backend bound event supported", bits_range: (8, 8), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "td_bad_spec_evt", description: "Topdown bad speculation event supported", bits_range: (9, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "td_frontend_bound_evt", description: "Topdown frontend bound event supported", bits_range: (10, 10), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "td_retiring_evt", description: "Topdown retiring event support", bits_range: (11, 11), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "lbr_inserts", description: "LBR support", bits_range: (12, 12), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // =================================================================================================================== - // Architectural Performance Monitoring Extended Sub-leaf 4 - // =================================================================================================================== - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 4, 4), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "allow_in_record", description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Should the migration compatibility check rather be CintainsBits? - ValueDefinition{ short: "cntr", description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", bits_range: (0, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - // TODO: Should the migration compatibility check rather be CintainsBits? - ValueDefinition{ short: "lbr", description: "LBR group and both bits [41:40] are available", bits_range: (8, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - // TODO: Should the migration compatibility check rather be CintainsBits? - ValueDefinition{ short: "xer", description: "These bits correspond to XER group bits [55:49]", bits_range: (17, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "grp", description: "If 1, the GRP group is available", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "aux", description: "If 1, the AUX group is available", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 4, 4), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "allow_in_record", description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", bits_range: (3, 3), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Should the migration compatibility check rather be CintainsBits? - ValueDefinition{ short: "cntr", description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", bits_range: (0, 7), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - // TODO: Should the migration compatibility check rather be CintainsBits? - ValueDefinition{ short: "lbr", description: "LBR group and both bits [41:40] are available", bits_range: (8, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - // TODO: Should the migration compatibility check rather be CintainsBits? - ValueDefinition{ short: "xer", description: "These bits correspond to XER group bits [55:49]", bits_range: (17, 23), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq }, - ValueDefinition{ short: "grp", description: "If 1, the GRP group is available", bits_range: (29, 29), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "aux", description: "If 1, the AUX group is available", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - - // =================================================================================================================== - // Architectural Performance Monitoring Extended Sub-leaf 5 - // =================================================================================================================== - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "architectural_pebs_counters", description: "General-purpose counters support Architectural PEBS. Bit vector of general-purpose counters for which the Architectural PEBS mechanism is available", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ]) - ), - - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pebs_pdist_counters", description: "General-purpose counters for which PEBS support PDIST", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ]) - ), - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pebs_fixed_function_counters", description: "Fixed-function counters support Architectural PEBS. Bit vector of fixed-function counters for which the Architectural PEBS mechanism is available. If ECX[x] == 1, then the IA32_PMC_FXm_CFG_C MSR is available, and PEBS is supported", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ]) - ), - - ( - Parameters{ leaf: 0x23, sub_leaf:RangeInclusive::new( 5, 5), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "pebs_fixed_function_pdist_counters", description: "Fixed-function counters for which PEBS supports PDIST", bits_range: (0, 31), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits}, - ]) - ), - - // =================================================================================================================== - // Converged Vector ISA Main Leaf - // =================================================================================================================== - - ( - Parameters{ leaf: 0x24, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "converged_vector_isa_max_sub_leaves", description: "Reports the maximum number of sub-leaves that are supported in leaf 0x24", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq}, - ]) - ), - - ( - Parameters{ leaf: 0x24, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "avx_10_version", description: "Reports the intel AVX10 Converged Vector ISA version", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq}, - ValueDefinition{ short: "avx_10_lengths", description: "Reserved at 111", bits_range: (0, 7), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore}, - ]) - ), - - // Hypervisor reserved CPUID leaves are set elsewhere - - // =================================================================================================================== - // Extended Function CPUID Information - // =================================================================================================================== - - ( - Parameters{ leaf: 0x80000000, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "max_ext_leaf", description: "Maximum extended CPUID leaf supported", bits_range: (0, 31), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::GtEq }, - ]) - ), - - ( - Parameters{ leaf: 0x80000000, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_vendorid_0", description: "Vendor ID string bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000000, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_vendorid_2", description: "Vendor ID string bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000000, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_vendorid_1", description: "Vendor ID string bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000001, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - // TODO: Would inherit be better than passthrough? Currently CHV manually copies these over from the host ... - ValueDefinitions::new(&[ - ValueDefinition{ short: "e_stepping_id", description: "Stepping ID", bits_range: (0, 3), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "e_base_model", description: "Base processor model", bits_range: (4, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "e_base_family", description: "Base processor family", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "e_base_type", description: "Base processor type (Transmeta)", bits_range: (12, 13), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "e_ext_model", description: "Extended processor model", bits_range: (16, 19), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "e_ext_family", description: "Extended processor family", bits_range: (20, 27), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000001, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "brand_id", description: "Brand ID", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "pkg_type", description: "Package type", bits_range: (28, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000001, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "lahf_lm", description: "LAHF and SAHF in 64-bit mode", bits_range: (0, 0), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "lzcnt", description: "LZCNT advanced bit manipulation", bits_range: (5, 5), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "prefetchw", description: "3DNow PREFETCH/PREFETCHW support", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x80000001, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "syscall", description: "SYSCALL and SYSRET instructions", bits_range: (11, 11), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "nx", description: "Execute Disable Bit available", bits_range: (20, 20), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "pdpe1gb", description: "1-GB large page support", bits_range: (26, 26), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - // TODO: Should this perhaps be overwritten to 0 and require opt-in via a feature? - ValueDefinition{ short: "rdtscp", description: "RDTSCP instruction and IA32_TSC_AUX are available", bits_range: (27, 27), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ValueDefinition{ short: "lm", description: "Long mode (x86-64, 64-bit support)", bits_range: (29, 29), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - // TODO: Would it be better to inherit these for the CPU profile (or zero it out entirely?) - ( - Parameters{ leaf: 0x80000002, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_0", description: "CPU brand ID string, bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000002, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_1", description: "CPU brand ID string, bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000002, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_2", description: "CPU brand ID string, bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000002, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_3", description: "CPU brand ID string, bytes 12 - 15", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000003, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_4", description: "CPU brand ID string bytes, 16 - 19", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000003, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_5", description: "CPU brand ID string bytes, 20 - 23", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000003, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_6", description: "CPU brand ID string bytes, 24 - 27", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000003, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_7", description: "CPU brand ID string bytes, 28 - 31", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000004, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_8", description: "CPU brand ID string, bytes 32 - 35", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000004, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_9", description: "CPU brand ID string, bytes 36 - 39", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000004, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_10", description: "CPU brand ID string, bytes 40 - 43", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000004, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "cpu_brandid_11", description: "CPU brand ID string, bytes 44 - 47", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000006, sub_leaf: RangeInclusive::new(0,0), register: CpuidReg::ECX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "l2_line_size", description: "L2 cache line size, in bytes", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "l2_nlines", description: "L2 cache number of lines per tag", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "l2_assoc", description: "L2 cache associativity", bits_range: (12, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "l2_size_kb", description: "L2 cache size, in KB", bits_range: (16, 31), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - // EAX, EBX and ECX of 0x8000_0007 are all reserved (=0) on Intel - - ( - Parameters{ leaf: 0x80000007, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EDX }, - ValueDefinitions::new(&[ - // TODO: We may want some mechanism to let users opt-in to using an invariant TSC provided by the hardware (when available). - // TODO: Probably unconditionally set by CHV - ValueDefinition{ short: "constant_tsc", description: "TSC ticks at constant rate across all P and C states", bits_range: (8, 8), policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ), - - ( - Parameters{ leaf: 0x80000008, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EAX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "phys_addr_bits", description: "Max physical address bits", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "virt_addr_bits", description: "Max virtual address bits", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ValueDefinition{ short: "guest_phys_addr_bits", description: "Max nested-paging guest physical address bits", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore }, - ]) - ), - - ( - Parameters{ leaf: 0x80000008, sub_leaf:RangeInclusive::new( 0, 0), register: CpuidReg::EBX }, - ValueDefinitions::new(&[ - ValueDefinition{ short: "wbnoinvd", description: "WBNOINVD supported", bits_range: (9, 9), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, - ]) - ) - ]) -}; - + CpuidDefinitions([ + // ========================================================================================= + // Basic CPUID Information + // ========================================================================================= + ( + Parameters { + leaf: 0x0, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "max_std_leaf", + description: "Maximum Input value for Basic CPUID Information", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x0, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_vendorid_0", + description: "CPU vendor ID string bytes 0 - 3", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0x0, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_vendorid_2", + description: "CPU vendor ID string bytes 8 - 11", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0x0, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_vendorid_1", + description: "CPU vendor ID string bytes 4 - 7", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + // TODO: Do we really want to inherit these values from the corresponding CPU, or should we zero it out or set something else here? + ( + Parameters { + leaf: 0x1, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "stepping", + description: "Stepping ID", + bits_range: (0, 3), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "base_model", + description: "Base CPU model ID", + bits_range: (4, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "base_family_id", + description: "Base CPU family ID", + bits_range: (8, 11), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "cpu_type", + description: "CPU type", + bits_range: (12, 13), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "ext_model", + description: "Extended CPU model ID", + bits_range: (16, 19), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "ext_family", + description: "Extended CPU family ID", + bits_range: (20, 27), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x1, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "brand_id", + description: "Brand index", + bits_range: (0, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "clflush_size", + description: "CLFLUSH instruction cache line size", + bits_range: (8, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + // This is set by cloud hypervisor + ValueDefinition { + short: "n_logical_cpu", + description: "Logical CPU count", + bits_range: (16, 23), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + // This is set by cloud hypervisor + ValueDefinition { + short: "local_apic_id", + description: "Initial local APIC physical ID", + bits_range: (24, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x1, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "sse3", + description: "Streaming SIMD Extensions 3 (SSE3)", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pclmulqdq", + description: "PCLMULQDQ instruction support", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "dtes64", + description: "64-bit DS save area", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Perhaps there should be some CHV feature for opting in to enabling this for non-host CPU profiles? + ValueDefinition { + short: "monitor", + description: "MONITOR/MWAIT support", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ds_cpl", + description: "CPL Qualified Debug Store", + bits_range: (4, 4), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Ideally configurable by the user (host must have this otherwise CHV will not run) + ValueDefinition { + short: "vmx", + description: "Virtual Machine Extensions", + bits_range: (5, 5), + policy: ProfilePolicy::Overwrite(1), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "smx", + description: "Safer Mode Extensions", + bits_range: (6, 6), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "est", + description: "Enhanced Intel SpeedStep", + bits_range: (7, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "tm2", + description: "Thermal Monitor 2", + bits_range: (8, 8), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ssse3", + description: "Supplemental SSE3", + bits_range: (9, 9), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "cnxt_id", + description: "L1 Context ID", + bits_range: (10, 10), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "sdbg", + description: "Silicon Debug", + bits_range: (11, 11), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "fma", + description: "FMA extensions using YMM state", + bits_range: (12, 12), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cx16", + description: "CMPXCHG16B instruction support", + bits_range: (13, 13), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "xtpr", + description: "xTPR Update Control", + bits_range: (14, 14), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "pdcm", + description: "Perfmon and Debug Capability", + bits_range: (15, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pcid", + description: "Process-context identifiers", + bits_range: (17, 17), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "dca", + description: "Direct Cache Access", + bits_range: (18, 18), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "sse4_1", + description: "SSE4.1", + bits_range: (19, 19), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "sse4_2", + description: "SSE4.2", + bits_range: (20, 20), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // Set by Cloud hypervisor + ValueDefinition { + short: "x2apic", + description: "X2APIC support", + bits_range: (21, 21), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "movbe", + description: "MOVBE instruction support", + bits_range: (22, 22), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "popcnt", + description: "POPCNT instruction support", + bits_range: (23, 23), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // Set by Cloud hypervisor + ValueDefinition { + short: "tsc_deadline_timer", + description: "APIC timer one-shot operation", + bits_range: (24, 24), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "aes", + description: "AES instructions", + bits_range: (25, 25), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xsave", + description: "XSAVE (and related instructions) support", + bits_range: (26, 26), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Seems to no longer be supported by QEMU, but is by KVM? We disable this for now. + ValueDefinition { + short: "osxsave", + description: "XSAVE (and related instructions) are enabled by OS", + bits_range: (27, 27), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx", + description: "AVX instructions support", + bits_range: (28, 28), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "f16c", + description: "Half-precision floating-point conversion support", + bits_range: (29, 29), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "rdrand", + description: "RDRAND instruction support", + bits_range: (30, 30), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: If set by CHV set to 0 and write comment + ValueDefinition { + short: "guest_status", + description: "System is running as guest; (para-)virtualized system", + bits_range: (31, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x1, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "fpu", + description: "Floating-Point Unit on-chip (x87)", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "vme", + description: "Virtual-8086 Mode Extensions", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "de", + description: "Debugging Extensions", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pse", + description: "Page Size Extension", + bits_range: (3, 3), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Does this also need special handling like TSC_DEADLINE_TIMER? + ValueDefinition { + short: "tsc", + description: "Time Stamp Counter", + bits_range: (4, 4), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "msr", + description: "Model-Specific Registers (RDMSR and WRMSR support)", + bits_range: (5, 5), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pae", + description: "Physical Address Extensions", + bits_range: (6, 6), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mce", + description: "Machine Check Exception", + bits_range: (7, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cx8", + description: "CMPXCHG8B instruction", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "apic", + description: "APIC on-chip", + bits_range: (9, 9), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related (maybe not necessary to look into which ones) + ValueDefinition { + short: "sep", + description: "SYSENTER, SYSEXIT, and associated MSRs", + bits_range: (11, 11), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mtrr", + description: "Memory Type Range Registers", + bits_range: (12, 12), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pge", + description: "Page Global Extensions", + bits_range: (13, 13), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mca", + description: "Machine Check Architecture", + bits_range: (14, 14), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cmov", + description: "Conditional Move Instruction", + bits_range: (15, 15), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pat", + description: "Page Attribute Table", + bits_range: (16, 16), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pse36", + description: "Page Size Extension (36-bit)", + bits_range: (17, 17), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "psn", + description: "Processor Serial Number", + bits_range: (18, 18), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "clfsh", + description: "CLFLUSH instruction", + bits_range: (19, 19), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ds", + description: "Debug Store", + bits_range: (21, 21), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "acpi", + description: "Thermal monitor and clock control", + bits_range: (22, 22), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mmx", + description: "MMX instructions", + bits_range: (23, 23), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "fxsr", + description: "FXSAVE and FXRSTOR instructions", + bits_range: (24, 24), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "sse", + description: "SSE instructions", + bits_range: (25, 25), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "sse2", + description: "SSE2 instructions", + bits_range: (26, 26), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ss", + description: "Self Snoop", + bits_range: (27, 27), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "htt", + description: "Hyper-threading", + bits_range: (28, 28), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "tm", + description: "Thermal Monitor", + bits_range: (29, 29), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Not really sure what the default should be for PBE. It seems like it is something that needs to be enabled via the IA32_MISC_ENABLE MSR hence perhaps this should be set via CPU features? + // MSR related + ValueDefinition { + short: "pbe", + description: "Pending Break Enable", + bits_range: (31, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // ========================================================================================= + // Cache and TLB Information + // ========================================================================================= + ( + Parameters { + leaf: 0x2, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "iteration_count", + description: "Number of times this leaf must be queried", + bits_range: (0, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc1", + description: "Descriptor #1", + bits_range: (8, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc2", + description: "Descriptor #2", + bits_range: (16, 23), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc3", + description: "Descriptor #3", + bits_range: (24, 30), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "eax_invalid", + description: "Descriptors 1-3 are invalid if set", + bits_range: (31, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x2, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "desc4", + description: "Descriptor #4", + bits_range: (0, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc5", + description: "Descriptor #5", + bits_range: (8, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc6", + description: "Descriptor #6", + bits_range: (16, 23), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc7", + description: "Descriptor #7", + bits_range: (24, 30), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "ebx_invalid", + description: "Descriptors 4-7 are invalid if set", + bits_range: (31, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x2, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "desc8", + description: "Descriptor #8", + bits_range: (0, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc9", + description: "Descriptor #9", + bits_range: (8, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc10", + description: "Descriptor #10", + bits_range: (16, 23), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc11", + description: "Descriptor #11", + bits_range: (24, 30), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "ecx_invalid", + description: "Descriptors 8-11 are invalid if set", + bits_range: (31, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x2, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "desc12", + description: "Descriptor #12", + bits_range: (0, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc13", + description: "Descriptor #13", + bits_range: (8, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc14", + description: "Descriptor #14", + bits_range: (16, 23), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "desc15", + description: "Descriptor #15", + bits_range: (24, 30), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "edx_invalid", + description: "Descriptors 12-15 are invalid if set", + bits_range: (31, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + // ========================================================================================= + // Deterministic Cache Parameters + // ========================================================================================= + ( + Parameters { + leaf: 0x4, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "cache_type", + description: "Cache type field", + bits_range: (0, 4), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "cache_level", + description: "Cache level (1-based)", + bits_range: (5, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + // TODO: Could there be a problem migrating from a CPU with self-initializing cache to one without? + ValueDefinition { + short: "cache_self_init", + description: "Self-initializing cache level", + bits_range: (8, 8), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "fully_associative", + description: "Fully-associative cache", + bits_range: (9, 9), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "num_threads_sharing", + description: "Number logical CPUs sharing this cache", + bits_range: (14, 25), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "num_cores_on_die", + description: "Number of cores in the physical package", + bits_range: (26, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x4, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "cache_linesize", + description: "System coherency line size (0-based)", + bits_range: (0, 11), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "cache_npartitions", + description: "Physical line partitions (0-based)", + bits_range: (12, 21), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "cache_nways", + description: "Ways of associativity (0-based)", + bits_range: (22, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x4, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cache_nsets", + description: "Cache number of sets (0-based)", + bits_range: (0, 30), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x4, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "wbinvd_rll_no_guarantee", + description: "WBINVD/INVD not guaranteed for Remote Lower-Level caches", + bits_range: (0, 0), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "ll_inclusive", + description: "Cache is inclusive of Lower-Level caches", + bits_range: (1, 1), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "complex_indexing", + description: "Not a direct-mapped cache (complex function)", + bits_range: (2, 2), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + // ========================================================================================= + // MONITOR/MWAIT + // ========================================================================================= + ( + Parameters { + leaf: 0x5, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "min_mon_size", + description: "Smallest monitor-line size, in bytes", + bits_range: (0, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::LtEq, + }]), + ), + ( + Parameters { + leaf: 0x5, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "max_mon_size", + description: "Largest monitor-line size, in bytes", + bits_range: (0, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x5, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "mwait_ext", + description: "Enumeration of MONITOR/MWAIT extensions is supported", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mwait_irq_break", + description: "Interrupts as a break-event for MWAIT is supported", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x5, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "n_c0_substates", + description: "Number of C0 sub C-states supported using MWAIT", + bits_range: (0, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "n_c1_substates", + description: "Number of C1 sub C-states supported using MWAIT", + bits_range: (4, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "n_c2_substates", + description: "Number of C2 sub C-states supported using MWAIT", + bits_range: (8, 11), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "n_c3_substates", + description: "Number of C3 sub C-states supported using MWAIT", + bits_range: (12, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "n_c4_substates", + description: "Number of C4 sub C-states supported using MWAIT", + bits_range: (16, 19), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "n_c5_substates", + description: "Number of C5 sub C-states supported using MWAIT", + bits_range: (20, 23), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "n_c6_substates", + description: "Number of C6 sub C-states supported using MWAIT", + bits_range: (24, 27), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "n_c7_substates", + description: "Number of C7 sub C-states supported using MWAIT", + bits_range: (28, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + // ========================================================================================= + // Thermal and Power Management + // ========================================================================================= + ( + Parameters { + leaf: 0x6, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "dtherm", + description: "Digital temperature sensor", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "turbo_boost", + description: "Intel Turbo Boost", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "arat", + description: "Always-Running APIC Timer (not affected by p-state)", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pln", + description: "Power Limit Notification (PLN) event", + bits_range: (4, 4), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ecmd", + description: "Clock modulation duty cycle extension", + bits_range: (5, 5), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pts", + description: "Package thermal management", + bits_range: (6, 6), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp", + description: "HWP (Hardware P-states) base registers are supported", + bits_range: (7, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp_notify", + description: "HWP notification (IA32_HWP_INTERRUPT MSR)", + bits_range: (8, 8), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp_act_window", + description: "HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported", + bits_range: (9, 9), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp_epp", + description: "HWP Energy Performance Preference", + bits_range: (10, 10), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp_pkg_req", + description: "HWP Package Level Request", + bits_range: (11, 11), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hdc_base_regs", + description: "HDC base registers are supported", + bits_range: (13, 13), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "turbo_boost_3_0", + description: "Intel Turbo Boost Max 3.0", + bits_range: (14, 14), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp_capabilities", + description: "HWP Highest Performance change", + bits_range: (15, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp_peci_override", + description: "HWP PECI override", + bits_range: (16, 16), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp_flexible", + description: "Flexible HWP", + bits_range: (17, 17), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp_fast", + description: "IA32_HWP_REQUEST MSR fast access mode", + bits_range: (18, 18), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hfi", + description: "HW_FEEDBACK MSRs supported", + bits_range: (19, 19), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hwp_ignore_idle", + description: "Ignoring idle logical CPU HWP req is supported", + bits_range: (20, 20), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "thread_director", + description: "Intel thread director support", + bits_range: (23, 23), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "therm_interrupt_bit25", + description: "IA32_THERM_INTERRUPT MSR bit 25 is supported", + bits_range: (24, 24), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x6, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + // TODO: Do we perhaps need some requirement for migration compatibility here? + ValueDefinition { + short: "n_therm_thresholds", + description: "Digital thermometer thresholds", + bits_range: (0, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x6, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + // MSR related + ValueDefinition { + short: "aperfmperf", + description: "MPERF/APERF MSRs (effective frequency interface)", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "epb", + description: "IA32_ENERGY_PERF_BIAS MSR support", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "thrd_director_nclasses", + description: "Number of classes, Intel thread director", + bits_range: (8, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x6, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "perfcap_reporting", + description: "Performance capability reporting", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "encap_reporting", + description: "Energy efficiency capability reporting", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "feedback_sz", + description: "Feedback interface structure size, in 4K pages", + bits_range: (8, 11), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "this_lcpu_hwfdbk_idx", + description: "This logical CPU hardware feedback interface index", + bits_range: (16, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + // =================================================================================================================== + // Structured Extended Feature Flags Enumeration Main Leaf + // =================================================================================================================== + ( + Parameters { + leaf: 0x7, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "leaf7_n_subleaves", + description: "Number of leaf 0x7 subleaves", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x7, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "fsgsbase", + description: "FSBASE/GSBASE read/write support", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "tsc_adjust", + description: "IA32_TSC_ADJUST MSR supported", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // SGX is deprecated so we disable it unconditionally for all CPU profiles + ValueDefinition { + short: "sgx", + description: "Intel SGX (Software Guard Extensions)", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "bmi1", + description: "Bit manipulation extensions group 1", + bits_range: (3, 3), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TSX related which is riddled with CVEs. Consider two profiles, or making it opt-in/out. QEMU always has a CPU model with and without TSX. + ValueDefinition { + short: "hle", + description: "Hardware Lock Elision", + bits_range: (4, 4), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx2", + description: "AVX2 instruction set", + bits_range: (5, 5), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + /*The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). + + Keep in mind however that in my limited understanding this isn't about enabling or disabling a feature, but it describes critical behaviour. + Hence I am wondering whether it should be a hard error if the host does not have this bit set, but the desired CPU profile does? + + TODO: Check what KVM_GET_SUPPORTED_CPUID actually gives here (on the Skylake server) + */ + ValueDefinition { + short: "fdp_excptn_only", + description: "FPU Data Pointer updated only on x87 exceptions", + bits_range: (6, 6), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "smep", + description: "Supervisor Mode Execution Protection", + bits_range: (7, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "bmi2", + description: "Bit manipulation extensions group 2", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "erms", + description: "Enhanced REP MOVSB/STOSB", + bits_range: (9, 9), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + /* + The instruction enabled by this seems rather powerful. Are we sure that doesn't have security implications? + I included this because it seems like QEMU does (to the best of my understanding). + */ + ValueDefinition { + short: "invpcid", + description: "INVPCID instruction (Invalidate Processor Context ID)", + bits_range: (10, 10), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // This is TSX related from what I can tell. TSX is riddled with CVEs: Consider two profiles (one with it disabled) or an opt-in/out feature. + ValueDefinition { + short: "rtm", + description: "Intel restricted transactional memory", + bits_range: (11, 11), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "rdt_m", + description: "Supports Intel Resource Director Technology Monitoring Capability if 1", + bits_range: (12, 12), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). TODO: Is it OK to just set this to 1? + ValueDefinition { + short: "zero_fcs_fds", + description: "Deprecates FPU CS and FPU DS values if 1", + bits_range: (13, 13), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // This has been deprecated + ValueDefinition { + short: "mpx", + description: "Intel memory protection extensions", + bits_range: (14, 14), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // This might be useful for certain high performance applications, but it also seems like a rather niche and advanced feature. QEMU does also not automatically enable this from what we can tell. + // TODO: Should we make this OPT-IN? + ValueDefinition { + short: "rdt_a", + description: "Intel RDT-A. Supports Intel Resource Director Technology Allocation Capability if 1", + bits_range: (15, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Do the wider avx512 zmm registers work out of the box when the hardware supports it? + ValueDefinition { + short: "avx512f", + description: "AVX-512 foundation instructions", + bits_range: (16, 16), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512dq", + description: "AVX-512 double/quadword instructions", + bits_range: (17, 17), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "rdseed", + description: "RDSEED instruction", + bits_range: (18, 18), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "adx", + description: "ADCX/ADOX instructions", + bits_range: (19, 19), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "smap", + description: "Supervisor mode access prevention", + bits_range: (20, 20), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512ifma", + description: "AVX-512 integer fused multiply add", + bits_range: (21, 21), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "clflushopt", + description: "CLFLUSHOPT instruction", + bits_range: (23, 23), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "clwb", + description: "CLWB instruction", + bits_range: (24, 24), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "intel_pt", + description: "Intel processor trace", + bits_range: (25, 25), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512pf", + description: "AVX-512 prefetch instructions", + bits_range: (26, 26), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512er", + description: "AVX-512 exponent/reciprocal instructions", + bits_range: (27, 27), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512cd", + description: "AVX-512 conflict detection instructions", + bits_range: (28, 28), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "sha_ni", + description: "SHA/SHA256 instructions", + bits_range: (29, 29), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512bw", + description: "AVX-512 byte/word instructions", + bits_range: (30, 30), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512vl", + description: "AVX-512 VL (128/256 vector length) extensions", + bits_range: (31, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x7, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "prefetchwt1", + description: "PREFETCHWT1 (Intel Xeon Phi only)", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512vbmi", + description: "AVX-512 Vector byte manipulation instructions", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // Also set by QEMU for CPU models from what we can tell + ValueDefinition { + short: "umip", + description: "User mode instruction protection", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // Also set by QEMU for CPU models from what we can tell + ValueDefinition { + short: "pku", + description: "Protection keys for user-space", + bits_range: (3, 3), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ospke", + description: "OS protection keys enable", + bits_range: (4, 4), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: QEMU seems to set this unconditionally whenever KVM supports it (TODO: Would it be best to set this unconditionally?) + ValueDefinition { + short: "waitpkg", + description: "WAITPKG instructions", + bits_range: (5, 5), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512_vbmi2", + description: "AVX-512 vector byte manipulation instructions group 2", + bits_range: (6, 6), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: This may be useful for nested virtualization? Perhaps it should be opt-in rather than unconditionally disabled? + ValueDefinition { + short: "cet_ss", + description: "CET shadow stack features", + bits_range: (7, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "gfni", + description: "Galois field new instructions", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "vaes", + description: "Vector AES instructions", + bits_range: (9, 9), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "vpclmulqdq", + description: "VPCLMULQDQ 256-bit instruction support", + bits_range: (10, 10), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512_vnni", + description: "Vector neural network instructions", + bits_range: (11, 11), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512_bitalg", + description: "AVX-512 bitwise algorithms", + bits_range: (12, 12), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // Seems to be TDX related which is experimental in CHV. We disable this for CPU profiles for now, but could potentially add it as an opt-in feature eventually. + ValueDefinition { + short: "tme", + description: "Intel total memory encryption", + bits_range: (13, 13), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512_vpopcntdq", + description: "AVX-512: POPCNT for vectors of DWORD/QWORD", + bits_range: (14, 14), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "la57", + description: "57-bit linear addresses (five-level paging)", + bits_range: (16, 16), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mawau_val_lm", + description: "BNDLDX/BNDSTX MAWAU value in 64-bit mode", + bits_range: (17, 21), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + // MSR related + ValueDefinition { + short: "rdpid", + description: "RDPID instruction", + bits_range: (22, 22), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // We leave key locker support out for CPU profiles for the time being. We may want this to be opt-in in the future though + ValueDefinition { + short: "key_locker", + description: "Intel key locker support", + bits_range: (23, 23), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "bus_lock_detect", + description: "OS bus-lock detection", + bits_range: (24, 24), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cldemote", + description: "CLDEMOTE instruction", + bits_range: (25, 25), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "movdiri", + description: "MOVDIRI instruction", + bits_range: (27, 27), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "movdir64b", + description: "MOVDIR64B instruction", + bits_range: (28, 28), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "enqcmd", + description: "Enqueue stores supported (ENQCMD{,S})", + bits_range: (29, 29), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // SGX support is deprecated so we disable it unconditionally for CPU profiles + ValueDefinition { + short: "sgx_lc", + description: "Intel SGX launch configuration", + bits_range: (30, 30), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pks", + description: "Protection keys for supervisor-mode pages", + bits_range: (31, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x7, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + // SGX is deprecated + ValueDefinition { + short: "sgx_keys", + description: "Intel SGX attestation services", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512_4vnniw", + description: "AVX-512 neural network instructions (Intel Xeon Phi only?)", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512_4fmaps", + description: "AVX-512 multiply accumulation single precision (Intel Xeon Phi only?)", + bits_range: (3, 3), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "fsrm", + description: "Fast short REP MOV", + bits_range: (4, 4), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "uintr", + description: "CPU supports user interrupts", + bits_range: (5, 5), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512_vp2intersect", + description: "VP2INTERSECT{D,Q} instructions", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "srdbs_ctrl", + description: "SRBDS mitigation MSR available: If 1, enumerates support for the IA32_MCU_OPT_CTRL MSR and indicates that its bit 0 (RNGDS_MITG_DIS) is also supported.", + bits_range: (9, 9), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "md_clear", + description: "VERW MD_CLEAR microcode support", + bits_range: (10, 10), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "rtm_always_abort", + description: "XBEGIN (RTM transaction) always aborts", + bits_range: (11, 11), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "tsx_force_abort", + description: "MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported", + bits_range: (13, 13), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "serialize", + description: "SERIALIZE instruction", + bits_range: (14, 14), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hybrid_cpu", + description: "The CPU is identified as a 'hybrid part'", + bits_range: (15, 15), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: This is TSX related which is riddled with CVEs. We should carefully decide what to do with regards to this feature. + ValueDefinition { + short: "tsxldtrk", + description: "TSX suspend/resume load address tracking", + bits_range: (16, 16), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // Might be relevant for confidential computing + ValueDefinition { + short: "pconfig", + description: "PCONFIG instruction", + bits_range: (18, 18), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "arch_lbr", + description: "Intel architectural LBRs", + bits_range: (19, 19), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure if this is the best default, but QEMU also seems to disable this for CPU models + ValueDefinition { + short: "ibt", + description: "CET indirect branch tracking", + bits_range: (20, 20), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_bf16", + description: "AMX-BF16: tile bfloat16 support", + bits_range: (22, 22), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512_fp16", + description: "AVX-512 FP16 instructions", + bits_range: (23, 23), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_tile", + description: "AMX-TILE: tile architecture support", + bits_range: (24, 24), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_int8", + description: "AMX-INT8: tile 8-bit integer support", + bits_range: (25, 25), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "spec_ctrl", + description: "Speculation Control (IBRS/IBPB: indirect branch restrictions)", + bits_range: (26, 26), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "intel_stibp", + description: "Single thread indirect branch predictors", + bits_range: (27, 27), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "flush_l1d", + description: "FLUSH L1D cache: IA32_FLUSH_CMD MSR", + bits_range: (28, 28), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "arch_capabilities", + description: "Intel IA32_ARCH_CAPABILITIES MSR", + bits_range: (29, 29), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "core_capabilities", + description: "IA32_CORE_CAPABILITIES MSR", + bits_range: (30, 30), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "spec_ctrl_ssbd", + description: "Speculative store bypass disable", + bits_range: (31, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Structured Extended Feature Flags Enumeration Sub-Leaf 1 + // =================================================================================================================== + ( + Parameters { + leaf: 0x7, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "sha512", + description: "SHA-512 extensions", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "sm3", + description: "SM3 instructions", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "sm4", + description: "SM4 instructions", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // RAO-INT is deprecated and removed from most compilers as far as we are aware + ValueDefinition { + short: "RAO-INT", + description: "RAO-INT instructions", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx_vnni", + description: "AVX-VNNI instructions", + bits_range: (4, 4), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx512_bf16", + description: "AVX-512 bfloat16 instructions", + bits_range: (5, 5), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + /* + Not set in QEMU from what we can tell, but according seems to be fine to expose this to guests + if we understood https://www.phoronix.com/news/Intel-Linux-LASS-KVM correctly. It is also + our understanding that this feature can enable guests opting in to more security (possibly at the cost of some performance). + */ + ValueDefinition { + short: "lass", + description: "Linear address space separation", + bits_range: (6, 6), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cmpccxadd", + description: "CMPccXADD instructions", + bits_range: (7, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "arch_perfmon_ext", + description: "ArchPerfmonExt: leaf 0x23 is supported", + bits_range: (8, 8), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "fzrm", + description: "Fast zero-length REP MOVSB", + bits_range: (10, 10), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "fsrs", + description: "Fast short REP STOSB", + bits_range: (11, 11), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "fsrc", + description: "Fast Short REP CMPSB/SCASB", + bits_range: (12, 12), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "fred", + description: "FRED: Flexible return and event delivery transitions", + bits_range: (17, 17), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lkgs", + description: "LKGS: Load 'kernel' (userspace) GS", + bits_range: (18, 18), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "wrmsrns", + description: "WRMSRNS instruction (WRMSR-non-serializing)", + bits_range: (19, 19), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "nmi_src", + description: "NMI-source reporting with FRED event data", + bits_range: (20, 20), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_fp16", + description: "AMX-FP16: FP16 tile operations", + bits_range: (21, 21), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "hreset", + description: "History reset support", + bits_range: (22, 22), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx_ifma", + description: "Integer fused multiply add", + bits_range: (23, 23), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lam", + description: "Linear address masking", + bits_range: (26, 26), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "rd_wr_msrlist", + description: "RDMSRLIST/WRMSRLIST instructions", + bits_range: (27, 27), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "invd_disable_post_bios_done", + description: "If 1, supports INVD execution prevention after BIOS Done", + bits_range: (30, 30), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "movrs", + description: "MOVRS", + bits_range: (31, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x7, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "intel_ppin", + description: "Protected processor inventory number (PPIN{,_CTL} MSRs)", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "pbndkb", + description: "PBNDKB instruction supported and enumerates the existence of the IA32_TSE_CAPABILITY MSR", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // TODO: Missing entry for (0x7, 1, ECX) + // Make the whole register zero though + // + ( + Parameters { + leaf: 0x7, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "avx_vnni_int8", + description: "AVX-VNNI-INT8 instructions", + bits_range: (4, 4), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx_ne_convert", + description: "AVX-NE-CONVERT instructions", + bits_range: (5, 5), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the value will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinition { + short: "amx_complex", + description: "AMX-COMPLEX instructions (starting from Granite Rapids)", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx_vnni_int16", + description: "AVX-VNNI-INT16 instructions", + bits_range: (10, 10), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "utmr", + description: "If 1, supports user-timer events", + bits_range: (13, 13), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "prefetchit_0_1", + description: "PREFETCHIT0/1 instructions", + bits_range: (14, 14), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "user_msr", + description: "If 1, supports the URDMSR and UWRMSR instructions", + bits_range: (15, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "uiret_uif", + description: "If 1, UIRET sets UIF to the value of bit 1 of the RFLAGS image loaded from the stack", + bits_range: (15, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cet_sss", + description: "CET supervisor shadow stacks safe to use", + bits_range: (18, 18), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "avx10", + description: "If 1, supports the Intel AVX10 instructions and indicates the presence of leaf 0x24", + bits_range: (19, 19), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "apx_f", + description: "If 1, the processor provides foundational support for Intel Advanced Performance Extensions", + bits_range: (21, 21), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mwait", + description: "If 1, MWAIT is supported even if (0x1 ECX bit 3 (monitor) is enumerated as 0)", + bits_range: (23, 23), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "slsm", + description: "If 1, indicates bit 0 of the IA32_INTEGRITY_STATUS MSR is supported. Bit 0 of this MSR indicates whether static lockstep is active on this logical processor", + bits_range: (24, 24), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Structured Extended Feature Flags Enumeration Sub-Leaf 2 + // =================================================================================================================== + ( + Parameters { + leaf: 0x7, + sub_leaf: RangeInclusive::new(2, 2), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + // MSR related + ValueDefinition { + short: "intel_psfd", + description: "If 1, indicates bit 7 of the IA32_SPEC_CTRL_MSR is supported. Bit 7 of this MSR disables fast store forwarding predictor without disabling speculative store bypass", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "ipred_ctrl", + description: "MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "rrsba_ctrl", + description: "MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "ddp_ctrl", + description: "MSR bit IA32_SPEC_CTRL.DDPD_U", + bits_range: (3, 3), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "bhi_ctrl", + description: "MSR bit IA32_SPEC_CTRL.BHI_DIS_S", + bits_range: (4, 4), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "mcdt_no", + description: "MCDT mitigation not needed", + bits_range: (5, 5), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "uclock_disable", + description: "UC-lock disable is supported", + bits_range: (6, 6), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Direct Cache Access Information + // =================================================================================================================== + ( + Parameters { + leaf: 0x9, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + // MSR related + ValueDefinition { + short: "dca_cap_msr_value", + description: "Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1f8H)", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + // =================================================================================================================== + // Architectural Performance Monitoring + // =================================================================================================================== + // We will just zero out everything to do with PMU for CPU profiles and require equality for migration to be considered compatible (for the time being). + // TODO: Left for another day + ( + Parameters { + leaf: 0xa, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "pmu_version", + description: "Performance monitoring unit version ID", + bits_range: (0, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "pmu_n_gcounters", + description: "Number of general PMU counters per logical CPU", + bits_range: (8, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "pmu_gcounters_nbits", + description: "Bitwidth of PMU general counters", + bits_range: (16, 23), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "pmu_cpuid_ebx_bits", + description: "Length of leaf 0xa EBX bit vector", + bits_range: (24, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + ( + Parameters { + leaf: 0xa, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "no_core_cycle_evt", + description: "Core cycle event not available", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "no_insn_retired_evt", + description: "Instruction retired event not available", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "no_refcycle_evt", + description: "Reference cycles event not available", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "no_llc_ref_evt", + description: "LLC-reference event not available", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "no_llc_miss_evt", + description: "LLC-misses event not available", + bits_range: (4, 4), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "no_br_insn_ret_evt", + description: "Branch instruction retired event not available", + bits_range: (5, 5), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "no_br_mispredict_evt", + description: "Branch mispredict retired event not available", + bits_range: (6, 6), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "no_td_slots_evt", + description: "Topdown slots event not available", + bits_range: (7, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + ( + Parameters { + leaf: 0xa, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "pmu_fcounters_bitmap", + description: "Fixed-function PMU counters support bitmap", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xa, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "pmu_n_fcounters", + description: "Number of fixed PMU counters", + bits_range: (0, 4), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "pmu_fcounters_nbits", + description: "Bitwidth of PMU fixed counters", + bits_range: (5, 12), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "anythread_depr", + description: "AnyThread deprecation", + bits_range: (15, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + // =================================================================================================================== + // Extended Topology Enumeration + // =================================================================================================================== + + // Leaf 0xB must be set by CHV itself (and do all necessary checks) hence we can ignore checking for migration compatibility here + // TODO: Set by cloud hypervisor. Set this to 0 with a comment that CHV will set it instead. + ( + Parameters { + leaf: 0xb, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "x2apic_id_shift", + description: "Bit width of this level (previous levels inclusive)", + bits_range: (0, 4), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + // Set by VMM/user provided config + ( + Parameters { + leaf: 0xb, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "domain_lcpus_count", + description: "Logical CPUs count across all instances of this domain", + bits_range: (0, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + // Set by VMM/user provided config + ( + Parameters { + leaf: 0xb, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "domain_nr", + description: "This domain level (subleaf ID)", + bits_range: (0, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "domain_type", + description: "This domain type", + bits_range: (8, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + // Set by VMM/user provided config + ( + Parameters { + leaf: 0xb, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "x2apic_id", + description: "x2APIC ID of current logical CPU", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + // =================================================================================================================== + // Processor Extended State Enumeration Main Leaf + // =================================================================================================================== + // TODO: Figure out properly when to use Inherit vs Passthrough + // TODO: Check that CHV checks for migration compatibility here + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "xcr0_x87", + description: "XCR0.X87 (bit 0) supported", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xcr0_sse", + description: "XCR0.SEE (bit 1) supported", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xcr0_avx", + description: "XCR0.AVX (bit 2) supported", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MPX is deprecated + ValueDefinition { + short: "xcr0_mpx_bndregs", + description: "XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MPX is deprecated + ValueDefinition { + short: "xcr0_mpx_bndcsr", + description: "XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)", + bits_range: (4, 4), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xcr0_avx512_opmask", + description: "XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)", + bits_range: (5, 5), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xcr0_avx512_zmm_hi256", + description: "XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)", + bits_range: (6, 6), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xcr0_avx512_hi16_zmm", + description: "XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)", + bits_range: (7, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // MSR related + ValueDefinition { + short: "xcr0_ia32_xss", + description: "XCR0.IA32_XSS (bit 8) used for IA32_XSS", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xcr0_pkru", + description: "XCR0.PKRU (bit 9) supported (XSAVE PKRU registers)", + bits_range: (9, 9), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xcr0_ia32_xss_bits", + description: "XCR0.IA32_XSS (bit 10 - 16) used for IA32_XSS", + bits_range: (10, 16), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinition { + short: "xcr0_tileconfig", + description: "XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)", + bits_range: (17, 17), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinition { + short: "xcr0_tiledata", + description: "XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA)", + bits_range: (18, 18), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + // TODO: Check if CHV checks 0xd for migration compatibility already + ValueDefinition { + short: "xsave_sz_xcr0_enabled", + description: "XSAVE/XRSTOR area byte size, for XCR0 enabled features", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + // We don't need migration compatibility requirements here since we check for each individual state component + ValueDefinition { + short: "xsave_sz_max", + description: "XSAVE/XRSTOR area max byte size, all CPU features", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "xcr0_upper_bits", + description: "Reports the valid bit fields of the upper 32 bits of the XCR0 register", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + // =================================================================================================================== + // Processor Extended State Enumeration Sub-leaf 1 + // =================================================================================================================== + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "xsaveopt", + description: "XSAVEOPT instruction", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xsavec", + description: "XSAVEC instruction", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "xgetbv1", + description: "XGETBV instruction with ECX = 1", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Can this have security implications in terms of supervisor state getting exposed? + ValueDefinition { + short: "xsaves", + description: "XSAVES/XRSTORS instructions (and XSS MSR)", + bits_range: (3, 3), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bitssthat userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinition { + short: "xfd", + description: "Extended feature disable support", + bits_range: (4, 4), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + /*NOTE: This will depend on which CPU features (in CHV) are enabled and pre-computation can potentially lead to a combinatorial explosion. Luckily we can deal with each component (and its size) separately, hence we can just passthrough whatever we get from the host here.*/ + ValueDefinition { + short: "xsave_sz_xcr0_xmms_enabled", + description: "XSAVE area size, all XCR0 and IA32_XSS features enabled", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::ECX, + }, + /* Reports the supported bits of the lower IA32_XSS MSR. IA32_XSS[n] can be set to 1 only if ECX[n] = 1*/ + ValueDefinitions::new(&[ + // TODO: Not sure what profile policy to set here + ValueDefinition { + short: "xcr0_7bits", + description: "Used for XCR0", + bits_range: (0, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + // TODO: Not sure about the profile pilicy here + ValueDefinition { + short: "xss_pt", + description: "PT state, supported", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure what profile policy to set here + ValueDefinition { + short: "xcr0_bit9", + description: "Used for XCR0", + bits_range: (9, 9), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure about the profile pilicy here + ValueDefinition { + short: "xss_pasid", + description: "PASID state, supported", + bits_range: (10, 10), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure about the profile pilicy here + ValueDefinition { + short: "xss_cet_u", + description: "CET user state, supported", + bits_range: (11, 11), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure about the profile pilicy here + ValueDefinition { + short: "xss_cet_p", + description: "CET supervisor state, supported", + bits_range: (12, 12), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure about the profile pilicy here + ValueDefinition { + short: "xss_hdc", + description: "HDC state, supported", + bits_range: (13, 13), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure about the profile pilicy here + ValueDefinition { + short: "xss_uintr", + description: "UINTR state, supported", + bits_range: (14, 14), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure about the profile pilicy here + ValueDefinition { + short: "xss_lbr", + description: "LBR state, supported", + bits_range: (15, 15), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure about the profile pilicy here + ValueDefinition { + short: "xss_hwp", + description: "HWP state, supported", + bits_range: (16, 16), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Not sure what profile policy to set here + ValueDefinition { + short: "xcr0_bits", + description: "Used for XCR0", + bits_range: (17, 18), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EDX, + }, + /* Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32 ] can be set to 1 only if EDX[n] = 1*/ + ValueDefinitions::new(&[ + // TODO: Not sure what profile policy to set here + ValueDefinition { + short: "ia32_xss_upper", + description: " Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32 ] can be set to 1 only if EDX[n] = 1", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Processor Extended State Enumeration Sub-leaves + // =================================================================================================================== + + /* LEAF 0xd sub-leaf n >=2 : + If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 ≤ n ≤ 31) is + invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 ≤ n ≤ 63) + is invalid if sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32]. + + */ + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(2, 63), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "xsave_sz", + description: "Size of save area for subleaf-N feature, in bytes", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(2, 63), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "xsave_offset", + description: "Offset of save area for subleaf-N feature, in bytes", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(2, 63), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "is_xss_bit", + description: "Subleaf N describes an XSS bit, otherwise XCR0 bit", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "compacted_xsave_64byte_aligned", + description: "When compacted, subleaf-N feature XSAVE area is 64-byte aligned", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + // TODO: This may depend on the "amx" feature? + ValueDefinition { + short: "xfd_faulting", + description: "Indicates support for xfd faulting", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + // =================================================================================================================== + // Intel Resource Director Technology Monitoring Enumeration + // =================================================================================================================== + ( + Parameters { + leaf: 0xf, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "core_rmid_max", + description: "RMID max, within this core, all types (0-based)", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0xf, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + // TODO: Not sure about the short name (generated by the x86-cpuid.org tool). What is cqm_llc? + ValueDefinition { + short: "cqm_llc", + description: "Supports L3 Cache Intel RDT Monitoring if 1", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Intel Resource Director Technology Monitoring Enumeration Sub-leaf 1 + // =================================================================================================================== + ( + Parameters { + leaf: 0xf, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EAX, + }, + // TODO: Not sure about the migration policy + ValueDefinitions::new(&[ + ValueDefinition { + short: "l3c_qm_bitwidth", + description: "L3 QoS-monitoring counter bitwidth (24-based)", + bits_range: (0, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "l3c_qm_overflow_bit", + description: "QM_CTR MSR bit 61 is an overflow bit", + bits_range: (8, 8), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "l3c_qm_non_cpu_agent", + description: "If 1, indicates the presence of non-CPU agent Intel RDT CTM support", + bits_range: (9, 9), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "l3c_qm_non_cpu_agent", + description: "If 1, indicates the presence of non-CPU agent Intel RDT MBM support", + bits_range: (10, 10), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + ( + Parameters { + leaf: 0xf, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EBX, + }, + // TODO: Not sure about the migration policy + ValueDefinitions::new(&[ValueDefinition { + short: "l3c_qm_conver_factor", + description: "QM_CTR MSR conversion factor to bytes", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xf, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::ECX, + }, + // TODO: Not sure about the migration policy + ValueDefinitions::new(&[ValueDefinition { + short: "l3c_qm_rmid_max", + description: "L3 QoS-monitoring max RMID", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0xf, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "cqm_occup_llc", + description: "L3 QoS occupancy monitoring supported", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cqm_mbm_total", + description: "L3 QoS total bandwidth monitoring supported", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cqm_mbm_local", + description: "L3 QoS local bandwidth monitoring supported", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration + // =================================================================================================================== + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + //TODO: These features may be good for increased performance. Perhaps there needs to be some mechanism to opt-in for non-host CPU profiles? + ValueDefinitions::new(&[ + ValueDefinition { + short: "cat_l3", + description: "L3 Cache Allocation Technology supported", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "cat_l2", + description: "L2 Cache Allocation Technology supported", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "mba", + description: "Memory Bandwidth Allocation supported", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 1) + // =================================================================================================================== + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cat_cbm_len", + description: "L3_CAT capacity bitmask length, minus-one notation", + bits_range: (0, 4), + policy: ProfilePolicy::Passthrough, /* TODO: ? */ + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, /* TODO: ? */ + }]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cat_units_bitmap", + description: "L3_CAT bitmap of allocation units", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, /* TODO: ? */ + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, /* TODO: ? */ + }]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::ECX, + }, + //TODO: These feature may be good for increased performance. Perhaps there needs to be some mechanism to opt-in for non-host CPU profiles? + ValueDefinitions::new(&[ + ValueDefinition { + short: "l3_cat_non_cpu_agents", + description: "L3_CAT for non-CPU agent is supported", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cdp_l3", + description: "L3/L2_CAT CDP (Code and Data Prioritization)", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cat_sparse_1s", + description: "L3/L2_CAT non-contiguous 1s value supported", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EDX, + }, + // TODO: We might need some way to opt in to use Intel cache allocation technology in guests with non-host CPU profiles. + ValueDefinitions::new(&[ValueDefinition { + short: "cat_cos_max", + description: "Highest COS number supported for this ResID", + bits_range: (0, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 2) + // =================================================================================================================== + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(2, 2), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cat_cbm_len", + description: "L2_CAT capacity bitmask length, minus-one notation", + bits_range: (0, 4), + policy: ProfilePolicy::Passthrough, /* TODO: ? */ + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, /* TODO: ? */ + }]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(2, 2), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cat_units_bitmap", + description: "L2_CAT bitmap of allocation units", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, /* TODO: ? */ + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, /* TODO: ? */ + }]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(2, 2), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cat_cos_max", + description: "Highest COS number supported for this ResID", + bits_range: (0, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(2, 2), + register: CpuidReg::ECX, + }, + // TODO: We might need some way to opt in to use Intel cache allocation technology in guests with non-host CPU profiles. + ValueDefinitions::new(&[ + ValueDefinition { + short: "cdp_l2", + description: "L2_CAT CDP (Code and Data Prioritization)", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "cat_sparse_1s", + description: "L2_CAT non-contiguous 1s value supported", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 3) + // =================================================================================================================== + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(3, 3), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + // TODO: We might need some way to opt in to use Intel MBA technology in guests with non-host CPU profiles. + ValueDefinition { + short: "mba_max_delay", + description: "Max MBA throttling value; minus-one notation", + bits_range: (0, 11), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }, + ]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(3, 3), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "per_thread_mba", + description: "Per-thread MBA controls are supported", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mba_delay_linear", + description: "Delay values are linear", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(3, 3), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "mba_cos_max", + description: "MBA max Class of Service supported", + bits_range: (0, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + // =================================================================================================================== + // Intel Resource Director Technology Allocation Enumeration Sub-leaf (ECX = ResID = 5) + // =================================================================================================================== + // + // TODO: We may want to have some way to opt-in to use Intel RDT for guests with non-host CPU profiles. + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(5, 5), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "core_max_throttle", + description: "Max Core throttling level supported by the corresponding ResID", + bits_range: (0, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }, + // TODO: Not sure about the short name + ValueDefinition { + short: "core_scope", + description: "If 1, indicates the logical processor scope of the IA32_QoS_Core_BW_Thrtl_n MSRs. Other values are reserved", + bits_range: (8, 11), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(5, 5), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cba_delay_linear", + description: "The response of the bandwidth control is approximately linear", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0x10, + sub_leaf: RangeInclusive::new(5, 5), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "core_cos_max", + description: "Core max Class of Service supported", + bits_range: (0, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + // SGX is already disabled and deprecated so we don't need to worry about leaf 0x12 and its subleaves + + // =================================================================================================================== + // Intel Processor Trace Enumeration Main Leaf + // =================================================================================================================== + ( + Parameters { + leaf: 0x14, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "pt_max_subleaf", + description: "Maximum leaf 0x14 subleaf", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x14, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "cr3_filtering", + description: "IA32_RTIT_CR3_MATCH is accessible", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "psb_cyc", + description: "Configurable PSB and cycle-accurate mode", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ip_filtering", + description: "IP/TraceStop filtering; Warm-reset PT MSRs preservation", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mtc_timing", + description: "MTC timing packet; COFI-based packets suppression", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ptwrite", + description: "PTWRITE support", + bits_range: (4, 4), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "power_event_trace", + description: "Power Event Trace support", + bits_range: (5, 5), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "psb_pmi_preserve", + description: "PSB and PMI preservation support", + bits_range: (6, 6), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "event_trace", + description: "Event Trace packet generation through IA32_RTIT_CTL.EventEn", + bits_range: (7, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "tnt_disable", + description: "TNT packet generation disable through IA32_RTIT_CTL.DisTNT", + bits_range: (8, 8), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x14, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "topa_output", + description: "ToPA output scheme support", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "topa_multiple_entries", + description: "ToPA tables can hold multiple entries", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "single_range_output", + description: "Single-range output scheme supported", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "trance_transport_output", + description: "Trace Transport subsystem output support", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ip_payloads_lip", + description: "IP payloads have LIP values (CS base included)", + bits_range: (31, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Intel Processor Trace Enumeration Sub-leaf 1 + // =================================================================================================================== + ( + Parameters { + leaf: 0x14, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "num_address_ranges", + description: "Filtering number of configurable Address Ranges", + bits_range: (0, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "mtc_periods_bmp", + description: "Bitmap of supported MTC period encodings", + bits_range: (16, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x14, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "cycle_thresholds_bmp", + description: "Bitmap of supported Cycle Threshold encodings", + bits_range: (0, 15), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "psb_periods_bmp", + description: "Bitmap of supported Configurable PSB frequency encodings", + bits_range: (16, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Time Stamp Counter and Core Crystal Clock Information + // =================================================================================================================== + + // TODO: Apparently these clock frequencies can be set by KVM. Would it perhaps make sense to set them to the same as the physical CPU the profile corresponds to? Or is it best to just pass through whatever we get from the host here? + ( + Parameters { + leaf: 0x15, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "tsc_denominator", + description: "Denominator of the TSC/'core crystal clock' ratio", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x15, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "tsc_numerator", + description: "Numerator of the TSC/'core crystal clock' ratio", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x15, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_crystal_hz", + description: "Core crystal clock nominal frequency, in Hz", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + // =================================================================================================================== + // Processor Frequency Information + // =================================================================================================================== + ( + Parameters { + leaf: 0x16, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_base_mhz", + description: "Processor base frequency, in MHz", + bits_range: (0, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x16, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_max_mhz", + description: "Processor max frequency, in MHz", + bits_range: (0, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x16, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "bus_mhz", + description: "Bus reference frequency, in MHz", + bits_range: (0, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + // =================================================================================================================== + // System-On-Chip Vendor Attribute Enumeration Main Leaf + // =================================================================================================================== + + // System-On-Chip should probably not be supported for CPU profiles for the foreseeable feature. + ( + Parameters { + leaf: 0x17, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "soc_max_subleaf", + description: "Maximum leaf 0x17 subleaf", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + // =================================================================================================================== + // Deterministic Address Translation Parameters + // =================================================================================================================== + + // TODO: Check that we can indeed ignore migration compatibility checks for this leaf + ( + Parameters { + leaf: 0x18, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "tlb_max_subleaf", + description: "Maximum leaf 0x18 subleaf", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x18, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "tlb_4k_page", + description: "TLB 4KB-page entries supported", + bits_range: (0, 0), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "tlb_2m_page", + description: "TLB 2MB-page entries supported", + bits_range: (1, 1), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "tlb_4m_page", + description: "TLB 4MB-page entries supported", + bits_range: (2, 2), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "tlb_1g_page", + description: "TLB 1GB-page entries supported", + bits_range: (3, 3), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "hard_partitioning", + description: "(Hard/Soft) partitioning between logical CPUs sharing this structure", + bits_range: (8, 10), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "n_way_associative", + description: "Ways of associativity", + bits_range: (16, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x18, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "n_sets", + description: "Number of sets", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x18, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "tlb_type", + description: "Translation cache type (TLB type)", + bits_range: (0, 4), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "tlb_cache_level", + description: "Translation cache level (1-based)", + bits_range: (5, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "is_fully_associative", + description: "Fully-associative structure", + bits_range: (8, 8), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "tlb_max_addressible_ids", + description: "Max number of addressable IDs for logical CPUs sharing this TLB - 1", + bits_range: (14, 25), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + // We don't support key locker for now (leaf 0x19): Hence we zero out leaf 0x19 for CPU profiles (and don't check it for migration compatibility) + // We zero LEAF 0x1A (Native Model ID Enumeration) out for CPU profiles (and don't check it for migration compatibility) + // LEAF 0x1B (PCONFIG) is zeroed out for CPU profiles for now (and we don't check it for migration compatibility) + + // =================================================================================================================== + // Last Branch Records Information + // =================================================================================================================== + ( + Parameters { + leaf: 0x1c, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "lbr_depth_8", + description: "Max stack depth (number of LBR entries) = 8", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_depth_16", + description: "Max stack depth (number of LBR entries) = 16", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_depth_24", + description: "Max stack depth (number of LBR entries) = 24", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_depth_32", + description: "Max stack depth (number of LBR entries) = 32", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_depth_40", + description: "Max stack depth (number of LBR entries) = 40", + bits_range: (4, 4), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_depth_48", + description: "Max stack depth (number of LBR entries) = 48", + bits_range: (5, 5), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_depth_56", + description: "Max stack depth (number of LBR entries) = 56", + bits_range: (6, 6), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_depth_64", + description: "Max stack depth (number of LBR entries) = 64", + bits_range: (7, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_deep_c_reset", + description: "LBRs maybe cleared on MWAIT C-state > C1", + bits_range: (30, 30), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_ip_is_lip", + description: "LBR IP contain Last IP, otherwise effective IP", + bits_range: (31, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x1c, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "lbr_cpl", + description: "CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_branch_filter", + description: "Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_call_stack", + description: "Call-stack mode (IA32_LBR_CTL[3] = 1) supported", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x1c, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "lbr_mispredict", + description: "Branch misprediction bit supported (IA32_LBR_x_INFO[63])", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_timed_lbr", + description: "Timed LBRs (CPU cycles since last LBR entry) supported", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_branch_type", + description: "Branch type field (IA32_LBR_INFO_x[59:56]) supported", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_events_gpc_bmp", + description: "LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters", + bits_range: (16, 19), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Tile Information Main Leaf + // =================================================================================================================== + // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. + ( + Parameters { + leaf: 0x1d, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "amx_max_palette", + description: "Highest palette ID / subleaf ID", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + // =================================================================================================================== + // Tile Palette 1 Sub-leaf + // =================================================================================================================== + // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. + ( + Parameters { + leaf: 0x1d, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "amx_palette_size", + description: "AMX palette total tiles size, in bytes", + bits_range: (0, 15), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, /* require equality as this can impact XSAVE */ + }, + ValueDefinition { + short: "amx_tile_size", + description: "AMX single tile's size, in bytes", + bits_range: (16, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + ( + Parameters { + leaf: 0x1d, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "amx_tile_row_size", + description: "AMX tile single row's size, in bytes", + bits_range: (0, 15), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "amx_palette_nr_tiles", + description: "AMX palette number of tiles", + bits_range: (16, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, /* Can affect XSAVE hence require equality here */ + }, + ]), + ), + ( + Parameters { + leaf: 0x1d, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "amx_tile_nr_rows", + description: "AMX tile max number of rows", + bits_range: (0, 15), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + // =================================================================================================================== + // TMUL Information Main Leaf + // =================================================================================================================== + // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. + ( + Parameters { + leaf: 0x1e, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "tmul_info_max", + description: "Reports the maximum number of sub-leaves that are supported in leaf 0x1e", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x1e, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "tmul_maxk", + description: "TMUL unit maximum height, K (rows or columns)", + bits_range: (0, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, /* TODO: OR should we go with Eq? */ + }, + ValueDefinition { + short: "tmul_maxn", + description: "TMUL unit maximum SIMD dimension, N (column bytes)", + bits_range: (8, 23), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, /* TODO: Or should we go with Eq? */ + }, + ]), + ), + // =================================================================================================================== + // TMUL Information Sub-leaf 1 + // =================================================================================================================== + // NOTE: AMX is opt-in, but there are no problems with inheriting these values. The CHV will take care of zeroing out the bits userspace applications should check for if the user did not opt-in to amx. + ( + Parameters { + leaf: 0x1e, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EAX, + }, + // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. + ValueDefinitions::new(&[ + ValueDefinition { + short: "amx_int8", + description: "If 1, the processor supports tile computational operations on 8-bit integers", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_bf16", + description: "If 1, the processor supports tile computational operations on bfloat16 numbers", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_complex", + description: "If 1, the processor supports the AMX-COMPLEX instructions", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_fp16", + description: "If 1, the processor supports tile computational operations on FP16 numbers", + bits_range: (3, 3), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_fp8", + description: "If 1, the processor supports tile computational operations on FP8 numbers", + bits_range: (4, 4), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_transpose", + description: "If 1, the processor supports the AMX-TRANSPOSE instructions", + bits_range: (5, 5), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_tf32", + description: "If 1, the processor supports the AMX-TF32 (FP19) instructions", + bits_range: (6, 6), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_avx512", + description: "If 1, the processor supports the AMX-AVX512 instructions", + bits_range: (7, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "amx_movrs", + description: "If 1, the processor supports the AMX-MOVRS instructions", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // V2 Extended Topology Enumeration + // =================================================================================================================== + + // We can ignore checking migration compatibility for the 0x1f leaf because these values must be set by CHV itself which should do all relevant checks + ( + Parameters { + leaf: 0x1f, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "x2apic_id_shift", + description: "Bit width of this level (previous levels inclusive)", + bits_range: (0, 4), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x1f, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "domain_lcpus_count", + description: "Logical CPUs count across all instances of this domain", + bits_range: (0, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x1f, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "domain_level", + description: "This domain level (subleaf ID)", + bits_range: (0, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "domain_type", + description: "This domain type", + bits_range: (8, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x1f, + sub_leaf: RangeInclusive::new(0, u32::MAX), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "x2apic_id", + description: "x2APIC ID of current logical CPU", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + // =================================================================================================================== + // Processor History Reset + // =================================================================================================================== + ( + Parameters { + leaf: 0x20, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "hreset_nr_subleaves", + description: "CPUID 0x20 max subleaf + 1", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x20, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "hreset_thread_director", + description: "HRESET of Intel thread director is supported", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + // =================================================================================================================== + // TDX + // =================================================================================================================== + + // TDX is not supported by CPU profiles for now. We just zero out this leaf for CPU profiles for the time being. + ( + Parameters { + leaf: 0x21, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "tdx_vendorid_0", + description: "TDX vendor ID string bytes 0 - 3", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0x21, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "tdx_vendorid_2", + description: "CPU vendor ID string bytes 8 - 11", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0x21, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "tdx_vendorid_1", + description: "CPU vendor ID string bytes 4 - 7", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + // =================================================================================================================== + // Architectural Performance Monitoring Extended Main Leaf + // =================================================================================================================== + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "subleaf_0", + description: "If 1, subleaf 0 exists", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "subleaf_1", + description: "If 1, subleaf 1 exists", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "subleaf_2", + description: "If 1, subleaf 2 exists", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "subleaf_3", + description: "If 1, subleaf 3 exists", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "subleaf_4", + description: "If 1, subleaf 4 exists", + bits_range: (4, 4), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "subleaf_5", + description: "If 1, subleaf 5 exists. The processor suppots Architectural PEBS. The IA32_PEBS_BASE and IA32_PEBS_INDEX MSRs exist", + bits_range: (5, 5), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "unitmask2", + description: "IA32_PERFEVTSELx MSRs UnitMask2 is supported", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "eq_bit", + description: "equal flag in the IA32_PERFEVTSELx MSR is supported", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "RDPMC_USR_DISABLE", + description: "RDPMC_USR_DISABLE", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + // TODO: Not sure about migration compatibility + ValueDefinition { + short: "num_slots_per_cycle", + description: "Number of slots per cycle. This number can be multiplied by the number of cycles (from CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.CORE or IA32_FIXED_CTR1) to determine the total number of slots", + bits_range: (0, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 1 + // =================================================================================================================== + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "pmu_gp_counters_bitmap", + description: "General-purpose PMU counters bitmap", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(1, 1), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "pmu_f_counters_bitmap", + description: "Fixed PMU counters bitmap", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 2 + // =================================================================================================================== + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(2, 2), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "pmu_acr_bitmap", + description: "Bitmap of Auto Counter Reload (ACR) general-purpose counters that can be reloaded", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 3 + // =================================================================================================================== + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(3, 3), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "core_cycles_evt", + description: "Core cycles event supported", + bits_range: (0, 0), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "insn_retired_evt", + description: "Instructions retired event supported", + bits_range: (1, 1), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "ref_cycles_evt", + description: "Reference cycles event supported", + bits_range: (2, 2), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "llc_refs_evt", + description: "Last-level cache references event supported", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "llc_misses_evt", + description: "Last-level cache misses event supported", + bits_range: (4, 4), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "br_insn_ret_evt", + description: "Branch instruction retired event supported", + bits_range: (5, 5), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "br_mispr_evt", + description: "Branch mispredict retired event supported", + bits_range: (6, 6), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "td_slots_evt", + description: "Topdown slots event supported", + bits_range: (7, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "td_backend_bound_evt", + description: "Topdown backend bound event supported", + bits_range: (8, 8), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "td_bad_spec_evt", + description: "Topdown bad speculation event supported", + bits_range: (9, 9), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "td_frontend_bound_evt", + description: "Topdown frontend bound event supported", + bits_range: (10, 10), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "td_retiring_evt", + description: "Topdown retiring event support", + bits_range: (11, 11), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lbr_inserts", + description: "LBR support", + bits_range: (12, 12), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 4 + // =================================================================================================================== + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(4, 4), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "allow_in_record", + description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition { + short: "cntr", + description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", + bits_range: (0, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition { + short: "lbr", + description: "LBR group and both bits [41:40] are available", + bits_range: (8, 9), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition { + short: "xer", + description: "These bits correspond to XER group bits [55:49]", + bits_range: (17, 23), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "grp", + description: "If 1, the GRP group is available", + bits_range: (29, 29), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "aux", + description: "If 1, the AUX group is available", + bits_range: (30, 30), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(4, 4), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "allow_in_record", + description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", + bits_range: (3, 3), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition { + short: "cntr", + description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", + bits_range: (0, 7), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition { + short: "lbr", + description: "LBR group and both bits [41:40] are available", + bits_range: (8, 9), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + // TODO: Should the migration compatibility check rather be CintainsBits? + ValueDefinition { + short: "xer", + description: "These bits correspond to XER group bits [55:49]", + bits_range: (17, 23), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "grp", + description: "If 1, the GRP group is available", + bits_range: (29, 29), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "aux", + description: "If 1, the AUX group is available", + bits_range: (30, 30), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // =================================================================================================================== + // Architectural Performance Monitoring Extended Sub-leaf 5 + // =================================================================================================================== + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(5, 5), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "architectural_pebs_counters", + description: "General-purpose counters support Architectural PEBS. Bit vector of general-purpose counters for which the Architectural PEBS mechanism is available", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(5, 5), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "pebs_pdist_counters", + description: "General-purpose counters for which PEBS support PDIST", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(5, 5), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "pebs_fixed_function_counters", + description: "Fixed-function counters support Architectural PEBS. Bit vector of fixed-function counters for which the Architectural PEBS mechanism is available. If ECX[x] == 1, then the IA32_PMC_FXm_CFG_C MSR is available, and PEBS is supported", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + ( + Parameters { + leaf: 0x23, + sub_leaf: RangeInclusive::new(5, 5), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "pebs_fixed_function_pdist_counters", + description: "Fixed-function counters for which PEBS supports PDIST", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + // =================================================================================================================== + // Converged Vector ISA Main Leaf + // =================================================================================================================== + ( + Parameters { + leaf: 0x24, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "converged_vector_isa_max_sub_leaves", + description: "Reports the maximum number of sub-leaves that are supported in leaf 0x24", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x24, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "avx_10_version", + description: "Reports the intel AVX10 Converged Vector ISA version", + bits_range: (0, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }, + ValueDefinition { + short: "avx_10_lengths", + description: "Reserved at 111", + bits_range: (0, 7), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + // Hypervisor reserved CPUID leaves are set elsewhere + + // =================================================================================================================== + // Extended Function CPUID Information + // =================================================================================================================== + ( + Parameters { + leaf: 0x80000000, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "max_ext_leaf", + description: "Maximum extended CPUID leaf supported", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, + }]), + ), + ( + Parameters { + leaf: 0x80000000, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_vendorid_0", + description: "Vendor ID string bytes 0 - 3", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000000, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_vendorid_2", + description: "Vendor ID string bytes 8 - 11", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000000, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_vendorid_1", + description: "Vendor ID string bytes 4 - 7", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000001, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + // TODO: Would inherit be better than passthrough? Currently CHV manually copies these over from the host ... + ValueDefinitions::new(&[ + ValueDefinition { + short: "e_stepping_id", + description: "Stepping ID", + bits_range: (0, 3), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "e_base_model", + description: "Base processor model", + bits_range: (4, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "e_base_family", + description: "Base processor family", + bits_range: (8, 11), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "e_base_type", + description: "Base processor type (Transmeta)", + bits_range: (12, 13), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "e_ext_model", + description: "Extended processor model", + bits_range: (16, 19), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "e_ext_family", + description: "Extended processor family", + bits_range: (20, 27), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x80000001, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "brand_id", + description: "Brand ID", + bits_range: (0, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "pkg_type", + description: "Package type", + bits_range: (28, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x80000001, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "lahf_lm", + description: "LAHF and SAHF in 64-bit mode", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lzcnt", + description: "LZCNT advanced bit manipulation", + bits_range: (5, 5), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "prefetchw", + description: "3DNow PREFETCH/PREFETCHW support", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x80000001, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "syscall", + description: "SYSCALL and SYSRET instructions", + bits_range: (11, 11), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "nx", + description: "Execute Disable Bit available", + bits_range: (20, 20), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "pdpe1gb", + description: "1-GB large page support", + bits_range: (26, 26), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + // TODO: Should this perhaps be overwritten to 0 and require opt-in via a feature? + ValueDefinition { + short: "rdtscp", + description: "RDTSCP instruction and IA32_TSC_AUX are available", + bits_range: (27, 27), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ValueDefinition { + short: "lm", + description: "Long mode (x86-64, 64-bit support)", + bits_range: (29, 29), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + // TODO: Would it be better to inherit these for the CPU profile (or zero it out entirely?) + ( + Parameters { + leaf: 0x80000002, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_0", + description: "CPU brand ID string, bytes 0 - 3", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000002, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_1", + description: "CPU brand ID string, bytes 4 - 7", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000002, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_2", + description: "CPU brand ID string, bytes 8 - 11", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000002, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_3", + description: "CPU brand ID string, bytes 12 - 15", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000003, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_4", + description: "CPU brand ID string bytes, 16 - 19", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000003, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_5", + description: "CPU brand ID string bytes, 20 - 23", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000003, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_6", + description: "CPU brand ID string bytes, 24 - 27", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000003, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_7", + description: "CPU brand ID string bytes, 28 - 31", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000004, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_8", + description: "CPU brand ID string, bytes 32 - 35", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000004, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_9", + description: "CPU brand ID string, bytes 36 - 39", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000004, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_10", + description: "CPU brand ID string, bytes 40 - 43", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000004, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "cpu_brandid_11", + description: "CPU brand ID string, bytes 44 - 47", + bits_range: (0, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }]), + ), + ( + Parameters { + leaf: 0x80000006, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "l2_line_size", + description: "L2 cache line size, in bytes", + bits_range: (0, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "l2_nlines", + description: "L2 cache number of lines per tag", + bits_range: (8, 11), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "l2_assoc", + description: "L2 cache associativity", + bits_range: (12, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "l2_size_kb", + description: "L2 cache size, in KB", + bits_range: (16, 31), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + // EAX, EBX and ECX of 0x8000_0007 are all reserved (=0) on Intel + ( + Parameters { + leaf: 0x80000007, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ + // TODO: We may want some mechanism to let users opt-in to using an invariant TSC provided by the hardware (when available). + // TODO: Probably unconditionally set by CHV + ValueDefinition { + short: "constant_tsc", + description: "TSC ticks at constant rate across all P and C states", + bits_range: (8, 8), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }, + ]), + ), + ( + Parameters { + leaf: 0x80000008, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "phys_addr_bits", + description: "Max physical address bits", + bits_range: (0, 7), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "virt_addr_bits", + description: "Max virtual address bits", + bits_range: (8, 15), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ValueDefinition { + short: "guest_phys_addr_bits", + description: "Max nested-paging guest physical address bits", + bits_range: (16, 23), + policy: ProfilePolicy::Passthrough, + migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, + }, + ]), + ), + ( + Parameters { + leaf: 0x80000008, + sub_leaf: RangeInclusive::new(0, 0), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "wbnoinvd", + description: "WBNOINVD supported", + bits_range: (9, 9), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, + }]), + ), + ]) +}; diff --git a/arch/src/x86_64/cpuid_definitions/mod.rs b/arch/src/x86_64/cpuid_definitions/mod.rs index 5af714fd54..39779cb544 100644 --- a/arch/src/x86_64/cpuid_definitions/mod.rs +++ b/arch/src/x86_64/cpuid_definitions/mod.rs @@ -58,7 +58,7 @@ pub enum MigrationCompatibilityRequirement { } /// A description of a range of bits in a register populated by the CPUID instruction with specific parameters. -#[derive(Clone, Copy)] +#[derive(Clone, Copy, Debug)] pub struct ValueDefinition { /// A short name for the value obtainable through CPUID pub short: &'static str, diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index 414b88270b..5090bf1c4e 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -530,7 +530,45 @@ impl CpuidFeatureEntry { let src_vm_feature_bits_only = different_feature_bits & src_vm_feature; let is_subset = src_vm_feature_bits_only == 0; if !is_subset { - todo!(); + // The check failed: We give precise information per missing bit + let mut bitmask = src_vm_feature_bits_only; + while bitmask != 0 { + let idx = bitmask.trailing_zeros(); + let lsb = bitmask & bitmask.wrapping_neg(); + bitmask ^= lsb; + error!( + "bit number: {} in leaf: {:#02x}, sub-leaf: {:#02x}, register: {:?}, is only present in the source vm cpuid", + idx, entry.function, entry.index, entry.feature_reg + ); + // Log more information about this feature, assuming an Intel CPU for now + // TODO: Check against the CPU vendor before using the intel definitions + if let Some((_, defs)) = + cpuid_definitions::intel::INTEL_CPUID_DEFINITIONS + .0 + .iter() + .find(|(param, _)| { + (param.leaf == entry.function) + && (param.sub_leaf.contains(&entry.index)) + }) + { + for def in defs.as_slice() { + // TODO: Might indeed be better to just use a normal range for the bits_range as per + // review comment(s) + if (u32::from(def.bits_range.0)) <= idx + && (idx <= u32::from(def.bits_range.1)) + { + info!( + "On Intel processors bit: {} in leaf: {:#02x}, sub-leaf: {:#02x}, register: {:?}, corresponds to value definition: {:?} ", + idx, + entry.function, + entry.index, + entry.feature_reg, + def + ); + } + } + } + } } is_subset } From 5427ca1944b80ae956362281ee23380a81cdee47 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 17 Nov 2025 15:56:50 +0100 Subject: [PATCH 33/75] Remove dev profile --- arch/src/x86_64/cpu_profile.rs | 21 ------------------- arch/src/x86_64/cpu_profiles/dev_profile.json | 1 - 2 files changed, 22 deletions(-) delete mode 100644 arch/src/x86_64/cpu_profiles/dev_profile.json diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index fef7167a4b..b8a87098d7 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -11,11 +11,6 @@ use serde::{Deserialize, Serialize}; pub enum CpuProfile { #[default] Host, - /// Work in progress profile to test on when developing. - //TODO: Replace this with a feature gated x86-64-v1 variant that all x86_64 host's should satisfy. - // Having such a variant would be good for testing in CI, but should not become part of the shipped - // cloud hypervisor. - DevLaptop, Skylake, SapphireRapids, } @@ -26,22 +21,6 @@ impl CpuProfile { pub(in crate::x86_64) fn data(&self) -> Option { match self { Self::Host => None, - Self::DevLaptop => { - /* - We only use this for local testing when developing the PoC. We should - introduce some proper CPU profiles ASAP! We should also have a better - profile for testing that can run in CI one idea would be running the - profile generation CLI on a qemu VM configured for the kvm64 CPU model or - something like that. - */ - Some( - serde_json::from_slice(include_bytes!("cpu_profiles/dev_profile.json")) - .inspect_err(|e| { - error!("BUG: could not deserialize CPU profile. Got error: {:?}", e) - }) - .expect("should be able to deserialize pre-generated data"), - ) - } Self::Skylake => Some( serde_json::from_slice(include_bytes!("cpu_profiles/skylake.json")) .inspect_err(|e| { diff --git a/arch/src/x86_64/cpu_profiles/dev_profile.json b/arch/src/x86_64/cpu_profiles/dev_profile.json deleted file mode 100644 index 1484ce6bcc..0000000000 --- a/arch/src/x86_64/cpu_profiles/dev_profile.json +++ /dev/null @@ -1 +0,0 @@ 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Quick fix: Overwrite policies for x2APIC and APIC on chip --- arch/src/x86_64/cpuid_definitions/intel.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index fd796f6152..83031f68e9 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -315,7 +315,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { short: "x2apic", description: "X2APIC support", bits_range: (21, 21), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Overwrite(1), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -468,7 +468,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { short: "apic", description: "APIC on-chip", bits_range: (9, 9), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Overwrite(1), migration_compatibility_req: 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Error::SetSupportedCpusFailed(e.into()))?; diff --git a/hypervisor/src/kvm/mod.rs b/hypervisor/src/kvm/mod.rs index eea499da51..891d2c9649 100644 --- a/hypervisor/src/kvm/mod.rs +++ b/hypervisor/src/kvm/mod.rs @@ -1869,6 +1869,7 @@ impl cpu::Vcpu for KvmVcpu { /// X86 specific call to setup the CPUID registers. /// fn set_cpuid2(&self, cpuid: &[CpuIdEntry]) -> cpu::Result<()> { + info!("setting cpuid2"); let cpuid: Vec = cpuid.iter().map(|e| (*e).into()).collect(); let kvm_cpuid = ::from_entries(&cpuid) diff --git a/vmm/src/cpu.rs b/vmm/src/cpu.rs index 416bce5d45..a9cb165c77 100644 --- a/vmm/src/cpu.rs +++ b/vmm/src/cpu.rs @@ -848,6 +848,7 @@ impl CpuManager { let state: CpuState = snapshot.to_state().map_err(|e| { Error::VcpuCreate(anyhow!("Could not get vCPU state from snapshot {:?}", e)) })?; + info!("Going to set cpuid in create_vcpu"); vcpu.vcpu .set_state(&state) .map_err(|e| Error::VcpuCreate(anyhow!("Could not set the vCPU state {:?}", e)))?; From b16aae5a1b19f1c052974a3b0e77d65fc669cdec Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 25 Nov 2025 11:54:31 +0100 Subject: [PATCH 39/75] Zero out TSX --- arch/src/x86_64/cpuid_definitions/intel.rs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index 83031f68e9..dcac016a25 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -1341,7 +1341,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { short: "hle", description: "Hardware Lock Elision", bits_range: (4, 4), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1397,12 +1397,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, - // This is TSX related from what I can tell. TSX is riddled with CVEs: Consider two profiles (one with it disabled) or an opt-in/out feature. + // This is TSX related. TSX is riddled with CVEs: Consider two profiles (one with it disabled) or an opt-in/out feature. ValueDefinition { short: "rtm", description: "Intel restricted transactional memory", bits_range: (11, 11), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1813,14 +1813,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { short: "rtm_always_abort", description: "XBEGIN (RTM transaction) always aborts", bits_range: (11, 11), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "tsx_force_abort", description: "MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported", bits_range: (13, 13), - policy: ProfilePolicy::Inherit, + policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1837,7 +1837,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, - // TODO: This is TSX related which is riddled with CVEs. We should carefully decide what to do with regards to this feature. + // TODO: This is TSX related which is riddled with CVEs. We could consider an additional profile enabling TSX in the future, but we leave it out for now. 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\ No newline at end of file From 11919e00b9c4b9a29edb8f6a1963fd6fc2a41e67 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 27 Nov 2025 19:30:04 +0100 Subject: [PATCH 41/75] Hex encoded serialization --- arch/src/x86_64/cpu_profile.rs | 9 +++++++- arch/src/x86_64/cpuid_definitions/mod.rs | 27 ++++++++++++++++++++++-- 2 files changed, 33 insertions(+), 3 deletions(-) diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index f97fdd7fb2..4c58ced8f5 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -1,4 +1,7 @@ -use crate::x86_64::{CpuidReg, cpuid_definitions::Parameters}; +use crate::x86_64::{ + CpuidReg, + cpuid_definitions::{Parameters, deserialize_from_hex, serialize_as_hex}, +}; use hypervisor::arch::x86::CpuIdEntry; use hypervisor::{CpuVendor, HypervisorType}; use serde::{Deserialize, Serialize}; @@ -92,8 +95,12 @@ incompatible with live migration of course). /// Used for adjusting an entire cpuid output register (EAX, EBX, ECX or EDX) #[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)] pub(super) struct CpuidOutputRegisterAdjustments { + #[serde(serialize_with = "serialize_as_hex")] + #[serde(deserialize_with = "deserialize_from_hex")] pub(in crate::x86_64) replacements: u32, /// Used to zero out the area `replacements` occupy. This mask is not necessarily !replacements, as replacements may pack values of different types (i.e. it is wrong to think of it as a bitset conceptually speaking). + #[serde(serialize_with = "serialize_as_hex")] + #[serde(deserialize_with = "deserialize_from_hex")] pub(in crate::x86_64) mask: u32, } impl CpuidOutputRegisterAdjustments { diff --git a/arch/src/x86_64/cpuid_definitions/mod.rs b/arch/src/x86_64/cpuid_definitions/mod.rs index 39779cb544..5d6dd68e85 100644 --- a/arch/src/x86_64/cpuid_definitions/mod.rs +++ b/arch/src/x86_64/cpuid_definitions/mod.rs @@ -1,16 +1,39 @@ +use serde::{Deserialize, Deserializer, Serialize, Serializer}; +use std::io::Write; use std::ops::RangeInclusive; -use serde::{Deserialize, Serialize}; - use crate::x86_64::CpuidReg; pub mod hypervisor; pub mod intel; +pub(in crate::x86_64) fn serialize_as_hex( + input: &u32, + serializer: S, +) -> Result { + // two bytes for "0x" prefix and eight for the hex encoded number + let mut buffer = [0_u8; 10]; + let _ = write!(&mut buffer[..], "{:#010x}", input); + let str = core::str::from_utf8(&buffer[..]) + .expect("the buffer should be filled with valid UTF-8 bytes"); + serializer.serialize_str(str) +} + +pub(in crate::x86_64) fn deserialize_from_hex<'de, D: Deserializer<'de>>( + deserializer: D, +) -> Result { + let hex = <&'de str as Deserialize>::deserialize(deserializer)?; + u32::from_str_radix(hex.strip_prefix("0x").unwrap_or(""), 16).map_err(|_| { + ::custom(format!("{hex} is not a hex encoded 32 bit integer")) + }) +} + /// Parameters for inspecting CPUID definitions. #[derive(Debug, Clone, Eq, PartialEq, Serialize, Deserialize)] pub struct Parameters { // The leaf (EAX) parameter used with the CPUID instruction + #[serde(serialize_with = "serialize_as_hex")] + #[serde(deserialize_with = "deserialize_from_hex")] pub leaf: u32, // The sub-leaf (ECX) parameter used with the CPUID instruction pub sub_leaf: RangeInclusive, From dd852616f9d3099b8c864ec790fd47148e0bb7f9 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 27 Nov 2025 19:31:52 +0100 Subject: [PATCH 42/75] Pretty print CPU profile JSON --- arch/src/x86_64/cpu_profile_generation.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 67479cab3e..a9694335d5 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -124,7 +124,7 @@ fn generate_cpu_profile_data_with( adjustments, }; - serde_json::to_writer(&mut writer, &profile_data) + serde_json::to_writer_pretty(&mut writer, &profile_data) .context("failed to serialize the generated profile data to the given writer")?; writer .flush() From d16e3c98db94498e0f5248cf63253c10a8e894cf Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 27 Nov 2025 19:46:16 +0100 Subject: [PATCH 43/75] Regenerate CPU profiles --- .../x86_64/cpu_profiles/sapphire-rapids.json | 2877 ++++++++++++++++- arch/src/x86_64/cpu_profiles/skylake.json | 2821 +++++++++++++++- 2 files changed, 5696 insertions(+), 2 deletions(-) diff --git a/arch/src/x86_64/cpu_profiles/sapphire-rapids.json b/arch/src/x86_64/cpu_profiles/sapphire-rapids.json index 783b8c1870..5c59c6cb5b 100644 --- a/arch/src/x86_64/cpu_profiles/sapphire-rapids.json +++ b/arch/src/x86_64/cpu_profiles/sapphire-rapids.json @@ -1 +1,2876 @@ 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"replacements": "0x00000000", + "mask": "0xffffffff" + } + ], + [ + { + "leaf": "0x40000000", + "sub_leaf": { + "start": 0, + "end": 0 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0xffffffff" + } + ], + [ + { + "leaf": "0x40000000", + "sub_leaf": { + "start": 0, + "end": 0 + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0xffffffff" + } + ], + [ + { + "leaf": "0x40000001", + "sub_leaf": { + "start": 0, + "end": 0 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x0103feff" + } + ], + [ + { + "leaf": "0x40000001", + "sub_leaf": { + "start": 0, + "end": 0 + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000001" + } + ] + ] +} \ No newline at end of file From f2b16839c78d293fc58aa4b031129082b7c50ee8 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 28 Nov 2025 10:25:39 +0100 Subject: [PATCH 44/75] Check for AMX CPUID (incomplete first attempt probably wrong approach) --- arch/src/x86_64/cpu_profile_generation.rs | 26 ++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index a9694335d5..6274f5d9ad 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -1,6 +1,6 @@ -use crate::x86_64::CpuidReg; #[cfg(feature = "kvm")] use crate::x86_64::cpuid_definitions::CpuidDefinitions; +use crate::x86_64::{AMX_BF16, AMX_INT8, AMX_TILE, CpuidReg}; use crate::x86_64::{ CpuidOutputRegisterAdjustments, cpu_profile::CpuProfileData, @@ -133,12 +133,36 @@ fn generate_cpu_profile_data_with( /// Get the supported CPUID entries from the hypervisor and make sure that they are sorted by function and index fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result> { + // Check for AMX compatibility. If this is supported we need to call arch_prctl before requesting the supported + // CPUID entries from the hypervisor + + // TODO: It might actually be enough to just query arch_prctl directly + if supports_amx() {} hypervisor .get_supported_cpuid() .context("CPU profile data generation failed") .map(sort_entries) } +fn supports_amx() -> bool { + // AMX is unfortunately not a stable feature in Rust yet, hence we need to + // manually query CPUID + + // First check that leaf 0x7 can be queried (this check is almost redundant, but it doesn't hurt to be a bit thorough) + + // SAFETY: leaf 0 is valid whenever the CPUID instruction is available + let max_std_leaf = unsafe { core::arch::x86_64::__cpuid(0).eax }; + if max_std_leaf >= 0x7 { + // SAFETY: We checked the existence of this leaf + let leaf_0x7_subleaf_0_edx = unsafe { core::arch::x86_64::__cpuid(0x7).edx }; + // It is probably enough to just check for AMX_TILE here, but in case that depends on arch_prctl, + // we check for the other basic AMX capabilities as well + (leaf_0x7_subleaf_0_edx & ((1 << AMX_TILE) | (1 << AMX_BF16) | (1 << AMX_INT8))) != 0 + } else { + false + } +} + fn sort_entries(mut cpuid: Vec) -> Vec { cpuid.sort_by(|entry, other_entry| { let fn_cmp = entry.function.cmp(&other_entry.function); From 824db90caa9312fed97ebacbd3cc7acb3a528635 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 28 Nov 2025 12:21:26 +0100 Subject: [PATCH 45/75] Enable TILE state components when AMX is available during profile generation --- arch/src/x86_64/cpu_profile_generation.rs | 54 +++++++++++++++-------- 1 file changed, 35 insertions(+), 19 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 6274f5d9ad..830d179745 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -1,6 +1,6 @@ +use crate::x86_64::CpuidReg; #[cfg(feature = "kvm")] use crate::x86_64::cpuid_definitions::CpuidDefinitions; -use crate::x86_64::{AMX_BF16, AMX_INT8, AMX_TILE, CpuidReg}; use crate::x86_64::{ CpuidOutputRegisterAdjustments, cpu_profile::CpuProfileData, @@ -10,7 +10,7 @@ use crate::x86_64::{ }, }; -use anyhow::Context; +use anyhow::{Context, anyhow}; use hypervisor::CpuVendor; use hypervisor::Hypervisor; use hypervisor::HypervisorType; @@ -135,34 +135,50 @@ fn generate_cpu_profile_data_with( fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result> { // Check for AMX compatibility. If this is supported we need to call arch_prctl before requesting the supported // CPUID entries from the hypervisor - - // TODO: It might actually be enough to just query arch_prctl directly - if supports_amx() {} + if amx_supported() { + request_guest_amx_support().map_err(|e| anyhow!(e))?; + } hypervisor .get_supported_cpuid() .context("CPU profile data generation failed") .map(sort_entries) } -fn supports_amx() -> bool { - // AMX is unfortunately not a stable feature in Rust yet, hence we need to - // manually query CPUID - - // First check that leaf 0x7 can be queried (this check is almost redundant, but it doesn't hurt to be a bit thorough) - - // SAFETY: leaf 0 is valid whenever the CPUID instruction is available - let max_std_leaf = unsafe { core::arch::x86_64::__cpuid(0).eax }; - if max_std_leaf >= 0x7 { - // SAFETY: We checked the existence of this leaf - let leaf_0x7_subleaf_0_edx = unsafe { core::arch::x86_64::__cpuid(0x7).edx }; - // It is probably enough to just check for AMX_TILE here, but in case that depends on arch_prctl, - // we check for the other basic AMX capabilities as well - (leaf_0x7_subleaf_0_edx & ((1 << AMX_TILE) | (1 << AMX_BF16) | (1 << AMX_INT8))) != 0 +fn amx_supported() -> bool { + // TODO: The vmm crate also essentially does this. We should + // rather use this function (or some variant of it) there as well. + const ARCH_GET_XCOMP_SUPP: usize = 0x1021; + const ARCH_XCOMP_TILECFG: usize = 17; + const ARCH_XCOMP_TILEDATA: usize = 18; + let mut features: usize = 0; + let result = + unsafe { libc::syscall(libc::SYS_arch_prctl, ARCH_GET_XCOMP_SUPP, &raw mut features) }; + let mask = (1 << ARCH_XCOMP_TILECFG) | (1 << ARCH_XCOMP_TILEDATA); + if result != 0 { + (features & mask) == mask } else { false } } +fn request_guest_amx_support() -> Result<(), &'static str> { + // TODO: This constant is also used in `guest_amx_supported` + // We should deduplicate this + const ARCH_XCOMP_TILEDATA: usize = 18; + const ARCH_REQ_GUEST_PERM: usize = 0x1025; + let result = unsafe { + libc::syscall( + libc::SYS_arch_prctl, + ARCH_REQ_GUEST_PERM, + ARCH_XCOMP_TILEDATA, + ) + }; + if result != 0 { + Ok(()) + } else { + Err("Failed to enable AMX tile state components for guests") + } +} fn sort_entries(mut cpuid: Vec) -> Vec { cpuid.sort_by(|entry, other_entry| { let fn_cmp = entry.function.cmp(&other_entry.function); From 3d3881188b9eda5fb1b64eff777bcbd82c910119 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 28 Nov 2025 13:12:30 +0100 Subject: [PATCH 46/75] fixed logic bugs --- arch/src/x86_64/cpu_profile_generation.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 830d179745..61918a434f 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -154,7 +154,7 @@ fn amx_supported() -> bool { let result = unsafe { libc::syscall(libc::SYS_arch_prctl, ARCH_GET_XCOMP_SUPP, &raw mut features) }; let mask = (1 << ARCH_XCOMP_TILECFG) | (1 << ARCH_XCOMP_TILEDATA); - if result != 0 { + if result == 0 { (features & mask) == mask } else { false @@ -173,12 +173,13 @@ fn request_guest_amx_support() -> Result<(), &'static str> { ARCH_XCOMP_TILEDATA, ) }; - if result != 0 { + if result == 0 { Ok(()) } else { Err("Failed to enable AMX tile state components for guests") } } + fn sort_entries(mut cpuid: Vec) -> Vec { cpuid.sort_by(|entry, other_entry| { let fn_cmp = entry.function.cmp(&other_entry.function); From 65cfd70a8ef83dc38ffa3dedbb3e6b57938dad56 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 28 Nov 2025 13:14:42 +0100 Subject: [PATCH 47/75] Update Sapphire Rapids profile --- .../x86_64/cpu_profiles/sapphire-rapids.json | 128 +++++++++++++++++- 1 file changed, 127 insertions(+), 1 deletion(-) diff --git a/arch/src/x86_64/cpu_profiles/sapphire-rapids.json b/arch/src/x86_64/cpu_profiles/sapphire-rapids.json index 5c59c6cb5b..a1c12e58b9 100644 --- a/arch/src/x86_64/cpu_profiles/sapphire-rapids.json +++ b/arch/src/x86_64/cpu_profiles/sapphire-rapids.json @@ -922,7 +922,7 @@ "register": "EAX" }, { - "replacements": "0x000002e7", + "replacements": "0x000602e7", "mask": "0x00000000" } ], @@ -1127,6 +1127,48 @@ "leaf": "0x0000000d", "sub_leaf": { "start": 10, + "end": 16 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 17, + "end": 17 + }, + "register": "EAX" + }, + { + "replacements": "0x00000040", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 18, + "end": 18 + }, + "register": "EAX" + }, + { + "replacements": "0x00002000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 19, "end": 63 }, "register": "EAX" @@ -1239,6 +1281,48 @@ "leaf": "0x0000000d", "sub_leaf": { "start": 10, + "end": 16 + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 17, + "end": 17 + }, + "register": "EBX" + }, + { + "replacements": "0x00000ac0", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 18, + "end": 18 + }, + "register": "EBX" + }, + { + "replacements": "0x00000b00", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 19, "end": 63 }, "register": "EBX" @@ -1351,6 +1435,48 @@ "leaf": "0x0000000d", "sub_leaf": { "start": 10, + "end": 16 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 17, + "end": 17 + }, + "register": "ECX" + }, + { + "replacements": "0x00000002", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 18, + "end": 18 + }, + "register": "ECX" + }, + { + "replacements": "0x00000006", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 19, "end": 63 }, "register": "ECX" From a5bfea91dba5be868182825e19203fddc046dfd4 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Wed, 3 Dec 2025 16:18:44 +0100 Subject: [PATCH 48/75] hypervisor: Make amx_supported public We want to use `XsaveState::amx_supported` during profile generation in order to enable AMX tile state components when they are supported by the CPU we are generating the profile for. Signed-off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- hypervisor/src/arch/x86/mod.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hypervisor/src/arch/x86/mod.rs b/hypervisor/src/arch/x86/mod.rs index 56d1e98a24..90cd838166 100644 --- a/hypervisor/src/arch/x86/mod.rs +++ b/hypervisor/src/arch/x86/mod.rs @@ -410,7 +410,7 @@ impl XsaveState { /// CPU vendor (AMX is currently only available on Intel CPUs). /// /// Returns `Ok` if AMX is supported on the host and `Err` otherwise. - fn amx_supported(hypervisor: &dyn Hypervisor) -> Result<(), AmxGuestSupportError> { + pub fn amx_supported(hypervisor: &dyn Hypervisor) -> Result<(), AmxGuestSupportError> { if !matches!(hypervisor.get_cpu_vendor(), CpuVendor::Intel) { return Err(AmxGuestSupportError::VendorDoesNotSupportAmx); } From a769bac82b30bea6f961142f64490ff09252e21b Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 4 Dec 2025 13:13:23 +0100 Subject: [PATCH 49/75] Use XsaveState::enable_amx_state_components during profile generation --- arch/src/x86_64/cpu_profile_generation.rs | 43 +++-------------------- 1 file changed, 4 insertions(+), 39 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 61918a434f..046731c363 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -11,10 +11,10 @@ use crate::x86_64::{ }; use anyhow::{Context, anyhow}; -use hypervisor::CpuVendor; use hypervisor::Hypervisor; use hypervisor::HypervisorType; use hypervisor::arch::x86::CpuIdEntry; +use hypervisor::{CpuVendor, arch::x86::XsaveState}; use std::io::Write; use std::ops::RangeInclusive; @@ -135,51 +135,16 @@ fn generate_cpu_profile_data_with( fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result> { // Check for AMX compatibility. If this is supported we need to call arch_prctl before requesting the supported // CPUID entries from the hypervisor - if amx_supported() { - request_guest_amx_support().map_err(|e| anyhow!(e))?; + if XsaveState::amx_supported(hypervisor).is_ok() { + XsaveState::enable_amx_state_components(hypervisor).map_err(|e| anyhow!(e))?; } + hypervisor .get_supported_cpuid() .context("CPU profile data generation failed") .map(sort_entries) } -fn amx_supported() -> bool { - // TODO: The vmm crate also essentially does this. We should - // rather use this function (or some variant of it) there as well. - const ARCH_GET_XCOMP_SUPP: usize = 0x1021; - const ARCH_XCOMP_TILECFG: usize = 17; - const ARCH_XCOMP_TILEDATA: usize = 18; - let mut features: usize = 0; - let result = - unsafe { libc::syscall(libc::SYS_arch_prctl, ARCH_GET_XCOMP_SUPP, &raw mut features) }; - let mask = (1 << ARCH_XCOMP_TILECFG) | (1 << ARCH_XCOMP_TILEDATA); - if result == 0 { - (features & mask) == mask - } else { - false - } -} - -fn request_guest_amx_support() -> Result<(), &'static str> { - // TODO: This constant is also used in `guest_amx_supported` - // We should deduplicate this - const ARCH_XCOMP_TILEDATA: usize = 18; - const ARCH_REQ_GUEST_PERM: usize = 0x1025; - let result = unsafe { - libc::syscall( - libc::SYS_arch_prctl, - ARCH_REQ_GUEST_PERM, - ARCH_XCOMP_TILEDATA, - ) - }; - if result == 0 { - Ok(()) - } else { - Err("Failed to enable AMX tile state components for guests") - } -} - fn sort_entries(mut cpuid: Vec) -> Vec { cpuid.sort_by(|entry, other_entry| { let fn_cmp = entry.function.cmp(&other_entry.function); From b78705962b26ccafb1919523b36352bc813cd674 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 4 Dec 2025 11:35:45 +0100 Subject: [PATCH 50/75] hypervisor: Introduce an enable AMX tile state components method Currently when the user configures AMX the corresponding state components get dynamically enabled directly inside the function body of vmm::cpu::CpuManager::new. With our ongoing work on CPU templates/profiles, there will (likely) be one more binary crate for producing CPU profiles that also needs to do this (without creating a CpuManager) and it may also be the case that we will need to call this function prior to `CpuManager::new` during live migrations. We thus add a method for enabling the AMX tile state components on the hypervisor trait that may be called wherever necessary. We argue that this is beneficial for code clarity independently of the upcoming CPU templates/profiles PR that we are working on. The astute reader will notice that the logic introduced here is not 100% the same as what is done inside the vmm::cpu::Cpumanager::new method. We claim that our approach is more in-line with the official documentation. Signed-off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- hypervisor/src/arch/x86/mod.rs | 82 ++++++++++++++++++++++++++++++++++ hypervisor/src/hypervisor.rs | 22 +++++++++ 2 files changed, 104 insertions(+) diff --git a/hypervisor/src/arch/x86/mod.rs b/hypervisor/src/arch/x86/mod.rs index 90cd838166..7725598218 100644 --- a/hypervisor/src/arch/x86/mod.rs +++ b/hypervisor/src/arch/x86/mod.rs @@ -19,6 +19,10 @@ use thiserror::Error; use crate::{CpuVendor, Hypervisor}; +use thiserror::Error; + +use crate::CpuVendor; + #[cfg(all(feature = "mshv_emulator", target_arch = "x86_64"))] pub mod emulator; pub mod gdt; @@ -465,3 +469,81 @@ impl XsaveState { } } } + +const ARCH_GET_XCOMP_SUPP: usize = 0x1021; +const ARCH_REQ_XCOMP_GUEST_PERM: usize = 0x1025; +const ARCH_XCOMP_TILECFG: usize = 17; +const ARCH_XCOMP_TILEDATA: usize = 18; + +/// Checks whether the host supports AMX. +/// +/// Returns `Ok` if AMX is supported on the host and `Err` otherwise. +pub(crate) fn amx_supported(cpu_vendor: CpuVendor) -> Result<(), AmxGuestSupportError> { + if !matches!(cpu_vendor, CpuVendor::Intel) { + return Err(AmxGuestSupportError::VendorDoesNotSupportAmx); + } + // We make a syscall to get information about which dynamically enabled + // XSAVE state components are supported. The corresponding state + // component bits will get set in `features` + let mut features: usize = 0; + // SAFETY: Syscall with valid parameters + let result = + unsafe { libc::syscall(libc::SYS_arch_prctl, ARCH_GET_XCOMP_SUPP, &raw mut features) }; + // Ensure that both the TILECFG and TILEDATA state components are supported + let mask = (1 << ARCH_XCOMP_TILECFG) | (1 << ARCH_XCOMP_TILEDATA); + if result != 0 { + return Err(AmxGuestSupportError::AmxNotSupported { errno: result }); + } + + if (features & mask) == mask { + Ok(()) + } else { + Err(AmxGuestSupportError::InvalidAmxTileFeatureCheck { features }) + } +} + +/// Asks the kernel to provide AMX support for guests. +pub(crate) fn request_guest_amx_support() -> Result<(), AmxGuestSupportError> { + // Make a syscall to request permission for guests to use the TILECFG + // and TILEDATA state components. Note that as per the kernel + // [documentation](https://docs.kernel.org/arch/x86/xstate.html#dynamic-features-for-virtual-machines) + // we need to pass in the number of the highest XSTATE component which is required for + // the facility to work which in this case is TILEDATA. + // + // This syscall will alter the size of `kvm_xsave` when KVM is used as the hypervisor. + // + // SAFETY: Syscall with valid parameters + let result = unsafe { + libc::syscall( + libc::SYS_arch_prctl, + ARCH_REQ_XCOMP_GUEST_PERM, + ARCH_XCOMP_TILEDATA, + ) + }; + if result == 0 { + Ok(()) + } else { + // Unwrap is OK because we verified that `result` is not zero + Err(AmxGuestSupportError::AmxGuestTileRequest { errno: result }) + } +} + +/// Error that may be returned when attempting to enable AMX state components for guests +#[derive(Debug, Error)] +pub enum AmxGuestSupportError { + /// Attempted to enable AMX on a CPU from a vendor that is not known to support AMX features. + #[error("The host CPU's vendor does not support AMX features. Only Intel provides such CPUs.")] + VendorDoesNotSupportAmx, + /// Unable to verify that the host supports AMX. + #[error("The host does not support AMX tile state components: errno={errno}")] + AmxNotSupported { errno: i64 }, + /// The syscall to check for AMX tile state support succeeded, but the returned + /// features did not match our expectations. + #[error( + "Could not verify AMX support. These are the supported features that were reported: features={features}" + )] + InvalidAmxTileFeatureCheck { features: usize }, + /// The request to enable AMX related state components for guests failed. + #[error("Failed to enable AMX tile state components for guests: errno={errno}")] + AmxGuestTileRequest { errno: i64 }, +} diff --git a/hypervisor/src/hypervisor.rs b/hypervisor/src/hypervisor.rs index 1974b02861..9d327d4b33 100644 --- a/hypervisor/src/hypervisor.rs +++ b/hypervisor/src/hypervisor.rs @@ -89,6 +89,13 @@ pub enum HypervisorError { /// #[error("Unsupported VmType")] UnsupportedVmType(), + + /// + /// The attempt to enable AMX tile state components failed + /// + #[cfg(target_arch = "x86_64")] + #[error("Failed to enable AMX tile state components")] + CouldNotEnableAmxStateComponents(#[source] crate::arch::x86::AmxGuestSupportError), } /// @@ -194,4 +201,19 @@ pub trait Hypervisor: Send + Sync { } } } + + /// This function enables the AMX related TILECFG and TILEDATA state components for guests. + /// + /// # Background + /// AMX uses a concept of tiles which are small 2D blocks of data stored in registers on the CPU, + /// where the TILECFG state component defines the shape and size of each tile (rows and columns), + /// and the TILEDATA state component holds the actual elements of these tiles used by matrix operations. + #[cfg(target_arch = "x86_64")] + fn enable_amx_state_components(&self) -> Result<()> { + let cpu_vendor = self.get_cpu_vendor(); + crate::arch::x86::amx_supported(cpu_vendor) + .map_err(HypervisorError::CouldNotEnableAmxStateComponents)?; + crate::arch::x86::request_guest_amx_support() + .map_err(HypervisorError::CouldNotEnableAmxStateComponents) + } } From 82f651b5af8497d541e9030878704eb81b79bb1f Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 4 Dec 2025 12:51:46 +0100 Subject: [PATCH 51/75] vmm: Refactor amx tile state component enabling logic We enable AMX tile state components via the hypervisor (as introduced in the previous commit) instead of doing this inline in the body of `CpuManager::new`. Signed-off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- vmm/src/cpu.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/vmm/src/cpu.rs b/vmm/src/cpu.rs index a9cb165c77..f6aef1dce4 100644 --- a/vmm/src/cpu.rs +++ b/vmm/src/cpu.rs @@ -738,8 +738,9 @@ impl CpuManager { #[cfg(target_arch = "x86_64")] if config.features.amx { - hypervisor::arch::x86::XsaveState::enable_amx_state_components(hypervisor.as_ref()) - .map_err(|e| crate::cpu::Error::AmxEnable(e.into()))?; + hypervisor + .enable_amx_state_components() + .map_err(|e| Error::AmxEnable(e.into()))?; } let proximity_domain_per_cpu: BTreeMap = { From d2b9691bee8c6d7cc8a0aead06eb782ca7d84b75 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 4 Dec 2025 16:46:31 +0100 Subject: [PATCH 52/75] arch: Enable amx when available during profile generation Signed-off-by: Oliver Anderson On-behalf-of: SAP oliver.anderson@sap.com --- arch/src/x86_64/cpu_profile_generation.rs | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 046731c363..2f5638c0ef 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -11,10 +11,9 @@ use crate::x86_64::{ }; use anyhow::{Context, anyhow}; -use hypervisor::Hypervisor; use hypervisor::HypervisorType; use hypervisor::arch::x86::CpuIdEntry; -use hypervisor::{CpuVendor, arch::x86::XsaveState}; +use hypervisor::{Hypervisor, HypervisorError}; use std::io::Write; use std::ops::RangeInclusive; @@ -134,9 +133,21 @@ fn generate_cpu_profile_data_with( /// Get the supported CPUID entries from the hypervisor and make sure that they are sorted by function and index fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result> { // Check for AMX compatibility. If this is supported we need to call arch_prctl before requesting the supported - // CPUID entries from the hypervisor - if XsaveState::amx_supported(hypervisor).is_ok() { - XsaveState::enable_amx_state_components(hypervisor).map_err(|e| anyhow!(e))?; + // CPUID entries from the hypervisor. We simply call the enable_amx_state_components method on the hypervisor and + // ignore any AMX not supported error to achieve this. + + match hypervisor.enable_amx_state_components() { + Ok(()) => {} + Err(HypervisorError::CouldNotEnableAmxStateComponents(amx_err)) => { + if !matches!( + amx_err, + hypervisor::arch::x86::AmxGuestSupportError::AmxNotSupported { errno } + ) { + return Err(amx_err) + .context("Could not generate profile. Failed to enable AMX tile state"); + } + } + Err(e) => unreachable!("Unexpected error when checking AMX support"), } hypervisor From 8ad4a1b94d962b0ff6ef8c78507cbb9ae4124d20 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 4 Dec 2025 22:13:54 +0100 Subject: [PATCH 53/75] Use hypervisor method --- arch/src/bin/generate-cpu-profile.rs | 3 +- arch/src/lib.rs | 6 +- arch/src/x86_64/cpu_profile.rs | 7 +- arch/src/x86_64/cpu_profile_generation.rs | 36 +++---- arch/src/x86_64/cpuid_definitions/mod.rs | 3 +- hypervisor/src/arch/x86/mod.rs | 125 ---------------------- 6 files changed, 28 insertions(+), 152 deletions(-) diff --git a/arch/src/bin/generate-cpu-profile.rs b/arch/src/bin/generate-cpu-profile.rs index 693467e142..8e0e76f985 100644 --- a/arch/src/bin/generate-cpu-profile.rs +++ b/arch/src/bin/generate-cpu-profile.rs @@ -1,5 +1,6 @@ -use anyhow::Context; use std::io::BufWriter; + +use anyhow::Context; #[cfg(all( target_arch = "x86_64", feature = "cpu_profile_generation", diff --git a/arch/src/lib.rs b/arch/src/lib.rs index e5795d2585..2a298d0ba3 100644 --- a/arch/src/lib.rs +++ b/arch/src/lib.rs @@ -11,9 +11,6 @@ #[macro_use] extern crate log; -#[cfg(target_arch = "x86_64")] -pub use crate::x86_64::cpu_profile::CpuProfile; - use std::collections::BTreeMap; use std::str::FromStr; use std::sync::Arc; @@ -23,6 +20,9 @@ use serde::de::IntoDeserializer; use serde::{Deserialize, Serialize}; use thiserror::Error; +#[cfg(target_arch = "x86_64")] +pub use crate::x86_64::cpu_profile::CpuProfile; + type GuestMemoryMmap = vm_memory::GuestMemoryMmap; type GuestRegionMmap = vm_memory::GuestRegionMmap; diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index 4c58ced8f5..04808d1729 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -1,11 +1,10 @@ -use crate::x86_64::{ - CpuidReg, - cpuid_definitions::{Parameters, deserialize_from_hex, serialize_as_hex}, -}; use hypervisor::arch::x86::CpuIdEntry; use hypervisor::{CpuVendor, HypervisorType}; use serde::{Deserialize, Serialize}; +use crate::x86_64::CpuidReg; +use crate::x86_64::cpuid_definitions::{Parameters, deserialize_from_hex, serialize_as_hex}; + #[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize, Default)] #[serde(rename_all = "kebab-case")] #[allow(non_camel_case_types)] diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 2f5638c0ef..17854cd450 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -1,22 +1,19 @@ -use crate::x86_64::CpuidReg; -#[cfg(feature = "kvm")] -use crate::x86_64::cpuid_definitions::CpuidDefinitions; -use crate::x86_64::{ - CpuidOutputRegisterAdjustments, - cpu_profile::CpuProfileData, - cpuid_definitions::{ - Parameters, ProfilePolicy, hypervisor::KVM_CPUID_DEFINITIONS, - intel::INTEL_CPUID_DEFINITIONS, - }, -}; - -use anyhow::{Context, anyhow}; -use hypervisor::HypervisorType; -use hypervisor::arch::x86::CpuIdEntry; -use hypervisor::{Hypervisor, HypervisorError}; use std::io::Write; use std::ops::RangeInclusive; +use anyhow::Context; +use hypervisor::CpuVendor; +use hypervisor::arch::x86::CpuIdEntry; +use hypervisor::{Hypervisor, HypervisorError, HypervisorType}; + +use crate::x86_64::cpu_profile::CpuProfileData; +#[cfg(feature = "kvm")] +use crate::x86_64::cpuid_definitions::CpuidDefinitions; +use crate::x86_64::cpuid_definitions::hypervisor::KVM_CPUID_DEFINITIONS; +use crate::x86_64::cpuid_definitions::intel::INTEL_CPUID_DEFINITIONS; +use crate::x86_64::cpuid_definitions::{Parameters, ProfilePolicy}; +use crate::x86_64::{CpuidOutputRegisterAdjustments, CpuidReg}; + /// Generate CPU profile data and convert it to a string, embeddable as Rust code, which is /// written to the given `writer` (e.g. a File). // @@ -141,13 +138,16 @@ fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result { if !matches!( amx_err, - hypervisor::arch::x86::AmxGuestSupportError::AmxNotSupported { errno } + hypervisor::arch::x86::AmxGuestSupportError::AmxNotSupported { .. } ) { return Err(amx_err) .context("Could not generate profile. Failed to enable AMX tile state"); } } - Err(e) => unreachable!("Unexpected error when checking AMX support"), + Err(e) => unreachable!(format!( + "Unexpected error when checking AMX support: error:={:?}", + e + )), } hypervisor diff --git a/arch/src/x86_64/cpuid_definitions/mod.rs b/arch/src/x86_64/cpuid_definitions/mod.rs index 5d6dd68e85..736a89e67a 100644 --- a/arch/src/x86_64/cpuid_definitions/mod.rs +++ b/arch/src/x86_64/cpuid_definitions/mod.rs @@ -1,7 +1,8 @@ -use serde::{Deserialize, Deserializer, Serialize, Serializer}; use std::io::Write; use std::ops::RangeInclusive; +use serde::{Deserialize, Deserializer, Serialize, Serializer}; + use crate::x86_64::CpuidReg; pub mod hypervisor; diff --git a/hypervisor/src/arch/x86/mod.rs b/hypervisor/src/arch/x86/mod.rs index 7725598218..0a39f11830 100644 --- a/hypervisor/src/arch/x86/mod.rs +++ b/hypervisor/src/arch/x86/mod.rs @@ -17,10 +17,6 @@ use std::sync::OnceLock; use thiserror::Error; -use crate::{CpuVendor, Hypervisor}; - -use thiserror::Error; - use crate::CpuVendor; #[cfg(all(feature = "mshv_emulator", target_arch = "x86_64"))] @@ -316,26 +312,6 @@ pub struct MsrEntry { pub data: u64, } -/// Error that may be returned when attempting to enable AMX state components for guests -#[derive(Debug, Error)] -pub enum AmxGuestSupportError { - /// Attempted to enable AMX on a CPU from a vendor that is not known to support AMX features. - #[error("The host CPU's vendor does not support AMX features. Only Intel provides such CPUs.")] - VendorDoesNotSupportAmx, - /// Unable to verify that the host supports AMX. - #[error("The host does not support AMX tile state components: errno={errno}")] - AmxNotSupported { errno: i64 }, - /// The syscall to check for AMX tile state support succeeded, but the returned - /// features did not match our expectations. - #[error( - "Could not verify AMX support. These are the supported features that were reported: features={features}" - )] - InvalidAmxTileFeatureCheck { features: usize }, - /// The request to enable AMX related state components for guests failed. - #[error("Failed to enable AMX tile state components for guests: errno={errno}")] - AmxGuestTileRequest { errno: i64 }, -} - /// The length of the XSAVE flexible array member (FAM). /// This length increases when arch_prctl is utilized to dynamically add state components. /// @@ -347,11 +323,6 @@ static XSAVE_FAM_LENGTH: OnceLock = OnceLock::new(); pub struct XsaveState(#[cfg(feature = "kvm")] pub(crate) kvm_bindings::Xsave); impl XsaveState { - const ARCH_GET_XCOMP_SUPP: usize = 0x1021; - const ARCH_REQ_XCOMP_GUEST_PERM: usize = 0x1025; - const ARCH_XCOMP_TILECFG: usize = 17; - const ARCH_XCOMP_TILEDATA: usize = 18; - /// Construct an instance via the given initializer. /// /// As long as dynamically enabled state components have only been enabled @@ -372,102 +343,6 @@ impl XsaveState { init(&mut xsave).map_err(Into::into)?; Ok(Self(xsave)) } - - /// This function enables the AMX related TILECFG and TILEDATA state components for guests. - /// - /// # Background - /// AMX uses a concept of tiles which are small 2D blocks of data stored in registers on the CPU, - /// where the TILECFG state component defines the shape and size of each tile (rows and columns), - /// and the TILEDATA state component holds the actual elements of these tiles used by matrix operations. - pub fn enable_amx_state_components( - hypervisor: &dyn Hypervisor, - ) -> Result<(), AmxGuestSupportError> { - Self::amx_supported(hypervisor)?; - Self::request_guest_amx_support()?; - - // If we are using the KVM hypervisor we meed to query for the new xsave2 size and update - // `XSAVE_FAM_LENGTH` accordingly. - #[cfg(feature = "kvm")] - { - // Obtain the number of bytes the kvm_xsave struct requires. - // This number is documented to always be at least 4096 bytes, but - let size = hypervisor.check_extension_int(kvm_ioctls::Cap::Xsave2); - // Reality check: We should at least have this number of bytes and probably more as we have enabled - // AMX tiles. If this is not the case, it is probably best to panic. - assert!(size >= 4096); - let fam_length = { - // Computation is documented in `[kvm_bindings::kvm_xsave2::len]` - ((size as usize) - size_of::()) - .div_ceil(size_of::()) - }; - XSAVE_FAM_LENGTH - .set(fam_length) - .expect("This should only be set once"); - } - - Ok(()) - } - - /// Checks whether the host supports AMX. - /// - /// The `hypervisor` is used to inform us about the - /// CPU vendor (AMX is currently only available on Intel CPUs). - /// - /// Returns `Ok` if AMX is supported on the host and `Err` otherwise. - pub fn amx_supported(hypervisor: &dyn Hypervisor) -> Result<(), AmxGuestSupportError> { - if !matches!(hypervisor.get_cpu_vendor(), CpuVendor::Intel) { - return Err(AmxGuestSupportError::VendorDoesNotSupportAmx); - } - // We make a syscall to get information about which dynamically enabled - // XSAVE state components are supported. The corresponding state - // component bits will get set in `features` - let mut features: usize = 0; - // SAFETY: Syscall with valid parameters - let result = unsafe { - libc::syscall( - libc::SYS_arch_prctl, - Self::ARCH_GET_XCOMP_SUPP, - &raw mut features, - ) - }; - // Ensure that both the TILECFG and TILEDATA state components are supported - let mask = (1 << Self::ARCH_XCOMP_TILECFG) | (1 << Self::ARCH_XCOMP_TILEDATA); - if result != 0 { - return Err(AmxGuestSupportError::AmxNotSupported { errno: result }); - } - - if (features & mask) == mask { - Ok(()) - } else { - Err(AmxGuestSupportError::InvalidAmxTileFeatureCheck { features }) - } - } - - /// Asks the kernel to provide AMX support for guests. - fn request_guest_amx_support() -> Result<(), AmxGuestSupportError> { - // Make a syscall to request permission for guests to use the TILECFG - // and TILEDATA state components. Note that as per the kernel - // [documentation](https://docs.kernel.org/arch/x86/xstate.html#dynamic-features-for-virtual-machines) - // we need to pass in the number of the highest XSTATE component which is required for - // the facility to work which in this case is TILEDATA. - // - // This syscall will alter the size of `kvm_xsave` when KVM is used as the hypervisor. - // - // SAFETY: Syscall with valid parameters - let result = unsafe { - libc::syscall( - libc::SYS_arch_prctl, - Self::ARCH_REQ_XCOMP_GUEST_PERM, - Self::ARCH_XCOMP_TILEDATA, - ) - }; - if result == 0 { - Ok(()) - } else { - // Unwrap is OK because we verified that `result` is not zero - Err(AmxGuestSupportError::AmxGuestTileRequest { errno: result }) - } - } } const ARCH_GET_XCOMP_SUPP: usize = 0x1021; From 4733b20ae0d80765518c1fcbddc16e939c659803 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 4 Dec 2025 22:14:10 +0100 Subject: [PATCH 54/75] add check on vmm --- vmm/src/lib.rs | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/vmm/src/lib.rs b/vmm/src/lib.rs index 52d799797a..1ed7fe57f1 100644 --- a/vmm/src/lib.rs +++ b/vmm/src/lib.rs @@ -8,6 +8,8 @@ extern crate event_monitor; #[macro_use] extern crate log; +use anyhow::Context; + /// Amount of iterations before auto-converging starts. const AUTO_CONVERGE_ITERATION_DELAY: u64 = 2; /// Step size in percent to increase the vCPU throttling. @@ -2277,6 +2279,15 @@ impl Vmm { "Live Migration is not supported when TDX is enabled" ))); }; + // TODO: Explain why we need to call this here. + + if src_vm_config.lock().unwrap().cpus.features.amx { + let _ = self + .hypervisor + .enable_amx_state_components() + .context("Unable to enable AMX before generating CPUID") + .map_err(|e| MigratableError::MigrateReceive(e))?; + } // We check the `CPUID` compatibility of between the source vm and destination, which is // mostly about feature compatibility. From a369b5e23e40279cf6efa0295c84b5684816fdbc Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 4 Dec 2025 22:22:45 +0100 Subject: [PATCH 55/75] x --- arch/src/x86_64/cpu_profile_generation.rs | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 17854cd450..e274a791db 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -144,10 +144,7 @@ fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result unreachable!(format!( - "Unexpected error when checking AMX support: error:={:?}", - e - )), + Err(_) => unreachable!("Unexpected error when checking AMX support"), } hypervisor From e3e0d5f7f08598051e7fa21ce7412ad0c0a18f24 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Thu, 4 Dec 2025 22:34:04 +0100 Subject: [PATCH 56/75] x --- arch/src/x86_64/cpu_profile_generation.rs | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index e274a791db..3e39fe5893 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -135,15 +135,13 @@ fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result {} - Err(HypervisorError::CouldNotEnableAmxStateComponents(amx_err)) => { - if !matches!( - amx_err, - hypervisor::arch::x86::AmxGuestSupportError::AmxNotSupported { .. } - ) { - return Err(amx_err) - .context("Could not generate profile. Failed to enable AMX tile state"); + Err(HypervisorError::CouldNotEnableAmxStateComponents(amx_err)) => match amx_err { + // TODO: Explain + err @ hypervisor::arch::x86::AmxGuestSupportError::AmxGuestTileRequest { .. } => { + return Err(err).context("Unable to enable AMX state tiles for guests"); } - } + _ => {} + }, Err(_) => unreachable!("Unexpected error when checking AMX support"), } From 7a1e628e179bd353ced61383a9a505d90637087c Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 5 Dec 2025 01:42:24 +0100 Subject: [PATCH 57/75] Add more permitted missing cpuid entries --- arch/src/x86_64/cpu_profile.rs | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index 04808d1729..6a50d6fec9 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -139,10 +139,52 @@ impl CpuidOutputRegisterAdjustments { } // Check that we found every value that was supposed to be replaced with something else than 0 let mut missing_entry = false; + + let eax_0xd_0 = cpuid + .iter() + .find(|entry| (entry.function == 0xd) && (entry.index == 0)) + .map(|entry| entry.eax) + .unwrap_or(0); + let ecx_0xd_1 = cpuid + .iter() + .find(|entry| (entry.function == 0xd) && (entry.index == 1)) + .map(|entry| entry.ecx) + .unwrap_or(0); + + let edx_0xd_0 = cpuid + .iter() + .find(|entry| (entry.function == 0xd) && (entry.index == 0)) + .map(|entry| entry.edx) + .unwrap_or(0); + let edx_0xd_1 = cpuid + .iter() + .find(|entry| (entry.function == 0xd) && (entry.index == 1)) + .map(|entry| entry.edx) + .unwrap_or(0); + for (param, adjustment) in adjustments { if adjustment.replacements == 0 { continue; } + let sub_start = *param.sub_leaf.start(); + let sub_end = *param.sub_leaf.end(); + if (param.leaf == 0xd) && (sub_start >= 2) && (sub_start < 32) && (sub_start == sub_end) + { + if (((1 << sub_start) & eax_0xd_0) == 0) && (((1 << sub_start) & ecx_0xd_1) == 0) { + // This means that the sub-leaf is to be considered invalid anyway and it is OK if we don't find it + continue; + } + } + + if (param.leaf == 0xd) && (sub_start >= 32) && (sub_start < 64) { + if (((1 << (sub_start - 32)) & edx_0xd_0) == 0) + && (((1 << (sub_start - 32)) & edx_0xd_1) == 0) + { + // This means that the sub-leaf is to be considered invalid anyway and it is OK if we don't find it + continue; + } + } + if param.leaf == 0xd && (param.sub_leaf.contains(&3) || param.sub_leaf.contains(&4)) { // TODO: Fix this via policies! continue; From 81954a609763abf3705c472fe6b2677306ae9d35 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 5 Dec 2025 02:11:48 +0100 Subject: [PATCH 58/75] Modify profile data to reflect AMX requirements --- arch/src/x86_64/cpu_profile.rs | 28 ++++++++++++++++++++++++++-- arch/src/x86_64/mod.rs | 2 +- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index 6a50d6fec9..466cbb9526 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -20,8 +20,8 @@ pub enum CpuProfile { impl CpuProfile { // We can only generate CPU profiles for the KVM hypervisor for the time being. #[cfg(feature = "kvm")] - pub(in crate::x86_64) fn data(&self) -> Option { - match self { + pub(in crate::x86_64) fn data(&self, amx: bool) -> Option { + let mut data: CpuProfileData = match self { Self::Host => None, Self::Skylake => Some( serde_json::from_slice(include_bytes!("cpu_profiles/skylake.json")) @@ -37,7 +37,31 @@ impl CpuProfile { }) .expect("should be able to deserialize pre-generated data"), ), + }?; + + if amx { + for adj in data.adjustments.iter_mut() { + if adj.0.sub_leaf.start() != adj.0.sub_leaf.end() { + continue; + } + let sub_leaf = *adj.0.sub_leaf.start(); + let leaf = adj.0.leaf; + if (leaf == 0xd) && (sub_leaf == 0) && (adj.0.register == CpuidReg::EAX) { + // TODO: Explain parameters + adj.1.replacements &= !((1 << 17) | (1 << 18)); + } + + if (leaf == 0xd) && (sub_leaf == 1) && (adj.0.register == CpuidReg::ECX) { + adj.1.replacements &= !((1 << 17) | (1 << 18)); + } + + if (leaf == 0xd) && ((sub_leaf == 17) | (sub_leaf == 18)) { + adj.1.replacements = 0; + } + } } + + Some(data) } #[cfg(not(feature = "kvm"))] diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index 89f6d93ee1..6c73d4c572 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -677,7 +677,7 @@ pub fn generate_common_cpuid( let (host_adjusted_to_profile, profile_cpu_vendor) = { config .profile - .data() + .data(config.amx) .map(|profile_data| { ( CpuidOutputRegisterAdjustments::adjust_cpuid_entries( From c197ef83332126225ec293a85fad0060bde5026d Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 5 Dec 2025 07:31:30 +0100 Subject: [PATCH 59/75] Temporary fix: Set XSAVE size in hypervisor::enable_amx_state_components --- hypervisor/src/arch/x86/mod.rs | 2 +- hypervisor/src/hypervisor.rs | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hypervisor/src/arch/x86/mod.rs b/hypervisor/src/arch/x86/mod.rs index 0a39f11830..4f6d841ebc 100644 --- a/hypervisor/src/arch/x86/mod.rs +++ b/hypervisor/src/arch/x86/mod.rs @@ -317,7 +317,7 @@ pub struct MsrEntry { /// /// IMPORTANT: This static should only be updated via methods on [`XsaveState`]. #[cfg(feature = "kvm")] -static XSAVE_FAM_LENGTH: OnceLock = OnceLock::new(); +pub(crate) static XSAVE_FAM_LENGTH: OnceLock = OnceLock::new(); #[derive(Debug, Clone, serde::Serialize, serde::Deserialize)] pub struct XsaveState(#[cfg(feature = "kvm")] pub(crate) kvm_bindings::Xsave); diff --git a/hypervisor/src/hypervisor.rs b/hypervisor/src/hypervisor.rs index 9d327d4b33..9dd74dcca9 100644 --- a/hypervisor/src/hypervisor.rs +++ b/hypervisor/src/hypervisor.rs @@ -210,6 +210,10 @@ pub trait Hypervisor: Send + Sync { /// and the TILEDATA state component holds the actual elements of these tiles used by matrix operations. #[cfg(target_arch = "x86_64")] fn enable_amx_state_components(&self) -> Result<()> { + // TODO: Remove this and go with upstream solution + use crate::arch::x86::XSAVE_FAM_LENGTH; + let size = self.check_extension_int(kvm_ioctls::Cap::Xsave2) as usize; + let _ = XSAVE_FAM_LENGTH.set(size); let cpu_vendor = self.get_cpu_vendor(); crate::arch::x86::amx_supported(cpu_vendor) .map_err(HypervisorError::CouldNotEnableAmxStateComponents)?; From f6ff87e16e1641f4535dd9db76bf9719b0013e19 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Fri, 5 Dec 2025 07:42:55 +0100 Subject: [PATCH 60/75] Fix bug --- arch/src/x86_64/cpu_profile.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index 466cbb9526..b3b04d991c 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -39,7 +39,7 @@ impl CpuProfile { ), }?; - if amx { + if !amx { for adj in data.adjustments.iter_mut() { if adj.0.sub_leaf.start() != adj.0.sub_leaf.end() { continue; From 46ec70100eba6c9dd6b7d29f1eec7430e6fe1855 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 8 Dec 2025 16:19:46 +0100 Subject: [PATCH 61/75] Change processor brand string --- arch/src/bin/generate-cpu-profile.rs | 13 +++- arch/src/x86_64/cpu_profile_generation.rs | 72 ++++++++++++++++++++--- 2 files changed, 76 insertions(+), 9 deletions(-) diff --git a/arch/src/bin/generate-cpu-profile.rs b/arch/src/bin/generate-cpu-profile.rs index 8e0e76f985..eabe47472d 100644 --- a/arch/src/bin/generate-cpu-profile.rs +++ b/arch/src/bin/generate-cpu-profile.rs @@ -1,15 +1,24 @@ use std::io::BufWriter; -use anyhow::Context; +use anyhow::{Context, anyhow}; #[cfg(all( target_arch = "x86_64", feature = "cpu_profile_generation", feature = "kvm" ))] fn main() -> anyhow::Result<()> { + // TODO: Consider using clap for argument parsing and allow the user to specify it with --name + let profile_name = std::env::args() + .nth(1) + .ok_or(anyhow!("A name for the profile needs to be provided"))?; + let hypervisor = hypervisor::new().context("Could not obtain hypervisor")?; // TODO: Consider letting the user provide a file path as a target instead of writing to stdout. // The way it is now should be sufficient for a PoC however. let writer = BufWriter::new(std::io::stdout().lock()); - arch::x86_64::cpu_profile_generation::generate_profile_data(writer, hypervisor.as_ref()) + arch::x86_64::cpu_profile_generation::generate_profile_data( + writer, + hypervisor.as_ref(), + profile_name, + ) } diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 3e39fe5893..033540c7db 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -1,7 +1,7 @@ use std::io::Write; use std::ops::RangeInclusive; -use anyhow::Context; +use anyhow::{Context, anyhow}; use hypervisor::CpuVendor; use hypervisor::arch::x86::CpuIdEntry; use hypervisor::{Hypervisor, HypervisorError, HypervisorType}; @@ -22,11 +22,13 @@ use crate::x86_64::{CpuidOutputRegisterAdjustments, CpuidReg}; pub fn generate_profile_data( mut writer: impl Write, hypervisor: &dyn Hypervisor, + profile_name: String, ) -> anyhow::Result<()> { let cpu_vendor = hypervisor.get_cpu_vendor(); if cpu_vendor != CpuVendor::Intel { unimplemented!("CPU profiles can only be generated for Intel CPUs at this point in time"); } + let hypervisor_type = hypervisor.hypervisor_type(); // This is just a reality check. if hypervisor_type != HypervisorType::Kvm { @@ -34,7 +36,12 @@ pub fn generate_profile_data( "CPU profiles can only be generated when using KVM as the hypervisor at this point in time" ); } - let supported_cpuid_sorted = supported_cpuid_sorted(hypervisor)?; + + let brand_string_bytes = cpu_brand_string_bytes(cpu_vendor, profile_name)?; + let cpuid = supported_cpuid(hypervisor)?; + let cpuid = overwrite_brand_string(cpuid, brand_string_bytes); + let supported_cpuid_sorted = sort_entries(cpuid); + generate_cpu_profile_data_with( hypervisor_type, cpu_vendor, @@ -45,6 +52,26 @@ pub fn generate_profile_data( ) } +/// Prepare the bytes which the brand string should consist of +fn cpu_brand_string_bytes(cpu_vendor: CpuVendor, profile_name: String) -> anyhow::Result<[u8; 48]> { + let cpu_vendor_str: String = serde_json::to_string(&cpu_vendor) + .expect("Should be possible to serialize CPU vendor to a string"); + let mut brand_string_bytes = [0_u8; 4 * 3 * 4]; + if cpu_vendor_str.len() + profile_name.len() > brand_string_bytes.len() { + return Err(anyhow!( + "The profile name is too long. Try using a shorter name" + )); + } + for (b, brand_byte) in cpu_vendor_str + .as_bytes() + .iter() + .chain(profile_name.as_bytes()) + .zip(brand_string_bytes.iter_mut()) + { + *brand_byte = *b; + } + Ok(brand_string_bytes) +} /// Computes [`CpuProfileData`] based on the given sorted vector of CPUID entries, hypervisor type, cpu_vendor /// and cpuid_definitions. /// @@ -127,12 +154,11 @@ fn generate_cpu_profile_data_with( .context("CPU profile generation failed: Unable to flush cpu profile data") } -/// Get the supported CPUID entries from the hypervisor and make sure that they are sorted by function and index -fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result> { +/// Get as many of the supported CPUID entries from the hypervisor as possible. +fn supported_cpuid(hypervisor: &dyn Hypervisor) -> anyhow::Result> { // Check for AMX compatibility. If this is supported we need to call arch_prctl before requesting the supported // CPUID entries from the hypervisor. We simply call the enable_amx_state_components method on the hypervisor and // ignore any AMX not supported error to achieve this. - match hypervisor.enable_amx_state_components() { Ok(()) => {} Err(HypervisorError::CouldNotEnableAmxStateComponents(amx_err)) => match amx_err { @@ -148,11 +174,43 @@ fn supported_cpuid_sorted(hypervisor: &dyn Hypervisor) -> anyhow::Result, + brand_string_bytes: [u8; 48], +) -> Vec { + let mut iter = brand_string_bytes + .as_chunks::<4>() + .0 + .iter() + .map(|c| u32::from_le_bytes(*c)); + let mut overwrite = |leaf: u32| CpuIdEntry { + function: leaf, + index: 0, + flags: 0, + eax: iter.next().unwrap_or(0), + ebx: iter.next().unwrap_or(0), + ecx: iter.next().unwrap_or(0), + edx: iter.next().unwrap_or(0), + }; + for leaf in [0x80000002, 0x80000003, 0x80000004] { + if let Some(entry) = cpuid + .iter_mut() + .find(|entry| (entry.function == leaf) && (entry.index == 0)) + { + *entry = overwrite(leaf); + } else { + cpuid.push(overwrite(leaf)); + } + } + cpuid +} + +/// Sort the CPUID entries by function and index fn sort_entries(mut cpuid: Vec) -> Vec { - cpuid.sort_by(|entry, other_entry| { + cpuid.sort_unstable_by(|entry, other_entry| { let fn_cmp = entry.function.cmp(&other_entry.function); if fn_cmp == core::cmp::Ordering::Equal { entry.index.cmp(&other_entry.index) From 0f9d1e13a76ff3c62d026d91a8eaa7496cc4529d Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 8 Dec 2025 17:24:43 +0100 Subject: [PATCH 62/75] Remove MPX properly --- arch/src/x86_64/cpu_profile.rs | 6 +- arch/src/x86_64/cpuid_definitions/intel.rs | 122 ++++++++++++++++++++- 2 files changed, 120 insertions(+), 8 deletions(-) diff --git a/arch/src/x86_64/cpu_profile.rs b/arch/src/x86_64/cpu_profile.rs index b3b04d991c..74fe7b3903 100644 --- a/arch/src/x86_64/cpu_profile.rs +++ b/arch/src/x86_64/cpu_profile.rs @@ -40,6 +40,7 @@ impl CpuProfile { }?; if !amx { + // In this case we will need to wipe out the AMX tile state components (if they are included in the profile) for adj in data.adjustments.iter_mut() { if adj.0.sub_leaf.start() != adj.0.sub_leaf.end() { continue; @@ -47,7 +48,6 @@ impl CpuProfile { let sub_leaf = *adj.0.sub_leaf.start(); let leaf = adj.0.leaf; if (leaf == 0xd) && (sub_leaf == 0) && (adj.0.register == CpuidReg::EAX) { - // TODO: Explain parameters adj.1.replacements &= !((1 << 17) | (1 << 18)); } @@ -209,10 +209,6 @@ impl CpuidOutputRegisterAdjustments { } } - if param.leaf == 0xd && (param.sub_leaf.contains(&3) || param.sub_leaf.contains(&4)) { - // TODO: Fix this via policies! - continue; - } if !cpuid.iter().any(|entry| { (entry.function == param.leaf) && (param.sub_leaf.contains(&entry.index)) }) { diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index dcac016a25..1471db9eeb 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -6,7 +6,7 @@ use super::{ ValueDefinition, ValueDefinitions, }; -pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { +pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { CpuidDefinitions([ // ========================================================================================= // Basic CPUID Information @@ -2573,7 +2573,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { // Processor Extended State Enumeration Main Leaf // =================================================================================================================== // TODO: Figure out properly when to use Inherit vs Passthrough - // TODO: Check that CHV checks for migration compatibility here + // TODO: Ensure that CHV checks for migration compatibility here ( Parameters { leaf: 0xd, @@ -2723,7 +2723,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { short: "xcr0_upper_bits", description: "Reports the valid bit fields of the upper 32 bits of the XCR0 register", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -2978,6 +2978,122 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<147> = const { }, ]), ), + // Intel MPX is deprecated hence we zero out these sub-leaves + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(3, 4), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-3-4-eax-mpx-zero", + description: "This leaf has been zeroed out because MPX state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(3, 4), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-3-4-ebx-mpx-zero", + description: "This leaf has been zeroed out because MPX state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(3, 4), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-3-4-ecx-mpx-zero", + description: "This leaf has been zeroed out because MPX state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(3, 4), + register: CpuidReg::EDX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "0xd-3-4-edx-mpx-zero", + description: "This leaf has been zeroed out because MPX state components are disabled", + bits_range: (0, 31), + policy: ProfilePolicy::Overwrite(0), + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(5, 63), + register: CpuidReg::EAX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "xsave_sz", + description: "Size of save area for subleaf-N feature, in bytes", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(5, 63), + register: CpuidReg::EBX, + }, + ValueDefinitions::new(&[ValueDefinition { + short: "xsave_offset", + description: "Offset of save area for subleaf-N feature, in bytes", + bits_range: (0, 31), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }]), + ), + ( + Parameters { + leaf: 0xd, + sub_leaf: RangeInclusive::new(5, 63), + register: CpuidReg::ECX, + }, + ValueDefinitions::new(&[ + ValueDefinition { + short: "is_xss_bit", + description: "Subleaf N describes an XSS bit, otherwise XCR0 bit", + bits_range: (0, 0), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ValueDefinition { + short: "compacted_xsave_64byte_aligned", + description: "When compacted, subleaf-N feature XSAVE area is 64-byte aligned", + bits_range: (1, 1), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + // TODO: This may depend on the "amx" feature? + ValueDefinition { + short: "xfd_faulting", + description: "Indicates support for xfd faulting", + bits_range: (2, 2), + policy: ProfilePolicy::Inherit, + migration_compatibility_req: MigrationCompatibilityRequirement::Eq, + }, + ]), + ), // =================================================================================================================== // Intel Resource Director Technology Monitoring Enumeration // =================================================================================================================== From ddb61537baa3593309e14068274dddb58273ca37 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 8 Dec 2025 17:31:49 +0100 Subject: [PATCH 63/75] Change brand string policy --- arch/src/x86_64/cpuid_definitions/intel.rs | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index 1471db9eeb..627b6ca2e9 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -5124,7 +5124,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_0", description: "CPU brand ID string, bytes 0 - 3", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5138,7 +5138,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_1", description: "CPU brand ID string, bytes 4 - 7", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5152,7 +5152,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_2", description: "CPU brand ID string, bytes 8 - 11", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5166,7 +5166,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_3", description: "CPU brand ID string, bytes 12 - 15", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5180,7 +5180,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_4", description: "CPU brand ID string bytes, 16 - 19", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5194,7 +5194,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_5", description: "CPU brand ID string bytes, 20 - 23", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5208,7 +5208,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_6", description: "CPU brand ID string bytes, 24 - 27", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5222,7 +5222,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_7", description: "CPU brand ID string bytes, 28 - 31", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5236,7 +5236,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_8", description: "CPU brand ID string, bytes 32 - 35", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5250,7 +5250,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_9", description: "CPU brand ID string, bytes 36 - 39", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5264,7 +5264,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_10", description: "CPU brand ID string, bytes 40 - 43", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), @@ -5278,7 +5278,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cpu_brandid_11", description: "CPU brand ID string, bytes 44 - 47", bits_range: (0, 31), - policy: ProfilePolicy::Passthrough, + policy: ProfilePolicy::Inherit, migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), From bc0605f2bab57139a94cdc95b4d00553d55abb58 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 8 Dec 2025 18:05:32 +0100 Subject: [PATCH 64/75] Use clap --- Cargo.lock | 1 + arch/Cargo.toml | 3 ++- arch/src/bin/generate-cpu-profile.rs | 27 +++++++++++++++++++-------- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 998dfb6f3c..ae5e350144 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -109,6 +109,7 @@ version = "0.1.0" dependencies = [ "anyhow", "byteorder", + "clap", "fdt", "hypervisor", "libc", diff --git a/arch/Cargo.toml b/arch/Cargo.toml index 68da4e4bf5..f1b119b6c1 100644 --- a/arch/Cargo.toml +++ b/arch/Cargo.toml @@ -17,11 +17,12 @@ kvm = ["hypervisor/kvm"] sev_snp = [] tdx = [] # Currently cpu profiles can only be generated with KVM -cpu_profile_generation = ["kvm"] +cpu_profile_generation = ["kvm", "dep:clap"] [dependencies] anyhow = { workspace = true } byteorder = { workspace = true } +clap = { workspace = true, optional = true } hypervisor = { path = "../hypervisor" } libc = { workspace = true } linux-loader = { workspace = true, features = ["bzimage", "elf", "pe"] } diff --git a/arch/src/bin/generate-cpu-profile.rs b/arch/src/bin/generate-cpu-profile.rs index eabe47472d..bd5b930fd5 100644 --- a/arch/src/bin/generate-cpu-profile.rs +++ b/arch/src/bin/generate-cpu-profile.rs @@ -1,16 +1,27 @@ -use std::io::BufWriter; - -use anyhow::{Context, anyhow}; -#[cfg(all( +#![cfg(all( target_arch = "x86_64", feature = "cpu_profile_generation", feature = "kvm" ))] +use anyhow::{Context, anyhow}; +use clap::{Arg, Command}; +use std::io::BufWriter; + fn main() -> anyhow::Result<()> { - // TODO: Consider using clap for argument parsing and allow the user to specify it with --name - let profile_name = std::env::args() - .nth(1) - .ok_or(anyhow!("A name for the profile needs to be provided"))?; + let cmd_arg = Command::new("generate-cpu-profile") + .version(env!("CARGO_PKG_VERSION")) + .arg_required_else_help(true) + .arg( + Arg::new("name") + .help( + "The name of the CPU profile. The name may may only contain ASCII characters.", + ) + .num_args(1) + .required(true), + ) + .get_matches(); + + let profile_name = cmd_arg.get_one::("name").unwrap(); let hypervisor = hypervisor::new().context("Could not obtain hypervisor")?; // TODO: Consider letting the user provide a file path as a target instead of writing to stdout. From 74aedeb5cb20c6a70d3b944720232212e4e0eb80 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 8 Dec 2025 18:08:23 +0100 Subject: [PATCH 65/75] Fix --- arch/src/x86_64/cpu_profile_generation.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 033540c7db..44145187ee 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -22,7 +22,7 @@ use crate::x86_64::{CpuidOutputRegisterAdjustments, CpuidReg}; pub fn generate_profile_data( mut writer: impl Write, hypervisor: &dyn Hypervisor, - profile_name: String, + profile_name: &str, ) -> anyhow::Result<()> { let cpu_vendor = hypervisor.get_cpu_vendor(); if cpu_vendor != CpuVendor::Intel { @@ -53,7 +53,7 @@ pub fn generate_profile_data( } /// Prepare the bytes which the brand string should consist of -fn cpu_brand_string_bytes(cpu_vendor: CpuVendor, profile_name: String) -> anyhow::Result<[u8; 48]> { +fn cpu_brand_string_bytes(cpu_vendor: CpuVendor, profile_name: &str) -> anyhow::Result<[u8; 48]> { let cpu_vendor_str: String = serde_json::to_string(&cpu_vendor) .expect("Should be possible to serialize CPU vendor to a string"); let mut brand_string_bytes = [0_u8; 4 * 3 * 4]; From 27edb674777378f19d3f846d8b6e1e3c5dfde316 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 8 Dec 2025 18:22:48 +0100 Subject: [PATCH 66/75] x --- arch/src/bin/generate-cpu-profile.rs | 6 ++---- arch/src/x86_64/cpu_profile_generation.rs | 1 + 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/src/bin/generate-cpu-profile.rs b/arch/src/bin/generate-cpu-profile.rs index bd5b930fd5..c6d17c19a5 100644 --- a/arch/src/bin/generate-cpu-profile.rs +++ b/arch/src/bin/generate-cpu-profile.rs @@ -3,7 +3,7 @@ feature = "cpu_profile_generation", feature = "kvm" ))] -use anyhow::{Context, anyhow}; +use anyhow::Context; use clap::{Arg, Command}; use std::io::BufWriter; @@ -13,9 +13,7 @@ fn main() -> anyhow::Result<()> { .arg_required_else_help(true) .arg( Arg::new("name") - .help( - "The name of the CPU profile. The name may may only contain ASCII characters.", - ) + .help("The name to give the CPU profile") .num_args(1) .required(true), ) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 44145187ee..570e10c909 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -56,6 +56,7 @@ pub fn generate_profile_data( fn cpu_brand_string_bytes(cpu_vendor: CpuVendor, profile_name: &str) -> anyhow::Result<[u8; 48]> { let cpu_vendor_str: String = serde_json::to_string(&cpu_vendor) .expect("Should be possible to serialize CPU vendor to a string"); + let cpu_vendor_str = cpu_vendor_str.trim_start_matches('"').trim_end_matches('"'); let mut brand_string_bytes = [0_u8; 4 * 3 * 4]; if cpu_vendor_str.len() + profile_name.len() > brand_string_bytes.len() { return Err(anyhow!( From cf1ae8a19e728dfe8095ff2e97b7695aa282bb6d Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 8 Dec 2025 18:28:15 +0100 Subject: [PATCH 67/75] x --- arch/src/x86_64/cpu_profile_generation.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 570e10c909..e42e8413d4 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -58,7 +58,7 @@ fn cpu_brand_string_bytes(cpu_vendor: CpuVendor, profile_name: &str) -> anyhow:: .expect("Should be possible to serialize CPU vendor to a string"); let cpu_vendor_str = cpu_vendor_str.trim_start_matches('"').trim_end_matches('"'); let mut brand_string_bytes = [0_u8; 4 * 3 * 4]; - if cpu_vendor_str.len() + profile_name.len() > brand_string_bytes.len() { + if cpu_vendor_str.len() + 1 + profile_name.len() > brand_string_bytes.len() { return Err(anyhow!( "The profile name is too long. Try using a shorter name" )); @@ -67,6 +67,7 @@ fn cpu_brand_string_bytes(cpu_vendor: CpuVendor, profile_name: &str) -> anyhow:: .as_bytes() .iter() .chain(profile_name.as_bytes()) + .chain(std::iter::once(&b' ')) .zip(brand_string_bytes.iter_mut()) { *brand_byte = *b; From c0c0fb6724e9e2e24050b01622ca705452a18355 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 8 Dec 2025 19:53:42 +0100 Subject: [PATCH 68/75] x --- arch/src/x86_64/cpu_profile_generation.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index e42e8413d4..6fa1c165aa 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -66,8 +66,8 @@ fn cpu_brand_string_bytes(cpu_vendor: CpuVendor, profile_name: &str) -> anyhow:: for (b, brand_byte) in cpu_vendor_str .as_bytes() .iter() - .chain(profile_name.as_bytes()) .chain(std::iter::once(&b' ')) + .chain(profile_name.as_bytes()) .zip(brand_string_bytes.iter_mut()) { *brand_byte = *b; From c3082d99eed9d675d975c6ceb78ec36a7896fb6c Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Mon, 8 Dec 2025 21:58:41 +0100 Subject: [PATCH 69/75] Regenerate Sapphire rapids --- .../x86_64/cpu_profiles/sapphire-rapids.json | 472 +++++++++++++++++- 1 file changed, 453 insertions(+), 19 deletions(-) diff --git a/arch/src/x86_64/cpu_profiles/sapphire-rapids.json b/arch/src/x86_64/cpu_profiles/sapphire-rapids.json index a1c12e58b9..0ea90aa979 100644 --- a/arch/src/x86_64/cpu_profiles/sapphire-rapids.json +++ b/arch/src/x86_64/cpu_profiles/sapphire-rapids.json @@ -965,7 +965,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -1486,6 +1486,440 @@ "mask": "0x00000000" } ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 3, + "end": 4 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 3, + "end": 4 + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 3, + "end": 4 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 3, + "end": 4 + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 5, + "end": 5 + }, + "register": "EAX" + }, + { + "replacements": "0x00000040", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 6, + "end": 6 + }, + "register": "EAX" + }, + { + "replacements": "0x00000200", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 7, + "end": 7 + }, + "register": "EAX" + }, + { + "replacements": "0x00000400", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 8, + "end": 8 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 9, + "end": 9 + }, + "register": "EAX" + }, + { + "replacements": "0x00000008", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 10, + "end": 16 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 17, + "end": 17 + }, + "register": "EAX" + }, + { + "replacements": "0x00000040", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 18, + "end": 18 + }, + "register": "EAX" + }, + { + "replacements": "0x00002000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 19, + "end": 63 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 5, + "end": 5 + }, + "register": "EBX" + }, + { + "replacements": "0x00000440", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 6, + "end": 6 + }, + "register": "EBX" + }, + { + "replacements": "0x00000480", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 7, + "end": 7 + }, + "register": "EBX" + }, + { + "replacements": "0x00000680", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 8, + "end": 8 + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 9, + "end": 9 + }, + "register": "EBX" + }, + { + "replacements": "0x00000a80", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 10, + "end": 16 + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 17, + "end": 17 + }, + "register": "EBX" + }, + { + "replacements": "0x00000ac0", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 18, + "end": 18 + }, + "register": "EBX" + }, + { + "replacements": "0x00000b00", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 19, + "end": 63 + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 5, + "end": 5 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 6, + "end": 6 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 7, + "end": 7 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 8, + "end": 8 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 9, + "end": 9 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 10, + "end": 16 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 17, + "end": 17 + }, + "register": "ECX" + }, + { + "replacements": "0x00000002", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 18, + "end": 18 + }, + "register": "ECX" + }, + { + "replacements": "0x00000006", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 19, + "end": 63 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], [ { "leaf": "0x0000000f", @@ -2700,8 +3134,8 @@ "register": "EAX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x65746e49", + "mask": "0x00000000" } ], [ @@ -2714,8 +3148,8 @@ "register": "EBX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x6153206c", + "mask": "0x00000000" } ], [ @@ -2728,8 +3162,8 @@ "register": "ECX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x69687070", + "mask": "0x00000000" } ], [ @@ -2742,8 +3176,8 @@ "register": "EDX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x72206572", + "mask": "0x00000000" } ], [ @@ -2756,8 +3190,8 @@ "register": "EAX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x64697061", + "mask": "0x00000000" } ], [ @@ -2770,8 +3204,8 @@ "register": "EBX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x00000073", + "mask": "0x00000000" } ], [ @@ -2785,7 +3219,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2799,7 +3233,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2813,7 +3247,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2827,7 +3261,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2841,7 +3275,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2855,7 +3289,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ From c639cad52fa9a51706a3bee7207a17904ae2fc6f Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 9 Dec 2025 09:24:36 +0100 Subject: [PATCH 70/75] Rename Overwrite to Static --- arch/src/x86_64/cpu_profile_generation.rs | 2 +- arch/src/x86_64/cpuid_definitions/intel.rs | 458 ++++++++++----------- arch/src/x86_64/cpuid_definitions/mod.rs | 4 +- 3 files changed, 232 insertions(+), 232 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index 6fa1c165aa..ce84d884e2 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -117,7 +117,7 @@ fn generate_cpu_profile_data_with( let (first_bit_pos, last_bit_pos) = value.bits_range; mask |= bit_range_mask(first_bit_pos, last_bit_pos); } - ProfilePolicy::Overwrite(overwrite_value) => { + ProfilePolicy::Static(overwrite_value) => { replacements |= overwrite_value << value.bits_range.0; } ProfilePolicy::Inherit => { diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index 627b6ca2e9..1738a858bf 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -145,7 +145,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "n_logical_cpu", description: "Logical CPU count", bits_range: (16, 23), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, // This is set by cloud hypervisor @@ -153,7 +153,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "local_apic_id", description: "Initial local APIC physical ID", bits_range: (24, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), @@ -183,7 +183,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "dtes64", description: "64-bit DS save area", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Perhaps there should be some CHV feature for opting in to enabling this for non-host CPU profiles? @@ -191,14 +191,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "monitor", description: "MONITOR/MWAIT support", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ds_cpl", description: "CPL Qualified Debug Store", bits_range: (4, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Ideally configurable by the user (host must have this otherwise CHV will not run) @@ -206,28 +206,28 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "vmx", description: "Virtual Machine Extensions", bits_range: (5, 5), - policy: ProfilePolicy::Overwrite(1), + policy: ProfilePolicy::Static(1), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "smx", description: "Safer Mode Extensions", bits_range: (6, 6), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "est", description: "Enhanced Intel SpeedStep", bits_range: (7, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "tm2", description: "Thermal Monitor 2", bits_range: (8, 8), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -242,14 +242,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cnxt_id", description: "L1 Context ID", bits_range: (10, 10), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "sdbg", description: "Silicon Debug", bits_range: (11, 11), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -271,7 +271,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "xtpr", description: "xTPR Update Control", bits_range: (14, 14), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related @@ -279,7 +279,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pdcm", description: "Perfmon and Debug Capability", bits_range: (15, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -315,7 +315,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "x2apic", description: "X2APIC support", bits_range: (21, 21), - policy: ProfilePolicy::Overwrite(1), + policy: ProfilePolicy::Static(1), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -337,7 +337,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "tsc_deadline_timer", description: "APIC timer one-shot operation", bits_range: (24, 24), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -468,7 +468,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "apic", description: "APIC on-chip", bits_range: (9, 9), - policy: ProfilePolicy::Overwrite(1), + policy: ProfilePolicy::Static(1), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related (maybe not necessary to look into which ones) @@ -525,7 +525,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "psn", description: "Processor Serial Number", bits_range: (18, 18), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -539,14 +539,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "ds", description: "Debug Store", bits_range: (21, 21), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "acpi", description: "Thermal monitor and clock control", bits_range: (22, 22), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -595,7 +595,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "tm", description: "Thermal Monitor", bits_range: (29, 29), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, @@ -605,7 +605,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pbe", description: "Pending Break Enable", bits_range: (31, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -931,7 +931,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "min_mon_size", description: "Smallest monitor-line size, in bytes", bits_range: (0, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::LtEq, }]), ), @@ -945,7 +945,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "max_mon_size", description: "Largest monitor-line size, in bytes", bits_range: (0, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), @@ -960,14 +960,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "mwait_ext", description: "Enumeration of MONITOR/MWAIT extensions is supported", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mwait_irq_break", description: "Interrupts as a break-event for MWAIT is supported", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -983,56 +983,56 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "n_c0_substates", description: "Number of C0 sub C-states supported using MWAIT", bits_range: (0, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c1_substates", description: "Number of C1 sub C-states supported using MWAIT", bits_range: (4, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c2_substates", description: "Number of C2 sub C-states supported using MWAIT", bits_range: (8, 11), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c3_substates", description: "Number of C3 sub C-states supported using MWAIT", bits_range: (12, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c4_substates", description: "Number of C4 sub C-states supported using MWAIT", bits_range: (16, 19), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c5_substates", description: "Number of C5 sub C-states supported using MWAIT", bits_range: (20, 23), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c6_substates", description: "Number of C6 sub C-states supported using MWAIT", bits_range: (24, 27), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c7_substates", description: "Number of C7 sub C-states supported using MWAIT", bits_range: (28, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), @@ -1051,14 +1051,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "dtherm", description: "Digital temperature sensor", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "turbo_boost", description: "Intel Turbo Boost", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1072,126 +1072,126 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pln", description: "Power Limit Notification (PLN) event", bits_range: (4, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ecmd", description: "Clock modulation duty cycle extension", bits_range: (5, 5), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pts", description: "Package thermal management", bits_range: (6, 6), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp", description: "HWP (Hardware P-states) base registers are supported", bits_range: (7, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_notify", description: "HWP notification (IA32_HWP_INTERRUPT MSR)", bits_range: (8, 8), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_act_window", description: "HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported", bits_range: (9, 9), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_epp", description: "HWP Energy Performance Preference", bits_range: (10, 10), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_pkg_req", description: "HWP Package Level Request", bits_range: (11, 11), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hdc_base_regs", description: "HDC base registers are supported", bits_range: (13, 13), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "turbo_boost_3_0", description: "Intel Turbo Boost Max 3.0", bits_range: (14, 14), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_capabilities", description: "HWP Highest Performance change", bits_range: (15, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_peci_override", description: "HWP PECI override", bits_range: (16, 16), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_flexible", description: "Flexible HWP", bits_range: (17, 17), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_fast", description: "IA32_HWP_REQUEST MSR fast access mode", bits_range: (18, 18), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hfi", description: "HW_FEEDBACK MSRs supported", bits_range: (19, 19), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_ignore_idle", description: "Ignoring idle logical CPU HWP req is supported", bits_range: (20, 20), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "thread_director", description: "Intel thread director support", bits_range: (23, 23), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "therm_interrupt_bit25", description: "IA32_THERM_INTERRUPT MSR bit 25 is supported", bits_range: (24, 24), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -1208,7 +1208,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "n_therm_thresholds", description: "Digital thermometer thresholds", bits_range: (0, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), @@ -1225,7 +1225,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "aperfmperf", description: "MPERF/APERF MSRs (effective frequency interface)", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related @@ -1233,14 +1233,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "epb", description: "IA32_ENERGY_PERF_BIAS MSR support", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "thrd_director_nclasses", description: "Number of classes, Intel thread director", bits_range: (8, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), @@ -1256,28 +1256,28 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "perfcap_reporting", description: "Performance capability reporting", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "encap_reporting", description: "Energy efficiency capability reporting", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "feedback_sz", description: "Feedback interface structure size, in 4K pages", bits_range: (8, 11), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "this_lcpu_hwfdbk_idx", description: "This logical CPU hardware feedback interface index", bits_range: (16, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), @@ -1326,7 +1326,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "sgx", description: "Intel SGX (Software Guard Extensions)", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1341,7 +1341,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "hle", description: "Hardware Lock Elision", bits_range: (4, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1402,14 +1402,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "rtm", description: "Intel restricted transactional memory", bits_range: (11, 11), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "rdt_m", description: "Supports Intel Resource Director Technology Monitoring Capability if 1", bits_range: (12, 12), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). TODO: Is it OK to just set this to 1? @@ -1425,7 +1425,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "mpx", description: "Intel memory protection extensions", bits_range: (14, 14), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // This might be useful for certain high performance applications, but it also seems like a rather niche and advanced feature. QEMU does also not automatically enable this from what we can tell. @@ -1434,7 +1434,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "rdt_a", description: "Intel RDT-A. Supports Intel Resource Director Technology Allocation Capability if 1", bits_range: (15, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Do the wider avx512 zmm registers work out of the box when the hardware supports it? @@ -1498,7 +1498,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "intel_pt", description: "Intel processor trace", bits_range: (25, 25), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1556,7 +1556,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "prefetchwt1", description: "PREFETCHWT1 (Intel Xeon Phi only)", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1652,7 +1652,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "tme", description: "Intel total memory encryption", bits_range: (13, 13), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1673,7 +1673,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "mawau_val_lm", description: "BNDLDX/BNDSTX MAWAU value in 64-bit mode", bits_range: (17, 21), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // MSR related @@ -1689,7 +1689,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "key_locker", description: "Intel key locker support", bits_range: (23, 23), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1724,7 +1724,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "enqcmd", description: "Enqueue stores supported (ENQCMD{,S})", bits_range: (29, 29), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // SGX support is deprecated so we disable it unconditionally for CPU profiles @@ -1732,14 +1732,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "sgx_lc", description: "Intel SGX launch configuration", bits_range: (30, 30), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pks", description: "Protection keys for supervisor-mode pages", bits_range: (31, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -1756,7 +1756,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "sgx_keys", description: "Intel SGX attestation services", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1784,7 +1784,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "uintr", description: "CPU supports user interrupts", bits_range: (5, 5), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1813,14 +1813,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "rtm_always_abort", description: "XBEGIN (RTM transaction) always aborts", bits_range: (11, 11), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "tsx_force_abort", description: "MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported", bits_range: (13, 13), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -1842,7 +1842,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "tsxldtrk", description: "TSX suspend/resume load address tracking", bits_range: (16, 16), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // Might be relevant for confidential computing @@ -1850,7 +1850,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pconfig", description: "PCONFIG instruction", bits_range: (18, 18), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related @@ -1858,7 +1858,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "arch_lbr", description: "Intel architectural LBRs", bits_range: (19, 19), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure if this is the best default, but QEMU also seems to disable this for CPU models @@ -1983,7 +1983,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "RAO-INT", description: "RAO-INT instructions", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -2023,7 +2023,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "arch_perfmon_ext", description: "ArchPerfmonExt: leaf 0x23 is supported", bits_range: (8, 8), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -2072,7 +2072,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "nmi_src", description: "NMI-source reporting with FRED event data", bits_range: (20, 20), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -2086,7 +2086,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "hreset", description: "History reset support", bits_range: (22, 22), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -2137,7 +2137,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "intel_ppin", description: "Protected processor inventory number (PPIN{,_CTL} MSRs)", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related @@ -2145,7 +2145,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pbndkb", description: "PBNDKB instruction supported and enumerates the existence of the IA32_TSE_CAPABILITY MSR", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -2193,7 +2193,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "utmr", description: "If 1, supports user-timer events", bits_range: (13, 13), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -2208,14 +2208,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "user_msr", description: "If 1, supports the URDMSR and UWRMSR instructions", bits_range: (15, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "uiret_uif", description: "If 1, UIRET sets UIF to the value of bit 1 of the RFLAGS image loaded from the stack", bits_range: (15, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -2243,7 +2243,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "mwait", description: "If 1, MWAIT is supported even if (0x1 ECX bit 3 (monitor) is enumerated as 0)", bits_range: (23, 23), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related @@ -2251,7 +2251,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "slsm", description: "If 1, indicates bit 0 of the IA32_INTEGRITY_STATUS MSR is supported. Bit 0 of this MSR indicates whether static lockstep is active on this logical processor", bits_range: (24, 24), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -2339,7 +2339,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "dca_cap_msr_value", description: "Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1f8H)", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), @@ -2360,28 +2360,28 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pmu_version", description: "Performance monitoring unit version ID", bits_range: (0, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "pmu_n_gcounters", description: "Number of general PMU counters per logical CPU", bits_range: (8, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "pmu_gcounters_nbits", description: "Bitwidth of PMU general counters", bits_range: (16, 23), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "pmu_cpuid_ebx_bits", description: "Length of leaf 0xa EBX bit vector", bits_range: (24, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), @@ -2397,56 +2397,56 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "no_core_cycle_evt", description: "Core cycle event not available", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_insn_retired_evt", description: "Instruction retired event not available", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_refcycle_evt", description: "Reference cycles event not available", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_llc_ref_evt", description: "LLC-reference event not available", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_llc_miss_evt", description: "LLC-misses event not available", bits_range: (4, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_br_insn_ret_evt", description: "Branch instruction retired event not available", bits_range: (5, 5), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_br_mispredict_evt", description: "Branch mispredict retired event not available", bits_range: (6, 6), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_td_slots_evt", description: "Topdown slots event not available", bits_range: (7, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), @@ -2461,7 +2461,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pmu_fcounters_bitmap", description: "Fixed-function PMU counters support bitmap", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -2476,21 +2476,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pmu_n_fcounters", description: "Number of fixed PMU counters", bits_range: (0, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "pmu_fcounters_nbits", description: "Bitwidth of PMU fixed counters", bits_range: (5, 12), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "anythread_depr", description: "AnyThread deprecation", bits_range: (15, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), @@ -2607,7 +2607,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "xcr0_mpx_bndregs", description: "XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MPX is deprecated @@ -2615,7 +2615,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "xcr0_mpx_bndcsr", description: "XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)", bits_range: (4, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { @@ -2989,7 +2989,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "0xd-3-4-eax-mpx-zero", description: "This leaf has been zeroed out because MPX state components are disabled", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -3003,7 +3003,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "0xd-3-4-ebx-mpx-zero", description: "This leaf has been zeroed out because MPX state components are disabled", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -3017,7 +3017,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "0xd-3-4-ecx-mpx-zero", description: "This leaf has been zeroed out because MPX state components are disabled", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -3031,7 +3031,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "0xd-3-4-edx-mpx-zero", description: "This leaf has been zeroed out because MPX state components are disabled", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -3107,7 +3107,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "core_rmid_max", description: "RMID max, within this core, all types (0-based)", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), @@ -3123,7 +3123,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cqm_llc", description: "Supports L3 Cache Intel RDT Monitoring if 1", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -3143,28 +3143,28 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "l3c_qm_bitwidth", description: "L3 QoS-monitoring counter bitwidth (24-based)", bits_range: (0, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "l3c_qm_overflow_bit", description: "QM_CTR MSR bit 61 is an overflow bit", bits_range: (8, 8), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "l3c_qm_non_cpu_agent", description: "If 1, indicates the presence of non-CPU agent Intel RDT CTM support", bits_range: (9, 9), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "l3c_qm_non_cpu_agent", description: "If 1, indicates the presence of non-CPU agent Intel RDT MBM support", bits_range: (10, 10), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), @@ -3180,7 +3180,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "l3c_qm_conver_factor", description: "QM_CTR MSR conversion factor to bytes", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -3195,7 +3195,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "l3c_qm_rmid_max", description: "L3 QoS-monitoring max RMID", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), @@ -3210,21 +3210,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cqm_occup_llc", description: "L3 QoS occupancy monitoring supported", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cqm_mbm_total", description: "L3 QoS total bandwidth monitoring supported", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cqm_mbm_local", description: "L3 QoS local bandwidth monitoring supported", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -3244,21 +3244,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cat_l3", description: "L3 Cache Allocation Technology supported", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "cat_l2", description: "L2 Cache Allocation Technology supported", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "mba", description: "Memory Bandwidth Allocation supported", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), @@ -3306,21 +3306,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "l3_cat_non_cpu_agents", description: "L3_CAT for non-CPU agent is supported", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cdp_l3", description: "L3/L2_CAT CDP (Code and Data Prioritization)", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cat_sparse_1s", description: "L3/L2_CAT non-contiguous 1s value supported", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -3336,7 +3336,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cat_cos_max", description: "Highest COS number supported for this ResID", bits_range: (0, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), @@ -3381,7 +3381,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cat_cos_max", description: "Highest COS number supported for this ResID", bits_range: (0, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), @@ -3397,14 +3397,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cdp_l2", description: "L2_CAT CDP (Code and Data Prioritization)", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cat_sparse_1s", description: "L2_CAT non-contiguous 1s value supported", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -3424,7 +3424,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "mba_max_delay", description: "Max MBA throttling value; minus-one notation", bits_range: (0, 11), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }, ]), @@ -3440,14 +3440,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "per_thread_mba", description: "Per-thread MBA controls are supported", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mba_delay_linear", description: "Delay values are linear", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -3462,7 +3462,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "mba_cos_max", description: "MBA max Class of Service supported", bits_range: (0, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), @@ -3482,7 +3482,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "core_max_throttle", description: "Max Core throttling level supported by the corresponding ResID", bits_range: (0, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }, // TODO: Not sure about the short name @@ -3490,7 +3490,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "core_scope", description: "If 1, indicates the logical processor scope of the IA32_QoS_Core_BW_Thrtl_n MSRs. Other values are reserved", bits_range: (8, 11), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), @@ -3505,7 +3505,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cba_delay_linear", description: "The response of the bandwidth control is approximately linear", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -3519,7 +3519,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "core_cos_max", description: "Core max Class of Service supported", bits_range: (0, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), @@ -3538,7 +3538,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pt_max_subleaf", description: "Maximum leaf 0x14 subleaf", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), @@ -3553,63 +3553,63 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cr3_filtering", description: "IA32_RTIT_CR3_MATCH is accessible", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "psb_cyc", description: "Configurable PSB and cycle-accurate mode", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ip_filtering", description: "IP/TraceStop filtering; Warm-reset PT MSRs preservation", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mtc_timing", description: "MTC timing packet; COFI-based packets suppression", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ptwrite", description: "PTWRITE support", bits_range: (4, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "power_event_trace", description: "Power Event Trace support", bits_range: (5, 5), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "psb_pmi_preserve", description: "PSB and PMI preservation support", bits_range: (6, 6), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "event_trace", description: "Event Trace packet generation through IA32_RTIT_CTL.EventEn", bits_range: (7, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "tnt_disable", description: "TNT packet generation disable through IA32_RTIT_CTL.DisTNT", bits_range: (8, 8), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -3625,35 +3625,35 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "topa_output", description: "ToPA output scheme support", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "topa_multiple_entries", description: "ToPA tables can hold multiple entries", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "single_range_output", description: "Single-range output scheme supported", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "trance_transport_output", description: "Trace Transport subsystem output support", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ip_payloads_lip", description: "IP payloads have LIP values (CS base included)", bits_range: (31, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -3672,14 +3672,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "num_address_ranges", description: "Filtering number of configurable Address Ranges", bits_range: (0, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mtc_periods_bmp", description: "Bitmap of supported MTC period encodings", bits_range: (16, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -3695,14 +3695,14 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cycle_thresholds_bmp", description: "Bitmap of supported Cycle Threshold encodings", bits_range: (0, 15), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "psb_periods_bmp", description: "Bitmap of supported Configurable PSB frequency encodings", bits_range: (16, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -3814,7 +3814,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "soc_max_subleaf", description: "Maximum leaf 0x17 subleaf", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), @@ -3957,70 +3957,70 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "lbr_depth_8", description: "Max stack depth (number of LBR entries) = 8", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_16", description: "Max stack depth (number of LBR entries) = 16", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_24", description: "Max stack depth (number of LBR entries) = 24", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_32", description: "Max stack depth (number of LBR entries) = 32", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_40", description: "Max stack depth (number of LBR entries) = 40", bits_range: (4, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_48", description: "Max stack depth (number of LBR entries) = 48", bits_range: (5, 5), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_56", description: "Max stack depth (number of LBR entries) = 56", bits_range: (6, 6), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_64", description: "Max stack depth (number of LBR entries) = 64", bits_range: (7, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_deep_c_reset", description: "LBRs maybe cleared on MWAIT C-state > C1", bits_range: (30, 30), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_ip_is_lip", description: "LBR IP contain Last IP, otherwise effective IP", bits_range: (31, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -4036,21 +4036,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "lbr_cpl", description: "CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_branch_filter", description: "Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_call_stack", description: "Call-stack mode (IA32_LBR_CTL[3] = 1) supported", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -4066,28 +4066,28 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "lbr_mispredict", description: "Branch misprediction bit supported (IA32_LBR_x_INFO[63])", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_timed_lbr", description: "Timed LBRs (CPU cycles since last LBR entry) supported", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_branch_type", description: "Branch type field (IA32_LBR_INFO_x[59:56]) supported", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_events_gpc_bmp", description: "LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters", bits_range: (16, 19), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -4389,7 +4389,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "hreset_thread_director", description: "HRESET of Intel thread director is supported", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), @@ -4408,7 +4408,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "tdx_vendorid_0", description: "TDX vendor ID string bytes 0 - 3", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -4422,7 +4422,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "tdx_vendorid_2", description: "CPU vendor ID string bytes 8 - 11", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -4436,7 +4436,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "tdx_vendorid_1", description: "CPU vendor ID string bytes 4 - 7", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), @@ -4454,42 +4454,42 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "subleaf_0", description: "If 1, subleaf 0 exists", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_1", description: "If 1, subleaf 1 exists", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_2", description: "If 1, subleaf 2 exists", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_3", description: "If 1, subleaf 3 exists", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_4", description: "If 1, subleaf 4 exists", bits_range: (4, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_5", description: "If 1, subleaf 5 exists. The processor suppots Architectural PEBS. The IA32_PEBS_BASE and IA32_PEBS_INDEX MSRs exist", bits_range: (5, 5), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -4505,21 +4505,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "unitmask2", description: "IA32_PERFEVTSELx MSRs UnitMask2 is supported", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "eq_bit", description: "equal flag in the IA32_PERFEVTSELx MSR is supported", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "RDPMC_USR_DISABLE", description: "RDPMC_USR_DISABLE", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -4536,7 +4536,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "num_slots_per_cycle", description: "Number of slots per cycle. This number can be multiplied by the number of cycles (from CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.CORE or IA32_FIXED_CTR1) to determine the total number of slots", bits_range: (0, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), @@ -4554,7 +4554,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pmu_gp_counters_bitmap", description: "General-purpose PMU counters bitmap", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), @@ -4568,7 +4568,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pmu_f_counters_bitmap", description: "Fixed PMU counters bitmap", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), @@ -4585,7 +4585,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pmu_acr_bitmap", description: "Bitmap of Auto Counter Reload (ACR) general-purpose counters that can be reloaded", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), @@ -4603,91 +4603,91 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "core_cycles_evt", description: "Core cycles event supported", bits_range: (0, 0), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "insn_retired_evt", description: "Instructions retired event supported", bits_range: (1, 1), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ref_cycles_evt", description: "Reference cycles event supported", bits_range: (2, 2), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "llc_refs_evt", description: "Last-level cache references event supported", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "llc_misses_evt", description: "Last-level cache misses event supported", bits_range: (4, 4), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "br_insn_ret_evt", description: "Branch instruction retired event supported", bits_range: (5, 5), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "br_mispr_evt", description: "Branch mispredict retired event supported", bits_range: (6, 6), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_slots_evt", description: "Topdown slots event supported", bits_range: (7, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_backend_bound_evt", description: "Topdown backend bound event supported", bits_range: (8, 8), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_bad_spec_evt", description: "Topdown bad speculation event supported", bits_range: (9, 9), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_frontend_bound_evt", description: "Topdown frontend bound event supported", bits_range: (10, 10), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_retiring_evt", description: "Topdown retiring event support", bits_range: (11, 11), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_inserts", description: "LBR support", bits_range: (12, 12), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -4706,7 +4706,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "allow_in_record", description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Should the migration compatibility check rather be CintainsBits? @@ -4714,7 +4714,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cntr", description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", bits_range: (0, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: Should the migration compatibility check rather be CintainsBits? @@ -4722,7 +4722,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "lbr", description: "LBR group and both bits [41:40] are available", bits_range: (8, 9), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: Should the migration compatibility check rather be CintainsBits? @@ -4730,21 +4730,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "xer", description: "These bits correspond to XER group bits [55:49]", bits_range: (17, 23), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "grp", description: "If 1, the GRP group is available", bits_range: (29, 29), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "aux", description: "If 1, the AUX group is available", bits_range: (30, 30), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -4760,7 +4760,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "allow_in_record", description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", bits_range: (3, 3), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Should the migration compatibility check rather be CintainsBits? @@ -4768,7 +4768,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "cntr", description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", bits_range: (0, 7), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: Should the migration compatibility check rather be CintainsBits? @@ -4776,7 +4776,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "lbr", description: "LBR group and both bits [41:40] are available", bits_range: (8, 9), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: Should the migration compatibility check rather be CintainsBits? @@ -4784,21 +4784,21 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "xer", description: "These bits correspond to XER group bits [55:49]", bits_range: (17, 23), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "grp", description: "If 1, the GRP group is available", bits_range: (29, 29), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "aux", description: "If 1, the AUX group is available", bits_range: (30, 30), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), @@ -4816,7 +4816,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "architectural_pebs_counters", description: "General-purpose counters support Architectural PEBS. Bit vector of general-purpose counters for which the Architectural PEBS mechanism is available", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), @@ -4830,7 +4830,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pebs_pdist_counters", description: "General-purpose counters for which PEBS support PDIST", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), @@ -4844,7 +4844,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pebs_fixed_function_counters", description: "Fixed-function counters support Architectural PEBS. Bit vector of fixed-function counters for which the Architectural PEBS mechanism is available. If ECX[x] == 1, then the IA32_PMC_FXm_CFG_C MSR is available, and PEBS is supported", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), @@ -4858,7 +4858,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "pebs_fixed_function_pdist_counters", description: "Fixed-function counters for which PEBS supports PDIST", bits_range: (0, 31), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), @@ -5378,7 +5378,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { short: "wbnoinvd", description: "WBNOINVD supported", bits_range: (9, 9), - policy: ProfilePolicy::Overwrite(0), + policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), diff --git a/arch/src/x86_64/cpuid_definitions/mod.rs b/arch/src/x86_64/cpuid_definitions/mod.rs index 736a89e67a..b95d37c3dc 100644 --- a/arch/src/x86_64/cpuid_definitions/mod.rs +++ b/arch/src/x86_64/cpuid_definitions/mod.rs @@ -62,8 +62,8 @@ pub enum ProfilePolicy { Passthrough, /// Set the following hardcoded value in the CPU profile. /// - /// This variant is typically used for features/values that don't work well with live migration (even when using the exact same physical CPU model) - Overwrite(u32), + /// This variant is typically used for features/values that don't work well with live migration (even when using the exact same physical CPU model). + Static(u32), } /// Describes how values within a CPUID output on two different hosts must relate to another in order for live-migration to be considered acceptable. From 9be2490c485e57cc3e42fde2f4e5fb069c9f5418 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 9 Dec 2025 09:28:14 +0100 Subject: [PATCH 71/75] Fix typos --- arch/src/x86_64/cpu_profile_generation.rs | 2 +- arch/src/x86_64/cpuid_definitions/intel.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index ce84d884e2..a55879574a 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -178,7 +178,7 @@ fn supported_cpuid(hypervisor: &dyn Hypervisor) -> anyhow::Result, brand_string_bytes: [u8; 48], diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index 1738a858bf..da9240378a 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -598,7 +598,7 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, - // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Overwrite(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, + // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Not really sure what the default should be for PBE. It seems like it is something that needs to be enabled via the IA32_MISC_ENABLE MSR hence perhaps this should be set via CPU features? // MSR related ValueDefinition { From 91bf088abbfb29b0068c09f6ff0e7acd9f843109 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 9 Dec 2025 09:36:34 +0100 Subject: [PATCH 72/75] As slice method instead of exposing internals --- arch/src/x86_64/cpu_profile_generation.rs | 4 ++-- arch/src/x86_64/cpuid_definitions/mod.rs | 8 +++++++- arch/src/x86_64/mod.rs | 2 +- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/src/x86_64/cpu_profile_generation.rs b/arch/src/x86_64/cpu_profile_generation.rs index a55879574a..6ce4aa9af7 100644 --- a/arch/src/x86_64/cpu_profile_generation.rs +++ b/arch/src/x86_64/cpu_profile_generation.rs @@ -92,9 +92,9 @@ fn generate_cpu_profile_data_with( let mut adjustments: Vec<(Parameters, CpuidOutputRegisterAdjustments)> = Vec::new(); for (parameter, values) in processor_cpuid_definitions - .0 + .as_slice() .iter() - .chain(hypervisor_cpuid_definitions.0.iter()) + .chain(hypervisor_cpuid_definitions.as_slice().iter()) { for (sub_leaf_range, maybe_matching_register_output_value) in extract_parameter_matches(parameter, &supported_cpuid_sorted) diff --git a/arch/src/x86_64/cpuid_definitions/mod.rs b/arch/src/x86_64/cpuid_definitions/mod.rs index b95d37c3dc..72daf874f4 100644 --- a/arch/src/x86_64/cpuid_definitions/mod.rs +++ b/arch/src/x86_64/cpuid_definitions/mod.rs @@ -122,5 +122,11 @@ impl ValueDefinitions { // TODO: Consider introducing a const as_slice method to make it impossible for the parameter -> value definitions // constraints being broken. pub struct CpuidDefinitions( - pub [(Parameters, ValueDefinitions); NUM_PARAMETERS], + [(Parameters, ValueDefinitions); NUM_PARAMETERS], ); + +impl CpuidDefinitions { + pub const fn as_slice(&self) -> &[(Parameters, ValueDefinitions); NUM_PARAMETERS] { + &self.0 + } +} diff --git a/arch/src/x86_64/mod.rs b/arch/src/x86_64/mod.rs index 6c73d4c572..a9fcd43d8c 100644 --- a/arch/src/x86_64/mod.rs +++ b/arch/src/x86_64/mod.rs @@ -544,7 +544,7 @@ impl CpuidFeatureEntry { // TODO: Check against the CPU vendor before using the intel definitions if let Some((_, defs)) = cpuid_definitions::intel::INTEL_CPUID_DEFINITIONS - .0 + .as_slice() .iter() .find(|(param, _)| { (param.leaf == entry.function) From bf5c438266d4435cb8ac9c836dc72413bc3fb860 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 9 Dec 2025 09:59:53 +0100 Subject: [PATCH 73/75] Remove migration compatibility requirement --- .../x86_64/cpuid_definitions/hypervisor.rs | 26 +- arch/src/x86_64/cpuid_definitions/intel.rs | 553 +----------------- arch/src/x86_64/cpuid_definitions/mod.rs | 16 - 3 files changed, 2 insertions(+), 593 deletions(-) diff --git a/arch/src/x86_64/cpuid_definitions/hypervisor.rs b/arch/src/x86_64/cpuid_definitions/hypervisor.rs index 889d6a8605..81edfd31e0 100644 --- a/arch/src/x86_64/cpuid_definitions/hypervisor.rs +++ b/arch/src/x86_64/cpuid_definitions/hypervisor.rs @@ -4,8 +4,7 @@ use std::ops::RangeInclusive; use crate::x86_64::CpuidReg; use crate::x86_64::cpuid_definitions::{ - CpuidDefinitions, MigrationCompatibilityRequirement, Parameters, ProfilePolicy, - ValueDefinition, ValueDefinitions, + CpuidDefinitions, Parameters, ProfilePolicy, ValueDefinition, ValueDefinitions, }; /// CPUID features defined for the KVM hypervisor. @@ -27,7 +26,6 @@ pub const KVM_CPUID_DEFINITIONS: CpuidDefinitions<6> = const { description: "The maximum valid leaf between 0x4000_0000 and 0x4FFF_FFF", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -41,7 +39,6 @@ pub const KVM_CPUID_DEFINITIONS: CpuidDefinitions<6> = const { description: "Part of the hypervisor string", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -55,7 +52,6 @@ pub const KVM_CPUID_DEFINITIONS: CpuidDefinitions<6> = const { description: "Part of the hypervisor string", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -69,7 +65,6 @@ pub const KVM_CPUID_DEFINITIONS: CpuidDefinitions<6> = const { description: "Part of the hypervisor string", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), //===================================================================== @@ -87,126 +82,108 @@ pub const KVM_CPUID_DEFINITIONS: CpuidDefinitions<6> = const { description: "kvmclock available at MSRs 0x11 and 0x12", bits_range: (0, 0), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_nop_io_delay", description: "Not necessary to perform delays on PIO operations", bits_range: (1, 1), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_mmu_op", description: "Deprecated", bits_range: (2, 2), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_clocksource2", description: "kvmclock available at MSRs 0x4b564d00 and 0x4b564d01", bits_range: (3, 3), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_async_pf", description: "async pf can be enabled by writing to MSR 0x4b564d02", bits_range: (4, 4), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_steal_time", description: "steal time can be enabled by writing to msr 0x4b564d03", bits_range: (5, 5), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_pv_eoi", description: "paravirtualized end of interrupt handler can be enabled by writing to msr 0x4b564d04", bits_range: (6, 6), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_pv_unhalt", description: "guest checks this feature bit before enabling paravirtualized spinlock support", bits_range: (7, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_pv_tlb_flush", description: "guest checks this feature bit before enabling paravirtualized tlb flush", bits_range: (9, 9), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_async_pf_vmexit", description: "paravirtualized async PF VM EXIT can be enabled by setting bit 2 when writing to msr 0x4b564d02", bits_range: (10, 10), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_pv_send_ipi", description: "guest checks this feature bit before enabling paravirtualized send IPIs", bits_range: (11, 11), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_poll_control", description: "host-side polling on HLT can be disabled by writing to msr 0x4b564d05.", bits_range: (12, 12), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_pv_sched_yield", description: "guest checks this feature bit before using paravirtualized sched yield.", bits_range: (13, 13), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_async_pf_int", description: "guest checks this feature bit before using the second async pf control msr 0x4b564d06 and async pf acknowledgment msr 0x4b564d07.", bits_range: (14, 14), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_msi_ext_dest_id", description: "guest checks this feature bit before using extended destination ID bits in MSI address bits 11-5.", bits_range: (15, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_hc_map_gpa_range", description: "guest checks this feature bit before using the map gpa range hypercall to notify the page state change", bits_range: (16, 16), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_migration_control", description: "guest checks this feature bit before using MSR_KVM_MIGRATION_CONTROL", bits_range: (17, 17), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "kvm_feature_clocksource_stable_bit", description: "host will warn if no guest-side per-cpu warps are expected in kvmclock", bits_range: (24, 24), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -221,7 +198,6 @@ pub const KVM_CPUID_DEFINITIONS: CpuidDefinitions<6> = const { description: "guest checks this feature bit to determine that vCPUs are never preempted for an unlimited time allowing optimizations", bits_range: (0, 0), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), ]) diff --git a/arch/src/x86_64/cpuid_definitions/intel.rs b/arch/src/x86_64/cpuid_definitions/intel.rs index da9240378a..52cfcf35aa 100644 --- a/arch/src/x86_64/cpuid_definitions/intel.rs +++ b/arch/src/x86_64/cpuid_definitions/intel.rs @@ -2,8 +2,7 @@ use std::ops::RangeInclusive; use super::{ - CpuidDefinitions, CpuidReg, MigrationCompatibilityRequirement, Parameters, ProfilePolicy, - ValueDefinition, ValueDefinitions, + CpuidDefinitions, CpuidReg, Parameters, ProfilePolicy, ValueDefinition, ValueDefinitions, }; pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { @@ -22,7 +21,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Maximum Input value for Basic CPUID Information", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -36,7 +34,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU vendor ID string bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -50,7 +47,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU vendor ID string bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -64,7 +60,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU vendor ID string bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), // TODO: Do we really want to inherit these values from the corresponding CPU, or should we zero it out or set something else here? @@ -80,42 +75,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Stepping ID", bits_range: (0, 3), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "base_model", description: "Base CPU model ID", bits_range: (4, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "base_family_id", description: "Base CPU family ID", bits_range: (8, 11), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "cpu_type", description: "CPU type", bits_range: (12, 13), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "ext_model", description: "Extended CPU model ID", bits_range: (16, 19), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "ext_family", description: "Extended CPU family ID", bits_range: (20, 27), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -131,14 +120,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Brand index", bits_range: (0, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "clflush_size", description: "CLFLUSH instruction cache line size", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, // This is set by cloud hypervisor ValueDefinition { @@ -146,7 +133,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Logical CPU count", bits_range: (16, 23), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, // This is set by cloud hypervisor ValueDefinition { @@ -154,7 +140,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Initial local APIC physical ID", bits_range: (24, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -170,21 +155,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Streaming SIMD Extensions 3 (SSE3)", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pclmulqdq", description: "PCLMULQDQ instruction support", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "dtes64", description: "64-bit DS save area", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Perhaps there should be some CHV feature for opting in to enabling this for non-host CPU profiles? ValueDefinition { @@ -192,14 +174,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "MONITOR/MWAIT support", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ds_cpl", description: "CPL Qualified Debug Store", bits_range: (4, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Ideally configurable by the user (host must have this otherwise CHV will not run) ValueDefinition { @@ -207,35 +187,30 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Virtual Machine Extensions", bits_range: (5, 5), policy: ProfilePolicy::Static(1), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "smx", description: "Safer Mode Extensions", bits_range: (6, 6), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "est", description: "Enhanced Intel SpeedStep", bits_range: (7, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "tm2", description: "Thermal Monitor 2", bits_range: (8, 8), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ssse3", description: "Supplemental SSE3", bits_range: (9, 9), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -243,28 +218,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L1 Context ID", bits_range: (10, 10), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "sdbg", description: "Silicon Debug", bits_range: (11, 11), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "fma", description: "FMA extensions using YMM state", bits_range: (12, 12), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cx16", description: "CMPXCHG16B instruction support", bits_range: (13, 13), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -272,7 +243,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "xTPR Update Control", bits_range: (14, 14), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -280,35 +250,30 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Perfmon and Debug Capability", bits_range: (15, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pcid", description: "Process-context identifiers", bits_range: (17, 17), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "dca", description: "Direct Cache Access", bits_range: (18, 18), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "sse4_1", description: "SSE4.1", bits_range: (19, 19), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "sse4_2", description: "SSE4.2", bits_range: (20, 20), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // Set by Cloud hypervisor ValueDefinition { @@ -316,21 +281,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "X2APIC support", bits_range: (21, 21), policy: ProfilePolicy::Static(1), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "movbe", description: "MOVBE instruction support", bits_range: (22, 22), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "popcnt", description: "POPCNT instruction support", bits_range: (23, 23), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // Set by Cloud hypervisor ValueDefinition { @@ -338,21 +300,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "APIC timer one-shot operation", bits_range: (24, 24), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "aes", description: "AES instructions", bits_range: (25, 25), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xsave", description: "XSAVE (and related instructions) support", bits_range: (26, 26), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Seems to no longer be supported by QEMU, but is by KVM? We disable this for now. ValueDefinition { @@ -360,28 +319,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XSAVE (and related instructions) are enabled by OS", bits_range: (27, 27), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx", description: "AVX instructions support", bits_range: (28, 28), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "f16c", description: "Half-precision floating-point conversion support", bits_range: (29, 29), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "rdrand", description: "RDRAND instruction support", bits_range: (30, 30), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: If set by CHV set to 0 and write comment ValueDefinition { @@ -389,7 +344,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "System is running as guest; (para-)virtualized system", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -405,28 +359,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Floating-Point Unit on-chip (x87)", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "vme", description: "Virtual-8086 Mode Extensions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "de", description: "Debugging Extensions", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pse", description: "Page Size Extension", bits_range: (3, 3), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Does this also need special handling like TSC_DEADLINE_TIMER? ValueDefinition { @@ -434,42 +384,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Time Stamp Counter", bits_range: (4, 4), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "msr", description: "Model-Specific Registers (RDMSR and WRMSR support)", bits_range: (5, 5), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pae", description: "Physical Address Extensions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mce", description: "Machine Check Exception", bits_range: (7, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cx8", description: "CMPXCHG8B instruction", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "apic", description: "APIC on-chip", bits_range: (9, 9), policy: ProfilePolicy::Static(1), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related (maybe not necessary to look into which ones) ValueDefinition { @@ -477,128 +421,109 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "SYSENTER, SYSEXIT, and associated MSRs", bits_range: (11, 11), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mtrr", description: "Memory Type Range Registers", bits_range: (12, 12), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pge", description: "Page Global Extensions", bits_range: (13, 13), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mca", description: "Machine Check Architecture", bits_range: (14, 14), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cmov", description: "Conditional Move Instruction", bits_range: (15, 15), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pat", description: "Page Attribute Table", bits_range: (16, 16), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pse36", description: "Page Size Extension (36-bit)", bits_range: (17, 17), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "psn", description: "Processor Serial Number", bits_range: (18, 18), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "clfsh", description: "CLFLUSH instruction", bits_range: (19, 19), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ds", description: "Debug Store", bits_range: (21, 21), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "acpi", description: "Thermal monitor and clock control", bits_range: (22, 22), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mmx", description: "MMX instructions", bits_range: (23, 23), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "fxsr", description: "FXSAVE and FXRSTOR instructions", bits_range: (24, 24), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "sse", description: "SSE instructions", bits_range: (25, 25), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "sse2", description: "SSE2 instructions", bits_range: (26, 26), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ss", description: "Self Snoop", bits_range: (27, 27), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "htt", description: "Hyper-threading", bits_range: (28, 28), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "tm", description: "Thermal Monitor", bits_range: (29, 29), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, - // TODO: Remove? CpuidDescription{ short: "ia64", description: "Legacy IA-64 (Itanium) support bit, now reserved", bits_range: (30, 30), policy: ProfilePolicy::Static(0), migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits }, // TODO: Not really sure what the default should be for PBE. It seems like it is something that needs to be enabled via the IA32_MISC_ENABLE MSR hence perhaps this should be set via CPU features? // MSR related ValueDefinition { @@ -606,7 +531,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Pending Break Enable", bits_range: (31, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -625,35 +549,30 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Number of times this leaf must be queried", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc1", description: "Descriptor #1", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc2", description: "Descriptor #2", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc3", description: "Descriptor #3", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "eax_invalid", description: "Descriptors 1-3 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -669,35 +588,30 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Descriptor #4", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc5", description: "Descriptor #5", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc6", description: "Descriptor #6", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc7", description: "Descriptor #7", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "ebx_invalid", description: "Descriptors 4-7 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -713,35 +627,30 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Descriptor #8", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc9", description: "Descriptor #9", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc10", description: "Descriptor #10", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc11", description: "Descriptor #11", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "ecx_invalid", description: "Descriptors 8-11 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -757,35 +666,30 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Descriptor #12", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc13", description: "Descriptor #13", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc14", description: "Descriptor #14", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "desc15", description: "Descriptor #15", bits_range: (24, 30), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "edx_invalid", description: "Descriptors 12-15 are invalid if set", bits_range: (31, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -804,14 +708,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Cache type field", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "cache_level", description: "Cache level (1-based)", bits_range: (5, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, // TODO: Could there be a problem migrating from a CPU with self-initializing cache to one without? ValueDefinition { @@ -819,28 +721,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Self-initializing cache level", bits_range: (8, 8), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "fully_associative", description: "Fully-associative cache", bits_range: (9, 9), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "num_threads_sharing", description: "Number logical CPUs sharing this cache", bits_range: (14, 25), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "num_cores_on_die", description: "Number of cores in the physical package", bits_range: (26, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -856,21 +754,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "System coherency line size (0-based)", bits_range: (0, 11), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "cache_npartitions", description: "Physical line partitions (0-based)", bits_range: (12, 21), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "cache_nways", description: "Ways of associativity (0-based)", bits_range: (22, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -885,7 +780,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Cache number of sets (0-based)", bits_range: (0, 30), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -900,21 +794,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "WBINVD/INVD not guaranteed for Remote Lower-Level caches", bits_range: (0, 0), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "ll_inclusive", description: "Cache is inclusive of Lower-Level caches", bits_range: (1, 1), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "complex_indexing", description: "Not a direct-mapped cache (complex function)", bits_range: (2, 2), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -932,7 +823,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Smallest monitor-line size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::LtEq, }]), ), ( @@ -946,7 +836,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Largest monitor-line size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -961,14 +850,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Enumeration of MONITOR/MWAIT extensions is supported", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mwait_irq_break", description: "Interrupts as a break-event for MWAIT is supported", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -984,56 +871,48 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Number of C0 sub C-states supported using MWAIT", bits_range: (0, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c1_substates", description: "Number of C1 sub C-states supported using MWAIT", bits_range: (4, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c2_substates", description: "Number of C2 sub C-states supported using MWAIT", bits_range: (8, 11), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c3_substates", description: "Number of C3 sub C-states supported using MWAIT", bits_range: (12, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c4_substates", description: "Number of C4 sub C-states supported using MWAIT", bits_range: (16, 19), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c5_substates", description: "Number of C5 sub C-states supported using MWAIT", bits_range: (20, 23), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c6_substates", description: "Number of C6 sub C-states supported using MWAIT", bits_range: (24, 27), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_c7_substates", description: "Number of C7 sub C-states supported using MWAIT", bits_range: (28, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -1052,147 +931,126 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Digital temperature sensor", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "turbo_boost", description: "Intel Turbo Boost", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "arat", description: "Always-Running APIC Timer (not affected by p-state)", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pln", description: "Power Limit Notification (PLN) event", bits_range: (4, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ecmd", description: "Clock modulation duty cycle extension", bits_range: (5, 5), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pts", description: "Package thermal management", bits_range: (6, 6), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp", description: "HWP (Hardware P-states) base registers are supported", bits_range: (7, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_notify", description: "HWP notification (IA32_HWP_INTERRUPT MSR)", bits_range: (8, 8), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_act_window", description: "HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported", bits_range: (9, 9), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_epp", description: "HWP Energy Performance Preference", bits_range: (10, 10), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_pkg_req", description: "HWP Package Level Request", bits_range: (11, 11), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hdc_base_regs", description: "HDC base registers are supported", bits_range: (13, 13), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "turbo_boost_3_0", description: "Intel Turbo Boost Max 3.0", bits_range: (14, 14), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_capabilities", description: "HWP Highest Performance change", bits_range: (15, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_peci_override", description: "HWP PECI override", bits_range: (16, 16), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_flexible", description: "Flexible HWP", bits_range: (17, 17), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_fast", description: "IA32_HWP_REQUEST MSR fast access mode", bits_range: (18, 18), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hfi", description: "HW_FEEDBACK MSRs supported", bits_range: (19, 19), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hwp_ignore_idle", description: "Ignoring idle logical CPU HWP req is supported", bits_range: (20, 20), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "thread_director", description: "Intel thread director support", bits_range: (23, 23), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "therm_interrupt_bit25", description: "IA32_THERM_INTERRUPT MSR bit 25 is supported", bits_range: (24, 24), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -1209,7 +1067,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Digital thermometer thresholds", bits_range: (0, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -1226,7 +1083,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "MPERF/APERF MSRs (effective frequency interface)", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1234,14 +1090,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "IA32_ENERGY_PERF_BIAS MSR support", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "thrd_director_nclasses", description: "Number of classes, Intel thread director", bits_range: (8, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -1257,28 +1111,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Performance capability reporting", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "encap_reporting", description: "Energy efficiency capability reporting", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "feedback_sz", description: "Feedback interface structure size, in 4K pages", bits_range: (8, 11), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "this_lcpu_hwfdbk_idx", description: "This logical CPU hardware feedback interface index", bits_range: (16, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -1296,7 +1146,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Number of leaf 0x7 subleaves", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -1311,7 +1160,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "FSBASE/GSBASE read/write support", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1319,7 +1167,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "IA32_TSC_ADJUST MSR supported", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // SGX is deprecated so we disable it unconditionally for all CPU profiles ValueDefinition { @@ -1327,14 +1174,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel SGX (Software Guard Extensions)", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "bmi1", description: "Bit manipulation extensions group 1", bits_range: (3, 3), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TSX related which is riddled with CVEs. Consider two profiles, or making it opt-in/out. QEMU always has a CPU model with and without TSX. ValueDefinition { @@ -1342,14 +1187,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Hardware Lock Elision", bits_range: (4, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx2", description: "AVX2 instruction set", bits_range: (5, 5), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, /*The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). @@ -1363,28 +1206,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "FPU Data Pointer updated only on x87 exceptions", bits_range: (6, 6), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "smep", description: "Supervisor Mode Execution Protection", bits_range: (7, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "bmi2", description: "Bit manipulation extensions group 2", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "erms", description: "Enhanced REP MOVSB/STOSB", bits_range: (9, 9), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, /* The instruction enabled by this seems rather powerful. Are we sure that doesn't have security implications? @@ -1395,7 +1234,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "INVPCID instruction (Invalidate Processor Context ID)", bits_range: (10, 10), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // This is TSX related. TSX is riddled with CVEs: Consider two profiles (one with it disabled) or an opt-in/out feature. ValueDefinition { @@ -1403,14 +1241,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel restricted transactional memory", bits_range: (11, 11), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "rdt_m", description: "Supports Intel Resource Director Technology Monitoring Capability if 1", bits_range: (12, 12), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // The KVM docs recommend always setting this (https://docs.kernel.org/virt/kvm/x86/errata.html#kvm-get-supported-cpuid-issues). TODO: Is it OK to just set this to 1? ValueDefinition { @@ -1418,7 +1254,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Deprecates FPU CS and FPU DS values if 1", bits_range: (13, 13), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // This has been deprecated ValueDefinition { @@ -1426,7 +1261,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel memory protection extensions", bits_range: (14, 14), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // This might be useful for certain high performance applications, but it also seems like a rather niche and advanced feature. QEMU does also not automatically enable this from what we can tell. // TODO: Should we make this OPT-IN? @@ -1435,7 +1269,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel RDT-A. Supports Intel Resource Director Technology Allocation Capability if 1", bits_range: (15, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Do the wider avx512 zmm registers work out of the box when the hardware supports it? ValueDefinition { @@ -1443,105 +1276,90 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "AVX-512 foundation instructions", bits_range: (16, 16), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512dq", description: "AVX-512 double/quadword instructions", bits_range: (17, 17), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "rdseed", description: "RDSEED instruction", bits_range: (18, 18), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "adx", description: "ADCX/ADOX instructions", bits_range: (19, 19), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "smap", description: "Supervisor mode access prevention", bits_range: (20, 20), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512ifma", description: "AVX-512 integer fused multiply add", bits_range: (21, 21), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "clflushopt", description: "CLFLUSHOPT instruction", bits_range: (23, 23), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "clwb", description: "CLWB instruction", bits_range: (24, 24), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "intel_pt", description: "Intel processor trace", bits_range: (25, 25), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512pf", description: "AVX-512 prefetch instructions", bits_range: (26, 26), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512er", description: "AVX-512 exponent/reciprocal instructions", bits_range: (27, 27), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512cd", description: "AVX-512 conflict detection instructions", bits_range: (28, 28), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "sha_ni", description: "SHA/SHA256 instructions", bits_range: (29, 29), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512bw", description: "AVX-512 byte/word instructions", bits_range: (30, 30), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512vl", description: "AVX-512 VL (128/256 vector length) extensions", bits_range: (31, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -1557,14 +1375,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "PREFETCHWT1 (Intel Xeon Phi only)", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512vbmi", description: "AVX-512 Vector byte manipulation instructions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // Also set by QEMU for CPU models from what we can tell ValueDefinition { @@ -1572,7 +1388,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "User mode instruction protection", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // Also set by QEMU for CPU models from what we can tell ValueDefinition { @@ -1580,14 +1395,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Protection keys for user-space", bits_range: (3, 3), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ospke", description: "OS protection keys enable", bits_range: (4, 4), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: QEMU seems to set this unconditionally whenever KVM supports it (TODO: Would it be best to set this unconditionally?) ValueDefinition { @@ -1595,14 +1408,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "WAITPKG instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512_vbmi2", description: "AVX-512 vector byte manipulation instructions group 2", bits_range: (6, 6), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: This may be useful for nested virtualization? Perhaps it should be opt-in rather than unconditionally disabled? ValueDefinition { @@ -1610,42 +1421,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CET shadow stack features", bits_range: (7, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "gfni", description: "Galois field new instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "vaes", description: "Vector AES instructions", bits_range: (9, 9), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "vpclmulqdq", description: "VPCLMULQDQ 256-bit instruction support", bits_range: (10, 10), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512_vnni", description: "Vector neural network instructions", bits_range: (11, 11), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512_bitalg", description: "AVX-512 bitwise algorithms", bits_range: (12, 12), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // Seems to be TDX related which is experimental in CHV. We disable this for CPU profiles for now, but could potentially add it as an opt-in feature eventually. ValueDefinition { @@ -1653,28 +1458,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel total memory encryption", bits_range: (13, 13), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512_vpopcntdq", description: "AVX-512: POPCNT for vectors of DWORD/QWORD", bits_range: (14, 14), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "la57", description: "57-bit linear addresses (five-level paging)", bits_range: (16, 16), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mawau_val_lm", description: "BNDLDX/BNDSTX MAWAU value in 64-bit mode", bits_range: (17, 21), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // MSR related ValueDefinition { @@ -1682,7 +1483,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "RDPID instruction", bits_range: (22, 22), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // We leave key locker support out for CPU profiles for the time being. We may want this to be opt-in in the future though ValueDefinition { @@ -1690,42 +1490,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel key locker support", bits_range: (23, 23), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "bus_lock_detect", description: "OS bus-lock detection", bits_range: (24, 24), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cldemote", description: "CLDEMOTE instruction", bits_range: (25, 25), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "movdiri", description: "MOVDIRI instruction", bits_range: (27, 27), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "movdir64b", description: "MOVDIR64B instruction", bits_range: (28, 28), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "enqcmd", description: "Enqueue stores supported (ENQCMD{,S})", bits_range: (29, 29), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // SGX support is deprecated so we disable it unconditionally for CPU profiles ValueDefinition { @@ -1733,14 +1527,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel SGX launch configuration", bits_range: (30, 30), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pks", description: "Protection keys for supervisor-mode pages", bits_range: (31, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -1757,42 +1549,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel SGX attestation services", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512_4vnniw", description: "AVX-512 neural network instructions (Intel Xeon Phi only?)", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512_4fmaps", description: "AVX-512 multiply accumulation single precision (Intel Xeon Phi only?)", bits_range: (3, 3), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "fsrm", description: "Fast short REP MOV", bits_range: (4, 4), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "uintr", description: "CPU supports user interrupts", bits_range: (5, 5), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512_vp2intersect", description: "VP2INTERSECT{D,Q} instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1800,42 +1586,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "SRBDS mitigation MSR available: If 1, enumerates support for the IA32_MCU_OPT_CTRL MSR and indicates that its bit 0 (RNGDS_MITG_DIS) is also supported.", bits_range: (9, 9), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "md_clear", description: "VERW MD_CLEAR microcode support", bits_range: (10, 10), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "rtm_always_abort", description: "XBEGIN (RTM transaction) always aborts", bits_range: (11, 11), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "tsx_force_abort", description: "MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported", bits_range: (13, 13), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "serialize", description: "SERIALIZE instruction", bits_range: (14, 14), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hybrid_cpu", description: "The CPU is identified as a 'hybrid part'", bits_range: (15, 15), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: This is TSX related which is riddled with CVEs. We could consider an additional profile enabling TSX in the future, but we leave it out for now. ValueDefinition { @@ -1843,7 +1623,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "TSX suspend/resume load address tracking", bits_range: (16, 16), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // Might be relevant for confidential computing ValueDefinition { @@ -1851,7 +1630,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "PCONFIG instruction", bits_range: (18, 18), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1859,7 +1637,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel architectural LBRs", bits_range: (19, 19), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure if this is the best default, but QEMU also seems to disable this for CPU models ValueDefinition { @@ -1867,35 +1644,30 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CET indirect branch tracking", bits_range: (20, 20), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_bf16", description: "AMX-BF16: tile bfloat16 support", bits_range: (22, 22), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512_fp16", description: "AVX-512 FP16 instructions", bits_range: (23, 23), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_tile", description: "AMX-TILE: tile architecture support", bits_range: (24, 24), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_int8", description: "AMX-INT8: tile 8-bit integer support", bits_range: (25, 25), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1903,7 +1675,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Speculation Control (IBRS/IBPB: indirect branch restrictions)", bits_range: (26, 26), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1911,7 +1682,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Single thread indirect branch predictors", bits_range: (27, 27), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1919,7 +1689,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "FLUSH L1D cache: IA32_FLUSH_CMD MSR", bits_range: (28, 28), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1927,7 +1696,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Intel IA32_ARCH_CAPABILITIES MSR", bits_range: (29, 29), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1935,7 +1703,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "IA32_CORE_CAPABILITIES MSR", bits_range: (30, 30), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -1943,7 +1710,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Speculative store bypass disable", bits_range: (31, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -1962,21 +1728,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "SHA-512 extensions", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "sm3", description: "SM3 instructions", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "sm4", description: "SM4 instructions", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // RAO-INT is deprecated and removed from most compilers as far as we are aware ValueDefinition { @@ -1984,21 +1747,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "RAO-INT instructions", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx_vnni", description: "AVX-VNNI instructions", bits_range: (4, 4), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx512_bf16", description: "AVX-512 bfloat16 instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, /* Not set in QEMU from what we can tell, but according seems to be fine to expose this to guests @@ -2010,119 +1770,102 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Linear address space separation", bits_range: (6, 6), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cmpccxadd", description: "CMPccXADD instructions", bits_range: (7, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "arch_perfmon_ext", description: "ArchPerfmonExt: leaf 0x23 is supported", bits_range: (8, 8), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "fzrm", description: "Fast zero-length REP MOVSB", bits_range: (10, 10), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "fsrs", description: "Fast short REP STOSB", bits_range: (11, 11), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "fsrc", description: "Fast Short REP CMPSB/SCASB", bits_range: (12, 12), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "fred", description: "FRED: Flexible return and event delivery transitions", bits_range: (17, 17), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lkgs", description: "LKGS: Load 'kernel' (userspace) GS", bits_range: (18, 18), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "wrmsrns", description: "WRMSRNS instruction (WRMSR-non-serializing)", bits_range: (19, 19), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "nmi_src", description: "NMI-source reporting with FRED event data", bits_range: (20, 20), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_fp16", description: "AMX-FP16: FP16 tile operations", bits_range: (21, 21), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "hreset", description: "History reset support", bits_range: (22, 22), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx_ifma", description: "Integer fused multiply add", bits_range: (23, 23), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lam", description: "Linear address masking", bits_range: (26, 26), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "rd_wr_msrlist", description: "RDMSRLIST/WRMSRLIST instructions", bits_range: (27, 27), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "invd_disable_post_bios_done", description: "If 1, supports INVD execution prevention after BIOS Done", bits_range: (30, 30), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "movrs", description: "MOVRS", bits_range: (31, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -2138,7 +1881,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Protected processor inventory number (PPIN{,_CTL} MSRs)", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2146,7 +1888,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "PBNDKB instruction supported and enumerates the existence of the IA32_TSE_CAPABILITY MSR", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -2165,14 +1906,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "AVX-VNNI-INT8 instructions", bits_range: (4, 4), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx_ne_convert", description: "AVX-NE-CONVERT instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the value will be zeroed out if the user has not opted in for "amx" via CpuFeatures. ValueDefinition { @@ -2180,28 +1919,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "AMX-COMPLEX instructions (starting from Granite Rapids)", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx_vnni_int16", description: "AVX-VNNI-INT16 instructions", bits_range: (10, 10), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "utmr", description: "If 1, supports user-timer events", bits_range: (13, 13), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "prefetchit_0_1", description: "PREFETCHIT0/1 instructions", bits_range: (14, 14), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2209,42 +1944,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "If 1, supports the URDMSR and UWRMSR instructions", bits_range: (15, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "uiret_uif", description: "If 1, UIRET sets UIF to the value of bit 1 of the RFLAGS image loaded from the stack", bits_range: (15, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cet_sss", description: "CET supervisor shadow stacks safe to use", bits_range: (18, 18), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "avx10", description: "If 1, supports the Intel AVX10 instructions and indicates the presence of leaf 0x24", bits_range: (19, 19), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "apx_f", description: "If 1, the processor provides foundational support for Intel Advanced Performance Extensions", bits_range: (21, 21), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mwait", description: "If 1, MWAIT is supported even if (0x1 ECX bit 3 (monitor) is enumerated as 0)", bits_range: (23, 23), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2252,7 +1981,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "If 1, indicates bit 0 of the IA32_INTEGRITY_STATUS MSR is supported. Bit 0 of this MSR indicates whether static lockstep is active on this logical processor", bits_range: (24, 24), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -2272,7 +2000,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "If 1, indicates bit 7 of the IA32_SPEC_CTRL_MSR is supported. Bit 7 of this MSR disables fast store forwarding predictor without disabling speculative store bypass", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2280,7 +2007,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2288,7 +2014,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2296,7 +2021,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "MSR bit IA32_SPEC_CTRL.DDPD_U", bits_range: (3, 3), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2304,7 +2028,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "MSR bit IA32_SPEC_CTRL.BHI_DIS_S", bits_range: (4, 4), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2312,7 +2035,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "MCDT mitigation not needed", bits_range: (5, 5), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2320,7 +2042,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "UC-lock disable is supported", bits_range: (6, 6), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -2340,7 +2061,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1f8H)", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -2361,28 +2081,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Performance monitoring unit version ID", bits_range: (0, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "pmu_n_gcounters", description: "Number of general PMU counters per logical CPU", bits_range: (8, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "pmu_gcounters_nbits", description: "Bitwidth of PMU general counters", bits_range: (16, 23), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "pmu_cpuid_ebx_bits", description: "Length of leaf 0xa EBX bit vector", bits_range: (24, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -2398,56 +2114,48 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Core cycle event not available", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_insn_retired_evt", description: "Instruction retired event not available", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_refcycle_evt", description: "Reference cycles event not available", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_llc_ref_evt", description: "LLC-reference event not available", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_llc_miss_evt", description: "LLC-misses event not available", bits_range: (4, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_br_insn_ret_evt", description: "Branch instruction retired event not available", bits_range: (5, 5), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_br_mispredict_evt", description: "Branch mispredict retired event not available", bits_range: (6, 6), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "no_td_slots_evt", description: "Topdown slots event not available", bits_range: (7, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -2462,7 +2170,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Fixed-function PMU counters support bitmap", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -2477,21 +2184,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Number of fixed PMU counters", bits_range: (0, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "pmu_fcounters_nbits", description: "Bitwidth of PMU fixed counters", bits_range: (5, 12), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "anythread_depr", description: "AnyThread deprecation", bits_range: (15, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -2512,7 +2216,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Bit width of this level (previous levels inclusive)", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), // Set by VMM/user provided config @@ -2527,7 +2230,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Logical CPUs count across all instances of this domain", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), // Set by VMM/user provided config @@ -2543,14 +2245,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "This domain level (subleaf ID)", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "domain_type", description: "This domain type", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -2566,7 +2266,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "x2APIC ID of current logical CPU", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), // =================================================================================================================== @@ -2586,21 +2285,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XCR0.X87 (bit 0) supported", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xcr0_sse", description: "XCR0.SEE (bit 1) supported", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xcr0_avx", description: "XCR0.AVX (bit 2) supported", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MPX is deprecated ValueDefinition { @@ -2608,7 +2304,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MPX is deprecated ValueDefinition { @@ -2616,28 +2311,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)", bits_range: (4, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xcr0_avx512_opmask", description: "XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)", bits_range: (5, 5), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xcr0_avx512_zmm_hi256", description: "XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)", bits_range: (6, 6), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xcr0_avx512_hi16_zmm", description: "XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)", bits_range: (7, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // MSR related ValueDefinition { @@ -2645,21 +2336,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XCR0.IA32_XSS (bit 8) used for IA32_XSS", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xcr0_pkru", description: "XCR0.PKRU (bit 9) supported (XSAVE PKRU registers)", bits_range: (9, 9), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xcr0_ia32_xss_bits", description: "XCR0.IA32_XSS (bit 10 - 16) used for IA32_XSS", bits_range: (10, 16), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. ValueDefinition { @@ -2667,7 +2355,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)", bits_range: (17, 17), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bits that userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. ValueDefinition { @@ -2675,7 +2362,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA)", bits_range: (18, 18), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -2692,7 +2378,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XSAVE/XRSTOR area byte size, for XCR0 enabled features", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -2709,7 +2394,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XSAVE/XRSTOR area max byte size, all CPU features", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -2724,7 +2408,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Reports the valid bit fields of the upper 32 bits of the XCR0 register", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), // =================================================================================================================== @@ -2742,21 +2425,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XSAVEOPT instruction", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xsavec", description: "XSAVEC instruction", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "xgetbv1", description: "XGETBV instruction with ECX = 1", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Can this have security implications in terms of supervisor state getting exposed? ValueDefinition { @@ -2764,7 +2444,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XSAVES/XRSTORS instructions (and XSS MSR)", bits_range: (3, 3), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // NOTE: AMX currently requires opt-in, even for the host CPU profile. We still inherit this value for profiles as the relevant feature bitssthat userspae applications must check will be zeroed out if the user has not opted in for "amx" via CpuFeatures. ValueDefinition { @@ -2772,7 +2451,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Extended feature disable support", bits_range: (4, 4), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -2789,7 +2467,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "XSAVE area size, all XCR0 and IA32_XSS features enabled", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -2807,7 +2484,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Used for XCR0", bits_range: (0, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: Not sure about the profile pilicy here ValueDefinition { @@ -2815,7 +2491,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "PT state, supported", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure what profile policy to set here ValueDefinition { @@ -2823,7 +2498,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Used for XCR0", bits_range: (9, 9), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure about the profile pilicy here ValueDefinition { @@ -2831,7 +2505,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "PASID state, supported", bits_range: (10, 10), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure about the profile pilicy here ValueDefinition { @@ -2839,7 +2512,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CET user state, supported", bits_range: (11, 11), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure about the profile pilicy here ValueDefinition { @@ -2847,7 +2519,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CET supervisor state, supported", bits_range: (12, 12), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure about the profile pilicy here ValueDefinition { @@ -2855,7 +2526,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "HDC state, supported", bits_range: (13, 13), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure about the profile pilicy here ValueDefinition { @@ -2863,7 +2533,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "UINTR state, supported", bits_range: (14, 14), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure about the profile pilicy here ValueDefinition { @@ -2871,7 +2540,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "LBR state, supported", bits_range: (15, 15), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure about the profile pilicy here ValueDefinition { @@ -2879,7 +2547,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "HWP state, supported", bits_range: (16, 16), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Not sure what profile policy to set here ValueDefinition { @@ -2887,7 +2554,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Used for XCR0", bits_range: (17, 18), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -2905,7 +2571,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: " Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32 ] can be set to 1 only if EDX[n] = 1", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -2930,7 +2595,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Size of save area for subleaf-N feature, in bytes", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -2944,7 +2608,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Offset of save area for subleaf-N feature, in bytes", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -2959,14 +2622,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Subleaf N describes an XSS bit, otherwise XCR0 bit", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "compacted_xsave_64byte_aligned", description: "When compacted, subleaf-N feature XSAVE area is 64-byte aligned", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: This may depend on the "amx" feature? ValueDefinition { @@ -2974,7 +2635,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Indicates support for xfd faulting", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -2990,7 +2650,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "This leaf has been zeroed out because MPX state components are disabled", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -3004,7 +2663,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "This leaf has been zeroed out because MPX state components are disabled", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -3018,7 +2676,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "This leaf has been zeroed out because MPX state components are disabled", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -3032,7 +2689,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "This leaf has been zeroed out because MPX state components are disabled", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -3046,7 +2702,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Size of save area for subleaf-N feature, in bytes", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -3060,7 +2715,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Offset of save area for subleaf-N feature, in bytes", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -3075,14 +2729,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Subleaf N describes an XSS bit, otherwise XCR0 bit", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "compacted_xsave_64byte_aligned", description: "When compacted, subleaf-N feature XSAVE area is 64-byte aligned", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: This may depend on the "amx" feature? ValueDefinition { @@ -3090,7 +2742,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Indicates support for xfd faulting", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -3108,7 +2759,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "RMID max, within this core, all types (0-based)", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -3124,7 +2774,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Supports L3 Cache Intel RDT Monitoring if 1", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -3144,28 +2793,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L3 QoS-monitoring counter bitwidth (24-based)", bits_range: (0, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "l3c_qm_overflow_bit", description: "QM_CTR MSR bit 61 is an overflow bit", bits_range: (8, 8), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "l3c_qm_non_cpu_agent", description: "If 1, indicates the presence of non-CPU agent Intel RDT CTM support", bits_range: (9, 9), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "l3c_qm_non_cpu_agent", description: "If 1, indicates the presence of non-CPU agent Intel RDT MBM support", bits_range: (10, 10), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -3181,7 +2826,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "QM_CTR MSR conversion factor to bytes", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -3196,7 +2840,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L3 QoS-monitoring max RMID", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -3211,21 +2854,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L3 QoS occupancy monitoring supported", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cqm_mbm_total", description: "L3 QoS total bandwidth monitoring supported", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cqm_mbm_local", description: "L3 QoS local bandwidth monitoring supported", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -3245,21 +2885,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L3 Cache Allocation Technology supported", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "cat_l2", description: "L2 Cache Allocation Technology supported", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "mba", description: "Memory Bandwidth Allocation supported", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -3277,7 +2914,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L3_CAT capacity bitmask length, minus-one notation", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, /* TODO: ? */ - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, /* TODO: ? */ }]), ), ( @@ -3291,7 +2927,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L3_CAT bitmap of allocation units", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, /* TODO: ? */ - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, /* TODO: ? */ }]), ), ( @@ -3307,21 +2942,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L3_CAT for non-CPU agent is supported", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cdp_l3", description: "L3/L2_CAT CDP (Code and Data Prioritization)", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cat_sparse_1s", description: "L3/L2_CAT non-contiguous 1s value supported", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -3337,7 +2969,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Highest COS number supported for this ResID", bits_range: (0, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), // =================================================================================================================== @@ -3354,7 +2985,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L2_CAT capacity bitmask length, minus-one notation", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, /* TODO: ? */ - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, /* TODO: ? */ }]), ), ( @@ -3368,7 +2998,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L2_CAT bitmap of allocation units", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, /* TODO: ? */ - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, /* TODO: ? */ }]), ), ( @@ -3382,7 +3011,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Highest COS number supported for this ResID", bits_range: (0, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -3398,14 +3026,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L2_CAT CDP (Code and Data Prioritization)", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "cat_sparse_1s", description: "L2_CAT non-contiguous 1s value supported", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -3425,7 +3051,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Max MBA throttling value; minus-one notation", bits_range: (0, 11), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }, ]), ), @@ -3441,14 +3066,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Per-thread MBA controls are supported", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mba_delay_linear", description: "Delay values are linear", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -3463,7 +3086,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "MBA max Class of Service supported", bits_range: (0, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), // =================================================================================================================== @@ -3483,7 +3105,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Max Core throttling level supported by the corresponding ResID", bits_range: (0, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }, // TODO: Not sure about the short name ValueDefinition { @@ -3491,7 +3112,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "If 1, indicates the logical processor scope of the IA32_QoS_Core_BW_Thrtl_n MSRs. Other values are reserved", bits_range: (8, 11), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -3506,7 +3126,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "The response of the bandwidth control is approximately linear", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -3520,7 +3139,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Core max Class of Service supported", bits_range: (0, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), // SGX is already disabled and deprecated so we don't need to worry about leaf 0x12 and its subleaves @@ -3539,7 +3157,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Maximum leaf 0x14 subleaf", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -3554,63 +3171,54 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "IA32_RTIT_CR3_MATCH is accessible", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "psb_cyc", description: "Configurable PSB and cycle-accurate mode", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ip_filtering", description: "IP/TraceStop filtering; Warm-reset PT MSRs preservation", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mtc_timing", description: "MTC timing packet; COFI-based packets suppression", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ptwrite", description: "PTWRITE support", bits_range: (4, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "power_event_trace", description: "Power Event Trace support", bits_range: (5, 5), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "psb_pmi_preserve", description: "PSB and PMI preservation support", bits_range: (6, 6), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "event_trace", description: "Event Trace packet generation through IA32_RTIT_CTL.EventEn", bits_range: (7, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "tnt_disable", description: "TNT packet generation disable through IA32_RTIT_CTL.DisTNT", bits_range: (8, 8), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -3626,35 +3234,30 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "ToPA output scheme support", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "topa_multiple_entries", description: "ToPA tables can hold multiple entries", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "single_range_output", description: "Single-range output scheme supported", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "trance_transport_output", description: "Trace Transport subsystem output support", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ip_payloads_lip", description: "IP payloads have LIP values (CS base included)", bits_range: (31, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -3673,14 +3276,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Filtering number of configurable Address Ranges", bits_range: (0, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "mtc_periods_bmp", description: "Bitmap of supported MTC period encodings", bits_range: (16, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -3696,14 +3297,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Bitmap of supported Cycle Threshold encodings", bits_range: (0, 15), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "psb_periods_bmp", description: "Bitmap of supported Configurable PSB frequency encodings", bits_range: (16, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -3723,7 +3322,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Denominator of the TSC/'core crystal clock' ratio", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -3737,7 +3335,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Numerator of the TSC/'core crystal clock' ratio", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -3751,7 +3348,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Core crystal clock nominal frequency, in Hz", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), // =================================================================================================================== @@ -3768,7 +3364,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Processor base frequency, in MHz", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -3782,7 +3377,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Processor max frequency, in MHz", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -3796,7 +3390,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Bus reference frequency, in MHz", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), // =================================================================================================================== @@ -3815,7 +3408,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Maximum leaf 0x17 subleaf", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), // =================================================================================================================== @@ -3834,7 +3426,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Maximum leaf 0x18 subleaf", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -3849,42 +3440,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "TLB 4KB-page entries supported", bits_range: (0, 0), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "tlb_2m_page", description: "TLB 2MB-page entries supported", bits_range: (1, 1), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "tlb_4m_page", description: "TLB 4MB-page entries supported", bits_range: (2, 2), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "tlb_1g_page", description: "TLB 1GB-page entries supported", bits_range: (3, 3), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "hard_partitioning", description: "(Hard/Soft) partitioning between logical CPUs sharing this structure", bits_range: (8, 10), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "n_way_associative", description: "Ways of associativity", bits_range: (16, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -3899,7 +3484,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Number of sets", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -3914,28 +3498,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Translation cache type (TLB type)", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "tlb_cache_level", description: "Translation cache level (1-based)", bits_range: (5, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "is_fully_associative", description: "Fully-associative structure", bits_range: (8, 8), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "tlb_max_addressible_ids", description: "Max number of addressable IDs for logical CPUs sharing this TLB - 1", bits_range: (14, 25), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -3958,70 +3538,60 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Max stack depth (number of LBR entries) = 8", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_16", description: "Max stack depth (number of LBR entries) = 16", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_24", description: "Max stack depth (number of LBR entries) = 24", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_32", description: "Max stack depth (number of LBR entries) = 32", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_40", description: "Max stack depth (number of LBR entries) = 40", bits_range: (4, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_48", description: "Max stack depth (number of LBR entries) = 48", bits_range: (5, 5), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_56", description: "Max stack depth (number of LBR entries) = 56", bits_range: (6, 6), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_depth_64", description: "Max stack depth (number of LBR entries) = 64", bits_range: (7, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_deep_c_reset", description: "LBRs maybe cleared on MWAIT C-state > C1", bits_range: (30, 30), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_ip_is_lip", description: "LBR IP contain Last IP, otherwise effective IP", bits_range: (31, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -4037,21 +3607,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_branch_filter", description: "Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_call_stack", description: "Call-stack mode (IA32_LBR_CTL[3] = 1) supported", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -4067,28 +3634,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Branch misprediction bit supported (IA32_LBR_x_INFO[63])", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_timed_lbr", description: "Timed LBRs (CPU cycles since last LBR entry) supported", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_branch_type", description: "Branch type field (IA32_LBR_INFO_x[59:56]) supported", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_events_gpc_bmp", description: "LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters", bits_range: (16, 19), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -4107,7 +3670,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Highest palette ID / subleaf ID", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), // =================================================================================================================== @@ -4126,14 +3688,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "AMX palette total tiles size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, /* require equality as this can impact XSAVE */ }, ValueDefinition { short: "amx_tile_size", description: "AMX single tile's size, in bytes", bits_range: (16, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -4149,14 +3709,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "AMX tile single row's size, in bytes", bits_range: (0, 15), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "amx_palette_nr_tiles", description: "AMX palette number of tiles", bits_range: (16, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, /* Can affect XSAVE hence require equality here */ }, ]), ), @@ -4171,7 +3729,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "AMX tile max number of rows", bits_range: (0, 15), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), // =================================================================================================================== @@ -4189,7 +3746,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Reports the maximum number of sub-leaves that are supported in leaf 0x1e", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -4204,14 +3760,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "TMUL unit maximum height, K (rows or columns)", bits_range: (0, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, /* TODO: OR should we go with Eq? */ }, ValueDefinition { short: "tmul_maxn", description: "TMUL unit maximum SIMD dimension, N (column bytes)", bits_range: (8, 23), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, /* TODO: Or should we go with Eq? */ }, ]), ), @@ -4232,63 +3786,54 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "If 1, the processor supports tile computational operations on 8-bit integers", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_bf16", description: "If 1, the processor supports tile computational operations on bfloat16 numbers", bits_range: (1, 1), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_complex", description: "If 1, the processor supports the AMX-COMPLEX instructions", bits_range: (2, 2), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_fp16", description: "If 1, the processor supports tile computational operations on FP16 numbers", bits_range: (3, 3), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_fp8", description: "If 1, the processor supports tile computational operations on FP8 numbers", bits_range: (4, 4), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_transpose", description: "If 1, the processor supports the AMX-TRANSPOSE instructions", bits_range: (5, 5), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_tf32", description: "If 1, the processor supports the AMX-TF32 (FP19) instructions", bits_range: (6, 6), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_avx512", description: "If 1, the processor supports the AMX-AVX512 instructions", bits_range: (7, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "amx_movrs", description: "If 1, the processor supports the AMX-MOVRS instructions", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -4308,7 +3853,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Bit width of this level (previous levels inclusive)", bits_range: (0, 4), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -4322,7 +3866,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Logical CPUs count across all instances of this domain", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -4337,14 +3880,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "This domain level (subleaf ID)", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "domain_type", description: "This domain type", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -4359,7 +3900,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "x2APIC ID of current logical CPU", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), // =================================================================================================================== @@ -4376,7 +3916,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPUID 0x20 max subleaf + 1", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -4390,7 +3929,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "HRESET of Intel thread director is supported", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), // =================================================================================================================== @@ -4409,7 +3947,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "TDX vendor ID string bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -4423,7 +3960,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU vendor ID string bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), ( @@ -4437,7 +3973,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU vendor ID string bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }]), ), // =================================================================================================================== @@ -4455,42 +3990,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "If 1, subleaf 0 exists", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_1", description: "If 1, subleaf 1 exists", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_2", description: "If 1, subleaf 2 exists", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_3", description: "If 1, subleaf 3 exists", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_4", description: "If 1, subleaf 4 exists", bits_range: (4, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "subleaf_5", description: "If 1, subleaf 5 exists. The processor suppots Architectural PEBS. The IA32_PEBS_BASE and IA32_PEBS_INDEX MSRs exist", bits_range: (5, 5), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -4506,21 +4035,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "IA32_PERFEVTSELx MSRs UnitMask2 is supported", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "eq_bit", description: "equal flag in the IA32_PERFEVTSELx MSR is supported", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "RDPMC_USR_DISABLE", description: "RDPMC_USR_DISABLE", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -4537,7 +4063,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Number of slots per cycle. This number can be multiplied by the number of cycles (from CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.CORE or IA32_FIXED_CTR1) to determine the total number of slots", bits_range: (0, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ]), ), @@ -4555,7 +4080,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "General-purpose PMU counters bitmap", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), ( @@ -4569,7 +4093,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Fixed PMU counters bitmap", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), // =================================================================================================================== @@ -4586,7 +4109,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Bitmap of Auto Counter Reload (ACR) general-purpose counters that can be reloaded", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), // =================================================================================================================== @@ -4604,91 +4126,78 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Core cycles event supported", bits_range: (0, 0), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "insn_retired_evt", description: "Instructions retired event supported", bits_range: (1, 1), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "ref_cycles_evt", description: "Reference cycles event supported", bits_range: (2, 2), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "llc_refs_evt", description: "Last-level cache references event supported", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "llc_misses_evt", description: "Last-level cache misses event supported", bits_range: (4, 4), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "br_insn_ret_evt", description: "Branch instruction retired event supported", bits_range: (5, 5), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "br_mispr_evt", description: "Branch mispredict retired event supported", bits_range: (6, 6), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_slots_evt", description: "Topdown slots event supported", bits_range: (7, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_backend_bound_evt", description: "Topdown backend bound event supported", bits_range: (8, 8), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_bad_spec_evt", description: "Topdown bad speculation event supported", bits_range: (9, 9), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_frontend_bound_evt", description: "Topdown frontend bound event supported", bits_range: (10, 10), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "td_retiring_evt", description: "Topdown retiring event support", bits_range: (11, 11), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lbr_inserts", description: "LBR support", bits_range: (12, 12), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -4707,7 +4216,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Should the migration compatibility check rather be CintainsBits? ValueDefinition { @@ -4715,7 +4223,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", bits_range: (0, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: Should the migration compatibility check rather be CintainsBits? ValueDefinition { @@ -4723,7 +4230,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "LBR group and both bits [41:40] are available", bits_range: (8, 9), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: Should the migration compatibility check rather be CintainsBits? ValueDefinition { @@ -4731,21 +4237,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "These bits correspond to XER group bits [55:49]", bits_range: (17, 23), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "grp", description: "If 1, the GRP group is available", bits_range: (29, 29), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "aux", description: "If 1, the AUX group is available", bits_range: (30, 30), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -4761,7 +4264,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "If 1, indicates that the ALLOW_IN_RECORD bit is available in the IA32_PMC_GPn_CFG_C and IA32_PMC_FXm_CFG_C MSRs", bits_range: (3, 3), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Should the migration compatibility check rather be CintainsBits? ValueDefinition { @@ -4769,7 +4271,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Counters group sub-groups general-purpose counters, fixed-function counters, and performance metrics are available", bits_range: (0, 7), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: Should the migration compatibility check rather be CintainsBits? ValueDefinition { @@ -4777,7 +4278,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "LBR group and both bits [41:40] are available", bits_range: (8, 9), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, // TODO: Should the migration compatibility check rather be CintainsBits? ValueDefinition { @@ -4785,21 +4285,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "These bits correspond to XER group bits [55:49]", bits_range: (17, 23), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::Eq, }, ValueDefinition { short: "grp", description: "If 1, the GRP group is available", bits_range: (29, 29), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "aux", description: "If 1, the AUX group is available", bits_range: (30, 30), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -4817,7 +4314,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "General-purpose counters support Architectural PEBS. Bit vector of general-purpose counters for which the Architectural PEBS mechanism is available", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), ( @@ -4831,7 +4327,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "General-purpose counters for which PEBS support PDIST", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), ( @@ -4845,7 +4340,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Fixed-function counters support Architectural PEBS. Bit vector of fixed-function counters for which the Architectural PEBS mechanism is available. If ECX[x] == 1, then the IA32_PMC_FXm_CFG_C MSR is available, and PEBS is supported", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), ( @@ -4859,7 +4353,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Fixed-function counters for which PEBS supports PDIST", bits_range: (0, 31), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), // =================================================================================================================== @@ -4876,7 +4369,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Reports the maximum number of sub-leaves that are supported in leaf 0x24", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -4891,14 +4383,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Reports the intel AVX10 Converged Vector ISA version", bits_range: (0, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }, ValueDefinition { short: "avx_10_lengths", description: "Reserved at 111", bits_range: (0, 7), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -4918,7 +4408,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Maximum extended CPUID leaf supported", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::GtEq, }]), ), ( @@ -4932,7 +4421,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Vendor ID string bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -4946,7 +4434,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Vendor ID string bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -4960,7 +4447,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Vendor ID string bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -4976,42 +4462,36 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Stepping ID", bits_range: (0, 3), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "e_base_model", description: "Base processor model", bits_range: (4, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "e_base_family", description: "Base processor family", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "e_base_type", description: "Base processor type (Transmeta)", bits_range: (12, 13), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "e_ext_model", description: "Extended processor model", bits_range: (16, 19), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "e_ext_family", description: "Extended processor family", bits_range: (20, 27), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -5027,14 +4507,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Brand ID", bits_range: (0, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "pkg_type", description: "Package type", bits_range: (28, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -5050,21 +4528,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "LAHF and SAHF in 64-bit mode", bits_range: (0, 0), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lzcnt", description: "LZCNT advanced bit manipulation", bits_range: (5, 5), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "prefetchw", description: "3DNow PREFETCH/PREFETCHW support", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -5080,21 +4555,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "SYSCALL and SYSRET instructions", bits_range: (11, 11), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "nx", description: "Execute Disable Bit available", bits_range: (20, 20), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "pdpe1gb", description: "1-GB large page support", bits_range: (26, 26), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, // TODO: Should this perhaps be overwritten to 0 and require opt-in via a feature? ValueDefinition { @@ -5102,14 +4574,12 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "RDTSCP instruction and IA32_TSC_AUX are available", bits_range: (27, 27), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ValueDefinition { short: "lm", description: "Long mode (x86-64, 64-bit support)", bits_range: (29, 29), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -5125,7 +4595,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string, bytes 0 - 3", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5139,7 +4608,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string, bytes 4 - 7", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5153,7 +4621,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string, bytes 8 - 11", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5167,7 +4634,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string, bytes 12 - 15", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5181,7 +4647,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string bytes, 16 - 19", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5195,7 +4660,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string bytes, 20 - 23", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5209,7 +4673,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string bytes, 24 - 27", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5223,7 +4686,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string bytes, 28 - 31", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5237,7 +4699,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string, bytes 32 - 35", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5251,7 +4712,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string, bytes 36 - 39", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5265,7 +4725,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string, bytes 40 - 43", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5279,7 +4738,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "CPU brand ID string, bytes 44 - 47", bits_range: (0, 31), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }]), ), ( @@ -5294,28 +4752,24 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "L2 cache line size, in bytes", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "l2_nlines", description: "L2 cache number of lines per tag", bits_range: (8, 11), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "l2_assoc", description: "L2 cache associativity", bits_range: (12, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "l2_size_kb", description: "L2 cache size, in KB", bits_range: (16, 31), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -5334,7 +4788,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "TSC ticks at constant rate across all P and C states", bits_range: (8, 8), policy: ProfilePolicy::Inherit, - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }, ]), ), @@ -5350,21 +4803,18 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "Max physical address bits", bits_range: (0, 7), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "virt_addr_bits", description: "Max virtual address bits", bits_range: (8, 15), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ValueDefinition { short: "guest_phys_addr_bits", description: "Max nested-paging guest physical address bits", bits_range: (16, 23), policy: ProfilePolicy::Passthrough, - migration_compatibility_req: MigrationCompatibilityRequirement::Ignore, }, ]), ), @@ -5379,7 +4829,6 @@ pub static INTEL_CPUID_DEFINITIONS: CpuidDefinitions<154> = const { description: "WBNOINVD supported", bits_range: (9, 9), policy: ProfilePolicy::Static(0), - migration_compatibility_req: MigrationCompatibilityRequirement::ContainsBits, }]), ), ]) diff --git a/arch/src/x86_64/cpuid_definitions/mod.rs b/arch/src/x86_64/cpuid_definitions/mod.rs index 72daf874f4..39f590558a 100644 --- a/arch/src/x86_64/cpuid_definitions/mod.rs +++ b/arch/src/x86_64/cpuid_definitions/mod.rs @@ -66,21 +66,6 @@ pub enum ProfilePolicy { Static(u32), } -/// Describes how values within a CPUID output on two different hosts must relate to another in order for live-migration to be considered acceptable. -#[derive(Debug, Copy, Clone, Eq, PartialEq)] -pub enum MigrationCompatibilityRequirement { - /// The value must be equal. - Eq, - /// The target host must have at least the same bits set. - ContainsBits, - /// The target's value must be greater or equal to the source's. - GtEq, - /// The target's value must be less than or equal to the source's. - LtEq, - /// The value does not have to be compared. - Ignore, -} - /// A description of a range of bits in a register populated by the CPUID instruction with specific parameters. #[derive(Clone, Copy, Debug)] pub struct ValueDefinition { @@ -92,7 +77,6 @@ pub struct ValueDefinition { pub bits_range: (u8, u8), /// The policy corresponding to this value when building CPU profiles. pub policy: ProfilePolicy, - pub migration_compatibility_req: MigrationCompatibilityRequirement, } /// Describes values within a register populated by the CPUID instruction with specific parameters. From 3d01ba80e0197cb6a2a180835218a4018ebdd5f9 Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 9 Dec 2025 10:14:45 +0100 Subject: [PATCH 74/75] Explain why we don't use a RangeInclusive --- arch/src/x86_64/cpuid_definitions/mod.rs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/src/x86_64/cpuid_definitions/mod.rs b/arch/src/x86_64/cpuid_definitions/mod.rs index 39f590558a..19e79f923f 100644 --- a/arch/src/x86_64/cpuid_definitions/mod.rs +++ b/arch/src/x86_64/cpuid_definitions/mod.rs @@ -74,6 +74,11 @@ pub struct ValueDefinition { /// A description of the value obtainable through CPUID pub description: &'static str, /// The range of bits in the output register corresponding to this feature or value. + /// + /// This is not a `RangeInclusive` because that type does unfortunately not implement `Copy`. + // + // TODO: `Copy` does not seem to be necessary for the time being, maybe we could implement this in terms of + // a `RangeInclusive`? pub bits_range: (u8, u8), /// The policy corresponding to this value when building CPU profiles. pub policy: ProfilePolicy, From 1dbf0f7a504b347e81502cf102522639401fcd9f Mon Sep 17 00:00:00 2001 From: Oliver Anderson Date: Tue, 9 Dec 2025 10:57:54 +0100 Subject: [PATCH 75/75] Update skylake profile --- arch/src/x86_64/cpu_profiles/skylake.json | 398 +++++++++++++++++++++- 1 file changed, 381 insertions(+), 17 deletions(-) diff --git a/arch/src/x86_64/cpu_profiles/skylake.json b/arch/src/x86_64/cpu_profiles/skylake.json index 9193d45ed9..84ae4d99ee 100644 --- a/arch/src/x86_64/cpu_profiles/skylake.json +++ b/arch/src/x86_64/cpu_profiles/skylake.json @@ -965,7 +965,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -1402,6 +1402,370 @@ "mask": "0x00000000" } ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 3, + "end": 3 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 4, + "end": 4 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 3, + "end": 3 + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 4, + "end": 4 + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 3, + "end": 3 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 4, + "end": 4 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 3, + "end": 3 + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 4, + "end": 4 + }, + "register": "EDX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 5, + "end": 5 + }, + "register": "EAX" + }, + { + "replacements": "0x00000040", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 6, + "end": 6 + }, + "register": "EAX" + }, + { + "replacements": "0x00000200", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 7, + "end": 7 + }, + "register": "EAX" + }, + { + "replacements": "0x00000400", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 8, + "end": 8 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 9, + "end": 9 + }, + "register": "EAX" + }, + { + "replacements": "0x00000008", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 10, + "end": 63 + }, + "register": "EAX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 5, + "end": 5 + }, + "register": "EBX" + }, + { + "replacements": "0x00000440", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 6, + "end": 6 + }, + "register": "EBX" + }, + { + "replacements": "0x00000480", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 7, + "end": 7 + }, + "register": "EBX" + }, + { + "replacements": "0x00000680", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 8, + "end": 8 + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 9, + "end": 9 + }, + "register": "EBX" + }, + { + "replacements": "0x00000a80", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 10, + "end": 63 + }, + "register": "EBX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 5, + "end": 5 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 6, + "end": 6 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 7, + "end": 7 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 8, + "end": 8 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 9, + "end": 9 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], + [ + { + "leaf": "0x0000000d", + "sub_leaf": { + "start": 10, + "end": 63 + }, + "register": "ECX" + }, + { + "replacements": "0x00000000", + "mask": "0x00000000" + } + ], [ { "leaf": "0x0000000f", @@ -2518,8 +2882,8 @@ "register": "EAX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x65746e49", + "mask": "0x00000000" } ], [ @@ -2532,8 +2896,8 @@ "register": "EBX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x6b53206c", + "mask": "0x00000000" } ], [ @@ -2546,8 +2910,8 @@ "register": "ECX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x6b616c79", + "mask": "0x00000000" } ], [ @@ -2560,8 +2924,8 @@ "register": "EDX" }, { - "replacements": "0x00000000", - "mask": "0xffffffff" + "replacements": "0x00000065", + "mask": "0x00000000" } ], [ @@ -2575,7 +2939,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2589,7 +2953,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2603,7 +2967,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2617,7 +2981,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2631,7 +2995,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2645,7 +3009,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2659,7 +3023,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [ @@ -2673,7 +3037,7 @@ }, { "replacements": "0x00000000", - "mask": "0xffffffff" + "mask": "0x00000000" } ], [