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target/arm: Rename FPCR_ QC, NZCV macros to FPSR_
The QC, N, Z, C, V bits live in the FPSR, not the FPCR. Rename the macros that define these bits accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240628142347.1283015-8-peter.maydell@linaro.org
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5 files changed

+27
-24
lines changed

5 files changed

+27
-24
lines changed

‎target/arm/cpu.h‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1697,6 +1697,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
16971697
#define FPSR_MASK 0xf800009f
16981698
#define FPCR_MASK 0x07ff9f00
16991699

1700+
/* FPCR bits */
17001701
#define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
17011702
#define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
17021703
#define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
@@ -1708,18 +1709,20 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
17081709
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
17091710
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
17101711
#define FPCR_AHP (1 << 26) /* Alternative half-precision */
1711-
#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
1712-
#define FPCR_V (1 << 28) /* FP overflow flag */
1713-
#define FPCR_C (1 << 29) /* FP carry flag */
1714-
#define FPCR_Z (1 << 30) /* FP zero flag */
1715-
#define FPCR_N (1 << 31) /* FP negative flag */
17161712

17171713
#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
17181714
#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
17191715
#define FPCR_LTPSIZE_LENGTH 3
17201716

1721-
#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1722-
#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
1717+
/* FPSR bits */
1718+
#define FPSR_QC (1 << 27) /* Cumulative saturation bit */
1719+
#define FPSR_V (1 << 28) /* FP overflow flag */
1720+
#define FPSR_C (1 << 29) /* FP carry flag */
1721+
#define FPSR_Z (1 << 30) /* FP zero flag */
1722+
#define FPSR_N (1 << 31) /* FP negative flag */
1723+
1724+
#define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V)
1725+
#define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC)
17231726

17241727
/**
17251728
* vfp_get_fpsr: read the AArch64 FPSR

‎target/arm/tcg/mve_helper.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1115,21 +1115,21 @@ static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m,
11151115

11161116
if (update_flags) {
11171117
/* Store C, clear NZV. */
1118-
env->vfp.fpsr &= ~FPCR_NZCV_MASK;
1119-
env->vfp.fpsr |= carry_in * FPCR_C;
1118+
env->vfp.fpsr &= ~FPSR_NZCV_MASK;
1119+
env->vfp.fpsr |= carry_in * FPSR_C;
11201120
}
11211121
mve_advance_vpt(env);
11221122
}
11231123

11241124
void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm)
11251125
{
1126-
bool carry_in = env->vfp.fpsr & FPCR_C;
1126+
bool carry_in = env->vfp.fpsr & FPSR_C;
11271127
do_vadc(env, vd, vn, vm, 0, carry_in, false);
11281128
}
11291129

11301130
void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm)
11311131
{
1132-
bool carry_in = env->vfp.fpsr & FPCR_C;
1132+
bool carry_in = env->vfp.fpsr & FPSR_C;
11331133
do_vadc(env, vd, vn, vm, -1, carry_in, false);
11341134
}
11351135

‎target/arm/tcg/translate-m-nocp.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -332,17 +332,17 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
332332
if (dc_isar_feature(aa32_mve, s)) {
333333
/* QC is only present for MVE; otherwise RES0 */
334334
TCGv_i32 qc = tcg_temp_new_i32();
335-
tcg_gen_andi_i32(qc, tmp, FPCR_QC);
335+
tcg_gen_andi_i32(qc, tmp, FPSR_QC);
336336
/*
337337
* The 4 vfp.qc[] fields need only be "zero" vs "non-zero";
338338
* here writing the same value into all elements is simplest.
339339
*/
340340
tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc),
341341
16, 16, qc);
342342
}
343-
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
343+
tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK);
344344
fpscr = load_cpu_field_low32(vfp.fpsr);
345-
tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
345+
tcg_gen_andi_i32(fpscr, fpscr, ~FPSR_NZCV_MASK);
346346
tcg_gen_or_i32(fpscr, fpscr, tmp);
347347
store_cpu_field_low32(fpscr, vfp.fpsr);
348348
break;
@@ -390,7 +390,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
390390
tcg_gen_deposit_i32(control, control, sfpa,
391391
R_V7M_CONTROL_SFPA_SHIFT, 1);
392392
store_cpu_field(control, v7m.control[M_REG_S]);
393-
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
393+
tcg_gen_andi_i32(tmp, tmp, ~FPSR_NZCV_MASK);
394394
gen_helper_vfp_set_fpscr(tcg_env, tmp);
395395
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
396396
break;
@@ -457,7 +457,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
457457
case ARM_VFP_FPSCR_NZCVQC:
458458
tmp = tcg_temp_new_i32();
459459
gen_helper_vfp_get_fpscr(tmp, tcg_env);
460-
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK);
460+
tcg_gen_andi_i32(tmp, tmp, FPSR_NZCVQC_MASK);
461461
storefn(s, opaque, tmp, true);
462462
break;
463463
case QEMU_VFP_FPSCR_NZCV:
@@ -466,7 +466,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
466466
* helper call for the "VMRS to CPSR.NZCV" insn.
467467
*/
468468
tmp = load_cpu_field_low32(vfp.fpsr);
469-
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
469+
tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK);
470470
storefn(s, opaque, tmp, true);
471471
break;
472472
case ARM_VFP_FPCXT_S:
@@ -476,7 +476,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
476476
tmp = tcg_temp_new_i32();
477477
sfpa = tcg_temp_new_i32();
478478
gen_helper_vfp_get_fpscr(tmp, tcg_env);
479-
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
479+
tcg_gen_andi_i32(tmp, tmp, ~FPSR_NZCV_MASK);
480480
control = load_cpu_field(v7m.control[M_REG_S]);
481481
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
482482
tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
@@ -529,7 +529,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
529529
sfpa = tcg_temp_new_i32();
530530
fpscr = tcg_temp_new_i32();
531531
gen_helper_vfp_get_fpscr(fpscr, tcg_env);
532-
tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
532+
tcg_gen_andi_i32(tmp, fpscr, ~FPSR_NZCV_MASK);
533533
control = load_cpu_field(v7m.control[M_REG_S]);
534534
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
535535
tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);

‎target/arm/tcg/translate-vfp.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -834,7 +834,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
834834
case ARM_VFP_FPSCR:
835835
if (a->rt == 15) {
836836
tmp = load_cpu_field_low32(vfp.fpsr);
837-
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
837+
tcg_gen_andi_i32(tmp, tmp, FPSR_NZCV_MASK);
838838
} else {
839839
tmp = tcg_temp_new_i32();
840840
gen_helper_vfp_get_fpscr(tmp, tcg_env);

‎target/arm/vfp_helper.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -196,7 +196,7 @@ uint32_t vfp_get_fpsr(CPUARMState *env)
196196
fpsr |= vfp_get_fpsr_from_host(env);
197197

198198
i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
199-
fpsr |= i ? FPCR_QC : 0;
199+
fpsr |= i ? FPSR_QC : 0;
200200
return fpsr;
201201
}
202202

@@ -222,7 +222,7 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val)
222222
* The bit we set within vfp.qc[] is arbitrary; the array as a
223223
* whole being zero/non-zero is what counts.
224224
*/
225-
env->vfp.qc[0] = val & FPCR_QC;
225+
env->vfp.qc[0] = val & FPSR_QC;
226226
env->vfp.qc[1] = 0;
227227
env->vfp.qc[2] = 0;
228228
env->vfp.qc[3] = 0;
@@ -234,7 +234,7 @@ void vfp_set_fpsr(CPUARMState *env, uint32_t val)
234234
* fp_status, and QC is in vfp.qc[]. Store the NZCV bits there,
235235
* and zero any of the other FPSR bits.
236236
*/
237-
val &= FPCR_NZCV_MASK;
237+
val &= FPSR_NZCV_MASK;
238238
env->vfp.fpsr = val;
239239
}
240240

@@ -1156,7 +1156,7 @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
11561156
uint32_t z = (pair >> 32) == 0;
11571157

11581158
/* Store Z, clear NCV, in FPSCR.NZCV. */
1159-
env->vfp.fpsr = (env->vfp.fpsr & ~FPCR_NZCV_MASK) | (z * FPCR_Z);
1159+
env->vfp.fpsr = (env->vfp.fpsr & ~FPSR_NZCV_MASK) | (z * FPSR_Z);
11601160

11611161
return result;
11621162
}

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