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Vanarillrubdos
Vanarill
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rubdos
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Initial WB55 support.
1 parent ea92699 commit dba4cb0

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‎Justfile‎

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@@ -51,6 +51,7 @@ check-all:
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DRONE_RUSTFLAGS='--cfg cortex_m_core="cortex_m4f_r0p1" --cfg stm32_mcu="stm32l4s7"' drone env thumbv7em-none-eabihf -- cargo check --package drone-stm32-map --features "{{features}}"
5252
DRONE_RUSTFLAGS='--cfg cortex_m_core="cortex_m4f_r0p1" --cfg stm32_mcu="stm32l4r9"' drone env thumbv7em-none-eabihf -- cargo check --package drone-stm32-map --features "{{features}}"
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DRONE_RUSTFLAGS='--cfg cortex_m_core="cortex_m4f_r0p1" --cfg stm32_mcu="stm32l4s9"' drone env thumbv7em-none-eabihf -- cargo check --package drone-stm32-map --features "{{features}}"
54+
DRONE_RUSTFLAGS='--cfg cortex_m_core="cortex_m4f_r0p1" --cfg stm32_mcu="stm32wbx5"' drone env thumbv7em-none-eabihf -- cargo check --package drone-stm32-map --features "{{features}}"
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# Generate the docs
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doc:

‎README.md‎

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@@ -47,6 +47,7 @@ a drop-in replacement for it.
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| `stm32l4s7` | ARM® Cortex®-M4F r0p1 | [RM0432](https://www.st.com/resource/en/reference_manual/dm00310109.pdf) | `adc` `dma` `exti` `gpio` `i2c` `rtc` `spi` `tim` `uart` |
4848
| `stm32l4r9` | ARM® Cortex®-M4F r0p1 | [RM0432](https://www.st.com/resource/en/reference_manual/dm00310109.pdf) | `adc` `dma` `exti` `gpio` `i2c` `rtc` `spi` `tim` `uart` |
4949
| `stm32l4s9` | ARM® Cortex®-M4F r0p1 | [RM0432](https://www.st.com/resource/en/reference_manual/dm00310109.pdf) | `adc` `dma` `exti` `gpio` `i2c` `rtc` `spi` `tim` `uart` |
50+
| `stm32wbx5` | ARM® Cortex®-M4F r0p1 | [RM0434](https://www.st.com/resource/en/reference_manual/dm00318631.pdf) | |
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`stm32_mcu` config flag should be set at the application level according to
5253
this table.

‎src/periph/gpio/lib.rs‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,8 @@ periph! {
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stm32_mcu = "stm32l4r9",
5252
stm32_mcu = "stm32l4s5",
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stm32_mcu = "stm32l4s7",
54-
stm32_mcu = "stm32l4s9"
54+
stm32_mcu = "stm32l4s9",
55+
stm32_mcu = "stm32wbx5"
5556
))]
5657
BUSSMENR {
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0x20 RwRegBitBand Shared;
@@ -82,7 +83,8 @@ periph! {
8283
stm32_mcu = "stm32l4r9",
8384
stm32_mcu = "stm32l4s5",
8485
stm32_mcu = "stm32l4s7",
85-
stm32_mcu = "stm32l4s9"
86+
stm32_mcu = "stm32l4s9",
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stm32_mcu = "stm32wbx5"
8688
))]
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AFRL {
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0x20 RwReg;
@@ -117,7 +119,8 @@ periph! {
117119
stm32_mcu = "stm32l4r9",
118120
stm32_mcu = "stm32l4s5",
119121
stm32_mcu = "stm32l4s7",
120-
stm32_mcu = "stm32l4s9"
122+
stm32_mcu = "stm32l4s9",
123+
stm32_mcu = "stm32wbx5"
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))]
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AFRH {
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0x20 RwReg;
@@ -132,7 +135,8 @@ periph! {
132135
}
133136
#[cfg(any(
134137
stm32_mcu = "stm32l4x5",
135-
stm32_mcu = "stm32l4x6"
138+
stm32_mcu = "stm32l4x6",
139+
stm32_mcu = "stm32wbx5"
136140
))]
137141
ASCR {
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0x20 RwReg Option;

‎svd/src/lib.rs‎

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Original file line numberDiff line numberDiff line change
@@ -74,10 +74,16 @@ fn svd_deserialize() -> Result<Device> {
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"stm32l4s5" => patch_stm32l4plus(parse_svd("STM32L4S5.svd")?),
7575
"stm32l4s7" => patch_stm32l4plus(parse_svd("STM32L4S7.svd")?),
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"stm32l4s9" => patch_stm32l4plus(parse_svd("STM32L4S9.svd")?),
77+
"stm32wbx5" => patch_stm32wbx5(parse_svd("STM32WBxx_CM4.svd")?),
7778
_ => bail!("invalid `stm32_mcu` cfg flag"),
7879
}
7980
}
8081

82+
fn patch_stm32wbx5(mut dev: Device) -> Result<Device> {
83+
fix_802154(&mut dev)?;
84+
Ok(dev)
85+
}
86+
8187
fn patch_stm32f102(mut dev: Device) -> Result<Device> {
8288
spi::fix_spi2_1(&mut dev)?;
8389
Ok(dev)
@@ -197,6 +203,199 @@ fn patch_stm32f413(mut dev: Device) -> Result<Device> {
197203
tim::fix_tim11_1(&mut dev)?;
198204
adc::fix_adc1_1(&mut dev)?;
199205
Ok(dev)
206+
fn fix_802154(dev: &mut Device) -> Result<(), Error> {
207+
dev.field_mut("PWR", "SR1", "802WUF").name = "IEEE802WUF".to_string();
208+
dev.field_mut("PWR", "C2CR1", "802EWKUP").name = "IEEE802EWKUP".to_string();
209+
Ok(())
210+
}
211+
212+
fn add_dmamux(dev: &mut Device) -> Result<(), Error> {
213+
dev.add_peripheral(serde_xml_rs::deserialize(
214+
read_svd("patch/add_dmamux.xml")?.as_bytes(),
215+
)?);
216+
Ok(())
217+
}
218+
219+
fn add_tim3(dev: &mut Device) -> Result<(), Error> {
220+
dev.new_peripheral(|peripheral| {
221+
peripheral.derived_from = Some("TIM2".to_string());
222+
peripheral.name = "TIM3".to_string();
223+
peripheral.base_address = 0x4000_0400;
224+
peripheral.interrupt = vec![Interrupt {
225+
name: "TIM3".to_string(),
226+
description: "TIM3 global interrupt".to_string(),
227+
value: 29,
228+
}];
229+
});
230+
Ok(())
231+
}
232+
233+
fn fix_adc(dev: &mut Device) -> Result<(), Error> {
234+
dev.field_mut("RCC", "AHB2SMENR", "ADCFSSMEN").name = "ADCSMEN".to_string();
235+
Ok(())
236+
}
237+
238+
fn fix_exti(dev: &mut Device) -> Result<(), Error> {
239+
for (reg_name, field_name) in &[("IMR2", "MR39"), ("EMR2", "MR39")] {
240+
let mut field = dev.field("EXTI", reg_name, field_name).clone();
241+
field.name = field.name.replace("39", "40");
242+
field.description = field.description.replace("39", "40");
243+
field.bit_offset += 1;
244+
dev.add_field("EXTI", reg_name, field);
245+
}
246+
Ok(())
247+
}
248+
249+
fn fix_i2c(dev: &mut Device) -> Result<(), Error> {
250+
dev.add_field("RCC", "APB1SMENR2", Field {
251+
name: "I2C4SMEN".to_string(),
252+
description: "I2C4 clocks enable during Sleep and Stop modes".to_string(),
253+
bit_offset: 1,
254+
bit_width: 1,
255+
access: None,
256+
});
257+
Ok(())
258+
}
259+
260+
fn fix_lptim1(dev: &mut Device) -> Result<(), Error> {
261+
dev.new_register("LPTIM1", |reg| {
262+
reg.name = "OR".to_string();
263+
reg.description = format!("{} option register", "LPTIM1");
264+
reg.address_offset = 0x20;
265+
reg.size = 0x20;
266+
reg.access = Some(Access::ReadWrite);
267+
reg.reset_value = 0x0000;
268+
reg.add_field(Field {
269+
name: "OR_0".to_string(),
270+
description: "Option register bit 0".to_string(),
271+
bit_offset: 0,
272+
bit_width: 1,
273+
access: None,
274+
});
275+
reg.add_field(Field {
276+
name: "OR_1".to_string(),
277+
description: "Option register bit 1".to_string(),
278+
bit_offset: 1,
279+
bit_width: 1,
280+
access: None,
281+
});
282+
});
283+
Ok(())
284+
}
285+
286+
fn fix_lptim2(dev: &mut Device) -> Result<(), Error> {
287+
dev.new_register("LPTIM2", |reg| {
288+
reg.name = "OR".to_string();
289+
reg.description = format!("{} option register", "LPTIM2");
290+
reg.address_offset = 0x20;
291+
reg.size = 0x20;
292+
reg.access = Some(Access::ReadWrite);
293+
reg.reset_value = 0x0000;
294+
reg.add_field(Field {
295+
name: "OR_0".to_string(),
296+
description: "Option register bit 0".to_string(),
297+
bit_offset: 0,
298+
bit_width: 1,
299+
access: None,
300+
});
301+
reg.add_field(Field {
302+
name: "OR_1".to_string(),
303+
description: "Option register bit 1".to_string(),
304+
bit_offset: 1,
305+
bit_width: 1,
306+
access: None,
307+
});
308+
});
309+
Ok(())
310+
}
311+
312+
fn fix_lpuart1(dev: &mut Device) -> Result<(), Error> {
313+
copy_field(dev, "USART3", "LPUART1", "CR3", "UCESM");
314+
Ok(())
315+
}
316+
317+
fn fix_pwr(dev: &mut Device) -> Result<(), Error> {
318+
dev.add_field("PWR", "CR1", Field {
319+
name: "RRSTP".to_string(),
320+
description: "SRAM3 retention in Stop 2 mode".to_string(),
321+
bit_offset: 4,
322+
bit_width: 1,
323+
access: None,
324+
});
325+
Ok(())
326+
}
327+
328+
fn fix_rcc(dev: &mut Device) -> Result<(), Error> {
329+
dev.new_register("RCC", |reg| {
330+
reg.name = "CCIPR2".to_string();
331+
reg.description = "Peripherals independent clock configuration register".to_string();
332+
reg.address_offset = 0x9C;
333+
reg.size = 0x20;
334+
reg.access = Some(Access::ReadWrite);
335+
reg.reset_value = 0x0000;
336+
reg.add_field(Field {
337+
name: "I2C4SEL".to_string(),
338+
description: "I2C4 clock source selection".to_string(),
339+
bit_offset: 0,
340+
bit_width: 2,
341+
access: None,
342+
});
343+
});
344+
Ok(())
345+
}
346+
347+
fn fix_rtc(dev: &mut Device) -> Result<(), Error> {
348+
dev.add_field("RCC", "APB1ENR1", Field {
349+
name: "RTCAPBEN".to_string(),
350+
description: "RTC APB clock enable".to_string(),
351+
bit_offset: 10,
352+
bit_width: 1,
353+
access: None,
354+
});
355+
dev.add_field("RCC", "APB1SMENR1", Field {
356+
name: "RTCAPBSMEN".to_string(),
357+
description: "RTC APB clock enable during Sleep and Stop modes".to_string(),
358+
bit_offset: 10,
359+
bit_width: 1,
360+
access: None,
361+
});
362+
Ok(())
363+
}
364+
365+
fn fix_spi2_1(dev: &mut Device) -> Result<(), Error> {
366+
dev.add_field("RCC", "APB1ENR", Field {
367+
name: "SPI2EN".to_string(),
368+
description: "SPI 2 clock enable".to_string(),
369+
bit_offset: 14,
370+
bit_width: 1,
371+
access: None,
372+
});
373+
dev.add_field("RCC", "APB1RSTR", Field {
374+
name: "SPI2RST".to_string(),
375+
description: "SPI2 reset".to_string(),
376+
bit_offset: 14,
377+
bit_width: 1,
378+
access: None,
379+
});
380+
copy_field(dev, "SPI1", "SPI2", "SR", "UDR");
381+
copy_field(dev, "SPI1", "SPI2", "SR", "CHSIDE");
382+
Ok(())
383+
}
384+
385+
fn fix_spi2_2(dev: &mut Device) -> Result<(), Error> {
386+
dev.add_field("RCC", "APB1ENR1", Field {
387+
name: "SPI2EN".to_string(),
388+
description: "SPI2 clock enable".to_string(),
389+
bit_offset: 14,
390+
bit_width: 1,
391+
access: None,
392+
});
393+
Ok(())
394+
}
395+
396+
fn fix_spi3_1(dev: &mut Device) -> Result<(), Error> {
397+
dev.field_mut("RCC", "APB1SMENR1", "SP3SMEN").name = "SPI3SMEN".to_string();
398+
Ok(())
200399
}
201400

202401
fn patch_stm32f427(mut dev: Device) -> Result<Device> {

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