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Description
Summary
Proposing to add STM32 as a third platform alongside POSIX and S32K1xx, targeting two Nucleo boards:
| Board | MCU | CAN | Clock | Flash/RAM |
|---|---|---|---|---|
| NUCLEO-G474RE | Cortex-M4F | FDCAN | 170 MHz | 512K / 128K |
| NUCLEO-F413ZH | Cortex-M4 | bxCAN | 96 MHz | 1.5M / 320K |
BSP Modules Included
- bspCan — register-level FDCAN (G4) + bxCAN (F4) drivers, no HAL dependency
- bspClock — PLL configuration for both chips (HSI/HSE → target freq)
- bspUart — polling UART TX/RX with dual register set support (F4 SR/DR vs G4 ISR/TDR)
- bspTimer — DWT CYCCNT-based system timer (architecture-level, chip-agnostic)
- bspInterruptsImpl — CPSID/CPSIE global interrupt masking
- bspMcu — CMSIS headers, linker scripts, startup assembly, NVIC macros
- bxCanTransceiver / fdCanTransceiver — OpenBSW
AbstractCANTransceiverwrappers - hardFaultHandler — Cortex-M4 register dump to NO_INIT RAM
- softwareSystemReset —
NVIC_SystemReset()with pre-reset hook - RTOS ports: FreeRTOS CM4F SysTick + ThreadX Cortex-M4/GNU
What's Not Yet Included (future PRs)
bspIo(GPIO abstraction)safeBspMcuWatchdog(IWDG driver)- CMakePresets entries for both boards
- Reference application executables
Validation
- 46/46 unit tests pass (22 BxCanTransceiver + 23 FdCanTransceiver + 1 UART)
- Validated against upstream OpenBSW with directory junctions on MinGW GCC 15.2.0
- CAN loopback self-test verified on NUCLEO-G474RE hardware
Proposed PR Strategy
- PR 1: Core platform (
platforms/stm32/) + F413ZH reference app - PR 2: G474RE reference app + FDCAN integration
- PR 3: GPIO + watchdog modules
Happy to adjust the approach based on maintainer feedback.
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