From 797cda000d5381cc02e497aa8565a49081b0f08a Mon Sep 17 00:00:00 2001 From: jburks Date: Thu, 16 Mar 2023 19:35:28 -0700 Subject: [PATCH] Enable 240p mode with bit 3 of DC_VIDEO. --- fpga/source/top.v | 8 ++++- fpga/source/video/video_composite.v | 53 +++++++++++++++++------------ 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/fpga/source/top.v b/fpga/source/top.v index 966c9f4..d282c35 100644 --- a/fpga/source/top.v +++ b/fpga/source/top.v @@ -103,6 +103,7 @@ module top( reg [11:0] l1_vscroll_r, l1_vscroll_next; reg [1:0] video_output_mode_r, video_output_mode_next; + reg line_mode_r, line_mode_next; reg [7:0] audio_pcm_sample_rate_r, audio_pcm_sample_rate_next; reg audio_mode_stereo_r, audio_mode_stereo_next; @@ -147,7 +148,7 @@ module top( 5'h09: begin if (dc_select_r == 0) begin - rddata = {current_field, sprites_enabled_r, l1_enabled_r, l0_enabled_r, 1'b0, chroma_disable_r, video_output_mode_r}; + rddata = {current_field, sprites_enabled_r, l1_enabled_r, l0_enabled_r, line_mode_r, chroma_disable_r, video_output_mode_r}; end else begin rddata = dc_active_hstart_r[9:2]; end @@ -298,6 +299,7 @@ module top( l0_enabled_next = l0_enabled_r; l1_enabled_next = l1_enabled_r; chroma_disable_next = chroma_disable_r; + line_mode_next = line_mode_r; dc_hscale_next = dc_hscale_r; dc_vscale_next = dc_vscale_r; dc_border_color_next = dc_border_color_r; @@ -426,6 +428,7 @@ module top( sprites_enabled_next = write_data[6]; l1_enabled_next = write_data[5]; l0_enabled_next = write_data[4]; + line_mode_next = write_data[3]; chroma_disable_next = write_data[2]; video_output_mode_next = write_data[1:0]; end else begin @@ -586,6 +589,7 @@ module top( l0_enabled_r <= 0; l1_enabled_r <= 0; chroma_disable_r <= 0; + line_mode_r <= 0; dc_hscale_r <= 8'd128; dc_vscale_r <= 8'd128; dc_border_color_r <= 0; @@ -662,6 +666,7 @@ module top( l0_enabled_r <= l0_enabled_next; l1_enabled_r <= l1_enabled_next; chroma_disable_r <= chroma_disable_next; + line_mode_r <= line_mode_next; dc_hscale_r <= dc_hscale_next; dc_vscale_r <= dc_vscale_next; dc_border_color_r <= dc_border_color_next; @@ -1076,6 +1081,7 @@ module top( // Line buffer / palette interface .palette_rgb_data(palette_rgb_data[11:0]), + .line_mode(line_mode_r), .next_frame(video_composite_next_frame), .next_line(video_composite_next_line), diff --git a/fpga/source/video/video_composite.v b/fpga/source/video/video_composite.v index deb3f5b..ff33eac 100644 --- a/fpga/source/video/video_composite.v +++ b/fpga/source/video/video_composite.v @@ -7,6 +7,8 @@ module video_composite( // Line buffer / palette interface input wire [11:0] palette_rgb_data, + input wire line_mode, + output wire next_frame, output wire next_line, output wire next_pixel, @@ -16,7 +18,7 @@ module video_composite( // Composite interface output wire [5:0] luma, output wire [5:0] chroma, - + // RGB interface output wire [3:0] rgb_r, output wire [3:0] rgb_g, @@ -62,39 +64,48 @@ module video_composite( // Vertical video timing (NTSC 60Hz): // // field1 (even): - // 0-5 equalization - // 6-11 vsync - // 12-17 equalization - // 18-37 blank active - // 38-524 active (243,5 lines) + // 480i | 240p (263 line mode) + // -----------------------------------+---------------------------------- + // 0-5 equalization | 0-5 equalization + // 6-11 vsync | 6-11 vsync + // 12-17 equalization | 12-17 equalization + // 18-37 blank active | 18-37 blank active + // 38-524 active (243,5 lines) | 38-525 active (244 lines) // // field2 (odd): - // 525-530 equalization - // 531-536 vsync - // 537-542 equalization - // 543-562 blank active - // 563-1049 active (243,5 lines) + // 480i | 240p (263 line mode) + // -----------------------------------+---------------------------------- + // 525-530 equalization | 526-531 equalization + // 531-536 vsync | 532-537 vsync + // 537-542 equalization | 538-543 equalization + // 543-562 blank active | 544-563 blank active + // 563-1049 active (243,5 lines) | 564-1051 active (244 lines) + // + // Most 240p implementations use the 262 line mode, however the 263 line mode + // uses the same composite sync signalling as 480i so 263 line mode is used + // here. + reg [10:0] vcnt = 0; // half-lines wire v_sync = (vcnt >= 6 && vcnt <= 11) || - (vcnt >= 531 && vcnt <= 536); + (vcnt >= (531+line_mode) && vcnt <= (536+line_mode)); wire v_equalization = (vcnt >= 0 && vcnt <= 5) || (vcnt >= 12 && vcnt <= 17) || - (vcnt >= 525 && vcnt <= 530) || - (vcnt >= 537 && vcnt <= 542); - + (vcnt >= (525+line_mode) && vcnt <= (530+line_mode)) || + (vcnt >= (537+line_mode) && vcnt <= (542+line_mode)); + wire v_active = - (vcnt >= 38+4 && vcnt <= 524-3) || // 240 lines - (vcnt >= 563+5 && vcnt <= 1049-2); // 240 lines - + (vcnt >= 38+4 && vcnt <= (524+line_mode)-3) || // 240 lines + (vcnt >= 563+5 && vcnt <= (1049+line_mode)-2); // 240 lines + reg field; // 0: even, 1: odd wire v_last2 = (vcnt == 38+3 || vcnt == 563+4); - wire v_last = (vcnt == 1049); - wire v_even_field_last = (vcnt == 524); + wire v_last = (vcnt == (1049+{8'b0,line_mode,1'b0})); + wire v_even_field_last = (vcnt == (524+line_mode)); assign next_line = (hcnt == H_SYNC + H_BACK_PORCH - 1); @@ -118,7 +129,7 @@ module video_composite( assign current_field = current_field_r; - assign vblank_pulse = h_half_line_last && (vcnt == 524 || vcnt == 1049); + assign vblank_pulse = h_half_line_last && (vcnt == (524+line_mode) || vcnt == (1049+{8'b0,line_mode,1'b0})); always @(posedge clk or posedge rst) begin if (rst) begin