cmd/compile: extend loong MOV*idx rules to match ADDshiftLLV

Fixes #76085

I was focused on restoring the old behavior and fixing the failing
test/codegen/floats.go:index* tests.

It is probable this same bug hides elsewhere in this file.

Change-Id: Ibb2cb2be5c7bbeb5eafa9705d998a67380f2b04c
Reviewed-on: https://go-review.googlesource.com/c/go/+/715580
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: Keith Randall <khr@google.com>
Auto-Submit: Jorropo <jorropo.pgm@gmail.com>
Reviewed-by: Keith Randall <khr@golang.org>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Michael Knyszek <mknyszek@google.com>

Author: Jorropo

src/cmd/compile/internal/ssa/_gen/LOONG64.rules

@@ -611,15 +611,24 @@
 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
 
 // register indexed load
-(MOVVload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx ptr idx mem)
-(MOVWUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr idx mem)
-(MOVWload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx ptr idx mem)
-(MOVHUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr idx mem)
-(MOVHload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx ptr idx mem)
-(MOVBUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr idx mem)
-(MOVBload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx ptr idx mem)
-(MOVFload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVFloadidx ptr idx mem)
-(MOVDload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr idx mem)
+(MOVVload  [off] {sym} (ADDV                ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx  ptr                                idx  mem)
+(MOVVload  [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx  ptr (SLLVconst <typ.Int64> [shift] idx) mem)
+(MOVWUload [off] {sym} (ADDV                ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr                                idx  mem)
+(MOVWUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
+(MOVWload  [off] {sym} (ADDV                ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx  ptr                                idx  mem)
+(MOVWload  [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx  ptr (SLLVconst <typ.Int64> [shift] idx) mem)
+(MOVHUload [off] {sym} (ADDV                ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr                                idx  mem)
+(MOVHUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
+(MOVHload  [off] {sym} (ADDV                ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx  ptr                                idx  mem)
+(MOVHload  [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx  ptr (SLLVconst <typ.Int64> [shift] idx) mem)
+(MOVBUload [off] {sym} (ADDV                ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr                                idx  mem)
+(MOVBUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
+(MOVBload  [off] {sym} (ADDV                ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx  ptr                                idx  mem)
+(MOVBload  [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx  ptr (SLLVconst <typ.Int64> [shift] idx) mem)
+(MOVFload  [off] {sym} (ADDV                ptr idx) mem) && off == 0 && sym == nil => (MOVFloadidx  ptr                                idx  mem)
+(MOVFload  [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVFloadidx  ptr (SLLVconst <typ.Int64> [shift] idx) mem)
+(MOVDload  [off] {sym} (ADDV                ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx  ptr                                idx  mem)
+(MOVDload  [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx  ptr (SLLVconst <typ.Int64> [shift] idx) mem)
 (MOVVloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVVload [int32(c)] ptr mem)
 (MOVVloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVVload [int32(c)] ptr mem)
 (MOVWUloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVWUload [int32(c)] ptr mem)
@@ -640,12 +649,18 @@
 (MOVDloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVDload [int32(c)] ptr mem)
 
 // register indexed store
-(MOVVstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVVstoreidx ptr idx val mem)
-(MOVWstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr idx val mem)
-(MOVHstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr idx val mem)
-(MOVBstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr idx val mem)
-(MOVFstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVFstoreidx ptr idx val mem)
-(MOVDstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr idx val mem)
+(MOVVstore [off] {sym} (ADDV                ptr idx) val mem) && off == 0 && sym == nil => (MOVVstoreidx ptr                                idx  val mem)
+(MOVVstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVVstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
+(MOVWstore [off] {sym} (ADDV                ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr                                idx  val mem)
+(MOVWstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
+(MOVHstore [off] {sym} (ADDV                ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr                                idx  val mem)
+(MOVHstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
+(MOVBstore [off] {sym} (ADDV                ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr                                idx  val mem)
+(MOVBstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
+(MOVFstore [off] {sym} (ADDV                ptr idx) val mem) && off == 0 && sym == nil => (MOVFstoreidx ptr                                idx  val mem)
+(MOVFstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVFstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
+(MOVDstore [off] {sym} (ADDV                ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr                                idx  val mem)
+(MOVDstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
 (MOVVstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVVstore [int32(c)] ptr val mem)
 (MOVVstoreidx (MOVVconst [c]) idx val mem) && is32Bit(c) => (MOVVstore [int32(c)] idx val mem)
 (MOVWstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVWstore [int32(c)] ptr val mem)