From ac9f52144a680af848933efc1dee7272251c0731 Mon Sep 17 00:00:00 2001
From: Changyuan Lyu <changyuanl@google.com>
Date: Mon, 27 Oct 2025 00:42:58 -0700
Subject: [PATCH] refactor(pci): remove redundant trait PciConfigArea

Signed-off-by: Changyuan Lyu <changyuanl@google.com>
---
 alioth/src/pci/cap.rs      | 19 ++++++++-----------
 alioth/src/pci/cap_test.rs |  1 -
 alioth/src/pci/config.rs   | 36 +++++-------------------------------
 alioth/src/virtio/pci.rs   | 20 +++++++-------------
 4 files changed, 20 insertions(+), 56 deletions(-)

diff --git a/alioth/src/pci/cap.rs b/alioth/src/pci/cap.rs
index 445fc419..37d16c0c 100644
--- a/alioth/src/pci/cap.rs
+++ b/alioth/src/pci/cap.rs
@@ -28,7 +28,7 @@ use crate::hv::IrqFd;
 use crate::mem::addressable::SlotBackend;
 use crate::mem::emulated::{Action, Mmio, MmioBus};
 use crate::pci::Error;
-use crate::pci::config::{DeviceHeader, PciConfigArea};
+use crate::pci::config::DeviceHeader;
 use crate::utils::truncate_u64;
 use crate::{align_up, c_enum, impl_mmio_for_zerocopy, mask_bits, mem};
 
@@ -165,8 +165,9 @@ impl Default for MsixTableEntry {
     }
 }
 
-pub trait PciCap: PciConfigArea {
+pub trait PciCap: Mmio {
     fn set_next(&mut self, val: u8);
+    fn reset(&self);
 }
 
 impl SlotBackend for Box<dyn PciCap> {
@@ -287,7 +288,11 @@ impl Mmio for MsixCapMmio {
     }
 }
 
-impl PciConfigArea for MsixCapMmio {
+impl PciCap for MsixCapMmio {
+    fn set_next(&mut self, val: u8) {
+        self.cap.write().header.next = val;
+    }
+
     fn reset(&self) {
         let mut cap = self.cap.write();
         cap.control.set_enabled(false);
@@ -295,12 +300,6 @@ impl PciConfigArea for MsixCapMmio {
     }
 }
 
-impl PciCap for MsixCapMmio {
-    fn set_next(&mut self, val: u8) {
-        self.cap.write().header.next = val;
-    }
-}
-
 #[derive(Debug)]
 pub enum MsixTableMmioEntry<F> {
     Entry(MsixTableEntry),
@@ -474,8 +473,6 @@ impl PciCap for NullCap {
     fn set_next(&mut self, val: u8) {
         self.next = val;
     }
-}
 
-impl PciConfigArea for NullCap {
     fn reset(&self) {}
 }
diff --git a/alioth/src/pci/cap_test.rs b/alioth/src/pci/cap_test.rs
index 029dfe0c..5b15c5e9 100644
--- a/alioth/src/pci/cap_test.rs
+++ b/alioth/src/pci/cap_test.rs
@@ -22,7 +22,6 @@ use crate::pci::cap::{
     MsiMsgCtrl, MsixCap, MsixCapMmio, MsixCapOffset, MsixMsgCtrl, MsixTableEntry, MsixTableMmio,
     MsixTableMmioEntry, MsixVectorCtrl, NullCap, PciCap, PciCapHdr, PciCapId, PciCapList,
 };
-use crate::pci::config::PciConfigArea;
 
 #[rstest]
 #[case(0x0, 1, 0x0)]
diff --git a/alioth/src/pci/config.rs b/alioth/src/pci/config.rs
index 5384e3d8..9c99ce0c 100644
--- a/alioth/src/pci/config.rs
+++ b/alioth/src/pci/config.rs
@@ -32,30 +32,6 @@ use crate::pci::cap::PciCapList;
 use crate::pci::{Bdf, PciBar};
 use crate::{assign_bits, c_enum, impl_mmio_for_zerocopy, mask_bits, mem};
 
-pub trait PciConfigArea: Mmio {
-    fn reset(&self);
-}
-
-impl Mmio for Box<dyn PciConfigArea> {
-    fn read(&self, offset: u64, size: u8) -> mem::Result<u64> {
-        Mmio::read(self.as_ref(), offset, size)
-    }
-
-    fn write(&self, offset: u64, size: u8, val: u64) -> mem::Result<Action> {
-        Mmio::write(self.as_ref(), offset, size, val)
-    }
-
-    fn size(&self) -> u64 {
-        Mmio::size(self.as_ref())
-    }
-}
-
-impl SlotBackend for Box<dyn PciConfigArea> {
-    fn size(&self) -> u64 {
-        Mmio::size(self.as_ref())
-    }
-}
-
 #[derive(Clone, Copy, Default, PartialEq, Eq, IntoBytes, FromBytes, KnownLayout, Immutable)]
 #[repr(transparent)]
 pub struct Command(u16);
@@ -453,6 +429,11 @@ impl EmulatedHeader {
         let mut header = self.data.write();
         header.set_command(command)
     }
+
+    fn reset(&self) {
+        let mut header = self.data.write();
+        header.set_command(Command::empty());
+    }
 }
 
 impl Mmio for EmulatedHeader {
@@ -477,13 +458,6 @@ impl Mmio for EmulatedHeader {
     }
 }
 
-impl PciConfigArea for EmulatedHeader {
-    fn reset(&self) {
-        let mut header = self.data.write();
-        header.set_command(Command::empty());
-    }
-}
-
 pub trait PciConfig: Mmio {
     fn get_header(&self) -> &EmulatedHeader;
     fn reset(&self);
diff --git a/alioth/src/virtio/pci.rs b/alioth/src/virtio/pci.rs
index 52c9c569..4256184d 100644
--- a/alioth/src/virtio/pci.rs
+++ b/alioth/src/virtio/pci.rs
@@ -33,7 +33,7 @@ use crate::pci::cap::{
 };
 use crate::pci::config::{
     BAR_MEM32, BAR_MEM64, BAR_PREFETCHABLE, CommonHeader, DeviceHeader, EmulatedConfig, HeaderType,
-    PciConfig, PciConfigArea,
+    PciConfig,
 };
 use crate::pci::{self, Pci, PciBar};
 use crate::sync::notifier::Notifier;
@@ -608,14 +608,12 @@ pub struct VirtioPciCap {
 }
 impl_mmio_for_zerocopy!(VirtioPciCap);
 
-impl PciConfigArea for VirtioPciCap {
-    fn reset(&self) {}
-}
-
 impl PciCap for VirtioPciCap {
     fn set_next(&mut self, val: u8) {
         self.header.next = val
     }
+
+    fn reset(&self) {}
 }
 
 #[repr(C, align(4))]
@@ -627,14 +625,12 @@ pub struct VirtioPciCap64 {
 }
 impl_mmio_for_zerocopy!(VirtioPciCap64);
 
-impl PciConfigArea for VirtioPciCap64 {
-    fn reset(&self) {}
-}
-
 impl PciCap for VirtioPciCap64 {
     fn set_next(&mut self, val: u8) {
         PciCap::set_next(&mut self.cap, val)
     }
+
+    fn reset(&self) {}
 }
 
 #[repr(C, align(4))]
@@ -645,14 +641,12 @@ pub struct VirtioPciNotifyCap {
 }
 impl_mmio_for_zerocopy!(VirtioPciNotifyCap);
 
-impl PciConfigArea for VirtioPciNotifyCap {
-    fn reset(&self) {}
-}
-
 impl PciCap for VirtioPciNotifyCap {
     fn set_next(&mut self, val: u8) {
         self.cap.header.next = val;
     }
+
+    fn reset(&self) {}
 }
 
 #[derive(Debug)]