From a8c6cc49b7f6bf4d911fb9d694189d78076d9b29 Mon Sep 17 00:00:00 2001
From: Taichi Ishitani <taichi730@gmail.com>
Date: Fri, 29 Nov 2024 00:42:54 +0900
Subject: [PATCH] Update rggen.md

Add Veryl support
---
 content/items/rggen.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/content/items/rggen.md b/content/items/rggen.md
index 9f22abcd..c238c2bd 100644
--- a/content/items/rggen.md
+++ b/content/items/rggen.md
@@ -28,6 +28,7 @@ RgGen has following features:
 
 * Generate following source files for CSR automatically from register map specifications
     * SystemVerilog/Verilog RTL
+    * [Veryl](https://veryl-lang.org) RTL
     * VHDL RTL
     * UVM register model (RAL)
     * Markdown documents