diff --git a/bsp_sedi/drivers/dma/sedi_dma_dw_axi.c b/bsp_sedi/drivers/dma/sedi_dma_dw_axi.c
new file mode 100644
index 0000000..6ad6553
--- /dev/null
+++ b/bsp_sedi/drivers/dma/sedi_dma_dw_axi.c
@@ -0,0 +1,665 @@
+/*
+ * Copyright (c) 2020-2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <sedi_driver_pm.h>
+#include <sedi_driver_dma.h>
+
+#include "sedi_driver_core.h"
+#include "sedi_dmac_regs.h"
+#include "sedi_dma_regs.h"
+#include "sedi_dma_misc_regs.h"
+#include "sedi_soc_regs.h"
+#include "sedi_soc_funcs.h"
+
+#define PERI_SUPPORT        1
+#define LINKED_LIST_SUPPORT 0
+#ifndef DMA_PHY_CHAN_NUM
+#define DMA_PHY_CHAN_NUM DMA_CHANNEL_NUM
+#endif
+
+#define SEDI_DMA_DRIVER_VERSION SEDI_DRIVER_VERSION_MAJOR_MINOR(0, 1)
+
+#define SEDI_DMA_POLL_UNTIL(_cond) SEDI_POLL_UNTIL((_cond), 1000)
+/*driver version*/
+static const sedi_driver_version_t driver_version = {SEDI_DMA_API_VERSION, SEDI_DMA_DRIVER_VERSION};
+
+typedef enum {
+	DMA_RS0 = 0,
+	DMA_RS1 = 1,
+	DMA_RS3 = 3,
+} dma_root_space;
+#define DT_IS_IN_DRAM (1)
+#define SR_IS_IN_DRAM (2)
+
+static int32_t sedi_dma_start_transfer_aux(sedi_dma_t dma_device, int channel_id, uint64_t sr_addr,
+					   uint64_t dest_addr, uint32_t length, uint8_t polling);
+static void dma_transfer_post(sedi_dma_t dev, int chn, uint64_t interrupt_status);
+
+typedef enum {
+	SEDI_CONFIG_DMA_TRANS_TYPE = SEDI_CONFIG_DMA_CONTROL_ID_MAX,
+	SEDI_CONFIG_DMA_LL_HEADER
+} dma_inner_control_code;
+
+/*!
+ * DMA Transfer Type, inner usage
+ */
+typedef enum {
+	DMA_TYPE_SINGLE,            /* Single block mode. */
+	DMA_TYPE_MULTI_CONT,        /* Contiguous multiblock mode. */
+	DMA_TYPE_MULTI_LL,          /* Link list multiblock mode. */
+	DMA_TYPE_MULTI_LL_CIRCULAR, /* Link list multiblock mode with cyclic operation. */
+	DMA_TYPE_MAX
+} dma_transfer_type_t;
+
+/* driver capabilities */
+static sedi_dma_capabilities_t driver_capabilities[SEDI_DMA_NUM] = {0};
+
+/* channel config*/
+typedef struct {
+	uint8_t config_applied: 1;
+	uint8_t tf_mode: 3;
+	uint8_t sr_mem_type: 2;
+	uint8_t dt_mem_type: 2;
+	uint8_t burst_length: 4;
+	uint8_t sr_width: 3;
+	uint8_t dt_width: 3;
+	uint8_t direction: 3;
+	uint8_t handshake_polarity: 1;
+	uint8_t peripheral_direction: 1;
+	uint8_t reserved: 1;
+	uint8_t handshake_device_id;
+#ifdef LINKED_LIST_SUPPORT
+	dma_linked_list_item_t *linked_list_header;
+#endif
+} channel_config_t;
+
+/*dma runtime context information */
+typedef struct {
+	channel_config_t channel_config[DMA_CHANNEL_NUM];
+	sedi_dma_event_cb_t cb_event[DMA_CHANNEL_NUM]; /*event callback*/
+	void *cb_param[DMA_CHANNEL_NUM];               /*event callback*/
+	sedi_dma_status_t status[DMA_CHANNEL_NUM];     /*status flags*/
+	uint16_t done_byte[DMA_CHANNEL_NUM];           /*the transferred byte*/
+#ifdef LINKED_LIST_SUPPORT
+	dma_linked_list_item_t *next_llp[DMA_CHANNEL_NUM];
+#endif
+	uint8_t vnn_status;
+	uint8_t power_status;
+	/*other private runtime data*/
+} dma_context_t;
+
+/*resources data structure*/
+typedef struct {
+	__IO_RW sedi_dmac_regs_t *comm_reg_ptr;
+	__IO_RW sedi_dma_regs_t *chan_reg_ptrs[DMA_CHANNEL_NUM];
+	__IO_RW uint32_t *chan_misc_regs;
+} dma_resources_t;
+
+static dma_context_t dma_context[SEDI_DMA_NUM] = {0};
+static dma_resources_t resources[SEDI_DMA_NUM];
+
+sedi_driver_version_t sedi_dma_get_version(void)
+{
+	return driver_version;
+}
+
+int sedi_dma_get_capabilities(IN sedi_dma_t dma_device, INOUT sedi_dma_capabilities_t *cap)
+{
+	DBG_CHECK(dma_device < SEDI_DMA_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+
+	if (sedi_dev_is_self_owned(SEDI_DEVID_DMA0 + dma_device)) {
+		driver_capabilities[dma_device].is_available = 1;
+	} else {
+		driver_capabilities[dma_device].is_available = 0;
+	}
+
+	*cap = driver_capabilities[dma_device];
+	return SEDI_DRIVER_OK;
+}
+
+static inline void dma_vnn_req(sedi_dma_t dma_device, int channel_id)
+{
+	unsigned int key = sedi_core_irq_lock();
+
+	if (dma_context[dma_device].vnn_status == 0) {
+		PM_VNN_DRIVER_REQ(VNN_ID_DMA0 + dma_device);
+	}
+	dma_context[dma_device].vnn_status |= BIT(channel_id);
+	sedi_core_irq_unlock(key);
+}
+
+static inline void dma_vnn_dereq(sedi_dma_t dma_device, int channel_id)
+{
+	unsigned int key = sedi_core_irq_lock();
+
+	if (dma_context[dma_device].vnn_status & (BIT(channel_id))) {
+		dma_context[dma_device].vnn_status &= (~BIT(channel_id));
+		if (dma_context[dma_device].vnn_status == 0) {
+			PM_VNN_DRIVER_DEREQ(VNN_ID_DMA0 + dma_device);
+		}
+	}
+	sedi_core_irq_unlock(key);
+}
+
+static void dma_set_default_channel_config(OUT channel_config_t *config)
+{
+	config->tf_mode = DMA_TYPE_MAX;
+	config->sr_mem_type = DMA_SRAM_MEM;
+	config->dt_mem_type = DMA_SRAM_MEM;
+	config->burst_length = DMA_BURST_TRANS_LENGTH_MAX;
+	config->sr_width = DMA_TRANS_WIDTH_MAX;
+	config->dt_width = DMA_TRANS_WIDTH_MAX;
+	config->direction = DMA_DIRECTION_MAX;
+	config->handshake_device_id = 0;
+#ifdef LINKED_LIST_SUPPORT
+	config->linked_list_header = NULL;
+#endif
+	config->config_applied = 0;
+}
+
+#define CH_TFR_DONE_INTR                                                                           \
+	SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_DMA_TFR_DONE_IntSignal,                        \
+		   ENABLE_DMA_TFR_DONE_IntSignal)
+#define CH_TFR_ERR_INTR                                                                            \
+	(SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_DEC_ERR_IntSignal,                        \
+		    ENABLE_SRC_DEC_ERR_IntSignal) |                                                \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_DST_DEC_ERR_IntSignal,                        \
+		    ENABLE_DST_DEC_ERR_IntSignal) |                                                \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_SLV_ERR_IntSignal,                        \
+		    ENABLE_SRC_SLV_ERR_IntSignal) |                                                \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_DST_SLV_ERR_IntSignal,                        \
+		    ENABLE_DST_SLV_ERR_IntSignal) |                                                \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_RD_DEC_ERR_IntSignal,                     \
+		    ENABLE_LLI_RD_DEC_ERR_IntSignal) |                                             \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_WR_DEC_ERR_IntSignal,                     \
+		    ENABLE_LLI_WR_DEC_ERR_IntSignal) |                                             \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_RD_SLV_ERR_IntSignal,                     \
+		    ENABLE_LLI_RD_SLV_ERR_IntSignal) |                                             \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_WR_SLV_ERR_IntSignal,                     \
+		    ENABLE_LLI_WR_SLV_ERR_IntSignal) |                                             \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,       \
+		    ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal) |                               \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,             \
+		    ENABLE_SLVIF_MULTIBLKTYPE_ERR_IntSignal) |                                     \
+	 SEDI_RBFVM(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_DEC_ERR_IntSignal,                      \
+		    ENABLE_SLVIF_DEC_ERR_IntSignal))
+
+/*  mask  channel interrupt */
+static inline void mask_channel_interrupt(volatile sedi_dma_regs_t *chx_regs)
+{
+	/*
+	 * per spec, keep intstatus_enablereg to track finish reason,
+	 * clear intsignal_enablereg to mask interrupt source
+	 */
+	chx_regs->intsignal_enablereg = 0;
+	chx_regs->intstatus_enablereg = CH_TFR_DONE_INTR | CH_TFR_ERR_INTR;
+}
+
+/* unmask channel interrupt */
+static inline void unmask_channel_interrupt(volatile sedi_dma_regs_t *chx_regs)
+{
+	chx_regs->intsignal_enablereg = CH_TFR_DONE_INTR | CH_TFR_ERR_INTR;
+	chx_regs->intstatus_enablereg = CH_TFR_DONE_INTR | CH_TFR_ERR_INTR;
+}
+
+/* clear channel interrupt */
+static void clear_channel_interrupt(volatile sedi_dma_regs_t *chx_regs)
+{
+	chx_regs->intclearreg = chx_regs->intstatus;
+}
+
+int32_t sedi_dma_init(IN sedi_dma_t dma_device, IN int channel_id, IN sedi_dma_event_cb_t cb,
+		      INOUT void *param)
+{
+	DBG_CHECK(dma_device < SEDI_DMA_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(channel_id < DMA_CHANNEL_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+
+	if ((uint32_t)(resources[dma_device].chan_reg_ptrs[channel_id]) <=
+	    (uint32_t)(resources[dma_device].comm_reg_ptr)) {
+		uint32_t reg_adrs = SEDI_IREG_BASE(DMA, 0) + SEDI_DMA_CHAN_OFF;
+
+		for (uint32_t chan_id = 0; chan_id < DMA_CHANNEL_NUM; ++chan_id) {
+			resources[dma_device].chan_reg_ptrs[chan_id] =
+				(volatile sedi_dma_regs_t *)reg_adrs;
+			reg_adrs += SEDI_DMA_CHAN_OFF;
+		}
+		resources[dma_device].chan_misc_regs =
+			(volatile uint32_t *)(SEDI_IREG_BASE(DMA, 0) + SEDI_DMA_MISC_OFF);
+		resources[dma_device].comm_reg_ptr =
+			(volatile sedi_dmac_regs_t *)SEDI_IREG_BASE(DMA, 0);
+	}
+
+	/* init default config context */
+	channel_config_t *config = &(dma_context[dma_device].channel_config[channel_id]);
+
+	dma_set_default_channel_config(config);
+	/*add callback*/
+	dma_context[dma_device].cb_event[channel_id] = cb;
+	dma_context[dma_device].cb_param[channel_id] = param;
+
+	volatile sedi_dma_regs_t *chan_regs = resources[dma_device].chan_reg_ptrs[channel_id];
+
+	mask_channel_interrupt(chan_regs);
+	clear_channel_interrupt(chan_regs);
+	dma_context[dma_device].status[channel_id].busy = 0;
+	dma_context[dma_device].status[channel_id].bus_error = 0;
+
+	return SEDI_DRIVER_OK;
+}
+
+int32_t sedi_dma_uninit(IN sedi_dma_t dma_device, IN int channel_id)
+{
+	DBG_CHECK(dma_device < SEDI_DMA_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(channel_id < DMA_CHANNEL_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+
+	dma_context[dma_device].cb_event[channel_id] = NULL;
+
+	mask_channel_interrupt(resources[dma_device].chan_reg_ptrs[channel_id]);
+	dma_context[dma_device].status[channel_id].busy = 0;
+	dma_context[dma_device].status[channel_id].bus_error = 0;
+	return SEDI_DRIVER_OK;
+}
+
+int dma_fill_linkedlist(INOUT dma_linked_list_item_t *ll_p, IN uint32_t src_addr,
+			IN uint32_t dst_addr, IN uint32_t block_size, uint32_t ctrl_low,
+			IN dma_linked_list_item_t *ll_p_next)
+{
+	return 0;
+}
+
+int32_t sedi_dma_set_power(IN sedi_dma_t dma_device, IN int channel_id, IN sedi_power_state_t state)
+{
+	DBG_CHECK(dma_device < SEDI_DMA_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(channel_id < DMA_CHANNEL_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+
+	int32_t ret = SEDI_DRIVER_OK;
+	unsigned int key = sedi_core_irq_lock();
+	sedi_devid_t devid = SEDI_DEVID_DMA0 + dma_device;
+
+	switch (state) {
+	case SEDI_POWER_FULL:
+		if (dma_context[dma_device].power_status == 0) {
+			sedi_pm_set_device_power(devid, SEDI_POWER_FULL);
+		}
+		dma_context[dma_device].power_status |= BIT(channel_id);
+		break;
+	case SEDI_POWER_LOW:
+	case SEDI_POWER_SUSPEND:
+	case SEDI_POWER_FORCE_SUSPEND:
+		sedi_dma_abort_transfer(dma_device, channel_id);
+		if (dma_context[dma_device].power_status == 0) {
+			break;
+		}
+		dma_context[dma_device].power_status &= (~BIT(channel_id));
+		if (dma_context[dma_device].power_status == 0) {
+			sedi_pm_set_device_power(devid, SEDI_POWER_SUSPEND);
+		}
+		break;
+	case SEDI_POWER_OFF:
+	default:
+		ret = SEDI_DRIVER_ERROR_PARAMETER;
+		break;
+	}
+	sedi_core_irq_unlock(key);
+
+	return ret;
+}
+
+int32_t sedi_dma_control(IN sedi_dma_t dma_device, IN int channel_id, IN uint32_t control_id,
+			 IN uint32_t arg)
+{
+	DBG_CHECK(dma_device < SEDI_DMA_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(channel_id < DMA_CHANNEL_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(control_id < SEDI_CONFIG_DMA_CONTROL_ID_MAX, SEDI_DRIVER_ERROR_PARAMETER);
+
+	channel_config_t *config = &(dma_context[dma_device].channel_config[channel_id]);
+
+	switch (control_id) {
+	case SEDI_CONFIG_DMA_SR_MEM_TYPE:
+		DBG_CHECK(arg < DMA_MEM_TYPE_MAX, SEDI_DRIVER_ERROR_PARAMETER);
+		config->sr_mem_type = arg;
+		break;
+	case SEDI_CONFIG_DMA_DT_MEM_TYPE:
+		DBG_CHECK(arg < DMA_MEM_TYPE_MAX, SEDI_DRIVER_ERROR_PARAMETER);
+		config->dt_mem_type = arg;
+		break;
+	case SEDI_CONFIG_DMA_DIRECTION:
+		DBG_CHECK(arg < DMA_DIRECTION_MAX, SEDI_DRIVER_ERROR_PARAMETER);
+		config->direction = arg;
+		break;
+	case SEDI_CONFIG_DMA_BURST_LENGTH:
+		DBG_CHECK(arg < DMA_BURST_TRANS_LENGTH_MAX, SEDI_DRIVER_ERROR_PARAMETER);
+		config->burst_length = arg;
+		break;
+	case SEDI_CONFIG_DMA_SR_TRANS_WIDTH:
+		DBG_CHECK(arg < DMA_TRANS_WIDTH_128, SEDI_DRIVER_ERROR_PARAMETER);
+		config->sr_width = arg;
+		break;
+	case SEDI_CONFIG_DMA_DT_TRANS_WIDTH:
+		DBG_CHECK(arg < DMA_TRANS_WIDTH_128, SEDI_DRIVER_ERROR_PARAMETER);
+		config->dt_width = arg;
+		break;
+#if PERI_SUPPORT
+	case SEDI_CONFIG_DMA_HS_DEVICE_ID:
+		config->handshake_device_id = arg;
+		break;
+	case SEDI_CONFIG_DMA_HS_DEVICE_ID_PER_DIR:
+		config->peripheral_direction = arg;
+		break;
+	case SEDI_CONFIG_DMA_HS_POLARITY:
+		DBG_CHECK(arg < DMA_HS_PER_RTX_MAX, SEDI_DRIVER_ERROR_PARAMETER);
+		config->handshake_polarity = arg;
+		break;
+#endif
+#ifdef LINKED_LIST_SUPPORT
+	case SEDI_CONFIG_DMA_LL_HEADER:
+		DBG_CHECK((arg), SEDI_DRIVER_ERROR_PARAMETER);
+		config->linked_list_header = (dma_linked_list_item_t *)arg;
+		break;
+#endif
+	default:
+		return SEDI_DRIVER_ERROR_PARAMETER;
+	}
+	config->config_applied = 0;
+	return SEDI_DRIVER_OK;
+}
+
+int sedi_dma_get_status(IN sedi_dma_t dma_device, IN int channel_id, OUT sedi_dma_status_t *status)
+{
+	DBG_CHECK(dma_device < SEDI_DMA_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(channel_id < DMA_CHANNEL_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+
+	*status = dma_context[dma_device].status[channel_id];
+	return SEDI_DRIVER_OK;
+}
+
+static int32_t dma_channel_apply_config(IN sedi_dma_t dma_device, IN int channel_id)
+{
+	channel_config_t *config = &(dma_context[dma_device].channel_config[channel_id]);
+	volatile sedi_dma_regs_t *chan_regs = resources[dma_device].chan_reg_ptrs[channel_id];
+
+	uint64_t chx_ctl = 0, chx_cfg = 0;
+
+	/*return if no need to config*/
+	if (config->config_applied == 1) {
+		return SEDI_DRIVER_OK;
+	}
+
+	DBG_CHECK(config->direction < DMA_DIRECTION_MAX, SEDI_DRIVER_ERROR_PARAMETER);
+	if (config->tf_mode == DMA_TYPE_SINGLE) {
+		/* single block mode config check */
+		DBG_CHECK(config->burst_length < DMA_BURST_TRANS_LENGTH_MAX,
+			  SEDI_DRIVER_ERROR_PARAMETER);
+		DBG_CHECK(config->sr_width < DMA_TRANS_WIDTH_MAX, SEDI_DRIVER_ERROR_PARAMETER);
+		DBG_CHECK(config->dt_width < DMA_TRANS_WIDTH_MAX, SEDI_DRIVER_ERROR_PARAMETER);
+		DBG_CHECK(config->peripheral_direction < DMA_HS_PER_RTX_MAX,
+			  SEDI_DRIVER_ERROR_PARAMETER);
+		/*set dest and src burst size */
+		chx_ctl = SEDI_RBFM_VALUE(DMA, CTL, DST_MSIZE, config->burst_length) |
+			  SEDI_RBFM_VALUE(DMA, CTL, SRC_MSIZE, config->burst_length) |
+			  SEDI_RBFM_VALUE(DMA, CTL, DST_TR_WIDTH, config->dt_width) |
+			  SEDI_RBFM_VALUE(DMA, CTL, SRC_TR_WIDTH, config->sr_width);
+		chx_cfg = SEDI_RBFM_VALUE(DMA, CFG2, TT_FC, config->direction);
+
+		if ((config->direction == DMA_PERIPHERAL_TO_MEMORY) ||
+		    (config->direction == DMA_PERIPHERAL_TO_PERIPHERAL)) {
+			chx_ctl |= SEDI_RBFVM(DMA, CTL, SINC, FIXED);
+			chx_cfg |=
+				SEDI_RBFM_VALUE(DMA, CFG2, SRC_PER, config->handshake_device_id) |
+				SEDI_RBFM_VALUE(DMA, CFG2, SRC_HWHS_POL,
+						config->handshake_polarity);
+		}
+		if ((config->direction == DMA_MEMORY_TO_PERIPHERAL) ||
+		    (config->direction == DMA_PERIPHERAL_TO_PERIPHERAL)) {
+			chx_ctl |= SEDI_RBFVM(DMA, CTL, DINC, FIXED);
+			chx_cfg |=
+				SEDI_RBFM_VALUE(DMA, CFG2, DST_PER, config->handshake_device_id) |
+				SEDI_RBFM_VALUE(DMA, CFG2, DST_HWHS_POL,
+						config->handshake_polarity);
+		}
+	}
+#ifdef LINKED_LIST_SUPPORT
+	else if (config->tf_mode == DMA_TYPE_MULTI_LL) {
+		return SEDI_DRIVER_ERROR_UNSUPPORTED;
+	}
+#endif
+	else {
+		return SEDI_DRIVER_ERROR_UNSUPPORTED;
+	}
+
+	chan_regs->ctl = chx_ctl;
+	chan_regs->cfg2 = chx_cfg;
+
+	uint32_t misc_ctl = 0;
+
+	/* memory type related registers config*/
+	/* source is memory*/
+	if ((config->direction == DMA_MEMORY_TO_PERIPHERAL) ||
+	    (config->direction == DMA_MEMORY_TO_MEMORY)) {
+		if (config->sr_mem_type == DMA_UMA_MEM) {
+			misc_ctl |= SEDI_RBFM_VALUE(DMA_MISC, CTL_CH, RD_RS, DMA_RS3);
+		}
+		if (config->sr_mem_type != DMA_SRAM_MEM) {
+			misc_ctl |= SR_IS_IN_DRAM | SEDI_RBFVM(DMA_MISC, CTL_CH, RD_NON_SNOOP, 1);
+		}
+	}
+	/* destination is memory*/
+	if ((config->direction == DMA_PERIPHERAL_TO_MEMORY) ||
+	    (config->direction == DMA_MEMORY_TO_MEMORY)) {
+		if (config->dt_mem_type == DMA_UMA_MEM) {
+			misc_ctl |= SEDI_RBFM_VALUE(DMA_MISC, CTL_CH, WR_RS, DMA_RS3);
+		}
+		if (config->dt_mem_type != DMA_SRAM_MEM) {
+			misc_ctl |= DT_IS_IN_DRAM | SEDI_RBFVM(DMA_MISC, CTL_CH, WR_NON_SNOOP, 1);
+		}
+	}
+	if ((config->sr_mem_type != DMA_SRAM_MEM) || (config->dt_mem_type != DMA_SRAM_MEM)) {
+		dma_vnn_req(dma_device, channel_id);
+	}
+
+	resources[dma_device].chan_misc_regs[channel_id] = misc_ctl;
+
+	config->config_applied = 1;
+	return SEDI_DRIVER_OK;
+}
+
+#define DMA_MAX_BLOCK_SIZE (4096) /* ref ISH5p8 HAS */
+int32_t sedi_dma_start_transfer(IN sedi_dma_t dma_device, IN int channel_id, IN uint64_t sr_addr,
+				IN uint64_t dest_addr, IN uint32_t length)
+{
+	DBG_CHECK(dma_device < SEDI_DMA_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(channel_id < DMA_CHANNEL_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(sr_addr > 0, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(dest_addr > 0, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(length > 0, SEDI_DRIVER_ERROR_PARAMETER);
+
+	dma_context_t *ctx = &dma_context[dma_device];
+	uint16_t sr_width = ctx->channel_config[channel_id].sr_width;
+
+	if (length > (DMA_MAX_BLOCK_SIZE << sr_width)) {
+		return SEDI_DRIVER_ERROR_PARAMETER;
+	}
+
+	if (ctx->status[channel_id].busy == 1) {
+		return SEDI_DRIVER_ERROR_BUSY;
+	}
+	ctx->status[channel_id].busy = 1;
+	ctx->status[channel_id].bus_error = 0;
+	ctx->channel_config[channel_id].tf_mode = DMA_TYPE_SINGLE;
+	return sedi_dma_start_transfer_aux(dma_device, channel_id, sr_addr, dest_addr, length, 0);
+}
+
+int32_t sedi_dma_start_transfer_polling(IN sedi_dma_t dma_device, IN int channel_id,
+					IN uint64_t sr_addr, IN uint64_t dest_addr,
+					IN uint32_t length)
+{
+	DBG_CHECK(dma_device < SEDI_DMA_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(channel_id < DMA_CHANNEL_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(sr_addr > 0, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(dest_addr > 0, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(length > 0, SEDI_DRIVER_ERROR_PARAMETER);
+
+	dma_context_t *ctx = &dma_context[dma_device];
+	uint16_t sr_width = ctx->channel_config[channel_id].sr_width;
+
+	if (length > (DMA_MAX_BLOCK_SIZE << sr_width)) {
+		return SEDI_DRIVER_ERROR_PARAMETER;
+	}
+
+	if (ctx->status[channel_id].busy == 1) {
+		return SEDI_DRIVER_ERROR_BUSY;
+	}
+	ctx->status[channel_id].busy = 1;
+	ctx->status[channel_id].bus_error = 0;
+	ctx->channel_config[channel_id].tf_mode = DMA_TYPE_SINGLE;
+	return sedi_dma_start_transfer_aux(dma_device, channel_id, sr_addr, dest_addr, length, 1);
+}
+
+static inline int32_t cal_block_ts(channel_config_t *config, uint32_t length)
+{
+	uint32_t sr_width_in_byte = 1 << (config->sr_width);
+
+	if (length % sr_width_in_byte) {
+		return length >> config->sr_width;
+	} else {
+		return (length >> config->sr_width) - 1;
+	}
+}
+
+static int32_t sedi_dma_start_transfer_aux(sedi_dma_t dma_device, int channel_id, uint64_t sr_addr,
+					   uint64_t dest_addr, uint32_t length, uint8_t polling)
+{
+	int32_t ret = SEDI_DRIVER_OK;
+	volatile sedi_dmac_regs_t *dmac_ptr = resources[dma_device].comm_reg_ptr;
+	volatile sedi_dma_regs_t *chan_regs = resources[dma_device].chan_reg_ptrs[channel_id];
+	channel_config_t *config = &(dma_context[dma_device].channel_config[channel_id]);
+
+	if (dmac_ptr->chenreg & (1 << channel_id)) {
+		return SEDI_DRIVER_ERROR_BUSY;
+	}
+	/* channel config*/
+	ret = dma_channel_apply_config(dma_device, channel_id);
+	if (ret != SEDI_DRIVER_OK) {
+		dma_context[dma_device].status[channel_id].busy = 0;
+		return ret;
+	}
+	if (config->tf_mode == DMA_TYPE_SINGLE) {
+		chan_regs->sar = sr_addr;
+		chan_regs->dar = dest_addr;
+		chan_regs->block_ts = cal_block_ts(config, length);
+	}
+#ifdef LINKED_LIST_SUPPORT
+	else if (config->tf_mode == DMA_TYPE_MULTI_LL) {
+		/* TODO */
+	}
+#endif
+
+	dmac_ptr->commonreg_intstatus_enablereg = 0;
+	dmac_ptr->commonreg_intsignal_enablereg = 0;
+	if (polling) {
+		/* TODO: should be mask, but can't distinguish reason now */
+		mask_channel_interrupt(chan_regs);
+	} else {
+		/* enable interrupt */
+		unmask_channel_interrupt(chan_regs);
+	}
+	dmac_ptr->cfgreg = SEDI_RBFVM(DMAC, CFGREG, DMAC_EN, ENABLED) |
+			   SEDI_RBFVM(DMAC, CFGREG, INT_EN, ENABLED);
+
+	/* enable channel*/
+	uint64_t chan_en_mask = SEDI_RBFVM(DMAC, CHENREG, CH1_EN, ENABLE_CH1) |
+				SEDI_RBFVM(DMAC, CHENREG, CH1_EN_WE, ENABLE_WR_CH1_EN);
+	chan_en_mask <<= channel_id;
+	dmac_ptr->chenreg |= chan_en_mask;
+	if (polling) {
+		if (SEDI_DMA_POLL_UNTIL(!(dmac_ptr->chenreg & chan_en_mask)) != SEDI_DRIVER_OK) {
+			ret = SEDI_DRIVER_ERROR;
+		}
+		dma_transfer_post(dma_device, channel_id, chan_regs->intstatus);
+	} else {
+		dma_set_default_channel_config(config);
+	}
+	return ret;
+}
+
+int32_t sedi_dma_abort_transfer(IN sedi_dma_t dma_device, IN int channel_id)
+{
+	DBG_CHECK(dma_device < SEDI_DMA_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+	DBG_CHECK(channel_id < DMA_CHANNEL_NUM, SEDI_DRIVER_ERROR_PARAMETER);
+
+	int32_t ret = SEDI_DRIVER_OK;
+	volatile uint64_t *chenreg_ptr = &resources[dma_device].comm_reg_ptr->chenreg;
+
+	if (dma_context[dma_device].status[channel_id].busy == 0) {
+		return SEDI_DRIVER_OK;
+	}
+
+	const uint64_t ch_susp_sts_test_bit = SEDI_RBFVM(DMAC, CHENREG, CH1_SUSP, ENABLE_CH1_SUSP)
+					      << channel_id;
+	*chenreg_ptr = ch_susp_sts_test_bit |
+		       (SEDI_RBFVM(DMAC, CHENREG, CH1_SUSP_WE, ENABLE_WR_CH1_SUSP) << channel_id);
+	/* Wait until the channel is suspended or timeout occurs */
+	if (SEDI_DMA_POLL_UNTIL(!(*chenreg_ptr & ch_susp_sts_test_bit)) != SEDI_DRIVER_OK) {
+		ret = SEDI_DRIVER_ERROR;
+	}
+	*chenreg_ptr = SEDI_RBFVM(DMAC, CHENREG, CH1_ABORT, ENABLE_CH1_ABORT) << channel_id;
+
+	dma_transfer_post(dma_device, channel_id, 0);
+	return ret;
+}
+
+int32_t sedi_dma_start_ll_transfer(IN sedi_dma_t dma_device, IN int channel_id,
+				   IN dma_linked_list_item_t *linkedlist_header)
+{
+	return 0;
+}
+
+static void dma_transfer_post(sedi_dma_t dev, int chn, uint64_t interrupt_status)
+{
+	channel_config_t *config = &(dma_context[dev].channel_config[chn]);
+	volatile sedi_dma_regs_t *chan_regs = resources[dev].chan_reg_ptrs[chn];
+	sedi_dma_event_cb_t cb;
+	void *usr_param;
+
+	/* clear interrupt*/
+	clear_channel_interrupt(chan_regs);
+
+	dma_vnn_dereq(dev, chn);
+
+	dma_set_default_channel_config(config);
+	dma_context[dev].status[chn].busy = 0;
+
+	cb = dma_context[dev].cb_event[chn];
+	usr_param = dma_context[dev].cb_param[chn];
+	if (interrupt_status & CH_TFR_DONE_INTR) {
+		if (cb != NULL) {
+			cb(dev, chn, SEDI_DMA_EVENT_TRANSFER_DONE, usr_param);
+		}
+	}
+	if (interrupt_status & CH_TFR_ERR_INTR) {
+		dma_context[dev].status[chn].bus_error = 1;
+		if (cb != NULL) {
+			cb(dev, chn, SEDI_DMA_EVENT_BUS_ERROR, usr_param);
+		}
+	}
+}
+
+void dma_isr(IN sedi_dma_t dev)
+{
+	uint64_t interrupt_status;
+	volatile sedi_dmac_regs_t *dmac_ptr = resources[dev].comm_reg_ptr;
+
+	for (int chn = 0; chn < DMA_PHY_CHAN_NUM; chn++) {
+		interrupt_status = resources[dev].chan_reg_ptrs[chn]->intstatus;
+		if (dmac_ptr->intstatusreg &
+		    (SEDI_RBFVM(DMAC, INTSTATUSREG, CH1_IntStat, ACTIVE) << chn)) {
+			if ((interrupt_status & CH_TFR_DONE_INTR) ||
+			    (interrupt_status & CH_TFR_ERR_INTR)) {
+				dma_transfer_post(dev, chn, interrupt_status);
+			}
+		}
+	}
+}
diff --git a/bsp_sedi/soc/common/include/sedi_dma_misc_regs.h b/bsp_sedi/soc/common/include/sedi_dma_misc_regs.h
new file mode 100644
index 0000000..e012d53
--- /dev/null
+++ b/bsp_sedi/soc/common/include/sedi_dma_misc_regs.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2023-2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * This file has been automatically generated
+ * Tool Version: 1.0.0
+ * Generation Date: 2023-09-19
+ */
+
+#ifndef _SEDI_DMA_MISC_REGS_H_
+#define _SEDI_DMA_MISC_REGS_H_
+
+#include <sedi_reg_defs.h>
+
+
+/* ********* DMA_MISC CTL_CH ***********
+ *
+ * Register of SEDI DMA_MISC
+ *   CTL_CH: DMA Channel Control register
+ *     AddressOffset  : 0x0
+ *     AccessType     : RW
+ *     WritableBitMask: 0x77b
+ *     ResetValue     : (uint32_t)0x0
+ */
+SEDI_REG_DEFINE(DMA_MISC, CTL_CH, 0x0, RW, (uint32_t)0x77b, (uint32_t)0x0);
+
+/*
+ * Bit Field of Register CTL_CH
+ *   TRANSFER_MODE: DMA Transfer Mode
+ *     BitOffset : 0
+ *     BitWidth  : 2
+ *     AccessType: RW
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_CH, TRANSFER_MODE, 0, 2, RW, (uint32_t)0x0);
+
+/*
+ * Bit Field of Register CTL_CH
+ *   RESERVED2: Non Snoop Attribute
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_CH, RESERVED2, 2, 1, RO, (uint32_t)0x0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, RESERVED2, 0, 0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, RESERVED2, 1, 1);
+
+/*
+ * Bit Field of Register CTL_CH
+ *   RD_RS: Read Root Space
+ *     BitOffset : 3
+ *     BitWidth  : 2
+ *     AccessType: RW
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_CH, RD_RS, 3, 2, RW, (uint32_t)0x0);
+
+/*
+ * Bit Field of Register CTL_CH
+ *   WR_RS: Write Root Space
+ *     BitOffset : 5
+ *     BitWidth  : 2
+ *     AccessType: RW
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_CH, WR_RS, 5, 2, RW, (uint32_t)0x0);
+
+/*
+ * Bit Field of Register CTL_CH
+ *   RESERVED1:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_CH, RESERVED1, 7, 1, RO, (uint32_t)0x0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, RESERVED1, 0, 0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, RESERVED1, 1, 1);
+
+/*
+ * Bit Field of Register CTL_CH
+ *   RD_NON_SNOOP: IOSF Virtual Channel
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_CH, RD_NON_SNOOP, 8, 1, RW, (uint32_t)0x0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, RD_NON_SNOOP, 0, 0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, RD_NON_SNOOP, 1, 1);
+
+/*
+ * Bit Field of Register CTL_CH
+ *   WR_NON_SNOOP: IOSF MdestID, Function Selection Bits
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_CH, WR_NON_SNOOP, 9, 1, RW, (uint32_t)0x0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, WR_NON_SNOOP, 0, 0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, WR_NON_SNOOP, 1, 1);
+
+/*
+ * Bit Field of Register CTL_CH
+ *   LLI_MODE: LLI Mode Selection
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_CH, LLI_MODE, 10, 1, RW, (uint32_t)0x0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, LLI_MODE, 0, 0);
+SEDI_RBFV_DEFINE(DMA_MISC, CTL_CH, LLI_MODE, 1, 1);
+
+/*
+ * Bit Field of Register CTL_CH
+ *   RESERVED0:
+ *     BitOffset : 11
+ *     BitWidth  : 21
+ *     AccessType: RO
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_CH, RESERVED0, 11, 21, RO, (uint32_t)0x0);
+
+/* ********* DMA_MISC CTL_SPARE ***********
+ *
+ * Register of SEDI DMA_MISC
+ *   CTL_SPARE: Spare Register
+ *     AddressOffset  : 0x100
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffff
+ *     ResetValue     : (uint32_t)0x0
+ */
+SEDI_REG_DEFINE(DMA_MISC, CTL_SPARE, 0x100, RW, (uint32_t)0xffffffff, (uint32_t)0x0);
+
+/*
+ * Bit Field of Register CTL_SPARE
+ *   SPARE: Spare
+ *     BitOffset : 0
+ *     BitWidth  : 32
+ *     AccessType: RW
+ *     ResetValue: (uint32_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA_MISC, CTL_SPARE, SPARE, 0, 32, RW, (uint32_t)0x0);
+
+/*
+ * Registers' Address Map Structure
+ */
+
+typedef struct {
+	/* DMA Channel Control register */
+	__IO_RW uint32_t ctl_ch[8];
+
+	/* Reserved */
+	__IO_RW uint32_t reserved0[55];
+
+	/* Spare Register */
+	__IO_RW uint32_t ctl_spare;
+
+} sedi_dma_misc_regs_t;
+#define SEDI_DMA_MISC_REGS_T sedi_dma_misc_regs_t
+
+
+#endif /* _SEDI_DMA_MISC_REGS_H_ */
diff --git a/bsp_sedi/soc/common/include/sedi_dma_regs.h b/bsp_sedi/soc/common/include/sedi_dma_regs.h
new file mode 100644
index 0000000..4e9cb39
--- /dev/null
+++ b/bsp_sedi/soc/common/include/sedi_dma_regs.h
@@ -0,0 +1,3137 @@
+/*
+ * Copyright (c) 2023-2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * This file has been automatically generated
+ * Tool Version: 1.0.0
+ * Generation Date: 2023-08-01
+ */
+
+#ifndef _SEDI_DMA_REGS_H_
+#define _SEDI_DMA_REGS_H_
+
+#include <sedi_reg_defs.h>
+
+/* ********* DMA SAR ***********
+ *
+ * Register of SEDI DMA
+ *   SAR: DW_axi_dmac Channel x Source Address Register
+ *     AddressOffset  : 0x0
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffffffffffff
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, SAR, 0x0, RW, (uint64_t)0xffffffffffffffff, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register SAR
+ *   SAR:
+ *     BitOffset : 0
+ *     BitWidth  : 64
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SAR, SAR, 0, 64, RW, (uint64_t)0x0);
+
+/* ********* DMA DAR ***********
+ *
+ * Register of SEDI DMA
+ *   DAR: DW_axi_dmac Channel x Destination Address Register
+ *     AddressOffset  : 0x8
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffffffffffff
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, DAR, 0x8, RW, (uint64_t)0xffffffffffffffff, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register DAR
+ *   DAR:
+ *     BitOffset : 0
+ *     BitWidth  : 64
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, DAR, DAR, 0, 64, RW, (uint64_t)0x0);
+
+/* ********* DMA BLOCK_TS ***********
+ *
+ * Register of SEDI DMA
+ *   BLOCK_TS: DW_axi_dmac Channel x Block Transfer Size Register
+ *     AddressOffset  : 0x10
+ *     AccessType     : RW
+ *     WritableBitMask: 0x3fffff
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, BLOCK_TS, 0x10, RW, (uint64_t)0x3fffff, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register BLOCK_TS
+ *   BLOCK_TS:
+ *     BitOffset : 0
+ *     BitWidth  : 22
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, BLOCK_TS, BLOCK_TS, 0, 22, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register BLOCK_TS
+ *   RSVD_DMAC_CHx_BLOCK_TSREG_63to22:
+ *     BitOffset : 22
+ *     BitWidth  : 42
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, BLOCK_TS, RSVD_DMAC_CHx_BLOCK_TSREG_63to22, 22, 42, RO, (uint64_t)0x0);
+
+/* ********* DMA CTL ***********
+ *
+ * Register of SEDI DMA
+ *   CTL: DW_axi_dmac Channel x Control Register
+ *     AddressOffset  : 0x18
+ *     AccessType     : RW
+ *     WritableBitMask: 0xc7ffffff7fffff50
+ *     ResetValue     : (uint64_t)0x1200
+ */
+SEDI_REG_DEFINE(DMA, CTL, 0x18, RW, (uint64_t)0xc7ffffff7fffff50, (uint64_t)0x1200);
+
+/*
+ * Bit Field of Register CTL
+ *   SMS:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, SMS, 0, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, SMS, MASTER1_INTF, 0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, SMS, MASTER2_INTF, 0x1);
+
+/*
+ * Bit Field of Register CTL
+ *   RSVD_DMAC_CHx_CTL_1:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_1, 1, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_1, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_1, 1, 1);
+
+/*
+ * Bit Field of Register CTL
+ *   DMS:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, DMS, 2, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, DMS, MASTER1_INTF, 0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, DMS, MASTER2_INTF, 0x1);
+
+/*
+ * Bit Field of Register CTL
+ *   RSVD_DMAC_CHx_CTL_3:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_3, 3, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_3, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_3, 1, 1);
+
+/*
+ * Bit Field of Register CTL
+ *   SINC:
+ *     BitOffset : 4
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, SINC, 4, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, SINC, FIXED, 0x1);
+SEDI_RBFV_DEFINE(DMA, CTL, SINC, INCREMENTAL, 0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   RSVD_DMAC_CHx_CTL_5:
+ *     BitOffset : 5
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_5, 5, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_5, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_5, 1, 1);
+
+/*
+ * Bit Field of Register CTL
+ *   DINC:
+ *     BitOffset : 6
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, DINC, 6, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, DINC, FIXED, 0x1);
+SEDI_RBFV_DEFINE(DMA, CTL, DINC, INCREMENTAL, 0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   RSVD_DMAC_CHx_CTL_7:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_7, 7, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_7, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_7, 1, 1);
+
+/*
+ * Bit Field of Register CTL
+ *   SRC_TR_WIDTH:
+ *     BitOffset : 8
+ *     BitWidth  : 3
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x2
+ */
+SEDI_RBF_DEFINE(DMA, CTL, SRC_TR_WIDTH, 8, 3, RW, (uint64_t)0x2);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_TR_WIDTH, BITS_128, 0x4);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_TR_WIDTH, BITS_16, 0x1);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_TR_WIDTH, BITS_256, 0x5);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_TR_WIDTH, BITS_32, 0x2);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_TR_WIDTH, BITS_512, 0x6);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_TR_WIDTH, BITS_64, 0x3);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_TR_WIDTH, BITS_8, 0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   DST_TR_WIDTH:
+ *     BitOffset : 11
+ *     BitWidth  : 3
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x2
+ */
+SEDI_RBF_DEFINE(DMA, CTL, DST_TR_WIDTH, 11, 3, RW, (uint64_t)0x2);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_TR_WIDTH, BITS_128, 0x4);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_TR_WIDTH, BITS_16, 0x1);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_TR_WIDTH, BITS_256, 0x5);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_TR_WIDTH, BITS_32, 0x2);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_TR_WIDTH, BITS_512, 0x6);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_TR_WIDTH, BITS_64, 0x3);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_TR_WIDTH, BITS_8, 0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   SRC_MSIZE:
+ *     BitOffset : 14
+ *     BitWidth  : 4
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, SRC_MSIZE, 14, 4, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEMS_1024, 0x9);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEMS_128, 0x6);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEMS_16, 0x3);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEMS_256, 0x7);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEMS_32, 0x4);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEMS_4, 0x1);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEMS_512, 0x8);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEMS_64, 0x5);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEMS_8, 0x2);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_MSIZE, DATA_ITEM_1, 0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   DST_MSIZE:
+ *     BitOffset : 18
+ *     BitWidth  : 4
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, DST_MSIZE, 18, 4, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEMS_1024, 0x9);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEMS_128, 0x6);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEMS_16, 0x3);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEMS_256, 0x7);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEMS_32, 0x4);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEMS_4, 0x1);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEMS_512, 0x8);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEMS_64, 0x5);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEMS_8, 0x2);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_MSIZE, DATA_ITEM_1, 0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   AR_CACHE:
+ *     BitOffset : 22
+ *     BitWidth  : 4
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, AR_CACHE, 22, 4, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   AW_CACHE:
+ *     BitOffset : 26
+ *     BitWidth  : 4
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, AW_CACHE, 26, 4, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   NonPosted_LastWrite_En:
+ *     BitOffset : 30
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, NonPosted_LastWrite_En, 30, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, NonPosted_LastWrite_En, Disable, 0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, NonPosted_LastWrite_En, Enable, 0x1);
+
+/*
+ * Bit Field of Register CTL
+ *   RSVD_DMAC_CHx_CTL_31:
+ *     BitOffset : 31
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_31, 31, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_31, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_31, 1, 1);
+
+/*
+ * Bit Field of Register CTL
+ *   AR_PROT:
+ *     BitOffset : 32
+ *     BitWidth  : 3
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, AR_PROT, 32, 3, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   AW_PROT:
+ *     BitOffset : 35
+ *     BitWidth  : 3
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, AW_PROT, 35, 3, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   ARLEN_EN:
+ *     BitOffset : 38
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, ARLEN_EN, 38, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, ARLEN_EN, Disable, 0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, ARLEN_EN, Enable, 0x1);
+
+/*
+ * Bit Field of Register CTL
+ *   ARLEN:
+ *     BitOffset : 39
+ *     BitWidth  : 8
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, ARLEN, 39, 8, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   AWLEN_EN:
+ *     BitOffset : 47
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, AWLEN_EN, 47, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, AWLEN_EN, Disable, 0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, AWLEN_EN, Enable, 0x1);
+
+/*
+ * Bit Field of Register CTL
+ *   AWLEN:
+ *     BitOffset : 48
+ *     BitWidth  : 8
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, AWLEN, 48, 8, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   SRC_STAT_EN:
+ *     BitOffset : 56
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, SRC_STAT_EN, 56, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_STAT_EN, Enable_STAT_FETCH, 0x1);
+SEDI_RBFV_DEFINE(DMA, CTL, SRC_STAT_EN, NO_STAT_FETCH, 0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   DST_STAT_EN:
+ *     BitOffset : 57
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, DST_STAT_EN, 57, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_STAT_EN, Enable_STAT_FETCH, 0x1);
+SEDI_RBFV_DEFINE(DMA, CTL, DST_STAT_EN, NO_STAT_FETCH, 0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   IOC_BlkTfr:
+ *     BitOffset : 58
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, IOC_BlkTfr, 58, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, IOC_BlkTfr, DISABLE_BLKTFR_INTR, 0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, IOC_BlkTfr, Enable_BLKTFR_INTR, 0x1);
+
+/*
+ * Bit Field of Register CTL
+ *   RSVD_DMAC_CHx_CTL_59to61:
+ *     BitOffset : 59
+ *     BitWidth  : 3
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, RSVD_DMAC_CHx_CTL_59to61, 59, 3, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   SHADOWREG_OR_LLI_LAST:
+ *     BitOffset : 62
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, SHADOWREG_OR_LLI_LAST, 62, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, SHADOWREG_OR_LLI_LAST, LAST_ITEM, 0x1);
+SEDI_RBFV_DEFINE(DMA, CTL, SHADOWREG_OR_LLI_LAST, NOT_LAST_ITEM, 0x0);
+
+/*
+ * Bit Field of Register CTL
+ *   SHADOWREG_OR_LLI_VALID:
+ *     BitOffset : 63
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CTL, SHADOWREG_OR_LLI_VALID, 63, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, SHADOWREG_OR_LLI_VALID, INVALID, 0x0);
+SEDI_RBFV_DEFINE(DMA, CTL, SHADOWREG_OR_LLI_VALID, VALID, 0x1);
+
+/* ********* DMA CFG2 ***********
+ *
+ * Register of SEDI DMA
+ *   CFG2: DW_axi_dmac Channel x Configuration Register 2
+ *     AddressOffset  : 0x20
+ *     AccessType     : RW
+ *     WritableBitMask: 0x7fff801f0000f9ff
+ *     ResetValue     : (uint64_t)0x3801b00000000
+ */
+SEDI_REG_DEFINE(DMA, CFG2, 0x20, RW, (uint64_t)0x7fff801f0000f9ff, (uint64_t)0x3801b00000000);
+
+/*
+ * Bit Field of Register CFG2
+ *   SRC_MULTBLK_TYPE:
+ *     BitOffset : 0
+ *     BitWidth  : 2
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, SRC_MULTBLK_TYPE, 0, 2, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, SRC_MULTBLK_TYPE, CONTINGUOUS, 0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, SRC_MULTBLK_TYPE, LINKED_LIST, 0x3);
+SEDI_RBFV_DEFINE(DMA, CFG2, SRC_MULTBLK_TYPE, RELOAD, 0x1);
+SEDI_RBFV_DEFINE(DMA, CFG2, SRC_MULTBLK_TYPE, SHADOW_REGISTER, 0x2);
+
+/*
+ * Bit Field of Register CFG2
+ *   DST_MULTBLK_TYPE:
+ *     BitOffset : 2
+ *     BitWidth  : 2
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, DST_MULTBLK_TYPE, 2, 2, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, DST_MULTBLK_TYPE, CONTINGUOUS, 0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, DST_MULTBLK_TYPE, LINKED_LIST, 0x3);
+SEDI_RBFV_DEFINE(DMA, CFG2, DST_MULTBLK_TYPE, RELOAD, 0x1);
+SEDI_RBFV_DEFINE(DMA, CFG2, DST_MULTBLK_TYPE, SHADOW_REGISTER, 0x2);
+
+/*
+ * Bit Field of Register CFG2
+ *   SRC_PER:
+ *     BitOffset : 4
+ *     BitWidth  : 5
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, SRC_PER, 4, 5, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   RSVD_DMAC_CHx_CFG_9_4:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_9_4, 9, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_9_4, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_9_4, 1, 1);
+
+/*
+ * Bit Field of Register CFG2
+ *   RSVD_DMAC_CHx_CFG_10:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_10, 10, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_10, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_10, 1, 1);
+
+/*
+ * Bit Field of Register CFG2
+ *   DST_PER:
+ *     BitOffset : 11
+ *     BitWidth  : 5
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, DST_PER, 11, 5, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   RSVD_DMAC_CHx_CFG_16_11:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_16_11, 16, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_16_11, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_16_11, 1, 1);
+
+/*
+ * Bit Field of Register CFG2
+ *   RSVD_DMAC_CHx_CFG_17:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_17, 17, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_17, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_17, 1, 1);
+
+/*
+ * Bit Field of Register CFG2
+ *   RD_UID:
+ *     BitOffset : 18
+ *     BitWidth  : 4
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, RD_UID, 18, 4, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   RSVD_DMAC_CHx_CFG_22to24:
+ *     BitOffset : 22
+ *     BitWidth  : 3
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_22to24, 22, 3, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   WR_UID:
+ *     BitOffset : 25
+ *     BitWidth  : 4
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, WR_UID, 25, 4, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   RSVD_DMAC_CHx_CFG_29to31:
+ *     BitOffset : 29
+ *     BitWidth  : 3
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_29to31, 29, 3, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   TT_FC:
+ *     BitOffset : 32
+ *     BitWidth  : 3
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x3
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, TT_FC, 32, 3, RW, (uint64_t)0x3);
+SEDI_RBFV_DEFINE(DMA, CFG2, TT_FC, MEM_TO_MEM_DMAC, 0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, TT_FC, MEM_TO_PER_DMAC, 0x1);
+SEDI_RBFV_DEFINE(DMA, CFG2, TT_FC, MEM_TO_PER_DST, 0x6);
+SEDI_RBFV_DEFINE(DMA, CFG2, TT_FC, PER_TO_MEM_DMAC, 0x2);
+SEDI_RBFV_DEFINE(DMA, CFG2, TT_FC, PER_TO_MEM_SRC, 0x4);
+SEDI_RBFV_DEFINE(DMA, CFG2, TT_FC, PER_TO_PER_DMAC, 0x3);
+SEDI_RBFV_DEFINE(DMA, CFG2, TT_FC, PER_TO_PER_DST, 0x7);
+SEDI_RBFV_DEFINE(DMA, CFG2, TT_FC, PER_TO_PER_SRC, 0x5);
+
+/*
+ * Bit Field of Register CFG2
+ *   HS_SEL_SRC:
+ *     BitOffset : 35
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, HS_SEL_SRC, 35, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, CFG2, HS_SEL_SRC, HARDWARE_HS, 0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, HS_SEL_SRC, SOFTWARE_HS, 0x1);
+
+/*
+ * Bit Field of Register CFG2
+ *   HS_SEL_DST:
+ *     BitOffset : 36
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, HS_SEL_DST, 36, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, CFG2, HS_SEL_DST, HARDWARE_HS, 0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, HS_SEL_DST, SOFTWARE_HS, 0x1);
+
+/*
+ * Bit Field of Register CFG2
+ *   SRC_HWHS_POL:
+ *     BitOffset : 37
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, SRC_HWHS_POL, 37, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, SRC_HWHS_POL, ACTIVE_HIGH, 0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, SRC_HWHS_POL, ACTIVE_LOW, 0x1);
+
+/*
+ * Bit Field of Register CFG2
+ *   DST_HWHS_POL:
+ *     BitOffset : 38
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, DST_HWHS_POL, 38, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, DST_HWHS_POL, ACTIVE_HIGH, 0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, DST_HWHS_POL, ACTIVE_LOW, 0x1);
+
+/*
+ * Bit Field of Register CFG2
+ *   RSVD_DMAC_CHx_CFG_39to46:
+ *     BitOffset : 39
+ *     BitWidth  : 8
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_39to46, 39, 8, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   CH_PRIOR:
+ *     BitOffset : 47
+ *     BitWidth  : 5
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x7
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, CH_PRIOR, 47, 5, RW, (uint64_t)0x7);
+
+/*
+ * Bit Field of Register CFG2
+ *   LOCK_CH:
+ *     BitOffset : 52
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, LOCK_CH, 52, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, LOCK_CH, CHANNEL_LOCK, 0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, LOCK_CH, NO_CHANNEL_LOCK, 0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   LOCK_CH_L:
+ *     BitOffset : 53
+ *     BitWidth  : 2
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, LOCK_CH_L, 53, 2, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   SRC_OSR_LMT:
+ *     BitOffset : 55
+ *     BitWidth  : 4
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, SRC_OSR_LMT, 55, 4, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   DST_OSR_LMT:
+ *     BitOffset : 59
+ *     BitWidth  : 4
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, DST_OSR_LMT, 59, 4, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFG2
+ *   RSVD_DMAC_CHx_CFG_63:
+ *     BitOffset : 63
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_63, 63, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_63, 0, 0);
+SEDI_RBFV_DEFINE(DMA, CFG2, RSVD_DMAC_CHx_CFG_63, 1, 1);
+
+/* ********* DMA LLP ***********
+ *
+ * Register of SEDI DMA
+ *   LLP: DW_axi_dmac Channel x Linked List Pointer Register
+ *     AddressOffset  : 0x28
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffffffffffc0
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, LLP, 0x28, RW, (uint64_t)0xffffffffffffffc0, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register LLP
+ *   LMS:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, LLP, LMS, 0, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, LLP, LMS, MASTER1_INTF, 0x0);
+SEDI_RBFV_DEFINE(DMA, LLP, LMS, MASTER2_INTF, 0x1);
+
+/*
+ * Bit Field of Register LLP
+ *   RSVD_DMAC_CHx_LLP_1to5:
+ *     BitOffset : 1
+ *     BitWidth  : 5
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, LLP, RSVD_DMAC_CHx_LLP_1to5, 1, 5, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register LLP
+ *   LOC:
+ *     BitOffset : 6
+ *     BitWidth  : 58
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, LLP, LOC, 6, 58, RW, (uint64_t)0x0);
+
+/* ********* DMA STATUSREG ***********
+ *
+ * Register of SEDI DMA
+ *   STATUSREG: DW_axi_dmac Channel x Status Register
+ *     AddressOffset  : 0x30
+ *     AccessType     : RO
+ *     WritableBitMask: 0x0
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, STATUSREG, 0x30, RO, (uint64_t)0x0, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register STATUSREG
+ *   CMPLTD_BLK_TFR_SIZE:
+ *     BitOffset : 0
+ *     BitWidth  : 22
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, STATUSREG, CMPLTD_BLK_TFR_SIZE, 0, 22, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register STATUSREG
+ *   RSVD_DMAC_CHx_STATUSREG_22to31:
+ *     BitOffset : 22
+ *     BitWidth  : 10
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, STATUSREG, RSVD_DMAC_CHx_STATUSREG_22to31, 22, 10, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register STATUSREG
+ *   DATA_LEFT_IN_FIFO:
+ *     BitOffset : 32
+ *     BitWidth  : 15
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, STATUSREG, DATA_LEFT_IN_FIFO, 32, 15, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register STATUSREG
+ *   RSVD_DMAC_CHx_STATUSREG_47to63:
+ *     BitOffset : 47
+ *     BitWidth  : 17
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, STATUSREG, RSVD_DMAC_CHx_STATUSREG_47to63, 47, 17, RO, (uint64_t)0x0);
+
+/* ********* DMA SWHSSRCREG ***********
+ *
+ * Register of SEDI DMA
+ *   SWHSSRCREG: DW_axi_dmac Channel x Software Handshake Source Register
+ *     AddressOffset  : 0x38
+ *     AccessType     : RW
+ *     WritableBitMask: 0x3f
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, SWHSSRCREG, 0x38, RW, (uint64_t)0x3f, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register SWHSSRCREG
+ *   SWHS_REQ_SRC:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSSRCREG, SWHS_REQ_SRC, 0, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_REQ_SRC, ACTIVE_SWHS_REQ_SRC, 0x1);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_REQ_SRC, INACTIVE_SWHS_REQ_SRC, 0x0);
+
+/*
+ * Bit Field of Register SWHSSRCREG
+ *   SWHS_REQ_SRC_WE:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSSRCREG, SWHS_REQ_SRC_WE, 1, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_REQ_SRC_WE, DISABLE_SWHS_REQ_SRC, 0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_REQ_SRC_WE, ENABLE_SWHS_REQ_SRC, 0x1);
+
+/*
+ * Bit Field of Register SWHSSRCREG
+ *   SWHS_SGLREQ_SRC:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSSRCREG, SWHS_SGLREQ_SRC, 2, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_SGLREQ_SRC, ACTIVE_SWHS_SGLREQ_SRC, 0x1);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_SGLREQ_SRC, INACTIVE_SWHS_SGLREQ_SRC, 0x0);
+
+/*
+ * Bit Field of Register SWHSSRCREG
+ *   SWHS_SGLREQ_SRC_WE:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSSRCREG, SWHS_SGLREQ_SRC_WE, 3, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_SGLREQ_SRC_WE, DISABLE_SWHS_SGLREQ_SRC, 0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_SGLREQ_SRC_WE, ENABLE_SWHS_SGLREQ_SRC, 0x1);
+
+/*
+ * Bit Field of Register SWHSSRCREG
+ *   SWHS_LST_SRC:
+ *     BitOffset : 4
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSSRCREG, SWHS_LST_SRC, 4, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_LST_SRC, ACTIVE_SWHS_LAST_SRC, 0x1);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_LST_SRC, INACTIVE_SWHS_LAST_SRC, 0x0);
+
+/*
+ * Bit Field of Register SWHSSRCREG
+ *   SWHS_LST_SRC_WE:
+ *     BitOffset : 5
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSSRCREG, SWHS_LST_SRC_WE, 5, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_LST_SRC_WE, DISABLE_SWHS_LAST_SRC, 0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSSRCREG, SWHS_LST_SRC_WE, ENABLE_SWHS_LAST_SRC, 0x1);
+
+/*
+ * Bit Field of Register SWHSSRCREG
+ *   RSVD_DMAC_CHx_SWHSSRCREG_6to63:
+ *     BitOffset : 6
+ *     BitWidth  : 58
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSSRCREG, RSVD_DMAC_CHx_SWHSSRCREG_6to63, 6, 58, RO, (uint64_t)0x0);
+
+/* ********* DMA SWHSDSTREG ***********
+ *
+ * Register of SEDI DMA
+ *   SWHSDSTREG: DW_axi_dmac Channel x Software Handshake Destination Register
+ *     AddressOffset  : 0x40
+ *     AccessType     : RW
+ *     WritableBitMask: 0x3f
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, SWHSDSTREG, 0x40, RW, (uint64_t)0x3f, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register SWHSDSTREG
+ *   SWHS_REQ_DST:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSDSTREG, SWHS_REQ_DST, 0, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_REQ_DST, ACTIVE_SWHS_REQ_DST, 0x1);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_REQ_DST, INACTIVE_SWHS_REQ_DST, 0x0);
+
+/*
+ * Bit Field of Register SWHSDSTREG
+ *   SWHS_REQ_DST_WE:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSDSTREG, SWHS_REQ_DST_WE, 1, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_REQ_DST_WE, DISABLE_SWHS_REQ_DST, 0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_REQ_DST_WE, ENABLE_SWHS_REQ_DST, 0x1);
+
+/*
+ * Bit Field of Register SWHSDSTREG
+ *   SWHS_SGLREQ_DST:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSDSTREG, SWHS_SGLREQ_DST, 2, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_SGLREQ_DST, ACTIVE_SWHS_SGLREQ_DST, 0x1);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_SGLREQ_DST, INACTIVE_SWHS_SGLREQ_DST, 0x0);
+
+/*
+ * Bit Field of Register SWHSDSTREG
+ *   SWHS_SGLREQ_DST_WE:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSDSTREG, SWHS_SGLREQ_DST_WE, 3, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_SGLREQ_DST_WE, DISABLE_SWHS_SGLREQ_DST, 0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_SGLREQ_DST_WE, ENABLE_SWHS_SGLREQ_DST, 0x1);
+
+/*
+ * Bit Field of Register SWHSDSTREG
+ *   SWHS_LST_DST:
+ *     BitOffset : 4
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSDSTREG, SWHS_LST_DST, 4, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_LST_DST, ACTIVE_SWHS_LAST_DST, 0x1);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_LST_DST, INACTIVE_SWHS_LAST_DST, 0x0);
+
+/*
+ * Bit Field of Register SWHSDSTREG
+ *   SWHS_LST_DST_WE:
+ *     BitOffset : 5
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSDSTREG, SWHS_LST_DST_WE, 5, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_LST_DST_WE, DISABLE_SWHS_LAST_DST, 0x0);
+SEDI_RBFV_DEFINE(DMA, SWHSDSTREG, SWHS_LST_DST_WE, ENABLE_SWHS_LAST_DST, 0x1);
+
+/*
+ * Bit Field of Register SWHSDSTREG
+ *   RSVD_DMAC_CHx_SWHSDSTREG_6to63:
+ *     BitOffset : 6
+ *     BitWidth  : 58
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SWHSDSTREG, RSVD_DMAC_CHx_SWHSDSTREG_6to63, 6, 58, RO, (uint64_t)0x0);
+
+/* ********* DMA BLK_TFR_RESUMEREQREG ***********
+ *
+ * Register of SEDI DMA
+ *   BLK_TFR_RESUMEREQREG: DW_axi_dmac Channel x Block Transfer Resume Request Register
+ *     AddressOffset  : 0x48
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffffffffffff
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, BLK_TFR_RESUMEREQREG, 0x48, RW, (uint64_t)0xffffffffffffffff, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register BLK_TFR_RESUMEREQREG
+ *   BLK_TFR_RESUMEREQ:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, BLK_TFR_RESUMEREQREG, BLK_TFR_RESUMEREQ, 0, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, BLK_TFR_RESUMEREQREG, BLK_TFR_RESUMEREQ, ACTIVE_BLK_TFR_RESUMEREQ, 0x1);
+SEDI_RBFV_DEFINE(DMA, BLK_TFR_RESUMEREQREG, BLK_TFR_RESUMEREQ, INACTIVE_BLK_TFR_RESUMEREQ, 0x0);
+
+/*
+ * Bit Field of Register BLK_TFR_RESUMEREQREG
+ *   RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63:
+ *     BitOffset : 1
+ *     BitWidth  : 63
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, BLK_TFR_RESUMEREQREG, RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63, 1, 63, RW,
+		(uint64_t)0x0);
+
+/* ********* DMA AXI_QOSREG ***********
+ *
+ * Register of SEDI DMA
+ *   AXI_QOSREG: DW_axi_dmac Channel x AXI QoS Register
+ *     AddressOffset  : 0x58
+ *     AccessType     : RW
+ *     WritableBitMask: 0x0
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, AXI_QOSREG, 0x58, RW, (uint64_t)0x0, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register AXI_QOSREG
+ *   AXI_AWQOS:
+ *     BitOffset : 0
+ *     BitWidth  : 4
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, AXI_QOSREG, AXI_AWQOS, 0, 4, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register AXI_QOSREG
+ *   AXI_ARQOS:
+ *     BitOffset : 4
+ *     BitWidth  : 4
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, AXI_QOSREG, AXI_ARQOS, 4, 4, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register AXI_QOSREG
+ *   RSVD_DMAC_CHx_AXI_QOSREG_8to63:
+ *     BitOffset : 8
+ *     BitWidth  : 56
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, AXI_QOSREG, RSVD_DMAC_CHx_AXI_QOSREG_8to63, 8, 56, RO, (uint64_t)0x0);
+
+/* ********* DMA SSTAT ***********
+ *
+ * Register of SEDI DMA
+ *   SSTAT: DW_axi_dmac Channel x Source Status Register
+ *     AddressOffset  : 0x60
+ *     AccessType     : RO
+ *     WritableBitMask: 0x0
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, SSTAT, 0x60, RO, (uint64_t)0x0, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register SSTAT
+ *   SSTAT:
+ *     BitOffset : 0
+ *     BitWidth  : 32
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SSTAT, SSTAT, 0, 32, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register SSTAT
+ *   RSVD_DMAC_CHx_SSTAT_32to63:
+ *     BitOffset : 32
+ *     BitWidth  : 32
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SSTAT, RSVD_DMAC_CHx_SSTAT_32to63, 32, 32, RO, (uint64_t)0x0);
+
+/* ********* DMA DSTAT ***********
+ *
+ * Register of SEDI DMA
+ *   DSTAT: DW_axi_dmac Channel x Destination Status Register
+ *     AddressOffset  : 0x68
+ *     AccessType     : RO
+ *     WritableBitMask: 0x0
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, DSTAT, 0x68, RO, (uint64_t)0x0, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register DSTAT
+ *   DSTAT:
+ *     BitOffset : 0
+ *     BitWidth  : 32
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, DSTAT, DSTAT, 0, 32, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register DSTAT
+ *   RSVD_DMAC_CHx_DSTAT_32to63:
+ *     BitOffset : 32
+ *     BitWidth  : 32
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, DSTAT, RSVD_DMAC_CHx_DSTAT_32to63, 32, 32, RO, (uint64_t)0x0);
+
+/* ********* DMA SSTATAR ***********
+ *
+ * Register of SEDI DMA
+ *   SSTATAR: DW_axi_dmac Channel x Source Status Fetch Register
+ *     AddressOffset  : 0x70
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffffffffffff
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, SSTATAR, 0x70, RW, (uint64_t)0xffffffffffffffff, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register SSTATAR
+ *   SSTATAR:
+ *     BitOffset : 0
+ *     BitWidth  : 64
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, SSTATAR, SSTATAR, 0, 64, RW, (uint64_t)0x0);
+
+/* ********* DMA DSTATAR ***********
+ *
+ * Register of SEDI DMA
+ *   DSTATAR: DW_axi_dmac Channel x Destination Status Fetch Register
+ *     AddressOffset  : 0x78
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffffffffffff
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, DSTATAR, 0x78, RW, (uint64_t)0xffffffffffffffff, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register DSTATAR
+ *   DSTATAR:
+ *     BitOffset : 0
+ *     BitWidth  : 64
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, DSTATAR, DSTATAR, 0, 64, RW, (uint64_t)0x0);
+
+/* ********* DMA INTSTATUS_ENABLEREG ***********
+ *
+ * Register of SEDI DMA
+ *   INTSTATUS_ENABLEREG: DW_axi_dmac Channel x Interrupt Status Enable Register
+ *     AddressOffset  : 0x80
+ *     AccessType     : RW
+ *     WritableBitMask: 0xf83f7ffb
+ *     ResetValue     : (uint64_t)0xffffffffffffffff
+ */
+SEDI_REG_DEFINE(DMA, INTSTATUS_ENABLEREG, 0x80, RW, (uint64_t)0xf83f7ffb,
+		(uint64_t)0xffffffffffffffff);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_BLOCK_TFR_DONE_IntStat:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_BLOCK_TFR_DONE_IntStat, 0, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_BLOCK_TFR_DONE_IntStat, DISABLE_BLOCK_TFR_DONE,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_BLOCK_TFR_DONE_IntStat, ENABLE_BLOCK_TFR_DONE,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_DMA_TFR_DONE_IntStat:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DMA_TFR_DONE_IntStat, 1, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DMA_TFR_DONE_IntStat, DISABLE_DMA_TFR_DONE, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DMA_TFR_DONE_IntStat, ENABLE_DMA_TFR_DONE, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2, 2, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2, 1, 1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SRC_TRANSCOMP_IntStat:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SRC_TRANSCOMP_IntStat, 3, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SRC_TRANSCOMP_IntStat, DISABLE_SRC_TRANSCOMP,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SRC_TRANSCOMP_IntStat, ENABLE_SRC_TRANSCOMP, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_DST_TRANSCOMP_IntStat:
+ *     BitOffset : 4
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DST_TRANSCOMP_IntStat, 4, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DST_TRANSCOMP_IntStat, DISABLE_DST_TRANSCOMP,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DST_TRANSCOMP_IntStat, ENABLE_DST_TRANSCOMP, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SRC_DEC_ERR_IntStat:
+ *     BitOffset : 5
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SRC_DEC_ERR_IntStat, 5, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SRC_DEC_ERR_IntStat, DISABLE_SRC_DEC_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SRC_DEC_ERR_IntStat, ENABLE_SRC_DEC_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_DST_DEC_ERR_IntStat:
+ *     BitOffset : 6
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DST_DEC_ERR_IntStat, 6, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DST_DEC_ERR_IntStat, DISABLE_DST_DEC_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DST_DEC_ERR_IntStat, ENABLE_DST_DEC_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SRC_SLV_ERR_IntStat:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SRC_SLV_ERR_IntStat, 7, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SRC_SLV_ERR_IntStat, DISABLE_SRC_SLV_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SRC_SLV_ERR_IntStat, ENABLE_SRC_SLV_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_DST_SLV_ERR_IntStat:
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DST_SLV_ERR_IntStat, 8, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DST_SLV_ERR_IntStat, DISABLE_DST_SLV_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_DST_SLV_ERR_IntStat, ENABLE_DST_SLV_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_LLI_RD_DEC_ERR_IntStat:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_RD_DEC_ERR_IntStat, 9, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_RD_DEC_ERR_IntStat, DISABLE_LLI_RD_DEC_ERR,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_RD_DEC_ERR_IntStat, ENABLE_LLI_RD_DEC_ERR,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_LLI_WR_DEC_ERR_IntStat:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_WR_DEC_ERR_IntStat, 10, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_WR_DEC_ERR_IntStat, DISABLE_LLI_WR_DEC_ERR,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_WR_DEC_ERR_IntStat, ENABLE_LLI_WR_DEC_ERR,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_LLI_RD_SLV_ERR_IntStat:
+ *     BitOffset : 11
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_RD_SLV_ERR_IntStat, 11, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_RD_SLV_ERR_IntStat, DISABLE_LLI_RD_SLV_ERR,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_RD_SLV_ERR_IntStat, ENABLE_LLI_RD_SLV_ERR,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_LLI_WR_SLV_ERR_IntStat:
+ *     BitOffset : 12
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_WR_SLV_ERR_IntStat, 12, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_WR_SLV_ERR_IntStat, DISABLE_LLI_WR_SLV_ERR,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_LLI_WR_SLV_ERR_IntStat, ENABLE_LLI_WR_SLV_ERR,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat:
+ *     BitOffset : 13
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat, 13, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,
+		 DISABLE_SHADOWREG_OR_LLI_INVALID_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,
+		 ENABLE_SHADOWREG_OR_LLI_INVALID_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat:
+ *     BitOffset : 14
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat, 14, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,
+		 DISABLE_SLVIF_MULTIBLKTYPE_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,
+		 ENABLE_SLVIF_MULTIBLKTYPE_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15:
+ *     BitOffset : 15
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15, 15, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15, 1, 1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_DEC_ERR_IntStat:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_DEC_ERR_IntStat, 16, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_DEC_ERR_IntStat, DISABLE_SLVIF_DEC_ERR,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_DEC_ERR_IntStat, ENABLE_SLVIF_DEC_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_WR2RO_ERR_IntStat:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WR2RO_ERR_IntStat, 17, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WR2RO_ERR_IntStat, DISABLE_SLVIF_WR2RO_ERR,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WR2RO_ERR_IntStat, ENABLE_SLVIF_WR2RO_ERR,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_RD2RWO_ERR_IntStat:
+ *     BitOffset : 18
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_RD2RWO_ERR_IntStat, 18, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_RD2RWO_ERR_IntStat,
+		 DISABLE_SLVIF_RD2RWO_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_RD2RWO_ERR_IntStat, ENABLE_SLVIF_RD2RWO_ERR,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_WRONCHEN_ERR_IntStat:
+ *     BitOffset : 19
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WRONCHEN_ERR_IntStat, 19, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WRONCHEN_ERR_IntStat,
+		 DISABLE_SLVIF_WRONCHEN_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WRONCHEN_ERR_IntStat,
+		 ENABLE_SLVIF_WRONCHEN_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat:
+ *     BitOffset : 20
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat, 20, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,
+		 DISABLE_SLVIF_SHADOWREG_WRON_VALID_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,
+		 ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_WRONHOLD_ERR_IntStat:
+ *     BitOffset : 21
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WRONHOLD_ERR_IntStat, 21, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WRONHOLD_ERR_IntStat,
+		 DISABLE_SLVIF_WRONHOLD_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WRONHOLD_ERR_IntStat,
+		 ENABLE_SLVIF_WRONHOLD_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24:
+ *     BitOffset : 22
+ *     BitWidth  : 3
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x7
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24, 22, 3, RO,
+		(uint64_t)0x7);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_WRPARITY_ERR_IntStat:
+ *     BitOffset : 25
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WRPARITY_ERR_IntStat, 25, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WRPARITY_ERR_IntStat,
+		 Disable_SLVIF_WRPARITY_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_SLVIF_WRPARITY_ERR_IntStat,
+		 Enable_SLVIF_WRPARITY_ERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26:
+ *     BitOffset : 26
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26, 26, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26, 1, 1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_CH_LOCK_CLEARED_IntStat:
+ *     BitOffset : 27
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_LOCK_CLEARED_IntStat, 27, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_LOCK_CLEARED_IntStat, DISABLE_CH_LOCK_CLEARED,
+		 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_LOCK_CLEARED_IntStat, ENABLE_CH_LOCK_CLEARED,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_CH_SRC_SUSPENDED_IntStat:
+ *     BitOffset : 28
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_SRC_SUSPENDED_IntStat, 28, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_SRC_SUSPENDED_IntStat,
+		 DISABLE_CH_SRC_SUSPENDED, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_SRC_SUSPENDED_IntStat, ENABLE_CH_SRC_SUSPENDED,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_CH_SUSPENDED_IntStat:
+ *     BitOffset : 29
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_SUSPENDED_IntStat, 29, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_SUSPENDED_IntStat, DISABLE_CH_SUSPENDED, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_SUSPENDED_IntStat, ENABLE_CH_SUSPENDED, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_CH_DISABLED_IntStat:
+ *     BitOffset : 30
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_DISABLED_IntStat, 30, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_DISABLED_IntStat, DISABLE_CH_DISABLED, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_DISABLED_IntStat, ENABLE_CH_DISABLED, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_CH_ABORTED_IntStat:
+ *     BitOffset : 31
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_ABORTED_IntStat, 31, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_ABORTED_IntStat, DISABLE_CH_ABORTED, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_CH_ABORTED_IntStat, ENABLE_CH_ABORTED, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_ECC_PROT_CHMem_CorrERR_IntStat:
+ *     BitOffset : 32
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_CHMem_CorrERR_IntStat, 32, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_CHMem_CorrERR_IntStat,
+		 DISABLE_ECC_CHMEM_CORRERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_CHMem_CorrERR_IntStat,
+		 ENABLE_ECC_CHMEM_CORRERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_ECC_PROT_CHMem_UnCorrERR_IntStat:
+ *     BitOffset : 33
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_CHMem_UnCorrERR_IntStat, 33, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,
+		 DISABLE_ECC_CHMEM_UNCORRERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,
+		 ENABLE_ECC_CHMEM_UNCORRERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_ECC_PROT_UIDMem_CorrERR_IntStat:
+ *     BitOffset : 34
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_UIDMem_CorrERR_IntStat, 34, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_UIDMem_CorrERR_IntStat,
+		 DISABLE_ECC_UIDMEM_CORRERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_UIDMem_CorrERR_IntStat,
+		 ENABLE_ECC_UIDMEM_CORRERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat:
+ *     BitOffset : 35
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat, 35, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,
+		 DISABLE_ECC_UIDMEM_UNCORRERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS_ENABLEREG, Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,
+		 ENABLE_ECC_UIDMEM_UNCORRERR, 0x1);
+
+/*
+ * Bit Field of Register INTSTATUS_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63:
+ *     BitOffset : 36
+ *     BitWidth  : 28
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0xfffffff
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63, 36, 28, RO,
+		(uint64_t)0xfffffff);
+
+/* ********* DMA INTSTATUS ***********
+ *
+ * Register of SEDI DMA
+ *   INTSTATUS: DW_axi_dmac Channel x Interrupt Status Register
+ *     AddressOffset  : 0x88
+ *     AccessType     : RO
+ *     WritableBitMask: 0x0
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, INTSTATUS, 0x88, RO, (uint64_t)0x0, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   BLOCK_TFR_DONE_IntStat:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, BLOCK_TFR_DONE_IntStat, 0, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, BLOCK_TFR_DONE_IntStat, BLOCK_TFR_COMPLETED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, BLOCK_TFR_DONE_IntStat, BLOCK_TFR_NOT_COMPLETE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   DMA_TFR_DONE_IntStat:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, DMA_TFR_DONE_IntStat, 1, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, DMA_TFR_DONE_IntStat, DMA_TFR_COMPLETED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, DMA_TFR_DONE_IntStat, DMA_TFR_NOT_COMPLETE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   RSVD_DMAC_CHx_INTSTATUSREG_2:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_2, 2, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_2, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_2, 1, 1);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SRC_TRANSCOMP_IntStat:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SRC_TRANSCOMP_IntStat, 3, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SRC_TRANSCOMP_IntStat, ACTIVE_SRC_TRANSCOMP, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SRC_TRANSCOMP_IntStat, INACTIVE_SRC_TRANSCOMP, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   DST_TRANSCOMP_IntStat:
+ *     BitOffset : 4
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, DST_TRANSCOMP_IntStat, 4, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, DST_TRANSCOMP_IntStat, ACTIVE_DST_TRANSCOMP, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, DST_TRANSCOMP_IntStat, INACTIVE_DST_TRANSCOMP, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SRC_DEC_ERR_IntStat:
+ *     BitOffset : 5
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SRC_DEC_ERR_IntStat, 5, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SRC_DEC_ERR_IntStat, ACTIVE_SRC_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SRC_DEC_ERR_IntStat, INACTIVE_SRC_DEC_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   DST_DEC_ERR_IntStat:
+ *     BitOffset : 6
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, DST_DEC_ERR_IntStat, 6, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, DST_DEC_ERR_IntStat, ACTIVE_DST_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, DST_DEC_ERR_IntStat, INACTIVE_DST_DEC_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SRC_SLV_ERR_IntStat:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SRC_SLV_ERR_IntStat, 7, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SRC_SLV_ERR_IntStat, ACTIVE_SRC_SLV_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SRC_SLV_ERR_IntStat, INACTIVE_SRC_SLV_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   DST_SLV_ERR_IntStat:
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, DST_SLV_ERR_IntStat, 8, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, DST_SLV_ERR_IntStat, ACTIVE_DST_SLV_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, DST_SLV_ERR_IntStat, INACTIVE_DST_SLV_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   LLI_RD_DEC_ERR_IntStat:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, LLI_RD_DEC_ERR_IntStat, 9, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, LLI_RD_DEC_ERR_IntStat, ACTIVE_LLI_RD_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, LLI_RD_DEC_ERR_IntStat, INACTIVE_LLI_RD_DEC_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   LLI_WR_DEC_ERR_IntStat:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, LLI_WR_DEC_ERR_IntStat, 10, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, LLI_WR_DEC_ERR_IntStat, ACTIVE_LLI_WR_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, LLI_WR_DEC_ERR_IntStat, INACTIVE_LLI_WR_DEC_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   LLI_RD_SLV_ERR_IntStat:
+ *     BitOffset : 11
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, LLI_RD_SLV_ERR_IntStat, 11, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, LLI_RD_SLV_ERR_IntStat, ACTIVE_LLI_RD_SLV_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, LLI_RD_SLV_ERR_IntStat, INACTIVE_LLI_RD_SLV_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   LLI_WR_SLV_ERR_IntStat:
+ *     BitOffset : 12
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, LLI_WR_SLV_ERR_IntStat, 12, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, LLI_WR_SLV_ERR_IntStat, ACTIVE_LLI_WR_SLV, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, LLI_WR_SLV_ERR_IntStat, INACTIVE_LLI_WR_SLV, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SHADOWREG_OR_LLI_INVALID_ERR_IntStat:
+ *     BitOffset : 13
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SHADOWREG_OR_LLI_INVALID_ERR_IntStat, 13, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SHADOWREG_OR_LLI_INVALID_ERR_IntStat,
+		 ACTIVE_SHADOWREG_OR_LLI_INVALID_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SHADOWREG_OR_LLI_INVALID_ERR_IntStat,
+		 INACTIVE_SHADOWREG_OR_LLI_INVALID_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SLVIF_MULTIBLKTYPE_ERR_IntStat:
+ *     BitOffset : 14
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SLVIF_MULTIBLKTYPE_ERR_IntStat, 14, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_MULTIBLKTYPE_ERR_IntStat, ACTIVE_SLVIF_MULTIBLKTYPE_ERR,
+		 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_MULTIBLKTYPE_ERR_IntStat, INACTIVE_SLVIF_MULTIBLKTYPE_ERR,
+		 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   RSVD_DMAC_CHx_INTSTATUSREG_15:
+ *     BitOffset : 15
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_15, 15, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_15, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_15, 1, 1);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SLVIF_DEC_ERR_IntStat:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SLVIF_DEC_ERR_IntStat, 16, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_DEC_ERR_IntStat, ACTIVE_SLVIF_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_DEC_ERR_IntStat, INACTIVE_SLVIF_DEC_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SLVIF_WR2RO_ERR_IntStat:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SLVIF_WR2RO_ERR_IntStat, 17, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_WR2RO_ERR_IntStat, ACTIVE_SLVIF_WR2RO_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_WR2RO_ERR_IntStat, INACTIVE_SLVIF_WR2RO_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SLVIF_RD2RWO_ERR_IntStat:
+ *     BitOffset : 18
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SLVIF_RD2RWO_ERR_IntStat, 18, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_RD2RWO_ERR_IntStat, ACTIVE_SLVIF_RD2RWO_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_RD2RWO_ERR_IntStat, INACTIVE_SLVIF_RD2RWO_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SLVIF_WRONCHEN_ERR_IntStat:
+ *     BitOffset : 19
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SLVIF_WRONCHEN_ERR_IntStat, 19, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_WRONCHEN_ERR_IntStat, ACTIVE_SLVIF_WRONCHEN_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_WRONCHEN_ERR_IntStat, INACTIVE_SLVIF_WRONCHEN_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat:
+ *     BitOffset : 20
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat, 20, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,
+		 ACTIVE_SLVIF_SHADOWREG_WRON_VALID_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,
+		 INACTIVE_SLVIF_SHADOWREG_WRON_VALID_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SLVIF_WRONHOLD_ERR_IntStat:
+ *     BitOffset : 21
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SLVIF_WRONHOLD_ERR_IntStat, 21, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_WRONHOLD_ERR_IntStat, ACTIVE_SLVIF_WRONHOLD_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_WRONHOLD_ERR_IntStat, INACTIVE_SLVIF_WRONHOLD_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   RSVD_DMAC_CHx_INTSTATUSREG_22to24:
+ *     BitOffset : 22
+ *     BitWidth  : 3
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_22to24, 22, 3, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   SLVIF_WRPARITY_ERR_IntStat:
+ *     BitOffset : 25
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, SLVIF_WRPARITY_ERR_IntStat, 25, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_WRPARITY_ERR_IntStat, ACTIVE_SLVIF_WRPARITY_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, SLVIF_WRPARITY_ERR_IntStat, INACTIVE_SLVIF_WRPARITY_ERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   RSVD_DMAC_CHx_INTSTATUSREG_26:
+ *     BitOffset : 26
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_26, 26, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_26, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_26, 1, 1);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   CH_LOCK_CLEARED_IntStat:
+ *     BitOffset : 27
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, CH_LOCK_CLEARED_IntStat, 27, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_LOCK_CLEARED_IntStat, ACTIVE_CH_LOCK_CLEARED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_LOCK_CLEARED_IntStat, INACTIVE_CH_LOCK_CLEARED, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   CH_SRC_SUSPENDED_IntStat:
+ *     BitOffset : 28
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, CH_SRC_SUSPENDED_IntStat, 28, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_SRC_SUSPENDED_IntStat, ACTIVE_CH_SRC_SUSPENDED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_SRC_SUSPENDED_IntStat, INACTIVE_CH_SRC_SUSPENDED, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   CH_SUSPENDED_IntStat:
+ *     BitOffset : 29
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, CH_SUSPENDED_IntStat, 29, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_SUSPENDED_IntStat, ACTIVE_CH_SUSPENDED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_SUSPENDED_IntStat, INACTIVE_CH_SUSPENDED, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   CH_DISABLED_IntStat:
+ *     BitOffset : 30
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, CH_DISABLED_IntStat, 30, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_DISABLED_IntStat, ACTIVE_CH_DISABLED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_DISABLED_IntStat, INACTIVE_CH_DISABLED, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   CH_ABORTED_IntStat:
+ *     BitOffset : 31
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, CH_ABORTED_IntStat, 31, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_ABORTED_IntStat, ACTIVE_CH_ABORTED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, CH_ABORTED_IntStat, INACTIVE_CH_ABORTED, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   ECC_PROT_CHMem_CorrERR_IntStat:
+ *     BitOffset : 32
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, ECC_PROT_CHMem_CorrERR_IntStat, 32, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, ECC_PROT_CHMem_CorrERR_IntStat, ACTIVE_EccPROT_CHMem_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, ECC_PROT_CHMem_CorrERR_IntStat, INACTIVE_EccPROT_CHMem_CorrERR,
+		 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   ECC_PROT_CHMem_UnCorrERR_IntStat:
+ *     BitOffset : 33
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, ECC_PROT_CHMem_UnCorrERR_IntStat, 33, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, ECC_PROT_CHMem_UnCorrERR_IntStat, ACTIVE_EccPROT_CHMem_UnCorrERR,
+		 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, ECC_PROT_CHMem_UnCorrERR_IntStat, INACTIVE_EccPROT_CHMem_UnCorrERR,
+		 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   ECC_PROT_UIDMem_CorrERR_IntStat:
+ *     BitOffset : 34
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, ECC_PROT_UIDMem_CorrERR_IntStat, 34, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, ECC_PROT_UIDMem_CorrERR_IntStat, ACTIVE_EccPROT_UIDMem_CorrERR,
+		 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, ECC_PROT_UIDMem_CorrERR_IntStat, INACTIVE_EccPROT_UIDMem_CorrERR,
+		 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   ECC_PROT_UIDMem_UnCorrERR_IntStat:
+ *     BitOffset : 35
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, ECC_PROT_UIDMem_UnCorrERR_IntStat, 35, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, ECC_PROT_UIDMem_UnCorrERR_IntStat, ACTIVE_EccPROT_UIDMem_UnCorrERR,
+		 0x1);
+SEDI_RBFV_DEFINE(DMA, INTSTATUS, ECC_PROT_UIDMem_UnCorrERR_IntStat,
+		 INACTIVE_EccPROT_UIDMem_UnCorrERR, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUS
+ *   RSVD_DMAC_CHx_INTSTATUSREG_36to63:
+ *     BitOffset : 36
+ *     BitWidth  : 28
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTSTATUS, RSVD_DMAC_CHx_INTSTATUSREG_36to63, 36, 28, RO, (uint64_t)0x0);
+
+/* ********* DMA INTSIGNAL_ENABLEREG ***********
+ *
+ * Register of SEDI DMA
+ *   INTSIGNAL_ENABLEREG: DW_axi_dmac Channel x Interrupt Signal Enable Register
+ *     AddressOffset  : 0x90
+ *     AccessType     : RW
+ *     WritableBitMask: 0xf83f7ffb
+ *     ResetValue     : (uint64_t)0xffffffffffffffff
+ */
+SEDI_REG_DEFINE(DMA, INTSIGNAL_ENABLEREG, 0x90, RW, (uint64_t)0xf83f7ffb,
+		(uint64_t)0xffffffffffffffff);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_BLOCK_TFR_DONE_IntSignal:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_BLOCK_TFR_DONE_IntSignal, 0, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_BLOCK_TFR_DONE_IntSignal,
+		 DISABLE_BLOCK_TFR_DONE_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_BLOCK_TFR_DONE_IntSignal,
+		 ENABLE_BLOCK_TFR_DONE_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_DMA_TFR_DONE_IntSignal:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DMA_TFR_DONE_IntSignal, 1, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DMA_TFR_DONE_IntSignal,
+		 DISABLE_DMA_TFR_DONE_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DMA_TFR_DONE_IntSignal,
+		 ENABLE_DMA_TFR_DONE_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2, 2, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2, 1, 1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SRC_TRANSCOMP_IntSignal:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_TRANSCOMP_IntSignal, 3, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_TRANSCOMP_IntSignal,
+		 DISABLE_SRC_TRANSCOMP_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_TRANSCOMP_IntSignal,
+		 ENABLE_SRC_TRANSCOMP_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_DST_TRANSCOMP_IntSignal:
+ *     BitOffset : 4
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DST_TRANSCOMP_IntSignal, 4, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DST_TRANSCOMP_IntSignal,
+		 DISABLE_DST_TRANSCOMP_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DST_TRANSCOMP_IntSignal,
+		 ENABLE_DST_TRANSCOMP_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SRC_DEC_ERR_IntSignal:
+ *     BitOffset : 5
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_DEC_ERR_IntSignal, 5, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_DEC_ERR_IntSignal,
+		 DISABLE_SRC_DEC_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_DEC_ERR_IntSignal,
+		 ENABLE_SRC_DEC_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_DST_DEC_ERR_IntSignal:
+ *     BitOffset : 6
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DST_DEC_ERR_IntSignal, 6, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DST_DEC_ERR_IntSignal,
+		 DISABLE_DST_DEC_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DST_DEC_ERR_IntSignal,
+		 ENABLE_DST_DEC_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SRC_SLV_ERR_IntSignal:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_SLV_ERR_IntSignal, 7, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_SLV_ERR_IntSignal,
+		 DISABLE_SRC_SLV_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SRC_SLV_ERR_IntSignal,
+		 ENABLE_SRC_SLV_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_DST_SLV_ERR_IntSignal:
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DST_SLV_ERR_IntSignal, 8, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DST_SLV_ERR_IntSignal,
+		 DISABLE_DST_SLV_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_DST_SLV_ERR_IntSignal,
+		 ENABLE_DST_SLV_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_LLI_RD_DEC_ERR_IntSignal:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_RD_DEC_ERR_IntSignal, 9, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_RD_DEC_ERR_IntSignal,
+		 DISABLE_LLI_RD_DEC_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_RD_DEC_ERR_IntSignal,
+		 ENABLE_LLI_RD_DEC_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_LLI_WR_DEC_ERR_IntSignal:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_WR_DEC_ERR_IntSignal, 10, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_WR_DEC_ERR_IntSignal,
+		 DISABLE_LLI_WR_DEC_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_WR_DEC_ERR_IntSignal,
+		 ENABLE_LLI_WR_DEC_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_LLI_RD_SLV_ERR_IntSignal:
+ *     BitOffset : 11
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_RD_SLV_ERR_IntSignal, 11, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_RD_SLV_ERR_IntSignal,
+		 DISABLE_LLI_RD_SLV_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_RD_SLV_ERR_IntSignal,
+		 ENABLE_LLI_RD_SLV_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_LLI_WR_SLV_ERR_IntSignal:
+ *     BitOffset : 12
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_WR_SLV_ERR_IntSignal, 12, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_WR_SLV_ERR_IntSignal,
+		 DISABLE_LLI_WR_SLV_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_LLI_WR_SLV_ERR_IntSignal,
+		 ENABLE_LLI_WR_SLV_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal:
+ *     BitOffset : 13
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal, 13, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,
+		 DISABLE_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,
+		 ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal:
+ *     BitOffset : 14
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal, 14, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,
+		 DISABLE_SLVIF_MULTIBLKTYPE_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,
+		 ENABLE_SLVIF_MULTIBLKTYPE_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15:
+ *     BitOffset : 15
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15, 15, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15, 1, 1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_DEC_ERR_IntSignal:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_DEC_ERR_IntSignal, 16, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_DEC_ERR_IntSignal,
+		 DISABLE_SLVIF_DEC_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_DEC_ERR_IntSignal,
+		 ENABLE_SLVIF_DEC_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_WR2RO_ERR_IntSignal:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WR2RO_ERR_IntSignal, 17, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WR2RO_ERR_IntSignal,
+		 DISABLE_SLVIF_WR2RO_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WR2RO_ERR_IntSignal,
+		 ENABLE_SLVIF_WR2RO_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_RD2RWO_ERR_IntSignal:
+ *     BitOffset : 18
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_RD2RWO_ERR_IntSignal, 18, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_RD2RWO_ERR_IntSignal,
+		 DISABLE_SLVIF_RD2RWO_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_RD2RWO_ERR_IntSignal,
+		 ENABLE_SLVIF_RD2RWO_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_WRONCHEN_ERR_IntSignal:
+ *     BitOffset : 19
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WRONCHEN_ERR_IntSignal, 19, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WRONCHEN_ERR_IntSignal,
+		 DISABLE_SLVIF_WRONCHEN_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WRONCHEN_ERR_IntSignal,
+		 ENABLE_SLVIF_WRONCHEN_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal:
+ *     BitOffset : 20
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal, 20, 1,
+		RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,
+		 DISABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,
+		 ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_WRONHOLD_ERR_IntSignal:
+ *     BitOffset : 21
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WRONHOLD_ERR_IntSignal, 21, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WRONHOLD_ERR_IntSignal,
+		 DISABLE_SLVIF_WRONHOLD_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WRONHOLD_ERR_IntSignal,
+		 ENABLE_SLVIF_WRONHOLD_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24:
+ *     BitOffset : 22
+ *     BitWidth  : 3
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x7
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24, 22, 3, RO,
+		(uint64_t)0x7);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_WRPARITY_ERR_IntSignal:
+ *     BitOffset : 25
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WRPARITY_ERR_IntSignal, 25, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WRPARITY_ERR_IntSignal,
+		 Disable_SLVIF_WRPARITY_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_SLVIF_WRPARITY_ERR_IntSignal,
+		 Enable_SLVIF_WRPARITY_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26:
+ *     BitOffset : 26
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26, 26, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26, 1, 1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_CH_LOCK_CLEARED_IntSignal:
+ *     BitOffset : 27
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_LOCK_CLEARED_IntSignal, 27, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_LOCK_CLEARED_IntSignal,
+		 DISABLE_CH_LOCK_CLEARED_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_LOCK_CLEARED_IntSignal,
+		 ENABLE_CH_LOCK_CLEARED_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_CH_SRC_SUSPENDED_IntSignal:
+ *     BitOffset : 28
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_SRC_SUSPENDED_IntSignal, 28, 1, RW,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_SRC_SUSPENDED_IntSignal,
+		 DISABLE_CH_SRC_SUSPENDED_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_SRC_SUSPENDED_IntSignal,
+		 ENABLE_CH_SRC_SUSPENDED_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_CH_SUSPENDED_IntSignal:
+ *     BitOffset : 29
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_SUSPENDED_IntSignal, 29, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_SUSPENDED_IntSignal,
+		 DISABLE_CH_SUSPENDED_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_SUSPENDED_IntSignal,
+		 ENABLE_CH_SUSPENDED_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_CH_DISABLED_IntSignal:
+ *     BitOffset : 30
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_DISABLED_IntSignal, 30, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_DISABLED_IntSignal,
+		 DISABLE_CH_DISABLED_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_DISABLED_IntSignal,
+		 ENABLE_CH_DISABLED_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_CH_ABORTED_IntSignal:
+ *     BitOffset : 31
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_ABORTED_IntSignal, 31, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_ABORTED_IntSignal,
+		 DISABLE_CH_ABORTED_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_CH_ABORTED_IntSignal, ENABLE_CH_ABORTED_IntSignal,
+		 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_ECC_PROT_CHMem_CorrERR_IntSignal:
+ *     BitOffset : 32
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_CHMem_CorrERR_IntSignal, 32, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_CHMem_CorrERR_IntSignal,
+		 DISABLE_ECC_CHMEM_CORRERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_CHMem_CorrERR_IntSignal,
+		 ENABLE_ECC_CHMEM_CORRERR, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal:
+ *     BitOffset : 33
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal, 33, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,
+		 DISABLE_ECC_CHMEM_UNCORRERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,
+		 ENABLE_ECC_CHMEM_UNCORRERR, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_ECC_PROT_UIDMem_CorrERR_IntSignal:
+ *     BitOffset : 34
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_UIDMem_CorrERR_IntSignal, 34, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,
+		 DISABLE_ECC_UIDMEM_CORRERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,
+		 ENABLE_ECC_UIDMEM_CORRERR, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal:
+ *     BitOffset : 35
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal, 35, 1, RO,
+		(uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,
+		 DISABLE_ECC_UIDMEM_UNCORRERR, 0x0);
+SEDI_RBFV_DEFINE(DMA, INTSIGNAL_ENABLEREG, Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,
+		 ENABLE_ECC_UIDMEM_UNCORRERR, 0x1);
+
+/*
+ * Bit Field of Register INTSIGNAL_ENABLEREG
+ *   RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63:
+ *     BitOffset : 36
+ *     BitWidth  : 28
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0xfffffff
+ */
+SEDI_RBF_DEFINE(DMA, INTSIGNAL_ENABLEREG, RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63, 36, 28, RO,
+		(uint64_t)0xfffffff);
+
+/* ********* DMA INTCLEARREG ***********
+ *
+ * Register of SEDI DMA
+ *   INTCLEARREG: DW_axi_dmac Channel x Interrupt Status Clear Register
+ *     AddressOffset  : 0x98
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffffffffffff
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMA, INTCLEARREG, 0x98, RW, (uint64_t)0xffffffffffffffff, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_BLOCK_TFR_DONE_IntStat:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_BLOCK_TFR_DONE_IntStat, 0, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_BLOCK_TFR_DONE_IntStat, CLEAR_BLOCK_TFR_DONE, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_BLOCK_TFR_DONE_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_DMA_TFR_DONE_IntStat:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_DMA_TFR_DONE_IntStat, 1, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_DMA_TFR_DONE_IntStat, CLEAR_DMA_TFR_DONE, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_DMA_TFR_DONE_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   RSVD_DMAC_CHx_INTCLEARREG_2:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_2, 2, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_2, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_2, 1, 1);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SRC_TRANSCOMP_IntStat:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SRC_TRANSCOMP_IntStat, 3, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SRC_TRANSCOMP_IntStat, CLEAR_SRC_TRANSCOMP, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SRC_TRANSCOMP_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_DST_TRANSCOMP_IntStat:
+ *     BitOffset : 4
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_DST_TRANSCOMP_IntStat, 4, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_DST_TRANSCOMP_IntStat, CLEAR_DST_TRANSCOMP, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_DST_TRANSCOMP_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SRC_DEC_ERR_IntStat:
+ *     BitOffset : 5
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SRC_DEC_ERR_IntStat, 5, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SRC_DEC_ERR_IntStat, CLEAR_SRC_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SRC_DEC_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_DST_DEC_ERR_IntStat:
+ *     BitOffset : 6
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_DST_DEC_ERR_IntStat, 6, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_DST_DEC_ERR_IntStat, CLEAR_DST_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_DST_DEC_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SRC_SLV_ERR_IntStat:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SRC_SLV_ERR_IntStat, 7, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SRC_SLV_ERR_IntStat, CLEAR_SRC_SLV_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SRC_SLV_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_DST_SLV_ERR_IntStat:
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_DST_SLV_ERR_IntStat, 8, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_DST_SLV_ERR_IntStat, CLEAR_DST_SLV_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_DST_SLV_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_LLI_RD_DEC_ERR_IntStat:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_LLI_RD_DEC_ERR_IntStat, 9, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_LLI_RD_DEC_ERR_IntStat, CLEAR_LLI_RD_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_LLI_RD_DEC_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_LLI_WR_DEC_ERR_IntStat:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_LLI_WR_DEC_ERR_IntStat, 10, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_LLI_WR_DEC_ERR_IntStat, CLEAR_LLI_WR_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_LLI_WR_DEC_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_LLI_RD_SLV_ERR_IntStat:
+ *     BitOffset : 11
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_LLI_RD_SLV_ERR_IntStat, 11, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_LLI_RD_SLV_ERR_IntStat, CLEAR_LLI_RD_SLV_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_LLI_RD_SLV_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_LLI_WR_SLV_ERR_IntStat:
+ *     BitOffset : 12
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_LLI_WR_SLV_ERR_IntStat, 12, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_LLI_WR_SLV_ERR_IntStat, CLEAR_LLI_WR_SLV_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_LLI_WR_SLV_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat:
+ *     BitOffset : 13
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat, 13, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,
+		 CLEAR_SHADOWREG_OR_LLI_INVALID_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat:
+ *     BitOffset : 14
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat, 14, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat,
+		 CLEAR_SLVIF_MULTIBLKTYPE_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   RSVD_DMAC_CHx_INTCLEARREG_15:
+ *     BitOffset : 15
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_15, 15, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_15, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_15, 1, 1);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SLVIF_DEC_ERR_IntStat:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_DEC_ERR_IntStat, 16, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_DEC_ERR_IntStat, CLEAR_SLVIF_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_DEC_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SLVIF_WR2RO_ERR_IntStat:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WR2RO_ERR_IntStat, 17, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WR2RO_ERR_IntStat, CLEAR_SLVIF_WR2RO_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WR2RO_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SLVIF_RD2RWO_ERR_IntStat:
+ *     BitOffset : 18
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_RD2RWO_ERR_IntStat, 18, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_RD2RWO_ERR_IntStat, CLEAR_SLVIF_RD2RWO_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_RD2RWO_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SLVIF_WRONCHEN_ERR_IntStat:
+ *     BitOffset : 19
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WRONCHEN_ERR_IntStat, 19, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WRONCHEN_ERR_IntStat, CLEAR_SLVIF_WRONCHEN_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WRONCHEN_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat:
+ *     BitOffset : 20
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat, 20, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,
+		 CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SLVIF_WRONHOLD_ERR_IntStat:
+ *     BitOffset : 21
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WRONHOLD_ERR_IntStat, 21, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WRONHOLD_ERR_IntStat, CLEAR_SLVIF_WRONHOLD_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WRONHOLD_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   RSVD_DMAC_CHx_INTCLEARREG_22to24:
+ *     BitOffset : 22
+ *     BitWidth  : 3
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_22to24, 22, 3, RW, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_SLVIF_WRPARITY_ERR_IntStat:
+ *     BitOffset : 25
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WRPARITY_ERR_IntStat, 25, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WRPARITY_ERR_IntStat, CLEAR_SLVIF_WRPARITY_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_SLVIF_WRPARITY_ERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   RSVD_DMAC_CHx_INTCLEARREG_26:
+ *     BitOffset : 26
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_26, 26, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_26, 0, 0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_26, 1, 1);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_CH_LOCK_CLEARED_IntStat:
+ *     BitOffset : 27
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_CH_LOCK_CLEARED_IntStat, 27, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_LOCK_CLEARED_IntStat, CLEAR_CH_LOCK_CLEARED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_LOCK_CLEARED_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_CH_SRC_SUSPENDED_IntStat:
+ *     BitOffset : 28
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_CH_SRC_SUSPENDED_IntStat, 28, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_SRC_SUSPENDED_IntStat, CLEAR_CH_SRC_SUSPENDED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_SRC_SUSPENDED_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_CH_SUSPENDED_IntStat:
+ *     BitOffset : 29
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_CH_SUSPENDED_IntStat, 29, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_SUSPENDED_IntStat, CLEAR_CH_SUSPENDED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_SUSPENDED_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_CH_DISABLED_IntStat:
+ *     BitOffset : 30
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_CH_DISABLED_IntStat, 30, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_DISABLED_IntStat, CLEAR_CH_DISABLED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_DISABLED_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_CH_ABORTED_IntStat:
+ *     BitOffset : 31
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_CH_ABORTED_IntStat, 31, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_ABORTED_IntStat, CLEAR_CH_ABORTED, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_CH_ABORTED_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_ECC_PROT_CHMem_CorrERR_IntStat:
+ *     BitOffset : 32
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_CHMem_CorrERR_IntStat, 32, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_CHMem_CorrERR_IntStat,
+		 CLEAR_ECC_CHMEM_CORRERR_IntStat, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_CHMem_CorrERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_ECC_PROT_CHMem_UnCorrERR_IntStat:
+ *     BitOffset : 33
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_CHMem_UnCorrERR_IntStat, 33, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_CHMem_UnCorrERR_IntStat,
+		 CLEAR_ECC_CHMEM_CORRERR_IntStat, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_CHMem_UnCorrERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_ECC_PROT_UIDMem_CorrERR_IntStat:
+ *     BitOffset : 34
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_UIDMem_CorrERR_IntStat, 34, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_UIDMem_CorrERR_IntStat,
+		 CLEAR_ECC_UIDMEM_CORRERR_IntStat, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_UIDMem_CorrERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat:
+ *     BitOffset : 35
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat, 35, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat,
+		 Clear_ECC_UIDMEM_CORRERR_IntStat, 0x1);
+SEDI_RBFV_DEFINE(DMA, INTCLEARREG, Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat, NO_ACTION, 0x0);
+
+/*
+ * Bit Field of Register INTCLEARREG
+ *   RSVD_DMAC_CHx_INTCLEARREG_36to63:
+ *     BitOffset : 36
+ *     BitWidth  : 28
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMA, INTCLEARREG, RSVD_DMAC_CHx_INTCLEARREG_36to63, 36, 28, RW, (uint64_t)0x0);
+
+/*
+ * Registers' Address Map Structure
+ */
+
+typedef struct {
+	/* DW_axi_dmac Channel x Source Address Register */
+	__IO_RW uint64_t sar;
+
+	/* DW_axi_dmac Channel x Destination Address Register */
+	__IO_RW uint64_t dar;
+
+	/* DW_axi_dmac Channel x Block Transfer Size Register */
+	__IO_RW uint64_t block_ts;
+
+	/* DW_axi_dmac Channel x Control Register */
+	__IO_RW uint64_t ctl;
+
+	/* DW_axi_dmac Channel x Configuration Register 2 */
+	__IO_RW uint64_t cfg2;
+
+	/* DW_axi_dmac Channel x Linked List Pointer Register */
+	__IO_RW uint64_t llp;
+
+	/* DW_axi_dmac Channel x Status Register */
+	__IO_R uint64_t statusreg;
+
+	/* DW_axi_dmac Channel x Software Handshake Source Register */
+	__IO_RW uint64_t swhssrcreg;
+
+	/* DW_axi_dmac Channel x Software Handshake Destination Register */
+	__IO_RW uint64_t swhsdstreg;
+
+	/* DW_axi_dmac Channel x Block Transfer Resume Request Register */
+	__IO_RW uint64_t blk_tfr_resumereqreg;
+
+	/* Reserved */
+	__IO_RW uint64_t reserved0[1];
+
+	/* DW_axi_dmac Channel x AXI QoS Register */
+	__IO_RW uint64_t axi_qosreg;
+
+	/* DW_axi_dmac Channel x Source Status Register */
+	__IO_R uint64_t sstat;
+
+	/* DW_axi_dmac Channel x Destination Status Register */
+	__IO_R uint64_t dstat;
+
+	/* DW_axi_dmac Channel x Source Status Fetch Register */
+	__IO_RW uint64_t sstatar;
+
+	/* DW_axi_dmac Channel x Destination Status Fetch Register */
+	__IO_RW uint64_t dstatar;
+
+	/* DW_axi_dmac Channel x Interrupt Status Enable Register */
+	__IO_RW uint64_t intstatus_enablereg;
+
+	/* DW_axi_dmac Channel x Interrupt Status Register */
+	__IO_R uint64_t intstatus;
+
+	/* DW_axi_dmac Channel x Interrupt Signal Enable Register */
+	__IO_RW uint64_t intsignal_enablereg;
+
+	/* DW_axi_dmac Channel x Interrupt Status Clear Register */
+	__IO_RW uint64_t intclearreg;
+
+} sedi_dma_regs_t;
+#define SEDI_DMA_REGS_T sedi_dma_regs_t
+
+#endif /* _SEDI_DMA_REGS_H_ */
diff --git a/bsp_sedi/soc/common/include/sedi_dmac_regs.h b/bsp_sedi/soc/common/include/sedi_dmac_regs.h
new file mode 100644
index 0000000..cd873e3
--- /dev/null
+++ b/bsp_sedi/soc/common/include/sedi_dmac_regs.h
@@ -0,0 +1,2260 @@
+/*
+ * Copyright (c) 2023-2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * This file has been automatically generated
+ * Tool Version: 1.0.0
+ * Generation Date: 2023-08-01
+ */
+
+#ifndef _SEDI_DMAC_REGS_H_
+#define _SEDI_DMAC_REGS_H_
+
+#include <sedi_reg_defs.h>
+
+/* ********* DMAC IDREG ***********
+ *
+ * Register of SEDI DMAC
+ *   IDREG: DW_axi_dmac Component ID Register
+ *     AddressOffset  : 0x0
+ *     AccessType     : RO
+ *     WritableBitMask: 0x0
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMAC, IDREG, 0x0, RO, (uint64_t)0x0, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register IDREG
+ *   DMAC_ID:
+ *     BitOffset : 0
+ *     BitWidth  : 32
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, IDREG, DMAC_ID, 0, 32, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register IDREG
+ *   RSVD_DMAC_IDREG:
+ *     BitOffset : 32
+ *     BitWidth  : 32
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, IDREG, RSVD_DMAC_IDREG, 32, 32, RO, (uint64_t)0x0);
+
+/* ********* DMAC COMPVERREG ***********
+ *
+ * Register of SEDI DMAC
+ *   COMPVERREG: DW_axi_dmac Component Version Register
+ *     AddressOffset  : 0x8
+ *     AccessType     : RO
+ *     WritableBitMask: 0x0
+ *     ResetValue     : (uint64_t)0x3230302a
+ */
+SEDI_REG_DEFINE(DMAC, COMPVERREG, 0x8, RO, (uint64_t)0x0, (uint64_t)0x3230302a);
+
+/*
+ * Bit Field of Register COMPVERREG
+ *   DMAC_COMPVER:
+ *     BitOffset : 0
+ *     BitWidth  : 32
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x3230302a
+ */
+SEDI_RBF_DEFINE(DMAC, COMPVERREG, DMAC_COMPVER, 0, 32, RO, (uint64_t)0x3230302a);
+
+/*
+ * Bit Field of Register COMPVERREG
+ *   RSVD_DMAC_COMPVERREG:
+ *     BitOffset : 32
+ *     BitWidth  : 32
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMPVERREG, RSVD_DMAC_COMPVERREG, 32, 32, RO, (uint64_t)0x0);
+
+/* ********* DMAC CFGREG ***********
+ *
+ * Register of SEDI DMAC
+ *   CFGREG: DW_axi_dmac Global Configuration Register
+ *     AddressOffset  : 0x10
+ *     AccessType     : RW
+ *     WritableBitMask: 0x3
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMAC, CFGREG, 0x10, RW, (uint64_t)0x3, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CFGREG
+ *   DMAC_EN:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CFGREG, DMAC_EN, 0, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CFGREG, DMAC_EN, DISABLED, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CFGREG, DMAC_EN, ENABLED, 0x1);
+
+/*
+ * Bit Field of Register CFGREG
+ *   INT_EN:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CFGREG, INT_EN, 1, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CFGREG, INT_EN, DISABLED, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CFGREG, INT_EN, ENABLED, 0x1);
+
+/*
+ * Bit Field of Register CFGREG
+ *   RSVD_DMAC_CFGREG:
+ *     BitOffset : 2
+ *     BitWidth  : 62
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CFGREG, RSVD_DMAC_CFGREG, 2, 62, RO, (uint64_t)0x0);
+
+/* ********* DMAC CHENREG ***********
+ *
+ * Register of SEDI DMAC
+ *   CHENREG: DW_axi_dmac Channel Enable Register
+ *     AddressOffset  : 0x18
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffffffff
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMAC, CHENREG, 0x18, RW, (uint64_t)0xffffffffffff, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH1_EN:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH1_EN, 0, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_EN, DISABLE_CH1, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_EN, ENABLE_CH1, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH2_EN:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH2_EN, 1, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_EN, DISABLE_CH2, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_EN, ENABLE_CH2, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH3_EN:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH3_EN, 2, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_EN, DISABLE_CH3, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_EN, ENABLE_CH3, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH4_EN:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH4_EN, 3, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_EN, DISABLE_CH4, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_EN, ENABLE_CH4, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH5_EN:
+ *     BitOffset : 4
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH5_EN, 4, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_EN, DISABLE_CH5, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_EN, ENABLE_CH5, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH6_EN:
+ *     BitOffset : 5
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH6_EN, 5, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_EN, DISABLE_CH6, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_EN, ENABLE_CH6, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH7_EN:
+ *     BitOffset : 6
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH7_EN, 6, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_EN, DISABLE_CH7, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_EN, ENABLE_CH7, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH8_EN:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH8_EN, 7, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_EN, DISABLE_CH8, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_EN, ENABLE_CH8, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH1_EN_WE:
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH1_EN_WE, 8, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_EN_WE, DISABLE_WR_CH1_EN, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_EN_WE, ENABLE_WR_CH1_EN, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH2_EN_WE:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH2_EN_WE, 9, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_EN_WE, DISABLE_WR_CH2_EN, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_EN_WE, ENABLE_WR_CH2_EN, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH3_EN_WE:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH3_EN_WE, 10, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_EN_WE, DISABLE_WR_CH3_EN, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_EN_WE, ENABLE_WR_CH3_EN, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH4_EN_WE:
+ *     BitOffset : 11
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH4_EN_WE, 11, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_EN_WE, DISABLE_WR_CH4_EN, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_EN_WE, ENABLE_WR_CH4_EN, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH5_EN_WE:
+ *     BitOffset : 12
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH5_EN_WE, 12, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_EN_WE, DISABLE_WR_CH5_EN, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_EN_WE, ENABLE_WR_CH5_EN, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH6_EN_WE:
+ *     BitOffset : 13
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH6_EN_WE, 13, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_EN_WE, DISABLE_WR_CH6_EN, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_EN_WE, ENABLE_WR_CH6_EN, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH7_EN_WE:
+ *     BitOffset : 14
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH7_EN_WE, 14, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_EN_WE, DISABLE_WR_CH7_EN, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_EN_WE, ENABLE_WR_CH7_EN, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH8_EN_WE:
+ *     BitOffset : 15
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH8_EN_WE, 15, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_EN_WE, DISABLE_WR_CH8_EN, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_EN_WE, ENABLE_WR_CH8_EN, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH1_SUSP:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH1_SUSP, 16, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_SUSP, DISABLE_CH1_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_SUSP, ENABLE_CH1_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH2_SUSP:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH2_SUSP, 17, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_SUSP, DISABLE_CH2_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_SUSP, ENABLE_CH2_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH3_SUSP:
+ *     BitOffset : 18
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH3_SUSP, 18, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_SUSP, DISABLE_CH3_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_SUSP, ENABLE_CH3_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH4_SUSP:
+ *     BitOffset : 19
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH4_SUSP, 19, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_SUSP, DISABLE_CH4_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_SUSP, ENABLE_CH4_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH5_SUSP:
+ *     BitOffset : 20
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH5_SUSP, 20, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_SUSP, DISABLE_CH5_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_SUSP, ENABLE_CH5_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH6_SUSP:
+ *     BitOffset : 21
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH6_SUSP, 21, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_SUSP, DISABLE_CH6_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_SUSP, ENABLE_CH6_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH7_SUSP:
+ *     BitOffset : 22
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH7_SUSP, 22, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_SUSP, DISABLE_CH7_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_SUSP, ENABLE_CH7_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH8_SUSP:
+ *     BitOffset : 23
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH8_SUSP, 23, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_SUSP, DISABLE_CH8_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_SUSP, ENABLE_CH8_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH1_SUSP_WE:
+ *     BitOffset : 24
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH1_SUSP_WE, 24, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_SUSP_WE, DISABLE_WR_CH1_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_SUSP_WE, ENABLE_WR_CH1_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH2_SUSP_WE:
+ *     BitOffset : 25
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH2_SUSP_WE, 25, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_SUSP_WE, DISABLE_WR_CH2_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_SUSP_WE, ENABLE_WR_CH2_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH3_SUSP_WE:
+ *     BitOffset : 26
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH3_SUSP_WE, 26, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_SUSP_WE, DISABLE_WR_CH3_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_SUSP_WE, ENABLE_WR_CH3_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH4_SUSP_WE:
+ *     BitOffset : 27
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH4_SUSP_WE, 27, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_SUSP_WE, DISABLE_WR_CH4_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_SUSP_WE, ENABLE_WR_CH4_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH5_SUSP_WE:
+ *     BitOffset : 28
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH5_SUSP_WE, 28, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_SUSP_WE, DISABLE_WR_CH5_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_SUSP_WE, ENABLE_WR_CH5_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH6_SUSP_WE:
+ *     BitOffset : 29
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH6_SUSP_WE, 29, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_SUSP_WE, DISABLE_WR_CH6_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_SUSP_WE, ENABLE_WR_CH6_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH7_SUSP_WE:
+ *     BitOffset : 30
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH7_SUSP_WE, 30, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_SUSP_WE, DISABLE_WR_CH7_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_SUSP_WE, ENABLE_WR_CH7_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH8_SUSP_WE:
+ *     BitOffset : 31
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH8_SUSP_WE, 31, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_SUSP_WE, DISABLE_WR_CH8_SUSP, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_SUSP_WE, ENABLE_WR_CH8_SUSP, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH1_ABORT:
+ *     BitOffset : 32
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH1_ABORT, 32, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_ABORT, DISABLE_CH1_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_ABORT, ENABLE_CH1_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH2_ABORT:
+ *     BitOffset : 33
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH2_ABORT, 33, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_ABORT, DISABLE_CH2_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_ABORT, ENABLE_CH2_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH3_ABORT:
+ *     BitOffset : 34
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH3_ABORT, 34, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_ABORT, DISABLE_CH3_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_ABORT, ENABLE_CH3_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH4_ABORT:
+ *     BitOffset : 35
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH4_ABORT, 35, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_ABORT, DISABLE_CH4_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_ABORT, ENABLE_CH4_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH5_ABORT:
+ *     BitOffset : 36
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH5_ABORT, 36, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_ABORT, DISABLE_CH5_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_ABORT, ENABLE_CH5_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH6_ABORT:
+ *     BitOffset : 37
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH6_ABORT, 37, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_ABORT, DISABLE_CH6_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_ABORT, ENABLE_CH6_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH7_ABORT:
+ *     BitOffset : 38
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH7_ABORT, 38, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_ABORT, DISABLE_CH7_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_ABORT, ENABLE_CH7_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH8_ABORT:
+ *     BitOffset : 39
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH8_ABORT, 39, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_ABORT, DISABLE_CH8_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_ABORT, ENABLE_CH8_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH1_ABORT_WE:
+ *     BitOffset : 40
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH1_ABORT_WE, 40, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_ABORT_WE, DISABLE_WR_CH1_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH1_ABORT_WE, ENABLE_WR_CH1_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH2_ABORT_WE:
+ *     BitOffset : 41
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH2_ABORT_WE, 41, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_ABORT_WE, DISABLE_WR_CH2_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH2_ABORT_WE, ENABLE_WR_CH2_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH3_ABORT_WE:
+ *     BitOffset : 42
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH3_ABORT_WE, 42, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_ABORT_WE, DISABLE_WR_CH3_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH3_ABORT_WE, ENABLE_WR_CH3_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH4_ABORT_WE:
+ *     BitOffset : 43
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH4_ABORT_WE, 43, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_ABORT_WE, DISABLE_WR_CH4_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH4_ABORT_WE, ENABLE_WR_CH4_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH5_ABORT_WE:
+ *     BitOffset : 44
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH5_ABORT_WE, 44, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_ABORT_WE, DISABLE_WR_CH5_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH5_ABORT_WE, ENABLE_WR_CH5_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH6_ABORT_WE:
+ *     BitOffset : 45
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH6_ABORT_WE, 45, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_ABORT_WE, DISABLE_WR_CH6_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH6_ABORT_WE, ENABLE_WR_CH6_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH7_ABORT_WE:
+ *     BitOffset : 46
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH7_ABORT_WE, 46, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_ABORT_WE, DISABLE_WR_CH7_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH7_ABORT_WE, ENABLE_WR_CH7_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   CH8_ABORT_WE:
+ *     BitOffset : 47
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, CH8_ABORT_WE, 47, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_ABORT_WE, DISABLE_WR_CH8_ABORT, 0x0);
+SEDI_RBFV_DEFINE(DMAC, CHENREG, CH8_ABORT_WE, ENABLE_WR_CH8_ABORT, 0x1);
+
+/*
+ * Bit Field of Register CHENREG
+ *   RSVD_DMAC_CHENREG:
+ *     BitOffset : 48
+ *     BitWidth  : 16
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, CHENREG, RSVD_DMAC_CHENREG, 48, 16, RO, (uint64_t)0x0);
+
+/* ********* DMAC INTSTATUSREG ***********
+ *
+ * Register of SEDI DMAC
+ *   INTSTATUSREG: DW_axi_dmac Combined Interrupt Status Register
+ *     AddressOffset  : 0x30
+ *     AccessType     : RO
+ *     WritableBitMask: 0x0
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMAC, INTSTATUSREG, 0x30, RO, (uint64_t)0x0, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   CH1_IntStat:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, CH1_IntStat, 0, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH1_IntStat, ACTIVE, 0x1);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH1_IntStat, INACTIVE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   CH2_IntStat:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, CH2_IntStat, 1, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH2_IntStat, ACTIVE, 0x1);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH2_IntStat, INACTIVE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   CH3_IntStat:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, CH3_IntStat, 2, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH3_IntStat, ACTIVE, 0x1);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH3_IntStat, INACTIVE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   CH4_IntStat:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, CH4_IntStat, 3, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH4_IntStat, ACTIVE, 0x1);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH4_IntStat, INACTIVE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   CH5_IntStat:
+ *     BitOffset : 4
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, CH5_IntStat, 4, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH5_IntStat, ACTIVE, 0x1);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH5_IntStat, INACTIVE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   CH6_IntStat:
+ *     BitOffset : 5
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, CH6_IntStat, 5, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH6_IntStat, ACTIVE, 0x1);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH6_IntStat, INACTIVE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   CH7_IntStat:
+ *     BitOffset : 6
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, CH7_IntStat, 6, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH7_IntStat, ACTIVE, 0x1);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH7_IntStat, INACTIVE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   CH8_IntStat:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, CH8_IntStat, 7, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH8_IntStat, ACTIVE, 0x1);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CH8_IntStat, INACTIVE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   RSVD_DMAC_INTSTATUSREG:
+ *     BitOffset : 8
+ *     BitWidth  : 8
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, RSVD_DMAC_INTSTATUSREG, 8, 8, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   CommonReg_IntStat:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, CommonReg_IntStat, 16, 1, RO, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CommonReg_IntStat, ACTIVE, 0x1);
+SEDI_RBFV_DEFINE(DMAC, INTSTATUSREG, CommonReg_IntStat, INACTIVE, 0x0);
+
+/*
+ * Bit Field of Register INTSTATUSREG
+ *   RSVD_DMAC_INTSTATUSREG_63to17:
+ *     BitOffset : 17
+ *     BitWidth  : 47
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, INTSTATUSREG, RSVD_DMAC_INTSTATUSREG_63to17, 17, 47, RO, (uint64_t)0x0);
+
+/* ********* DMAC COMMONREG_INTCLEARREG ***********
+ *
+ * Register of SEDI DMAC
+ *   COMMONREG_INTCLEARREG: DW_axi_dmac Common Register Space Interrupt Clear Register
+ *     AddressOffset  : 0x38
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffffffffffffff
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMAC, COMMONREG_INTCLEARREG, 0x38, RW, (uint64_t)0xffffffffffffffff, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_SLVIF_CommonReg_DEC_ERR_IntStat:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_DEC_ERR_IntStat, 0, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_DEC_ERR_IntStat,
+		 CLEAR_SLVIF_CommonReg_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_DEC_ERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_SLVIF_CommonReg_WR2RO_ERR_IntStat:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_WR2RO_ERR_IntStat, 1, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_WR2RO_ERR_IntStat,
+		 CLEAR_SLVIF_CommonReg_WR2RO_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_WR2RO_ERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_SLVIF_CommonReg_RD2WO_ERR_IntStat:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_RD2WO_ERR_IntStat, 2, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_RD2WO_ERR_IntStat,
+		 CLEAR_SLVIF_CommonReg_RD2WO_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_RD2WO_ERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_SLVIF_CommonReg_WrOnHold_ERR_IntStat:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_WrOnHold_ERR_IntStat, 3, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_WrOnHold_ERR_IntStat,
+		 CLEAR_SLVIF_CommonReg_WrOnHold_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_WrOnHold_ERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   RSVD_DMAC_COMMONREG_INTCLEARREG_6to4:
+ *     BitOffset : 4
+ *     BitWidth  : 3
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, RSVD_DMAC_COMMONREG_INTCLEARREG_6to4, 4, 3, RW,
+		(uint64_t)0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_SLVIF_CommonReg_WRPARITY_ERR_IntStat:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_WRPARITY_ERR_IntStat, 7, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_WRPARITY_ERR_IntStat,
+		 CLEAR_SLVIF_CommonReg_WRPARITY_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_CommonReg_WRPARITY_ERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_SLVIF_UndefinedReg_DEC_ERR_IntStat:
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_UndefinedReg_DEC_ERR_IntStat, 8, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_UndefinedReg_DEC_ERR_IntStat,
+		 CLEAR_SLVIF_UndefinedReg_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_SLVIF_UndefinedReg_DEC_ERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF1_RCH0_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH0_EccPROT_CorrERR_IntStat, 9, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH0_EccPROT_CorrERR_IntStat,
+		 CLEAR_MXIF1_RCH0_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH0_EccPROT_CorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat, 10, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,
+		 CLEAR_MXIF1_RCH0_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF1_RCH1_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 11
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH1_EccPROT_CorrERR_IntStat, 11, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH1_EccPROT_CorrERR_IntStat,
+		 CLEAR_MXIF1_RCH1_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH1_EccPROT_CorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 12
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat, 12, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,
+		 CLEAR_MXIF1_RCH1_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF1_BCH_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 13
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_BCH_EccPROT_CorrERR_IntStat, 13, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_BCH_EccPROT_CorrERR_IntStat,
+		 CLEAR_MXIF1_BCH_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_BCH_EccPROT_CorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF1_BCH_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 14
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_BCH_EccPROT_UnCorrERR_IntStat, 14, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_BCH_EccPROT_UnCorrERR_IntStat,
+		 CLEAR_MXIF1_BCH_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF1_BCH_EccPROT_UnCorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF2_RCH0_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 15
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH0_EccPROT_CorrERR_IntStat, 15, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH0_EccPROT_CorrERR_IntStat,
+		 CLEAR_MXIF2_RCH0_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH0_EccPROT_CorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat, 16, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,
+		 CLEAR_MXIF2_RCH0_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF2_RCH1_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH1_EccPROT_CorrERR_IntStat, 17, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH1_EccPROT_CorrERR_IntStat,
+		 CLEAR_MXIF2_RCH1_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH1_EccPROT_CorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 18
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat, 18, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,
+		 CLEAR_MXIF2_RCH1_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF2_BCH_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 19
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_BCH_EccPROT_CorrERR_IntStat, 19, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_BCH_EccPROT_CorrERR_IntStat,
+		 CLEAR_MXIF2_BCH_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_BCH_EccPROT_CorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   Clear_MXIF2_BCH_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 20
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_BCH_EccPROT_UnCorrERR_IntStat, 20, 1, RW,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_BCH_EccPROT_UnCorrERR_IntStat,
+		 CLEAR_MXIF2_BCH_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTCLEARREG, Clear_MXIF2_BCH_EccPROT_UnCorrERR_IntStat, No_ACTION,
+		 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTCLEARREG
+ *   RSVD_DMAC_COMMONREG_INTCLEARREG_63to21:
+ *     BitOffset : 21
+ *     BitWidth  : 43
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTCLEARREG, RSVD_DMAC_COMMONREG_INTCLEARREG_63to21, 21, 43, RW,
+		(uint64_t)0x0);
+
+/* ********* DMAC COMMONREG_INTSTATUS_ENABLEREG ***********
+ *
+ * Register of SEDI DMAC
+ *   COMMONREG_INTSTATUS_ENABLEREG: DW_axi_dmac Common Register Space Interrupt Enable Register
+ *     AddressOffset  : 0x40
+ *     AccessType     : RW
+ *     WritableBitMask: 0x10f
+ *     ResetValue     : (uint64_t)0xffffffffffffffff
+ */
+SEDI_REG_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, 0x40, RW, (uint64_t)0x10f,
+		(uint64_t)0xffffffffffffffff);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_CommonReg_DEC_ERR_IntStat:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_DEC_ERR_IntStat, 0, 1,
+		RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_DEC_ERR_IntStat,
+		 DISABLE_SLVIF_CommonReg_DEC_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_DEC_ERR_IntStat,
+		 ENABLE_SLVIF_CommonReg_DEC_ERR, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_CommonReg_WR2RO_ERR_IntStat:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_WR2RO_ERR_IntStat, 1, 1,
+		RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_WR2RO_ERR_IntStat,
+		 DISABLE_SLVIF_CommonReg_WR2RO_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_WR2RO_ERR_IntStat,
+		 ENABLE_SLVIF_CommonReg_WR2RO_ERR, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_CommonReg_RD2WO_ERR_IntStat:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_RD2WO_ERR_IntStat, 2, 1,
+		RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_RD2WO_ERR_IntStat,
+		 DISABLE_SLVIF_CommonReg_RD2WO_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_RD2WO_ERR_IntStat,
+		 ENABLE_SLVIF_CommonReg_RD2WO_ERR, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_CommonReg_WrOnHold_ERR_IntStat:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_WrOnHold_ERR_IntStat, 3,
+		1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_WrOnHold_ERR_IntStat,
+		 DISABLE_SLVIF_CommonReg_WrOnHold_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_WrOnHold_ERR_IntStat,
+		 ENABLE_SLVIF_CommonReg_WrOnHold_ERR, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_6to4:
+ *     BitOffset : 4
+ *     BitWidth  : 3
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x7
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_6to4,
+		4, 3, RO, (uint64_t)0x7);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_CommonReg_WRPARITY_ERR_IntStat:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_WRPARITY_ERR_IntStat, 7,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_WRPARITY_ERR_IntStat,
+		 DISABLE_SLVIF_CommonReg_WRPARITY_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_CommonReg_WRPARITY_ERR_IntStat,
+		 ENABLE_SLVIF_CommonReg_WRPARITY_ERR, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_SLVIF_UndefinedReg_DEC_ERR_IntStat:
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_UndefinedReg_DEC_ERR_IntStat, 8,
+		1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_UndefinedReg_DEC_ERR_IntStat,
+		 DISABLE_SLVIF_UndefinedReg_DEC_ERR, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_SLVIF_UndefinedReg_DEC_ERR_IntStat,
+		 ENABLE_SLVIF_UndefinedReg_DEC_ERR, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF1_RCH0_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_CorrERR_IntStat, 9,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_CorrERR_IntStat,
+		 DISABLE_MXIF1_RCH0_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_CorrERR_IntStat,
+		 ENABLE_MXIF1_RCH0_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,
+		10, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,
+		 DISABLE_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,
+		 ENABLE_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF1_RCH1_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 11
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_CorrERR_IntStat, 11,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_CorrERR_IntStat,
+		 DISABLE_MXIF1_RCH1_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_CorrERR_IntStat,
+		 ENABLE_MXIF1_RCH1_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 12
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,
+		12, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,
+		 DISABLE_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,
+		 ENABLE_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF1_BCH_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 13
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_BCH_EccPROT_CorrERR_IntStat, 13,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_BCH_EccPROT_CorrERR_IntStat,
+		 DISABLE_MXIF1_BCH_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_BCH_EccPROT_CorrERR_IntStat,
+		 ENABLE_MXIF1_BCH_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 14
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntStat, 14,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntStat,
+		 DISABLE_MXIF1_BCH_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntStat,
+		 ENABLE_MXIF1_BCH_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF2_RCH0_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 15
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_CorrERR_IntStat, 15,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_CorrERR_IntStat,
+		 DISABLE_MXIF2_RCH0_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_CorrERR_IntStat,
+		 ENABLE_MXIF2_RCH0_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,
+		16, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,
+		 DISABLE_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,
+		 ENABLE_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF2_RCH1_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_CorrERR_IntStat, 17,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_CorrERR_IntStat,
+		 DISABLE_MXIF2_RCH1_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_CorrERR_IntStat,
+		 ENABLE_MXIF2_RCH1_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 18
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,
+		18, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,
+		 DISABLE_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,
+		 ENABLE_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF2_BCH_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 19
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_BCH_EccPROT_CorrERR_IntStat, 19,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_BCH_EccPROT_CorrERR_IntStat,
+		 DISABLE_MXIF2_BCH_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_BCH_EccPROT_CorrERR_IntStat,
+		 ENABLE_MXIF2_BCH_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 20
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntStat, 20,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntStat,
+		 DISABLE_MXIF2_BCH_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntStat,
+		 ENABLE_MXIF2_BCH_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUS_ENABLEREG
+ *   RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_63to21:
+ *     BitOffset : 21
+ *     BitWidth  : 43
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x7ffffffffff
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUS_ENABLEREG, RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_63to21,
+		21, 43, RO, (uint64_t)0x7ffffffffff);
+
+/* ********* DMAC COMMONREG_INTSIGNAL_ENABLEREG ***********
+ *
+ * Register of SEDI DMAC
+ *   COMMONREG_INTSIGNAL_ENABLEREG: DW_axi_dmac Common Register Space Interrupt Signal Enable
+ * Register AddressOffset  : 0x48 AccessType     : RW WritableBitMask: 0x10f ResetValue     :
+ * (uint64_t)0xffffffffffffffff
+ */
+SEDI_REG_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, 0x48, RW, (uint64_t)0x10f,
+		(uint64_t)0xffffffffffffffff);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_CommonReg_DEC_ERR_IntSignal:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_DEC_ERR_IntSignal, 0, 1,
+		RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_DEC_ERR_IntSignal,
+		 DISABLE_SLVIF_CommonReg_DEC_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_DEC_ERR_IntSignal,
+		 ENABLE_SLVIF_CommonReg_DEC_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_CommonReg_WR2RO_ERR_IntSignal:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_WR2RO_ERR_IntSignal, 1,
+		1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_WR2RO_ERR_IntSignal,
+		 DISABLE_SLVIF_CommonReg_WR2RO_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_WR2RO_ERR_IntSignal,
+		 ENABLE_SLVIF_CommonReg_WR2RO_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_CommonReg_RD2WO_ERR_IntSignal:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_RD2WO_ERR_IntSignal, 2,
+		1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_RD2WO_ERR_IntSignal,
+		 DISABLE_SLVIF_CommonReg_RD2WO_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_RD2WO_ERR_IntSignal,
+		 ENABLE_SLVIF_CommonReg_RD2WO_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_CommonReg_WrOnHold_ERR_IntSignal:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_WrOnHold_ERR_IntSignal,
+		3, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_WrOnHold_ERR_IntSignal,
+		 DISABLE_SLVIF_CommonReg_WrOnHold_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_WrOnHold_ERR_IntSignal,
+		 ENABLE_SLVIF_CommonReg_WrOnHold_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_6to4:
+ *     BitOffset : 4
+ *     BitWidth  : 3
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x7
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_6to4,
+		4, 3, RO, (uint64_t)0x7);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_CommonReg_WRPARITY_ERR_IntSignal:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_WRPARITY_ERR_IntSignal,
+		7, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_WRPARITY_ERR_IntSignal,
+		 DISABLE_SLVIF_CommonReg_WRPARITY_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_CommonReg_WRPARITY_ERR_IntSignal,
+		 ENABLE_SLVIF_CommonReg_WRPARITY_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_SLVIF_UndefinedReg_DEC_ERR_IntSignal:
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_UndefinedReg_DEC_ERR_IntSignal, 8,
+		1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_UndefinedReg_DEC_ERR_IntSignal,
+		 DISABLE_SLVIF_UndefinedReg_DEC_ERR_IntSignal, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_SLVIF_UndefinedReg_DEC_ERR_IntSignal,
+		 ENABLE_SLVIF_UndefinedReg_DEC_ERR_IntSignal, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF1_RCH0_EccPROT_CorrERR_IntSignal:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_CorrERR_IntSignal, 9,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_CorrERR_IntSignal,
+		 DISABLE_MXIF1_RCH0_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_CorrERR_IntSignal,
+		 ENABLE_MXIF1_RCH0_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntSignal:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntSignal,
+		10, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntSignal,
+		 DISABLE_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntSignal,
+		 ENABLE_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF1_RCH1_EccPROT_CorrERR_IntSignal:
+ *     BitOffset : 11
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_CorrERR_IntSignal,
+		11, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_CorrERR_IntSignal,
+		 DISABLE_MXIF1_RCH1_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_CorrERR_IntSignal,
+		 ENABLE_MXIF1_RCH1_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntSignal:
+ *     BitOffset : 12
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntSignal,
+		12, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntSignal,
+		 DISABLE_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntSignal,
+		 ENABLE_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF1_BCH_EccPROT_CorrERR_IntSignal:
+ *     BitOffset : 13
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_BCH_EccPROT_CorrERR_IntSignal, 13,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_BCH_EccPROT_CorrERR_IntSignal,
+		 DISABLE_MXIF1_BCH_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_BCH_EccPROT_CorrERR_IntSignal,
+		 ENABLE_MXIF1_BCH_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntSignal:
+ *     BitOffset : 14
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntSignal,
+		14, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntSignal,
+		 DISABLE_MXIF1_BCH_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntSignal,
+		 ENABLE_MXIF1_BCH_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF2_RCH0_EccPROT_CorrERR_IntSignal:
+ *     BitOffset : 15
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_CorrERR_IntSignal,
+		15, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_CorrERR_IntSignal,
+		 DISABLE_MXIF2_RCH0_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_CorrERR_IntSignal,
+		 ENABLE_MXIF2_RCH0_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntSignal:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntSignal,
+		16, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntSignal,
+		 DISABLE_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntSignal,
+		 ENABLE_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF2_RCH1_EccPROT_CorrERR_IntSignal:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_CorrERR_IntSignal,
+		17, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_CorrERR_IntSignal,
+		 DISABLE_MXIF2_RCH1_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_CorrERR_IntSignal,
+		 ENABLE_MXIF2_RCH1_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntSignal:
+ *     BitOffset : 18
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntSignal,
+		18, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntSignal,
+		 DISABLE_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntSignal,
+		 ENABLE_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF2_BCH_EccPROT_CorrERR_IntSignal:
+ *     BitOffset : 19
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_BCH_EccPROT_CorrERR_IntSignal, 19,
+		1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_BCH_EccPROT_CorrERR_IntSignal,
+		 DISABLE_MXIF2_BCH_EccPROT_CorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_BCH_EccPROT_CorrERR_IntSignal,
+		 ENABLE_MXIF2_BCH_EccPROT_CorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntSignal:
+ *     BitOffset : 20
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntSignal,
+		20, 1, RO, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntSignal,
+		 DISABLE_MXIF2_BCH_EccPROT_UnCorrERR_IntStat, 0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntSignal,
+		 ENABLE_MXIF2_BCH_EccPROT_UnCorrERR_IntStat, 0x1);
+
+/*
+ * Bit Field of Register COMMONREG_INTSIGNAL_ENABLEREG
+ *   RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_63to21:
+ *     BitOffset : 21
+ *     BitWidth  : 43
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x7ffffffffff
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSIGNAL_ENABLEREG, RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_63to21,
+		21, 43, RO, (uint64_t)0x7ffffffffff);
+
+/* ********* DMAC COMMONREG_INTSTATUSREG ***********
+ *
+ * Register of SEDI DMAC
+ *   COMMONREG_INTSTATUSREG: DW_axi_dmac Common Register Space Interrupt Status Register
+ *     AddressOffset  : 0x50
+ *     AccessType     : RO
+ *     WritableBitMask: 0x0
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMAC, COMMONREG_INTSTATUSREG, 0x50, RO, (uint64_t)0x0, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   SLVIF_CommonReg_DEC_ERR_IntStat:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_DEC_ERR_IntStat, 0, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_DEC_ERR_IntStat,
+		 Active_CommonReg_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_DEC_ERR_IntStat,
+		 Inactive_CommonReg_DEC_ERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   SLVIF_CommonReg_WR2RO_ERR_IntStat:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_WR2RO_ERR_IntStat, 1, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_WR2RO_ERR_IntStat,
+		 Active_CommonReg_WR2RO_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_WR2RO_ERR_IntStat,
+		 Inactive_CommonReg_WR2RO_ERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   SLVIF_CommonReg_RD2WO_ERR_IntStat:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_RD2WO_ERR_IntStat, 2, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_RD2WO_ERR_IntStat,
+		 Active_CommonReg_RD2WO_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_RD2WO_ERR_IntStat,
+		 Inactive_CommonReg_RD2WO_ERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   SLVIF_CommonReg_WrOnHold_ERR_IntStat:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_WrOnHold_ERR_IntStat, 3, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_WrOnHold_ERR_IntStat,
+		 Active_CommonReg_WrOnHold_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_WrOnHold_ERR_IntStat,
+		 Inactive_CommonReg_WrOnHold_ERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   RSVD_DMAC_COMMONREG_INTSTATUSREG_6to4:
+ *     BitOffset : 4
+ *     BitWidth  : 3
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, RSVD_DMAC_COMMONREG_INTSTATUSREG_6to4, 4, 3, RO,
+		(uint64_t)0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   SLVIF_CommonReg_WRPARITY_ERR_IntStat:
+ *     BitOffset : 7
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_WRPARITY_ERR_IntStat, 7, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_WRPARITY_ERR_IntStat,
+		 Active_CommonReg_WRPARITY_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_CommonReg_WRPARITY_ERR_IntStat,
+		 Inactive_CommonReg_WRPARITY_ERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   SLVIF_UndefinedReg_DEC_ERR_IntStat:
+ *     BitOffset : 8
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_UndefinedReg_DEC_ERR_IntStat, 8, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_UndefinedReg_DEC_ERR_IntStat,
+		 Active_UndefinedReg_DEC_ERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, SLVIF_UndefinedReg_DEC_ERR_IntStat,
+		 Inactive_UndefinedReg_DEC_ERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF1_RCH0_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 9
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH0_EccPROT_CorrERR_IntStat, 9, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH0_EccPROT_CorrERR_IntStat,
+		 Active_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH0_EccPROT_CorrERR_IntStat,
+		 Inactive_EccPROT_CorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF1_RCH0_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 10
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH0_EccPROT_UnCorrERR_IntStat, 10, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,
+		 Active_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,
+		 Inactive_EccPROT_UnCorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF1_RCH1_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 11
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH1_EccPROT_CorrERR_IntStat, 11, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH1_EccPROT_CorrERR_IntStat,
+		 Active_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH1_EccPROT_CorrERR_IntStat,
+		 Inactive_EccPROT_CorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF1_RCH1_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 12
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH1_EccPROT_UnCorrERR_IntStat, 12, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,
+		 Active_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,
+		 Inactive_EccPROT_UnCorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF1_BCH_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 13
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_BCH_EccPROT_CorrERR_IntStat, 13, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_BCH_EccPROT_CorrERR_IntStat,
+		 Active_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_BCH_EccPROT_CorrERR_IntStat,
+		 Inactive_EccPROT_CorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF1_BCH_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 14
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_BCH_EccPROT_UnCorrERR_IntStat, 14, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_BCH_EccPROT_UnCorrERR_IntStat,
+		 Active_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF1_BCH_EccPROT_UnCorrERR_IntStat,
+		 Inactive_EccPROT_UnCorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF2_RCH0_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 15
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH0_EccPROT_CorrERR_IntStat, 15, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH0_EccPROT_CorrERR_IntStat,
+		 Active_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH0_EccPROT_CorrERR_IntStat,
+		 Inactive_EccPROT_CorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF2_RCH0_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 16
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH0_EccPROT_UnCorrERR_IntStat, 16, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,
+		 Active_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,
+		 Inactive_EccPROT_UnCorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF2_RCH1_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 17
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH1_EccPROT_CorrERR_IntStat, 17, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH1_EccPROT_CorrERR_IntStat,
+		 Active_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH1_EccPROT_CorrERR_IntStat,
+		 Inactive_EccPROT_CorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF2_RCH1_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 18
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH1_EccPROT_UnCorrERR_IntStat, 18, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,
+		 Active_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,
+		 Inactive_EccPROT_UnCorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF2_BCH_EccPROT_CorrERR_IntStat:
+ *     BitOffset : 19
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_BCH_EccPROT_CorrERR_IntStat, 19, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_BCH_EccPROT_CorrERR_IntStat,
+		 Active_EccPROT_CorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_BCH_EccPROT_CorrERR_IntStat,
+		 Inactive_EccPROT_CorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   MXIF2_BCH_EccPROT_UnCorrERR_IntStat:
+ *     BitOffset : 20
+ *     BitWidth  : 1
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_BCH_EccPROT_UnCorrERR_IntStat, 20, 1, RO,
+		(uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_BCH_EccPROT_UnCorrERR_IntStat,
+		 Active_EccPROT_UnCorrERR, 0x1);
+SEDI_RBFV_DEFINE(DMAC, COMMONREG_INTSTATUSREG, MXIF2_BCH_EccPROT_UnCorrERR_IntStat,
+		 Inactive_EccPROT_UnCorrERR, 0x0);
+
+/*
+ * Bit Field of Register COMMONREG_INTSTATUSREG
+ *   RSVD_DMAC_COMMONREG_INTSTATUSREG_63to21:
+ *     BitOffset : 21
+ *     BitWidth  : 43
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, COMMONREG_INTSTATUSREG, RSVD_DMAC_COMMONREG_INTSTATUSREG_63to21, 21, 43, RO,
+		(uint64_t)0x0);
+
+/* ********* DMAC RESETREG ***********
+ *
+ * Register of SEDI DMAC
+ *   RESETREG: DW_axi_dmac Software Reset Register
+ *     AddressOffset  : 0x58
+ *     AccessType     : RW
+ *     WritableBitMask: 0x1
+ *     ResetValue     : (uint64_t)0x0
+ */
+SEDI_REG_DEFINE(DMAC, RESETREG, 0x58, RW, (uint64_t)0x1, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register RESETREG
+ *   DMAC_RST:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, RESETREG, DMAC_RST, 0, 1, RW, (uint64_t)0x0);
+SEDI_RBFV_DEFINE(DMAC, RESETREG, DMAC_RST, 0, 0);
+SEDI_RBFV_DEFINE(DMAC, RESETREG, DMAC_RST, 1, 1);
+
+/*
+ * Bit Field of Register RESETREG
+ *   RSVD_DMAC_ResetReg_1to63:
+ *     BitOffset : 1
+ *     BitWidth  : 63
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, RESETREG, RSVD_DMAC_ResetReg_1to63, 1, 63, RO, (uint64_t)0x0);
+
+/* ********* DMAC LOWPOWER_CFGREG ***********
+ *
+ * Register of SEDI DMAC
+ *   LOWPOWER_CFGREG: DW_axi_dmac Low Power Configuration Register
+ *     AddressOffset  : 0x60
+ *     AccessType     : RW
+ *     WritableBitMask: 0xffffff0000000f
+ *     ResetValue     : (uint64_t)0xf0f0f0000000f
+ */
+SEDI_REG_DEFINE(DMAC, LOWPOWER_CFGREG, 0x60, RW, (uint64_t)0xffffff0000000f,
+		(uint64_t)0xf0f0f0000000f);
+
+/*
+ * Bit Field of Register LOWPOWER_CFGREG
+ *   GBL_CSLP_EN:
+ *     BitOffset : 0
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, LOWPOWER_CFGREG, GBL_CSLP_EN, 0, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, LOWPOWER_CFGREG, GBL_CSLP_EN, GBL_CSLP_DISABLE, 0x0);
+SEDI_RBFV_DEFINE(DMAC, LOWPOWER_CFGREG, GBL_CSLP_EN, GBL_CSLP_ENABLE, 0x1);
+
+/*
+ * Bit Field of Register LOWPOWER_CFGREG
+ *   CHNL_CSLP_EN:
+ *     BitOffset : 1
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, LOWPOWER_CFGREG, CHNL_CSLP_EN, 1, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, LOWPOWER_CFGREG, CHNL_CSLP_EN, CHNL_CSLP_DISABLE, 0x0);
+SEDI_RBFV_DEFINE(DMAC, LOWPOWER_CFGREG, CHNL_CSLP_EN, CHNL_CSLP_ENABLE, 0x1);
+
+/*
+ * Bit Field of Register LOWPOWER_CFGREG
+ *   SBIU_CSLP_EN:
+ *     BitOffset : 2
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, LOWPOWER_CFGREG, SBIU_CSLP_EN, 2, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, LOWPOWER_CFGREG, SBIU_CSLP_EN, SBIU_CSLP_DISABLE, 0x0);
+SEDI_RBFV_DEFINE(DMAC, LOWPOWER_CFGREG, SBIU_CSLP_EN, SBIU_CSLP_ENABLE, 0x1);
+
+/*
+ * Bit Field of Register LOWPOWER_CFGREG
+ *   MXIF_CSLP_EN:
+ *     BitOffset : 3
+ *     BitWidth  : 1
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0x1
+ */
+SEDI_RBF_DEFINE(DMAC, LOWPOWER_CFGREG, MXIF_CSLP_EN, 3, 1, RW, (uint64_t)0x1);
+SEDI_RBFV_DEFINE(DMAC, LOWPOWER_CFGREG, MXIF_CSLP_EN, MXIF_CSLP_DISABLE, 0x0);
+SEDI_RBFV_DEFINE(DMAC, LOWPOWER_CFGREG, MXIF_CSLP_EN, MXIF_CSLP_ENABLE, 0x1);
+
+/*
+ * Bit Field of Register LOWPOWER_CFGREG
+ *   RSVD_DMAC_LOWPOWER_CFGREG_31to4:
+ *     BitOffset : 4
+ *     BitWidth  : 28
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, LOWPOWER_CFGREG, RSVD_DMAC_LOWPOWER_CFGREG_31to4, 4, 28, RO, (uint64_t)0x0);
+
+/*
+ * Bit Field of Register LOWPOWER_CFGREG
+ *   GLCH_LPDLY:
+ *     BitOffset : 32
+ *     BitWidth  : 8
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0xf
+ */
+SEDI_RBF_DEFINE(DMAC, LOWPOWER_CFGREG, GLCH_LPDLY, 32, 8, RW, (uint64_t)0xf);
+
+/*
+ * Bit Field of Register LOWPOWER_CFGREG
+ *   SBIU_LPDLY:
+ *     BitOffset : 40
+ *     BitWidth  : 8
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0xf
+ */
+SEDI_RBF_DEFINE(DMAC, LOWPOWER_CFGREG, SBIU_LPDLY, 40, 8, RW, (uint64_t)0xf);
+
+/*
+ * Bit Field of Register LOWPOWER_CFGREG
+ *   MXIF_LPDLY:
+ *     BitOffset : 48
+ *     BitWidth  : 8
+ *     AccessType: RW
+ *     ResetValue: (uint64_t)0xf
+ */
+SEDI_RBF_DEFINE(DMAC, LOWPOWER_CFGREG, MXIF_LPDLY, 48, 8, RW, (uint64_t)0xf);
+
+/*
+ * Bit Field of Register LOWPOWER_CFGREG
+ *   RSVD_DMAC_LOWPOWER_CFGREG_63to56:
+ *     BitOffset : 56
+ *     BitWidth  : 8
+ *     AccessType: RO
+ *     ResetValue: (uint64_t)0x0
+ */
+SEDI_RBF_DEFINE(DMAC, LOWPOWER_CFGREG, RSVD_DMAC_LOWPOWER_CFGREG_63to56, 56, 8, RO, (uint64_t)0x0);
+
+/*
+ * Registers' Address Map Structure
+ */
+
+typedef struct {
+	/* DW_axi_dmac Component ID Register */
+	__IO_R uint64_t idreg;
+
+	/* DW_axi_dmac Component Version Register */
+	__IO_R uint64_t compverreg;
+
+	/* DW_axi_dmac Global Configuration Register */
+	__IO_RW uint64_t cfgreg;
+
+	/* DW_axi_dmac Channel Enable Register */
+	__IO_RW uint64_t chenreg;
+
+	/* Reserved */
+	__IO_RW uint64_t reserved0[2];
+
+	/* DW_axi_dmac Combined Interrupt Status Register */
+	__IO_R uint64_t intstatusreg;
+
+	/* DW_axi_dmac Common Register Space Interrupt Clear Register */
+	__IO_RW uint64_t commonreg_intclearreg;
+
+	/* DW_axi_dmac Common Register Space Interrupt Enable Register */
+	__IO_RW uint64_t commonreg_intstatus_enablereg;
+
+	/* DW_axi_dmac Common Register Space Interrupt Signal Enable Register */
+	__IO_RW uint64_t commonreg_intsignal_enablereg;
+
+	/* DW_axi_dmac Common Register Space Interrupt Status Register */
+	__IO_R uint64_t commonreg_intstatusreg;
+
+	/* DW_axi_dmac Software Reset Register */
+	__IO_RW uint64_t resetreg;
+
+	/* DW_axi_dmac Low Power Configuration Register */
+	__IO_RW uint64_t lowpower_cfgreg;
+
+} sedi_dmac_regs_t;
+#define SEDI_DMAC_REGS_T sedi_dmac_regs_t
+
+#endif /* _SEDI_DMAC_REGS_H_ */
diff --git a/bsp_sedi/soc/intel_ish/include/sedi_soc_defs.h b/bsp_sedi/soc/intel_ish/include/sedi_soc_defs.h
index b714cd8..7899b90 100644
--- a/bsp_sedi/soc/intel_ish/include/sedi_soc_defs.h
+++ b/bsp_sedi/soc/intel_ish/include/sedi_soc_defs.h
@@ -192,8 +192,6 @@ typedef enum {
 	SEDI_DEVID_TOP
 } sedi_devid_t;
 
-#define DMA_MISC_FUNC   1
-
 /*!
  * peripheral device id for dma handshake
  */
diff --git a/bsp_sedi/soc/intel_ish/include/sedi_soc_regs.h b/bsp_sedi/soc/intel_ish/include/sedi_soc_regs.h
index 1972a5f..266b533 100644
--- a/bsp_sedi/soc/intel_ish/include/sedi_soc_regs.h
+++ b/bsp_sedi/soc/intel_ish/include/sedi_soc_regs.h
@@ -19,6 +19,8 @@ SEDI_IREG_BASE_DEFINE(UART, 2, 0x08104000);
 /****** dma *****/
 
 SEDI_IREG_BASE_DEFINE(DMA, 0, 0x10100000);
+#define SEDI_DMA_CHAN_OFF	0x100
+#define SEDI_DMA_MISC_OFF	0x1000
 
 /****** i2c *****/
 
diff --git a/zephyr/drivers/dma/CMakeLists.txt b/zephyr/drivers/dma/CMakeLists.txt
index 8908122..d7e1ad6 100644
--- a/zephyr/drivers/dma/CMakeLists.txt
+++ b/zephyr/drivers/dma/CMakeLists.txt
@@ -2,4 +2,8 @@
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
-zephyr_library_ootree_sources(${BSP_SEDI_DIR}/drivers/dma/sedi_dma_ann_1p0.c)
+if(CONFIG_SOC_INTEL_ISH_5_4_1 OR CONFIG_SOC_INTEL_ISH_5_6_0)
+  zephyr_library_ootree_sources(${BSP_SEDI_DIR}/drivers/dma/sedi_dma_ann_1p0.c)
+else()
+  zephyr_library_ootree_sources(${BSP_SEDI_DIR}/drivers/dma/sedi_dma_dw_axi.c)
+endif()