From 9b2983d06fb90e0103e5ec412fb765b4e715f0ef Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Fri, 19 Dec 2025 10:55:06 -0700 Subject: [PATCH 1/2] readme: Add core UMaskExt documentation This commit adds documentation for the core event attribute UMaskExt. Note that the attribute will eventually be renamed to UMask2 to align with the Intel SDM. --- README.md | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 112fe26f..26db623d 100644 --- a/README.md +++ b/README.md @@ -199,9 +199,19 @@ is defined architecturally. Each value corresponds to an event logic unit and sh mask value to obtain an architectural performance event. ### UMask -This field maps to the Unit Mask filed in the `IA32_PERFEVTSELx[15:8]` MSRs. It further qualifies the event logic +This field maps to the Unit Mask field in the `IA32_PERFEVTSELx[15:8]` MSRs. It further qualifies the event logic unit selected in the event select field to detect a specific micro-architectural condition. +### UMaskExt (Core events) +This field maps to the Unit Mask 2 field in the `IA32_PERFEVTSELx[47:40]` MSRs. First introduced with architectural +performance monitoring version 6. + +> These bits qualify the condition that the selected event logic unit detects. Valid UMASK2 values for each +event logic unit are specific to the unit. The new UMASK2 field may also be used in conjunction with UMASK. + +:warning: `UMaskExt` will be renamed to `UMask2` to align with the Intel® SDM. Please refer to +https://github.com/intel/perfmon/issues/357 for additional information. + ### EventName It is a string of characters to identify the programming of an event. From a64fe0156cb239faabe4bc207db3b9d2dcc07cc8 Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Fri, 19 Dec 2025 13:34:23 -0700 Subject: [PATCH 2/2] readme: Fixup event name and MSR --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 26db623d..de2a5d89 100644 --- a/README.md +++ b/README.md @@ -247,7 +247,7 @@ This is useful in event-based sampling. This field gives a recommended default o workload or tool preference. ### MSRIndex -Additional MSRs may be required for programming certain events. This field gives the address of such MSRS. +Additional MSRs may be required for programming certain events. This field gives the address of such MSRs. Examples include: * 0x3F6: MSR_PEBS_LD_LAT - used to configure the Load Latency Performance Monitoring Facility * 0x1A6/0x1A7: MSR_OFFCORE_RSP_X - used to configure the offcore response events @@ -263,7 +263,7 @@ Applies to processors that support both precise and non-precise events in **Proc 0. The event cannot be programmed to collect a PEBS record. 1. The event may be programmed to collect a PEBS record, but caution is advised. For instance, PEBS collection of this event may consume limited PEBS resources whereas interrupt-based sampling may be sufficient for the usage model. 2. The event may be programmed to collect a PEBS record, and due to the nature of the event, PEBS collection may be preferred. For instance, -PEBS collection of Goldmont's `HW_INTERUPTS.RECIEVED` event is recommended because the hardware interrupt being counted may lead to the masking of +PEBS collection of Goldmont's `HW_INTERRUPTS.RECEIVED` event is recommended because the hardware interrupt being counted may lead to the masking of interrupts which would interfere with interrupt-based sampling. 3. The event must be programmed to collect a PEBS record.