diff --git a/.github/workflows/build_test.yaml b/.github/workflows/build_test.yaml
new file mode 100644
index 0000000000000..04dae68b12cc8
--- /dev/null
+++ b/.github/workflows/build_test.yaml
@@ -0,0 +1,198 @@
+---
+#------------------------------------------------------------------------------
+# QEMU OpenTitan CI
+#
+# Copyright (c) 2023-2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache License 2.0
+#------------------------------------------------------------------------------
+
+name: Build & Test QEMU OT
+on:
+  - pull_request
+  - workflow_dispatch
+jobs:
+  build-clang:
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Install deps
+        run: |
+          wget -qO- https://apt.llvm.org/llvm-snapshot.gpg.key |
+            sudo tee /etc/apt/trusted.gpg.d/apt.llvm.org.asc &&
+          sudo add-apt-repository "deb http://apt.llvm.org/noble/ llvm-toolchain-noble-21 main" &&
+          sudo apt-get update &&
+          sudo apt-get install -y git make pkg-config clang-21 cmake ninja-build python3 rust-all \
+            libpixman-1-dev libglib2.0-dev
+      - name: Check out QEMU
+        uses: actions/checkout@v4
+      - name: Configure
+        run: |
+          rm -rf build-clang
+          git clean -dffx subprojects
+          mkdir build-clang
+          (cd build-clang &&
+           ../configure --cc=clang-21 --disable-werror --disable-install-blobs \
+             --target-list=riscv32-softmmu,riscv64-softmmu)
+      - name: Build
+        run: |
+          ninja -C build-clang &&
+          ninja -C build-clang qemu-img &&
+          strip build-clang/qemu-system-riscv32
+      - name: Create minimal test binaries
+        run: |
+          scripts/opentitan/swexit.py -t ibexdemo -b 0x0 -o build-clang/exit_id.bin
+          scripts/opentitan/swexit.py -t earlgrey -b 0x80 -o build-clang/exit_eg.bin
+          scripts/opentitan/swexit.py -t darjeeling -b 0x80 -o build-clang/exit_dj.bin
+      - name: Upload QEMU binary artifacts
+        uses: actions/upload-artifact@v4
+        with:
+          name: qemu-bin
+          path: |
+            build-clang/qemu-system-riscv32
+            build-clang/exit_*.bin
+            docs/config/opentitan/*.cfg
+          retention-days: 1
+      - name: Pack source artifacts
+        # GitHub takes ages to retrieve each source file, so pack them
+        run: |
+          tar czf qemu-src-artifact.tar.gz \
+            subprojects/libtomcrypt/src/headers/*.h \
+            build-clang/*.h \
+            build-clang/qapi/*.h \
+            build-clang/trace/*.h \
+            build-clang/config.status \
+            build-clang/compile_commands.json
+      - name: Upload QEMU source artifacts
+        uses: actions/upload-artifact@v4
+        with:
+          name: qemu-src
+          path: qemu-src-artifact.tar.gz
+          retention-days: 1
+
+  format:
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Install tools
+        run: |
+          wget -qO- https://apt.llvm.org/llvm-snapshot.gpg.key |
+            sudo tee /etc/apt/trusted.gpg.d/apt.llvm.org.asc &&
+          sudo add-apt-repository "deb http://apt.llvm.org/noble/ llvm-toolchain-noble-21 main" &&
+          sudo apt-get update &&
+          sudo apt-get install -y clang-format-21
+      - name: Check out QEMU
+        uses: actions/checkout@v4
+      - name: Check C code format
+        run: |
+          scripts/opentitan/ot-format.sh --ci --Werror --dry-run
+
+  lint-python:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check out QEMU
+        uses: actions/checkout@v4
+      - name: Install tools
+        run: |
+          sudo apt-get update &&
+          sudo apt-get install -y python3-pip
+          # ubuntu "latest" is too old to require --break-system-packages ...
+          pip3 install -r scripts/opentitan/requirements.txt
+      - name: Lint Python code
+        run: |
+          flake8 --config scripts/opentitan/.flake8 scripts/opentitan/*.py \
+          python/qemu/jtagtools python/qemu/ot
+          pylint --rcfile scripts/opentitan/.pylintrc -d 'duplicate-code' -d 'fixme' \
+          scripts/opentitan/*.py python/qemu/jtagtools python/qemu/ot
+
+  lint-clang:
+    runs-on: ubuntu-24.04
+    needs: build-clang
+    steps:
+      - name: Install tools
+        run: |
+          wget -qO- https://apt.llvm.org/llvm-snapshot.gpg.key |
+            sudo tee /etc/apt/trusted.gpg.d/apt.llvm.org.asc &&
+          sudo add-apt-repository "deb http://apt.llvm.org/noble/ llvm-toolchain-noble-21 main" &&
+          sudo apt-get update &&
+          sudo apt-get install -y clang-tidy-21 libglib2.0-dev
+      - name: Check out QEMU
+        uses: actions/checkout@v4
+      - name: Download QEMU source artifacts
+        uses: actions/download-artifact@v4
+        with:
+          name: qemu-src
+      - name: Unpack source artifacts
+        run: |
+          tar xzf qemu-src-artifact.tar.gz
+      - name: Clang tidy
+        # Expect many warnings/errors (accounted but not reported) from included QEMU files
+        run: |
+          scripts/opentitan/ot-tidy.py --build-dir build-clang --ci-files -j
+
+  lint-commits:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          fetch-depth: 0 # Don't shallow clone, we need to see all commits.
+      - name: Lint commits
+        run: ./scripts/opentitan/lint-commits.sh "origin/${{ github.base_ref }}"
+
+  test-clang:
+    runs-on: ubuntu-24.04
+    needs: build-clang
+    steps:
+      - name: Install tools
+        run: |
+          sudo apt-get update &&
+          sudo apt-get install -y libpixman-1-0 libglib2.0-dev
+      - name: Download QEMU binary artifacts
+        uses: actions/download-artifact@v4
+        with:
+          name: qemu-bin
+      - name: Check machine availability
+        run: |
+          chmod +x build-clang/qemu-system-riscv32 &&
+          build-clang/qemu-system-riscv32 -M help | grep ibexdemo &&
+          build-clang/qemu-system-riscv32 -M help | grep ot-earlgrey &&
+          build-clang/qemu-system-riscv32 -M help | grep ot-darjeeling
+      - name: Check IbexDemo VM execution
+        run: |
+          timeout -s KILL 4 build-clang/qemu-system-riscv32 -M ibexdemo -nographic \
+            -device loader,addr=0x100080,file=build-clang/exit_id.bin -d in_asm,int
+      - name: Check EarlGrey VM execution
+        run: |
+          timeout -s KILL 4 build-clang/qemu-system-riscv32 -M ot-earlgrey,no_epmp_cfg=true -nographic \
+            -object ot-rom_img,id=rom,file=build-clang/exit_eg.bin -global ot-ibex_wrapper.lc-ignore=on \
+            -readconfig docs/config/opentitan/earlgrey.cfg -d in_asm,int \
+            -trace ot_ibex_wrapper_exit
+      - name: Check Darjeeling VM execution
+        run: |
+          timeout -s KILL 4 build-clang/qemu-system-riscv32 -M ot-darjeeling,no_epmp_cfg=true -nographic \
+            -object ot-rom_img,id=rom0,file=build-clang/exit_dj.bin -global ot-ibex_wrapper.lc-ignore=on \
+            -readconfig docs/config/opentitan/darjeeling.cfg -d in_asm,int \
+            -trace ot_ibex_wrapper_exit
+
+  build-gcc:
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Install tools
+        run: |
+          wget -qO- https://apt.llvm.org/llvm-snapshot.gpg.key |
+          sudo tee /etc/apt/trusted.gpg.d/apt.llvm.org.asc &&
+          sudo add-apt-repository "deb http://apt.llvm.org/noble/ llvm-toolchain-noble-21 main" &&
+          sudo apt-get update &&
+          sudo apt-get install -y git make pkg-config gcc cmake ninja-build python3 rust-all \
+            libpixman-1-dev libglib2.0-dev
+      - name: Check out QEMU
+        uses: actions/checkout@v4
+      - name: Configure
+        run: |
+          rm -rf build-gcc
+          git clean -dffx subprojects
+          mkdir build-gcc
+          (cd build-gcc &&
+           ../configure --cc=gcc --enable-werror --disable-install-blobs \
+             --target-list=riscv32-softmmu,riscv64-softmmu)
+      - name: Build
+        run: |
+          ninja -C build-gcc
diff --git a/.github/workflows/ci_regression.yml b/.github/workflows/ci_regression.yml
new file mode 100644
index 0000000000000..2a236b8318ddc
--- /dev/null
+++ b/.github/workflows/ci_regression.yml
@@ -0,0 +1,51 @@
+#------------------------------------------------------------------------------
+# OpenTitan CI regression runner
+#
+# Copyright (c) 2025 lowRISC CIC
+# SPDX-License-Identifier: Apache License 2.0
+#------------------------------------------------------------------------------
+
+name: OT Tests
+on:
+  pull_request:
+  workflow_dispatch:
+    inputs:
+      opentitan_repo:
+        description: OpenTitan repository to be checked out
+        required: true
+        default: lowRISC/opentitan
+        type: string
+      opentitan_ref:
+        description: Branch, tag, or commit ref from OpenTitan to test
+        required: true
+        default: earlgrey_1.0.0
+        type: string
+
+jobs:
+  earlgrey_rom_with_fake_keys:
+    name: ROM
+    uses: ./.github/workflows/eg_regression.yml
+    secrets: inherit
+    with:
+      exec_env: sim_qemu_rom_with_fake_keys
+      opentitan_repo: ${{ inputs.opentitan_repo || 'lowRISC/opentitan' }}
+      opentitan_ref: ${{ inputs.opentitan_ref || 'earlgrey_1.0.0' }}
+
+  earlgrey_rom_ext:
+    name: ROM_EXT
+    uses: ./.github/workflows/eg_regression.yml
+    secrets: inherit
+    with:
+      exec_env: sim_qemu_rom_ext
+      test_timeout: 150
+      opentitan_repo: ${{ inputs.opentitan_repo || 'lowRISC/opentitan' }}
+      opentitan_ref: ${{ inputs.opentitan_ref || 'earlgrey_1.0.0' }}
+
+  earlgrey_sival_rom_ext:
+    name: SiVal ROM_EXT
+    uses: ./.github/workflows/eg_regression.yml
+    secrets: inherit
+    with:
+      exec_env: sim_qemu_sival_rom_ext
+      opentitan_repo: ${{ inputs.opentitan_repo || 'lowRISC/opentitan' }}
+      opentitan_ref: ${{ inputs.opentitan_ref || 'earlgrey_1.0.0' }}
diff --git a/.github/workflows/create_release.yml b/.github/workflows/create_release.yml
new file mode 100644
index 0000000000000..2091ed9319f0d
--- /dev/null
+++ b/.github/workflows/create_release.yml
@@ -0,0 +1,51 @@
+name: Create Release
+on:
+  workflow_dispatch:
+    inputs:
+      release_tag:
+        required: true
+        type: string
+
+jobs:
+  release:
+    permissions:
+      # Necessary permissions to create a release.
+      contents: write
+    env:
+      BUILD_DIR: build
+      BRANCH_NAME: ${{ github.event.repository.default_branch }}
+      RELEASE_BIN_ARCHIVE: qemu-ot-earlgrey-${{ inputs.release_tag }}-x86_64-unknown-linux-gnu.tar.gz
+    runs-on: ubuntu-22.04
+    timeout-minutes: 10
+    steps:
+      - name: Check out repository
+        uses: actions/checkout@v3
+      # Update the package index, then install all dependencies listed in
+      # the various apt-requirements.txt files in the project.
+      - name: Install Dependencies
+        run: |
+          sudo apt-get update
+          sudo apt-get install -y ninja-build libpixman-1-dev
+      - name: Configure
+        run: |
+          mkdir "$BUILD_DIR"
+          cd "$BUILD_DIR"
+          ../configure --target-list=riscv32-softmmu --without-default-features --enable-tcg \
+            --enable-tools --enable-trace-backends=log
+      - name: Build
+        run: |
+          cd "$BUILD_DIR"
+          ninja
+          ninja qemu-img
+      - name: Create binary archive
+        run: |
+          ./scripts/opentitan/make_release.sh "$RELEASE_BIN_ARCHIVE" . "$BUILD_DIR"
+      - name: Create release
+        env:
+          GH_TOKEN: ${{ github.token }}
+        run: |
+          gh release create \
+            --target "$BRANCH_NAME" \
+            ${{ inputs.release_tag }} \
+            --generate-notes \
+            "$RELEASE_BIN_ARCHIVE#QEMU system emulator"
diff --git a/.github/workflows/eg_regression.yml b/.github/workflows/eg_regression.yml
new file mode 100644
index 0000000000000..0080870ede90f
--- /dev/null
+++ b/.github/workflows/eg_regression.yml
@@ -0,0 +1,78 @@
+#------------------------------------------------------------------------------
+# OpenTitan regression run definition
+#
+# Copyright (c) 2025 lowRISC CIC
+# SPDX-License-Identifier: Apache License 2.0
+#------------------------------------------------------------------------------
+
+name: OpenTitan Regression
+on:
+  workflow_call:
+    inputs:
+      exec_env:
+        description: OpenTitan QEMU execution environment to test
+        required: true
+        default: qemu  # Default tag, captures all QEMU exec envs in OpenTitan
+        type: string
+      test_timeout:
+        description: The maximum timeout in seconds to use per executed test
+        required: false
+        type: string
+      opentitan_repo:
+        description: OpenTitan repository to be checked out
+        required: true
+        default: lowRISC/opentitan
+        type: string
+      opentitan_ref:
+        description: Branch, tag, or commit ref from OpenTitan to test
+        required: true
+        default: earlgrey_1.0.0
+        type: string
+
+jobs:
+  regression:
+    name: EG Regression
+    runs-on: ubuntu-22.04
+    steps:
+      - name: Checkout OpenTitan
+        uses: actions/checkout@v5
+        with:
+          repository: ${{ inputs.opentitan_repo || 'lowRISC/opentitan' }}
+          ref: ${{ inputs.opentitan_ref || 'earlgrey_1.0.0' }}
+          fetch-depth: 0 # fetch all commits to avoid bug with bitstream rule
+
+      - name: Prepare OpenTitan environment
+        uses: ./.github/actions/prepare-env
+
+      - name: Checkout QEMU
+        uses: actions/checkout@v5
+        with:
+          path: qemu
+
+      - name: Build QEMU
+        working-directory: qemu
+        run: |
+          ./configure \
+            --target-list=riscv32-softmmu \
+            --without-default-features \
+            --enable-tcg \
+            --disable-tools \
+            --enable-trace-backends=log
+
+          ninja -C build qemu-system-riscv32
+
+      - name: Run OpenTitan regressions
+        shell: bash
+        run: |
+          set -o pipefail
+          ./qemu/scripts/opentitan/run-bazel-tests.sh ./ qemu \
+            ${{ inputs.exec_env }} \
+            ${{ inputs.test_timeout }} \
+            | tee ${{ inputs.exec_env }}_test_results.txt
+
+      - name: Upload Bazel test results
+        if: always()
+        uses: actions/upload-artifact@v4
+        with:
+          name: ${{ inputs.exec_env }}-bazel-test-results
+          path: ${{ inputs.exec_env }}_test_results.txt
diff --git a/.gitignore b/.gitignore
index 61fa39967b542..f23f42e170371 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,7 +6,6 @@
 .sdk
 .stgit-*
 .git-submodule-status
-.clang-format
 .gdb_history
 cscope.*
 tags
@@ -20,3 +19,11 @@ GTAGS
 *.swp
 *.patch
 *.gcov
+subprojects/*-*/
+subprojects/libtomcrypt/
+subprojects/packagecache/
+!subprojects/packagefiles/**/*.patch
+hw/opentitan/otbn/otbn/Cargo.lock
+hw/opentitan/otbn/otbn/target/
+.clangd
+.zed
diff --git a/.gitlab-ci.d/opentitan/build.yml b/.gitlab-ci.d/opentitan/build.yml
new file mode 100644
index 0000000000000..48c69f1f7f6b7
--- /dev/null
+++ b/.gitlab-ci.d/opentitan/build.yml
@@ -0,0 +1,75 @@
+#------------------------------------------------------------------------------
+# QEMU OpenTitan CI
+#------------------------------------------------------------------------------
+
+build-clang:
+  tags:
+    - qemu_ot
+  stage: build
+  # build QEMU for OT platforms, ensure subprojects are cleaned up first
+  # store generated header files and ninja command file as artifacts, which are
+  # required to run the clang-tidy stage
+  # libvhost-user.c generates sign-compare warnings with clang, so disable
+  # warning-as-error
+  # the alternative would be to build here with GCC, then rebuild everything
+  # with clang in clang-tidy stage, as meson generates different, incompatible
+  # warning list between GCC and clang...
+  script:
+    - rm -rf build
+    - git clean -dffx subprojects
+    - mkdir build
+    - cd build
+    - ../configure --cc=clang-21 --disable-werror $QEMU_BUILD_OPTS
+        --target-list=riscv32-softmmu,riscv64-softmmu,x86_64-linux-user
+    - ninja
+    - ninja qemu-img
+    - strip qemu-system-riscv32 qemu-img
+    - QEMU_DIR="$(cd .. && pwd -P)"; cat compile_commands.json |
+        sed -E 's,'"$QEMU_DIR"',@QEMU_DIR@,g' > compile_commands.json.tpl
+    - ../scripts/opentitan/swexit.py -t ibexdemo -b 0x0 -o exit_id.bin
+    - ../scripts/opentitan/swexit.py -t earlgrey -b 0x80 -o exit_eg.bin
+    - ../scripts/opentitan/swexit.py -t darjeeling -b 0x80 -o exit_dj.bin
+  artifacts:
+    public: false
+    expire_in: 1 hour
+    name: "qemu-ot"
+    paths:
+      - subprojects/libtomcrypt/src/headers/*.h
+      - build/*.h
+      - build/qapi/*.h
+      - build/trace/*.h
+      - build/config.status
+      - build/compile_commands.json.tpl
+      - build/qemu-system-riscv32
+      - build/qemu-img
+      - build/exit_*.bin
+
+build-gcc:
+  tags:
+    - qemu_ot
+  stage: build
+  # build QEMU for OT platforms, ensure subprojects are cleaned up first
+  # build with GCC may need different warnings
+  script:
+    - rm -rf build-gcc
+    - mkdir build-gcc
+    - cd build-gcc
+    - ../configure --cc=gcc $QEMU_BUILD_OPTS --target-list=riscv32-softmmu,riscv64-softmmu
+    - ninja
+
+format:
+  tags:
+    - qemu_ot
+  stage: build
+  script:
+    - scripts/opentitan/ot-format.sh --ci --Werror --dry-run
+
+tidy:
+  tags:
+    - qemu_ot
+  stage: build
+  needs: ["build-clang"]
+  script:
+    - QEMU_DIR="$(pwd -P)"; cat build/compile_commands.json.tpl |
+        sed -E 's,@QEMU_DIR@,'"$QEMU_DIR"',g' > build/compile_commands.json
+    - scripts/opentitan/ot-tidy.py --build-dir build --ci-files -j
diff --git a/.gitlab-ci.d/opentitan/ot-bmtests.yml b/.gitlab-ci.d/opentitan/ot-bmtests.yml
new file mode 100644
index 0000000000000..9134c53b0925a
--- /dev/null
+++ b/.gitlab-ci.d/opentitan/ot-bmtests.yml
@@ -0,0 +1,63 @@
+# Baremetal Tests for Earlgrey & Darjeeling
+
+baremetal-eg-tests:
+  tags:
+    - qemu_ot
+  stage: test
+  needs:
+    - "build-clang"
+    - project: rv/sandbox/rot/baremetal_test
+      job: build-eg
+      ref: $BAREMETAL_REF
+      artifacts: true
+  variables:
+    BASEDIR: bmtests/eg
+    CI_EXEC: 1
+    DISABLE_FLAKY: 1
+  script:
+    - python3 -m virtualenv .venv
+    - . .venv/bin/activate
+    - pip3 install -r scripts/opentitan/requirements.txt
+    - rm -rf ${BASEDIR}
+    - mkdir -p ${BASEDIR}
+    - zstd -d --stdout ot-eg-bmtest.tar.zst | tar xf - -C ${BASEDIR}
+    - find ${BASEDIR}
+    - scripts/opentitan/pyot.py -vv -c ${BASEDIR}/data/ot-earlgrey/qemu/pyot.hjson
+         -w ot-earlgrey.csv -R -T 3
+  artifacts:
+    public: false
+    expire_in: 1 year
+    name: "bm-ot-earlgrey"
+    paths:
+      - ot-earlgrey.csv
+
+baremetal-dj-tests:
+  tags:
+    - qemu_ot
+  stage: test
+  needs:
+    - "build-clang"
+    - project: rv/sandbox/rot/baremetal_test
+      job: build-dj
+      ref: $BAREMETAL_REF
+      artifacts: true
+  variables:
+    BASEDIR: bmtests/dj
+    CI_EXEC: 1
+    DISABLE_FLAKY: 1
+  script:
+    - python3 -m virtualenv .venv
+    - . .venv/bin/activate
+    - pip3 install -r scripts/opentitan/requirements.txt
+    - rm -rf ${BASEDIR}
+    - mkdir -p ${BASEDIR}
+    - zstd -d --stdout ot-dj-bmtest.tar.zst | tar xf - -C ${BASEDIR}
+    - find ${BASEDIR}
+    - scripts/opentitan/pyot.py -vv -c ${BASEDIR}/data/ot-darjeeling/qemu/pyot.hjson
+         -w ot-darjeeling.csv -R -T 3
+  artifacts:
+    public: false
+    expire_in: 1 year
+    name: "bm-ot-darjeeling"
+    paths:
+      - ot-darjeeling.csv
diff --git a/.gitlab-ci.d/opentitan/ot-smoke.yml b/.gitlab-ci.d/opentitan/ot-smoke.yml
new file mode 100644
index 0000000000000..ed5a82c9fd409
--- /dev/null
+++ b/.gitlab-ci.d/opentitan/ot-smoke.yml
@@ -0,0 +1,20 @@
+smoke-tests-ot:
+  tags:
+    - qemu_ot
+  stage: test
+  needs: ["build-clang"]
+  script:
+    - build/qemu-system-riscv32 -M help | grep ibexdemo
+    - build/qemu-system-riscv32 -M help | grep ot-earlgrey
+    - timeout -s KILL 4 build/qemu-system-riscv32 -M ibexdemo -nographic
+        -device loader,addr=0x100080,file=build/exit_id.bin -d in_asm,int
+    - timeout -s KILL 4 build/qemu-system-riscv32 -M ot-earlgrey,no_epmp_cfg=true
+        -object ot-rom_img,id=rom,file=build/exit_eg.bin -d in_asm,int
+        -nographic -global ot-ibex_wrapper.lc-ignore=on
+        -readconfig docs/config/opentitan/earlgrey.cfg
+        -trace ot_ibex_wrapper_exit
+    - timeout -s KILL 4 build/qemu-system-riscv32 -M ot-darjeeling,no_epmp_cfg=true
+        -object ot-rom_img,id=rom0,file=build/exit_dj.bin -d in_asm,int
+        -nographic -global ot-ibex_wrapper.lc-ignore=on
+        -readconfig docs/config/opentitan/darjeeling.cfg
+        -trace ot_ibex_wrapper_exit
diff --git a/.gitlab-ci.d/opentitan/python-ot.yml b/.gitlab-ci.d/opentitan/python-ot.yml
new file mode 100644
index 0000000000000..fb0cc173e82c3
--- /dev/null
+++ b/.gitlab-ci.d/opentitan/python-ot.yml
@@ -0,0 +1,14 @@
+python-ot:
+  tags:
+    - qemu_ot
+  stage: build
+  script:
+    # disable duplicate code as all front end are tested at once (false positive)
+    # disable fixme ("# TODO" comments)
+    - python3 -m virtualenv .venv
+    - . .venv/bin/activate
+    - pip3 install -r scripts/opentitan/requirements.txt
+    - pylint --rcfile scripts/opentitan/.pylintrc -d 'duplicate-code' -d 'fixme'
+      scripts/opentitan/*.py python/qemu/jtagtools python/qemu/ot
+    - flake8 --config scripts/opentitan/.flake8
+      scripts/opentitan/*.py python/qemu/jtagtools python/qemu/ot
diff --git a/.gitlab-ci.d/opentitan/qemu-ot.yml b/.gitlab-ci.d/opentitan/qemu-ot.yml
new file mode 100644
index 0000000000000..7e2886b7ac24c
--- /dev/null
+++ b/.gitlab-ci.d/opentitan/qemu-ot.yml
@@ -0,0 +1,9 @@
+variables:
+  BAREMETAL_REF: "ot-251125-1"
+  QEMU_BUILD_OPTS: "--disable-install-blobs"
+
+include:
+  - local: '/.gitlab-ci.d/opentitan/build.yml'
+  - local: '/.gitlab-ci.d/opentitan/python-ot.yml'
+  - local: '/.gitlab-ci.d/opentitan/ot-smoke.yml'
+  - local: '/.gitlab-ci.d/opentitan/ot-bmtests.yml'
diff --git a/MAINTAINERS b/MAINTAINERS
index 63e9ba521bcc5..e714850420e16 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1680,14 +1680,41 @@ F: pc-bios/vof*
 
 RISC-V Machines
 ---------------
+
+EarlGrey and Darjeeling OpenTitan platforms
+M: Emmanuel Blot <eblot@rivosinc.com>
+M: Loïc Lefort <loic@rivosinc.com>
+S: Supported
+F: hw/opentitan/*
+F: include/hw/opentitan/*
+F: scripts/opentitan/*
+F: hw/riscv/ot_darjeeling.c
+F: hw/riscv/ot_earlgrey.c
+F: include/hw/riscv/ot_darjeeling.h
+F: include/hw/riscv/ot_earlgrey.h
+
+Ibex platforms and utilities
+M: Emmanuel Blot <eblot@rivosinc.com>
+M: Loïc Lefort <loic@rivosinc.com>
+S: Supported
+F: hw/riscv/ibex_common.c
+F: include/hw/riscv/ibex_common.h
+F: include/hw/riscv/ibex_irq.h
+F: hw/ibexdemo/*
+F: include/hw/ibexdemo/*
+
 OpenTitan
 M: Alistair Francis <Alistair.Francis@wdc.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: hw/riscv/opentitan.c
-F: hw/*/ibex_*.c
+F: hw/ssi/ibex_spi_host.c
+F: hw/timer/ibex_timer.c
+F: hw/char/ibex_uart.c
 F: include/hw/riscv/opentitan.h
-F: include/hw/*/ibex_*.h
+F: include/hw/ssi/ibex_spi_host.h
+F: include/hw/timer/ibex_timer.h
+F: include/hw/char/ibex_uart.h
 
 Microchip PolarFire SoC Icicle Kit
 L: qemu-riscv@nongnu.org
diff --git a/README.md b/README.md
new file mode 100644
index 0000000000000..11e299d9ce13a
--- /dev/null
+++ b/README.md
@@ -0,0 +1,19 @@
+# QEMU OpenTitan README
+
+[![.github/workflows/build_test.yaml](https://github.com/lowRISC/qemu/actions/workflows/build_test.yaml/badge.svg?branch=ot-10.1.0)](https://github.com/lowRISC/qemu/actions/workflows/build_test.yaml)
+
+QEMU is a generic and open source machine & userspace emulator and virtualizer.
+
+QEMU is capable of emulating a complete machine in software without any need for hardware
+virtualization support. By using dynamic translation, it achieves very good performance.
+
+This branch contains a fork of QEMU 10.1.0 dedicated to support lowRISC Ibex platforms:
+  * [OpenTitan](https://opentitan.org) [EarlGrey](docs/opentitan/ot_earlgrey.md), based on
+    [1.0.0](https://github.com/lowRISC/opentitan/tree/earlgrey_1.0.0).
+  * [OpenTitan](https://opentitan.org) [Darjeeling](docs/opentitan/ot_darjeeling.md), based on
+    [development version](https://github.com/lowRISC/opentitan/tree/master).
+  * [lowRISC](https://github.com/lowRISC/ibex-demo-system) [IbexDemo](docs/opentitan/ibexdemo.md).
+
+See [installation instructions](docs/opentitan/index.md)
+
+See also original [QEMU README file](README_QEMU.rst)
diff --git a/README.rst b/README_QEMU.rst
similarity index 100%
rename from README.rst
rename to README_QEMU.rst
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 7c20d9db122e5..2db0decc25d61 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -653,6 +653,10 @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
 static inline bool cpu_handle_halt(CPUState *cpu)
 {
 #ifndef CONFIG_USER_ONLY
+    if (unlikely(cpu->disabled)) {
+        return true;
+    }
+
     if (cpu->halted) {
         const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
         bool leave_halt = tcg_ops->cpu_exec_halt(cpu);
@@ -703,6 +707,10 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
         *ret = cpu->exception_index;
         if (*ret == EXCP_DEBUG) {
             cpu_handle_debug_exception(cpu);
+            if (cpu->exception_index < 0) {
+                /* the handler has cleared the exception */
+                return false;
+            }
         }
         cpu->exception_index = -1;
         return true;
@@ -998,6 +1006,13 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
                 tb_add_jump(last_tb, tb_exit, tb);
             }
 
+            if (unlikely((s.cflags != -1) && (s.cflags & CF_SINGLE_STEP))) {
+                CPUClass *cc = cpu->cc;
+                if (cc->debug_enable_singlestep) {
+                    cc->debug_enable_singlestep(cpu, s.pc);
+                }
+            }
+
             cpu_loop_exec_tb(cpu, tb, s.pc, &last_tb, &tb_exit);
 
             /* Try to align the host and virtual clocks
diff --git a/configs/devices/riscv32-softmmu/default.mak b/configs/devices/riscv32-softmmu/default.mak
index c2cd86ce05f02..8122e3247503f 100644
--- a/configs/devices/riscv32-softmmu/default.mak
+++ b/configs/devices/riscv32-softmmu/default.mak
@@ -10,3 +10,6 @@
 # CONFIG_SIFIVE_U=n
 # CONFIG_RISCV_VIRT=n
 # CONFIG_OPENTITAN=n
+# CONFIG_OT_DARJEELING=n
+# CONFIG_OT_EARLGREY=n
+# CONFIG_IBEXDEMO=n
diff --git a/disas/meson.build b/disas/meson.build
index bbfa11978352e..d549b9b072ebf 100644
--- a/disas/meson.build
+++ b/disas/meson.build
@@ -7,7 +7,8 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))
 common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(
     'riscv.c',
     'riscv-xthead.c',
-    'riscv-xventana.c'
+    'riscv-xventana.c',
+    'riscv-zbr.c'
 ))
 common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
 common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
diff --git a/disas/riscv-zbr.c b/disas/riscv-zbr.c
new file mode 100644
index 0000000000000..1f03752ec3518
--- /dev/null
+++ b/disas/riscv-zbr.c
@@ -0,0 +1,78 @@
+/*
+ * QEMU RISC-V Disassembler for Zbr
+ *
+ * Copyright (c) 2023 Rivos Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+
+#include "disas/riscv.h"
+#include "disas/riscv-zbr.h"
+
+typedef enum {
+    /* 0 is reserved for rv_op_illegal. */
+    rv_op_crc32_b = 1,
+    rv_op_crc32_h = 2,
+    rv_op_crc32_w = 3,
+    rv_op_crc32_d = 4,
+    rv_op_crc32c_b = 5,
+    rv_op_crc32c_h = 6,
+    rv_op_crc32c_w = 7,
+    rv_op_crc32c_d = 8,
+} rv_zbr_op;
+
+const rv_opcode_data rv_zbr_opcode_data[] = {
+    { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
+    { "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+};
+
+void decode_zbr(rv_decode *dec, rv_isa isa)
+{
+    rv_inst inst = dec->inst;
+    rv_opcode op = rv_op_illegal;
+
+    switch ((inst >> 0) & 0b1111111) {
+    case 0b0010011:
+        switch ((inst >> 12) & 0b111) {
+        case 0b001:
+            switch ((inst >> 20 & 0b111111111111)) {
+            case 0b011000010000:
+                op = rv_op_crc32_b;
+                break;
+            case 0b011000010001:
+                op = rv_op_crc32_h;
+                break;
+            case 0b011000010010:
+                op = rv_op_crc32_w;
+                break;
+            case 0b011000010011:
+                op = rv_op_crc32_d;
+                break;
+            case 0b011000011000:
+                op = rv_op_crc32c_b;
+                break;
+            case 0b011000011001:
+                op = rv_op_crc32c_h;
+                break;
+            case 0b011000011010:
+                op = rv_op_crc32c_w;
+                break;
+            case 0b011000011011:
+                op = rv_op_crc32c_d;
+                break;
+            }
+            break;
+        }
+        break;
+    }
+    dec->op = op;
+}
diff --git a/disas/riscv-zbr.h b/disas/riscv-zbr.h
new file mode 100644
index 0000000000000..366040ed53c23
--- /dev/null
+++ b/disas/riscv-zbr.h
@@ -0,0 +1,18 @@
+/*
+ * QEMU RISC-V Disassembler for Zbr
+ *
+ * Copyright (c) 2023 Rivos Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef DISAS_RISCV_ZBR_H
+#define DISAS_RISCV_ZBR_H
+
+#include "disas/riscv.h"
+
+extern const rv_opcode_data rv_zbr_opcode_data[];
+
+void decode_zbr(rv_decode *, rv_isa);
+
+#endif /* DISAS_RISCV_ZBR_H */
diff --git a/disas/riscv.c b/disas/riscv.c
index 85cd2a9c2aefe..a6185a1017a43 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -27,6 +27,9 @@
 #include "disas/riscv-xthead.h"
 #include "disas/riscv-xventana.h"
 
+/* Extensions that are not yet upstream */
+#include "disas/riscv-zbr.h"
+
 typedef enum {
     /* 0 is reserved for rv_op_illegal. */
     rv_op_lui = 1,
@@ -5434,6 +5437,9 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
         { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
         { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
         { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
+
+        /* Instructions that are not yet upstream */
+        { has_zbr_p, rv_zbr_opcode_data, decode_zbr },
     };
 
     for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
@@ -5529,3 +5535,14 @@ int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info)
 {
     return print_insn_riscv(memaddr, info, rv128);
 }
+
+const char *get_riscv_debug_reg_name(int regno)
+{
+    switch (regno) {
+        case 0x0000 ... 0x0fff: return csr_name(regno);
+        case 0x1000 ... 0x101f: return rv_ireg_name_sym[regno-0x1000];
+        case 0x1020 ... 0x103f: return rv_freg_name_sym[regno-0x1020];
+        /* TODO: need to add vector regs (not part of 0.13.2 debug spec) */
+        default: return NULL;
+    }
+}
diff --git a/docs/config/opentitan/darjeeling.cfg b/docs/config/opentitan/darjeeling.cfg
new file mode 100644
index 0000000000000..e7b9802d8b9e3
--- /dev/null
+++ b/docs/config/opentitan/darjeeling.cfg
@@ -0,0 +1,69 @@
+# Generated from OpenTitan commit: c5507b4cdc
+
+[ot_device "ot-rom_ctrl.rom0"]
+  key = "30ae84156d37cc68063276f9e85faee1"
+  nonce = "0a553e45bab60fd5"
+
+[ot_device "ot-rom_ctrl.rom1"]
+  key = "9649127ec56c7b0e9645bf231b5b37b8"
+  nonce = "29ae80f5b440dc77"
+
+[ot_device "ot-otp-dj"]
+  digest_const = "09c87e42745452d8a010a9f0ef3221d5"
+  digest_iv = "a0806e02a1fba55b"
+  inv_default_part_15 = "58b183f3d37975b4a9524de21084a9d64bba835c10b5e29043022273f7afbf68e78e601c1704c34a6dfd043e96e1ef76d15c0798ef406091d605165216fd3f856fb88c3b4fd535bd"
+  inv_default_part_16 = "00000000696900001f2a6bd606d55f72"
+  inv_default_part_17 = "1fb5110b0618183cbf722f142ef9facfb5742826d2ce8d8bb874ddd1dbca5322ddf650f1a00008ee0000000000000000"
+  inv_default_part_18 = "2552a6aa7830346413591b15ed2553188688686a7d26f94a0000000000000000"
+  inv_default_part_19 = "eff32b59c0a86294d9767fdcb47456994c8fd64171edb20835aef32cf20b0c620e9af6c53593daec8e3caa2e495a897602e2904aa8a7090712cf9a372be9c2b9c1fbff3b68368c5afedcdee44f5d8d84276d9c42b4b5c6539c73a2705a4682baa1885457797963c3980bff063fc8bc645a7f3e2373a78aa20000000000000000"
+  inv_default_part_20 = "9c47222c695c123916e90f1bdde834c31d3eef689e998822eddeb20732f666faba37deb973d827e00000000000000000"
+  inv_default_part_21 = "6149b9ff4f5979607aead63a44f896431df745a52c5af5fdf86d2ce9fa1041c43f145a8bf5be7640d7aaf2481067180fd08f694a5f790581d728bd369d03f8087a60a7f8ed956442c9cff0f99e594c7307f376e7b2b2ff8c"
+  scrmbl_key = "d6780626a12b5904a9b37439f8177d19d04d3fad040ed02909a9ea4b5429b9e6"
+  secret0_scramble_key = "688a9a20b68e0d35660e593f560f6866"
+  secret1_scramble_key = "a1ad90a50942397740ab78c5737a2379"
+  secret2_scramble_key = "c2ede5b25ec5514b680ccaab361c3f85"
+  secret3_scramble_key = "8e1c5cccc121a2c95d21294d190ab75c"
+  sram_const = "4dcba329ff2f7d4b8a3acdb325087fab"
+  sram_iv = "9bd623e40aec9b61"
+
+[ot_device "ot-lc_ctrl"]
+  dev = "d2fd2987e3062f6119c7560acbbe9f6f"
+  invalid = "0d20b07721f7ff507ad2b9fb9cc7ff06"
+  lc_state_first = "eebd62140286d28089f20c8f78baa23d9210b65583a165a35342d646189f81d751c346984482681b"
+  lc_state_last = "eebde6d52eb6dbd5b9f79dcf7ebfbe3fb672bff5dfe577afd36efe6f99ffe1ff73e3779ec4fa7a9b"
+  lc_trscnt_first = "ff595454ab481e0fd02144da44cc929a4149279a202522dcf2352590ec602b24d82b42968a94dec42469cc17190a4e65"
+  lc_trscnt_last = "ff59557fbb79decfd2b776fb6fcfdf9b51f9affbad277bfcfab7a7b1ef70ebafdcebd6bebadeffc7a66fff17993a7e75"
+  ownership_first = "ea846e2884d9198c4a42348a61406249"
+  ownership_last = "fecc6faaeef93dcccefef68f696f6adf"
+  production = "ffc2171a49199bb53d8e0daa8f0578db"
+  raw_unlock_token = "e4225dc332ea1fda63b4c524556ed4d4"
+  rma = "aa5f022791480b4e709e0f80976e0966"
+  soc_dbg_first = "6b36fc2c"
+  soc_dbg_last = "ebf6fc7f"
+  test_unlocked = "e4c72c47d9e15fa8ff9f82833e32c151"
+
+[ot_device "ot-keymgr_dpe"]
+  aes_seed = "9a885419a9d57e36519fa42d20efa348cb77f5089a8381b62d9717b3647e5ce0"
+  hard_output_seed = "4d57ac27843ea2a0163efeda5b24d93f97d62d99c960542f4a1f2595192e9a96"
+  kmac_seed = "796ca68aa29523d3f94f27c74acae76b3e145326741f804e3c3a3451469c6118"
+  lfsr_seed = "488f3ffa7700ec4c"
+  none_seed = "49fcb59874cddc9cbc645d9e02a96b9980911844d3c74de85e05164b829d484b"
+  otbn_seed = "fa23bc32e428ad2be2584fe8d5491fa8e7f19aaa4133ad0d2704702ae2ff9d98"
+  revision_seed = "7b416b49b114f994a969864a57c3482ab3bdcbd9fe825728f7ba40a22c9719c5"
+  soft_output_seed = "d7c160f492d0e8757631ebf752a1e5604e2d6171f5dba9ec4249052dcc7a4d58"
+
+[ot_device "ot-ast-dj"]
+  topclocks = "main:1000000000,io:1000000000,aon:62500000"
+  aonclocks = "aon"
+
+[ot_device "ot-clkmgr"]
+  topclocks = "main:16,io:16,aon:1"
+  refclock = "aon"
+  subclocks = "io_div2:io:2,io_div4:io:4,aes:main:1,hmac:main:1,kmac:main:1,otbn:main:1"
+  groups = "powerup:aon+io+io_div2+io_div4+main,trans:aes+hmac+kmac+otbn,infra:aon+io_div4+main,secure:io_div4+main,peri:aon+io_div2+io_div4,timers:aon+io_div4"
+  swcg = "peri"
+  hint = "trans"
+
+[ot_device "ot-pwrmgr"]
+  clocks = "main,io"
+
diff --git a/docs/config/opentitan/earlgrey.cfg b/docs/config/opentitan/earlgrey.cfg
new file mode 100644
index 0000000000000..0836d865872be
--- /dev/null
+++ b/docs/config/opentitan/earlgrey.cfg
@@ -0,0 +1,71 @@
+# Generated from OpenTitan commit: 011b6ea1fe
+
+[ot_device "ot-rom_ctrl"]
+  key = "663c291739ff0e7d644758fee1c58564"
+  nonce = "fee457dee82b6e06"
+
+[ot_device "ot-otp-eg"]
+  digest_const = "0e95f517cb98955b4d5a89aa9109294a"
+  digest_iv = "bead91d5fa4e0915"
+  flash_addr_const = "d60822e1faec5c7290c7f21f6224f027"
+  flash_addr_iv = "0b7474d640f8a7f5"
+  flash_data_const = "277195fc471e4b26b6641214b61d1b43"
+  flash_data_iv = "e048b657396b4b83"
+  inv_default_part_5 = "7edc64361898f6ff7023461f42b4a5b3f7f71ea9a9507acf17c456385a48b963a629408e450e8458f3cd636e3c9a1140ae2905da9b31bb7ac60dd16b888838df2737bacf95ed7bf8"
+  inv_default_part_6 = "6969690000000000f254e78568a7f4bb"
+  inv_default_part_7 = "024c5fee0f5c8bb2c3080ad0531facb5370ad4f5b61d71b62203a5595f131d71a060cae9543819be"
+  inv_default_part_8 = "31dc5b08ced196d3b50ff2274384b9dbdd0d4e5d6bd0177ec2dce29f8327c8dbca99e674d3996d4260d2a0790332d0552ab6973f142947235a0c88a3ea33571096c8ddc72428751c29709bbd80960ee0a80ddce593c569c4"
+  inv_default_part_9 = "8a1cd4f5518b4d2a1978b594ed3dcd94671685f41086d5d3f6f8a097aad0585e4d857adfdebd0d2c0ece8ed011c5bad01988d871b8d25f316e627ccc51fc79029f45333ca4988068edfed1b3f0968cd628a94cbb02adbb8c"
+  inv_default_part_10 = "be6f2b4a67801b852a4529345af1cdbf37e97ab260e717e8e3c3363a666c130154d936fd1163e401fadd9f8c0ee9d1a056a2719fc2c345a4873c594f465e723e64ba4e17c79665cccb7943e751f0059633fbb917e41db693"
+  scrmbl_key = "55d70063277642b5309a163990b966cd494444c3bcdf8087b7facd65e9654cd8"
+  secret0_scramble_key = "3ba121c5e097ddeb7768b4c666e9c3da"
+  secret1_scramble_key = "effa6d736c5eff49ae7b70f9c46e5a62"
+  secret2_scramble_key = "85a9e830bc059ba9286d6e2856a05cc3"
+  sram_const = "4a22d4b78fe0266fbee3958332f2939b"
+  sram_iv = "f98c48b1f9377284"
+
+[ot_device "ot-lc_ctrl"]
+  dev = "90f9c5c06f733dc911a321dd4c0ac240"
+  invalid = "5bc66d10208c4fb51b97bbf4d12c378c"
+  lc_state_first = "ee75b407d2314d2ef84185ac8c990f536071632c086d4c924070be92d2948d6228b2711e9b2d8c4d"
+  lc_state_last = "ee75fe0ffe7b6f3ffc5f9ffd9ff96fdb7f736f6c9e6fdcd35277fef2d3bdcd6ffbb2f59fdf3fbedd"
+  lc_trscnt_first = "dfb6c45a241f85ce9f42229e8627462fdb02c6701242f14b41891180045c09c26c52744267c04aa055921b9461bb07da"
+  lc_trscnt_last = "dfb6f4fabf1fefcebf5ba2ffc677c6afdbabcefeb672f36b4fbdb3988dfe1be67e7e77ca77c76af7ddde3b9e7fbfe7de"
+  ownership_first = "3c61398d626885931da660ed2ab18a0f"
+  ownership_last = "bc757dbdeaf9b7d35de7e9efabfbbecf"
+  production = "6d467215dab3f2b54a52e6728678af07"
+  raw_unlock_token = "ea2b3f32cbe77554e43c8ea7ebf197c2"
+  rma = "18068e344d2eae4d73c8fa54de8aa4a4"
+  soc_dbg_first = "440af80d"
+  soc_dbg_last = "6c9ef9cf"
+  test_unlocked = "cfd6a5a5bf3032db51fa1eb92f6ce10e"
+
+[ot_device "ot-keymgr"]
+  aes_seed = "c9e662e1e1b4982b3e8eff63890dbeae926fd468a77efde3de5b4caf4776a247"
+  cdi_seed = "516c144b34c96dfabb6f6e79208a74f35c79f397c4e4c7e22b7581848a90a125"
+  creator_identity_seed = "70251696fbb4ba169a6cd82fad46a0a5c04009bb934c7ef7b83b6e40610b4309"
+  hard_output_seed = "baf4410f06dcc036fcd16fcde97d171891105dd895e3a1d0a19a16d6dbd8b20f"
+  kmac_seed = "baba4c9908ed16bc5415ec16d28c53551312fcedcf2832a66ceacf8ed4d5b616"
+  lfsr_seed = "6ca8a8225c8e1705"
+  none_seed = "4b2276bec9fc1a7a5722a9aaca4db84a32e5c6985a1a6435118b5f5f3fd3b931"
+  otbn_seed = "177dd43b56fa754e1f53ad658193b563d9bdc6d2aee84852f0cc7371ed3a6faa"
+  owner_identity_seed = "a4a7bdb05fe921615bf2ff984540f7d43ece76b4eb13363774ed2ed45545e927"
+  owner_int_identity_seed = "fcb9dc54d4276137f9901d09a76aeaa19de5c579fd38bdf38f0c21d6a52226b6"
+  revision_seed = "20bdaf59fe2ae209b8325d2c8c35fc960679b106a87e59e6aeb1b5302d334010"
+  soft_output_seed = "f6d9e4abac398d42c745eef646c1464dca86dafd7c7c71e6058ddfd871c51cac"
+
+[ot_device "ot-ast-eg"]
+  topclocks = "main:100000000,io:96000000,usb:48000000,aon:200000"
+  aonclocks = "aon"
+
+[ot_device "ot-clkmgr"]
+  topclocks = "main:500,io:480,usb:240,aon:1"
+  refclock = "aon"
+  subclocks = "io_div2:io:2,io_div4:io:4,aes:main:1,hmac:main:1,kmac:main:1,otbn:main:1"
+  groups = "powerup:aon+io+io_div2+io_div4+main+usb,trans:aes+hmac+kmac+otbn,infra:io+io_div2+io_div4+main+usb,secure:aon+io_div4+main,peri:aon+io+io_div2+io_div4+usb,timers:aon+io_div4"
+  swcg = "peri"
+  hint = "trans"
+
+[ot_device "ot-pwrmgr"]
+  clocks = "main,io,usb"
+
diff --git a/docs/opentitan/cfggen.md b/docs/opentitan/cfggen.md
new file mode 100644
index 0000000000000..60fb06e867135
--- /dev/null
+++ b/docs/opentitan/cfggen.md
@@ -0,0 +1,96 @@
+# `cfggen.py`
+
+`cfggen.py` is a helper tool that can generate a QEMU OT configuration file,
+for use with QEMU's `-readconfig` option, populated with sensitive data for
+the ROM controller(s), the OTP controller, the Life Cycle controller, etc.
+
+It heurastically parses configuration and generated RTL files to extract from
+them the required keys, seeds, nonces and other tokens that are not stored in
+the QEMU binary.
+
+## Usage
+
+````text
+usage: cfggen.py [-h] [-T {darjeeling,earlgrey}] [-o CFG] [-c SV] [-l SV]
+                 [-S HJSON] [-t HJSON] [-s SOCID] [-C COUNT]
+                 [-a {config,clock}] [-x DEVICE.NAME] [-v] [-d]
+                 [OTDIR]
+
+OpenTitan QEMU configuration file generator.
+
+options:
+  -h, --help            show this help message and exit
+
+Files:
+  OTDIR                 OpenTitan root directory
+  -T, --top {darjeeling,earlgrey}
+                        OpenTitan top name
+  -o, --out CFG         Filename of the config file to generate
+  -c, --otpconst SV     OTP Constant SV file (default: auto)
+  -l, --lifecycle SV    LifeCycle SV file (default: auto)
+  -S, --secrets HJSON   Secret HJSON file (default: auto)
+  -t, --topcfg HJSON    OpenTitan top HJSON config file (default: auto)
+
+Modifiers:
+  -s, --socid SOCID     SoC identifier, if any
+  -C, --count COUNT     SoC count (default: 1)
+
+Actions:
+  -a, --action {config,clock}
+                        Action(s) to perform, default: config
+  -x, --exclude DEVICE.NAME
+                        Discard any property from DEVICE that starts with NAME
+                        (may be repeated)
+
+Extras:
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+### Arguments
+
+`OTDIR` is a required positional argument which should point to the root directory of the OpenTitan
+repository to analyze. It is used to generate the path towards the required files to parse, each of
+which can be overridden with options `-c`, `-l` and `-t`.
+
+* `-a` specify one or more actions to execute. Default is to generate a configuration file. It is
+  also possible to emit the list of module input clocks in a plain text format.
+
+* `-C` specify how many SoCs are used on the platform
+
+* `-c` alternative path to the `otp_ctrl_part_pkg.sv` file
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-l` alternative path to the `lc_ctrl_state_pkg.sv.sv` file
+
+* `-o` the filename of the configuration file to generate. It not specified, the generated content
+  is printed out to the standard output.
+
+* `-S` path to the generated file that contains all the "secret" constants of the _top_.
+
+* `-s` specify a SoC identifier for OT platforms with multiple SoCs
+
+* `-T` specify the OpenTitan _top_ name, such as `darjeeling`, `earlgrey`, ... This option is
+  mandatory if `-t` is not specified. An OTDIR root directory should be specified with this option.
+
+* `-t` path to the `top_<top>.gen.hjson` file. This option is mandatory is `-T` is not specified.
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+* `-x` can be used to prevent some device properties from being emitted in the output stream. This
+  can be useful while implementing a device, whose emulation does not support the comprehensive
+  feature set of its HW counterpart.
+
+### Examples
+
+````sh
+./scripts/opentitan/cfggen.py ../opentitan -T earlgrey -o opentitan.cfg
+````
+
+````sh
+# do not emit any 'flash*' properties for the EarlGrey OTP controller
+./scripts/opentitan/cfggen.py -o opentitan.cfg \
+    -t ../opentitan/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+    -x ot-otp-eg.flash
+````
diff --git a/docs/opentitan/checkregs.md b/docs/opentitan/checkregs.md
new file mode 100644
index 0000000000000..d16fcf5a86ab6
--- /dev/null
+++ b/docs/opentitan/checkregs.md
@@ -0,0 +1,72 @@
+# `checkregs.py`
+
+`checkregs.py` checks whether QEMU register definitions for OpenTitan match the generated OpenTitan
+`*_regs.h` files. This enables to spot major differences whenever OpenTitan definitions are updated.
+
+Note that only register addresses are checked for now, the bit assignment in each register is not
+validated.
+
+## Usage
+
+````text
+usage: checkregs.py [-h] [-q dir] [-a] [-k] [-M] [-v] [-d] file [file ...]
+
+Verify register definitions.
+
+positional arguments:
+  file                register header file
+
+options:
+  -h, --help          show this help message and exit
+  -q dir, --qemu dir  QEMU directory to seek
+  -a, --all           list all discrepancies
+  -k, --keep          keep verifying if QEMU impl. is not found
+  -M, --no-map        do not convert regs into QEMU impl. path
+  -v, --verbose       increase verbosity
+  -d, --debug         enable debug mode
+````
+
+### Arguments
+
+* `-a` list all discrepancies rather than only reporting their count.
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-k` keep searching for discrepancies if some error is detected.
+
+* `-M` do not try to map radix of input register files into their QEMU counter part
+
+* `-q dir` the directory to look for OpenTitan devices to check.
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+### Examples
+
+* All EarlGrey register files have been copied into `opentitan/regs-251rc1`
+
+  ````sh
+  scripts/opentitan/checkregs.py -k -q hw/opentitan ~/opentitan/regs-251rc1/*.h
+  ````
+  reports
+  ````
+  ERROR ot.regs    ot_hmac.c: 1 discrepancies
+  ERROR ot.regs    ot_otbn.c: 2 discrepancies
+  ERROR ot.regs    ot_otp.c: 69 discrepancies
+  ERROR ot.regs    ot_pinmux.c: 585 discrepancies
+  ERROR ot.regs    ot_ibex_wrapper.c: 1 discrepancies
+  658 differences
+  ````
+  `pinmux` and `otp` registers in QEMU OT are not implemented as a flat list of registers, which
+  explain the large amount of discrepancies.
+
+  ````sh
+  scripts/opentitan/checkregs.py -a -k -q hw/opentitan ~/opentitan/regs-251rc1/rv_core_ibex_regs.h -v
+  ````
+  reports
+  ````
+  WARNING ot.regs    QEMU ot_ibex_wrapper.c is missing 1 defs
+  WARNING ot.regs    .. DV_SIM_WINDOW (0x80)
+    ERROR ot.regs    ot_ibex_wrapper.c: 1 discrepancies
+  1 differences
+  ````
+  which is Ok as DV_SIM_WINDOW is not supported on QEMU.
diff --git a/docs/opentitan/debug.md b/docs/opentitan/debug.md
new file mode 100644
index 0000000000000..b378dfc60c887
--- /dev/null
+++ b/docs/opentitan/debug.md
@@ -0,0 +1,51 @@
+## Useful debugging options
+
+### Device log traces
+
+Most OpenTitan virtual devices can emit log traces. To select which traces should be logged, a plain
+text file can be used along with QEMU `-trace` option.
+
+To populate this file, the easiest way is to dump all available traces and filter them with a
+pattern, for example to get all OpenTitan trace messages:
+
+````sh
+qemu-system-riscv32 -trace help | grep -E '^ot_' > ot_trace.log
+qemu-system-riscv32 -trace events=ot_trace.log -D qemu.log ...
+````
+
+* It is *highly* recommended to use the `-D` option switch when any `-trace` or `-d` (see below) is
+selected, to avoid saturating the standard output stream with traces and redirect them into the
+specified log file.
+
+### QEMU log traces
+
+QEMU provides another way of logging execution of the virtual machine using the `-d` option. Those
+log messages are not tied to a specific device but rather to QEMU features. `-d help` can be used
+to enumerate these log features, however the most useful ones are enumerated here:
+
+   * `unimp` reports log messages for unimplemented features, _e.g._ when the vCPU attempts to
+     read from or write into a memory mapped device that has not been implemented.
+   * `guest_errors` reports log messages of invalid guest software requests, _e.g._ attempts to
+     perform an invalid configuration.
+   * `int` reports all interruptions *and* exceptions handled by the vCPU. It may be quite verbose
+     but also very useful to track down an invalid memory or I/O access for example. This is the
+     first option to use if the virtual machine seems to stall on start up.
+   * `in_asm` reports the decoded vCPU instructions that are translated by the QEMU TCG, _i.e._ here
+     the RISC-V instructions. Note that transcoded instructions are cached and handled by blocks,
+     so the flow of transcoded instruction do not exactly reflect the stream of the executed guest
+     instruction, e.g. may only appear once in a loop. Use the next log option, `exec`, to get
+     more detailed but also much more verbose log traces.
+   * `exec` reports the vCPU execution stream.
+
+Those options should be combined with a comma separator, _e.g._ `-d unimp,guest_errors,int`
+
+`in_asm` option may be able to report the name of the guest executed function, as long as the guest
+application symbols have been loaded. This is the case when the `-kernel` option is used to load
+an ELF non-stripped file. Unfortunately, this feature is not available for guest applications that
+are loaded from a raw binary file (`.bin`, `.signed.bin`, ...). However the
+[`flashgen.py`](flashgen.md) script implements a workaround for this feature, please refer to this
+script for more details.
+
+Finally, a Rust demangler has been added to QEMU, which enables the QEMU integrated disassembler to
+emit the demangled names of the Rust symbols for Rust-written guest applications rather than their
+mangled versions as stored in the ELF file.
diff --git a/docs/opentitan/devproxy.md b/docs/opentitan/devproxy.md
new file mode 100644
index 0000000000000..82b72c1f4e6c0
--- /dev/null
+++ b/docs/opentitan/devproxy.md
@@ -0,0 +1,1181 @@
+## DevProxy Protocol
+
+### Header
+
+#### DevProxy header
+
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|            COMMAND            |            LENGTH             |
++---------------+---------------+---------------+---------------+
+|                              UID                            |I|
++---------------+---------------+---------------+---------------+
+```
+
+#### DOE PCIe header [doe-pcie-header]
+
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             VendorID          |ObjectDataType |       -       |
++---------------+---------------+---------------+---------------+
+|             Length                |            -              |
++---------------+---------------+---------------+---------------+
+```
+
+#### Length fields
+
+##### Notes
+ * Values are encoded using the LE (litle endian) format
+ * `LENGTH` is the length in bytes excluding the first 8 bytes of the MBXPROXY protocol header,
+   coded on 16 bits. Payload is therefore < 64KB.
+ * This field is different from the `Length` is the length in 32-bit words (DW per Intel
+   terminology) of the Data Object itself, including the 2 first 32-bit words of the DOE header,
+   coded on 18 bits. Theoritical DOE payload is therefore ~1MB, which is capped by the MBX protocol.
+   It is not expected to have DOE packets larger than 4KB anyway.
+
+#### UID and Initiator fields
+
+DevProxy header is not related whatsoever to the content of the DOE packet, it is a simplistic TLV
+protocol, extended with a 31+1 bit UID. This UID is not accounted for in the `LENGTH` field, and is
+always present. The UID is a monotonic increasing integer. The initiator of a request should
+increment the UID for each request. The receiver should reply once with the same UID. The receiver
+should always acknowledge a request, whether it is successfully handled or not, in which case it
+should reply with a error code, using the UID of the failed command. The MSB of the 32-bit field
+that contains the UID is used to distinguish the peer. The QEMU peer is using `1`, the remote peer
+should use `0`. There are therefore two independent UID sequences: each UID is managed and
+incremented by the initiator, the receiver never modifies the UID. UIDs are used as sanity check to
+ensure sync is not lost between requests and responses. It is a fatal error to miss one UID or to
+reuse one. Roll over cases are not managed (2G requests). DevProxy protocol can be used with any
+kind of payload, i.e. not DOE payloads. This is the case for the first requests performed on the
+communication link for example (see below).
+
+#### Command fields
+
+Commands are coded with a 16-bit field. It is expected to only use ASCII bytes for commands, i.e.
+two characters that should be enough to encode many commands. Moreover, the initiator of a request
+should use UPPERCASE command, and the receiver should reply with the same command using only
+lowercased character. This allows to disambiguate initiators from responders, and use of ASCII
+character helps tracking and debugging packets. If a command cannot be executed on the receiver
+side, the receiver should reply with a `xx` response command (lowercased). The UID enables to track
+which command has failed. There is no other cases where the initiator command and the response
+command differ (case-insensitive). `XX` is therefore a reserved command.
+
+#### Role fields
+
+`Role` field encode an access control list role to use to access a register or a memory location.
+Valid values depends on the remote proxy, however the highest (role = 0xF) is reserved to specify
+that role field should be ignored, and role-less accessor should be used by the remote proxy.
+
+### Request/Response packets
+
+#### Error
+
+##### Request
+
+Not applicable
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'xx'              |            4..4+N             |
++---------------+---------------+---------------+---------------+
+|                              UID                            |S|
++---------------+---------------+---------------+---------------+
+|            Address            |         Device        |   -   |
++---------------+---------------+---------------+---------------+
+|                          Error Code                           |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                         (Error Message)                       |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+```
+* `Error Code` is a 32-bit error code that is always present
+
+```
++------------+---------------+----------------------------------+
+| Error Code | Error Type    | Error Description                |
++------------+---------------+----------------------------------+
+|    0x0     |               | No error                         |
++------------+---------------+----------------------------------+
+|    0x1     | Undefined     | Unknown                          |
++------------+---------------+----------------------------------+
+|    0x101   | Request       | Invalid command length           |
++------------+---------------+----------------------------------+
+|    0x102   | Request       | Invalid command code             |
++------------+---------------+----------------------------------+
+|    0x103   | Request       | Invalid request identifier       |
++------------+---------------+----------------------------------+
+|    0x104   | Request       | Invalid specifier identifier     |
++------------+---------------+----------------------------------+
+|    0x105   | Request       | Invalid device identifier        |
++------------+---------------+----------------------------------+
+|    0x106   | Request       | Invalid request                  |
++------------+---------------+----------------------------------+
+|    0x107   | Request       | Invalid address/register address |
++------------+---------------+----------------------------------+
+|    0x201   | State         | Device in error                  |
++------------+---------------+----------------------------------+
+|    0x401   | Local         | Cannot read device               |
++------------+---------------+----------------------------------+
+|    0x402   | Local         | Cannot write device              |
++------------+---------------+----------------------------------+
+|    0x403   | Local         | Truncated response               |
++------------+---------------+----------------------------------+
+|    0x404   | Local         | Incomplete write                 |
++------------+---------------+----------------------------------+
+|    0x405   | Local         | Out of resources                 |
++------------+---------------+----------------------------------+
+|    0x801   | Internal      | Unsupported device               |
++------------+---------------+----------------------------------+
+|    0x802   | Internal      | Duplicated unique identifier     |
++------------+---------------+----------------------------------+
+```
+
+* `Error Message` is an optional error message to help diagnose the actual error. The length of the
+  error message string can be retrieved from the `LENGTH` field.
+
+Any request may be responded with an error packet.
+
+#### Handshake
+
+Handshake is the first command exchanged over the communication link. It enables sanity check of the
+link, and to retrieve the version of the protocol the QEMU peer implement. It is the application
+responsability to ensure it can successfully communicate with the QEMU proxy.
+
+Only initiated by the application.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'HS'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'hs'              |               4               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+| Version Min   | Version Maj   |                               |
++---------------+---------------+---------------+---------------+
+```
+
+The current version for this documentation is v0.15.
+
+Note that semantic versionning does not apply for v0 series.
+
+#### Logmask
+
+Logmask can be used to change the qemu_log_mask bitmap at runtime, so log
+settings can be altered for specific runtime ranges, for a specific test for
+example
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'HL'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---+-----------+---------------+---------------+---------------+
+| Op|                         Log mask                          |
++---+-----------+---------------+---------------+---------------+
+```
+
+* `Op`: Log operation, among:
+  * `0`: change nothing, only read back the current log levels
+  * `1`: add new log channels from the log mask
+  * `2`: clear log channels from the log mask
+  * `3`: apply the log mask as is, overridding previous log channel settings
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'hl'              |               4               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---+-----------+---------------+---------------+---------------+
+| 0 |                    Previous log mask                      |
++---+-----------+---------------+---------------+---------------+
+```
+
+#### Enumerate Devices [enumerate-devices]
+
+Enumerate should be called by the Application to retrieve the list of remote devices that can be
+driven from the Application over the communication link.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'ED'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'ed'              |            0..4*7N            |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|            Offset             |         Device        |   -   |
++---------------+---------------+---------------+---------------+
+|                          Base Address                         |
++---------------+---------------+---------------+---------------+
+|                           Word Count                          |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                           Identifier                          |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+|            Offset             |         Device        |   -   |
++---------------+---------------+---------------+---------------+
+|                          Base Address                         |
++---------------+---------------+---------------+---------------+
+|                           Word Count                          |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                           Identifier                          |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+|                             ....                              |
++---------------+---------------+---------------+---------------+
+|            Offset             |         Device        |   -   |
++---------------+---------------+---------------+---------------+
+|                          Base Address                         |
++---------------+---------------+---------------+---------------+
+|                           Word Count                          |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                           Identifier                          |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+```
+Reponse contains 0 up to N devices, each device is described with a 28-byte entry, where:
+
+* `Device` is a unique device identifier that should be used to select the device for all further
+   requests to the device.
+* `Offset` is the relative base address of the first register than can be accessed on the device,
+   expressed in 32-bit word count
+* `RegCount` is the count of 32-bit registers that can be accessed, starting from the base address,
+   only if b0 is zero.
+* `WordCount` is the count of 32-bit slots for a memory-type device
+* `Base Address` is the base address of the device in the address space as seen from the local CPU.
+* `Identifier` is an arbitrary 16-character string that describes the device.
+
+The count of device entries can be retrieved from the `LENGTH` field.
+
+#### Enumerate Memory Spaces [enumerate-mr-spaces]
+
+Enumerate should be called by the Application to retrieve the list of remote memory spaces that can
+be used from the Application over the communication link.
+
+Each memory space is a top-level memory region, _i.e._ a root memory region.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'ES'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'es'              |            0..11*4N           |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|                             -                 |      MSpc     |
++---------------+---------------+---------------+---------------+
+|                         Start Address                         |
++---------------+---------------+---------------+---------------+
+|                             Size                              |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                           Identifier                          |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+|                             -                 |      MSpc     |
++---------------+---------------+---------------+---------------+
+|                         Start Address                         |
++---------------+---------------+---------------+---------------+
+|                             Size                              |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                           Identifier                          |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+|                             ....                              |
++---------------+---------------+---------------+---------------+
+|                             -                 |      MSpc     |
++---------------+---------------+---------------+---------------+
+|                         Start Address                         |
++---------------+---------------+---------------+---------------+
+|                             Size                              |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                           Identifier                          |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+```
+Reponse contains 0 up to N devices, each device is described with a 44-byte entry, where:
+
+* `MSpc` is a unique address space identifier than can be used as a selector in other proxy
+  commands.
+* `Start Address` is the lowest valid address in the address space.
+* `Size` is the size (in bytes) of the address space
+* `Identifier` is an arbitrary 32-character string that describes the memory space.
+
+The count of address spaces can be retrieved from the `LENGTH` field.
+
+#### Register Read
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'RW'              |               8               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|            Address            |         Device        | Role  |
++---------------+---------------+---------------+---------------+
+```
+
+Read the content of a 32-bit word register, where
+
+* `Address` is the register index, i.e. the relative address in bytes / 4.
+* `Role` is the initiator role to use to access the device
+* `Device` is the device to access (see [Enumerate](#enumerate-devices))
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'rw'              |               4               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|                             Value                             |
++---------------+---------------+---------------+---------------+
+```
+
+#### Register Write
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'WW'              |              12               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|            Address            |         Device        | Role  |
++---------------+---------------+---------------+---------------+
+|                             Value                             |
++---------------+---------------+---------------+---------------+
+|                             Mask                              |
++---------------+---------------+---------------+---------------+
+```
+
+Write the content of a 32-bit word register, where
+
+* `Address` is the register index, i.e. the relative address in bytes / 4.
+* `Role` is the initiator role to use to access the device
+* `Device` is the device to access (see [Enumerate](#enumerate-devices))
+* `Value` is the (optionally masked) 32-bit value to write
+* `Mask` is the mask of bits to be written. Masked bits (0) are left unmodified, unmasked bits (1)
+  are replaced with the bits from the value field. The remote device use read-modify-write sequence
+  if the destination device does not support atomic set.
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'ww'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+#### Read Buffer
+
+Read the content of several subsequence 32-bit registers, where
+
+* `Address` is the index of the first register, i.e. the relative address in bytes / 4. The address
+  is automatically incremented by the receiver side to read each register
+* `Role` is the initiator role to use to access the device
+* `Device` is the device to access (see [Enumerate](#enumerate-devices))
+* `Count` is the number of the register to read.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'RS'              |               8               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|            Address            |         Device        | Role  |
++---------------+---------------+---------------+---------------+
+|                             Count                             |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'rs'              |           4..4*Count          |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|                             Value #0                          |
++---------------+---------------+---------------+---------------+
+|                             Value #1                          |
++---------------+---------------+---------------+---------------+
+|                              ....                             |
++---------------+---------------+---------------+---------------+
+|                             Value #N-1                        |
++---------------+---------------+---------------+---------------+
+```
+
+#### Write Buffer
+
+Write the content of several subsequence 32-bit registers, where
+
+* `Address` is the index of the first register, i.e. the relative address in bytes / 4. The address
+  is automatically incremented by the receiver side to write each register
+* `Role` is the initiator role to use to access the device
+* `Device` is the device to access (see [Enumerate](#enumerate-devices))
+* `Value` are the values to write in each register.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'WS'              |           4 + 4*Count         |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|            Address            |         Device        | Role  |
++---------------+---------------+---------------+---------------+
+|                             Value #0                          |
++---------------+---------------+---------------+---------------+
+|                             Value #1                          |
++---------------+---------------+---------------+---------------+
+|                              ....                             |
++---------------+---------------+---------------+---------------+
+|                             Value #N-1                        |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'ws'              |               4               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|                             Count                             |
++---------------+---------------+---------------+---------------+
+```
+
+#### Read Mailbox
+
+Read the content of a DOE mailbox, where
+
+* `Address` is the index of the mailbox register, i.e. the relative address in bytes / 4.
+* `Role` is the initiator role to use to access the device
+* `Device` is the device to access (see [Enumerate](#enumerate-devices))
+* `Count` is the number of the 32-bit words to read out of the mailbox
+
+The content of the mailbox is read till either `Count` 32-bit words are read _or_ the Data Object
+has been fully read. Each read word is automatically flagged as read in the remote mailbox (see DOE
+protocol for detail).
+
+It is the responsability of the Application to ensure that the remote mailbox is ready to be read
+before initiating this command. If an error occurs during the read out of the mailbox, an error
+response should be returned. It is not an error to read less words than requests, _i.e._ it is safe
+to specify a high count of words to read - as long as the response may fit into a DevProxy packet.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'RX'              |               8               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|            Address            |         Device        | Role  |
++---------------+---------------+---------------+---------------+
+|                             Count                             |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'rx'              |            4..4*Count         |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|                             Value #0                          |
++---------------+---------------+---------------+---------------+
+|                             Value #1                          |
++---------------+---------------+---------------+---------------+
+|                              ....                             |
++---------------+---------------+---------------+---------------+
+|                             Value #Count-1                    |
++---------------+---------------+---------------+---------------+
+```
+
+#### Write Mailbox
+
+Write a message into the DOE mailbox, where
+
+* `Address` is the index of the mailbox register, i.e. the relative address in bytes / 4.
+* `Role` is the initiator role to use to access the device
+* `Device` is the device to access (see [Enumerate](#enumerate-devices))
+* `Value` are the values to write to the mailbox
+
+It is the responsability of the Application to ensure that the remote mailbox is reday to be written
+before initiating this command. If an error occurs during the write to the mailbox, an error
+response should be returned.
+
+The responder side automatically triggers the GO bit once all values have been written to the
+destination mailbox (if no error occurs).
+
+The Application is in charge of formatting the payload to ensure that it contains a valid DOE object
+(including formatting the header, see [DOE PCIe header](#doe-pcie-header))
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'WX'              |            4 + 4*Count        |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|            Address            |         Device        | Role  |
++---------------+---------------+---------------+---------------+
+|                             Value #0                          |
++---------------+---------------+---------------+---------------+
+|                             Value #1                          |
++---------------+---------------+---------------+---------------+
+|                              ....                             |
++---------------+---------------+---------------+---------------+
+|                             Value #N-1                        |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'wx'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|                             Count                             |
++---------------+---------------+---------------+---------------+
+```
+
+#### Read Memory
+
+Read the content of a memory device, where
+
+* `Address` is the address in bytes of the first 32-bit word
+* `Role` is the initiator role to use to access the device
+* `Device` is the device to access (see [Enumerate](#enumerate-devices))
+* `Count` is the number of 32-bit word to be read.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'RM'              |              12               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|               -               |         Device        | Role  |
++---------------+---------------+---------------+---------------+
+|                            Address                            |
++---------------+---------------+---------------+---------------+
+|                             Count                             |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'rm'              |            4..4*Count         |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|                            Value #0                           |
++---------------+---------------+---------------+---------------+
+|                            Value #1                           |
++---------------+---------------+---------------+---------------+
+|                              ....                             |
++---------------+---------------+---------------+---------------+
+|                            Value #N-1                         |
++---------------+---------------+---------------+---------------+
+```
+
+#### Write Memory
+
+Write a buffer to a memory device
+
+* `Address` is the address in bytes of the first 32-bit word to be written
+* `Role` is the initiator role to use to access the device
+* `Device` is the device to access (see [Enumerate Devices](#enumerate-devices))
+* `Value` are the values to write in memory word.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'WM'              |           8 + 4*Count         |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|               -               |         Device        | Role  |
++---------------+---------------+---------------+---------------+
+|                            Address                            |
++---------------+---------------+---------------+---------------+
+|                            Value #0                           |
++---------------+---------------+---------------+---------------+
+|                            Value #1                           |
++---------------+---------------+---------------+---------------+
+|                              ....                             |
++---------------+---------------+---------------+---------------+
+|                            Value #N-1                         |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'wm'              |               4               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|                             Count                             |
++---------------+---------------+---------------+---------------+
+```
+
+#### Resume VM execution
+
+Resume execution if the VM is currently stopped.
+
+When VM is started in stod mode `-S`, proxy can be used to configure the VM before kicking off the
+vCPUs.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'CX'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'cx'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+#### Quit
+
+Stop QEMU emulation and return an error code to the caller.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'QT'              |               8               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|                           Error code                          |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'qt'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+This is the last command, as QEMU should exit upon receiving this request.
+
+#### Enumerate Device Interrupt [enumerate-irq]
+
+Enumerate can be called by the Application to retrieve the list of interrupt groups of a supported
+device. The group in the response can be further used with the [Signal Interrupt API](#signal-interrupt),
+[Intercept Interrupts](#intercept-interrupt) and [Release Interrupts](#release-interrupt).
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'IE'              |               4               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|               -               |         Device        |   -   |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
++---------------+---------------+---------------+---------------+
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'ie'              |            0..36N             |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|            IRQ count          |     Group     |O|        -    |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                           Identifier                          |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+|            IRQ count          |     Group     |O|      -      |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                           Identifier                          |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+|                             ....                              |
++---------------+---------------+---------------+---------------+
+|            IRQ count          |     Group     |O|      -      |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                                                               |
+|                           Identifier                          |
+|                                                               |
+|                                                               |
++---------------+---------------+---------------+---------------+
+```
+Reponse contains 0 up to N interrupt groups, each group is described with a 36-byte entry, where:
+
+* `IRQ count` is the count of the input interrupts for this group,
+* `O` is set if IRQ in this group are output interrupts or or not set if they are input interrupts,
+* `Group` is the interrupt group identifier identifier.
+* `Identifier` defines the interrupt group name
+
+The count of address spaces can be retrieved from the `LENGTH` field.
+
+#### Intercept Interrupts [intercept-interrupt]
+
+Route one or more device output interrupts to the proxy (vs. the internal PLIC)
+
+* `Device` is the device to access (see [Enumerate Device](#enumerate-devices))
+* `Group` is the IRQ group in the device (see [Enumerate Interrupt](#enumerate-irq))
+* `Interrupt mask` define which interrupts should be released (1 bit per interrupt). The count of
+  32-bit interrupt mask word can be retrieved from the header length.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'II'              |              8..              |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|     Group     |        -      |         Device        |   -   |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                        Interrupt mask                         |
+|                                                               |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'ii'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+#### Release Interrupts [release-interrupt]
+
+Revert any previous interception, reconnecting selected IRQ to their original
+destination device.
+
+* `Device` is the device to access (see [Enumerate Device](#enumerate-devices))
+* `Group` is the IRQ group in the device (see [Enumerate Interrupt](#enumerate-irq))
+* `Interrupt mask` define which interrupts should be released (1 bit per interrupt). The count of
+  32-bit interrupt mask word can be retrieved from the header length.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'IR'              |              8..              |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|     Group     |        -      |         Device        |   -   |
++---------------+---------------+---------------+---------------+
+|                                                               |
+|                        Interrupt mask                         |
+|                                                               |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'ir'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+#### Signal Interrupt [signal-interrupt]
+
+Set or Reset an input interrupt line.
+
+* `Device` is the device to access (see [Enumerate Device](#enumerate-devices)),
+* `Group` the identifier of the IRQ group (see [Enumerate Interrupt](#enumerate-irq)),
+* `Interrupt line` the index of the interrupt line to signal within the group. The interrupt line
+   should range between 0 and the input IRQ count for this group,
+* `Level` the new interrupt line level. Usually `1` to assert/set (1) or `0` to deassert/release,
+  even if any 32-bit value is accepted.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'IS'              |               12              |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|             Group             |         Device        |   -   |
++---------------+---------------+---------------+---------------+
+|          Interrupt line       |               -               |
++---------------+---------------+---------------+---------------+
+|                             Level                             |
++---------------+---------------+---------------+---------------+
+```
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'is'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+#### Intercept arbitrary MMIO region [intercept-region]
+
+It is possible to get intercept access to a memory region. Any intercepted region cannot
+be any longer accessed by the remote vCPU.
+
+Use with care, as it may generate a very high traffic on the communication link. Width of
+intercepted location should be kept small.
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'MI'              |              12               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|R|W| Priority  | - |   Stop    |       -       |      MSpc     |
++---------------+---------------+---------------+---------------+
+|                            Address                            |
++---------------+---------------+---------------+---------------+
+|                             Size                              |
++---------------+---------------+---------------+---------------+
+```
+
+* `R` whether to notify on read access
+* `W` whether to notify on write access
+* `Priority` is the priority order (increasing order). 0 is reserved. If not sure, use 1.
+* `Stop` auto-stop count. If non-zero, only the specified count of notifications are reported,
+   after which the MMIO location intercepter is automatically discarded.
+* `MSpc` is the memory space of the region to select (see [Enumerate Memory Spaces](#enumerate-mr-spaces))
+* `Address` is the byte address of the first byte to intercept in the selected memory space
+* `Size` is the width in bytes of the region to intercept
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'mi'              |               4               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|               0               |         Region        |   -   |
++---------------+---------------+---------------+---------------+
+```
+
+* `Region` is the new intercepter number that describes the intercepting region
+
+#### Release intercepted MMIO locations
+
+##### Request
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'MR'              |               4               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+|               -               |         Region        |   -   |
++---------------+---------------+---------------+---------------+
+```
+
+* `Region` is the number of the intercepter to release
+
+##### Response
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|             'mr'              |               0               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |0|
++---------------+---------------+---------------+---------------+
+```
+
+* `Device` is the new device number that describes the intercepting region
+
+### Interrupt signalling
+
+Interrupt signalling are messages that never expect a response and that may be sent/received at any
+time. Each receiver should be prepared to handle many interrupt messages without any prior
+request/command.
+
+An [intercept interrupt](#intercept-interrupt) command should have been first used to select which
+interrupt(s) to receive.
+
+#### "Wired" Interrupt
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|              '^W'             |               12              |
++---------------+---------------+---------------+---------------+
+|                              UID                            |1|
++---------------+---------------+---------------+---------------+
+|               -               |         Device        |   -   |
++---------------+---------------+---------------+---------------+
+|            Channel            |     Group     |O|      -      |
++---------------+---------------+---------------+---------------+
+|                            Value                              |
++---------------+---------------+---------------+---------------+
+```
+
+* `Device` that triggered the interrupt
+* `Group` which interrupt group has been triggered
+* `Channel` which interrupt channel for the group has been triggered
+* `Value` the new interrupt value. For binary IRQs, `1` when IRQ is raised, `0` when it is lowered.
+
+#### MSI Interrupt
+
+To be defined.
+
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|              '^M'             |               8               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |1|
++---------------+---------------+---------------+---------------+
+|               -               |         Device        | Role  |
++---------------+---------------+---------------+---------------+
+|                            Value                              |
++---------------+---------------+---------------+---------------+
+```
+
+#### Region Access
+
+See [Intercept arbitrary MMIO region](#intercept-region) to register a watcher
+
+```
++---------------+---------------+---------------+---------------+
+|       0       |       1       |       2       |       3       |
+|0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
++---------------+---------------+---------------+---------------+
+|              '^R'             |              12               |
++---------------+---------------+---------------+---------------+
+|                              UID                            |1|
++---------------+---------------+---------------+---------------+
+|R|W|   | Width |       -       |         Region        |  Role |
++---------------+---------------+---------------+---------------+
+|                            Address                            |
++---------------+---------------+---------------+---------------+
+|                             Value                             |
++---------------+---------------+---------------+---------------+
+```
+
+* `Region` the region watcher identifier, as returned in the interception registration response
+* `R` read access
+* `W` write access
+* `Width` the width in byte of the MMIO access (1/2/4)
+* `Address` the absolute address of the MMIO access
+* `Value` the value if memory location was written, 0 otherwise
diff --git a/docs/opentitan/dtm.md b/docs/opentitan/dtm.md
new file mode 100644
index 0000000000000..706dc8d117d04
--- /dev/null
+++ b/docs/opentitan/dtm.md
@@ -0,0 +1,170 @@
+# `dtm.py`
+
+`dtm.py` checks that the JTAG/DTM/DM stack is up and running and demonstrates how to use the Debug
+Module to access the Ibex core.
+
+## Usage
+
+````text
+usage: dtm.py [-h] [-S SOCKET] [-t] [-w DELAY] [-l IR_LENGTH]
+              [--idcode IDCODE] [--dtmcs DTMCS] [--dmi DMI] [-b BASE] [-I]
+              [-c CSR] [-C CSR_CHECK] [-x] [-X] [-a ADDRESS] [-m {read,write}]
+              [-s SIZE] [-f FILE] [-D DATA] [-e ELF] [-F] [-v] [-d]
+
+Debug Transport Module tiny demo
+
+options:
+  -h, --help            show this help message and exit
+
+Virtual machine:
+  -S, --socket SOCKET   connection (default tcp:localhost:3335)
+  -t, --terminate       terminate QEMU when done
+  -w, --idle DELAY      stay idle before interacting with DTM
+
+DMI:
+  -l, --ir-length IR_LENGTH
+                        bit length of the IR register (default: 5)
+  --idcode IDCODE       define the ID code (default: 1)
+  --dtmcs DTMCS         define an alternative DTMCS register (default: 0x10)
+  --dmi DMI             define an alternative DMI register (default: 0x11)
+  -b, --base BASE       define DMI base address (default: 0x0)
+
+Info:
+  -I, --info            report JTAG ID code and DTM configuration
+  -c, --csr CSR         read CSR value from hart
+  -C, --csr-check CSR_CHECK
+                        check CSR value matches
+
+Actions:
+  -x, --execute         update the PC from a loaded ELF file
+  -X, --no-exec         does not resume hart execution
+
+Memory:
+  -a, --address ADDRESS
+                        address of the first byte to access
+  -m, --mem {read,write}
+                        access memory using System Bus
+  -s, --size SIZE       size in bytes of memory to access
+  -f, --file FILE       file to read/write data for memory access
+  -D, --data DATA       data to write using memory access
+  -e, --elf ELF         load ELF file into memory
+  -F, --fast-mode       do not check system bus status while transferring
+
+Extras:
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+### Arguments
+
+* `-a` specify the memory address where data is loaded or stored. Useful with the `--mem` option.
+  See also the `--size` option. Note that only 32-bit aligned addresses are supported for now.
+
+* `-b` specify the DMI base address for the RISC-V Debug Module
+
+* `-C` compare a CSR value to the specified value. Requires option `--csr`.
+
+* `-c` read and report a CSR from the Ibex core.
+
+* `-D` data to write, useful with `--mem` option in write mode. Mutually exclusive with `--file`.
+  Data may be specified as an decimal or hexadecimal integer, limited to 32-bit integers. It is also
+  possible to use `:` followed with a string of hexadecimal nibbles (without 0x prefix).
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-e` specify an ELF32 application file to upload into memory. See also the `--exec` option.
+
+* `-F` assume System Bus can cope with received data pace. This feature increases transfer data
+  rate by bypassing SB status check. However it  may cause the transfer to fail in case System Bus
+  becomes busy while data are transferred.
+
+* `-f` specify the file to read from or write to when option `--mem` is used. Mutually exclusive
+  with option `--data`.
+
+* `-I` report the JTAG ID code and the DTM configuration.
+
+* `-l` specify the length of the TAP instruction register length.
+
+* `-m <read|write>` specify a memory operation to perform. See also `--address`, `--size` and
+  `--file` options. With `read` operation, if no `--file` is specified, the content of the selected
+  memory segment is dumped to stdout, with a similar format as the output of `hexdump -C`. If a file
+  is supplied, the content of the segment is written as binary data into this file. With `write`
+  operation, `--file` argument is mandatory. The content of the binary file is copied into the
+  memory, starting at the `--address`. See also the `--elf` option for uploading applications.
+
+* `-S` specify the socket info to connect to the remote device.
+    * for QEMU VM JTAG server, TCP and Unix sockets are supported, _i.e._ `tcp:host:port` or
+      `unix:path/to/socket`.
+        * For TCP, this should follow the setting of the
+          `-chardev socket,id=taprbb,host=<host>,port=<num>,...` option for invoking QEMU.
+        * for Unix sockets, host/port are replaced with the unix socket path specified instead:
+          `-chardev socket,id=taprbb,path=<socket/path>`.
+    * for FTDI *232H USB-JTAG interfaces, PyFtdi v0.59+ Python module should be installed, and
+      pyftdi URL should be used to specify the FTDI device: _e.g._ `ftdi://ftdi:2232/1`
+
+* `-s` specify the number of bytes to read from or write to memory. Useful with the `--mem` option.
+  See also the `--address` option. This option may be omitted for the `write` memory operation, in
+  which case the size of the specified file is used. Note that only sizes multiple of 4 bytes are
+  supported for now.
+
+* `-t` send QEMU a request for termination when this script exits.
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+* `-w` pause execution on start up before communication with the remote DTM. This enables QEMU VM
+  to initialize and boot the guest SW before attempting a communication. It can be repeated once,
+  the second value being used to delay the termination of the VM when the `-t` option is used.
+
+* `-X` do not attempt to resume normal execution of the hart once DTM operation have been completed.
+  This can be useful for example when the QEMU VM is started with `-S` and no application code has
+  been loaded in memory: once the DTM operations are completed, the default behavior is to resume
+  the hart execution, would start execution code from the current PC and cause an immediate
+  exception. The `-x` option can nevertheless be executed, as it is the last action that the script
+  performs.
+
+* `-x` execute the loaded ELF application from its entry point. Requires the `--elf` option.
+  Application is executed even with `-X` defined.
+
+* `--idcode` specify an alternate IDCODE value
+
+* `--dmi` specify an alternate address for the DMI register
+
+* `--dtmcs` specify an alternate address for the DTMCS register
+
+### Examples
+
+Running QEMU VM with the `-chardev socket,id=taprbb,host=localhost,port=3335,server=on,wait=off`
+option:
+
+* Retrieve JTAG/DTM/DM information and `mtvec` CSR value
+  ````sh
+  ./scripts/opentitan/dtm.py -I -c mtvec
+  ````
+
+* Check that the MISA CSR matches the expected Ibex core value:
+  ````sh
+  ./scripts/opentitan/dtm.py -c misa -C 0x401411ad
+  ````
+
+* Load (fast mode) and execute an application
+  ````sh
+  ./scripts/opentitan/dtm.py -e .../helloworld -x -F
+  ````
+
+* Dump a memory segment to stdout
+  ````sh
+  ./scripts/opentitan/dtm.py -m read -a 0x1000_0080 -s 0x100
+  ````
+
+* Upload a file into memory and leave the Ibex core halted
+  ````sh
+  ./scripts/opentitan/dtm.py -m write -a 0x1000_0000 -f file.dat -X
+
+  ````
+
+* Write a 32-bit integer into memory
+  ````sh
+  ./scripts/opentitan/dtm.py -m write -a 0x1000_0000 -D 0x1234abcd
+  # or
+  ./scripts/opentitan/dtm.py -m write -a 0x1000_0000 -D :1234abcd
+  ````
diff --git a/docs/opentitan/flashgen.md b/docs/opentitan/flashgen.md
new file mode 100644
index 0000000000000..a58b762fdb554
--- /dev/null
+++ b/docs/opentitan/flashgen.md
@@ -0,0 +1,108 @@
+# `flashgen.py`
+
+`flashgen.py` populates a QEMU RAW image file which can be loaded by the OpenTitan integrated
+flash controller virtual device.
+
+## Usage
+
+````text
+usage: flashgen.py [-h] [-D] [-a {0,1}] [-s OFFSET] [-x file] [-X elf]
+                   [-b file] [-B elf] [-t OTDESC] [-T] [-U] [-A] [-v] [-d]
+                   flash
+
+Create/update an OpenTitan backend flash file.
+
+options:
+  -h, --help            show this help message and exit
+
+Image:
+  flash                 virtual flash file
+  -D, --discard         Discard any previous flash file content
+  -a, --bank {0,1}      flash bank for data (default: 0)
+  -s, --offset OFFSET   offset of the BL0 file (default: 0x10000)
+
+Files:
+  -x, --exec file       rom extension or application
+  -X, --exec-elf elf    ELF file for rom extension or application, for symbol
+                        tracking (default: auto)
+  -b, --boot file       bootloader 0 file
+  -B, --boot-elf elf    ELF file for bootloader, for symbol tracking (default:
+                        auto)
+  -t, --otdesc OTDESC   OpenTitan style file descriptor, may be repeated
+  -T, --ignore-time     Discard time checking on ELF files
+  -U, --unsafe-elf      Discard sanity checking on ELF files
+  -A, --accept-invalid  Blindly accept invalid input files
+
+Extra:
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+The (signed) binary files contain no symbols, which can make low-level debugging in QEMU difficult
+when using the `-d in_asm` and/or `-d exec` option switches.
+
+If an ELF file with the same radix as a binary file is located in the directory of the binary
+file, or its location is specified in the command line, the path to the ELF file is encoded
+into the flash image within a dedicated debug section.
+
+The OT flash controller emulation, when the stored ELF file exists, attempts to load the symbols
+from this ELF file into QEMU disassembler. This enables the QEMU disassembler - used with the
+`in_asm`/`exec` QEMU options - to output the name of each executed function as an addition to the
+guest PC value.
+
+It is therefore recommended to ensure the ELF files are located in the same directory as their
+matching signed binary files to help with debugging.
+
+### Arguments
+
+* `-A` accept any kind of input files, discarding all sanity checks. This option should only be used
+  to check the behavior of the VM and guest code when invalid files are stored in the embedded flash
+  device.
+
+* `-a bank` specify the data partition to store the binary file into, mutually exclusive with `-t`.
+
+* `-B elf` specify an alternative path to the BL0 ELF file. If not specified, the ELF path file is
+  reconstructed from the specified binary file (from the same directory). The ELF file is only used
+  as a hint for QEMU loader. Requires option `-b`, mutually exclusive with `-t`.
+
+* `-b file` specify the BL0 (signed) binary file to store in the data partition of the flash
+  image file. The Boot Loader 0 binary file is stored in the data partition at the offset
+  specified with the -s option, mutually exclusive with `-t`.
+
+* `-D` discard any flash content that may exist in the QEMU RAW image file.
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-s offset` the offset of the BootLoader image file in the data partition. Note that this offset
+  may also be hardcoded in the ROM_EXT application. Changing the default offset may cause the
+  ROM_EXT to fail to load the BL0 application.
+
+* `-t binfile@address` specify a binary file to store into the data partition of the flash.
+  This is a compatibility option introduced to support the original `opentitantool image assemble`
+  syntax. The provided address should be specified in hexadecimal format. Currently, it is not
+  possible to specify a matching ELF file as the flash debug trailer format is hardcoded to only
+  support ROM EXT and bootloader binaries in both banks, and does not support arbitrary ELFs.
+  This option may be repeated to specify multiple files such as the ROM EXT and a bootloader for
+  example. This option is mutually exclusive with `-b`, `-B`, `-x`, `-X` and `-a`.
+
+* `-X elf` specify an alternative path to the ROM_EXT ELF file. If not specified, the ELF path file
+  is reconstructed from the specified binary file (from the same directory). The ELF file is only
+  used as a hint for QEMU loader. Requires option `-x`, mutually exclusive with `-t`.
+
+* `-x file` specify the ROM_EXT (signed) binary file or the application to store into the data
+  partition of the flash image file. Alternatively this file can be any (signed) binary file such as
+  an OpenTitan test application. Note that if a BL0 binary file is used, the ROM_EXT/test binary
+  file should be smaller than the selected offset for the bootloader location, mutually exclusive
+  with `-t`.
+
+* `-T` tell the script to ignore any time discrepancy between a binary and an ELF file. A binary
+  file being generated from an ELF file, the former is not expected to be older than the latter.
+
+* `-U` tell the script to ignore any discrepancies found between a binary file and an ELF file. If
+  the path to an ELF file is stored in the flash image file, the ELF content is validated against
+  the binary file. Its code position and size, overall size and entry point should be coherent.
+  This option implies `-T` option, _i.e._ also discards time comparison between BIN and ELF files.
+  Note that contents of both files are not compared, as the binary file may be amended after the ELF
+  file creation.
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
diff --git a/docs/opentitan/gdbreplay.md b/docs/opentitan/gdbreplay.md
new file mode 100644
index 0000000000000..71af7867bb1d1
--- /dev/null
+++ b/docs/opentitan/gdbreplay.md
@@ -0,0 +1,87 @@
+# `gdbreplay.py`
+
+`gdbreplay.py` uses QEMU log files containing `exec` messages to help a GDB client to replay
+execution of a guest application.
+
+It parses QEMU log files, and creates a GDB server serving GDB remote requests. GDB client can
+add breakpoints and follow executed instructions by the guest, stepping or running till a
+breakpoint is encountered. It is possible to run execution backward.
+
+Supported GDB commands:
+
+ * step/step instruction
+ * reverse step/step instruction
+ * continue
+ * hardware breakpoint
+ * memory dump (code only), requires to provide the application(s) with the help of ELF or binary
+   files
+
+QEMU traces do not contain register values so it is not possible to observe any register content or
+data.
+
+## Usage
+
+````text
+usage: gdbreplay.py [-h] [-t LOG] [-e ELF] [-a ADDRESS] [-b BIN] [-g GDB] [-v] [-d]
+
+QEMU GDB replay.
+
+options:
+  -h, --help            show this help message and exit
+  -t LOG, --trace LOG   QEMU execution trace log
+  -e ELF, --elf ELF     ELF application
+  -a ADDRESS, --address ADDRESS
+                        Address to load each specified binary
+  -b BIN, --bin BIN     Binary application
+  -g GDB, --gdb GDB     GDB server (default to localhost:3333)
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+### Arguments
+
+* `-a` specify an address where to load the matching RAW binary application, see `-b` option for
+  details. May be repeated.
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-b` specify a RAW binary application. May be repeated. For each `-b` argument, there should be
+  a matching `-a` argument.
+
+* `-e` specify a ELF application to load. May be repeated.
+
+* `-g` specify an alternative interface/port to listen for GDB client
+
+* `-t` specify the QEMU log to parse for `exec`ution traces (see `-d exec` QEMU option)
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+### Examples
+
+* From one terminal, starts the GDB replay tool
+  ````sh
+  # Load two ELFs here, one for the ROM, one for the application to debug
+  ./scripts/opentitan/gdbreplay.py -vv -t qemu.log \
+      -e test_rom_fpga_cw310.elf -e csrng_kat_test_prog_fpga_cw310.elf
+  ````
+
+* From another terminal, starts a regular GDB client
+  ````sh
+  riscv64-unknown-elf-gdb
+  ````
+  then
+  ````
+  # Load the ELF file on GDB side so that it knows the symbols
+  file csrng_kat_test_prog_fpga_cw310.elf
+  # Connect to gdbreplay
+  target remote :3333
+  # Add a HW breakpoint to the entry function of the test
+  hb test_main
+  # Execute till breakpoint
+  c
+  ...
+  # Move execution back to the `test_main` caller
+  rsi
+  # Move execution point to the very first instruction
+  rc
+  ````
diff --git a/docs/opentitan/gpiodev.md b/docs/opentitan/gpiodev.md
new file mode 100644
index 0000000000000..0c160d5245f15
--- /dev/null
+++ b/docs/opentitan/gpiodev.md
@@ -0,0 +1,78 @@
+# `gpiodev.py`
+
+`gpiodev.py` acts as a GPIO CharDev backend to record and verify GPIO updates.
+
+It can be used to run regression tests and verify that the guest emits a predefined sequence of
+GPIO updates.
+
+## Usage
+
+````text
+usage: gpiodev.py [-h] [-p PORT] [-c CHECK] [-r RECORD] [-e END] [-q] [-s] [-t] [-v] [-d]
+
+GPIO device tiny simulator.
+
+options:
+  -h, --help            show this help message and exit
+  -p PORT, --port PORT  remote host TCP port (defaults to 8007)
+  -c CHECK, --check CHECK
+                        input file to check command sequence
+  -r RECORD, --record RECORD
+                        output file to record command sequence
+  -e END, --end END     emit the specified value to trigger remote exit on last received command
+  -q, --quit-on-error   exit on first error
+  -s, --single          run once: terminate once first remote disconnects
+  -t, --log-time        emit time in log messages
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+### Arguments
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-p` specify an alternative TCP port to listen for incoming QEMU CharDev socket requests
+
+* `-c` specify a pre-recorded GPIO backend text file - which only contains ASCII characters and
+  compare that incoming GPIO requests against the recorded data
+
+* `-r` specify a file to record incoming GPIO requests
+
+* `-e` emit a pre-defined GPIO input command - sent to the QEMU GPIO CharDev backend - that may be
+  recognized by the QEMU guest code as a special marker to end a test sequence. Requires the _check_
+  option for detecting the last expected GPIO request.
+
+* `-q` close the QEMU socket connection on first error or mismatched GPIO request when used with
+  the _check_ option.
+
+* `-s` quite the script on the first QEMU socket disconnection. Default is to listen for a new QEMU
+  CharDev socket connection, restarting from a fresh state.
+
+* `-t` add time to log messages
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+### Exit Status
+
+This script returns 0 if no error has been detected, or 1 if an error has been detected or the
+GPIO command stream has not been validated against the check file if any.
+
+### Examples
+
+With the following examples:
+
+`-chardev socket,id=gpio,host=localhost,port=8007 -global ot-gpio-$OTMACHINE.chardev=gpio` has been
+added to the QEMU command line to connect the GPIO backend to the incoming socket opened from the
+script. See the [GPIO documentation](ot_gpio.md) for details and the role of the `OTMACHINE`
+environment variable.
+
+* Record a GPIO request sequence
+  ````sh
+  ./scripts/opentitan/gpiodev.py -vv -r gpio.txt -s
+  ````
+
+* Check a GPIO request sequence against a previously record one, then triggers a VM guest app
+  triggered termination by setting GPIO 31 to a high level.
+  ````sh
+  ./scripts/opentitan/gpiodev.py -vv -c gpio.txt -s -e 0x8000_0000
+  ````
diff --git a/docs/opentitan/i2c_host_proxy.md b/docs/opentitan/i2c_host_proxy.md
new file mode 100644
index 0000000000000..8d100e33d400b
--- /dev/null
+++ b/docs/opentitan/i2c_host_proxy.md
@@ -0,0 +1,52 @@
+# OpenTitan I2C Host Proxy
+
+The `ot-i2c-host-proxy` device provides a way to execute I2C transactions with QEMU I2C bus devices
+through an externally driven `chardev` interface.
+
+The device can perform read or write transactions with bus devices and is intended to be used to
+drive the Opentitan I2C device Target mode, though it can be used to interact with other devices on
+the QEMU I2C buses.
+
+## Configuration
+
+A chardev and proxy device can be created in QEMU with the following arguments:
+
+`-chardev pty,i2cN -device ot-i2c-host-proxy,bus=<bus>,chardev=i2cN`
+
+Where `bus` is any of the system's I2C buses. On Earl Grey for example, these are `ot-i2c0`,
+`ot-i2c1`, and `ot-i2c2`.
+
+## Protocol
+
+The protocol over the chardev mirrors the I2C specification closely.
+
+Before each transaction, the protocol version must be sent. This is sent as an `i` byte (for I2C),
+followed by the version number byte (currently 1). The device will respond with an ACK byte
+(see below) if the version matches the implementation, and a NACK byte otherwise.
+
+A start and repeated start condition is signalled with an `S` byte, followed by a byte containing
+the 7-bit target address of the transaction and the read/write bit as the least significant bit
+(0 indicates a write transfer, 1 indicates a read transfer).
+
+On a repeated start condition, the I2C target address of the first transfer will be used, and the
+provided address is ignored (transfer direction can be changed). This is a limitation of QEMU.
+
+When a read transfer is active, a `R` byte can be sent to read a byte of data from the target I2C
+device.
+
+When a write transfer is active, a `W` byte, followed by a data byte, can be sent to write that
+byte to the target I2C device.
+
+A stop condition to end the transaction is signalled with a `P` byte.
+
+Following a start/repeated start condition and the address byte, as well as after every byte
+written during a write transfer, an ACK is signalled with a `.` byte, and a NACK is signalled with
+a `!` byte. If the start of a transfer is NACKed, the transaction should be terminated with a stop
+condition.
+
+On a parser error, a `x` byte will be returned, and the parser will not accept any more command
+bytes until reset.
+
+The implementation will throttle processing of written bytes to allow control to return to the
+vCPU, so that OT I2C may process the current transaction and prepare response bytes for upcoming
+reads.
diff --git a/docs/opentitan/ibex_hart.md b/docs/opentitan/ibex_hart.md
new file mode 100644
index 0000000000000..ec5101166cbff
--- /dev/null
+++ b/docs/opentitan/ibex_hart.md
@@ -0,0 +1,30 @@
+# IBEX Hart
+
+## Supported features
+
+* `RV32I` v2.1 Base Integer Instruction Set with `B` (`Zba`, `Zbb`, `Zbc` and `Zbs`) `C`, `M`
+  extensions
+* `Zicsr` and `Zifencei` extensions
+* `Smepmp` extension (ePMP)
+* `Zbr` v0.93 unratified ISA extension (crc32 instructions)
+
+## Unsupported features
+
+* Extensions not defined in RISC-V standard and/or not ratified are not supported (except `Zbr`)
+  * `Zbe`, `Zbf`, `Zbp` and `Zbt`
+* Ibex NMI
+* custom CSRs: `cpuctrlsts`, `secureseed`
+* `mret` extension (double fault management)
+
+## Useful options
+
+* `-icount 6` reduces the execution speed of the vCPU (Ibex core) to 1GHz >> 6, _i.e._ ~15MHz,
+  which should roughly match the expected speed of the Ibex core running on the CW310 FPGA, which
+  is set to 10 MHz. This option is very useful/mandatory to run many OpenTitan tests that rely on
+  time or CPU cycle to validate features. Using `-icount` option slows down execution speed though,
+  so it is not recommended to use it when the main goal is to develop SW to run on the virtual
+  machine. An alternative is to use `-icount shift=auto`, which offers fastest emulation execution,
+  while preserving an accurate ratio between the vCPU clock and the virtual devices.
+
+* `-cpu lowrisc-ibex,x-zbr=false` can be used to force disable the Zbr experimental-and-deprecated
+  RISC-V bitmap extension for CRC32 extension.
diff --git a/docs/opentitan/ibexdemo.md b/docs/opentitan/ibexdemo.md
new file mode 100644
index 0000000000000..68911ef8d1fac
--- /dev/null
+++ b/docs/opentitan/ibexdemo.md
@@ -0,0 +1,22 @@
+# IbexDemo on Arty A7
+
+Ibex Demo is a very lightweight platform that demonstrate the Ibex core features.
+
+* Hello Word application
+````sh
+qemu-system-riscv32 -M ibexdemo -nographic -kernel .../hello_world/demo
+````
+
+* Mandelbrot demo
+````sh
+qemu-system-riscv32 -M ibexdemo -display <gtk|cocoa> -kernel .../demo/lcd_st7735/lcd_st7735
+````
+
+## Useful execution options
+
+#### vCPU
+
+* `-icount N` reduces the execution speed of the vCPU (Ibex core) to 1GHz >> N
+
+* `-cpu lowrisc-ibex,x-zbr=true` can be used to force enable (IbexDemo platform) the Zbr
+  experimental-and-deprecated RISC-V bitmap extension for CRC32 extension.
diff --git a/docs/opentitan/index.md b/docs/opentitan/index.md
new file mode 100644
index 0000000000000..3da481270c7c4
--- /dev/null
+++ b/docs/opentitan/index.md
@@ -0,0 +1,41 @@
+# Ibex SoC emulation
+
+## Requirements
+
+1. A native toolchain for C and Rust
+2. Ninja build tool
+
+Note: never tested on Windows hosts.
+
+## Building
+
+````sh
+mkdir build
+cd build
+../configure --target-list=riscv32-softmmu --without-default-features --enable-tcg \
+    --enable-tools --enable-trace-backends=log \
+    [--enable-gtk --enable-pixman | --enable-cocoa]
+ninja
+ninja qemu-img
+````
+
+* `--enable-gtk --enable-pixman` and `--enable-cocoa` are only useful when using a graphical
+  display, such as the IbexDemo platform. It is mosly useless with the OpenTitan platform.
+
+    * `--enable-gtk --enable-pixman` should be used on Linux hosts
+    * `--enable-cocoa` should be used on macOS hosts
+
+* `--extra-cflags=-Wno-deprecated-declarations` and
+  `--extra-ldflags=-Wl,-no_warn_duplicate_libraries` may be required to build on recent releases of
+   macOS (QEMU issues which are not related to the OpenTitan port)
+
+### Useful build options
+
+ * `--enable-debug`
+ * `--enable-sanitizers`
+
+## Supported platforms
+
+ * [IbexDemo](ibexdemo.md) built for Digilent Arty7 board
+ * [Darjeeling](ot_darjeeling.md) build for CW310 "Bergen" board
+ * [EarlGrey](ot_earlgrey.md) build for CW310 "Bergen" board
diff --git a/docs/opentitan/jtag-dm.md b/docs/opentitan/jtag-dm.md
new file mode 100644
index 0000000000000..a5636edc296b0
--- /dev/null
+++ b/docs/opentitan/jtag-dm.md
@@ -0,0 +1,157 @@
+# JTAG and RISC-V Debug Module support for OpenTitan
+
+RISC-V Debug Module is implemented as an alternative to the default QEMU GDB server.
+
+It can be used when low-level features are required, such as prototyping JTAG manufacturing and
+provisioning software development, or emulating JTAG Debug Authentication.
+
+This initial implementation of the RISC-V Debug Module and Pulp DM supports the following features:
+
+- Ibex core debugging (RV32 only); not tested with multiple harts
+- system bus memory access: read and write guest memory
+- guest code debugging
+- single stepping
+- HW breakpoints
+- HW watchpoints
+
+## Communicating with RISC-V DM through a JTAG connection
+
+In QEMU machines for OpenTitan, any Debug Module can register on the Debug Transport Module, which
+dispatches requests to Debug Module depending on the received DMI address.
+
+See also [JTAG mailbox](jtagmbx.md) and [Life Controller](lc_ctrl_dmi.md) for other Debug Modules.
+
+```
++--------------------------+
+| Host (OpenOCD or Python) |
++--------------------------+
+      |
+      | TCP connection ("bitbang mode")
+      |
++-----|-----------------------------------------------------------------------------------+
+|     |                                                                             QEMU  |
+|     v                                              +---------+                          |
+| +-------------+     +-----+     +-----------+      | PULP-DM |         +------+         |
+| | JTAG server |---->| DTM |---->| RISC-V DM |<---->+ ------- +<=======>| Hart |         |
+| +-------------+     +-----+     +-----------+      | ROM/RAM |    ||   +------+         |
+|                                      ||            +---------+    ||                    |
+|                                      ||                           ||   +--------------+ |
+|                                       ================================>| I/O, RAM, ...| |
+|                                                                        +--------------+ |
++-----------------------------------------------------------------------------------------+
+```
+
+### Remote bitbang protocol
+
+The JTAG server supports the Remote Bitbang Protocol which is compatible with other tools such as
+Spike and [OpenOCD](https://github.com/riscv/riscv-openocd).
+
+QEMU should be started with an option such as:
+`-chardev socket,id=taprbb,host=localhost,port=3335,server=on,wait=off` so that the JTAG server is
+instantiated and listens for incoming connection on TCP port 3335.
+
+#### Remote termination feature
+
+The remote Remote Bitbang Protocol supports a "_quit_" feature which enables the remote client to
+trigger the end of execution of the QEMU VM. This feature can be useful to run automated tests for
+example.
+
+It is nevertheless possible to disable this feature and ignore the remote exit request so that
+multiple JTAG sessions can be run without terminating the QEMU VM.
+
+To disable this feature, use the `quit` option: `-global tap-ctrl-rbb,quit=off`.
+
+#### Implementation
+
+* JTAG server is implemented with `jtag/jtag_bitbang.c`
+* DTM is implemented with `hw/riscv/dtm.c`
+* RISC-V DM is implemented with `hw/riscv/dm.c`
+* Pulp-DM is implemented with `hw/misc/pulp_rv_dm.c`
+
+See also other supported DM modules on OpenTitan:
+
+* [JTAG mailbox DMI](jtagmbx.md)
+* [LifeCycle DMI](lc_ctrl_dmi.md)
+
+## Communicating with JTAG server using OpenOCD
+
+OpenOCD running on a host can connect to the embedded JTAG server, using a configuration script such
+as
+
+```tcl
+adapter driver remote_bitbang
+remote_bitbang host localhost
+remote_bitbang port 3335
+
+transport select jtag
+
+set _CHIPNAME riscv
+# part 1, ver 0, lowRISC; actual TAP id depends on the QEMU machine
+set _CPUTAPID 0x00011cdf
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+# Hart debug base also depends on the QEMU machine
+set DM_BASE 0x00
+
+target create $_CHIPNAME riscv -chain-position $_TARGETNAME rtos hwthread -dbgbase $DM_BASE
+```
+
+## Connecting GDB to OpenOCD
+
+In another terminal, `riscv{32,64}-unknown-elf-gdb` can be used to connect to OpenOCD:
+
+```
+# 64-bit version support 32-bit targets
+riscv64-unknown-elf-gdb
+```
+
+A basic `$HOME/.gdbinit` as the following should connect GDB to the running OpenOCD instance:
+```
+target remote :3333
+```
+
+## Communicating with JTAG server using Python
+
+`scripts/opentitan/ot` directory contains Python modules that provide several APIs to test the
+JTAG/DTM/DM stack.
+
+A demo application is available from [`scripts/opentitan/dtm.py`](dtm.md) that can report basic
+information about this stack and demonstrate how to use the Debug Module to access the Ibex core.
+
+The [`scripts/opentitan/otpdm.py`](otpdm.md) also use the same stack to access the cells of the OTP
+controller.
+
+### Troubleshooting [#troubleshooting]
+
+A common issue with initial JTAG configuration is to use the wrong Instruction Register length.
+The IR length depends on the actual implementation of the TAP controller and therefore may be
+different across HW implementations, here across OpenTitan instantiations.
+
+Unfortunately, there is no reliable way to automatically detect the IR length, this needs to be
+a setting that should be provided to the JTAG tool. Scripts in `scripts/opentitan` use the `-l` /
+`--ir-length` option to specify the IR length. The default value may be obtained with the `-h`
+option, which is IR length = 5 bits for default EarlGrey and Darjeeling machines.
+
+Whenever the wrong IR length is specified, or the default IR length is used with a HW/VM machine
+that uses a non-default length, the first instruction that is stored in the TAP instruction register
+is misinterpreted, which may cause different errors with the same root cause: a wrong IR length
+setting.
+
+It is recommended to query the DMI address bits with for example [`scripts/opentitan/dtm.py`](dtm.md)
+which is a basic command that needs a valid IR length setting to complete. Use `dtm.py -I` to query
+some low-level information from the remote peer.
+
+It should report something like:
+````
+IDCODE:    0x11cdf
+DTM:       v0.13, 12 bits
+````
+
+* If the DTM bit count is stuck to 0, the IR length is likely wrong,
+* If an error message such as `Invalid reported address bits` is returned, the IR length is likely
+  wrong.
+
+Another common issue is to use a machine with multiple Debug Modules but fail to specify its base
+address. The default DMI base address is always `0x0`. Use `-b` / `--base` option to select the
+proper Debug Module base address.
diff --git a/docs/opentitan/jtagmbx.md b/docs/opentitan/jtagmbx.md
new file mode 100644
index 0000000000000..7501140834f87
--- /dev/null
+++ b/docs/opentitan/jtagmbx.md
@@ -0,0 +1,244 @@
+# Darjeeling JTAG Mailbox
+
+The JTAG mailbox host side (responder) is connected to the private OT address space, while the
+system side (requester) is connected to a Debug Tile Link bus.
+
+## Communicating with the JTAG Mailbox through a JTAG connection
+
+In QEMU, a bridge between the Debug Transport Module (DTM) and the JTAG Mailbox is implemented
+as Debug Module bridge.
+
+```
++----------------+
+| Host (OpenOCD) |
++----------------+
+      |
+      | TCP connection ("bitbang mode")
+      |
++-----|-----------------------------------------------------------------------------------+
+|     v                                                                                   |
+| +-------------+     +-----+     +----------+         +---------+         +------+       |
+| | JTAG server |---->| DTM |---->| ot_dm_tl |====D====|S> MBX <H|====P====| Hart |       |
+| +-------------+     +-----+     +----------+         +---------+         +------+       |
+|                                                                                     QEMU|
++-----------------------------------------------------------------------------------------+
+```
+
+where:
+  `P` is the private OT bus
+  `D` is the debug bus
+
+QEMU should be started with an option such as:
+`-chardev socket,id=taprbb,host=localhost,port=3335,server=on,wait=off` so that the JTAG server is
+instantiated and listens for incoming connection on TCP port 3335.
+
+## Communicating with JTAG server and JTAG MailBox using Python
+
+OpenTitan implementation provides JTAG/DTM/DMI/Mailbox stack available as Python modules:
+
+* jtag/tap module is available from `python/qemu/jtag` directory
+* dtm/dmi and jtag mailbox modules are available from `scripts/opentitan` directory
+
+Python snippet to create a communication channel with the VM JTAG mailbox:
+
+````py
+from socket import create_connection
+from jtag.bitbang import JtagBitbangController
+from jtag.jtag import JtagEngine
+from ot.dtm import DebugTransportModule
+from ot.mailbox.jtag import JtagMbox
+
+sock = create_connection(('localhost', 3335), timeout=1.0)
+ctrl = JtagBitbangController(sock)
+eng = JtagEngine(ctrl)
+ctrl.tap_reset(True)
+dtm = DebugTransportModule(eng, 5)  # IR length depends on the actual machine
+version, abits = dtm['dtmcs'].dmi_version, dtm['dtmcs'].abits
+print(f'DTM: v{version[0]}.{version[1]}, {abits} bits')
+dtm['dtmcs'].dmireset()
+mbj = JtagMbox(dtm, 0x2200 >> 2)
+
+# See ot.mailbox.sysmbox.SysMbox for mailbox communication API
+````
+
+## Communicating with JTAG server using OpenOCD
+
+It is possible from OpenOCD running a host to connect to the embedded JTAG server using the
+`remote_bitbang` protocol, using a configuration script such as
+
+```tcl
+adapter driver remote_bitbang
+remote_bitbang host localhost
+remote_bitbang port 3335
+
+transport select jtag
+
+set _CHIPNAME riscv
+# part 1, ver 0, lowRISC; actual TAP id depends on the QEMU machine
+set _CPUTAPID 0x00011cdf
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+# Hart debug base also depends on the QEMU machine
+set DM_BASE 0x00
+
+target create $_CHIPNAME riscv -chain-position $_TARGETNAME rtos hwthread -dbgbase $DM_BASE
+```
+
+From here, it is possible reach the JTAG dmi through the DMI device:
+
+```tcl
+# Mailbox system register addresses
+set MBX_SYS_BASE 0x200
+
+set SYS_INTR_MSG_ADDR $($MBX_SYS_BASE + 0x0)
+set SYS_INTR_MSG_DATA $($MBX_SYS_BASE + 0x1)
+set SYS_CONTROL       $($MBX_SYS_BASE + 0x2)
+set SYS_STATUS        $($MBX_SYS_BASE + 0x3)
+set SYS_WRITE_DATA    $($MBX_SYS_BASE + 0x4)
+set SYS_READ_DATA     $($MBX_SYS_BASE + 0x5)
+
+# Mailbox system register bits
+set SYS_CONTROL_ABORT      0x1
+set SYS_CONTROL_SYS_INT_EN 0x2
+set SYS_CONTROL_GO         0x80000000
+
+set SYS_STATUS_BUSY        0x1
+set SYS_STATUS_INT         0x2
+set SYS_STATUS_ERROR       0x4
+set SYS_STATUS_READY       0x80000000
+
+# read the STATUS register
+dmi_read $SYS_STATUS
+
+# write the GO bit of the control register
+dmi_write $SYS_CONTROL $SYS_CONTROL_GO
+```
+
+Unfortunalely the current version of OpenOCD (v0.12+) does not support a JTAG-DMI communication if
+no RISC-V DM module is connected to the DMI device, _i.e._
+
+```
++----------------+
+| Host (OpenOCD) |
++----------------+
+      |
+      | TCP connection ("bitbang mode")
+      |
++-----|-----------------------------------------------------------------------------------+
+|     v                                                                                   |
+| +-------------+     +-----+     +----------+         +---------+         +------+       |
+| | JTAG server |---->| DTM |-+-->| ot_dm_tl |====D====|S> MBX <H|===++=P==| Hart |       |
+| +-------------+     +-----+ |   +----------+         +---------+   ||    +------+       |
+|                             |                                      ||                   |
+|                             |   +----+     +-------- +             ||                   |
+|                              -->| DM |---->| PulpDM  |==============                    |
+|                                 +----+     +---------+                                  |
+|                                            | ROM/RAM |                                  |
+|                                            +---------+                                  |
+|                                                                                         |
+|                                                                                     QEMU|
++-----------------------------------------------------------------------------------------+
+```
+
+If no RISC-V compatible DM is detected at `$DM_BASE`, OpenOCD enters an infinite loop seeking a
+valid DM module.
+
+DM / PulpDM should be part of an upcoming delivery. Meanwhile it is required to tweak OpenOCD so
+that it accepts staying connected to the DMI even if it cannot locate a valud DM:
+
+```diff
+diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
+index 2ab28deac..0e84418d9 100644
+--- a/src/target/riscv/riscv-013.c
++++ b/src/target/riscv/riscv-013.c
+@@ -1882,6 +1882,8 @@ static int examine(struct target *target)
+ 		return ERROR_FAIL;
+ 	}
+
++	target->state = TARGET_UNAVAILABLE;
++	return ERROR_OK;
+ 	/* Reset the Debug Module. */
+ 	dm013_info_t *dm = get_dm(target);
+ 	if (!dm)
+diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
+index 5bae01d5f..786f2520a 100644
+--- a/src/target/riscv/riscv.c
++++ b/src/target/riscv/riscv.c
+@@ -3167,6 +3167,8 @@ int riscv_openocd_poll(struct target *target)
+ {
+ 	LOG_TARGET_DEBUG_IO(target, "Polling all harts.");
+
++	return ERROR_OK;
++
+ 	struct list_head *targets;
+
+ 	LIST_HEAD(single_target_list);
+```
+
+## Communicating with the JTAG Mailbox through a DevProxy connection
+
+DevProxy is a communication tool that enables to control QEMU devices from a remote host, over a
+TCP connection.
+
+It can access QEMU `SysBusDevice` through their `MemoryRegion` API, intercepts or generate IRQs on
+those devices, intercepts accesses to plain RAM region and read or modify their content. See the
+[devproxy.md](devproxy.md) document for information about the DevProxy communication protocol and
+supported features.
+
+The `devproxy.py` Python module implements the DevProxy protocol and can be used on a host to
+remotely control selected devices in the QEMU machine. It includes support for the Mailbox devices
+for both the Host and System interfaces.
+
+```
++--------------------+
+| Host (Python, ...) |
++--------------------+
+      |
+      | TCP connection
+      |
++-----|-----------------------------------------+
+|     v                                         |
+| +-----------------+                           |
+| | DevProxy server |------                     |
+| +-----------------+      |                    |
+|      |                   |                    |
+|     CTN               Private                 |
+|      |                   |                    |
+|      |    +---------+    |                    |
+|      +--->|S> MBX <H|<---+                    |
+|      |    +---------+    |    +------+        |
+|      |                   +---<| Hart |        |
+|      |    +---------+    |    +------+        |
+|      +--->|S> MBX <H|<---+                    |
+|      |    +---------+    |    +---------+     |
+|      |                   +--->| MBX RAM |     |
+|      |    +---------+    |    +---------+     |
+|      +--->|S> MBX <H|<---+                    |
+|      |    +---------+    |    +-----+         |
+|      |                   +--->| RAM |         |
+|      |                   |    +-----+         |
+|     ...                  |                    |
+|      |    +---------+    |                    |
+|      +--->|   IPI   |    |                    |
+|      |    +---------+    |                    |
+|     ...                 ...                   |
+|                                           QEMU|
++-----------------------------------------------+
+```
+
+QEMU should be started with a option pair to enable communication with the DevProxy server:
+* `-chardev socket,id=devproxy,host=localhost,port=8003,server=on,wait=off
+* `-global ot-dev_proxy.chardev=devproxy`
+
+Subsequently, a Python script importing the `devproxy.py` module can be used to communicate with
+the JTAG mailbox.
+
+Note: `devproxy.py` needs to be found within the Python path, using for example
+```sh
+export PYTHONPATH=${QEMU_SOURCE_PATH}/scripts/opentitan
+```
+
+### Troubleshooting
+
+See the [Troubleshooting](jtag-dm.md#troubleshooting) section for details.
diff --git a/docs/opentitan/keymgr-dpe.md b/docs/opentitan/keymgr-dpe.md
new file mode 100644
index 0000000000000..4fed6eb529acc
--- /dev/null
+++ b/docs/opentitan/keymgr-dpe.md
@@ -0,0 +1,244 @@
+# `keymgr-dpe.py`
+
+`keymgr-dpe.py` is a helper tool that can be used to generate or verify Key Manager DPE keys, using
+the same parameters as the QEMU machine and the real HW, for debugging purposes.
+
+## Usage
+
+````text
+usage: keymgr-dpe.py [-h] -c CFG -j HJSON [-l SV] [-m VMEM] [-R RAW] [-r ROM]
+                     [-e BITS] [-z SIZE] [-v] [-d]
+                     {generate,execute,verify} ...
+
+QEMU OT tool to generate Key Manager DPE keys.
+
+positional arguments:
+  {generate,execute,verify}
+                        Execution mode
+    generate            generate a key
+    execute             execute sqeuence
+    verify              verify execution log
+
+options:
+  -h, --help            show this help message and exit
+
+Files:
+  -c, --config CFG      input QEMU OT config file
+  -j, --otp-map HJSON   input OTP controller memory map file
+  -l, --lifecycle SV    input lifecycle system verilog file
+  -m, --vmem VMEM       input VMEM file
+  -R, --raw RAW         input QEMU OTP raw image file
+  -r, --rom ROM         input ROM image file, may be repeated
+
+Parameters:
+  -e, --ecc BITS        ECC bit count (default: 6)
+  -z, --rom-size SIZE   ROM image size in bytes, may be repeated
+
+Extras:
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+### Arguments
+
+* `-c` QEMU OT config file, which can be generated with the [`cfggen.py`](cfggen.md) script.
+  See also predefined files from the `docs/config/opentitan` directory.
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-e` specify how many bits are used in the HEX and VMEM files to store ECC information.
+
+* `-j` specify the path to the HJSON OTP controller map file, usually stored in OT
+  `hw/ip/otp_ctrl/data/otp_ctrl_mmap.hjson`, required to decode any OTP file.
+
+* `-l` specify the life cycle system verilog file that defines the encoding of the life cycle
+  states, required to decode the Life Cycle state, which is stored in the OTP file.
+
+* `-m` specify the input VMEM file that contains the OTP fuse content, mutually exclusive with `-R`
+
+* `-r` specify the path to a ROM file. This option should be repeated for each ROM file. The ROM
+  file may either be a ELF or a binary file, in which case the same count of `-z` ROM size option,
+  specified in the same order as the ROM file, is required. When such a ROM file format is used, the
+  ROM digest is computed from the ROM file content. The ROM file can also be specified a `HEX`
+  scrambled file, in which case the digest is read from the file itself. `VMEM` format is not yet
+  supported.
+
+* `-R` specify the path to the QEMU OTP RAW image file, which can be generated with the
+  [`otptool.py`](otptool.md), mutually exclusive with option `-m`.
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+* `-z` specify the size of each ROM file in bytes. It should be repeated for each specified ROM
+ file, except if all ROM files are specified as HEX formatted files. It can either be specified as
+ an integer or an integer with an SI-suffix (Ki, Mi), such as `-z 64Ki`.
+
+Depending on the execution mode, the following options are available:
+
+## Generate options
+
+This mode can be used to generate a single output key, which can be stored into an output file.
+
+```
+usage: keymgr-dpe.py [-h] -c CFG -j HJSON [-l SV] [-m VMEM] [-R RAW] [-r ROM]
+                     [-e BITS] [-z SIZE] [-v] [-d]
+                     {generate,execute,verify} ...
+
+QEMU OT tool to generate Key Manager DPE keys.
+
+positional arguments:
+  {generate,execute,verify}
+                        Execution mode
+    generate            generate a key
+    execute             execute sequence
+    verify              verify execution log
+
+options:
+  -h, --help            show this help message and exit
+
+Files:
+  -c, --config CFG      input QEMU OT config file
+  -j, --otp-map HJSON   input OTP controller memory map file
+  -l, --lifecycle SV    input lifecycle system verilog file
+  -m, --vmem VMEM       input VMEM file
+  -R, --raw RAW         input QEMU OTP raw image file
+  -r, --rom ROM         input ROM image file, may be repeated
+
+Parameters:
+  -e, --ecc BITS        ECC bit count (default: 6)
+  -z, --rom-size SIZE   ROM image size in bytes, may be repeated
+
+Extras:
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+```
+
+### Arguments
+
+* `-b` specify the software binding for an _advance_ stage of the key manager. It should be repeated
+   for each new stage to execute. Note the first stage does not require a software binding value and
+   is always executed. The expected format is a hexa-decimal encoded string (without 0x prefix). It
+   is automatically padded with zero bytes up to the maximum software binding size supported by the
+   HW.
+
+* `-c` specify a QEMU [configuration file](otcfg.md) from which to read all the cryptographic
+  constants. See the [`cfggen.py`](cfggen.md) tool to generate such a file.
+
+* `-g` specify the kind of generation to perform. If not specified, it is inferred from the `-t`
+  target option.
+
+* `-j` specify the path to the HJSON OTP controller map file, usually named `otp_ctrl_mmap.hjson`.
+
+* `-l` specify the life cycle system verilog file, usually named `lc_ctrl_state_pkg.sv`, that
+  defines the encoding of the life cycle states.
+
+* `-k` the version of the key to generate
+
+* `-o` specify the output file path for the generated key
+
+* `-R` when specified, the Key Manager output slot is encoded as a Rust constant, whose
+   name is specified with this option. Default is to print the output slot in plain text.
+
+* `-s` specify the salt for the _generate_ stage of the key manager. The expected format is a hexa-
+   decimal encoded string (without 0x prefix). It is automatically padded with zero bytes up to the
+   maximum salt size supported by the HW.
+
+* `-t` specify the destination for the _generate_ stage.
+
+### Examples
+
+````sh
+keymgr-dpe.py -vv -c docs/config/opentitan/darjeeling.cfg \
+    -j otp_ctrl_mmap.hjson -m img_otp.vmem -l lc_ctrl_state_pkg.sv \
+    -r base_rom.39.scr.hex -r second_rom.39.scr.hex -b 0 -b 0 -t AES -k 0 -s 0
+````
+
+````sh
+keymgr-dpe.py -vv -c docs/config/opentitan/darjeeling.cfg \
+    -j otp_ctrl_mmap.hjson -m img_otp.vmem -l lc_ctrl_state_pkg.sv \
+    -r rom0.elf -r keymgr-dpe-basic-test -z 64Ki -z 32Ki -t SW -k 0 -s 0
+````
+
+## Execute options [execute-options]
+
+This mode can be used to execute a sequence of steps, with multiple key generations.
+
+It requires an input file containing the sequence of steps to execute, which follows the INI file
+format. Each section in the file represents a step in the sequence, and the options within each
+section specify the parameters for that step.
+
+```
+usage: keymgr-dpe.py execute [-h] -s INI
+
+options:
+  -h, --help          show this help message and exit
+  -s, --sequence INI  execution sequence definition
+```
+
+### Arguments
+
+* `-s` specify an INI-like configuration file containing the sequence of steps to execute
+
+    Typical input file:
+
+    ````ini
+    [step_1]
+    mode = initialize
+    dst = 0
+
+    [step_2]
+    mode = advance
+    binding = [0]
+    src = 0
+    dst = 1
+    allow_child = true
+    exportable = true
+    retain_parent = true
+
+    [step_3]
+    mode = generate
+    src = 1
+    dst = otbn
+    key_version = 0
+    salt = "[49379059ff52399275666880c0e44716999612df80f1a9de481eae4045e2c7f0]"
+
+    [step_4]
+    mode = generate
+    src = 1
+    dst = none
+    key_version = 0
+    salt = "[49379059ff52399275666880c0e44716999612df80f1a9de481eae4045e2c7f0]"
+    ````
+
+## Verify options
+
+This mode can be used to verify the execution of a unit test, which is expected to print out the
+input parameters it sends to the KeyManger DPE and the output key which is generated by the latter.
+
+Note that as the generated sideloaded key cannot usually be accessed by the Ibex core, the following
+tricks are used:
+
+* for AES sideloaded key, the AES key is used to encrypt a zeroed plaintext, and the verification is
+performed on the ciphertext
+* for KMAC sideloaded key, the KMAC key is used to perform a hash on a zeroed input buffer, and the
+verification is performed on the resulting hash value.
+* for OTBN sideloaded key, the OTBN key is read by the OTBN core and replicated into its data
+memory, which is then read back by the Ibex core. In this cas, the direct key is verified.
+
+```
+usage: keymgr-dpe.py verify [-h] -l LOG
+
+options:
+  -h, --help          show this help message and exit
+  -l, --exec-log LOG  execution log to verify
+```
+
+### Arguments
+
+* `-l` specify the execution log to verify. The execution log is expected to contain the output of
+  a test that has run on the OpenTitan platform. It should emit a syntax identical to the format
+  described in the [Execute options](#execute-options) section, _i.e._ an INI-like syntax. To
+  distinguish INI syntax from any other log output, each line of interest should be prefixed with a
+  `T> ` marker.
+
+    [`pyot.py`](pyot.md) script may be used to generate the log file, see `--log-file` option or the
+    `log_file` test parameter.
diff --git a/docs/opentitan/lc_ctrl_dmi.md b/docs/opentitan/lc_ctrl_dmi.md
new file mode 100644
index 0000000000000..d30137aa4febc
--- /dev/null
+++ b/docs/opentitan/lc_ctrl_dmi.md
@@ -0,0 +1,70 @@
+# LifeCycle Controller over DTM
+
+## Communicating with the Life Cycle Controller through a JTAG connection
+
+In QEMU, a bridge between the Debug Transport Module (DTM) and the Life Cycle Controller is
+implemented as a Debug Module bridge.
+
+```
++----------------+
+| Host (OpenOCD) |
++----------------+
+      |
+      | TCP connection ("bitbang mode")
+      |
++-----|-----------------------------------------------------------------------------------+
+|     v                                                                                   |
+| +-------------+     +-----+     +----------+         +---------+         +------+       |
+| | JTAG server |---->| DTM |---->| ot_dm_tl |====D====| LC Ctrl |====P====| Hart |       |
+| +-------------+     +-----+     +----------+         +---------+         +------+       |
+|                                                                                     QEMU|
++-----------------------------------------------------------------------------------------+
+```
+
+where:
+  `P` is the private OT bus
+  `D` is the debug bus
+
+In Darjeeling, a top-level debug crossbar multiplexes debug access to several devices, including
+the Life Cycle Controller. Therefore, there is a single DTM and Debug Module bridge. In the QEMU
+implementation of Darjeeling we thus have a single JTAG server, reachable over the `taprbb`
+character device. For that machine, QEMU should be started with an option such as:
+`-chardev socket,id=taprbb,host=localhost,port=3335,server=on,wait=off` so that the JTAG server is
+instantiated and listens for incoming connections on TCP port 3335.
+
+In Earlgrey, we have multiple JTAG TAPs, including one for the Life Cycle Controller. The Life Cycle
+Controller instantiates its own DTM and Debug Module bridge. Therefore, in the QEMU implementation
+of Earlgrey we use a separate character device for that JTAG server, named instead `taprbb-lc-ctrl`.
+
+## Communicating with JTAG server and Life Cycle controller using Python
+
+OpenTitan implementation provides JTAG/DTM/DMI/Mailbox stack available as Python modules:
+
+* jtag/tap module is available from `python/qemu/jtag` directory
+* dtm/dmi and jtag mailbox modules are available from `scripts/opentitan` directory
+
+Python snippet to create a communication channel with the VM JTAG mailbox:
+
+````py
+from socket import create_connection
+from jtag.bitbang import JtagBitbangController
+from jtag.jtag import JtagEngine
+from ot.dtm import DebugTransportModule
+from ot.lc_ctrl.lcdmi import LifeCycleController
+
+sock = create_connection(('localhost', 3335), timeout=1.0)
+ctrl = JtagBitbangController(sock)
+eng = JtagEngine(ctrl)
+ctrl.tap_reset(True)
+dtm = DebugTransportModule(eng, 5)  # IR length depends on the actual machine
+version, abits = dtm['dtmcs'].dmi_version, dtm['dtmcs'].abits
+print(f'DTM: v{version[0]}.{version[1]}, {abits} bits')
+dtm['dtmcs'].dmireset()
+lc_ctrl = LifeCycleController(dtm, 0x3000 >> 2)
+
+# See LifeCycleController for LC controller communication API
+````
+
+### Troubleshooting
+
+See the [Troubleshooting](jtag-dm.md#troubleshooting) section for details.
diff --git a/docs/opentitan/ot_aes.md b/docs/opentitan/ot_aes.md
new file mode 100644
index 0000000000000..16ad9a48f0b88
--- /dev/null
+++ b/docs/opentitan/ot_aes.md
@@ -0,0 +1,7 @@
+# OpenTitan AES
+
+* `-global ot-aes.fast-mode=false` can be used to better emulate AES HW IP, as some OT tests expect
+  the Ibex core to execute while the HW is performing AES rounds. Without this option, the virtual
+  HW may only give back execution to the vCPU once the AES operation is complete, which make those
+  OT tests to fail. Disabling fast mode better emulates the HW to the expense of higher AES latency
+  and throughput.
diff --git a/docs/opentitan/ot_darjeeling.md b/docs/opentitan/ot_darjeeling.md
new file mode 100644
index 0000000000000..c3980084ade24
--- /dev/null
+++ b/docs/opentitan/ot_darjeeling.md
@@ -0,0 +1,147 @@
+# Darjeeling
+
+## Supported version
+
+Please check out the `ot_darjeeling.c` file header.
+
+## Supported devices
+
+### Near feature-complete devices
+
+* [AES](ot_aes.md)
+* Alert controller
+  * ping mechanism is not supported
+* AON Timer
+* CSRNG
+* EDN
+* HMAC
+* [IBEX CPU](ibex_cpu.md)
+* [JTAG](jtag-dm.md) (compatible with OpenOCD/Spike "remote bitbang" protocol)
+* Key manager DPE
+  * Almost feature complete
+  * Missing entropy reseeding, and support for KMAC masking (when available)
+* Mailbox
+   * [JTAG mailbox](jtagmbx.md) can be accessed through JTAG using a DM-TL bridge
+* [OTBN](ot_otbn.md)
+* [OTP controller](ot_otp.md)
+  * read and write features are supported,
+  * Present scrambling is supported with digest checks,
+  * ECC (detection and correction) is supported
+  * zero-ization is not yet supported
+* [RISC-V Debug Module](jtag-dm.md) and Pulp Debug Module
+* [ROM controller](ot_rom_ctrl.md)
+* [SoC debug controller documentation](ot_soc_dbg_ctrl.md)
+* SPI data flash (from QEMU upstream w/ fixes)
+* [SPI Host controller](ot_spi_host.md)
+  * HW bus config is ignored (SPI mode, speed, ...)
+* [SPI Device](ot_spi_device.md)
+* Timer
+* [UART](ot_uart.md)
+  * missing RX timeout, TX break not supported
+  * bitrate is not paced vs. selected baurate
+
+### Partially implemented devices
+
+Devices in this group implement subset(s) of the real HW.
+
+* Clock Manager
+  * Runtime-configurable device, through properties
+  * Manage clock dividers, groups, hints, software configurable clocks
+  * Propagate clock signals from source (AST, ...) to devices
+  * Hint management and measurement are not implemented
+* DMA
+  * Only memory-to-memory transfers (inc. hashing) are supported, Handshake modes are not supported
+* Entropy Src
+   * test/health features are not supported
+* [GPIO](ot_gpio.md)
+   * A CharDev backend can be used to get GPIO outputs and update GPIO inputs
+* [I2C controller](ot_i2c.md)
+  * Supports only one target mode address - ADDRESS1 and MASK1 are not implemented
+  * Timing features are not implemented
+  * Loopback mode is not implemented
+* [Ibex wrapper](ot_ibex_wrapper.md)
+  * random source (connected to CSR), FPGA version, virtual remapper, fetch enable can be controlled
+    from Power Manager
+* KMAC
+  * Masking is not supported
+* Lifecycle controller
+  * [LC controller](lc_ctrl_dmi.md) can be accessed through JTAG using a DM-TL bridge
+  * Escalation is not supported
+* [ROM controller](ot_rom_ctrl.md)
+* SRAM controller
+  * Initialization and scrambling from OTP key supported
+  * Wait for init completion (bus stall) emulated
+* SoC Proxy only supports IRQ routing/gating
+
+### Sparsely implemented devices
+
+In this group, device CSRs are supported (w/ partial or full access control & masking) but only some
+features are implemented.
+
+* Analog Sensor Top
+  * noise source only (from host source)
+  * configurable clock sources
+* Pinmux
+  * Basic features (pull up/down, open drain) are supported for GPIO pin only
+* Power Manager
+  * Fast FSM is partially supported, Slow FSM is bypassed
+  * Interactions with other devices (such as the Reset Manager) are limited
+* [Reset Manager](ot_rstmgr.md)
+  * HW and SW reset requests are supported
+
+### Dummy devices
+
+Devices in this group are mostly implemented with a RAM backend or real CSRs but do not implement
+any useful feature (only allow guest test code to execute as expected).
+
+* Sensor
+
+### Additional devices
+
+* [DevProxy](devproxy.md) is a CharDev-enabled component that can be remotely controlled to enable
+  communication with the system-side buses of the mailboxes and DMA devices. A Python library is
+  available as `scripts/opentitan/devproxy.py` and provide an API to remote drive the devproxy
+  communication interface.
+
+## Running the virtual machine
+
+See [OpenTitan machine](ot_machine.md) documentation for options.
+
+### Arbitrary application
+
+````sh
+qemu-system-riscv32 -M ot-darjeeling,no_epmp_cfg=true -display none -serial mon:stdio \
+  -readconfig docs/config/opentitan/darjeeling.cfg \
+  -global ot-ibex_wrapper.lc-ignore=on -kernel hello.elf
+````
+
+### Boot sequence ROM, ROM_EXT, BLO
+
+````sh
+qemu-system-riscv32 -M ot-darjeeling -display none -serial mon:stdio \
+  -readconfig docs/config/opentitan/darjeeling.cfg \
+  -object ot-rom_img,id=rom,file=rom_with_fake_keys_fpga_cw310.elf \
+  -drive if=pflash,file=otp-rma.raw,format=raw \
+  -drive if=mtd,bus=0,file=flash.raw,format=raw
+````
+
+where `otp-rma.raw` contains the RMA OTP image and `flash.raw` contains the signed binary file of
+the ROM_EXT and the BL0. See [`otptool.py`](otptool.md) and [`flashgen.py`](flashgen.md) tools to
+generate the `.raw` image files.
+
+## Buses
+
+Darjeeling emulation supports the following buses:
+
+| **Type** | **Num** | **Usage**                                                  |
+| -------- | ------- | -----------------------------------------------------------|
+| `mtd`    |    0    | [SPI host](ot_spi_host.md), [SPI device](ot_spi_device.md) |
+| `pflash` |    0    | [OTP](ot_otp.md)                                           |
+
+## Tools
+
+See [`tools.md`](tools.md)
+
+## Useful debugging options
+
+See [debug option](debug.md) for details.
diff --git a/docs/opentitan/ot_earlgrey.md b/docs/opentitan/ot_earlgrey.md
new file mode 100644
index 0000000000000..61489efd39ef5
--- /dev/null
+++ b/docs/opentitan/ot_earlgrey.md
@@ -0,0 +1,141 @@
+# EarlGrey
+
+## Supported version
+
+[Earlgrey 1.0.0](https://github.com/lowRISC/opentitan/tree/earlgrey_1.0.0)
+
+## Supported devices
+
+### Near feature-complete devices
+
+* [AES](ot_aes.md)
+* Alert controller
+  * ping mechanism is not supported
+* AON Timer
+* CSRNG
+* EDN
+* [Flash controller](ot_flash.md)
+  * largely functional but without ECCs/ICVs, scrambling functionality & alerts
+  * no modelling of erase suspend or RMA entry
+  * lc_ctrl NVM debug signal not implemented, escalation partially implemented
+* HMAC
+* [IBEX CPU](ibex_cpu.md)
+* [Key manager](ot_keymgr.md)
+  * Almost feature complete
+  * Missing entropy reseeding, and support for KMAC masking (when available)
+* [OTBN](ot_otbn.md)
+* [OTP controller](ot_otp.md)
+  * read and write features are supported,
+  * Present scrambling is supported with digest checks,
+  * ECC (detection and correction) is supported
+* [ROM controller](ot_rom_ctrl.md)
+* SPI data flash (from QEMU upstream w/ fixes)
+* [SPI Host controller](ot_spi_host.md)
+  * HW bus config is ignored (SPI mode, speed, ...)
+* [SPI Device](ot_spi_device.md)
+* Timer
+* [UART](ot_uart.md)
+  * missing RX timeout, TX break not supported
+  * bitrate is not paced vs. selected baurate
+
+### Partially implemented devices
+
+Devices in this group implement subset(s) of the real HW.
+
+* Clock Manager
+  * Runtime-configurable device, through properties
+  * Manage clock dividers, groups, hints, software configurable clocks
+  * Propagate clock signals from source (AST, ...) to devices
+  * Hint management and measurement are not implemented
+* Entropy Src
+   * test/health features are not supported
+* [I2C controller](ot_i2c.md)
+  * Supports only one target mode address - ADDRESS1 and MASK1 are not implemented
+  * Timing features are not implemented
+  * Loopback mode is not implemented
+* [Ibex wrapper](ot_ibex_wrapper.md)
+  * random source (connected to CSR), FPGA version, virtual remapper, fetch enable can be controlled
+    from Power Manager
+* KMAC
+  * Masking is not supported
+* Lifecycle controller
+  * [LC controller](lc_ctrl_dmi.md) can be accessed through JTAG using a DM-TL bridge
+* [ROM controller](ot_rom_ctrl.md)
+* SRAM controller
+  * Initialization and scrambling from OTP key supported
+  * Wait for init completion (bus stall) emulated
+* [USB Device](ot_usbdev.md)
+
+### Sparsely implemented devices
+
+In this group, device CSRs are supported (w/ partial or full access control & masking) but only some
+features are implemented.
+
+* Analog Sensor Top
+  * noise source only (from host source)
+  * configurable clock sources
+* [GPIO](ot_gpio.md)
+  * Connections with pinmux not implemented (need to be ported from [Darjeeling](ot_darjeeling.md)
+    version)
+* Power Manager
+  * Fast FSM is partially supported, Slow FSM is bypassed
+  * Interactions with other devices (such as the Reset Manager) are limited
+* [Reset Manager](ot_rstmgr.md)
+  * HW and SW reset requests are supported
+
+### Dummy devices
+
+Devices in this group are mostly implemented with a RAM backend or real CSRs but do not implement
+any useful feature (only allow guest test code to execute as expected).
+Some just use generic `UNIMP` devices to define a memory region.
+
+* Pattern Generator
+* Pinmux
+* PWM
+* Sensor Control
+* System Reset Controller
+
+## Running the virtual machine
+
+See [OpenTitan machine](ot_machine.md) documentation for options.
+
+### Arbitrary application
+
+````sh
+qemu-system-riscv32 -M ot-earlgrey,no_epmp_cfg=true -display none -serial mon:stdio \
+  -readconfig docs/config/opentitan/earlgrey.cfg \
+  -global ot-ibex_wrapper.lc-ignore=on  -kernel hello.elf
+````
+
+### Boot sequence ROM, ROM_EXT, BLO
+
+````sh
+qemu-system-riscv32 -M ot-earlgrey -display none -serial mon:stdio \
+  -readconfig docs/config/opentitan/earlgrey.cfg \
+  -object ot-rom_img,id=rom,file=rom_with_fake_keys_fpga_cw310.elf \
+  -drive if=pflash,file=otp-rma.raw,format=raw \
+  -drive if=mtd,bus=2,file=flash.raw,format=raw
+````
+
+where `otp-rma.raw` contains the RMA OTP image and `flash.raw` contains the signed binary file of
+the ROM_EXT and the BL0. See [`otptool.py`](otptool.md) and [`flashgen.py`](flashgen.md) tools to
+generate the `.raw` image files.
+
+## Buses
+
+EarlGrey emulation supports the following buses:
+
+| **Type** | **Num** | **Usage**                                                    |
+| -------- | ------- | -------------------------------------------------------------|
+| `mtd`    |    0    | [SPI host 0](ot_spi_host.md), [SPI device](ot_spi_device.md) |
+| `mtd`    |    1    | [SPI host 1](ot_spi_host.md)                                 |
+| `mtd`    |    2    | [Embedded Flash](ot_flash.md)                                |
+| `pflash` |    0    | [OTP](ot_otp.md)                                             |
+
+## Tools
+
+See [`tools.md`](tools.md)
+
+## Useful debugging options
+
+See [debug option](debug.md) for details.
diff --git a/docs/opentitan/ot_eg_pad_ring.md b/docs/opentitan/ot_eg_pad_ring.md
new file mode 100644
index 0000000000000..8e7301a8a58dd
--- /dev/null
+++ b/docs/opentitan/ot_eg_pad_ring.md
@@ -0,0 +1,33 @@
+# OpenTitan Earl Grey Pad Ring
+
+## Power-on Reset (POR)
+
+The Earl Grey Pad Ring currently only supports the negated Power-on Reset (PoR) pad, which can
+be signalled by setting the `por_n` property and resetting the VM to perform a Power-on Reset.
+This can for example be done with the QEMU Monitor via the following command sequence:
+```
+> qom-set ot-eg-pad-ring.0 por_n low
+> system_reset
+> qom-set ot-eg-pad-ring.0 por_n high
+```
+
+Equivalent QMP JSON commands can also be used.
+
+Note that the current implementation directly invokes a reset request on any reset where a falling
+edge is detected (i.e. the reset strapping is asserted), and it is not well supported to "hold" the
+device in reset. If it is desired to emulate this time, you should stop and resume the VM for
+for the duration of the reset, e.g.:
+```
+/* Asserting the POR signal */
+> stop
+> qom-set ot-eg-pad-ring.0 por_n low
+> system_reset
+/* ... wait for the duration of the reset ... */
+/* De-asserting the POR signal */
+> qom-set ot-eg-pad-ring.0 por_n high
+> cont
+```
+
+## MIO Pads
+
+Currently, Earl Grey's MIO pads are not connected in the Pad Ring / Pinmux.
diff --git a/docs/opentitan/ot_flash.md b/docs/opentitan/ot_flash.md
new file mode 100644
index 0000000000000..0b223488832f6
--- /dev/null
+++ b/docs/opentitan/ot_flash.md
@@ -0,0 +1,20 @@
+# OpenTitan embedded flash
+
+* `-drive if=mtd,id=eflash,bus=<bus>,file=<filename>,format=raw` should be used to specify a path to
+  a QEMU RAW image file used as the OpenTitan internal flash controller image. This _RAW_ file
+  should have been generated with the [`flashgen.py`](flashgen.md) tool.
+
+## Machine specific options
+
+### EarlGrey Machine
+
+MTD bus 2 is assigned to the internal controller with the embedded flash storage, _i.e._ the command
+line option should be written `-drive if=mtd,id=eflash,bus=2,file=<filename>,format=raw`.
+
+### Darjeeling Machine
+
+[Darjeeling](ot_darjeeling.md) machine does not support an embedded flash device.
+
+## Notes
+
+For external SPI data flash support, see [SPI host](ot_spi_host.md) documentation.
diff --git a/docs/opentitan/ot_gpio.md b/docs/opentitan/ot_gpio.md
new file mode 100644
index 0000000000000..67a68785d5130
--- /dev/null
+++ b/docs/opentitan/ot_gpio.md
@@ -0,0 +1,136 @@
+# OpenTitan GPIO
+
+## Foreword
+
+There are two variations of the GPIO device: one for EarlGrey, one for Darjeeling variants.
+
+In the following document, `OTMACHINE` should be defined as `eg` for EarlGrey machine or as `dj`
+for Darjeeling one.
+
+## Options
+
+### Darjeeling machine
+
+When using multiple GPIO IPs, traces may become highly verbose, coming from multiple source.
+It is possible to limit the trace to a single GPIO IP, using the following option:
+
+`-global ot-gpio-dj.log_id=<ot_id>` where _ot_id_ is the OpenTitan identifier of the GPIO device.
+
+When no `log_id` option is specified, all GPIO IP may emit trace messages.
+
+#### Note
+
+This option is not supported on the [EarlGrey](ot_earlgrey.md) machine, since only one GPIO device
+instance is available.
+
+## Initial configuration
+
+It is possible to configure initial values of the GPIO pins:
+
+OpenTitan GPIO driver accept global options:
+
+- `ot-gpio-$OTMACHINE.in` defines the input values of the GPIO port as a 32-bit value
+- `ot-gpio-$OTMACHINE.out` defines the output values of the GPIO port as a 32-bit value
+- `ot-gpio-$OTMACHINE.oe` defines the output enable of the GPIO port as a 32-bit value
+
+All values default to zero, that is all GPIOs as input/hi-z, read 0.
+
+### Example
+
+```
+-global ot-gpio-dj.in=0x00ffff00 -global ot-gpio-dj.oe=0x1 -global ot-gpio-dj.out=0x1
+```
+
+Note: If there were several GPIO instances in a machine, these configurations would apply to all
+GPIO instances.
+
+## Character Device
+
+OpenTitan GPIO driver can be connected to any CharDev device to expose as a very simple ASCII data
+stream the GPIO input and output pins.
+
+This CharDev device can be used to stimulate the GPIO and perform unit tests.
+
+To connect the GPIO to its optional character device, use the following QEMU option
+
+```
+-chardev type,id=gpio -global ot-gpio-$OTMACHINE.chardev=gpio
+```
+
+where type is one of the supported QEMU chardev type, such as
+
+- serial to connect to an existing serial communication device
+- socket to use a TCP connection
+- pipe to use a local pipe
+- ...
+
+`id` is an arbitrary string that should always match the value defined with the `-global` option.
+
+## Protocol
+
+The communication protocol is ASCII based and very simple.
+Each frame follows the following format:
+
+### Format
+
+```
+<TYPE> : <HEXVALUE> <CR> <LF>
+```
+
+where:
+
+1. `TYPE` is a single uppercase char
+2. `HEXVALUE` is a 32-bit hex encoded lowercase value
+3. `CR` is the carriage return character (0x0d)
+4. `LF` is the line feed character, or end-of-line (0x0a)
+
+Each frame is delimited with `LF` characters. `CR` are ignored and accepted to ease compatibility
+with some terminals but are useless.
+
+The hex value represents the 32-bit GPIO values.
+
+#### Supported frame types
+
+A type describes the meaning of the hex value. Supported types are:
+
+* `C` clear/reset host (at QEMU start up)
+* `D` direction, _i.e._ Output Enable in OpenTitan terminology (QEMU -> host)
+* `I` input GPIO values (host -> QEMU)
+* `M` mask GPIO input values, i.e. non connected input pins (host -> QEMU)
+* `O` output GPIO values (QEMU -> host)
+* `P` output GPIO pull up/down values (QEMU -> host)
+* `Q` query input (QEMU -> host). QEMU may emit this frame, so that the host replies with a new
+  input `I` frame (hexvalue of `Q` is ignored)
+* `R` repeat (host -> QEMU). The host may ask QEMU to repeat the last `D` and `O` frames
+* `Y` forwards the GPIO input that QEMU has read to the host (QEMU -> host) for tracking purposes
+* `Z` output pull up/down GPIO HiZ values (QEMU -> host). 1 means HiZ, 0 means
+  pull up/down values apply.
+
+Frames are only emitted whenever the state of either peer (QEMU, host) change. QEMU should emit `D`
+and `O` frames whenever the GPIO configuration or output values are updated. The host should emit
+a `I` frame whenever its own input lines change.
+
+`Q` and `R` are only emitted when a host connects to QEMU or when one side resets its internal
+state.
+
+### Example
+
+The `scripts/opentitan/trellis` directory contains two Python files that may be copied to an
+an Adafruit NeoTrellis M4 Express card initialized with Circuit Python 8.0+
+
+These scripts provide a physical, visual interface to the virtual GPIO pins, which is connected to
+the QEMU machine over a serial port (a USB CDC VCP in this case).
+
+To connect to the NeoTrellis board, use a configuration such as:
+
+```
+-chardev serial,id=gpio,path=$SERIALDEV -global ot-gpio-$OTMACHINE.chardev=gpio
+```
+
+where `SERIALDEV` is the data serial port of the Neotreillis board, _e.g._ `/dev/ttyACM1`
+
+Note: the first serial port of the board is reserved to its debug console.
+
+### Testing
+
+See the [gpiodev.py](gpiodev.md) script.
diff --git a/docs/opentitan/ot_i2c.md b/docs/opentitan/ot_i2c.md
new file mode 100644
index 0000000000000..5013a508da905
--- /dev/null
+++ b/docs/opentitan/ot_i2c.md
@@ -0,0 +1,8 @@
+# OpenTitan I2C
+
+* `-device <name>,bus=<bus>,address=<address>` can be used to attach devices at a specific address
+  to one of the three I2C buses.
+
+  Bus names depends on the platform. They are usually named as `ot-i2c0` ... `ot-i2cN`.
+
+See also [I2C host proxy](i2c_host_proxy.md)
diff --git a/docs/opentitan/ot_ibex_wrapper.md b/docs/opentitan/ot_ibex_wrapper.md
new file mode 100644
index 0000000000000..8a45fab0741c3
--- /dev/null
+++ b/docs/opentitan/ot_ibex_wrapper.md
@@ -0,0 +1,39 @@
+# OpenTitan Ibex Wrapper
+
+* `-global ot-ibex_wrapper.lc-ignore=on` should be used whenever no OTP image is provided, or if
+  the current LifeCycle state stored in the OTP image does not allow the Ibex core to fetch data.
+  This switch forces the Ibex core to execute whatever the LifeCycle broadcasted signal, which
+  departs from the HW behavior but maybe helpful to run the machine without a full OTP set up. The
+  alternative to allow the Ibex core to execute guest code is to provide a valid OTP image with one
+  of the expected LifeCycle state, such as TestUnlock*, Dev, Prod or RMA.
+
+* `-global ot-ibex_wrapper.lc-ignore-ids=<ids>` acts as `lc-ignore`, enabling the selection of
+  specific ibex wrapper instance based on their unique identifiers. See `ot_id` property in the
+  machine definition file for a list of valid identifiers. `<ids>` should be defined as a comma-
+  separated list of valid identifiers. It is only possible to ignore LifeCycle states with this
+  option, not to enforce them.
+
+The `FPGA_INFO` register of the Ibex Wrapper device is used to report that the HW platform is a QEMU
+virtual machine. It contains three ASCII chars `QMU` followed with a configurable _version_ field in
+the MSB, whose meaning is not defined. It can be any 8-byte value, and defaults to 0x0. To configure
+this version field, use the `qemu_version` property of the Ibex Wrapper device.
+
+The `DV_SIM_STATUS` register (address 0 of the `DV_SIM_WINDOW`) can be used to exit QEMU with a
+passing or failing status code. The lower half of the word is written either `900d` (good) or `baad`
+(bad). If an error code is written to the upper half of the word, QEMU will exit with that status
+code for failures. The `-global ot-ibex_wrapper.dv-sim-status-exit=[on|off]` can be used to control
+whether QEMU shuts down when this register is written.
+
+There are two modes to handle address remapping, with different limitations:
+
+- default mode: use an MMU-like implementation (via ot_vmapper) to remap addresses. This mode
+  enables to remap instruction accesses and data accesses independently, as the real HW. However,
+  due to QEMU limitations, addresses and mapped region sizes should be aligned and multiple of 4096
+  bytes, i.e. a standard MMU page size. This is the recommended mode.
+
+- legacy mode: This mode has no address nor size limitations, however it cannot distinguish
+  instruction accesses from data accesses, which means that both kind of accesses must be defined
+  for each active remapping slot for the remapping to be enabled. Moreover it relies on MemoryRegion
+  aliasing and may not be as robust as the default mode. It is recommended to use the default mode
+  whenever possible. To enable this legacy mode, set the `alias-mode` property to true:
+  `-global ot-ibex_wrapper.alias-mode=true`
diff --git a/docs/opentitan/ot_keymgr.md b/docs/opentitan/ot_keymgr.md
new file mode 100644
index 0000000000000..f36eb1b8aa7bb
--- /dev/null
+++ b/docs/opentitan/ot_keymgr.md
@@ -0,0 +1,14 @@
+# OpenTitan Key Manager support
+
+## Properties
+
+- `-global ot-keymgr.disable-flash-seed-check=true` can be used to disable the
+data validity check in the Keymgr for loaded flash secrets (the owner and
+creator seed). This validity check ensures that the loaded key is not all-zero
+or all-one (and thus probably uninitialized). When emulating OpenTitan, it may
+be useful to be able to advance using uninitialized keys due to a lack of flash
+info splicing, to bypass the need to run through an entire provisioning flow.
+  - Note also that the fatal Keymgr alert caused by failing this check should
+  not appear for unprovisioned flash if flash scrambling is implemented (and
+  enabled). This is because the garbage unscrambled data that is read will not
+  pass this check.
diff --git a/docs/opentitan/ot_machine.md b/docs/opentitan/ot_machine.md
new file mode 100644
index 0000000000000..146a9a3be9079
--- /dev/null
+++ b/docs/opentitan/ot_machine.md
@@ -0,0 +1,24 @@
+# OpenTitan machine
+
+### Machine configuration
+
+To start up an OpenTitan virtual machine, a configuration file is required. See [OT config](otcfg.md)
+documentation for details. The configuration file should be specified with the `-readconfig` option.
+
+### `-M <machine>` optional arguments
+
+* `no_epmp_cfg=true` can be appended to the machine option switch, _i.e._
+  `-M ot-earlgrey,no_epmp_cfg=true` to disable the initial ePMP configuration, which can be very
+  useful to execute arbitrary code on the Ibex core without requiring an OT ROM image to boot up.
+
+* `ignore_elf_entry=true` can be appended to the machine option switch, _i.e._
+  `-M ot-earlgrey,ignore_elf_entry=true` to prevent the ELF entry point of a loaded application to
+  update the vCPU reset vector at startup. When this option is used, with `-kernel` option for
+  example, the application is loaded in memory but the default machine reset vector is used.
+
+* `verilator=true` can be appended to the machine option switch, to select Verilator lowered clocks:
+  _i.e._ `-M ot-earlgrey,verilator=true` to select Verilator reduced clock rates. It enables to run
+  FW which has been built for the Verilator target in OpenTitan main repository.
+
+See also [ot-ibex_wrapper.lc-ignore option](ot_ibex_wrapper.md) to enable VM start up without a
+valid [OTP](ot_otp.md) image file.
diff --git a/docs/opentitan/ot_otbn.md b/docs/opentitan/ot_otbn.md
new file mode 100644
index 0000000000000..f06ee1683392c
--- /dev/null
+++ b/docs/opentitan/ot_otbn.md
@@ -0,0 +1,9 @@
+# OpenTitan OTBN
+
+* `-global ot-otbn.logfile=<filename>` output OTBN execution message to the specified logfile. When
+  _logasm_ option (see below) is not enabled, only execution termination and error messages are
+  logged. `stderr` can be used to log the messages to the standard error stream instead of a file.
+
+* `-global ot-otbn.logasm=<true|false>` dumps executed instructions on OTBN core into the _logfile_
+  filename. Beware that this further slows down execution speed, which could likely result in the
+  guest application on the Ibex core to time out.
diff --git a/docs/opentitan/ot_otp.md b/docs/opentitan/ot_otp.md
new file mode 100644
index 0000000000000..0b03a138a0faf
--- /dev/null
+++ b/docs/opentitan/ot_otp.md
@@ -0,0 +1,10 @@
+# OpenTitan OTP
+
+* `-drive if=pflash,file=otp.raw,format=raw` should be used to specify a path to a QEMU RAW image
+  file used as the OpenTitan OTP image. This _RAW_ file should have been generated with the
+  [`otptool.py`](otptool.md) tool.
+
+* on LC escalate reception, it is possible to early abort VM execution. Specify
+  `-global ot-otp-<top>.fatal_escalate=true` to enable this feature.
+  where `top` should be defined as `eg` for the [EarlGrey](ot_earlgrey.md) machine, or `dj` for the
+  [Darjeeling](ot_darjeeling.md) machine.
diff --git a/docs/opentitan/ot_rom_ctrl.md b/docs/opentitan/ot_rom_ctrl.md
new file mode 100644
index 0000000000000..fc7d36c19bb5f
--- /dev/null
+++ b/docs/opentitan/ot_rom_ctrl.md
@@ -0,0 +1,101 @@
+# OpenTitan ROM Controller
+
+The OpenTitan ROM Controller computes a digest of the ROM content on boot, using one of the
+application interfaces of the KMAC. When the ROM check is complete, the ROM Controller sends a
+signal to the Power Manager. This triggers CPU startup if the ROM check was successful.
+
+On real hardware, the ROM digest is computed on the ROM content _including ECC_ and the expected
+digest value is stored at the end of the scrambled ROM (with invalid ECC to make sure it's not
+accessible by software).
+
+On the QEMU emulated ROM Controller, if the ROM controller is submitted a scrambled ROM image file,
+its digest is used and verified. Otherwise, a fake digest is generated, i.e. no actual ROM content
+validation is performed.
+
+## QEMU ROM Options
+
+### Supported image file formats
+
+The type of a ROM image file format is automatically detected from its content.
+
+The ROM file digest can be provided on the QEMU command line using this option:
+
+```
+-object ot-rom_img,id=<romid>,file=/path/to/rom
+```
+
+#### ELF ROM file
+
+ELF32 RISC-V file can be used as a ROM controller image file. Such file format neither supports
+digest nor ECC. Digest is faked in this case.
+
+#### VMEM ROM file
+
+Two kinds of VMEM files are supported:
+
+* 32-bit VMEM files, _i.e._ VMEM file without ECC. Such file should contain non-scrambled data.
+* 39-bit VMEM files, _i.e._ VMEM file with 7-bit ECC and scrambled data.
+
+39-bit scrambled ECC VMEM files are only supported when the QEMU machine has instantiated the ROM
+controller with `key` and `nonce` arguments.
+
+#### HEX ROM file
+
+39-bit HEX files, _i.e._ HEX file with 7-bit ECC and scrambled data.
+
+39-bit scrambled ECC HEX files are only supported when the QEMU machine has instantiated the ROM
+controller with `key` and `nonce` arguments.
+
+Note that HEX file format differs from IHEX file format. The former only contains hexadecimal-
+encoded data, where the two first digits contain the 7-bit ECC value, and the remaining digits
+contains the 32-bit data value.
+
+#### Binary ROM file
+
+Flat, raw binary file can be used as a ROM controller image file. Such file format neither supports
+digest nor ECC. Digest is faked in this case.
+
+### ROM identifiers [#romid]
+
+The ROM image ID may depend on the SoC.
+
+* for EarlGrey which has a single ROM, the ID is expected to be `rom`.
+* for a SoC with two ROMs, the IDs would be expected to be `rom0` and `rom1`.
+* for a machine with multiple SoCs, the IDs would be additionally prefixed with the SoC name and a
+  full stop, _e.g._ `soc0.rom0`
+
+### ROM unscrambling constants
+
+Each machine and each ROM controller uses a different pair of (key, nonce) constants to unscramble
+the ROM content.
+
+These constants may be defined in the machine, or in an external configuration file so that these
+constants are present neither in the QEMU source code nor the QEMU binary. The standard QEMU
+`-readconfig <file.cfg>` may be used to load those constants.
+
+See [OpenTitan configuration file](otcfg.md) for details.
+
+## Booting with and without ROM
+
+### With ROM
+
+This mode is useful to implement the standard OpenTitan boot flow.
+
+In this mode, the ROM digest is always checked against the expected digest value if a scrambled ROM
+image file is submitted.
+
+### Without ROM
+
+This mode is useful when starting an application using `-kernel` QEMU option: the application starts
+directly at CPU reset.
+
+If no ROM image is specified on QEMU command line (or if the ROM image does not have the expected ID
+for the machine), it does not prevent the CPU from starting:
+- ROM Controller provides an empty ROM region
+- ROM Controller activates _fake digest_ mode: digest is computed on the empty ROM region and
+  expected digest value is faked. ROM is "valid" so signal is sent to Power Manager to start the
+CPU.
+
+When the `-kernel` option is used, the default `resetvec` of the machine is overridden with the
+entry point defined in the ELF file. The default `mtvec` is not modified - it is expected the ELF
+early code updates the `mtvec` with a reachable location if no ROM is used.
diff --git a/docs/opentitan/ot_rstmgr.md b/docs/opentitan/ot_rstmgr.md
new file mode 100644
index 0000000000000..b825c8c9b7741
--- /dev/null
+++ b/docs/opentitan/ot_rstmgr.md
@@ -0,0 +1,9 @@
+# OpenTitan Reset Manager
+
+It is possible to limit the number of times the VM reboots the guest. This option may be useful
+during the development process when an issue in the early FW stages - such as the ROM - causes an
+endless reboot cycles of the guest.
+
+To limit the reboot cycles, use the `-global ot-rstmgr.fatal_reset=<N>` option, where `N` is an
+unsigned integer. This option forces the QEMU VM to exit the N^th^ time the reset manager receives
+a reset request, rather than rebooting the whole machine endlessly as the default behavior.
diff --git a/docs/opentitan/ot_soc_dbg_ctrl.md b/docs/opentitan/ot_soc_dbg_ctrl.md
new file mode 100644
index 0000000000000..e0fbcc1b1aa05
--- /dev/null
+++ b/docs/opentitan/ot_soc_dbg_ctrl.md
@@ -0,0 +1,11 @@
+# OpenTitan SoC Debug controller
+
+SoC debug controller manages SoC debug policies based on external signals - such as GPIO, Power
+Manager states and LifeCycle states, the later being defined from the OTP content. If no OTP image
+is provided, or a RAW (blank) image is provided, or if the OTP image defines a LifeCycle in any of
+TEST* or RMA states, a Darjeeling machine that features a SoC Debug controller may enter the DFT
+("Debug For Test") execution mode, where the Ibex core may not resume execution till a JTAG debugger
+triggers it.
+
+To force QEMU to execute an application despite this feature, bypassing the DFT mode, use
+`-global ot-socdbg_ctrl.dft-ignore=on` QEMU option.
diff --git a/docs/opentitan/ot_spi_device.md b/docs/opentitan/ot_spi_device.md
new file mode 100644
index 0000000000000..e5907a639b0fe
--- /dev/null
+++ b/docs/opentitan/ot_spi_device.md
@@ -0,0 +1,131 @@
+# OpenTitan SPI Device
+
+## Supported modes
+
+### Flash mode
+
+This mode is fully supported (to the extent of the understanding of the HW...).
+
+### Passthrough mode
+
+This mode is supported, with minor deficiencies: The two-stage read pipeline, and dummy cycle
+counts of 1 to 7 are not supported as SPI transfers are modelled with byte-granularity (see the
+[CharDev protocol](#spi-device-chardev-protocol)). For commands with 1 to 7 dummy cycles specified,
+the maximum 8 dummy cycles (1 dummy byte) will be used.
+
+### TPM
+
+This mode is partially supported, TPM commands handled by hw are not supported yet. The CharDev
+protocol doesn't support a distinct chip select for TPM, therefore it is sharing the same CS with
+the other modes. If CS is asserted and TPM is enabled, the TPM will have priority.
+
+## Connection with a SPI Host
+
+### CharDev simple bus header
+
+To communicate with the SPI device emulation, it is possible to create and use any QEMU CharDev.
+
+The CharDev is expected to used as a full bi-directional, stream based, asynchronous communication
+channel.
+
+CharDev always output as many payload bytes as it receives, like a regular SPI bus.
+
+### Creating QEMU SPI Device CharDev
+
+The most common/useful CharDev for SPI device is to use a TCP communication stream, which can be
+instantiated this way from the command line:
+
+````
+-chardev socket,id=spidev,host=localhost,port=8004,server=on,wait=off
+````
+
+Note that `opentitantool` and association library do support this protocol when the `qemu` backend
+is used:
+
+````
+opentitantool --interface qemu --help
+A tool for interacting with OpenTitan chips.
+
+Usage: opentitantool [OPTIONS] <COMMAND>
+
+Commands:
+  ...
+  spi        Commands for interacting with a SPI EEPROM
+  ...
+      --qemu-host <QEMU_HOST>                            [default: localhost]
+      --qemu-spidev-port <QEMU_SPIDEV_PORT>              [default: 8004]
+````
+
+IT is also possible to use [`spidevflash.py`](spidevflash.md) tool to upload a binary using the same
+protocol.
+
+### SPI Device CharDev protocol
+
+SPI clock is not emulated, but each byte exchanged over the communication channel represent 8-bit
+SPI data. Dual and Quad lines are not emulated, all communications happen over a regular byte
+stream - which does not prevent from using dual or quad SPI flash commands.
+
+As some out-of-band or metadata is required, for example the status of the /CS line, a small header
+is inserted by the SPI host for each SPI communication packet in the MOSI stream. There is no such
+header inserted into the stream for the MISO channel. Moreover as the SPI header contains the length
+of the payload, it also acts as a SPI packet delimiter. Each time the SPI host peer is disconnected,
+the /CS line and the SPI device state machine are reset so it is possible to recover from a
+corrupted communication w/o exiting QEMU.
+
+A packet is limited to a payload of 65536 bytes, however an SPI transaction may extend over several
+SPI communication packets.
+
+A CharDev communication is always initiated by the remote SPI host. It transmits the 8-byte SPI
+device header described below, where the first word can be considered as a magic number, and
+the last word describes the payload that comes right after the header. The payload should contain
+the <length> count of bytes (SPI MOSI data). The SPI device should start receiving the very same
+<length> count of bytes (SPI MISO data). In other words, the payload in both direction have always
+the same amount of bytes.
+
+The host-to-device stream always starts with a 8-byte header, and there is no header, i.e. only
+payload in the device-to-host stream. The header <c> bit defines whether the host releases the /CS
+line once the SPI transfer is over, or whether the SPI device should expect a continuation SPI
+transfer, which is always prefixed with another header. The last SPI transfer of a SPI transaction
+should release the /CS line, i.e. <c> should be 0.
+
+````
+ Time -->
+
+ MOSI: | Header1 | TX Payload1 <x bytes> | Header2 | TX Payload2 <y bytes> |
+                 \                       \         \                       \
+ MISO:            | RX Payload1 <x bytes> |         | RX Payload2 <y bytes> |
+````
+
+````
+       +---------------+---------------+---------------+---------------+
+       |       0       |       1       |       2       |       3       |
+       +---------------+---------------+---------------+---------------+
+       |0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F|
+ 0x00 -+---------------+---------------+---------------+---------------+
+       |      '/'      |      'C'      |      'S'      |    version    |
+ 0x04 -+---------------+---------------+---------------+---------------+
+       |p|a|t|r|  -  |c|       -       |      length (Byte count)      |
+ 0x08 -+---------------+---------------+---------------+---------------+
+       |               |               |               |               |
+ 0x0c -+---------------+---------------+---------------+---------------+
+       |                             . . .                             |
+      -+---------------+---------------+---------------+---------------+
+       |               |
+      -+---------------+
+````
+
+  - `version`: protocol version, current version uses 0.
+  - `length`: count of payload bytes (does not need to be a multiple of 4)
+  - `p`: polarity, should match `CFG.CPOL` (not yet supported)
+  - `a`: phase, should match `CFG.CPHA` (not yet supported)
+  - `t`: tx order, see `CFG.TX_ORDER` (not yet supported)
+  - `r`: rx order, see `CFG.RX_ORDER` (not yet supported)
+  - `c`: whether to keep _/CS_ low (=1) or release _/CS_ (=0) when payload has been processed. Any
+    SPI transaction should end with C=0 packet. However it is possible to use several SPI device
+    CharDev packets to handle a single SPI transaction: example: JEDEC ID w/ continuation code,
+    polling for BUSY bit, ...
+
+Note that SPI device support bit reversing for both TX and RX, the bit configuration in the SPI
+device header is only used for debugging (tracking configuration mismatch between the host and the
+device). Polarity and Phase are not emulated however SPI stream is explicitly corrupted (bit
+inversion) if CPOL/CPHA do not match between host and device.
diff --git a/docs/opentitan/ot_spi_host.md b/docs/opentitan/ot_spi_host.md
new file mode 100644
index 0000000000000..569e18703bafb
--- /dev/null
+++ b/docs/opentitan/ot_spi_host.md
@@ -0,0 +1,44 @@
+# OpenTitan SPI Host
+
+* `-drive if=mtd,bus=<bus>,file=<filename>,format=raw` should be used to specify a path to a QEMU RAW
+  image file used as the SPI data flash backend file. This _RAW_ file should have been created with
+  the qemu-img tool. There is no dedicated tool to populate this image file for now.
+
+  ````sh
+  qemu-img create -f raw spi.raw 16M
+  ````
+
+  See the machine section for supported `<bus>` values.
+
+* `-global ot-spi_host.start-delay=<time>` may be used to change the default SPI Host FSM start
+  delay. This delay is used to yield back the control to the vCPU before kicking of the execution
+  of a new SPI Host command, so that the guest code gets a chance to check the statuses of the SPI
+  Host right after pushing the command. Without this delay, the SPI Host state may change quickly
+  and report statuses that might be different than the real HW, _e.g._ a command may already be
+  completed when the guest code reads back the SPI Host status. Time should be specified in ns,
+  and defaults to 20000 (20 µs).
+
+* -`global ot-spi_host.completion-delay=<time>` may be forced to discard the experimental SPI Host
+  clock pacing, which helps to achieve the requested bandwidth on the SPI Host bus, which is always
+  caped with the performances of the QEMU host. Forcing a small value here can help achieving the
+  best SPI Host transfer performances, but decreases accuracy of the SPI Host clock settings. Time
+  should be specified in ns, and defaults to 0 that indicates automatic SPI bus clock management.
+
+## Machine specific options
+
+### EarlGrey Machine
+
+MTD bus 0 is assigned to the SPI0 Host controller and MTD bus 1 is assigned to the SPI1 Host
+controller. See also the [Embedded Flash controller](ot_flash.md) documentation.
+
+* `-global ot-earlgrey-board.spiflash<bus>=<flash_type>` should be used to instantiate a SPI
+  dataflash device of the specified type to the first device (/CS0) of the specified bus.
+  Any SPI dataflash device supported by QEMU can be used. To list the supported devices, use
+  `grep -F 'INFO("' hw/block/m25p80.c | cut -d'"' -f2`
+
+### Darjeeling Machine
+
+MTD bus 0 is assigned to the unique SPI0 Host controller.
+
+The Darjeeling machine is configured with an ISSP IS25WP128 SPI data flash device. It is not
+possible to select another SPI data flash device model from the command line.
diff --git a/docs/opentitan/ot_uart.md b/docs/opentitan/ot_uart.md
new file mode 100644
index 0000000000000..f5540802d171d
--- /dev/null
+++ b/docs/opentitan/ot_uart.md
@@ -0,0 +1,39 @@
+# OpenTitan UART
+
+## Connecting to the UART
+
+* `-serial mon:stdio`, used as the first `-serial` option, redirects the virtual UART0 to the
+  current console/shell.
+
+* `-chardev socket,id=serial1,host=localhost,port=8001,server=on,wait=off` and
+  `-serial chardev:serial1` can be used to redirect UART1 (in this example) to a TCP socket. These
+  options are not specific to OpenTitan emulation, but are useful to communicate over a UART.
+  Note that QEMU offers many `chardev` backends, please check QEMU documentation for details.
+
+## Sending Break Conditions
+
+Break conditions can be sent to the UART on select supported CharDev backends (telnet, mux) or by
+sending the `chardev-send-break` command with the CharDev ID via the QEMU Monitor. Break conditions
+are treated as transient events and the length of time of a break condition is not considered.
+
+## Oversampling
+
+OpenTitan's UART has a `VAL` register which oversamples the RX pin 16 times per bit. This cannot be
+emulated by QEMU which uses a CharDev backend and does not have a notion of accurate sampling times.
+
+If software wishes to poll the `VAL` register to determine break conditions, there are some
+properties available to help with emulating this use case:
+
+* `-global ot-uart.oversample-break=true` is used to enable UART break oversampling. This will
+  attempt to display 16 samples of the last bit received in the `VAL` register, which will be 16
+  high bits after any UART frame is transmitted (as these end with a stop bit, which is high), or 16
+  low bits if the UART previously received a break condition and has not received any frames since.
+  That is, enabling this property assumes that transmitted break conditions are "held" until the
+  next UART transfer in terms of what is being shown in the oversampled `VAL` register.
+
+* `-global ot-uart.toggle-break=true` is used to provide more control over "holding" the UART RX
+  break condition like a GPIO strap, and changes the behavior of a UART such that received break
+  condition events now *toggle* the break condition state rather than keeping it asserted until the
+  next transfer. This allows any device talking to OpenTitan via UART to have more precise control
+  over when the UART VAL register displays idle and when it displays a break condition, as it can
+  precisely toggle the break condition on or off like a GPIO strapping being held down.
diff --git a/docs/opentitan/ot_usbdev.md b/docs/opentitan/ot_usbdev.md
new file mode 100644
index 0000000000000..19415b69de382
--- /dev/null
+++ b/docs/opentitan/ot_usbdev.md
@@ -0,0 +1,321 @@
+# OpenTitan USBDEV
+
+**Warning:** the USBDEV driver is still in development and not expected to work at the moment!
+
+## `usbdev-cmd` Chardev
+
+The USBDEV driver exposes a chardev with ID `usbdev-cmd` which can used to control some aspects of
+the emulation.
+Once connected, the driver accepts textual commands.
+Each command must end with a newline.
+The following commands are recognized:
+- `vbus_on`: turn on VBUS, see [VBUS handling](#VBUS-handling) for more details.
+- `vbus_off`: turn off VBUS, see [VBUS handling](#VBUS-handling) for more details.
+
+## `usbdev-host` Chardev
+
+The USBDEV driver exposes a chardev with ID `usbdev-host` which can used to simulate the presence
+of a USB host.
+The implementation is such that the USBDEV behaves as a server, waiting for a connection from a
+virtual host.
+Once connected, the host and device exchange  binary commands following the protocol described in
+the [host simulation](#host-simulation) section.
+
+## VBUS handling
+
+On a real machine, the VBUS sense pin is usually connected to the VBUS connector so that the chip
+can detect when a cable is plugged in.
+For the purpose of emulation, a different approach needs to be taken. The driver supports two modes
+of operation which are controlled by the `vbus-override` property which can be set on the
+command-line by `-global ot-usbdev.vbus-override=<mode>`.
+The following modes are supported:
+
+- `vbus-override=on`: in this mode, the VBUS sense pin is entirely managed over the `usbdev`
+  chardev.
+  By default, the sense pin will be set to level low. The `vbus_on` and `vbus_off` commands
+  can be used to change the value of the sense pin. Note that in this mode, the VBUS sense signal
+  will be completely independent of the presence of a USB host.
+- `vbus-override=off`: in this mode, the `vbus_on` and `vbus_off` commands control a virtual "VBUS
+  enable" gate. The VBUS sense pin will be reported as level high if and only if the VBUS enable
+  gate is enabled **and** a USB host has enabled VBUS (see [host simulation](#host-simulation))
+  By default, the VBUS gate is enabled.
+
+## Host simulation
+
+The QEMU USBDEV driver only simulates a USB device controller (UDC) which requires the presence
+of a USB host.
+A (virtual) host exchanges messages with the UDC over the
+[`udev-host` chardev](#usbdev-host-chardev).
+This binary protocol is somewhat similar to the [USB/IP][usbip] protocol but lower level.
+This protocol is also different from the [USB network redirection (a.k.a usbredir)][usbredir]
+protocol supported by QEMU.
+
+[usbip]: (https://docs.kernel.org/usb/usbip_protocol.html)
+[usbredir]: (https://gitlab.freedesktop.org/spice/usbredir/-/blob/main/docs/usb-redirection-protocol.md)
+
+### Rationale for a different protocol
+
+Both the USB/IP and usbredir protocols are too high-level for the purpose of emulating and testing
+a low-level UDC driver.
+For example, both protocols require that the device be fully enumerated and configured before the
+host is even made aware of its presence.
+In contrast, we want to be able to fully emulate the enumeration sequence.
+Another big difference is bus management: USB/IP does not support bus resets and usbredir does not
+support resume/suspend, and neither models VBUS.
+This is a side-effect of the intended use case of these protocols: to connect a real USB device to
+a virtual USB host.
+However, this new protocol should be low-level enough that it is possible to implement a bridge
+from either usbredir or USB/IP to this protocol (while losing some features).
+
+### High-level overview
+
+This protocol does not specify which of the device or the host should be the client/guest.
+On connection, the client must send a [`Hello` command](#hello-command), to which the server must
+respond with another `Hello` command.
+After that, messages are exchanged asynchronously.
+
+#### Bus states
+
+The protocol reflects the low-level details of the USB bus and provides independent handling of
+VBUS (controlled by the host) and connection (controlled by the device).
+The host can turn VBUS on and off at any point. When VBUS is on, the device can freely connect or
+disconnect by asynchronously sending a message to the host.
+As on a real bus, turning off VBUS disconnects the device.
+VBUS is assumed to be initially off.
+
+It is an error for the device to send a message when VBUS is not on and the host must ignore such
+messages.
+However due to the asynchronous nature of the protocol, it is possible for the host to receive a
+message event *after* sending a `VBUS Off` message which was sent *before* reception of this
+message by the device.
+The ID of the message makes it clear when this is the case so that the host can safely ignore those
+messages.
+
+When VBUS is turned on, the host assumes that the device is *not* connected. The device must send
+a `Connect` message to notify the host.
+
+While VBUS is turned on, the host can reset, suspend or resume the device.
+As on a real bus, the device will become unconfigured after a bus reset and an enumeration sequence
+must be performed.
+
+**TODO** Clarify suspend/resume
+
+### Packet format
+
+The protocol is based on packets which are exchanged asynchronously by the device and host.
+Each packet starts with a header followed by a payload.
+All fields are in little-endian.
+
+| **Field** | **Offset** | **Size** | **Value** |
+| --------- | ---------- | -------- | --------- |
+| Command   |      0     |     4    | Command number (see below) |
+| Size      |      4     |     4    | Size of the payload (header excluded)
+| Packet ID |      8     |     4    | Unique ID used to match responses |
+
+The host must increase the ID of its message by one each time it sends a message.
+The ID used by the device is defined in the respective sections of their commands.
+
+The following commands are defined.
+
+| **Command** | **Value** | **Direction** | **Description** | **Reference** |
+| ----------- | --------- | ------------- | --------------- | ------------- |
+| Invalid     |     0     | N/A           |  To avoid 0 meaning something | |
+| Hello       |     1     | Both          | First packet sent when connecting | [Hello command](#hello-command) |
+| VBUS On     |     2     | Host to device | Turn VBUS on | [Bus commands](#bus-commands) |
+| VBUS Off    |     3     | Host to device | Turn VBUS off | [Bus commands](#bus-commands) |
+| Connect     |     4     | Device to host | Report device connection | [Bus commands](#bus-commands) |
+| Disconnect  |     5     | Device to host | Report device disconnection | [Bus commands](#bus-commands) |
+| Reset       |     6     | Host to device | Reset the device | [Bus commands](#bus-commands) |
+| Resume      |     7     | Host to device | Resume the device | [Bus commands](#bus-commands) |
+| Suspend     |     8     | Host to device | Suspend the device | [Bus commands](#bus-commands) |
+| Setup       |     9     | Host to device | Send a SETUP packet | [Setup command](#setup-command) |
+| Transfer    |    10     | Host to device | Start a transfer | [Transfer command](#transfer-command) |
+| Complete    |    11     | Device to host | Complete a transfer | [Complete command](#complete-command) |
+| Cancel      |    12     | Host to device | Cancel a transfer | [Cancel command](#cancel-command) |
+
+
+
+#### Hello command
+
+The ID of this command must be 0.
+The payload of this command is defined as follows.
+
+| **Field** | **Offset** | **Size** | **Value** |
+| --------- | ---------- | -------- | --------- |
+| Magic value |      0   |     4    | String `UDCX` |
+| Major version |   4    |     2    |      1    |
+| Minor version |   6    |     2    |     0     |
+
+#### Bus commands
+
+These commands (VBUS On/Off, (Dis)connection, Reset, Suspend/Resume) do not have any payload.
+See the [bus states](#bus-states) section for more detail.
+
+For the Connect/Disconnect commands, which are sent by the device, the ID should be the ID of the
+*last command* processed by the device.
+
+Sending a `Reset`, `VBUS Off` or `Suspend` command to the device automatically cancels any pending
+`Transfer` command.
+The device *may* send a `Complete` event with the `Cancelled` status for such transfers.
+
+#### Setup command
+
+This command is used to send a SETUP packet to the device.
+The payload of this command starts with a header defined as follows.
+See [Transfer handling](#transfer-handling) for more details.
+
+| **Field** | **Offset** | **Size** | **Value** |
+| --------- | ---------- | -------- | --------- |
+| Address   |     0      |    1     | Device address |
+| Endpoint  |     1      |    1     | Endpoint number |
+| Reserved  |     2      |    2     | Set to zero |
+| Setup     |     4      |    8     | SETUP packet |
+
+Sending a `Setup` command to an endpoint automatically cancels any pending transfer on this
+endpoint.
+The device *may* send a `Complete` event to the host with the `Cancelled` status.
+
+#### Transfer command
+
+This command is used to start a transfer to or from the device.
+See [Transfer handling](#transfer-handling) for more details.
+The payload of this command is defined below.
+
+| **Field** | **Offset** | **Size** | **Value** |
+| --------- | ---------- | -------- | --------- |
+| Address   |     0      |    1     | Device address |
+| Endpoint  |     1      |    1     | Endpoint (see below) |
+| Packet Size |   2      |    2     | Packet size (see [Transfer handling](#transfer-handling)) |
+| Flags     |     4      |    1     | Transfer flags (see below) |
+| Reserved  |     5      |    3     | Set to 0 |
+| Transfer Size |  8     |    4     | Size of the data |
+| Data      |     12     | variable | Transfer data (see below) |
+
+The `Endpoint` field is encoded as follows:
+| **Field** | **Bits** | **Value** |
+| --------- | -------- | -------- |
+| EP Number | 3:0      | The endpoint number |
+| Reserved  | 6:4      | Set to 0 |
+| Direction | 7        | Set to 1 for IN endpoint and 0 for OUT endpoint |
+
+Note that when submitting a control transfer, the `Direction` field must be set to indicate whether
+this is control OUT or IN transaction.
+
+The following flags are defined.
+
+| **Flag** | **Bit** | **Meaning** |
+| -------- | ------- | ----------- |
+| ZLP      |    0    | A zero-length packet must be sent after the data (only valid for OUT transfers) |
+
+For OUT transfers, the `Transfer Size` field indicates the size of the data in the payload after
+the header.
+For IN transfers, the `Transfer Size` field indicates the maximum size of the transfers to return
+to the host.
+
+Sending a `Transfer` command to an endpoint while one is already in progress is an error.
+The device must immediately reply with a `Complete` event with the `Error` status.
+
+#### Cancel command
+
+See [Transfer handling](#transfer-handling) for more details.
+The payload of this command is defined as follows.
+
+| **Field** | **Offset** | **Size** | **Value** |
+| --------- | ---------- | -------- | --------- |
+| Transfer ID |   0      |     4    | ID of the transfer to cancel |
+
+#### Complete command
+
+The ID of this command must be the ID of the corresponding `Transfer` command.
+See [Transfer handling](#transfer-handling) for more details.
+The payload of this command is defined as follows.
+
+| **Field** | **Offset** | **Size** | **Value** |
+| --------- | ---------- | -------- | --------- |
+| Status    |     0      |     1    | Status of the transfer (see below) |
+| Reserved  |     1      |     3    | Set to 0 |
+| Transfer Size | 4      |     4    | Amount of data transferred |
+| Data      |     8      | variable | Transfer data (see below) |
+
+The `Transfer Size` field indicates the size of the data.
+The data must only be present when completing an IN transaction.
+
+The following status codes are defined:
+
+| **Status** | **Value** | **Meaning** |
+| -------- | ------- | ----------- |
+| Success  |    0    | The data was successfully transferred |
+| Stalled  |    1    | The device stalled the transfer |
+| Cancelled |    2   | Transfer was cancelled (see below) |
+| Error    |    3    | An unspecified error occurred |
+
+A transfer may be cancelled by any bus event such a turning VBUS off, the device disconnecting,
+the host resetting or suspending the device, or the host sending a `Setup` command.
+
+
+### Transfer handling
+
+In order to perform data transfers, the host must send a correct sequence of Setup and Data
+commands, in accordance to the USB specification.
+The protocol is designed to be very low-level and only provides minimal help.
+The host is allowed to send non-spec compliant sequences to fuzz the device.
+For properly sequenced transfers, the host should follow the guidelines below.
+
+Note that the `Transfer` command allows the host to send/receive more data than the indicated
+packet size.
+In this case, the transfer will automatically be split into multiple packets of size `Packet Size`.
+For OUT transfers, all packets except possibly the last one will be of the size indicated in the
+command.
+For IN transfers, the transfer stops as soon as a short packet is received (packet of size less
+than the one indicated in the command).
+If the `ZLP` flag is set for an OUT transfer, the device will additionally receive a zero-length
+packet.
+If at any point during this sequence, the device stalls the transfer, the transfer stops and the
+device must send a `Complete` event to the host with the `Stalled` status and the `Size` field
+indicating how much data was transferred successfully (and for IN transfers, the data must be
+present in the payload).
+If the transfer succeeds, the device must send a `Complete` event with the `Success` status, the
+`Size` field indicating how much data was transferred successfully (and for IN transfers, the data
+must be present in the payload).
+
+Upon receiving a `Cancel` command, the device must stop the requested transfer as soon as possible
+and send a `Complete` event with the `Cancel` status. Note that due to the asynchronous nature
+of the protocol, the following sequences of events are possible:
+- the device receives a `Cancel` command for an already completed transfer: the device must ignore
+  the request,
+- the device receives a `Cancel` command for a transfer but the transfer finishes before it can
+  be cancelled: the device must send a `Complete` event, which can either be `Cancelled` or the
+  otherwise normal status of the transfer.
+
+### Control transfers
+
+The host should first send a `Setup` command at the selected address and endpoint.
+The device does not reply to this command. Note that the USB specification specifies that sending
+a SETUP packet to an endpoint immediately cancels any transaction on this endpoint.
+The device *may* send `Complete` events for such transfers with the `Cancelled` status.
+
+The rest of the sequence depends on the direction of the transfer:
+- OUT transfers: the host should send one or more `Transfer` commands to the endpoint
+  (with the OUT direction) with the control data and the device answers with `Complete` events.
+  Once all transfers are complete, the host should send a `Transfer` command to the endpoint
+  with the IN direction and `Size` set to 0, to which the device answers with a `Complete` event.
+- IN transfers: the host should send one or more `Transfer` commands to the endpoint,
+  (with the IN direction) and the device answers with `Complete` events containing the data.
+  Once all transfers are complete, the host should send a `Transfer` command to the endpoint
+  with the OUT direction and `Size` set to 0, to which the device answers with a `Complete` event.
+
+### Bulk and interrupt transfers
+
+TODO
+
+### Cancelling transfers
+
+If the host wishes to cancel a pending transfer, it must send the `Cancel` command with the ID
+of the corresponding `Transfer` command to be cancelled. Due to the asynchronous nature of
+the protocol, it is possible that the transfer successfully completes before the device processes
+the `Cancel` request. Therefore the host *should* wait for a `Complete` event to determine the
+final outcome of the transfer.
+
+## Note
+
+Note: There is no USB device on the [Darjeeling machine](ot_darjeeling.md)
diff --git a/docs/opentitan/otcfg.md b/docs/opentitan/otcfg.md
new file mode 100644
index 0000000000000..577b682d89466
--- /dev/null
+++ b/docs/opentitan/otcfg.md
@@ -0,0 +1,109 @@
+# OpenTitan configuration file
+
+Some OpenTitan configuration parameters are sensitive enough to avoid storing them into the QEMU
+source code nor the built QEMU binary.
+
+Such configuration parameters are - but not limited to -:
+* Keys
+* Nonces
+* Seeds
+* Tokens
+* ...
+
+It is required to load a selected list of configuration parameters from a QEMU configuration file
+that the QEMU executable loads at startup, which enables to store those sensitive parameters into
+a different location than the QEMU source code and executable.
+
+This configuration file, whose syntax is loosely based on the INI file format, should be specified
+with the `-readconfig <file.cfg>` QEMU option.
+
+Depending on the machine, the parameters may either override default constants defined in the source
+code - such as default cryptographic constants that are already exposed in the public OpenTitan
+repository - or be required in the configuration file for the matching device to become functional.
+
+⚠️ Beware **not** to store such a configuration file into a public repository if it contains
+   production data!
+
+## Default configuration files
+
+Default configuration files with can be found in the `docs/config/opentitan` directory. Be sure to
+select the file whose filename matches the OpenTitan machine.
+
+## Syntax
+
+All sections in the configuration files should follow the following scheme:
+`[ot_device "<device>[<.ot_id>"]`, where `<device>` is the mandatory OpenTitan device name, and
+`<ot_id>` is an optional device instance identifier.
+
+When no `<ot_id>` identifier is provided, the parameter within the sections are applied to all
+instances of the selected device.
+
+The separator between the `<device>` and the `<ot_id>` parameter should be a single dot `.`.
+
+The remaining line of the section are (key, value) pairs, expressed as `<key> = <value>`. The `key`
+is always a string which is one of the device's supported properties. The value may either be a
+string, a unsigned 64-bit integer or boolean, which should match the type of the selected property.
+
+### Example
+
+```ini
+[ot_device "ot_dev"]
+a_string_prop = "abcde"
+an_integer = 0x1234
+a_boolean = true
+```
+
+## Generation
+
+It is possible to delegate the generation of an OpenTitan configuration file to the [`cfggen.py`](cfggen.md)
+script, using an existing OpenTitan repository.
+
+## Configurable constants
+
+Constants can usually be retrieved from the OpenTitan autogenerated "top" HSJON file, from the
+`hw/<topname>/data/autogen/<topname>.gen.hjson` file.
+
+### ROM controller [rom]
+
+```ini
+[ot_device "ot-rom_ctrl.<romid>"]
+  # 128-bit key, match RndCnstRomCtrl*ScrKey
+  key = "ffeeddccbbaa99887766554433221100"
+  # 64-bit nonce, match RndCnstRomCtrl*ScrNonce
+  nonce = "0123456789abcdef"
+```
+where `<romid>` is the ROM identifier as documented [here](ot_rom_ctrl.md#romid)
+
+### OTP controller [otp]
+
+```ini
+[ot_device "ot-otp-dj"]
+  # 256-bit scramble key, match RndCnstOtpCtrlScrmblKeyInit
+  scrmbl_key = "ffeeddccbbaa99887766554433221100ffeeddccbbaa99887766554433221100"
+  # consistency digest
+  digest_const = "ffeeddccbbaa99887766554433221100"
+  digest_iv = "0123456789abcdef"
+  # SRAM data key
+  sram_const = "ffeeddccbbaa99887766554433221100"
+  sram_iv = "0123456789abcdef"
+  # 20-byte sequence of the first non-RAW life cycle state (LC_STATE_TESTUNLOCKED0)
+  lc_state_first = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+  # 20-byte sequence of the last valid life cycle state (LC_STATE_SCRAP)
+  lc_state_last = "bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb"
+  # 24-byte sequence for the first non-RAW transition count (#1)
+  lc_trscnt_first = "cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc"
+  # 24-byte sequence for the last transition count (#24)
+  lc_trscnt_last = "dddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd"
+```
+
+Here, `digest_const` is expected to match the `--constant` argument of the [otptool.py](otptool.md)
+tool, whereas `digest_iv` is expected to match its `--iv` argument. Should those values differ,
+OpenTitan OTP controller would fail to verify the OTP partition digests.
+
+### Life-Cycle controller [lifecycle]
+
+```ini
+[ot_device "ot-lc_ctrl"]
+  # 128-bit token
+  raw_unlock_token = "ffeeddccbbaa99887766554433221100"
+```
diff --git a/docs/opentitan/otpdm.md b/docs/opentitan/otpdm.md
new file mode 100644
index 0000000000000..49a17ab74ec12
--- /dev/null
+++ b/docs/opentitan/otpdm.md
@@ -0,0 +1,139 @@
+# `dtm.py`
+
+`otpdm.py` gives access to the OTP Controller through the JTAG/DTM/DM interface.
+
+## Usage
+
+````text
+usage: otpdm.py [-h] [-H HOST] [-P PORT] [-Q] [-l IR_LENGTH] [-b BASE] [-j HJSON] [-a ADDRESS]
+                [-p PARTITION] [-i ITEM] [-L] [-r] [-w WRITE] [-D] [-v] [-d]
+
+OTP controller access through the RISC-V Debug Module
+
+options:
+  -h, --help            show this help message and exit
+
+Virtual machine:
+  -H HOST, --host HOST  JTAG host (default: localhost)
+  -P PORT, --port PORT  JTAG port, default: 3335
+  -Q, --no-quit         do not ask the QEMU to quit on exit
+
+DMI:
+  -l IR_LENGTH, --ir-length IR_LENGTH
+                        bit length of the IR register
+  -b BASE, --base BASE  define DMI base address
+
+OTP:
+  -j HJSON, --otp-map HJSON
+                        input OTP controller memory map file
+  -a ADDRESS, --address ADDRESS
+                        base address the OTP controller, default: 0x30130000
+  -p PARTITION, --partition PARTITION
+                        select a partition
+  -i ITEM, --item ITEM  select a partition item
+  -L, --list            list the partitions and/or the items
+  -r, --read            read the value of the selected item
+  -w WRITE, --write WRITE
+                        write the value to the selected item
+  -D, --digest          show the OTP HW partition digests
+
+Extras:
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode````
+````
+
+### Arguments
+
+* `-a` specify an alternative address for the OTP controller on the OT bus.
+
+* `-b` specify the DMI base address for the RISC-V Debug Module.
+
+* `-D` show partition digest(s). If no partition is selected (see option `-p`), the digest of all
+       partitions are shown; otherwise the digest of the selected partition is shown. Requires
+       option `-j`.
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-H` specify the address of the QEMU VM.
+
+* `-i` select a specific item from a partition. See option `-L` to get a list of valid item names
+       for the currently selected partition. Requires `-p` option.
+
+* `-j` specify the path to the OpenTitan OTP controller map, _e.g._ `otp_ctrl_mmap.hjson`.
+
+* `-L` list the names of the partitions if no partition is selected (see option `-p`). If option
+       `-p` is used, list the names of the selected partition items if no item is selected (see
+       option `-i`). If option `-i` is used, show all the properties of the selected item.
+
+* `-l` specify the length of the TAP instruction register length.
+
+* `-P` specify the TCP port of the JTAG server in the QEMU VM, should follow the TCP setting of the
+  `-chardev socket,id=taprbb,...` option for invoking QEMU.
+
+* `-p` select a partition using its name. See option `-L` to get a list of valid partition names.
+       Requires option `-j`.
+
+* `-Q` do not send QEMU a request for termination when this script exits.
+
+* `-r` load and show the value of the selected item. Requires options `-p` and `-i`.
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+* `-w` store the value into the selected item. Requires options `-p` and `-i`. The value should be
+       specified as an hexadecimal or decimal integer for item whose size is less or equal to 8
+       bytes. For larger items the value should be specified as a sequence of hexa-encoded bytes.
+
+### Examples
+
+Running QEMU VM with the `-chardev socket,id=taprbb,host=localhost,port=33355,server=on,wait=off`
+option:
+
+* List all supported partitions
+  ````sh
+  ./scripts/opentitan/otpdm.py -j .../otp_ctrl_mmap.hjson -L
+  ````
+
+* List all supported items of a partition
+  ````sh
+  ./scripts/opentitan/otpdm.py -j .../otp_ctrl_mmap.hjson -p HW_CFG1 -L
+  ````
+
+* List all properties of an item
+  ````sh
+  ./scripts/opentitan/otpdm.py -j .../otp_ctrl_mmap.hjson -p HW_CFG1 -i EN_SRAM_IFETCH -L
+  ````
+
+* Show all digests
+  ````sh
+  ./scripts/opentitan/otpdm.py -j .../otp_ctrl_mmap.hjson -D
+  ````
+
+* Show the digest of a single partition (parsable output)
+  ````sh
+  ./scripts/opentitan/otpdm.py -j .../otp_ctrl_mmap.hjson -p HW_CFG1 -D
+  ````
+
+* Read the value of an item along with the item properties
+  ````sh
+  ./scripts/opentitan/otpdm.py -j .../otp_ctrl_mmap.hjson -p HW_CFG1 -i EN_SRAM_IFETCH -r
+  ````
+
+* Read the value of an item along (parsable output)
+  ````sh
+  ./scripts/opentitan/otpdm.py -j .../otp_ctrl_mmap.hjson -p HW_CFG1 -i EN_SRAM_IFETCH -r
+  ````
+
+* Write the value of an integer item
+  ````sh
+  ./scripts/opentitan/otpdm.py -j .../otp_ctrl_mmap.hjson -p HW_CFG1 -i EN_SRAM_IFETCH -w 0xff
+  ````
+
+* Write the value of a long item
+  ````sh
+  ./scripts/opentitan/otpdm.py -j .../otp_ctrl_mmap.hjson -p HW_CFG0 -i DEVICE_ID \
+    -w 4c6f72656d20697073756d20646f6c6f722073697420616d65742c20636f6e73
+  ````
+
+### Troubleshooting
+
+See the [Troubleshooting](jtag-dm.md#troubleshooting) section for details.
diff --git a/docs/opentitan/otptool.md b/docs/opentitan/otptool.md
new file mode 100644
index 0000000000000..8474d04ffd99f
--- /dev/null
+++ b/docs/opentitan/otptool.md
@@ -0,0 +1,359 @@
+# `otptool.py`
+
+`otptool.py` is a tool to deal with QEMU OT RAW image files, which are managed by the OpenTitan OTP
+controller virtual device.
+
+## Usage
+
+````text
+usage: otptool.py [-h] [-j HJSON] [-m VMEM] [-l SV] [-o FILE] [-r RAW]
+                  [-x VMEM] [-X VMEM] [-k {auto,otp,fuz}] [-e BITS]
+                  [-C CONFIG] [-c INT] [-i INT] [-w] [-n] [-f PART:FIELD]
+                  [--force-absorb] [--no-version] [-s] [-E] [-D] [-U]
+                  [-g {LCVAL,LCTPL,PARTS,REGS}] [-F] [-G PART]
+                  [--change PART:FIELD=VALUE] [--empty PARTITION]
+                  [--erase PART:FIELD] [--clear-bit CLEAR_BIT]
+                  [--set-bit SET_BIT] [--toggle-bit TOGGLE_BIT]
+                  [--write ADDR/HEXBYTES] [--patch-token NAME=VALUE]
+                  [--out-kind {qemu,bmtest}] [--top-name TOP_NAME] [-v] [-d]
+
+QEMU OT tool to manage OTP files.
+
+options:
+  -h, --help            show this help message and exit
+
+Files:
+  -j, --otp-map HJSON   input OTP controller memory map file
+  -m, --vmem VMEM       input VMEM file
+  -l, --lifecycle SV    input lifecycle system verilog file
+  -o, --output FILE     output filename (default to stdout)
+  -r, --raw RAW         QEMU OTP raw image file
+  -x, --export VMEM     Export data to a VMEM file
+  -X, --export-verbose VMEM
+                        Export data to a VMEM file with field info
+
+Parameters:
+  -k, --kind {auto,otp,fuz}
+                        kind of content in VMEM input file, default: auto
+  -e, --ecc BITS        ECC bit count
+  -C, --config CONFIG   read Present constants from QEMU config file
+  -c, --constant INT    finalization constant for Present scrambler
+  -i, --iv INT          initialization vector for Present scrambler
+  -w, --wide            use wide output, non-abbreviated content
+  -n, --no-decode       do not attempt to decode OTP fields
+  -f, --filter PART:FIELD
+                        filter which OTP fields are shown
+  --force-absorb        force absorption
+  --no-version          do not report the OTP image version
+
+Commands:
+  -s, --show            show the OTP content
+  -E, --ecc-recover     attempt to recover errors with ECC
+  -D, --digest          check the OTP HW partition digest
+  -U, --update          update RAW file after ECC recovery or bit changes
+  -g, --generate {LCVAL,LCTPL,PARTS,REGS}
+                        generate code, see doc for options
+  -F, --fix-ecc         rebuild ECC
+  -G, --fix-digest PART
+                        rebuild HW digest
+  --change PART:FIELD=VALUE
+                        change the content of an OTP field
+  --empty PARTITION     reset the content of a whole partition, including its
+                        digest if any
+  --erase PART:FIELD    clear out an OTP field
+  --clear-bit CLEAR_BIT
+                        clear a bit at specified location
+  --set-bit SET_BIT     set a bit at specified location
+  --toggle-bit TOGGLE_BIT
+                        toggle a bit at specified location
+  --write ADDR/HEXBYTES
+                        write bytes at specified location
+  --patch-token NAME=VALUE
+                        change a LC hashed token, using Rust file
+  --out-kind {qemu,bmtest}
+                        select output format for code generation (default:
+                        qemu)
+  --top-name TOP_NAME   optional top name for code generation (default: auto)
+
+Extras:
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+This script can be used for several purposes:
+
+1. Creating a QEMU OT OTP image file that is used as the OTP or Fuse controller backend, from a
+   VMEM file that is generated when the HW files are created,
+2. Showing and decoding the content of OTP image files, whether it is a pristine generated file
+   or a file that has been modified by the QEMU machine,
+3. Verifying the Digest of the OTP partitions that support HW digest (using Present scrambling),
+4. Create QEMU C source files containing definition values that replicate the ones generated when
+   the OT HW is built.
+
+Please note that only the first feature is supported for Fuse (non-OpenTitan) images.
+
+### QEMU OTP RAW image versions
+
+There are two versions of the RAW image file:
+
+v1 and v2 differs from the presence or not of the Present scrambling constants. When a QEMU OTP RAW
+image file contains the constants, the v2 format is used, otherwise the v1 format is used. The
+script supports both versions.
+
+Fuse RAW images only use the v1 type.
+
+### Arguments
+
+* `-c` specify the finalization constant for the Present scrambler used for partition digests.
+  This value is "usually" found within the `hw/ip/otp_ctrl/rtl/otp_ctrl_part_pkg.sv` OT file,
+  from the last entry of `RndCnstDigestConst` array, _i.e._ item 0. It is used along with option
+  `-D` to verify partition digests, and stored in the optional QEMU OTP RAW image file for use by
+  the virtual OTP controller when used along with the `-r` option.
+
+* `-C` specify a QEMU [configuration file](otcfg.md) from which to read the Present constants that
+  are required for digest computation. It is a convenience switch to replace both `-i` and options.
+  See [`cfggen.py`](cfggen.md) tool to generate such a file.
+
+* `-c` specify the initialization constant for the Present scrambler used for partition digests.
+  This option is required when `-D` Present digest checking is used. See also `-i` option switch.
+  Override option `-C` if any.
+
+* `-D` performs a partition digest checks for all partitions with a defined digest. The Present
+  constant should be defined to perform digest verification. They can be specified with the `-c` and
+  `-i` options switches, or when using a QEMU OTP RAW v2 file that stores these constants, or when
+  a QEMU configuration file is specified with the `-C` option.
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-E` use ECC data to fix recoverable errors
+
+* `-e` specify how many bits are used in the VMEM file to store ECC information.
+
+* `-F` may be used to rebuild the ECC values for all slots that have been modified using any
+  modification operation, and any detected error.
+
+* `-f` select which partition(s) and partition field(s) should be shown when option `-s` is used.
+  When not specified, all partitions and fields are reported.
+
+* `-G` can be used to (re)build the HW digest of a partition after altering one or more of its
+  fields, see `--change` option.
+
+* `-g` can be used to generate skeleton files, from OTP and LifeCycle known definitions. See the
+  [Generation](#generation) section for details. See option `-o` to specify the path to the file to
+  generate. See also the `--out-kind` option for output formats.
+
+* `-i` specify the initialization vector for the Present scrambler used for partition digests.
+  This value is "usually" found in `otp_ctrl_part_pkg.sv` OT file, from the last entry of
+  `RndCnstDigestIV` array, _i.e._ item 0. It is used along with option `-D` to verify partition
+  digests, and stored in the optional output OTP image file for use by the virtual OTP controller
+  when used along with the `-o` option. Override option `-C` if any.
+
+* `-j` specify the path to the HJSON OTP controller map file, usually named `otp_ctrl_mmap.hjson`.
+  This file is required with many options when the OTP image file needs to be interpreted, such as
+  digest verification, content dump, C file generation, ...
+
+* `-k` specify the kind of input VMEM file, either OTP or Fuse kind. The script attempts to detect
+  the kind of the input VMEM file from its content when this option is not specified or set to
+  `auto`. It is fails to detect the file kind or if the kind needs to be enforced, use this option.
+
+* `-l` specify the life cycle system verilog file, usually named `lc_ctrl_state_pkg.sv`, that
+  defines the encoding of the life cycle states. This option is not required to generate a RAW image
+  file, but required when the `-L` option switch is used.
+
+* `-m` specify the input VMEM file that contains the OTP fuse content. See also the `-k` option.
+
+* `-n` tell the script not to attempt to decode the content of encoded fields, such as the hardened
+  booleans values. When used, the raw value of each field is printed out.
+
+* `-o` specify the path to the output C file to generate, see `-G` option. If not specified, the
+  generated file is emitted on the standard output.
+
+* `-r` specify the path to the QEMU OTP RAW image file. When used with the `-m` option switch, a
+  new QEMU OTP image file is generated. Otherwise, the QEMU OTP RAW image file should exist and is
+  used as the data source for the OTP content, such as content decoding and digest verification.
+
+* `-s` decodes some of the content of the OTP fuse values. This option requires the `-j` option.
+
+* `-U` when a RAW file is loaded, update its contents after bit modification changes or ECC
+  recovery. This option is mutually exclusive with VMEM
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+* `-w` tell the script not to truncate the values of the large fields, _i.e._ the fields than
+  contain long sequence of bytes. If repeated, the empty long fields are also printed in full, as
+  a sequence of empty bytes.
+
+* `-X` similar to `-x` option, with extra comment in generated file to document each generated VMEM
+  line with the partition and field description.
+
+* `-x` export the current data and ECC content into a text file using the VMEM 24 encoding format,
+  _i.e._ 24-bit hex chunks where the first byte depicts the 6-bit ECC and the remaining two bytes
+  contain a 16-bit value.
+
+* `--clear-bit` clears the specified bit in the OTP data. This flag may be repeated. This option is
+  only intended to corrupt the OTP content so that HW & SW behavior may be exercised should such
+  a condition exists. See [Bit position syntax](#bit-syntax) for how to specify a bit.
+
+* `--change` updates the value of a field in the specified partition. The flag may be repeated.
+  Note that changing the partition content without specifying the `-F` flag may result into a
+  corrupted partition. `otptool.py` accepts the following value syntax:
+
+  - `"string"` or `'string'`: an arbitrary string, which is automatically encoded into UTF8 raw
+    bytes. Note that the shell may interpret the single or double quote characters, so it may be
+    required to use `'part:field="string"'` as the argument to bypass any shell replacement,
+  - `true`, `false`, `on`, `off`, `enabled`, `disabled` as a boolean specifier. The boolean value is
+    encoded according to the OTP map into an hardened boolean or a MUBI value,
+  - an hexadecimal value starting with with `0x`
+  - a string of hexadecimal nibbles, _e.g._ `01020304abcdef`, which is converted into raw bytes
+
+  If the partition field is larger than the specified value, the value is left-extended with NUL
+  bytes. Values larger than the partition field length are rejected.
+
+* `--empty` reset a whole partition, including its digest if any and ECC bits. This option is only
+  intended for test purposes. This flag may be repeated. Partition(s) can be specified either by
+  their index or their name.
+
+* `--erase` reset a specific field within a partition. The flag may be repeated.
+
+* `--force-absorb` force allocation of aborbable free space. Input HJSON map files already define
+  absorbable space allocated to absorbable partitions. This option forces absorbable space
+  allocation. It may be removed in a future version.
+
+* `--no-version` disable OTP image version reporting when `-s` is used.
+
+* `--out-kind` define the output format for code generation for the `-g` option. Note that only a
+  subset of the generation types are available in some output kinds.
+
+* `--patch-token` patch a Life Cycle hashed token. This feature is primary aimed at testing the
+  Life Cycle controller. With this option, the partition to update is automatically found using
+  the token `NAME`. If the partition containing the token to update is already locked, its digest is
+  automatically patched; otherwise the digest is left empty. The token `VALUE` should be specified
+  as a hexadecimal string with no `0x` prefix. The token value is expected to be the plaintext
+  token, as the script takes care of hashing it and storing the hashed value into the OTP image.
+  To change a LC token file with an immediate value with no further processing, see the `--change`
+  option.
+
+* `--set-bit` sets the specified bit in the OTP data. This flag may be repeated. This option is
+   only intended to corrupt the OTP content so that HW & SW behavior may be exercised should such
+   a condition exists. See [Bit position syntax](#bit-syntax) for how to specify a bit.
+
+* `--toggle-bit` toggles the specified bit in the OTP data. This flag may be repeated. This option
+  is only intended to corrupt the OTP content so that HW & SW behavior may be exercised should such
+  a condition exists. See [Bit position syntax](#bit-syntax) for how to specify a bit.
+
+* `--top-name` defines the OpenTitan top name for some code generation feature. It overrides any
+  top name that may be automatically retrieved from the configuration file hierarchy.
+
+* `--write` overrides any data (not ECC). If can be combined with `--fix-ecc` to automatically
+  rebuild the ECC of the data slot that have been altered. This option may be repeated. The argument
+  should comply with the `offset/hexdata` syntax, where the _offset_ part is defined in the
+  [Bit position syntax](#bit-syntax) and _hexdata_ is a byte sequence specified as a hexadecimal
+  string.
+
+All modification features can only be performed on RAW image, VMEM images are never modified. To
+modify RAW file content, either a VMEM file is required in addition to the RAW file as the data
+source, or the `-U` is required to tell that the RAW file should be read, modified and written back.
+
+#### Note
+
+Earlgrey OTP virtual device has not been updated to support Present scrambler, so neither `-c` nor
+`-i` option should be used to generate an Earlgrey-compatible RAW image.
+
+### Bit position specifier [#bit-syntax]
+
+`--clear-bit` and `--set-bit` options expect the location of the bit to alter. The syntax to specify
+a bit is defined as `<offset>/<bit>` where `offset` is the byte offset in the OTP data stream and
+`bit` is the bit within the specified location.
+
+The address is rounded down to the granule size, _e.g._ if OTP fuses are organized as 16-bit slots,
+address 2N and 2N+1 are considered the same.
+
+As a special syntax, offset may be specified as `0h...`, in which case the offset value is doubled,
+which enables to directly specify the half-word offset encoded in the input VMEM 24 file. For
+example, to write at @0006, either use `0xc` or `0h6` as the offset specifier.
+
+If the bit is larger than the data slot, it indicates the location with the ECC part, _e.g._ if OTP
+fuses are organized as 16-bit slots with 6-bit ECC, bit 0 to 15 indicates a bit into the data slot,
+while bit 16 to 21 indicates an ECC bit.
+
+It is possible to tell the script to rebuild the ECC value for the modified bits, using `-F`.
+The default behavior is to not automatically update the ECC value, as the primary usage for these
+bit modification operations is to test the error detection and correction feature.
+
+### Generation [#generation]
+
+The generation feature may be used to generate part of the OTP and LifeCycle QEMU implementation,
+based on known definitions from the OpenTitan constants. This option accepts on of the following
+argument:
+
+* `LCVAL` generates a file describing the LifeCycle constants as C arrays. Requires `-l` option.
+* `LCTPL` generates a file describing the LifeCycle State encoding as a C array. . Requires `-l`
+  option.
+* `PARTS` generates a file describing the OTP partition properties as C arrays. Requires `-j`
+  option.
+* `REGS` generates a file describing the OTP partition registers as C definitions. Requires `-j`
+  option.
+
+ See `-o` to specify an output file for the generated file.
+
+### Examples
+
+Generate a QEMU RAW v1 image for the virtual OTP controller, here with an RMA OTP configuration:
+````sh
+scripts/opentitan/otptool.py -m img_rma.24.vmem -r otp.raw [-k otp]
+````
+
+Generate a QEMU RAW v1 image for the virtual OTP controller, here with an RMA OTP configuration:
+````sh
+scripts/opentitan/otptool.py -m fusemap.hex -r fuse.raw [-k fuz]
+````
+
+The following examples only apply with the OpenTitan OTP image files:
+
+Generate a QEMU RAW v2 image for the virtual OTP controller, here with an RMA OTP configuration:
+````sh
+scripts/opentitan/otptool.py -m img_rma.24.vmem -r otp.raw \
+    -i 0x0123456789abcdef -c 0x00112233445566778899aabbccddeeff
+````
+
+Generate a QEMU RAW v2 image for the virtual OTP controller, here with an RMA OTP configuration,
+load Present constants from a QEMU configuration file.
+````sh
+scripts/opentitan/otptool.py -m img_rma.24.vmem -r otp.raw -i docs/config/opentitan/earlgrey.cfg
+````
+
+Decode the content of an OTP VMEM file:
+````sh
+scripts/opentitan/otptool.py -m img_rma.24.vmem -j otp_ctrl_mmap.hjson -s
+````
+
+Decode the content of a QEMU OTP RAW file:
+````sh
+scripts/opentitan/otptool.py -r otp.raw -j otp_ctrl_mmap.hjson -s
+````
+
+Decode the content of a QEMU OTP RAW file along with the lifecycle information:
+````sh
+scripts/opentitan/otptool.py -r otp.raw -j otp_ctrl_mmap.hjson -l lc_ctrl_state_pkg.sv -s
+````
+
+Verify the HW digests of a QEMU OTP RAW v2 file:
+````sh
+scripts/opentitan/otptool.py -r otp.raw -j otp_ctrl_mmap.hjson -D
+````
+
+Verify the HW digests of a QEMU OTP RAW v1 file:
+````sh
+scripts/opentitan/otptool.py -r otp.raw -j otp_ctrl_mmap.hjson -D \
+    -i 0x0123456789abcdef -c 0x00112233445566778899aabbccddeeff
+````
+
+Generate a C source file with LifeCycle constant definitions:
+````sh
+scripts/opentitan/otptool.py -g LCVAL -l lc_ctrl_state_pkg.sv -o lc_state.c
+````
+
+Generates a C source file with OTP partition properties:
+````sh
+scripts/opentitan/otptool.py -j otp_ctrl_mmap.hjson -g PARTS -o otp_part.c
+````
diff --git a/docs/opentitan/pymod.md b/docs/opentitan/pymod.md
new file mode 100644
index 0000000000000..1275998dfab55
--- /dev/null
+++ b/docs/opentitan/pymod.md
@@ -0,0 +1,29 @@
+# Python modules for OpenTitan machines
+
+The communication ports of the OpenTitan machines exposed through CharDev devices can be used
+to access the devices from the local host (or also from a remote host when the CharDev is created
+using a TCP socket).
+
+* `python/qemu/jtag`: JTAG / TAP controller client, using the _Remote BitBang Protocol_
+* `python/qemu/ot`: OpenTitan tools
+  * `devproxy`: implementation of the communication channel with the QEMU devproxy device.
+  * `dm`: RISC-V Debug Module support,
+  * `dtm`: Debug Transport Module support,
+  * `eflash`: Embedded Flash support,
+  * `gpio`: GPIO support,
+  * `km`: Key Manager support,
+  * `lc_ctrl`: [Life Cycle controller](lc_ctrl_dmi.md) over JTAG/DMI support,
+  * `mailbox`: support for accessing the responder and the requester sides of the DOE mailbox. Also
+    support the [JTAG mailbox](jtagmbx.md) for accessing the mailbox from a JTAG/DMI link,
+  * `otp`: support for parsing and verifying OTP VMEM images, as well as generating and decoding
+     QEMU RAW image files,
+  * `pyot`: implements the Python OpenTitan test orchestrator tool,
+  * `rom`: support for parsing and verifying ROM images,
+  * `socdbg`: support for communication with the SoC debug module of DMI,
+  * `spi`: support SPI device communication, _i.e._ acts as a SPI master connected to QEMU SPI
+     device port,
+  * `util`: miscellaneous utililies such as ELF format tools and logging utilities,
+     scrambler/descrambler used in OTP image files for HW digest verification.
+
+Please check the [Python tools](tools.md) documentation for details and scripts that rely
+on these APIs.
diff --git a/docs/opentitan/pyot.md b/docs/opentitan/pyot.md
new file mode 100644
index 0000000000000..31801c18bcd36
--- /dev/null
+++ b/docs/opentitan/pyot.md
@@ -0,0 +1,593 @@
+# `pyot.py`
+
+`pyot.py` is a tool to run OpenTitan tests on QEMU and report results.
+
+## Usage
+
+````text
+usage: pyot.py [-h] [-A] [-D DELAY] [-i ICOUNT] [-L FILE] [-M VARIANT]
+               [-N LOG] [-m MACHINE] [-Q OPTS] [-q QEMU] [-P VCP] [-p DEVICE]
+               [-S SOC] [-s] [-t TRACE|FILE] [-U] [-b file] [-c HJSON]
+               [-e BUS] [-f RAW] [-g CFGFILE] [-H] [-K] [-l file] [-O RAW]
+               [-o VMEM] [-r ELF] [-w CSV] [-x file] [-X] [-F TEST]
+               [-k SECONDS] [-z] [-R] [-T FACTOR] [-Z] [-d] [-G] [-V] [-v]
+               [--log-file FILE] [--log-udp UDP_PORT] [--quiet]
+               [--debug LOGGER] [--info LOGGER] [--warn LOGGER]
+
+OpenTitan QEMU unit test sequencer.
+
+options:
+  -h, --help            show this help message and exit
+
+Virtual machine:
+  -A, --asan            redirect address sanitizer error log stream
+  -D, --start-delay DELAY
+                        QEMU start up delay before initial comm
+  -i, --icount ICOUNT   virtual instruction counter with 2^ICOUNT clock ticks
+                        per inst. or 'auto'
+  -L, --qemu-log FILE   log file for trace and log messages
+  -M, --variant VARIANT
+                        machine variant (machine specific)
+  -N, --log LOG         log message types
+  -m, --machine MACHINE
+                        virtual machine (default to ot-earlgrey)
+  -Q, --opts OPTS       QEMU verbatim option (may be repeated)
+  -q, --qemu QEMU       path to qemu application (default: build/qemu-system-
+                        riscv32-unsigned)
+  -P, --vcp VCP         serial port devices (default: use serial0)
+  -p, --device DEVICE   serial port device name / template name (default to
+                        localhost:8000)
+  -S, --first-soc SOC   Identifier of the first SoC, if any
+  -s, --singlestep      enable "single stepping" QEMU execution mode
+  -t, --trace TRACE|FILE
+                        enable trace (may be repeated)
+  -U, --muxserial       enable multiple virtual UARTs to be muxed into same
+                        host output channel
+
+Files:
+  -b, --boot file       bootloader 0 file
+  -c, --config HJSON    path to HJSON configuration file
+  -e, --embedded-flash BUS
+                        generate an eflash image file for MTD bus
+  -f, --flash RAW       SPI flash image file
+  -g, --otcfg CFGFILE   configuration option file for OT devices
+  -H, --no-flash-header
+                        application and/or bootloader files contain no OT
+                        header
+  -K, --keep-tmp        Do not automatically remove temporary files and dirs
+                        on exit
+  -l, --loader file     ROM trampoline to execute, if any
+  -O, --otp-raw RAW     OTP image file
+  -o, --otp VMEM        OTP VMEM file
+  -r, --rom ELF         ROM file (may be repeated, in load order)
+  -w, --result CSV      path to output result file
+  -x, --exec file       application to load
+  -X, --rom-exec        load application as ROM image (default: as kernel)
+
+Execution:
+  -F, --filter TEST     run tests with matching filter, prefix with "!" to
+                        exclude matching tests
+  -k, --timeout SECONDS
+                        exit after the specified seconds (default: 60 secs)
+  -z, --list            show a list of tests to execute and exit
+  -R, --summary         show a result summary
+  -T, --timeout-factor FACTOR
+                        timeout factor
+  -Z, --zero            do not error if no test can be executed
+
+Extras:
+  -d                    enable debug mode
+  -G, --log-time        show local time in log messages
+  -V, --vcp-verbose     increase verbosity of QEMU virtual comm ports
+  -v, --verbose         increase verbosity
+  --log-file FILE       copy log messages to a file
+  --log-udp UDP_PORT    change UDP port for log messages, use 0 to disable
+  --quiet               quiet logging: only be verbose on errors
+  --debug LOGGER        assign debug level to logger(s)
+  --info LOGGER         assign info level to logger(s)
+  --warn LOGGER         assign warning level to logger(s)
+````
+
+This tool may be used in two ways, which can be combined:
+
+* From the command line, it is possible to run a QEMU test session for one application.
+* Using a HJSON configuration file, it is possible to run several QEMU test sessions for each
+  specified test in the configuration file. This mode is enabled when a HJSON config file is
+  specified.
+
+### Virtual machine
+
+* `-A` / `--asan` filter address sanitizer traces and report them as log traces
+* `-D` / `--start-delay` VM start up delay. Grace period to wait for the VM to start up before
+  attempting to communicate with its char devices.
+* `-i` / `--icount` to specify virtual instruction counter with 2^N clock ticks per instruction.
+  Use 'auto' to enable QEMU adaptive icount counter. Note that this option slows down the execution
+  of guest applications.
+* `-L` / `--log_file` specify the log file for trace and log messages from QEMU.
+* `-N` / `--log` specify which log message types should be logged; most useful types are:
+  * `in_asm`/`A` for guest instruction disassembly,
+  * `unimp`/`U` for uimplemented guest features,
+  * `int`/`I` for guest interrupts and exceptions,
+  * `guest_errors`/`G` for unexpected guest behavior,
+  * `exec`/`E` for guest execution stream (caution: highly verbose).
+  These definitions may be abbreviated using their upper case, single char variants, _e.g._
+  `-N GIU` would enable _guest_errors_, _interruptions_ and _unimplemented features_ logs.
+* `-M` / `--variant` specify a variant of the selected machine. The accepted values depend on the
+  machine, see `-m` option.
+* `-m` / `--machine` specify the kind of virtual machine to run.
+* `-q` / `--qemu` specify an alternative path to the QEMU application.
+* `-Q` / `--opts` add a single QEMU option forwarded verbatim to QEMU (no check is performed)
+   * Note that it is easier to use the special option marker `--` to append many options to QEMU:
+     any argument after this marker is forwarded verbatim to QEMU.
+* `-p` / `--device` specify an alternative TCP communication channel. This option should only be
+  used if the default channel is already in use.
+* `-S` / `--first-soc` define the name of the first SoC to boot, if any. This flag is only used to
+  prefix property names
+* `-s` / `--singlestep` enable QEMU "single stepping" mode.
+* `-t` / `--trace` add trace message. May be repeaded. Either specified an event definition file,
+  or a trace event name. To obtain a list of available traces, invoke with `-trace help`.
+* `-T` / `--timeout-factor` apply a multiplier factor to all timeouts. Specified as a real number,
+  it can be greater to increase timeouts or lower than 1 to decrease timeouts.
+* `-U` / `--muxserial` enable muxing QEMU VCP. This option is required when several virtual UARTs
+  are routed to the same host output channel.
+
+### Files
+
+* `-b` / ` --boot`  specify a bootloader 0 file that can be added to the flash image file when
+  a ROM extension file is specified with the `-x` option. This option is mutually exclusive with
+  the `-f` option.
+* `-c` / `--config` specify a HJSON configuration file, see the [Configuration](#Configurationfile)
+  section for details.
+* `-e` / `embedded-flash` generate an embedded flash image file for the specified MTD bus. The
+  default is to provide ROM and application files as device options.
+* `-f` / `--flash` specify a RAW image file that stores the embedded Flash content, which can be
+   generated with the [`flashgen.py`](flashgen.md) tool. Alternatively, see the `-x` option.
+* `-g` / `--otcfg` specify a configuration file with OpenTitan configuration options, such as
+   clock definitions, cryptographic constants (seeds, keys, nonces, ...). May be repeated.
+* `-H` / `--no-flash-header` executable files should be considered as raw files with no OpenTitan
+  flash headers.
+* `-K` / `--keep-tmp` do not automatically remove temporary files and directories on exit. The user
+  is in charge of discarding any generated files and directories after execution. The paths to the
+  generated items are emitted as warning messages.
+* `-l` / `--loader` ROM trampoline to execute, if any
+* `-O` / `--otp-raw` specify a RAW image file for OTP fuses, which can be generated with the
+  [`otptool.py`](otpconf.md) tool. Alternatively, see the `-o` option.
+* `-o` / ` --otp` specify an OTP VMEM file. This option is mutually exclusive with the `-O` option.
+  This script takes care of calling [`otptool.py`](otpconf.md) to generate a temporary OTP file
+  that is discarded when this script exits.
+* `-r` / `--rom` specify a ROM ELF file. Without a ROM file, it is unlikely to start up any regular
+  application since the emulated lowRISC vCPU is preconfigured with a locked PMP, as the real HW.
+  When no ROM is specified, test applications are executed immediately, as a replacement of the ROM
+  executable. This option may be repeated, to load several ROMs, in the same order as specified
+* `-w` / `--result` specify an output CSV report file where the result of all the QEMU sessions,
+  one per test, are reported.
+* `-x` / ` --exec` specify a ROM extension, an application or a test to execute. This option is
+  mutually exclusive with the `-f` option. This script takes care of calling
+  [`flashgen.py`](flashgen.md) to generate a temporary flash file that is discarded when the
+  application has been run.
+* `-X` / `--rom-exec` load application as ROM image (default: as kernel)
+
+### Execution
+
+* `-F` / `--filter` when used, only tests whose filenames match one of the selected filter are
+  considered. This option only applies to tests enumerated from the configuration file. If a filter
+  starts with '!', any matching test is excluded.
+* `-k` / `--timeout` define the maximal duration of each QEMU session. QEMU is terminated or killed
+  after this delay if the executed test has not completed in time.
+* `-R` / `--summary` show a execution result summary on exit
+* `-Z`, `--zero` do not report an error if no test can be executed with the specified filters and
+   detected test applications. Default behavior is to report an error should such a condition arise,
+   as it likely comes from a misconfiguration or build issue.
+* `-z` / `--list` list all tests to be executed and exit
+
+### Extras
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+* `-G` / `--log-time` show local time before each logged message
+* `-V` / `--vcp-verbose` can be repeated to increase verbosity of the QEMU virtual comm ports
+* `-v` / `--verbose` can be repeated to increase verbosity of the script, mostly for debug purpose.
+* `--quiet` only emit verbose log traces if an error is detected
+* `--log-file` copy log messages to the specified file (previous content if any is overwritten)
+* `--log-udp` change the port of the UDP log service on specified UDP port. Use `0` to disable the
+  service.
+* `--debug` enable the debug level for the selected logger, may be repeated
+* `--info` enable the info level for the selected logger, may be repeated
+* `--warn` enable the warning level for the selected logger, may be repeated
+
+## Configuration file
+
+This script accepts HJSON configuration file to define how to run a test session.
+To install the dependency-less HJSON module, use a command such as `pip3 install hjson`.
+
+Sample config for running OpenTitan tests:
+````hjson
+{
+    aliases:
+    {
+        BASEDIR: ${OT_DIR}/bazel-out/k8-fastbuild/bin
+    }
+    testdir:  ${BASEDIR}/sw
+    default:
+    {
+        rom: ${BASEDIR}/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.elf
+        otp: ${BASEDIR}/hw/ip/otp_ctrl/data/img_rma.24.vmem
+        timeout: 3
+        icount: 6
+    }
+    include:
+    [
+        **/*.fake_rsa_test_key_0.signed.bin
+    ]
+    #include_from:
+    #[
+    #    ${BASEDIR}/../test_list.txt
+    #]
+    exclude:
+    [
+        alert_handler_*
+        ast_clk_out_*
+        clkmgr_off_*
+        i2c_*
+        manuf_cp_*
+        sensor_ctrl_*
+        spi_device_*
+        spi_passthru_*
+        usbdev_*
+    ]
+    suffixes:
+    [
+        _prog_fpga_cw310
+    ]
+    tests:
+    {
+        aes_idle_test:
+        {
+            opts:
+            [
+                -global
+                ot-aes.fast-mode=false
+            ]
+        }
+        alert_handler_lpg_reset_toggle_test:
+        {
+            timeout: 10
+        }
+        boot_data_functest:
+        {
+            icount: 1
+        }
+        otbn_rsa_test:
+        {
+            timeout: 5
+        }
+        ecdsa_p256_functest:
+        {
+            timeout: 5
+        }
+        ecdh_p256_functest:
+        {
+            timeout: 5
+        }
+        entropy_src_csrng_test:
+        {
+            icount: ""
+        }
+        csrng_edn_concurrency_test:
+        {
+            timeout: 15
+        }
+        csrng_smoketest:
+        {
+            timeout: 5
+        }
+    }
+}
+````
+
+Sample config for running some non-OpenTitan tests:
+````hjson
+{
+    aliases:
+    {
+        basedir: ${TEST_DIR}
+    }
+    testdir: ${BASEDIR}/target/riscv32imc-unknown-none-elf/debug
+    default:
+    {
+        timeout:  3
+        machine:  ot-earlgrey,no_epmp_cfg=true
+    }
+    virtual:
+    {
+        ot-flash: ${BASEDIR}/flash.raw
+    }
+    # It would be nice if ELF files could have an .elf extension w/ Cargo
+    # Let's include everything and exclude non-ELF files
+    include:
+    [
+        *
+    ]
+    exclude:
+    [
+        *.d
+        *.rlib
+        # void dummy app never completes
+        void
+    ]
+    tests:
+    {
+        edn-lim-test:
+        {
+            timeout:  6
+        }
+        mbxhost-test:
+        {
+            env:
+            {
+                PYTHONPATH: ${QEMU_SRC_DIR}/scripts/opentitan
+            }
+            opts:
+            [
+                -chardev socket,id=devproxy,host=localhost,port=8003,server=on,wait=off
+                -global ot-dev_proxy.chardev=devproxy
+            ]
+            with:
+            [
+                ${BASEDIR}/tools/mbxhost_test.py -vv -I 3 -P 3 -t
+            ]
+            timeout: 20
+        }
+        spihost-test:
+        {
+            # This test needs a specific SPI flash image
+            pre:
+            [
+                qemu-img create -f raw @{}/spiflash.raw 16M
+                dd if=${BASEDIR}/data/spihost/content.txt of=@{}/spiflash.raw conv=notrunc
+            ]
+            opts:
+            [
+                -drive if=mtd,format=raw,file=spiflash.raw
+            ]
+            post:
+            [
+                rm -r @{}/spiflash.raw
+            ]
+            timeout: 10
+        }
+        timer-test:
+        {
+            timeout:  15
+        }
+        aes-kat-test:
+        {
+            # This test needs to be driven by a host script
+            opts:
+            [
+                -chardev socket,id=serial1,host=localhost,port=8001,server=on,wait=off
+                -serial chardev:serial1
+            ]
+            with:
+            [
+                ${BASEDIR}/tools/katcomm.py -t ${BASEDIR}/data/aes/nist/kat/*.rsp
+            ]
+            timeout: 30
+        }
+    }
+}
+````
+
+### Configuration file sections
+
+* `aliases`
+  This section may be used to define string aliases to simplify further definitions.
+
+  Note that the resulting aliases are always uppercased. To use an alias, use the `${ALIAS}` syntax.
+  Environment variables may also be used as aliases.
+
+  Several special variables are automatically defined:
+  * `${CONFIG}` refers to the path of the configuration file itself,
+  * `${TESTDIR}` refers to the default test path (see `testdir` below).
+  * `${QEMU_SRC_DIR}` refers to the path to the QEMU source directory
+  * `${QEMU_BIN_DIR}` refers to the directory than contains the QEMU executable.
+
+  Moreover, the following special variables are defined for each executed test:
+  * `${UTPATH}` absolute path to the executed OT test
+  * `${UTDIR}` absolute path to the directory containing the executed OT test
+  * `${UTFILE}` file name of the executed OT test (without directory specifier)
+  * `${UDPLOG}` UDP log service, if UDP log service has been enabled, see `--log-udp` option.
+
+* `testdir`
+  This section may be used to define the default path where to look for tests to run.
+
+* `default`
+  This section defines the default options to use with all the tests.
+
+  In the `tests` section, it is possible to add or remove options for specific tests.
+
+  The option names are the same ones as the script option switches, please refer to the Usage
+  section for details.
+
+* `virtual`
+  This section defines virtual tests, as a mapping.
+  Each entry defines the name of the virtual test to create and the actual test binary to execute.
+
+  This enables testing the same binary in multiple configurations, using different options and
+  settings.
+
+  Virtual tests can be filtered and configured as any regular tests.
+
+* `include`
+  This section contains the list of tests to be run.
+
+  Globalisation patterns (`*` and `?`) may be used to match multiple files. Use `**/` to define a
+  recursive path.
+
+  It is possible to exclude some tests from this list with the `exclude` and `exclude_from`
+  sections.
+
+  It is possible to define sub-sections as items of the list. Each subsection should be a map, where
+  the sub-section is only evaluated if an environment variable exists and evaluates to true. This
+  enables configuring lists based on environment variables, such as running is some specific
+  contexts such as a CI environment.
+
+* `include_from`
+  This section contains a list of files defining the tests to be run.
+
+  Each file should be a plain text file with one test application per line.
+
+  `#` can be used to prefix any comments that are therefore ignored. Empty lines are also ignored.
+
+  Aliases can be used in the file paths. If, after resolution of aliases, a test file does not
+  start with a leading directory separator, the test filename is assumed to be relative to the path
+  of the current include file.
+
+  Note that `include_from` (and `exclude_from`) do not support globalization patterns (`*` and `?`).
+
+  Virtual tests cannot be specified in `include_from`, nor `exclude_from` files.
+
+* `exclude`
+  This section contains the list of tests not to be run.
+
+  Globalisation characters (`*` and `?`) may be used to select files with glob patterns. Use `**/`
+  to define a recursive path.
+
+  This section enables the removal of specific tests from the lists that have been built using the
+  `include` and `include_from` sections.
+
+* `exclude_from`
+  This section contains a list of files defining the tests to exclude.
+
+  The syntax is identical to the `include_from` section.
+
+* `suffixes`
+  This section defines shortcut to further reduce the definition and report of test filenames.
+
+  Any test filename ending up with one of the suffixes is automatically stripped. Further test
+  configuration in the `tests` section should omit this suffix. The generated test report also
+  omit these suffixes.
+
+* `tests`
+  This section enables option customization for each test entry.
+
+  * To add a new option, specify it as in the `default` section.
+  * To remove a default option, use an empty value (`""`)
+
+### Special test sections
+
+Each test section may have special subsections that may be used to execute arbitrary commands:
+
+* `pre` subsection contains commands to execute before QEMU is executed.
+
+  * This subsection may be useful to create some test files, or to start up a server.
+
+* `with` section contains commands to execute as soon as QEMU is started.
+
+  * This subsection may be useful to inject some test patterns over a communication channel into
+    the guest program running on the VM
+
+* `post` section contains commands to execute once the QEMU session has completed.
+
+  * This section may be useful to perform some cleanup or post processing analysis once the QEMU
+    session is over
+
+It is also possible to define an `env` section to define special environment variables that would be
+required by the commands defined in the previous subsections.
+
+Regular or 'synchronous' commands are only executed if all the previous commands have been
+successful. Moreover, commands in the `post` subsection are only executed if the QEMU session has
+completed successfully.
+
+Background commands are commands that run in the background till they complete on their own, or
+automatically once the QEMU session has completed.
+
+1. `pre` and `post` commands default to synchronous execution; `post` commands cannot be defined as
+background commands.
+2. `with` commands default to background execution.
+
+To change the default execution style for a command, add a suffix to the command definition:
+
+1. append a `&` character to select background execution, useful with `pre` commands
+2. append a `!` character to select synchronous execution, useful with `with` commands; it is
+   possible to append `@T` with `T` is defined as an integral value, _e.g._ the `sleep 5!@6`
+   statement executes the sleep command which waits for 5 seconds. This command does not time out
+   since its timeout is set to 6 seconds.
+
+#### Temporary directories
+
+It is possible to use the special `@{dir_id}/` syntax, where `dir_id` should be a regular
+identifier.
+
+Whenever such directory placeholder is detected, it is replaced with a temporary directory which is
+created the first time the identifier is encountered, and automatically removed along all its
+contents when `pyot.py` exits. It is also possible to remove a temporary directory at any time with
+a regular `rm -r` command. The temporary directories are not removed between tests, so that content
+of temporary directories may be shared/reused across tests.
+
+As a special syntax, the `@{}/` (empty directory identifier) can be used to create a temporary
+directory which is automatically removed once the test completes, whatever its completion status
+(success or failure).
+
+## Result file sample
+
+````csv
+Name,Result,Time,Icount,Error
+aes_entropy_test,pass,0.050,6,
+aes_functest,pass,0.052,6,
+aes_gcm_functest,pass,0.068,6,
+aes_gcm_timing_test,fail,0.054,6,CHECK-fail: AES-GCM decryption was not constant-time for different invalid tags
+aes_idle_test,pass,0.046,6,
+aes_masking_off_test,fail,0.042,6,"CHECK-STATUS-fail: Internal:[""CSR"";22]"
+aes_smoketest,pass,0.045,6,
+aes_test,pass,0.044,6,
+...
+````
+
+## Return value
+
+The script returns the error code of the most occurring error, or success (0)
+
+## Examples
+
+* The most typical usage requires a HJSON configuration file and produces an output CSV file. `-vv`,
+  that is the information log level, should be enough to track execution without getting too many
+  log messages.
+
+  ````sh
+  ./scripts/opentitan/pyot.py -vv -c pyot.hjson -w pyot.csv
+  ````
+
+  Note that results can be live-tracked from another terminal using a command like the following:
+
+  ````sh
+  tail -f pyot.csv
+  ````
+
+* Running at single test can be done without any configuration file:
+
+  ````sh
+  export BASEDIR=$OT_DIR/bazel-out/k8-fastbuild/bin
+  ./scripts/opentitan/pyot.py -vv \
+    --rom $BASEDIR/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.elf \
+    --otp $BASEDIR/hw/ip/otp_ctrl/data/img_rma.24.vmem \
+    --exec $BASEDIR/sw/device/tests/uart_smoketest_prog_fpga_cw310.fake_rsa_test_key_0.signed.bin
+  ````
+
+* The full OpenTitan boot flow with production ROM can also be run:
+
+  ````sh
+  export BASEDIR=$OT_DIR/bazel-out/k8-fastbuild/bin
+  ./scripts/opentitan/pyot.py -vv \
+    --rom $BASEDIR/sw/device/silicon_creator/rom/rom_with_fake_keys_fpga_cw310.elf \
+    --otp $BASEDIR/hw/ip/otp_ctrl/data/img_rma.24.vmem \
+    --exec $BASEDIR/sw/device/silicon_creator/rom_ext/rom_ext_slot_virtual_fpga_cw310.fake_rsa_test_key_0.signed.bin \
+    --boot $BASEDIR/sw/device/silicon_owner/bare_metal/bare_metal_slot_virtual_fpga_cw310.fake_rsa_rom_ext_test_key_0.signed.bin
+  ````
+
+## Tips
+
+* `-N I` option is quite useful to debug application startup issues.
+
+* `-N A` option only displays the first time that a RISC-V instruction block is translated to
+  host code, not each time the instructions are executed. Use `-N E` to display the actual
+  executed instructions. Enabling single stepping is also helpful in this case (with `-s`).
diff --git a/docs/opentitan/regressions.md b/docs/opentitan/regressions.md
new file mode 100644
index 0000000000000..4add9ea58780e
--- /dev/null
+++ b/docs/opentitan/regressions.md
@@ -0,0 +1,33 @@
+# OpenTitan regressions
+
+The `run-bazel-tests.sh` script and accompanying CI workflow allow us to run regression tests
+against the OpenTitan repository. Currently only Earlgrey tests are supported.
+
+With a checkout of OpenTitan, the script can be run like this:
+
+```sh
+./scripts/opentitan/run-bazel-tests.sh path/to/opentitan path/to/qemu \
+    [execution_environment] [timeout]
+```
+
+The script will execute all QEMU-compatible tests using QEMU as it was built at the given path. The
+test results will be compared against a list checked into this repository at
+`tests/opentitan/data/earlgrey-tests.txt`.
+
+Each test occupies its own line, prefixed by the expected status. Tests with a `pass` status are
+expected to pass - failures indicate a regression in either QEMU or Earlgrey. The script will fail
+if there is a mismatch between the tests that we expect to pass and the actual results.
+
+Some tests may be flaky and pass or fail on different runs of the same QEMU and OpenTitan checkouts.
+These tests can be prefixed with the `flaky` status to cause the script to ignore them. This will
+suppress these tests from being printed as unexpected passes when they do succeed, but will also
+stop their failures from causing the script to fail.
+
+After each test, a comment can be provided (starting with a `#`), which can help log the reasons
+that tests might have become flaky.
+
+Specifying an execution environment when running the script will restrict to only running and
+comparing against tests for that execution environment. This can be used for more granular testing
+to break down large test workloads. If you do not specify an execution environment, _all_ available
+QEMU tests will be executed. When specifying an execution environment, a maximum test timeout (in
+seconds) to use for that environment can also be provided as a subsequent argument to the script.
diff --git a/docs/opentitan/romtool.md b/docs/opentitan/romtool.md
new file mode 100644
index 0000000000000..1439d64d637f0
--- /dev/null
+++ b/docs/opentitan/romtool.md
@@ -0,0 +1,83 @@
+# `romtool.py`
+
+`romtool.py` converts ROM image between different file formats.
+
+Supported input formats:
+* `ELF`: RISC-V RV32 executable file (only supported as input ROM file)
+* `BIN`: RISC-V RV32 executable file
+* `VMEM`: Plain VMEM text file
+* `SVMEM`: Scrambled VMEM text file with 7-bit SEC-DED
+* `HEX`: Scrambled HEX text file with 7-bit SEC-DED
+
+## Usage
+
+````text
+usage: romtool.py [-h] -c CFG [-o OUTPUT] [-D] [-f {HEX,BIN,SVMEM,VMEM}]
+                  [-i ROM_ID] [-s] [-z SIZE] [-v] [-d]
+                  rom
+
+QEMU OT tool to generate a scrambled ROM image.
+
+options:
+  -h, --help            show this help message and exit
+
+Files:
+  rom                   input ROM image file
+  -c, --config CFG      input QEMU OT config file
+  -o, --output OUTPUT   output ROM image file
+
+Parameters:
+  -D, --digest          Show the ROM digest
+  -f, --output-format {HEX,BIN,SVMEM,VMEM}
+                        Output file format (default: HEX)
+  -i, --rom-id ROM_ID   ROM image identifier
+  -s, --subst-perm      Enable legacy mode with S&P mode
+  -z, --rom-size SIZE   ROM image size in bytes (accepts Ki suffix)
+
+Extras:
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+### Arguments
+
+* `-c` specify a QEMU [configuration file](otcfg.md) from which to read all the cryptographic
+  constants. See [`cfggen.py`](cfggen.md) tool to generate such a file.
+
+* `-D` show the loaded or computed ROM digest as an hexadecimal string
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-f` output file format. `HEX` format always output scrambled/SEC-DED data, `SVMEM` specifies a
+  VMEM format with scrambled/SEC-DED data. Note: input file format is automatically detected from
+  the content of the input ROM file.
+
+* `-i` ROM identifier. Required for platforms with multiple ROMs
+
+* `-o` outfile file, default to stdout (beware when using a binary format)
+
+* `-s` use legacy scrambling scheme, with extra substitute and permute stages, but less PRINCE
+  stages. Only useful for older files.
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+* `-z` ROM file size. Required for all input file formats but the `HEX` or `SVMEM` format.
+  `Ki` (kilobytes) suffix is supported.
+
+### Examples
+
+Generate a scrambled with SEC-DED data in HEX format:
+````sh
+# EarlGrey
+scripts/opentitan/romtool.py -c ot.cfg -z 32Ki -o rom.hex rom.elf
+# Darjeeling (base ROM)
+scripts/opentitan/romtool.py -c ot.cfg -z 32Ki -i 0 -o rom0.hex rom0.elf
+````
+
+Extract clear data from a scrambled HEX file:
+````sh
+# EarlGrey
+scripts/opentitan/romtool.py -c ot.cfg -f VMEM -o rom.vmem rom.hex
+# Darjeeling (base ROM)
+scripts/opentitan/romtool.py -c ot.cfg -i 0 -f VMEM -o rom.vmem rom.hex
+```
diff --git a/docs/opentitan/spidevflash.md b/docs/opentitan/spidevflash.md
new file mode 100644
index 0000000000000..b8c166ae83495
--- /dev/null
+++ b/docs/opentitan/spidevflash.md
@@ -0,0 +1,77 @@
+# `spidevflash.py`
+
+`spidevflash.py` is a tiny script to upload bootstrap image using the SPI device virtual device.
+
+## Usage
+
+````text
+usage: spidevflash.py [-h] -f FILE [-a ADDRESS] [-S SOCKET] [-R RETRY_COUNT]
+                      [-T SYNC_TIME] [--idle DELAY] [-t] [-r HOST] [-p PORT]
+                      [--log-udp UDP_PORT] [-v] [-d]
+
+SPI device flasher tool.
+
+options:
+  -h, --help            show this help message and exit
+  -f, --file FILE       Binary file to flash
+  -a, --address ADDRESS
+                        Address in the SPI flash (default: 0)
+  -S, --socket SOCKET   connection string
+  -R, --retry-count RETRY_COUNT
+                        connection retry count (default: 1)
+  -T, --sync-time SYNC_TIME
+                        synchronization max time (default: 5.0s)
+  --idle DELAY          stay idle before establish connection
+  -t, --terminate       terminate QEMU VM on completion
+  -r, --host HOST       remote host name (default: localhost)
+  -p, --port PORT       remote host TCP port (default: 8004)
+  --log-udp UDP_PORT    Log to a local UDP logger
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+### Arguments
+
+* `-a` specify an alternative start address'
+
+* `-d` only useful to debug the script, reports any Python traceback to the standard error stream.
+
+* `-f` specify the binary file to upload'
+
+* `-p` specify an alternative port for the TCP connection on the QEMU instance. Mutually exclusive
+  with `-S`.
+
+* `-R` specify the number of connection attempts before giving up.
+
+* `-r` specify the name or address of the remote host running the QEMU instance. Mutually exclusive
+  with `-S`.
+
+* `-S` specify a connection string to the remote host running the QEMU instance, _e.g._
+  `tcp:localhost:8004` or `unix:/tmp/socket`. Mutually exclusive with `-r` and `-p`.
+
+* `-T` specify the maximum allowed time to successfully synchronize with the remote SPI device once
+   the connection has been established
+
+* `-v` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+* `--idle` wait for the specified delay in seconds before attempting a connection to the QEMU SPI
+   device socket
+
+* `--log-udp` specify a UDP port on the local host to redirect log messages,
+
+### Examples
+
+In the following example
+
+````
+-chardev socket,id=spidev,host=localhost,port=8004,server=on,wait=off
+-global ot-spi_device.chardev=spidev`
+````
+
+should be added to the QEMU command line to create a TCP chardev and to connect it to the SPI Device
+backend. See the [SPI Device](ot_spi_device.md) documentation for details.
+
+* Upload a bootstrap binary
+  ````sh
+  ./scripts/opentitan/spidevflash.py -f test_bootstrap_virtual_sim_dv+manifest.bin
+  ````
diff --git a/docs/opentitan/tools.md b/docs/opentitan/tools.md
new file mode 100644
index 0000000000000..ef250de7f2fad
--- /dev/null
+++ b/docs/opentitan/tools.md
@@ -0,0 +1,82 @@
+# OpenTitan QEMU tools
+
+All the OpenTitan tools and associated files are stored in the `scripts/opentitan` directory.
+
+## Installation
+
+Most tools are implemented in Python language. They require Python 3.10 or newer.
+
+It is recommended to install Python dependencies using a [virtual environment](https://virtualenv.pypa.io).
+
+To install Python dependencies, use:
+```sh
+pip3 install -r scripts/opentitan/requirements.txt
+```
+
+## Execution wrapper
+
+Launching a QEMU VM with the right option switches may rapidly become complex due to the number
+of options and the available features.
+
+* [`pyot.py`](pyot.md) can be used to run unit tests and OpenTitan tests
+
+## Companion file management
+
+* [`cfggen.py`](cfggen.md) can be used to generate an OpenTitan [configuration file](otcfg.md) from
+  an existing OpenTitan repository.
+* [`romtool.py`](romtool.md) can be used to convert a ROM image file between different file formats.
+* [`otpdm.py`](otpdm.md) can be used to access the OTP Controller over a JTAG/DTM/DM link. It reads
+  out partition's item values and can update those items.
+* [`otptool.py`](otptool.md) can be used to generate an OTP image from a OTP VMEM file and can be
+  used to decode (some of the) encoded data in the OTP image.
+* [`flashgen.py`](flashgen.md) can be used to generate a flash image with either a ROM_EXT and BL0
+  signed files, or a single OpenTitan signed test files.
+* `swexit.py` is a tiny Python script to generate the simplest RISC-V executable (with no need for
+  a RISC-V toolchain) that is used to ensure the QEMU OpenTitan machine can start up and quit.
+
+## Development
+
+* [`autoregs.py`] is a Python script that generates register definitions and function templates to
+  create a skeleton file QEMU system bus device emulation.
+* [`autotop.py`] is a Python script that generates machine definitions to create a skeleton file for
+  a QEMU OpenTitan machine.
+* [`checkregs.py`](checkregs.md) is an internal tool design to check the discrepancies between
+   OpenTitan generated register definition files and their QEMU counterparts. It is only useful to
+   develop the machine itself.
+* `devproxy.py` is a Python module that provides an API to remote drive the [DevProxy](devproxy.md)
+  communication interface.
+* [`dtm.py`](dtm.md) is a tiny Python script that can be used to check the JTAG/DTM/DM stack is
+  up and running and demonstrate how to use the Debug Module to access the Ibex core.
+* [`gdbreplay.py`](gdbreplay.md) is a basic GDB server that can be used to replay Ibex execution
+  stream from a QEMU execution trace.
+* [`gpiodev.py`](gpiodev.md) is a tiny script to run regression tests with GPIO device.
+* `mbbdef.py` is a simple Python tool to extract multi-bit bool definition from OpenTitan' HJSON
+  configuration file
+* [`keymgre-dpe.py`](keymgre-dpe.md) is a simple Python tool to generate KeyManager DPE output keys
+  using the same parameters as the KeyManager DPE. It is dedicated to unit test purposes.
+* `ot-format.sh` is a simple shell wrapper to run clang-format (code formatter) on OpenTitan files
+* `ot-tidy.py` is a python wrapper script to run clang-tidy (the LLVM C linter) on OpenTitan files,
+  optionally in parallel, and locally or for CI.
+* [`run-bazel-tests.sh`](regressions.md) is a script for running the OpenTitan test suite against
+  a local build of QEMU.
+* [`spidevflash.py`](spidevflash.md) is a tiny script to upload a binary using the SPI device.
+* `treillis/` directory contains the test application to test the [GPIO](ot_gpio.md) device.
+* [`uartmux.py`](uartmux.md) is a tiny stream wrapper to help dealing with multiple QEMU output
+  streams, typically multiple virtual UARTs.
+* [`verilate.py`](verilate.md) is a Verilator wrapper tool to run unit tests on Verilator simulation
+  environment. It is designed as a companion tool to help writing QEMU OpenTitan devices, running
+  the very same binaries as QEMU and comparing the outcome of each simulation environment.
+
+## Python modules
+
+See [Python modules](pymod.md) documentation.
+
+## Configuration files
+
+* `darjeeling-ocd.cfg` is a sample configuration file for OpenOCD to connect to the JTAG interface
+* `clang-format.yml` is the configuration file for clang-format used for all OpenTitan and Ibex
+  source files
+* `clang-tidy.yml` is the configuration file for clang-tidy used for all OpenTitan and Ibex source
+  files
+* `.flake8` is the configuration file for the Python Flake8 linter for OT tools
+* `.pylintrc` is the configuration file for the Python PyLint linter for OT tools
diff --git a/docs/opentitan/uartmux.md b/docs/opentitan/uartmux.md
new file mode 100644
index 0000000000000..cf1546f577631
--- /dev/null
+++ b/docs/opentitan/uartmux.md
@@ -0,0 +1,65 @@
+# `uartmux.py`
+
+`uartmux.py` is a tiny stream wrapper to help dealing with multiple QEMU output streams, typically
+multiple virtual UARTs.
+
+## Usage
+
+````text
+usage: uartmux.py [-h] [-i IFACE] [-p PORT] [-c CHANNEL] [-v] [-d] [name ...]
+
+QEMU UART muxer.
+
+positional arguments:
+  name                  assign name to input connection
+
+options:
+  -h, --help            show this help message and exit
+  -i IFACE, --iface IFACE
+                        specify TCP interface to listen to (default: localhost)
+  -p PORT, --port PORT  specify TCP port to listen to (default: 9000)
+  -c CHANNEL, --channel CHANNEL
+                        expected comm channel count(default: 3)
+  -s SEPARATOR, --separator SEPARATOR
+                        repeat separator between each session
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+````
+
+`uartmux.py` may be used with QEMU character devices, _i.e._ `chardev` defined as network streams,
+such as `-chardev socket`.
+
+`uartmux.py` listens on multiple input streams, and prints them one line at a time, colorizing each
+stream with a different color when an ANSI terminal is used.
+
+It enables a coherent output log when multiple virtual UARTs are emitting at once.
+
+### Arguments
+
+* `name` optional name(s) for prefixing each log message line with the known channel name
+
+* `-c` / `--channel` how many input streams are expected, in order to assign the same ANSI color
+  to the same input stream across subsequence QEMU sessions. Note that if not defined, default to
+  the count of defined names
+
+* `-d` / `--debug` only useful to debug the script, reports any Python traceback to the standard
+  error stream.
+
+* `-i` / `--iface` select an alternative interface for listening on, default to localhost
+
+* `-p` / `--port` select an alternative TCP port for listening on, default to 9000
+
+* `-s` / `--separator` emit this separator between each detected QEMU session
+
+* `-v` / `--verbose` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+### Example
+
+QEMU using two virtual UART output identified as `uart0` and `uart1`:
+
+* run `uartmux.py uart0 uart1` in one terminal
+* run QEMU in another terminal with the following option switches:
+  ```
+  -chardev socket,id=uart0,host=127.0.0.1,port=9000
+  -chardev socket,id=uart1,host=127.0.0.1,port=9000
+  ```
diff --git a/docs/opentitan/verilate.md b/docs/opentitan/verilate.md
new file mode 100644
index 0000000000000..e62682278c21f
--- /dev/null
+++ b/docs/opentitan/verilate.md
@@ -0,0 +1,162 @@
+# `verilate.py`
+
+`verilate.py` is a Verilator wrapper tool to run unit tests on Verilator simulation environment. It
+is designed as a companion tool to help writing QEMU OpenTitan devices, running the very same
+binaries as QEMU and comparing the outcome of each simulation environment.
+
+## Usage
+
+````text
+usage: verilate.py [-h] [-V VERILATOR] [-R FILE] [-M FILE] [-F FILE] [-O VMEM]
+                   [-K] [-D TMP_DIR] [-c CFG] [-a PREFIX] [-b TCP_PORT]
+                   [-C CYCLES] [-I] [-k SECONDS] [-l] [-P FILE] [-w] [-x] [-v]
+                   [-d] [-G]
+                   [ELF ...]
+
+Verilator wrapper.
+
+options:
+  -h, --help            show this help message and exit
+
+Files:
+  ELF                   application file, may be repeated
+  -V, --verilator VERILATOR
+                        Verilator executable
+  -R, --rom FILE        ROM file, may be repeated
+  -M, --ram FILE        RAM file, may be repeated
+  -F, --flash FILE      eFlash file, may be repeated
+  -O, --otp VMEM        OTP file
+  -K, --keep-tmp        do not automatically remove temporary files and dirs
+                        on exit
+  -D, --tmp-dir TMP_DIR
+                        store the temporary files in the specified directory
+  -c, --config CFG      input QEMU OT config file (required w/ non scrambled
+                        ROM images)
+
+Verilator:
+  -a, --artifact-name PREFIX
+                        set an alternative artifact name (default is derived
+                        from the application name)
+  -b, --spi-device-bridge TCP_PORT
+                        Create a SPI device bridge
+  -C, --cycles CYCLES   exit after the specified cycles
+  -I, --show-init       show initializable devices
+  -k, --timeout SECONDS
+                        exit after the specified seconds (default: 600.0 secs)
+  -l, --link-exec-log   create a symlink to the execution log file
+  -P, --profile FILE    enable/manage profile file
+  -w, --wave-gen        generate output wave file
+  -x, --save-exec-log   save execution log
+
+Extras:
+  -v, --verbose         increase verbosity
+  -d, --debug           enable debug mode
+  -G, --log-time        show local time in log messages
+````
+
+### Arguments
+
+* `ELF` one or more application files to load in Verilator emulated memory devices before starting
+  the simulation environment. It can be repeated. ELF metadata are used to discover in which device
+  to load each ELF application: ROM, RAM or eFlash devices are supported. If another file input
+  format (such as `VMEM`, `HEX`, `BIN`, ...) needs to be used, please refer to options `-R`, `-M`
+  and `-F`.
+
+* `-a` / `--artifact` all artifact files (see `-l`, `-x` and `-w`) are named after the application
+  name. This option specifies an alternative file prefix for all those artifacts.
+
+* `-b` / `--spi-device-bridge` create a local server on the specified TCP port that accepts QEMU SPI
+  device CharDev compliant requests, translates and converts them into simplified Verilator SPI DPI
+  requests using its PTY SPI device channel. SDO output data received on the PTY channel are
+  converted back into QEMU CharDev compliant responses. This feature can be enabled to use SPI
+  device tests that have been designed for the QEMU VM.
+
+* `-C` / `--cycles` abort Verilator execution after the specified count of cycles. See also the `-k`
+  option.
+
+* `-c` / `--config` specify a QEMU [configuration file](otcfg.md) from which to read all the
+  cryptographic constants. See [`cfggen.py`](cfggen.md) tool to generate such a file. It is required
+  to scramble any non-pre scrambled ROM input file.
+
+* `-d` / `--debug` only useful to debug the script, reports any Python traceback to the standard
+  error stream.
+
+* `-D` / `--tmp-dir` specify a custom directory for temporary files.
+
+* `-F` specify a file to load into the embedded flash device. This option can be repeated if the
+  simulated platform supports multiple embedded flash partitions, in which case the specified files
+  are loaded in partition order. See option `-I` for a list of supported devices.
+
+* `-G` / `--log-time` show local time before each logged message
+
+* `-K` / `--keep-tmp` do not automatically remove temporary files and directories on exit. The user
+  is in charge of discarding any generated files and directories after execution. The paths to the
+  generated items are emitted as warning messages.
+
+* `-k` / `--timeout` abort Verilator execution after the specified time. See also the `-c` option.
+
+* `-I` / `--show-init` show a list of initializable (loadable) devices for the specified Verilator
+  environment (see option `-V`).
+
+* `-l` / `--link-log` create a shortcut (a symbolic link) to the Verilator trace log file while
+  Verilator is running. This gives a known file name to track while Verilator is executing, so it is
+  easy to follow the execution status (such as with `tail -F` command). See also the `-x` option to
+  save the resulting trace log file after completion. See also `-a`.
+
+* `-M` / `--ram` specify a file to load into a RAM. This option can be repeated if the simulated
+  platform supports multiple RAM devices, in which case the specified files are loaded in RAM order.
+  Note that the "order" of RAM depends on each platform. See option `-I` for a list of supported
+  devices.
+
+* `-O` / `--otp` specify the image file to load into the OTP controller. This option only supports
+  VMEM plain text file with 24-bit data chunks (6 bit ECC + 16 bit data), as produced by the
+  OpenTitan tools.
+
+* `-P` / `--profile` create/use a Verilator profile file. Only useful for profile-guided Verilator
+  optimization.
+
+* `-R` / `--rom` specify a file to load into a ROM. This option can be repeated if the simulated
+  platform supports multiple ROM devices, in which case the specified files are loaded in ROM order.
+  See option `-I` for a list of supported devices.
+
+* `-V` / `--verilator` where to find the Verilator executable. This option expects a directory. The
+  file structure tree is traversed till a `Vchip_sim_tb` application is found. It is primarily
+  designed to locate this application from a Bazel binary tree, such the one produced in OpenTitan
+  repository.
+
+* `-v` / `--verbose` can be repeated to increase verbosity of the script, mostly for debug purpose.
+
+* `-x` / `--execution-log` save the generated Verilator trace log file after execution. The file is
+  saved even if Verilator is aborted or killed. See also option `-l` for a live view of execution
+  traces. See also `-a`.
+
+* `-w` / `--wave` generate a GtkWave-compatible FST wave file, named after the main application.
+  See also `-a`.
+
+### Examples
+
+* Show a list of initializable devices:
+    ````sh
+    scripts/opentitan/verilate.py -V bazel-bin -I
+    ````
+    output:
+    ````
+    flash0  0x20000000   512 KiB
+    flash1  0x20080000   512 KiB
+    otp     0x40000000    16 KiB
+    ram     0x10000000   128 KiB
+    rom     0x00008000    32 KiB
+    ````
+
+* Run a Verilator session with an OpenTitan unit test, using a pre-scrambled ROM file and an
+  application in flash:
+    ````sh
+    scripts/opentitan/verilate.py -V ../ot/bazel-bin -x -O img_rma.24.vmem \
+      -R test_rom_sim_verilator.39.scr.vmem -F test_rom_sim_verilator.39.scr.vmem -vv
+    ````
+
+* Run a Verilator session with a baremetal test and generate a GtkWave file:
+    ````sh
+    scripts/opentitan/verilate.py -V ../ot/bazel-bin -c docs/config/opentitan/earlgrey.cfg \
+      -x exec.log -O img_rma.24.vmem -vv rom0.elf helloworld -w
+    ````
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 5b2fc06e58dff..e8136b0132594 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -2309,18 +2309,20 @@ static int gdb_handle_packet(const char *line_buf)
 
 void gdb_set_stop_cpu(CPUState *cpu)
 {
-    GDBProcess *p = gdb_get_cpu_process(cpu);
-
-    if (!p->attached) {
-        /*
-         * Having a stop CPU corresponding to a process that is not attached
-         * confuses GDB. So we ignore the request.
-         */
-        return;
+    if (gdbserver_state.init) {
+        GDBProcess *p = gdb_get_cpu_process(cpu);
+    
+        if (!p->attached) {
+            /*
+             * Having a stop CPU corresponding to a process that is not attached
+             * confuses GDB. So we ignore the request.
+             */
+            return;
+        }
+    
+        gdbserver_state.c_cpu = cpu;
+        gdbserver_state.g_cpu = cpu;
     }
-
-    gdbserver_state.c_cpu = cpu;
-    gdbserver_state.g_cpu = cpu;
 }
 
 void gdb_read_byte(uint8_t ch)
diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx
index 41674dcbe1eb2..da3bfb5c847dd 100644
--- a/hmp-commands-info.hx
+++ b/hmp-commands-info.hx
@@ -998,6 +998,18 @@ SRST
     Show the crypto devices.
 ERST
 
+    {
+        .name       = "ibex",
+        .args_type  = "",
+        .params     = "",
+        .help       = "Show Ibex vCPU info",
+    },
+
+SRST
+  ``info ibex``
+    Show Ibex vCPU information.
+ERST
+
     {
         .name       = "firmware-log",
         .args_type  = "max-size:o?",
diff --git a/hw/Kconfig b/hw/Kconfig
index 9e6c789ae7ee5..91c9c0d5e924b 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -69,6 +69,15 @@ source sparc64/Kconfig
 source tricore/Kconfig
 source xtensa/Kconfig
 
+# Ibex Demo System devices
+source ibexdemo/Kconfig
+
+# JTAG devices
+source jtag/Kconfig
+
+# OpenTitan devices
+source opentitan/Kconfig
+
 # Symbols used by multiple targets
 config TEST_DEVICES
     bool
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index a5336d92ff9fc..d5acd2319f8f8 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -224,7 +224,8 @@ static const FlashPartInfo known_devices[] = {
     { INFO("is25lp256",   0x9d6019,      0,  64 << 10, 512, ER_4K) },
     { INFO("is25wp032",   0x9d7016,      0,  64 << 10,  64, ER_4K) },
     { INFO("is25wp064",   0x9d7017,      0,  64 << 10, 128, ER_4K) },
-    { INFO("is25wp128",   0x9d7018,      0,  64 << 10, 256, ER_4K) },
+    { INFO("is25wp128",   0x9d7018,      0,  64 << 10, 256, ER_4K),
+      .sfdp_read = m25p80_sfdp_is25wp128 },
     { INFO("is25wp256",   0x9d7019,      0,  64 << 10, 512, ER_4K),
       .sfdp_read = m25p80_sfdp_is25wp256 },
 
@@ -364,6 +365,8 @@ static const FlashPartInfo known_devices[] = {
       .sfdp_read = m25p80_sfdp_w25q512jv },
     { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K),
       .sfdp_read = m25p80_sfdp_w25q01jvq },
+    { INFO("w25q512nw",   0xef6020,      0,  64 << 10, 1024, ER_4K | ER_32K),
+      .sfdp_read = m25p80_sfdp_w25q512nw },
 
     /* Microchip */
     { INFO("25csm04",      0x29cc00,      0x100,  64 << 10,  8, 0) },
@@ -403,6 +406,7 @@ typedef enum {
     DPP = 0xa2,
     QPP = 0x32,
     QPP_4 = 0x34,
+    PP_4 = 0x38,
     RDID_90 = 0x90,
     RDID_AB = 0xab,
     AAI_WP = 0xad,
@@ -456,6 +460,7 @@ typedef enum {
     STATE_COLLECTING_VAR_LEN_DATA,
     STATE_READING_DATA,
     STATE_READING_SFDP,
+    STATE_RESET,
 } CMDState;
 
 typedef enum {
@@ -518,6 +523,7 @@ struct Flash {
     bool block_protect3;
     bool top_bottom_bit;
     bool status_register_write_disabled;
+    bool hw_reset; /* HW reset status */
     uint8_t ear;
 
     int64_t dirty_page;
@@ -528,6 +534,7 @@ struct Flash {
 
 struct M25P80Class {
     SSIPeripheralClass parent_class;
+    ResettablePhases parent_phases;
     const FlashPartInfo *pi;
 };
 
@@ -646,6 +653,7 @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd)
         return;
     }
     memset(s->storage + offset, 0xff, len);
+    s->write_enable = false;
     flash_sync_area(s, offset, len);
 }
 
@@ -759,6 +767,7 @@ static void complete_collecting_data(Flash *s)
     case PP:
     case PP4:
     case PP4_4:
+    case PP_4:
         s->state = STATE_PAGE_PROGRAM;
         break;
     case AAI_WP:
@@ -953,8 +962,6 @@ static void reset_memory(Flash *s)
     default:
         break;
     }
-
-    trace_m25p80_reset_done(s);
 }
 
 static uint8_t numonyx_mode(Flash *s)
@@ -1001,17 +1008,13 @@ static void decode_fast_read_cmd(Flash *s)
         s->needed_bytes += 1;
         break;
     case MAN_WINBOND:
-        s->needed_bytes += 8;
+        s->needed_bytes += 1;
         break;
     case MAN_NUMONYX:
         s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
         break;
     case MAN_MACRONIX:
-        if (extract32(s->volatile_cfg, 6, 2) == 1) {
-            s->needed_bytes += 6;
-        } else {
-            s->needed_bytes += 8;
-        }
+        s->needed_bytes += 1;
         break;
     case MAN_SPANSION:
         s->needed_bytes += extract32(s->spansion_cr2v,
@@ -1173,6 +1176,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)
     case ERASE4_SECTOR:
     case PP:
     case PP4:
+    case PP_4:
     case DIE_ERASE:
     case RDID_90:
     case RDID_AB:
@@ -1546,6 +1550,10 @@ static int m25p80_cs(SSIPeripheral *ss, bool select)
 {
     Flash *s = M25P80(ss);
 
+    if (s->state == STATE_RESET) {
+        return 0;
+    }
+
     if (select) {
         if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
             complete_collecting_data(s);
@@ -1572,6 +1580,9 @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
 
     switch (s->state) {
 
+    case STATE_RESET:
+        break;
+
     case STATE_PAGE_PROGRAM:
         trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
         flash_write8(s, s->cur_addr, (uint8_t)tx);
@@ -1662,6 +1673,32 @@ static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level)
     s->wp_level = !!level;
 }
 
+static void m25p80_hw_reset(void *opaque, int n, int level)
+{
+    Flash *s = opaque;
+
+    g_assert(n == 0);
+
+    bool nreset = (bool)level; /* RESET# */
+
+    if (nreset == !s->hw_reset) {
+        /*
+         * ignore IRQ request without change, as Resettable API tracks count of
+         * reset calls. HW signal is only a level.
+         */
+        return;
+    }
+
+    s->hw_reset = !nreset;
+
+    if (s->hw_reset) {
+        resettable_assert_reset(OBJECT(s), RESET_TYPE_COLD);
+    } else {
+        resettable_release_reset(OBJECT(s), RESET_TYPE_COLD);
+    }
+}
+
+
 static void m25p80_realize(SSIPeripheral *ss, Error **errp)
 {
     Flash *s = M25P80(ss);
@@ -1694,13 +1731,22 @@ static void m25p80_realize(SSIPeripheral *ss, Error **errp)
         memset(s->storage, 0xFF, s->size);
     }
 
+    qdev_init_gpio_in_named(DEVICE(s), &m25p80_hw_reset, "RESET#", 1);
+
     qdev_init_gpio_in_named(DEVICE(s),
                             m25p80_write_protect_pin_irq_handler, "WP#", 1);
 }
 
-static void m25p80_reset(DeviceState *d)
+static void m25p80_reset_enter(Object *obj, ResetType type)
 {
-    Flash *s = M25P80(d);
+    M25P80Class *c = M25P80_GET_CLASS(obj);
+    Flash *s = M25P80(obj);
+
+    trace_m25p80_reset(s, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
 
     s->wp_level = true;
     s->status_register_write_disabled = false;
@@ -1711,6 +1757,22 @@ static void m25p80_reset(DeviceState *d)
     s->top_bottom_bit = false;
 
     reset_memory(s);
+
+    s->state = STATE_RESET;
+}
+
+static void m25p80_reset_exit(Object *obj, ResetType type)
+{
+    M25P80Class *c = M25P80_GET_CLASS(obj);
+    Flash *s = M25P80(obj);
+
+    trace_m25p80_reset(s, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    s->state = STATE_IDLE;
 }
 
 static int m25p80_pre_save(void *opaque)
@@ -1869,10 +1931,14 @@ static void m25p80_class_init(ObjectClass *klass, const void *data)
     k->cs_polarity = SSI_CS_LOW;
     dc->vmsd = &vmstate_m25p80;
     device_class_set_props(dc, m25p80_properties);
-    device_class_set_legacy_reset(dc, m25p80_reset);
     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
     mc->pi = data;
     dc->desc = "Serial Flash";
+    ResettableClass *rc = RESETTABLE_CLASS(dc);
+    M25P80Class *fc = M25P80_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &m25p80_reset_enter, NULL,
+                                       &m25p80_reset_exit,
+                                       &fc->parent_phases);
 }
 
 static const TypeInfo m25p80_info = {
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index a03a291a09b5f..90e69576d42f0 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -440,10 +440,82 @@ static const uint8_t sfdp_w25q80bl[] = {
 };
 define_sfdp_read(w25q80bl);
 
+static const uint8_t sfdp_w25q512nw[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
+    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x1f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0x00, 0x33, 0x02, 0xa6, 0x00,
+    0x81, 0xe7, 0x14, 0xd9, 0xe9, 0x63, 0x76, 0x33,
+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xbd, 0xd5, 0x5c,
+    0x19, 0xf7, 0x5d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(w25q512nw);
+
 /*
  * Integrated Silicon Solution (ISSI)
  */
 
+static const uint8_t sfdp_is25wp128[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
+    0x9d, 0x05, 0x01, 0x03, 0x80, 0x00, 0x00, 0x02,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xf9, 0xff, 0xff, 0xff, 0xff, 0x07,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x80, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0xff, 0x23, 0x4a, 0xc9, 0x00,
+    0x82, 0xd8, 0x11, 0xc7, 0xcc, 0xcd, 0x68, 0x46,
+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c,
+    0x4a, 0x42, 0x2c, 0xff, 0xf0, 0x30, 0xc0, 0x80,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0x50, 0x19, 0x50, 0x16, 0x9e, 0xf9, 0xc0, 0x64,
+    0x8f, 0xec, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(is25wp128);
+
 static const uint8_t sfdp_is25wp256[] = {
     0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
     0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index 35785686a0ec3..33f560bb9cc6e 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -27,7 +27,9 @@ uint8_t m25p80_sfdp_w25q256(uint32_t addr);
 uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
 uint8_t m25p80_sfdp_w25q80bl(uint32_t addr);
 uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
+uint8_t m25p80_sfdp_w25q512nw(uint32_t addr);
 
+uint8_t m25p80_sfdp_is25wp128(uint32_t addr);
 uint8_t m25p80_sfdp_is25wp256(uint32_t addr);
 
 #endif
diff --git a/hw/block/trace-events b/hw/block/trace-events
index cc9a9f2460394..d1fba1d65e8a6 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -80,7 +80,7 @@ xen_block_device_destroy(unsigned int number) "%u"
 # m25p80.c
 m25p80_flash_erase(void *s, int offset, uint32_t len) "[%p] offset = 0x%"PRIx32", len = %u"
 m25p80_programming_zero_to_one(void *s, uint32_t addr, uint8_t prev, uint8_t data) "[%p] programming zero to one! addr=0x%"PRIx32"  0x%"PRIx8" -> 0x%"PRIx8
-m25p80_reset_done(void *s) "[%p] Reset done."
+m25p80_reset(void *s, const char *msg) "[%p] %s"
 m25p80_command_decoded(void *s, uint32_t cmd) "[%p] new command:0x%"PRIx32
 m25p80_complete_collecting(void *s, uint32_t cmd, int n, uint8_t ear, uint32_t cur_addr) "[%p] decode cmd: 0x%"PRIx32" len %d ear 0x%"PRIx8" addr 0x%"PRIx32
 m25p80_populated_jedec(void *s) "[%p] populated jedec code"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 020c0a84bb6e5..0cbbaedb2f189 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -95,3 +95,6 @@ config IP_OCTAL_232
     bool
     default y
     depends on IPACK
+
+config IBEX_UART
+    bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index a9e1dc26c0fa1..f47fa11bbe023 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -2,7 +2,7 @@ system_ss.add(when: 'CONFIG_CADENCE', if_true: files('cadence_uart.c'))
 system_ss.add(when: 'CONFIG_CMSDK_APB_UART', if_true: files('cmsdk-apb-uart.c'))
 system_ss.add(when: 'CONFIG_ESCC', if_true: files('escc.c'))
 system_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_apbuart.c'))
-system_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_uart.c'))
+system_ss.add(when: 'CONFIG_IBEX_UART', if_true: files('ibex_uart.c'))
 system_ss.add(when: 'CONFIG_IMX', if_true: files('imx_serial.c'))
 system_ss.add(when: 'CONFIG_IP_OCTAL_232', if_true: files('ipoctal232.c'))
 system_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('parallel-isa.c'))
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index 8c306c89e4530..8758ecba957d8 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -104,6 +104,16 @@ void cpu_reset(CPUState *cpu)
     trace_cpu_reset(cpu->cpu_index);
 }
 
+static void cpu_common_reset_enter(Object *obj, ResetType type)
+{
+    CPUState *cpu = CPU(obj);
+
+    if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+        qemu_log("CPU Reset Enter (CPU %d)\n", cpu->cpu_index);
+        log_cpu_state(cpu, cpu->cc->reset_dump_flags);
+    }
+}
+
 static void cpu_common_reset_hold(Object *obj, ResetType type)
 {
     CPUState *cpu = CPU(obj);
@@ -379,6 +389,7 @@ static void cpu_common_class_init(ObjectClass *klass, const void *data)
     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
     dc->realize = cpu_common_realizefn;
     dc->unrealize = cpu_common_unrealizefn;
+    rc->phases.enter = cpu_common_reset_enter;
     rc->phases.hold = cpu_common_reset_hold;
     rc->phases.exit = cpu_common_reset_exit;
     cpu_class_init_props(dc);
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 590c5b02aa1d8..6e98eeb0c6c47 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -448,7 +448,6 @@ ssize_t load_elf_as(const char *filename,
                             true, NULL);
 }
 
-/* return < 0 if error, otherwise the number of bytes loaded in memory */
 ssize_t load_elf_ram_sym(const char *filename,
                          uint64_t (*elf_note_fn)(void *, void *, bool),
                          uint64_t (*translate_fn)(void *, uint64_t),
@@ -457,6 +456,23 @@ ssize_t load_elf_ram_sym(const char *filename,
                          uint32_t *pflags, int elf_data_order, int elf_machine,
                          int clear_lsb, int data_swab,
                          AddressSpace *as, bool load_rom, symbol_fn_t sym_cb)
+{
+    return load_elf_ram_sym_nosz(filename, elf_note_fn, translate_fn,
+                                 translate_opaque, pentry, lowaddr, highaddr,
+                                 pflags, elf_data_order, elf_machine, clear_lsb,
+                                 data_swab, as, load_rom, sym_cb, true);
+}
+
+/* return < 0 if error, otherwise the number of bytes loaded in memory */
+ssize_t load_elf_ram_sym_nosz(const char *filename,
+                              uint64_t (*elf_note_fn)(void *, void *, bool),
+                              uint64_t (*translate_fn)(void *, uint64_t),
+                              void *translate_opaque, uint64_t *pentry,
+                              uint64_t *lowaddr, uint64_t *highaddr,
+                              uint32_t *pflags, int elf_data_order,
+                              int elf_machine, int clear_lsb, int data_swab,
+                              AddressSpace *as, bool load_rom,
+                              symbol_fn_t sym_cb, bool skip_nosz)
 {
     const int host_data_order = HOST_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB;
     int fd, must_swab;
@@ -490,12 +506,14 @@ ssize_t load_elf_ram_sym(const char *filename,
         ret = load_elf64(filename, fd, elf_note_fn,
                          translate_fn, translate_opaque, must_swab,
                          pentry, lowaddr, highaddr, pflags, elf_machine,
-                         clear_lsb, data_swab, as, load_rom, sym_cb);
+                         clear_lsb, data_swab, as, load_rom, sym_cb,
+                         skip_nosz);
     } else {
         ret = load_elf32(filename, fd, elf_note_fn,
                          translate_fn, translate_opaque, must_swab,
                          pentry, lowaddr, highaddr, pflags, elf_machine,
-                         clear_lsb, data_swab, as, load_rom, sym_cb);
+                         clear_lsb, data_swab, as, load_rom, sym_cb,
+                         skip_nosz);
     }
 
     if (ret > 0) {
@@ -507,6 +525,61 @@ ssize_t load_elf_ram_sym(const char *filename,
     return ret;
 }
 
+/* return < 0 if error, otherwise 0 */
+int load_elf_sym(const char *filename, int big_endian, int elf_machine,
+                 int clear_lsb)
+{
+    int fd, data_order, target_data_order, must_swab;
+    ssize_t ret = ELF_LOAD_FAILED;
+    uint8_t e_ident[EI_NIDENT];
+
+    fd = open(filename, O_RDONLY | O_BINARY);
+    if (fd < 0) {
+        perror(filename);
+        return -1;
+    }
+    if (read(fd, e_ident, sizeof(e_ident)) != sizeof(e_ident)) {
+        goto fail;
+    }
+    if (e_ident[0] != ELFMAG0 ||
+        e_ident[1] != ELFMAG1 ||
+        e_ident[2] != ELFMAG2 ||
+        e_ident[3] != ELFMAG3) {
+        ret = ELF_LOAD_NOT_ELF;
+        goto fail;
+    }
+#if HOST_BIG_ENDIAN
+    data_order = ELFDATA2MSB;
+#else
+    data_order = ELFDATA2LSB;
+#endif
+    must_swab = data_order != e_ident[EI_DATA];
+    if (big_endian) {
+        target_data_order = ELFDATA2MSB;
+    } else {
+        target_data_order = ELFDATA2LSB;
+    }
+
+    if (target_data_order != e_ident[EI_DATA]) {
+        ret = ELF_LOAD_WRONG_ENDIAN;
+        goto fail;
+    }
+
+    lseek(fd, 0, SEEK_SET);
+    if (e_ident[EI_CLASS] == ELFCLASS64) {
+        ret = load_elf_symbols64(filename, fd, must_swab, elf_machine,
+                                 clear_lsb);
+    } else {
+        ret = load_elf_symbols32(filename, fd, must_swab, elf_machine,
+                                 clear_lsb);
+    }
+
+ fail:
+    close(fd);
+    return ret;
+}
+
+
 static void bswap_uboot_header(uboot_image_header_t *hdr)
 {
 #if !HOST_BIG_ENDIAN
@@ -1342,6 +1415,11 @@ int rom_check_and_register_reset(void)
     return 0;
 }
 
+void rom_load(void)
+{
+    rom_reset(NULL);
+}
+
 void rom_set_fw(FWCfgState *f)
 {
     fw_cfg = f;
diff --git a/hw/core/meson.build b/hw/core/meson.build
index b5a545a0edd63..9f4c9e708bd3b 100644
--- a/hw/core/meson.build
+++ b/hw/core/meson.build
@@ -42,6 +42,7 @@ system_ss.add(files(
   'qdev-hotplug.c',
   'qdev-properties-system.c',
   'reset.c',
+  'rust_demangle.c',
   'sysbus.c',
   'vm-change-state-handler.c',
   'clock-vmstate.c',
diff --git a/hw/core/rust_demangle.c b/hw/core/rust_demangle.c
new file mode 100644
index 0000000000000..fad33f09b8cb0
--- /dev/null
+++ b/hw/core/rust_demangle.c
@@ -0,0 +1,1751 @@
+/* Demangler for the Rust programming language
+   Copyright (C) 2016-2023 Free Software Foundation, Inc.
+   Written by David Tolnay (dtolnay@gmail.com).
+   Rewritten by Eduard-Mihai Burtescu (eddyb@lyken.rs) for v0 support.
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+In addition to the permissions in the GNU Library General Public
+License, the Free Software Foundation gives you unlimited permission
+to link the compiled version of this file into combinations with other
+programs, and to distribute those combinations without any restriction
+coming from the use of this file.  (The Library Public License
+restrictions do apply in other respects; for example, they cover
+modification of the file, and distribution when not linked into a
+combined executable.)
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB.
+If not, see <http://www.gnu.org/licenses/>.  */
+
+
+#include "qemu/osdep.h"
+#include <ctype.h>
+#include "hw/core/rust_demangle.h"
+
+
+struct rust_demangler
+{
+  const char *sym;
+  size_t sym_len;
+
+  void *callback_opaque;
+  demangle_callbackref callback;
+
+  /* Position of the next character to read from the symbol. */
+  size_t next;
+
+  /* Non-zero if any error occurred. */
+  int errored;
+
+  /* Non-zero if nothing should be printed. */
+  int skipping_printing;
+
+  /* Non-zero if printing should be verbose (e.g. include hashes). */
+  int verbose;
+
+  /* Rust mangling version, with legacy mangling being -1. */
+  int version;
+
+  /* Recursion depth.  */
+  unsigned int recursion;
+  /* Maximum number of times demangle_path may be called recursively.  */
+#define RUST_MAX_RECURSION_COUNT  1024
+#define RUST_NO_RECURSION_LIMIT   ((unsigned int) -1)
+
+  uint64_t bound_lifetime_depth;
+};
+
+/* Determine host character set.  */
+#define HOST_CHARSET_UNKNOWN 0
+#define HOST_CHARSET_ASCII   1
+#define HOST_CHARSET_EBCDIC  2
+
+#if  '\n' == 0x0A && ' ' == 0x20 && '0' == 0x30 \
+   && 'A' == 0x41 && 'a' == 0x61 && '!' == 0x21
+#  define HOST_CHARSET HOST_CHARSET_ASCII
+#else
+# if '\n' == 0x15 && ' ' == 0x40 && '0' == 0xF0 \
+   && 'A' == 0xC1 && 'a' == 0x81 && '!' == 0x5A
+#  define HOST_CHARSET HOST_CHARSET_EBCDIC
+# else
+#  define HOST_CHARSET HOST_CHARSET_UNKNOWN
+# endif
+#endif
+
+/* Categories.  */
+
+enum {
+  /* In C99 */
+  _sch_isblank  = 0x0001, /* space \t */
+  _sch_iscntrl  = 0x0002, /* nonprinting characters */
+  _sch_isdigit  = 0x0004, /* 0-9 */
+  _sch_islower  = 0x0008, /* a-z */
+  _sch_isprint  = 0x0010, /* any printing character including ' ' */
+  _sch_ispunct  = 0x0020, /* all punctuation */
+  _sch_isspace  = 0x0040, /* space \t \n \r \f \v */
+  _sch_isupper  = 0x0080, /* A-Z */
+  _sch_isxdigit = 0x0100, /* 0-9A-Fa-f */
+
+  /* Extra categories useful to cpplib.  */
+  _sch_isidst = 0x0200, /* A-Za-z_ */
+  _sch_isvsp    = 0x0400, /* \n \r */
+  _sch_isnvsp   = 0x0800, /* space \t \f \v \0 */
+
+  /* Combinations of the above.  */
+  _sch_isalpha  = _sch_isupper|_sch_islower,  /* A-Za-z */
+  _sch_isalnum  = _sch_isalpha|_sch_isdigit,  /* A-Za-z0-9 */
+  _sch_isidnum  = _sch_isidst|_sch_isdigit, /* A-Za-z0-9_ */
+  _sch_isgraph  = _sch_isalnum|_sch_ispunct,  /* isprint and not space */
+  _sch_iscppsp  = _sch_isvsp|_sch_isnvsp, /* isspace + \0 */
+  _sch_isbasic  = _sch_isprint|_sch_iscppsp     /* basic charset of ISO C
+               (plus ` and @)  */
+};
+
+/* Character classification.  */
+
+/* Shorthand */
+#define bl _sch_isblank
+#define cn _sch_iscntrl
+#define di _sch_isdigit
+#define is _sch_isidst
+#define lo _sch_islower
+#define nv _sch_isnvsp
+#define pn _sch_ispunct
+#define pr _sch_isprint
+#define sp _sch_isspace
+#define up _sch_isupper
+#define vs _sch_isvsp
+#define xd _sch_isxdigit
+
+/* Masks.  */
+#define L  (const unsigned short) (lo|is   |pr) /* lower case letter */
+#define XL (const unsigned short) (lo|is|xd|pr) /* lowercase hex digit */
+#define U  (const unsigned short) (up|is   |pr) /* upper case letter */
+#define XU (const unsigned short) (up|is|xd|pr) /* uppercase hex digit */
+#define D  (const unsigned short) (di   |xd|pr) /* decimal digit */
+#define P  (const unsigned short) (pn      |pr) /* punctuation */
+#define _  (const unsigned short) (pn|is   |pr) /* underscore */
+
+#define C  (const unsigned short) (         cn) /* control character */
+#define Z  (const unsigned short) (nv      |cn) /* NUL */
+#define M  (const unsigned short) (nv|sp   |cn) /* cursor movement: \f \v */
+#define V  (const unsigned short) (vs|sp   |cn) /* vertical space: \r \n */
+#define T  (const unsigned short) (nv|sp|bl|cn) /* tab */
+#define S  (const unsigned short) (nv|sp|bl|pr) /* space */
+
+const unsigned short _sch_istable[256] =
+{
+  Z,  C,  C,  C,   C,  C,  C,  C,   /* NUL SOH STX ETX  EOT ENQ ACK BEL */
+  C,  T,  V,  M,   M,  V,  C,  C,   /* BS  HT  LF  VT   FF  CR  SO  SI  */
+  C,  C,  C,  C,   C,  C,  C,  C,   /* DLE DC1 DC2 DC3  DC4 NAK SYN ETB */
+  C,  C,  C,  C,   C,  C,  C,  C,   /* CAN EM  SUB ESC  FS  GS  RS  US  */
+  S,  P,  P,  P,   P,  P,  P,  P,   /* SP  !   "   #    $   %   &   '   */
+  P,  P,  P,  P,   P,  P,  P,  P,   /* (   )   *   +    ,   -   .   /   */
+  D,  D,  D,  D,   D,  D,  D,  D,   /* 0   1   2   3    4   5   6   7   */
+  D,  D,  P,  P,   P,  P,  P,  P,   /* 8   9   :   ;    <   =   >   ?   */
+  P, XU, XU, XU,  XU, XU, XU,  U,   /* @   A   B   C    D   E   F   G   */
+  U,  U,  U,  U,   U,  U,  U,  U,   /* H   I   J   K    L   M   N   O   */
+  U,  U,  U,  U,   U,  U,  U,  U,   /* P   Q   R   S    T   U   V   W   */
+  U,  U,  U,  P,   P,  P,  P,  _,   /* X   Y   Z   [    \   ]   ^   _   */
+  P, XL, XL, XL,  XL, XL, XL,  L,   /* `   a   b   c    d   e   f   g   */
+  L,  L,  L,  L,   L,  L,  L,  L,   /* h   i   j   k    l   m   n   o   */
+  L,  L,  L,  L,   L,  L,  L,  L,   /* p   q   r   s    t   u   v   w   */
+  L,  L,  L,  P,   P,  P,  P,  C,   /* x   y   z   {    |   }   ~   DEL */
+
+  /* high half of unsigned char is locale-specific, so all tests are
+     false in "C" locale */
+  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,
+  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,
+  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,
+  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,
+
+  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,
+  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,
+  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,
+  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,  0, 0, 0, 0,
+};
+
+#define _sch_test(c, bit) (_sch_istable[(c) & 0xff] & (unsigned short)(bit))
+
+#define ISALPHA(c)  _sch_test(c, _sch_isalpha)
+#define ISALNUM(c)  _sch_test(c, _sch_isalnum)
+#define ISBLANK(c)  _sch_test(c, _sch_isblank)
+#define ISCNTRL(c)  _sch_test(c, _sch_iscntrl)
+#define ISDIGIT(c)  _sch_test(c, _sch_isdigit)
+#define ISGRAPH(c)  _sch_test(c, _sch_isgraph)
+#define ISLOWER(c)  _sch_test(c, _sch_islower)
+#define ISPRINT(c)  _sch_test(c, _sch_isprint)
+#define ISPUNCT(c)  _sch_test(c, _sch_ispunct)
+#define ISSPACE(c)  _sch_test(c, _sch_isspace)
+#define ISUPPER(c)  _sch_test(c, _sch_isupper)
+#define ISXDIGIT(c) _sch_test(c, _sch_isxdigit)
+
+#define ISIDNUM(c)  _sch_test(c, _sch_isidnum)
+#define ISIDST(c) _sch_test(c, _sch_isidst)
+#define IS_ISOBASIC(c)  _sch_test(c, _sch_isbasic)
+#define IS_VSPACE(c)  _sch_test(c, _sch_isvsp)
+#define IS_NVSPACE(c) _sch_test(c, _sch_isnvsp)
+#define IS_SPACE_OR_NUL(c)  _sch_test(c, _sch_iscppsp)
+
+/* Character transformation.  */
+extern const unsigned char  _sch_toupper[256];
+extern const unsigned char  _sch_tolower[256];
+#define TOUPPER(c) _sch_toupper[(c) & 0xff]
+#define TOLOWER(c) _sch_tolower[(c) & 0xff]
+
+/* Parsing functions. */
+
+static char
+peek (const struct rust_demangler *rdm)
+{
+  if (rdm->next < rdm->sym_len)
+    return rdm->sym[rdm->next];
+  return 0;
+}
+
+static int
+eat (struct rust_demangler *rdm, char c)
+{
+  if (peek (rdm) == c)
+    {
+      rdm->next++;
+      return 1;
+    }
+  else
+    return 0;
+}
+
+static char
+next (struct rust_demangler *rdm)
+{
+  char c = peek (rdm);
+  if (!c)
+    rdm->errored = 1;
+  else
+    rdm->next++;
+  return c;
+}
+
+static uint64_t
+parse_integer_62 (struct rust_demangler *rdm)
+{
+  char c;
+  uint64_t x;
+
+  if (eat (rdm, '_'))
+    return 0;
+
+  x = 0;
+  while (!eat (rdm, '_') && !rdm->errored)
+    {
+      c = next (rdm);
+      x *= 62;
+      if (ISDIGIT (c))
+        x += c - '0';
+      else if (ISLOWER (c))
+        x += 10 + (c - 'a');
+      else if (ISUPPER (c))
+        x += 10 + 26 + (c - 'A');
+      else
+        {
+          rdm->errored = 1;
+          return 0;
+        }
+    }
+  return x + 1;
+}
+
+static uint64_t
+parse_opt_integer_62 (struct rust_demangler *rdm, char tag)
+{
+  if (!eat (rdm, tag))
+    return 0;
+  return 1 + parse_integer_62 (rdm);
+}
+
+static uint64_t
+parse_disambiguator (struct rust_demangler *rdm)
+{
+  return parse_opt_integer_62 (rdm, 's');
+}
+
+static size_t
+parse_hex_nibbles (struct rust_demangler *rdm, uint64_t *value)
+{
+  char c;
+  size_t hex_len;
+
+  hex_len = 0;
+  *value = 0;
+
+  while (!eat (rdm, '_'))
+    {
+      *value <<= 4;
+
+      c = next (rdm);
+      if (ISDIGIT (c))
+        *value |= c - '0';
+      else if (c >= 'a' && c <= 'f')
+        *value |= 10 + (c - 'a');
+      else
+        {
+          rdm->errored = 1;
+          return 0;
+        }
+      hex_len++;
+    }
+
+  return hex_len;
+}
+
+struct rust_mangled_ident
+{
+  /* ASCII part of the identifier. */
+  const char *ascii;
+  size_t ascii_len;
+
+  /* Punycode insertion codes for Unicode codepoints, if any. */
+  const char *punycode;
+  size_t punycode_len;
+};
+
+static struct rust_mangled_ident
+parse_ident (struct rust_demangler *rdm)
+{
+  char c;
+  size_t start, len;
+  int is_punycode = 0;
+  struct rust_mangled_ident ident;
+
+  ident.ascii = NULL;
+  ident.ascii_len = 0;
+  ident.punycode = NULL;
+  ident.punycode_len = 0;
+
+  if (rdm->version != -1)
+    is_punycode = eat (rdm, 'u');
+
+  c = next (rdm);
+  if (!ISDIGIT (c))
+    {
+      rdm->errored = 1;
+      return ident;
+    }
+  len = c - '0';
+
+  if (c != '0')
+    while (ISDIGIT (peek (rdm)))
+      len = len * 10 + (next (rdm) - '0');
+
+  /* Skip past the optional `_` separator (v0). */
+  if (rdm->version != -1)
+    eat (rdm, '_');
+
+  start = rdm->next;
+  rdm->next += len;
+  /* Check for overflows. */
+  if ((start > rdm->next) || (rdm->next > rdm->sym_len))
+    {
+      rdm->errored = 1;
+      return ident;
+    }
+
+  ident.ascii = rdm->sym + start;
+  ident.ascii_len = len;
+
+  if (is_punycode)
+    {
+      ident.punycode_len = 0;
+      while (ident.ascii_len > 0)
+        {
+          ident.ascii_len--;
+
+          /* The last '_' is a separator between ascii & punycode. */
+          if (ident.ascii[ident.ascii_len] == '_')
+            break;
+
+          ident.punycode_len++;
+        }
+      if (!ident.punycode_len)
+        {
+          rdm->errored = 1;
+          return ident;
+        }
+      ident.punycode = ident.ascii + (len - ident.punycode_len);
+    }
+
+  if (ident.ascii_len == 0)
+    ident.ascii = NULL;
+
+  return ident;
+}
+
+/* Printing functions. */
+
+static void
+print_str (struct rust_demangler *rdm, const char *data, size_t len)
+{
+  if (!rdm->errored && !rdm->skipping_printing)
+    rdm->callback (data, len, rdm->callback_opaque);
+}
+
+#define PRINT(s) print_str (rdm, s, strlen (s))
+
+static void
+print_uint64 (struct rust_demangler *rdm, uint64_t x)
+{
+  char s[21];
+  snprintf (s, 21, "%" PRIu64, x);
+  PRINT (s);
+}
+
+static void
+print_uint64_hex (struct rust_demangler *rdm, uint64_t x)
+{
+  char s[17];
+  snprintf (s, 17, "%" PRIx64, x);
+  PRINT (s);
+}
+
+/* Return a 0x0-0xf value if the char is 0-9a-f, and -1 otherwise. */
+static int
+decode_lower_hex_nibble (char nibble)
+{
+  if ('0' <= nibble && nibble <= '9')
+    return nibble - '0';
+  if ('a' <= nibble && nibble <= 'f')
+    return 0xa + (nibble - 'a');
+  return -1;
+}
+
+/* Return the unescaped character for a "$...$" escape, or 0 if invalid. */
+static char
+decode_legacy_escape (const char *e, size_t len, size_t *out_len)
+{
+  char c = 0;
+  size_t escape_len = 0;
+  int lo_nibble = -1, hi_nibble = -1;
+
+  if (len < 3 || e[0] != '$')
+    return 0;
+
+  e++;
+  len--;
+
+  if (e[0] == 'C')
+    {
+      escape_len = 1;
+
+      c = ',';
+    }
+  else if (len > 2)
+    {
+      escape_len = 2;
+
+      if (e[0] == 'S' && e[1] == 'P')
+        c = '@';
+      else if (e[0] == 'B' && e[1] == 'P')
+        c = '*';
+      else if (e[0] == 'R' && e[1] == 'F')
+        c = '&';
+      else if (e[0] == 'L' && e[1] == 'T')
+        c = '<';
+      else if (e[0] == 'G' && e[1] == 'T')
+        c = '>';
+      else if (e[0] == 'L' && e[1] == 'P')
+        c = '(';
+      else if (e[0] == 'R' && e[1] == 'P')
+        c = ')';
+      else if (e[0] == 'u' && len > 3)
+        {
+          escape_len = 3;
+
+          hi_nibble = decode_lower_hex_nibble (e[1]);
+          if (hi_nibble < 0)
+            return 0;
+          lo_nibble = decode_lower_hex_nibble (e[2]);
+          if (lo_nibble < 0)
+            return 0;
+
+          /* Only allow non-control ASCII characters. */
+          if (hi_nibble > 7)
+            return 0;
+          c = (hi_nibble << 4) | lo_nibble;
+          if (c < 0x20)
+            return 0;
+        }
+    }
+
+  if (!c || len <= escape_len || e[escape_len] != '$')
+    return 0;
+
+  *out_len = 2 + escape_len;
+  return c;
+}
+
+static void
+print_ident (struct rust_demangler *rdm, struct rust_mangled_ident ident)
+{
+  char unescaped;
+  uint8_t *out, *p, d;
+  size_t len, cap, punycode_pos, j;
+  /* Punycode parameters and state. */
+  uint32_t c;
+  size_t base, t_min, t_max, skew, damp, bias, i;
+  size_t delta, w, k, t;
+
+  if (rdm->errored || rdm->skipping_printing)
+    return;
+
+  if (rdm->version == -1)
+    {
+      /* Ignore leading underscores preceding escape sequences.
+         The mangler inserts an underscore to make sure the
+         identifier begins with a XID_Start character. */
+      if (ident.ascii_len >= 2 && ident.ascii[0] == '_'
+          && ident.ascii[1] == '$')
+        {
+          ident.ascii++;
+          ident.ascii_len--;
+        }
+
+      while (ident.ascii_len > 0)
+        {
+          /* Handle legacy escape sequences ("$...$", ".." or "."). */
+          if (ident.ascii[0] == '$')
+            {
+              unescaped
+                  = decode_legacy_escape (ident.ascii, ident.ascii_len, &len);
+              if (unescaped)
+                print_str (rdm, &unescaped, 1);
+              else
+                {
+                  /* Unexpected escape sequence, print the rest verbatim. */
+                  print_str (rdm, ident.ascii, ident.ascii_len);
+                  return;
+                }
+            }
+          else if (ident.ascii[0] == '.')
+            {
+              if (ident.ascii_len >= 2 && ident.ascii[1] == '.')
+                {
+                  /* ".." becomes "::" */
+                  PRINT ("::");
+                  len = 2;
+                }
+              else
+                {
+                  PRINT (".");
+                  len = 1;
+                }
+            }
+          else
+            {
+              /* Print everything before the next escape sequence, at once. */
+              for (len = 0; len < ident.ascii_len; len++)
+                if (ident.ascii[len] == '$' || ident.ascii[len] == '.')
+                  break;
+
+              print_str (rdm, ident.ascii, len);
+            }
+
+          ident.ascii += len;
+          ident.ascii_len -= len;
+        }
+
+      return;
+    }
+
+  if (!ident.punycode)
+    {
+      print_str (rdm, ident.ascii, ident.ascii_len);
+      return;
+    }
+
+  len = 0;
+  cap = 4;
+  while (cap < ident.ascii_len)
+    {
+      cap *= 2;
+      /* Check for overflows. */
+      if ((cap * 4) / 4 != cap)
+        {
+          rdm->errored = 1;
+          return;
+        }
+    }
+
+  /* Store the output codepoints as groups of 4 UTF-8 bytes. */
+  out = (uint8_t *)malloc (cap * 4);
+  if (!out)
+    {
+      rdm->errored = 1;
+      return;
+    }
+
+  /* Populate initial output from ASCII fragment. */
+  for (len = 0; len < ident.ascii_len; len++)
+    {
+      p = out + 4 * len;
+      p[0] = 0;
+      p[1] = 0;
+      p[2] = 0;
+      p[3] = ident.ascii[len];
+    }
+
+  /* Punycode parameters and initial state. */
+  base = 36;
+  t_min = 1;
+  t_max = 26;
+  skew = 38;
+  damp = 700;
+  bias = 72;
+  i = 0;
+  c = 0x80;
+
+  punycode_pos = 0;
+  while (punycode_pos < ident.punycode_len)
+    {
+      /* Read one delta value. */
+      delta = 0;
+      w = 1;
+      k = 0;
+      do
+        {
+          k += base;
+          t = k < bias ? 0 : (k - bias);
+          if (t < t_min)
+            t = t_min;
+          if (t > t_max)
+            t = t_max;
+
+          if (punycode_pos >= ident.punycode_len)
+            goto cleanup;
+          d = ident.punycode[punycode_pos++];
+
+          if (ISLOWER (d))
+            d = d - 'a';
+          else if (ISDIGIT (d))
+            d = 26 + (d - '0');
+          else
+            {
+              rdm->errored = 1;
+              goto cleanup;
+            }
+
+          delta += d * w;
+          w *= base - t;
+        }
+      while (d >= t);
+
+      /* Compute the new insert position and character. */
+      len++;
+      i += delta;
+      c += i / len;
+      i %= len;
+
+      /* Ensure enough space is available. */
+      if (cap < len)
+        {
+          cap *= 2;
+          /* Check for overflows. */
+          if ((cap * 4) / 4 != cap || cap < len)
+            {
+              rdm->errored = 1;
+              goto cleanup;
+            }
+        }
+      p = (uint8_t *)realloc (out, cap * 4);
+      if (!p)
+        {
+          rdm->errored = 1;
+          goto cleanup;
+        }
+      out = p;
+
+      /* Move the characters after the insert position. */
+      p = out + i * 4;
+      memmove (p + 4, p, (len - i - 1) * 4);
+
+      /* Insert the new character, as UTF-8 bytes. */
+      p[0] = c >= 0x10000 ? 0xf0 | (c >> 18) : 0;
+      p[1] = c >= 0x800 ? (c < 0x10000 ? 0xe0 : 0x80) | ((c >> 12) & 0x3f) : 0;
+      p[2] = (c < 0x800 ? 0xc0 : 0x80) | ((c >> 6) & 0x3f);
+      p[3] = 0x80 | (c & 0x3f);
+
+      /* If there are no more deltas, decoding is complete. */
+      if (punycode_pos == ident.punycode_len)
+        break;
+
+      i++;
+
+      /* Perform bias adaptation. */
+      delta /= damp;
+      damp = 2;
+
+      delta += delta / len;
+      k = 0;
+      while (delta > ((base - t_min) * t_max) / 2)
+        {
+          delta /= base - t_min;
+          k += base;
+        }
+      bias = k + ((base - t_min + 1) * delta) / (delta + skew);
+    }
+
+  /* Remove all the 0 bytes to leave behind an UTF-8 string. */
+  for (i = 0, j = 0; i < len * 4; i++)
+    if (out[i] != 0)
+      out[j++] = out[i];
+
+  print_str (rdm, (const char *)out, j);
+
+cleanup:
+  free (out);
+}
+
+/* Print the lifetime according to the previously decoded index.
+   An index of `0` always refers to `'_`, but starting with `1`,
+   indices refer to late-bound lifetimes introduced by a binder. */
+static void
+print_lifetime_from_index (struct rust_demangler *rdm, uint64_t lt)
+{
+  char c;
+  uint64_t depth;
+
+  PRINT ("'");
+  if (lt == 0)
+    {
+      PRINT ("_");
+      return;
+    }
+
+  depth = rdm->bound_lifetime_depth - lt;
+  /* Try to print lifetimes alphabetically first. */
+  if (depth < 26)
+    {
+      c = 'a' + depth;
+      print_str (rdm, &c, 1);
+    }
+  else
+    {
+      /* Use `'_123` after running out of letters. */
+      PRINT ("_");
+      print_uint64 (rdm, depth);
+    }
+}
+
+/* Demangling functions. */
+
+static void demangle_binder (struct rust_demangler *rdm);
+static void demangle_path (struct rust_demangler *rdm, int in_value);
+static void demangle_generic_arg (struct rust_demangler *rdm);
+static void demangle_type (struct rust_demangler *rdm);
+static int demangle_path_maybe_open_generics (struct rust_demangler *rdm);
+static void demangle_dyn_trait (struct rust_demangler *rdm);
+static void demangle_const (struct rust_demangler *rdm);
+static void demangle_const_uint (struct rust_demangler *rdm);
+static void demangle_const_int (struct rust_demangler *rdm);
+static void demangle_const_bool (struct rust_demangler *rdm);
+static void demangle_const_char (struct rust_demangler *rdm);
+
+/* Optionally enter a binder ('G') for late-bound lifetimes,
+   printing e.g. `for<'a, 'b> `, and make those lifetimes visible
+   to the caller (via depth level, which the caller should reset). */
+static void
+demangle_binder (struct rust_demangler *rdm)
+{
+  uint64_t i, bound_lifetimes;
+
+  if (rdm->errored)
+    return;
+
+  bound_lifetimes = parse_opt_integer_62 (rdm, 'G');
+  if (bound_lifetimes > 0)
+    {
+      PRINT ("for<");
+      for (i = 0; i < bound_lifetimes; i++)
+        {
+          if (i > 0)
+            PRINT (", ");
+          rdm->bound_lifetime_depth++;
+          print_lifetime_from_index (rdm, 1);
+        }
+      PRINT ("> ");
+    }
+}
+
+static void
+demangle_path (struct rust_demangler *rdm, int in_value)
+{
+  char tag, ns;
+  int was_skipping_printing;
+  size_t i, backref, old_next;
+  uint64_t dis;
+  struct rust_mangled_ident name;
+
+  if (rdm->errored)
+    return;
+
+  if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
+    {
+      ++ rdm->recursion;
+      if (rdm->recursion > RUST_MAX_RECURSION_COUNT)
+  /* FIXME: There ought to be a way to report
+     that the recursion limit has been reached.  */
+  goto fail_return;
+    }
+
+  switch (tag = next (rdm))
+    {
+    case 'C':
+      dis = parse_disambiguator (rdm);
+      name = parse_ident (rdm);
+
+      print_ident (rdm, name);
+      if (rdm->verbose)
+        {
+          PRINT ("[");
+          print_uint64_hex (rdm, dis);
+          PRINT ("]");
+        }
+      break;
+    case 'N':
+      ns = next (rdm);
+      if (!ISLOWER (ns) && !ISUPPER (ns))
+  goto fail_return;
+
+      demangle_path (rdm, in_value);
+
+      dis = parse_disambiguator (rdm);
+      name = parse_ident (rdm);
+
+      if (ISUPPER (ns))
+        {
+          /* Special namespaces, like closures and shims. */
+          PRINT ("::{");
+          switch (ns)
+            {
+            case 'C':
+              PRINT ("closure");
+              break;
+            case 'S':
+              PRINT ("shim");
+              break;
+            default:
+              print_str (rdm, &ns, 1);
+            }
+          if (name.ascii || name.punycode)
+            {
+              PRINT (":");
+              print_ident (rdm, name);
+            }
+          PRINT ("#");
+          print_uint64 (rdm, dis);
+          PRINT ("}");
+        }
+      else
+        {
+          /* Implementation-specific/unspecified namespaces. */
+
+          if (name.ascii || name.punycode)
+            {
+              PRINT ("::");
+              print_ident (rdm, name);
+            }
+        }
+      break;
+    case 'M':
+    case 'X':
+      /* Ignore the `impl`'s own path.*/
+      parse_disambiguator (rdm);
+      was_skipping_printing = rdm->skipping_printing;
+      rdm->skipping_printing = 1;
+      demangle_path (rdm, in_value);
+      rdm->skipping_printing = was_skipping_printing;
+      /* fallthrough */
+    case 'Y':
+      PRINT ("<");
+      demangle_type (rdm);
+      if (tag != 'M')
+        {
+          PRINT (" as ");
+          demangle_path (rdm, 0);
+        }
+      PRINT (">");
+      break;
+    case 'I':
+      demangle_path (rdm, in_value);
+      if (in_value)
+        PRINT ("::");
+      PRINT ("<");
+      for (i = 0; !rdm->errored && !eat (rdm, 'E'); i++)
+        {
+          if (i > 0)
+            PRINT (", ");
+          demangle_generic_arg (rdm);
+        }
+      PRINT (">");
+      break;
+    case 'B':
+      backref = parse_integer_62 (rdm);
+      if (!rdm->skipping_printing)
+        {
+          old_next = rdm->next;
+          rdm->next = backref;
+          demangle_path (rdm, in_value);
+          rdm->next = old_next;
+        }
+      break;
+    default:
+      goto fail_return;
+    }
+  goto pass_return;
+
+ fail_return:
+  rdm->errored = 1;
+ pass_return:
+  if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
+    -- rdm->recursion;
+}
+
+static void
+demangle_generic_arg (struct rust_demangler *rdm)
+{
+  uint64_t lt;
+  if (eat (rdm, 'L'))
+    {
+      lt = parse_integer_62 (rdm);
+      print_lifetime_from_index (rdm, lt);
+    }
+  else if (eat (rdm, 'K'))
+    demangle_const (rdm);
+  else
+    demangle_type (rdm);
+}
+
+static const char *
+basic_type (char tag)
+{
+  switch (tag)
+    {
+    case 'b':
+      return "bool";
+    case 'c':
+      return "char";
+    case 'e':
+      return "str";
+    case 'u':
+      return "()";
+    case 'a':
+      return "i8";
+    case 's':
+      return "i16";
+    case 'l':
+      return "i32";
+    case 'x':
+      return "i64";
+    case 'n':
+      return "i128";
+    case 'i':
+      return "isize";
+    case 'h':
+      return "u8";
+    case 't':
+      return "u16";
+    case 'm':
+      return "u32";
+    case 'y':
+      return "u64";
+    case 'o':
+      return "u128";
+    case 'j':
+      return "usize";
+    case 'f':
+      return "f32";
+    case 'd':
+      return "f64";
+    case 'z':
+      return "!";
+    case 'p':
+      return "_";
+    case 'v':
+      return "...";
+
+    default:
+      return NULL;
+    }
+}
+
+static void
+demangle_type (struct rust_demangler *rdm)
+{
+  char tag;
+  size_t i, old_next, backref;
+  uint64_t lt, old_bound_lifetime_depth;
+  const char *basic;
+  struct rust_mangled_ident abi;
+
+  if (rdm->errored)
+    return;
+
+  tag = next (rdm);
+
+  basic = basic_type (tag);
+  if (basic)
+    {
+      PRINT (basic);
+      return;
+    }
+
+   if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
+    {
+      ++ rdm->recursion;
+      if (rdm->recursion > RUST_MAX_RECURSION_COUNT)
+  /* FIXME: There ought to be a way to report
+     that the recursion limit has been reached.  */
+  {
+    rdm->errored = 1;
+    -- rdm->recursion;
+    return;
+  }
+    }
+
+  switch (tag)
+    {
+    case 'R':
+    case 'Q':
+      PRINT ("&");
+      if (eat (rdm, 'L'))
+        {
+          lt = parse_integer_62 (rdm);
+          if (lt)
+            {
+              print_lifetime_from_index (rdm, lt);
+              PRINT (" ");
+            }
+        }
+      if (tag != 'R')
+        PRINT ("mut ");
+      demangle_type (rdm);
+      break;
+    case 'P':
+    case 'O':
+      PRINT ("*");
+      if (tag != 'P')
+        PRINT ("mut ");
+      else
+        PRINT ("const ");
+      demangle_type (rdm);
+      break;
+    case 'A':
+    case 'S':
+      PRINT ("[");
+      demangle_type (rdm);
+      if (tag == 'A')
+        {
+          PRINT ("; ");
+          demangle_const (rdm);
+        }
+      PRINT ("]");
+      break;
+    case 'T':
+      PRINT ("(");
+      for (i = 0; !rdm->errored && !eat (rdm, 'E'); i++)
+        {
+          if (i > 0)
+            PRINT (", ");
+          demangle_type (rdm);
+        }
+      if (i == 1)
+        PRINT (",");
+      PRINT (")");
+      break;
+    case 'F':
+      old_bound_lifetime_depth = rdm->bound_lifetime_depth;
+      demangle_binder (rdm);
+
+      if (eat (rdm, 'U'))
+        PRINT ("unsafe ");
+
+      if (eat (rdm, 'K'))
+        {
+          if (eat (rdm, 'C'))
+            {
+              abi.ascii = "C";
+              abi.ascii_len = 1;
+            }
+          else
+            {
+              abi = parse_ident (rdm);
+              if (!abi.ascii || abi.punycode)
+                {
+                  rdm->errored = 1;
+                  goto restore;
+                }
+            }
+
+          PRINT ("extern \"");
+
+          /* If the ABI had any `-`, they were replaced with `_`,
+             so the parts between `_` have to be re-joined with `-`. */
+          for (i = 0; i < abi.ascii_len; i++)
+            {
+              if (abi.ascii[i] == '_')
+                {
+                  print_str (rdm, abi.ascii, i);
+                  PRINT ("-");
+                  abi.ascii += i + 1;
+                  abi.ascii_len -= i + 1;
+                  i = 0;
+                }
+            }
+          print_str (rdm, abi.ascii, abi.ascii_len);
+
+          PRINT ("\" ");
+        }
+
+      PRINT ("fn(");
+      for (i = 0; !rdm->errored && !eat (rdm, 'E'); i++)
+        {
+          if (i > 0)
+            PRINT (", ");
+          demangle_type (rdm);
+        }
+      PRINT (")");
+
+      if (eat (rdm, 'u'))
+        {
+          /* Skip printing the return type if it's 'u', i.e. `()`. */
+        }
+      else
+        {
+          PRINT (" -> ");
+          demangle_type (rdm);
+        }
+
+    /* Restore `bound_lifetime_depth` to outside the binder. */
+    restore:
+      rdm->bound_lifetime_depth = old_bound_lifetime_depth;
+      break;
+    case 'D':
+      PRINT ("dyn ");
+
+      old_bound_lifetime_depth = rdm->bound_lifetime_depth;
+      demangle_binder (rdm);
+
+      for (i = 0; !rdm->errored && !eat (rdm, 'E'); i++)
+        {
+          if (i > 0)
+            PRINT (" + ");
+          demangle_dyn_trait (rdm);
+        }
+
+      /* Restore `bound_lifetime_depth` to outside the binder. */
+      rdm->bound_lifetime_depth = old_bound_lifetime_depth;
+
+      if (!eat (rdm, 'L'))
+        {
+          rdm->errored = 1;
+          return;
+        }
+      lt = parse_integer_62 (rdm);
+      if (lt)
+        {
+          PRINT (" + ");
+          print_lifetime_from_index (rdm, lt);
+        }
+      break;
+    case 'B':
+      backref = parse_integer_62 (rdm);
+      if (!rdm->skipping_printing)
+        {
+          old_next = rdm->next;
+          rdm->next = backref;
+          demangle_type (rdm);
+          rdm->next = old_next;
+        }
+      break;
+    default:
+      /* Go back to the tag, so `demangle_path` also sees it. */
+      rdm->next--;
+      demangle_path (rdm, 0);
+    }
+
+  if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
+    -- rdm->recursion;
+}
+
+/* A trait in a trait object may have some "existential projections"
+   (i.e. associated type bindings) after it, which should be printed
+   in the `<...>` of the trait, e.g. `dyn Trait<T, U, Assoc=X>`.
+   To this end, this method will keep the `<...>` of an 'I' path
+   open, by omitting the `>`, and return `Ok(true)` in that case. */
+static int
+demangle_path_maybe_open_generics (struct rust_demangler *rdm)
+{
+  int open;
+  size_t i, old_next, backref;
+
+  open = 0;
+
+  if (rdm->errored)
+    return open;
+
+  if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
+    {
+      ++ rdm->recursion;
+      if (rdm->recursion > RUST_MAX_RECURSION_COUNT)
+  {
+    /* FIXME: There ought to be a way to report
+       that the recursion limit has been reached.  */
+    rdm->errored = 1;
+    goto end_of_func;
+  }
+    }
+
+  if (eat (rdm, 'B'))
+    {
+      backref = parse_integer_62 (rdm);
+      if (!rdm->skipping_printing)
+        {
+          old_next = rdm->next;
+          rdm->next = backref;
+          open = demangle_path_maybe_open_generics (rdm);
+          rdm->next = old_next;
+        }
+    }
+  else if (eat (rdm, 'I'))
+    {
+      demangle_path (rdm, 0);
+      PRINT ("<");
+      open = 1;
+      for (i = 0; !rdm->errored && !eat (rdm, 'E'); i++)
+        {
+          if (i > 0)
+            PRINT (", ");
+          demangle_generic_arg (rdm);
+        }
+    }
+  else
+    demangle_path (rdm, 0);
+
+ end_of_func:
+  if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
+    -- rdm->recursion;
+
+  return open;
+}
+
+static void
+demangle_dyn_trait (struct rust_demangler *rdm)
+{
+  int open;
+  struct rust_mangled_ident name;
+
+  if (rdm->errored)
+    return;
+
+  open = demangle_path_maybe_open_generics (rdm);
+
+  while (eat (rdm, 'p'))
+    {
+      if (!open)
+        PRINT ("<");
+      else
+        PRINT (", ");
+      open = 1;
+
+      name = parse_ident (rdm);
+      print_ident (rdm, name);
+      PRINT (" = ");
+      demangle_type (rdm);
+    }
+
+  if (open)
+    PRINT (">");
+}
+
+static void
+demangle_const (struct rust_demangler *rdm)
+{
+  char ty_tag;
+  size_t old_next, backref;
+
+  if (rdm->errored)
+    return;
+
+  if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
+    {
+      ++ rdm->recursion;
+      if (rdm->recursion > RUST_MAX_RECURSION_COUNT)
+  /* FIXME: There ought to be a way to report
+     that the recursion limit has been reached.  */
+  goto fail_return;
+    }
+
+  if (eat (rdm, 'B'))
+    {
+      backref = parse_integer_62 (rdm);
+      if (!rdm->skipping_printing)
+        {
+          old_next = rdm->next;
+          rdm->next = backref;
+          demangle_const (rdm);
+          rdm->next = old_next;
+        }
+      goto pass_return;
+    }
+
+  ty_tag = next (rdm);
+  switch (ty_tag)
+    {
+    /* Placeholder. */
+    case 'p':
+      PRINT ("_");
+      goto pass_return;
+
+    /* Unsigned integer types. */
+    case 'h':
+    case 't':
+    case 'm':
+    case 'y':
+    case 'o':
+    case 'j':
+      demangle_const_uint (rdm);
+      break;
+
+    /* Signed integer types. */
+    case 'a':
+    case 's':
+    case 'l':
+    case 'x':
+    case 'n':
+    case 'i':
+      demangle_const_int (rdm);
+      break;
+
+    /* Boolean. */
+    case 'b':
+      demangle_const_bool (rdm);
+      break;
+
+    /* Character. */
+    case 'c':
+      demangle_const_char (rdm);
+      break;
+
+    default:
+      goto fail_return;
+    }
+
+  if (!rdm->errored && rdm->verbose)
+    {
+      PRINT (": ");
+      PRINT (basic_type (ty_tag));
+    }
+  goto pass_return;
+
+ fail_return:
+  rdm->errored = 1;
+ pass_return:
+  if (rdm->recursion != RUST_NO_RECURSION_LIMIT)
+    -- rdm->recursion;
+}
+
+static void
+demangle_const_uint (struct rust_demangler *rdm)
+{
+  size_t hex_len;
+  uint64_t value;
+
+  if (rdm->errored)
+    return;
+
+  hex_len = parse_hex_nibbles (rdm, &value);
+
+  if (hex_len > 16)
+    {
+      /* Print anything that doesn't fit in `uint64_t` verbatim. */
+      PRINT ("0x");
+      print_str (rdm, rdm->sym + (rdm->next - hex_len), hex_len);
+    }
+  else if (hex_len > 0)
+    print_uint64 (rdm, value);
+  else
+    rdm->errored = 1;
+}
+
+static void
+demangle_const_int (struct rust_demangler *rdm)
+{
+  if (eat (rdm, 'n'))
+    PRINT ("-");
+  demangle_const_uint (rdm);
+}
+
+static void
+demangle_const_bool (struct rust_demangler *rdm)
+{
+  uint64_t value;
+
+  if (parse_hex_nibbles (rdm, &value) != 1)
+    {
+      rdm->errored = 1;
+      return;
+    }
+
+  if (value == 0)
+    PRINT ("false");
+  else if (value == 1)
+    PRINT ("true");
+  else
+    rdm->errored = 1;
+}
+
+static void
+demangle_const_char (struct rust_demangler *rdm)
+{
+  size_t hex_len;
+  uint64_t value;
+
+  hex_len = parse_hex_nibbles (rdm, &value);
+
+  if (hex_len == 0 || hex_len > 8)
+    {
+      rdm->errored = 1;
+      return;
+    }
+
+  /* Match Rust's character "debug" output as best as we can. */
+  PRINT ("'");
+  if (value == '\t')
+    PRINT ("\\t");
+  else if (value == '\r')
+    PRINT ("\\r");
+  else if (value == '\n')
+    PRINT ("\\n");
+  else if (value > ' ' && value < '~')
+    {
+      /* Rust also considers many non-ASCII codepoints to be printable, but
+   that logic is not easily ported to C. */
+      char c = value;
+      print_str (rdm, &c, 1);
+    }
+  else
+    {
+      PRINT ("\\u{");
+      print_uint64_hex (rdm, value);
+      PRINT ("}");
+    }
+  PRINT ("'");
+}
+
+/* A legacy hash is the prefix "h" followed by 16 lowercase hex digits.
+   The hex digits must contain at least 5 distinct digits. */
+static int
+is_legacy_prefixed_hash (struct rust_mangled_ident ident)
+{
+  uint16_t seen;
+  int nibble;
+  size_t i, count;
+
+  if (ident.ascii_len != 17 || ident.ascii[0] != 'h')
+    return 0;
+
+  seen = 0;
+  for (i = 0; i < 16; i++)
+    {
+      nibble = decode_lower_hex_nibble (ident.ascii[1 + i]);
+      if (nibble < 0)
+        return 0;
+      seen |= (uint16_t)1 << nibble;
+    }
+
+  /* Count how many distinct digits were seen. */
+  count = 0;
+  while (seen)
+    {
+      if (seen & 1)
+        count++;
+      seen >>= 1;
+    }
+
+  return count >= 5;
+}
+
+int
+rust_demangle_callback (const char *mangled, int options,
+                        demangle_callbackref callback, void *opaque)
+{
+  const char *p;
+  struct rust_demangler rdm;
+  struct rust_mangled_ident ident;
+
+  rdm.sym = mangled;
+  rdm.sym_len = 0;
+
+  rdm.callback_opaque = opaque;
+  rdm.callback = callback;
+
+  rdm.next = 0;
+  rdm.errored = 0;
+  rdm.skipping_printing = 0;
+  rdm.verbose = (options & DMGL_VERBOSE) != 0;
+  rdm.version = 0;
+  rdm.recursion = (options & DMGL_NO_RECURSE_LIMIT) ? RUST_NO_RECURSION_LIMIT : 0;
+  rdm.bound_lifetime_depth = 0;
+
+  /* Rust symbols always start with _R (v0) or _ZN (legacy). */
+  if (rdm.sym[0] == '_' && rdm.sym[1] == 'R')
+    rdm.sym += 2;
+  else if (rdm.sym[0] == '_' && rdm.sym[1] == 'Z' && rdm.sym[2] == 'N')
+    {
+      rdm.sym += 3;
+      rdm.version = -1;
+    }
+  else
+    return 0;
+
+  /* Paths (v0) always start with uppercase characters. */
+  if (rdm.version != -1 && !ISUPPER (rdm.sym[0]))
+    return 0;
+
+  /* Rust symbols (v0) use only [_0-9a-zA-Z] characters. */
+  for (p = rdm.sym; *p; p++)
+    {
+      /* Rust v0 symbols can have '.' suffixes, ignore those.  */
+      if (rdm.version == 0 && *p == '.')
+        break;
+
+      rdm.sym_len++;
+
+      if (*p == '_' || ISALNUM (*p))
+        continue;
+
+      /* Legacy Rust symbols can also contain [.:$] characters.
+         Or @ in the .suffix (which will be skipped, see below). */
+      if (rdm.version == -1 && (*p == '$' || *p == '.' || *p == ':'
+                                || *p == '@'))
+        continue;
+
+      return 0;
+    }
+
+  /* Legacy Rust symbols need to be handled separately. */
+  if (rdm.version == -1)
+    {
+      /* Legacy Rust symbols always end with E.  But can be followed by a
+         .suffix (which we want to ignore).  */
+      int dot_suffix = 1;
+      while (rdm.sym_len > 0 &&
+             !(dot_suffix && rdm.sym[rdm.sym_len - 1] == 'E'))
+        {
+          dot_suffix = rdm.sym[rdm.sym_len - 1] == '.';
+          rdm.sym_len--;
+        }
+
+      if (!(rdm.sym_len > 0 && rdm.sym[rdm.sym_len - 1] == 'E'))
+        return 0;
+      rdm.sym_len--;
+
+      /* Legacy Rust symbols also always end with a path segment
+         that encodes a 16 hex digit hash, i.e. '17h[a-f0-9]{16}'.
+         This early check, before any parse_ident calls, should
+         quickly filter out most C++ symbols unrelated to Rust. */
+      if (!(rdm.sym_len > 19
+            && !memcmp (&rdm.sym[rdm.sym_len - 19], "17h", 3)))
+        return 0;
+
+      do
+        {
+          ident = parse_ident (&rdm);
+          if (rdm.errored || !ident.ascii)
+            return 0;
+        }
+      while (rdm.next < rdm.sym_len);
+
+      /* The last path segment should be the hash. */
+      if (!is_legacy_prefixed_hash (ident))
+        return 0;
+
+      /* Reset the state for a second pass, to print the symbol. */
+      rdm.next = 0;
+      if (!rdm.verbose && rdm.sym_len > 19)
+        {
+          /* Hide the last segment, containing the hash, if not verbose. */
+          rdm.sym_len -= 19;
+        }
+
+      do
+        {
+          if (rdm.next > 0)
+            print_str (&rdm, "::", 2);
+
+          ident = parse_ident (&rdm);
+          print_ident (&rdm, ident);
+        }
+      while (rdm.next < rdm.sym_len);
+    }
+  else
+    {
+      demangle_path (&rdm, 1);
+
+      /* Skip instantiating crate. */
+      if (!rdm.errored && rdm.next < rdm.sym_len)
+        {
+          rdm.skipping_printing = 1;
+          demangle_path (&rdm, 0);
+        }
+
+      /* It's an error to not reach the end. */
+      rdm.errored |= rdm.next != rdm.sym_len;
+    }
+
+  return !rdm.errored;
+}
+
+/* Growable string buffers. */
+struct str_buf
+{
+  char *ptr;
+  size_t len;
+  size_t cap;
+  int errored;
+};
+
+static void
+str_buf_reserve (struct str_buf *buf, size_t extra)
+{
+  size_t available, min_new_cap, new_cap;
+  char *new_ptr;
+
+  /* Allocation failed before. */
+  if (buf->errored)
+    return;
+
+  available = buf->cap - buf->len;
+
+  if (extra <= available)
+    return;
+
+  min_new_cap = buf->cap + (extra - available);
+
+  /* Check for overflows. */
+  if (min_new_cap < buf->cap)
+    {
+      buf->errored = 1;
+      return;
+    }
+
+  new_cap = buf->cap;
+
+  if (new_cap == 0)
+    new_cap = 4;
+
+  /* Double capacity until sufficiently large. */
+  while (new_cap < min_new_cap)
+    {
+      new_cap *= 2;
+
+      /* Check for overflows. */
+      if (new_cap < buf->cap)
+        {
+          buf->errored = 1;
+          return;
+        }
+    }
+
+  new_ptr = (char *)realloc (buf->ptr, new_cap);
+  if (new_ptr == NULL)
+    {
+      free (buf->ptr);
+      buf->ptr = NULL;
+      buf->len = 0;
+      buf->cap = 0;
+      buf->errored = 1;
+    }
+  else
+    {
+      buf->ptr = new_ptr;
+      buf->cap = new_cap;
+    }
+}
+
+static void
+str_buf_append (struct str_buf *buf, const char *data, size_t len)
+{
+  str_buf_reserve (buf, len);
+  if (buf->errored)
+    return;
+
+  memcpy (buf->ptr + buf->len, data, len);
+  buf->len += len;
+}
+
+static void
+str_buf_demangle_callback (const char *data, size_t len, void *opaque)
+{
+  str_buf_append ((struct str_buf *)opaque, data, len);
+}
+
+char *
+rust_demangle (const char *mangled, int options)
+{
+  struct str_buf out;
+  int success;
+
+  out.ptr = NULL;
+  out.len = 0;
+  out.cap = 0;
+  out.errored = 0;
+
+  success = rust_demangle_callback (mangled, options,
+                                    str_buf_demangle_callback, &out);
+
+  if (!success)
+    {
+      free (out.ptr);
+      return NULL;
+    }
+
+  str_buf_append (&out, "\0", 1);
+  return out.ptr;
+}
+
+void
+rust_demangle_replace (char *mangled)
+{
+  struct str_buf out;
+  int success;
+
+  out.ptr = NULL;
+  out.len = 0;
+  out.cap = 0;
+  out.errored = 0;
+
+  success = rust_demangle_callback(mangled, 0, str_buf_demangle_callback, &out);
+
+  if (!success) {
+    free (out.ptr);
+    return;
+  }
+
+  str_buf_append (&out, "\0", 1);
+
+  size_t len = strlen(mangled);
+  if (len > out.len) {
+    memcpy(mangled, out.ptr, out.len);
+    free(out.ptr);
+  }
+}
diff --git a/hw/display/Kconfig b/hw/display/Kconfig
index 1e95ab28ef405..20ae0db824d4c 100644
--- a/hw/display/Kconfig
+++ b/hw/display/Kconfig
@@ -37,6 +37,9 @@ config SSD0303
 config SSD0323
     bool
 
+config ST7735
+    bool
+
 config VGA_PCI
     bool
     default y if PCI_DEVICES
diff --git a/hw/display/meson.build b/hw/display/meson.build
index 90e6c041bdbc1..60bfa5698570e 100644
--- a/hw/display/meson.build
+++ b/hw/display/meson.build
@@ -14,6 +14,7 @@ system_ss.add(when: 'CONFIG_PL110', if_true: files('pl110.c'))
 system_ss.add(when: 'CONFIG_SII9022', if_true: files('sii9022.c'))
 system_ss.add(when: 'CONFIG_SSD0303', if_true: files('ssd0303.c'))
 system_ss.add(when: 'CONFIG_SSD0323', if_true: files('ssd0323.c'))
+system_ss.add(when: 'CONFIG_ST7735', if_true: files('st7735.c'))
 system_ss.add(when: 'CONFIG_XEN_BUS', if_true: files('xenfb.c'))
 
 system_ss.add(when: 'CONFIG_VGA_PCI', if_true: files('vga-pci.c'))
diff --git a/hw/display/st7735.c b/hw/display/st7735.c
new file mode 100644
index 0000000000000..5c8b0a6edbc05
--- /dev/null
+++ b/hw/display/st7735.c
@@ -0,0 +1,622 @@
+/*
+ * QEMU Sitronix ST7735 controller device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: only a small subset of the ST7735 are supported.
+ *       - inversion/rotation/... are ignored
+ *       - gamma settings are ignored
+ *       - read back functions are not supported
+ *       - ...
+ *       Moreover, only host consoles with 24bpp/32bpp are supported.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "hw/display/st7735.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+#include "ui/console.h"
+
+/* clang-format off */
+REG8(NOP, 0x00u)
+REG8(SWRESET, 0x01u)
+REG8(RDDID, 0x04u)
+REG8(RDDST, 0x09u)
+REG8(RDDPM, 0x0au)
+REG8(RDDMADCTL, 0x0bu)
+REG8(RDDCOLMOD, 0x0cu)
+REG8(RDDIM, 0x0du)
+REG8(RDDSM, 0x0eu)
+REG8(SLPIN, 0x10u)
+REG8(SLPOUT, 0x11u)
+REG8(PTLON, 0x12u)
+REG8(NORON, 0x13u)
+REG8(INVOFF, 0x20u)
+REG8(INVON, 0x21u)
+REG8(GAMSET, 0x26u)
+REG8(DISPOFF, 0x28u)
+REG8(DISPON, 0x29u)
+REG8(CASET, 0x2au)
+REG8(RASET, 0x2bu)
+REG8(RAMWR, 0x2cu)
+REG8(RAMRD, 0x2eu)
+REG8(PTLAR, 0x30u)
+REG8(TEOFF, 0x34u)
+REG8(TEON, 0x35u)
+REG8(MADCTL, 0x36u)
+    FIELD(MADCTL, MH, 2u, 1u)
+    FIELD(MADCTL, RGB, 2u, 1u)
+    FIELD(MADCTL, ML, 4u, 1u)
+    FIELD(MADCTL, MV, 5u, 1u)
+    FIELD(MADCTL, MX, 6u, 1u)
+    FIELD(MADCTL, MY, 7u, 1u)
+REG8(IDMOFF, 0x38u)
+REG8(IDMON, 0x39u)
+REG8(COLMOD, 0x3au)
+REG8(FRMCTR1, 0xb1u)
+REG8(FRMCTR2, 0xb2u)
+REG8(FRMCTR3, 0xb3u)
+REG8(INVCTR , 0xb4u)
+    FIELD(INVCTR, NLC, 0u, 1u)
+    FIELD(INVCTR, NLB, 1u, 1u)
+    FIELD(INVCTR, NLA, 2u, 1u)
+REG8(DISSET5, 0xb6u)
+REG8(PWCTR1, 0xc0u)
+REG8(PWCTR2, 0xc1u)
+REG8(PWCTR3, 0xc2u)
+REG8(PWCTR4, 0xc3u)
+REG8(PWCTR5, 0xc4u)
+REG8(VMCTR1, 0xc5u)
+REG8(VMOFCTR, 0xc7u)
+REG8(WRID2, 0xd1u)
+REG8(NVFCTR1, 0xd9u)
+REG8(NVFCTR2, 0xdeu)
+REG8(NVFCTR3, 0xdfu)
+REG8(RDID1, 0xdau)
+REG8(RDID2, 0xdbu)
+REG8(RDID3, 0xdcu)
+REG8(GMCTRP1, 0xe0u)
+REG8(GMCTRN1, 0xe1u)
+REG8(EXTCTRL, 0xf0u)
+REG8(VCOM4L, 0xffu)
+REG8(PWCTR6, 0xfcu)
+/* clang-format on */
+
+#define ST7735_DEFAULT_WIDTH  162u
+#define ST7735_DEFAULT_HEIGHT 132u
+
+#define ST7735_BUFFER_LEN 16u /* max SSI payload (except. gfx data) */
+
+#define ST7735_FB_PIXEL       uint32_t /* 32 bpp (24 bpp real)*/
+#define ST7735_FB_BPP         sizeof(ST7735_FB_PIXEL)
+#define ST7735_FB_PIXELS(_s_) ((_s_)->width * (_s_)->height)
+
+enum St7735SsiState {
+    STATE_IDLE,
+    STATE_COLLECTING_DATA,
+    STATE_WRITING_MEMORY,
+};
+
+typedef enum St7735PixelMode {
+    PX_INV = 0u, /* invalid mode */
+    PX_444 = 0x3u, /* 12-bit pixel */
+    PX_565 = 0x5u, /* 16-bit pixel */
+    PX_666 = 0x6u, /* 18-bit pixel */
+} St7735PixelMode;
+
+struct St7735State {
+    SSIPeripheral ssidev;
+    QemuConsole *con;
+
+    uint8_t state; /* SM state */
+    uint8_t command; /* command in progress */
+    uint32_t length; /* payload length for the current command */
+    uint32_t pos; /* count of received payload bytes */
+    uint8_t buffer[ST7735_BUFFER_LEN];
+    bool dc; /* false: handling command, true: handling data/payload */
+    bool nreset; /* reset is active low */
+
+    bool redraw;
+    ST7735_FB_PIXEL *fb; /* framebuffer (may be NULL) */
+    uint8_t col; /* current column in FB */
+    uint8_t row; /* current row in FB */
+
+    uint16_t width;
+    uint16_t height;
+
+    struct {
+        St7735PixelMode pixmode;
+        uint8_t madctl;
+        uint8_t invctr;
+        uint16_t xs;
+        uint16_t xe;
+        uint16_t ys;
+        uint16_t ye;
+    } disp;
+};
+
+static void st7735_sw_reset(St7735State *s)
+{
+    trace_st7735_reset("");
+
+    s->command = R_NOP;
+    s->pos = 0;
+    s->length = 0;
+    s->col = 0;
+    s->row = 0;
+}
+
+static void st7735_reset(DeviceState *dev)
+{
+    St7735State *s = ST7735(dev);
+
+    trace_st7735_reset("hw");
+
+    memset(&s->disp, 0, sizeof(s->disp));
+
+    st7735_sw_reset(s);
+
+    /* note: FB is not cleared even on HW reset as per the datasheet. */
+}
+
+static void st7735_sleep(St7735State *s, bool on)
+{
+    trace_st7735_set("sleep", on);
+}
+
+static void st7735_partial_mode(St7735State *s, bool on)
+{
+    trace_st7735_set("partial mode", on);
+}
+
+static void st7735_invert(St7735State *s, bool on)
+{
+    trace_st7735_set("invert", on);
+}
+
+static void st7735_idle(St7735State *s, bool on)
+{
+    trace_st7735_set("idle", on);
+}
+
+static void st7735_display(St7735State *s, bool on)
+{
+    trace_st7735_set("display", on);
+}
+
+static void st7735_gpio_event(void *opaque, int irq, int level)
+{
+    St7735State *s = opaque;
+    bool value = (bool)level;
+
+
+    switch (irq) {
+    case ST7735_IO_RESET:
+        trace_st7735_gpio("reset", value);
+        if (!value && s->nreset) {
+            st7735_reset(DEVICE(s));
+        }
+        s->nreset = value;
+        break;
+    case ST7735_IO_D_C:
+        trace_st7735_gpio("d/c", value);
+        s->dc = value;
+        break;
+    default:
+        break;
+    }
+}
+
+static void st7735_decode_command(St7735State *s, uint8_t cmd)
+{
+    s->pos = 0;
+
+    s->command = cmd;
+
+    switch (cmd) {
+    case R_NOP:
+        break;
+    case R_SWRESET:
+        st7735_sw_reset(s);
+        break;
+    case R_SLPIN:
+    case R_SLPOUT:
+        st7735_sleep(s, !(cmd - R_SLPIN));
+        break;
+    case R_PTLON:
+    case R_NORON:
+        st7735_partial_mode(s, !(cmd - R_PTLON));
+        break;
+    case R_INVOFF:
+    case R_INVON:
+        st7735_invert(s, (bool)(cmd - R_INVOFF));
+        break;
+    case R_DISPOFF:
+    case R_DISPON:
+        st7735_display(s, (bool)(cmd - R_DISPOFF));
+        break;
+    case R_CASET:
+    case R_RASET:
+        s->length = 4u;
+        break;
+    case R_RAMWR:
+        s->state = STATE_WRITING_MEMORY;
+        s->col = s->disp.xs;
+        s->row = s->disp.ys;
+        break;
+    case R_MADCTL:
+        s->length = 1u;
+        break;
+    case R_IDMOFF:
+    case R_IDMON:
+        st7735_idle(s, !(cmd - R_IDMOFF));
+        break;
+    case R_COLMOD:
+        s->length = 1u;
+        break;
+    case R_FRMCTR1:
+    case R_FRMCTR2:
+        s->length = 3u;
+        break;
+    case R_FRMCTR3:
+        s->length = 6u;
+        break;
+    case R_DISSET5:
+        s->length = 2u;
+        break;
+    case R_INVCTR:
+        s->length = 1u;
+        break;
+    case R_PWCTR1:
+    case R_PWCTR3:
+    case R_PWCTR4:
+    case R_PWCTR5:
+    case R_PWCTR6:
+        s->length = 2u;
+        break;
+    case R_PWCTR2:
+        s->length = 1u;
+        break;
+    case R_VMCTR1:
+        s->length = 2u;
+        break;
+    case R_GMCTRP1:
+    case R_GMCTRN1:
+        s->length = 16u;
+        break;
+    case R_GAMSET:
+    case R_RAMRD:
+    case R_PTLAR:
+    case R_TEOFF:
+    case R_TEON:
+    case R_RDDID:
+    case R_RDDST:
+    case R_RDDPM:
+    case R_RDDMADCTL:
+    case R_RDDCOLMOD:
+    case R_RDDIM:
+    case R_RDDSM:
+    case R_VMOFCTR:
+    case R_WRID2:
+    case R_NVFCTR1:
+    case R_NVFCTR2:
+    case R_NVFCTR3:
+    case R_RDID1:
+    case R_RDID2:
+    case R_RDID3:
+    case R_EXTCTRL:
+    case R_VCOM4L:
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: Command not supported 0x%02x\n", __func__,
+                      cmd);
+        break;
+    }
+}
+
+static void st7735_execute_command(St7735State *s)
+{
+    switch (s->command) {
+    case R_COLMOD:
+        switch (s->buffer[0]) {
+        case PX_444:
+        case PX_565:
+        case PX_666:
+            s->disp.pixmode = (St7735PixelMode)s->buffer[0];
+            break;
+        default:
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown pixel mode %u\n",
+                          __func__, s->buffer[0]);
+            break;
+        }
+        break;
+    case R_MADCTL:
+        s->disp.madctl = s->buffer[0];
+        break;
+    case R_INVCTR:
+        s->disp.invctr = s->buffer[0];
+        break;
+    case R_CASET: /* See .10 Memory Data Write/ Read Direction */
+        s->disp.xs = MIN(lduw_be_p(&s->buffer[0u]), s->width);
+        s->disp.xe = MIN(lduw_be_p(&s->buffer[2u]), s->width);
+        s->row = s->disp.ys;
+        trace_st7735_cursor("X", s->disp.xs, s->disp.xe);
+        break;
+    case R_RASET:
+        s->disp.ys = MIN(lduw_be_p(&s->buffer[0u]), s->height);
+        s->disp.ye = MIN(lduw_be_p(&s->buffer[2u]), s->height);
+        s->col = s->disp.xs;
+        trace_st7735_cursor("Y", s->disp.xs, s->disp.xe);
+        break;
+    case R_FRMCTR1: /* don't care */
+    case R_FRMCTR2:
+    case R_FRMCTR3:
+    case R_DISSET5:
+    case R_PWCTR1:
+    case R_PWCTR2:
+    case R_PWCTR3:
+    case R_PWCTR4:
+    case R_PWCTR5:
+    case R_PWCTR6:
+    case R_VMCTR1:
+    case R_GMCTRP1: /* gamma control */
+    case R_GMCTRN1:
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: Command not supported 0x%02x\n", __func__,
+                      s->command);
+        break;
+    }
+}
+
+static inline uint32_t st7735_make_pixel(uint8_t r, uint8_t g, uint8_t b)
+{
+    /* PIXMAN_x8r8g8b8 encoding */
+    return (((uint32_t)r) << 16u) | (((uint32_t)g) << 8u) | ((uint32_t)b << 0u);
+}
+
+static ST7735_FB_PIXEL *st7735_get_pixel(St7735State *s)
+{
+    if (s->col > s->disp.xe) {
+        s->col = s->disp.xs;
+        s->row++;
+    }
+    if (s->row > s->disp.ye) {
+        s->row = s->disp.ys;
+    }
+
+    return &s->fb[s->col + s->row * s->width];
+}
+
+static void st7735_write_memory(St7735State *s, uint8_t byte)
+{
+    s->buffer[s->pos++] = byte;
+    ST7735_FB_PIXEL *pixel;
+    uint8_t r, g, b;
+    switch (s->disp.pixmode) {
+    case PX_565:
+        if (s->pos == 2u) {
+            s->pos = 0u;
+            pixel = st7735_get_pixel(s);
+            uint16_t px16 = lduw_be_p(&s->buffer[0u]);
+            r = (uint8_t)((px16 >> 8u) & 0xf8u);
+            g = (uint8_t)((px16 >> 3u) & 0xfcu);
+            b = (uint8_t)((px16 << 3u) & 0xf8u);
+            pixel[0u] = st7735_make_pixel(r, g, b);
+            s->col += 1u;
+            break;
+        }
+        return;
+    case PX_666:
+        if (s->pos == 3u) {
+            s->pos = 0u;
+            pixel = st7735_get_pixel(s);
+            r = (uint8_t)(s->buffer[0u] & 0xfcu);
+            g = (uint8_t)(s->buffer[1u] & 0xfcu);
+            b = (uint8_t)(s->buffer[2u] & 0xfcu);
+            pixel[0u] = st7735_make_pixel(r, g, b);
+            s->col += 1u;
+            break;
+        };
+        return;
+    case PX_444:
+        if (s->pos == 3u) {
+            s->pos = 0u;
+            pixel = st7735_get_pixel(s);
+            r = (uint8_t)(s->buffer[0u] & 0xf0u);
+            g = (uint8_t)(s->buffer[0u] << 4u);
+            b = (uint8_t)(s->buffer[1u] & 0xf0u);
+            pixel[0u] = st7735_make_pixel(r, g, b);
+            r = (uint8_t)(s->buffer[1u] << 4u);
+            g = (uint8_t)(s->buffer[2u] & 0xf0u);
+            b = (uint8_t)(s->buffer[2u] << 4u);
+            pixel[1u] = st7735_make_pixel(r, g, b);
+            s->col += 2u;
+            break;
+        }
+        return;
+    default:
+        /* be sure to reset the pixel buffer if not handled */
+        s->pos = 0;
+        return;
+    }
+}
+
+static uint32_t st7735_transfer(SSIPeripheral *dev, uint32_t rx)
+{
+    St7735State *s = ST7735(dev);
+
+    if (!s->nreset) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Ignoring SSI in HW reset\n",
+                      __func__);
+        return 0u;
+    }
+
+    switch (s->state) {
+    case STATE_WRITING_MEMORY:
+        if (s->dc && s->fb) {
+            st7735_write_memory(s, rx);
+            return 0;
+        }
+        break;
+    case STATE_IDLE:
+        if (!s->dc) {
+            s->length = 0;
+            st7735_decode_command(s, (uint8_t)rx);
+            if (s->length) {
+                s->state = STATE_COLLECTING_DATA;
+            }
+            return 0;
+        }
+        break;
+    case STATE_COLLECTING_DATA:
+        if (s->dc) {
+            if (s->pos < ST7735_BUFFER_LEN) {
+                s->buffer[s->pos++] = (uint8_t)rx;
+                if (s->pos == s->length) {
+                    st7735_execute_command(s);
+                }
+            } else {
+                s->pos++;
+            }
+            return 0;
+        }
+        break;
+    }
+
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: Ignoring SSI data, D/C: %u, state %d\n",
+                  __func__, s->dc, s->state);
+
+    return 0u;
+}
+
+static int st7735_set_cs(SSIPeripheral *dev, bool select)
+{
+    St7735State *s = ST7735(dev);
+
+    if (select) {
+        if (s->state == STATE_WRITING_MEMORY) {
+            s->redraw = true;
+        }
+        s->pos = 0;
+        s->length = 0;
+        s->state = STATE_IDLE;
+    }
+
+    return 0;
+}
+
+static void st7735_invalidate_display(void *opaque)
+{
+    St7735State *s = opaque;
+
+    s->redraw = true;
+}
+
+static void st7735_update_display(void *opaque)
+{
+    St7735State *s = opaque;
+
+    if (!s->redraw || !s->fb) {
+        return;
+    }
+
+    DisplaySurface *surface = qemu_console_surface(s->con);
+    void *dest = surface_data(surface);
+    memcpy(dest, s->fb, ST7735_FB_PIXELS(s) * ST7735_FB_BPP);
+    dpy_gfx_update(s->con, 0, 0, s->width, s->height);
+    s->redraw = false;
+}
+
+static const Property st7735_properties[] = {
+    DEFINE_PROP_UINT16("width", St7735State, width, ST7735_DEFAULT_WIDTH),
+    DEFINE_PROP_UINT16("height", St7735State, height, ST7735_DEFAULT_HEIGHT),
+};
+
+static const GraphicHwOps st7735_ui_ops = {
+    .invalidate = &st7735_invalidate_display,
+    .gfx_update = &st7735_update_display,
+};
+
+static void st7735_realize(SSIPeripheral *dev, Error **errp)
+{
+    St7735State *s = ST7735(dev);
+
+    s->con = graphic_console_init(DEVICE(dev), 0, &st7735_ui_ops, s);
+    qemu_console_resize(s->con, s->width, s->height);
+
+    qdev_init_gpio_in_named(DEVICE(dev), &st7735_gpio_event, ST7735_IO_LINES,
+                            ST7735_IO_COUNT);
+
+    DisplaySurface *surface = qemu_console_surface(s->con);
+    int bpp = surface_bits_per_pixel(surface);
+    if (bpp >= 24) {
+        s->fb = g_new0(ST7735_FB_PIXEL, ST7735_FB_PIXELS(s));
+    } else {
+        qemu_log_mask(LOG_UNIMP, "%s: No support for display w/ %d bpp\n",
+                      __func__, bpp);
+        s->fb = NULL;
+    }
+}
+
+static void st7735_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
+
+    device_class_set_legacy_reset(dc, &st7735_reset);
+    k->realize = &st7735_realize;
+    k->transfer = &st7735_transfer;
+    k->set_cs = &st7735_set_cs;
+    k->cs_polarity = SSI_CS_LOW;
+
+    device_class_set_props(dc, st7735_properties);
+    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
+}
+
+static const TypeInfo st7735_info = {
+    .name = TYPE_ST7735,
+    .parent = TYPE_SSI_PERIPHERAL,
+    .instance_size = sizeof(St7735State),
+    .class_init = &st7735_class_init,
+};
+
+static void st7735_register_types(void)
+{
+    type_register_static(&st7735_info);
+}
+
+type_init(st7735_register_types);
+
+void st7735_configure(DeviceState *dev, hwaddr addr)
+{
+    SysBusDevice *busdev = SYS_BUS_DEVICE(dev);
+
+    sysbus_realize_and_unref(busdev, &error_fatal);
+    sysbus_mmio_map(busdev, 0, addr);
+}
diff --git a/hw/display/trace-events b/hw/display/trace-events
index e323a82cff24b..992e90360229f 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -226,3 +226,8 @@ apple_gfx_iosfc_unmap_memory(void *a, void *b, void *c, void *d, void *e, void *
 apple_gfx_iosfc_unmap_memory_region(void* mem, void *region) "unmapping @ %p from memory region %p"
 apple_gfx_iosfc_raise_irq(uint32_t vector) "vector=0x%x"
 
+# st7735
+st7735_reset(const char *msg) "%s"
+st7735_set(const char *msg, bool enable) "%s: %u"
+st7735_gpio(const char *line, bool enable) "%s: %u"
+st7735_cursor(const char *axis, uint16_t start, uint16_t end) "%s: %hu..%hu"
diff --git a/hw/ibexdemo/Kconfig b/hw/ibexdemo/Kconfig
new file mode 100644
index 0000000000000..12583294118c1
--- /dev/null
+++ b/hw/ibexdemo/Kconfig
@@ -0,0 +1,17 @@
+# Ibex Demo System
+
+config IBEXDEMO_GPIO
+    bool
+
+config IBEXDEMO_SIMCTRL
+    bool
+
+config IBEXDEMO_SPI
+    bool
+    select SSI
+
+config IBEXDEMO_TIMER
+    bool
+
+config IBEXDEMO_UART
+    bool
diff --git a/hw/ibexdemo/ibexdemo_gpio.c b/hw/ibexdemo/ibexdemo_gpio.c
new file mode 100644
index 0000000000000..0978df872f38c
--- /dev/null
+++ b/hw/ibexdemo/ibexdemo_gpio.c
@@ -0,0 +1,221 @@
+/*
+ * QEMU lowRISC Ibex Demo GPIO device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "hw/ibexdemo/ibexdemo_gpio.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(OUT, 0x00u)
+REG32(IN, 0x04u)
+REG32(IN_DBNC, 0x08u)
+REG32(OUT_SHIFT, 0x0cu)
+/* clang-format on */
+
+struct IbexDemoGPIOState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+
+    uint32_t in_count;
+    uint32_t out_count;
+
+    uint32_t input;
+    uint32_t output;
+    uint32_t output_level;
+
+    qemu_irq *gpo;
+};
+
+static void ibexdemo_gpio_update_output(IbexDemoGPIOState *s)
+{
+    trace_ibexdemo_gpio_output(s->output);
+
+    uint32_t output = s->output;
+    uint32_t change = output ^ s->output_level;
+
+    for (unsigned ix = 0; ix < s->out_count; ix++) {
+        if (change & 0b1) {
+            qemu_set_irq(s->gpo[ix], (int)(output & 0b1));
+        }
+        output >>= 1u;
+        change >>= 1u;
+    }
+
+    s->output_level = s->output;
+}
+
+static void ibexdemo_gpio_reset(DeviceState *dev)
+{
+    IbexDemoGPIOState *s = IBEXDEMO_GPIO(dev);
+
+    s->input = 0;
+    s->output = 0;
+    s->output_level = UINT32_MAX; /* be sure to update all output on reset */
+
+    ibexdemo_gpio_update_output(s);
+}
+
+static uint64_t ibexdemo_gpio_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    IbexDemoGPIOState *s = opaque;
+    uint32_t val32;
+
+    switch (addr >> 2u) {
+    case R_OUT:
+        val32 = s->output;
+        break;
+    case R_IN:
+    case R_IN_DBNC:
+        val32 = s->input;
+        break;
+    case R_OUT_SHIFT:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: not supported\n", __func__);
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        val32 = 0;
+        break;
+    }
+
+    return (uint64_t)val32;
+}
+
+static void ibexdemo_gpio_write(void *opaque, hwaddr addr, uint64_t val64,
+                                unsigned int size)
+{
+    IbexDemoGPIOState *s = opaque;
+
+    switch (addr >> 2u) {
+    case R_OUT:
+        s->output = val64 & ((1u << s->out_count) - 1u);
+        ibexdemo_gpio_update_output(s);
+        break;
+    case R_IN:
+    case R_IN_DBNC:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O registers\n", __func__);
+        break;
+    case R_OUT_SHIFT:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: not supported\n", __func__);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+}
+
+static void ibexdemo_gpio_input_event(void *opaque, int irq, int level)
+{
+    IbexDemoGPIOState *s = opaque;
+
+    if (irq < s->in_count) {
+        if (level) {
+            s->input |= 1u << irq;
+        } else {
+            s->input &= ~(1u << irq);
+        }
+    }
+
+    trace_ibexdemo_gpio_input(s->input);
+}
+
+static const MemoryRegionOps ibexdemo_gpio_ops = {
+    .read = &ibexdemo_gpio_read,
+    .write = &ibexdemo_gpio_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const Property ibexdemo_gpio_properties[] = {
+    DEFINE_PROP_UINT32("in_count", IbexDemoGPIOState, in_count,
+                       IBEXDEMO_GPIO_IN_MAX),
+    DEFINE_PROP_UINT32("out_count", IbexDemoGPIOState, out_count,
+                       IBEXDEMO_GPIO_IN_MAX),
+};
+
+static void ibexdemo_gpio_realize(DeviceState *dev, Error **errp)
+{
+    IbexDemoGPIOState *s = IBEXDEMO_GPIO(dev);
+
+    if (s->in_count > IBEXDEMO_GPIO_IN_MAX) {
+        s->in_count = IBEXDEMO_GPIO_IN_MAX;
+    }
+    if (s->out_count > IBEXDEMO_GPIO_OUT_MAX) {
+        s->out_count = IBEXDEMO_GPIO_OUT_MAX;
+    }
+
+    qdev_init_gpio_in_named(dev, &ibexdemo_gpio_input_event,
+                            IBEXDEMO_GPIO_IN_LINES, s->in_count);
+}
+
+static void ibexdemo_gpio_init(Object *obj)
+{
+    IbexDemoGPIOState *s = IBEXDEMO_GPIO(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ibexdemo_gpio_ops, s,
+                          TYPE_IBEXDEMO_GPIO, 0x1000u);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    s->gpo = g_new0(qemu_irq, IBEXDEMO_GPIO_OUT_MAX);
+
+    qdev_init_gpio_out_named(DEVICE(obj), s->gpo, IBEXDEMO_GPIO_OUT_LINES,
+                             IBEXDEMO_GPIO_OUT_MAX);
+}
+
+static void ibexdemo_gpio_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    device_class_set_legacy_reset(dc, &ibexdemo_gpio_reset);
+    dc->realize = &ibexdemo_gpio_realize;
+    device_class_set_props(dc, ibexdemo_gpio_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static const TypeInfo ibexdemo_gpio_info = {
+    .name = TYPE_IBEXDEMO_GPIO,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IbexDemoGPIOState),
+    .instance_init = &ibexdemo_gpio_init,
+    .class_init = &ibexdemo_gpio_class_init,
+};
+
+static void ibexdemo_gpio_register_types(void)
+{
+    type_register_static(&ibexdemo_gpio_info);
+}
+
+type_init(ibexdemo_gpio_register_types);
diff --git a/hw/ibexdemo/ibexdemo_simctrl.c b/hw/ibexdemo/ibexdemo_simctrl.c
new file mode 100644
index 0000000000000..98e753ac2730f
--- /dev/null
+++ b/hw/ibexdemo/ibexdemo_simctrl.c
@@ -0,0 +1,133 @@
+/*
+ * QEMU lowRISC Ibex Demo Sim Control device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "hw/ibexdemo/ibexdemo_simctrl.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/sysbus.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(OUT, 0x00u)
+REG32(CTRL, 0x08u)
+/* clang-format on */
+
+struct IbexDemoSimCtrlState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+};
+
+static uint64_t ibexdemo_simctrl_read(void *opaque, hwaddr addr,
+                                      unsigned int size)
+{
+    uint32_t val32;
+
+    switch (addr >> 2u) {
+    case R_OUT:
+    case R_CTRL:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: wdata is write only\n", __func__);
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        val32 = 0;
+        break;
+    }
+
+    return (uint64_t)val32;
+}
+
+static void ibexdemo_simctrl_write(void *opaque, hwaddr addr, uint64_t val64,
+                                   unsigned int size)
+{
+    switch (addr >> 2u) {
+    case R_OUT:
+        putc((int)(uint8_t)val64, stderr);
+        break;
+    case R_CTRL:
+        if (val64 & 1u) {
+            /* as a QEMU extension, bits [7:1] are used as exit code */
+            qemu_system_shutdown_request_with_code(
+                SHUTDOWN_CAUSE_GUEST_SHUTDOWN, (val64 >> 1u) & 0x7fu);
+        }
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+}
+
+static const MemoryRegionOps ibexdemo_simctrl_ops = {
+    .read = &ibexdemo_simctrl_read,
+    .write = &ibexdemo_simctrl_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 1,
+    .impl.max_access_size = 4,
+};
+
+static void ibexdemo_simctrl_init(Object *obj)
+{
+    IbexDemoSimCtrlState *s = IBEXDEMO_SIMCTRL(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ibexdemo_simctrl_ops, s,
+                          TYPE_IBEXDEMO_SIMCTRL, 0x400u);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void ibexdemo_simctrl_realize(DeviceState *dev, Error **errp)
+{
+    /* empty */
+}
+
+static void ibexdemo_simctrl_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = &ibexdemo_simctrl_realize;
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static const TypeInfo ibexdemo_simctrl_info = {
+    .name = TYPE_IBEXDEMO_SIMCTRL,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IbexDemoSimCtrlState),
+    .instance_init = &ibexdemo_simctrl_init,
+    .class_init = &ibexdemo_simctrl_class_init,
+};
+
+static void ibexdemo_simctrl_register_types(void)
+{
+    type_register_static(&ibexdemo_simctrl_info);
+}
+
+type_init(ibexdemo_simctrl_register_types);
diff --git a/hw/ibexdemo/ibexdemo_spi.c b/hw/ibexdemo/ibexdemo_spi.c
new file mode 100644
index 0000000000000..c26816af0f26c
--- /dev/null
+++ b/hw/ibexdemo/ibexdemo_spi.c
@@ -0,0 +1,145 @@
+/*
+ * QEMU lowRISC Ibex Demo SPI host device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "hw/ibexdemo/ibexdemo_spi.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(TX, 0x00u)
+    FIELD(TX, DATA, 0u, 8u)
+REG32(STATUS, 0x04u)
+    FIELD(STATUS, TX_FULL, 0u, 1u)
+    FIELD(STATUS, TX_EMPTY, 1u, 1u)
+/* clang-format on */
+
+struct IbexDemoSPIState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    SSIBus *ssi;
+};
+
+static void ibexdemo_spi_reset(DeviceState *dev)
+{
+    /* empty */
+}
+
+static uint64_t ibexdemo_spi_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    uint32_t val32;
+
+    switch (addr >> 2u) {
+    case R_TX:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: wdata is write only\n", __func__);
+        val32 = 0;
+        break;
+    case R_STATUS:
+        val32 = FIELD_DP32(0, STATUS, TX_EMPTY, 1u);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        val32 = 0;
+        break;
+    }
+
+    return (uint64_t)val32;
+}
+
+static void ibexdemo_spi_write(void *opaque, hwaddr addr, uint64_t val64,
+                               unsigned int size)
+{
+    IbexDemoSPIState *s = opaque;
+
+    switch (addr >> 2u) {
+    case R_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: reg is read only\n", __func__);
+        break;
+    case R_TX:
+        trace_ibexdemo_spi_output((uint8_t)val64);
+        (void)ssi_transfer(s->ssi, (uint8_t)val64);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+}
+
+static const MemoryRegionOps ibexdemo_spi_ops = {
+    .read = &ibexdemo_spi_read,
+    .write = &ibexdemo_spi_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static void ibexdemo_spi_init(Object *obj)
+{
+    IbexDemoSPIState *s = IBEXDEMO_SPI(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ibexdemo_spi_ops, s,
+                          TYPE_IBEXDEMO_SPI, 0x400u);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    s->ssi = ssi_create_bus(DEVICE(obj), "spi0");
+}
+
+static void ibexdemo_spi_realize(DeviceState *dev, Error **errp)
+{
+    /* empty */
+}
+
+static void ibexdemo_spi_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    device_class_set_legacy_reset(dc, &ibexdemo_spi_reset);
+    dc->realize = &ibexdemo_spi_realize;
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static const TypeInfo ibexdemo_spi_info = {
+    .name = TYPE_IBEXDEMO_SPI,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IbexDemoSPIState),
+    .instance_init = &ibexdemo_spi_init,
+    .class_init = &ibexdemo_spi_class_init,
+};
+
+static void ibexdemo_spi_register_types(void)
+{
+    type_register_static(&ibexdemo_spi_info);
+}
+
+type_init(ibexdemo_spi_register_types);
diff --git a/hw/ibexdemo/ibexdemo_timer.c b/hw/ibexdemo/ibexdemo_timer.c
new file mode 100644
index 0000000000000..7cb1364746478
--- /dev/null
+++ b/hw/ibexdemo/ibexdemo_timer.c
@@ -0,0 +1,227 @@
+/*
+ * QEMU lowRISC Ibex Demo Timer device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ * based on ibex_timer.c from Western Digital Copyright (c) 2021
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "qapi/error.h"
+#include "hw/ibexdemo/ibexdemo_timer.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+
+
+REG32(MTIME, 0x00u)
+REG32(MTIMEH, 0x04u)
+REG32(MTIMECMP, 0x08u)
+REG32(MTIMECMPH, 0x0cu)
+
+struct IbexDemoTimerState {
+    SysBusDevice parent_obj;
+    QEMUTimer *timer;
+
+    MemoryRegion mmio;
+
+    uint64_t mtimecmp;
+    uint64_t timer_compare;
+    uint32_t timebase_freq;
+
+    IbexIRQ irq;
+};
+
+static uint64_t ibexdemo_timer_read_rtc(IbexDemoTimerState *s)
+{
+    return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), s->timebase_freq,
+                    NANOSECONDS_PER_SECOND);
+}
+
+static void ibexdemo_timer_update(IbexDemoTimerState *s)
+{
+    uint64_t now = ibexdemo_timer_read_rtc(s);
+
+    if (now >= s->mtimecmp) {
+        qemu_log_mask(CPU_LOG_EXEC,
+                      "[Timer IRQ] %08" PRIx64 " >= %08" PRIx64 "\n", now,
+                      s->mtimecmp);
+        ibex_irq_set(&s->irq, true);
+        return;
+    }
+
+    ibex_irq_set(&s->irq, false);
+
+    uint64_t next, diff;
+
+    diff = s->mtimecmp - now;
+    next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+           muldiv64(diff, NANOSECONDS_PER_SECOND, s->timebase_freq);
+
+    if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
+        timer_mod(s->timer, INT64_MAX);
+    } else {
+        timer_mod(s->timer, next);
+    }
+}
+
+static void ibexdemo_timer_cb(void *opaque)
+{
+    IbexDemoTimerState *s = opaque;
+
+    ibex_irq_set(&s->irq, true);
+}
+
+static void ibexdemo_timer_reset(DeviceState *dev)
+{
+    IbexDemoTimerState *s = IBEXDEMO_TIMER(dev);
+
+    timer_del(s->timer);
+    s->mtimecmp = 0u;
+    ibex_irq_set(&s->irq, false);
+
+    ibexdemo_timer_update(s);
+}
+
+static uint64_t ibexdemo_timer_read(void *opaque, hwaddr addr, unsigned size)
+{
+    IbexDemoTimerState *s = opaque;
+    uint32_t val32;
+
+    switch (addr >> 2u) {
+    case R_MTIME:
+        val32 = (uint32_t)ibexdemo_timer_read_rtc(s);
+        break;
+    case R_MTIMEH:
+        val32 = (uint32_t)(ibexdemo_timer_read_rtc(s) >> 32u);
+        break;
+    case R_MTIMECMP:
+        val32 = (uint32_t)s->mtimecmp;
+        break;
+    case R_MTIMECMPH:
+        val32 = (uint32_t)(s->mtimecmp >> 32u);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        val32 = 0;
+        break;
+    }
+
+    return (uint64_t)val32;
+}
+
+static void ibexdemo_timer_write(void *opaque, hwaddr addr, uint64_t val64,
+                                 unsigned size)
+{
+    IbexDemoTimerState *s = opaque;
+    uint64_t tmp;
+
+    switch (addr >> 2) {
+    case R_MTIME:
+    case R_MTIMEH:
+        /* todo: how to support write to mtime? */
+        qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported\n");
+        break;
+    case R_MTIMECMP:
+        tmp = s->mtimecmp >> 32u;
+        tmp <<= 32u;
+        s->mtimecmp = tmp | (uint32_t)val64;
+        ibexdemo_timer_update(s);
+        break;
+    case R_MTIMECMPH:
+        tmp = s->mtimecmp << 32u;
+        tmp >>= 32u;
+        val64 <<= 32u;
+        s->mtimecmp = val64 | tmp;
+        ibexdemo_timer_update(s);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+}
+
+static const MemoryRegionOps ibexdemo_timer_ops = {
+    .read = ibexdemo_timer_read,
+    .write = ibexdemo_timer_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const Property ibexdemo_timer_properties[] = {
+    DEFINE_PROP_UINT32("timebase-freq", IbexDemoTimerState, timebase_freq,
+                       50000000),
+};
+
+static void ibexdemo_timer_init(Object *obj)
+{
+    IbexDemoTimerState *s = IBEXDEMO_TIMER(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ibexdemo_timer_ops, s,
+                          TYPE_IBEXDEMO_TIMER, 0x1000u);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    ibex_sysbus_init_irq(obj, &s->irq);
+
+    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ibexdemo_timer_cb, s);
+
+    /*
+     * todo: need to check whether mtime CSR is supported. If so, see
+     * void riscv_cpu_set_rdtime_fn();
+     */
+}
+
+static void ibexdemo_timer_realize(DeviceState *dev, Error **errp)
+{
+    IbexDemoTimerState *s = IBEXDEMO_TIMER(dev);
+
+    qdev_init_gpio_out(dev, &s->irq.irq, 1);
+}
+
+static void ibexdemo_timer_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    device_class_set_legacy_reset(dc, ibexdemo_timer_reset);
+    dc->realize = ibexdemo_timer_realize;
+    device_class_set_props(dc, ibexdemo_timer_properties);
+}
+
+static const TypeInfo ibexdemo_timer_info = {
+    .name = TYPE_IBEXDEMO_TIMER,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IbexDemoTimerState),
+    .instance_init = ibexdemo_timer_init,
+    .class_init = ibexdemo_timer_class_init,
+};
+
+static void ibexdemo_timer_register_types(void)
+{
+    type_register_static(&ibexdemo_timer_info);
+}
+
+type_init(ibexdemo_timer_register_types);
diff --git a/hw/ibexdemo/ibexdemo_uart.c b/hw/ibexdemo/ibexdemo_uart.c
new file mode 100644
index 0000000000000..73552a0d54c88
--- /dev/null
+++ b/hw/ibexdemo/ibexdemo_uart.c
@@ -0,0 +1,295 @@
+/*
+ * QEMU lowRISC Ibex Demo UART device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/fifo8.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "chardev/char-fe.h"
+#include "hw/ibexdemo/ibexdemo_uart.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+
+/* clang-format off */
+REG32(RX, 0x00u)
+    FIELD(RX, DATA, 0u, 8u)
+REG32(TX, 0x04u)
+    FIELD(TX, DATA, 0u, 8u)
+REG32(STATUS, 0x08u)
+    FIELD(STATUS, RX_FIFO_EMPTY, 0u, 1u)
+    FIELD(STATUS, TX_FIFO_FULL, 1u, 1u)
+/* clang-format on */
+
+#define IBEXDEMO_UART_RX_FIFO_SIZE 128u
+#define IBEXDEMO_UART_TX_FIFO_SIZE 128u
+
+struct IbexDemoUARTState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ irq;
+
+    CharFrontend chr;
+    guint watch_tag;
+
+    Fifo8 rx_fifo;
+    Fifo8 tx_fifo;
+    bool irq_level;
+};
+
+static void ibexdemo_uart_update_irq(IbexDemoUARTState *s)
+{
+    bool irq_level = !fifo8_is_empty(&s->rx_fifo);
+    ibex_irq_set(&s->irq, irq_level);
+}
+
+static int ibexdemo_uart_can_receive(void *opaque)
+{
+    IbexDemoUARTState *s = opaque;
+
+    return (int)fifo8_num_free(&s->rx_fifo);
+}
+
+static void ibexdemo_uart_receive(void *opaque, const uint8_t *buf, int size)
+{
+    IbexDemoUARTState *s = opaque;
+
+    while (size && !fifo8_is_full(&s->rx_fifo)) {
+        fifo8_push(&s->rx_fifo, *buf++);
+        size--;
+    }
+
+    if (size) {
+        qemu_log_mask(LOG_GUEST_ERROR, "ibexdemo_uart: RX FIFO overflow");
+    }
+
+    ibexdemo_uart_update_irq(s);
+}
+
+static void ibexdemo_uart_xmit(IbexDemoUARTState *s)
+{
+    /* drain the fifo when there's no back-end */
+    if (!qemu_chr_fe_backend_connected(&s->chr)) {
+        fifo8_reset(&s->tx_fifo);
+        return;
+    }
+
+    const uint8_t *buf;
+    uint32_t size;
+    int ret;
+
+    buf = fifo8_peek_bufptr(&s->tx_fifo, fifo8_num_used(&s->tx_fifo), &size);
+    ret = qemu_chr_fe_write(&s->chr, buf, size);
+
+    if (ret > 0) {
+        fifo8_drop(&s->tx_fifo, ret);
+    }
+}
+
+static gboolean ibexdemo_uart_watch_cb(void *do_not_use, GIOCondition cond,
+                                       void *opaque)
+{
+    IbexDemoUARTState *s = opaque;
+
+    s->watch_tag = 0;
+    ibexdemo_uart_xmit(s);
+
+    return FALSE;
+}
+
+static void ibexdemo_uart_tx_write(IbexDemoUARTState *s, uint8_t val)
+{
+    if (!qemu_chr_fe_backend_connected(&s->chr)) {
+        return;
+    }
+
+    if (fifo8_is_full(&s->tx_fifo)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "ibexdemo_uart: TX FIFO overflow");
+        return;
+    }
+
+    fifo8_push(&s->tx_fifo, val);
+
+    ibexdemo_uart_xmit(s);
+}
+
+static void ibexdemo_uart_reset(DeviceState *dev)
+{
+    IbexDemoUARTState *s = IBEXDEMO_UART(dev);
+
+    fifo8_reset(&s->rx_fifo);
+    fifo8_reset(&s->tx_fifo);
+
+    ibexdemo_uart_update_irq(s);
+
+    qemu_chr_fe_accept_input(&s->chr);
+}
+
+static uint64_t ibexdemo_uart_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    IbexDemoUARTState *s = opaque;
+    uint32_t val32;
+    bool rx_full;
+
+    switch (addr >> 2u) {
+    case R_RX:
+        rx_full = fifo8_is_full(&s->rx_fifo);
+        if (!fifo8_is_empty(&s->rx_fifo)) {
+            val32 = fifo8_pop(&s->rx_fifo);
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "ibexdemo_uart: RX FIFO underflow");
+            val32 = 0;
+        }
+        if (rx_full) {
+            /*
+             * RX was full and was not accepting any new input; now that one
+             * byte has been popped out, get ready to receive more
+             */
+            qemu_chr_fe_accept_input(&s->chr);
+        }
+        ibexdemo_uart_update_irq(s);
+        break;
+    case R_TX:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: wdata is write only\n", __func__);
+        val32 = 0;
+        break;
+    case R_STATUS:
+        val32 = FIELD_DP32(0, STATUS, RX_FIFO_EMPTY,
+                           (uint32_t)fifo8_is_empty(&s->rx_fifo));
+        val32 = FIELD_DP32(val32, STATUS, TX_FIFO_FULL,
+                           (uint32_t)fifo8_is_full(&s->tx_fifo));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        val32 = 0;
+        break;
+    }
+
+    return (uint64_t)val32;
+}
+
+static void ibexdemo_uart_write(void *opaque, hwaddr addr, uint64_t val64,
+                                unsigned int size)
+{
+    IbexDemoUARTState *s = opaque;
+
+    switch (addr >> 2u) {
+    case R_RX:
+    case R_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: reg is read only\n", __func__);
+        break;
+    case R_TX:
+        ibexdemo_uart_tx_write(s, (uint8_t)val64);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+}
+
+static const MemoryRegionOps ibexdemo_uart_ops = {
+    .read = &ibexdemo_uart_read,
+    .write = &ibexdemo_uart_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const Property ibexdemo_uart_properties[] = {
+    DEFINE_PROP_CHR("chardev", IbexDemoUARTState, chr),
+};
+
+static int ibexdemo_uart_be_change(void *opaque)
+{
+    IbexDemoUARTState *s = opaque;
+
+    qemu_chr_fe_set_handlers(&s->chr, &ibexdemo_uart_can_receive,
+                             &ibexdemo_uart_receive, NULL,
+                             &ibexdemo_uart_be_change, s, NULL, true);
+
+    if (s->watch_tag > 0) {
+        g_source_remove(s->watch_tag);
+        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+                                             ibexdemo_uart_watch_cb, s);
+    }
+
+    return 0;
+}
+
+static void ibexdemo_uart_realize(DeviceState *dev, Error **errp)
+{
+    IbexDemoUARTState *s = IBEXDEMO_UART(dev);
+
+    fifo8_create(&s->tx_fifo, IBEXDEMO_UART_TX_FIFO_SIZE);
+
+    qemu_chr_fe_set_handlers(&s->chr, &ibexdemo_uart_can_receive,
+                             &ibexdemo_uart_receive, NULL,
+                             &ibexdemo_uart_be_change, s, NULL, true);
+}
+
+static void ibexdemo_uart_init(Object *obj)
+{
+    IbexDemoUARTState *s = IBEXDEMO_UART(obj);
+
+    ibex_sysbus_init_irq(obj, &s->irq);
+
+    memory_region_init_io(&s->mmio, obj, &ibexdemo_uart_ops, s,
+                          TYPE_IBEXDEMO_UART, 0x1000u);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    fifo8_create(&s->rx_fifo, IBEXDEMO_UART_RX_FIFO_SIZE);
+    fifo8_create(&s->tx_fifo, IBEXDEMO_UART_TX_FIFO_SIZE);
+}
+
+static void ibexdemo_uart_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    device_class_set_legacy_reset(dc, &ibexdemo_uart_reset);
+    dc->realize = &ibexdemo_uart_realize;
+    device_class_set_props(dc, ibexdemo_uart_properties);
+    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+}
+
+static const TypeInfo ibexdemo_uart_info = {
+    .name = TYPE_IBEXDEMO_UART,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IbexDemoUARTState),
+    .instance_init = &ibexdemo_uart_init,
+    .class_init = &ibexdemo_uart_class_init,
+};
+
+static void ibexdemo_uart_register_types(void)
+{
+    type_register_static(&ibexdemo_uart_info);
+}
+
+type_init(ibexdemo_uart_register_types);
diff --git a/hw/ibexdemo/meson.build b/hw/ibexdemo/meson.build
new file mode 100644
index 0000000000000..4a7223adae976
--- /dev/null
+++ b/hw/ibexdemo/meson.build
@@ -0,0 +1,7 @@
+# Ibex Demo System
+
+system_ss.add(when: 'CONFIG_IBEXDEMO_GPIO', if_true: files('ibexdemo_gpio.c'))
+system_ss.add(when: 'CONFIG_IBEXDEMO_SIMCTRL', if_true: files('ibexdemo_simctrl.c'))
+system_ss.add(when: 'CONFIG_IBEXDEMO_SPI', if_true: files('ibexdemo_spi.c'))
+system_ss.add(when: 'CONFIG_IBEXDEMO_TIMER', if_true: files('ibexdemo_timer.c'))
+system_ss.add(when: 'CONFIG_IBEXDEMO_UART', if_true: files('ibexdemo_uart.c'))
diff --git a/hw/ibexdemo/trace-events b/hw/ibexdemo/trace-events
new file mode 100644
index 0000000000000..52b20f8b42d4b
--- /dev/null
+++ b/hw/ibexdemo/trace-events
@@ -0,0 +1,10 @@
+# IbexDemo Trace Events
+
+# ibexdemo_gpio
+
+ibexdemo_gpio_input(uint32_t gpios) "in: [0x%08x]"
+ibexdemo_gpio_output(uint32_t gpios) "out: [0x%08x]"
+
+# ibexdemo_spi.c
+
+ibexdemo_spi_output(uint8_t byte) "[0x%02x]"
diff --git a/hw/ibexdemo/trace.h b/hw/ibexdemo/trace.h
new file mode 100644
index 0000000000000..74ceb8745b56d
--- /dev/null
+++ b/hw/ibexdemo/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_ibexdemo.h"
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 3160b216fdc97..80b6a4e131960 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -31,6 +31,7 @@
 #include "migration/vmstate.h"
 #include "hw/irq.h"
 #include "system/kvm.h"
+#include "trace.h"
 
 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
 {
@@ -62,14 +63,32 @@ static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
     return old;
 }
 
+static void sifive_plic_set_level(SiFivePLICState *plic, int irq, bool level)
+{
+    atomic_set_masked(&plic->level[irq >> 5], 1 << (irq & 31), -!!level);
+}
+
+static bool sifive_plic_get_level(SiFivePLICState *plic, int irq)
+{
+    return (plic->level[irq >> 5] & (1 << (irq & 31))) != 0;
+}
+
 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
 {
-    atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
+    uint32_t old;
+    old = atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -level);
+    if ((old >> (irq & 31)) ^ level) {
+        trace_sifive_plic_set_pending(irq, level);
+    }
 }
 
 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
 {
-    atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
+    uint32_t old;
+    old = atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -level);
+    if ((old >> (irq & 31)) ^ level) {
+        trace_sifive_plic_set_claimed(irq, level);
+    }
 }
 
 static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
@@ -124,9 +143,11 @@ static void sifive_plic_update(SiFivePLICState *plic)
 
         switch (mode) {
         case PLICMode_M:
+            trace_sifive_plic_update(hartid, 'M', level);
             qemu_set_irq(plic->m_external_irqs[hartid - plic->hartid_base], level);
             break;
         case PLICMode_S:
+            trace_sifive_plic_update(hartid, 'S', level);
             qemu_set_irq(plic->s_external_irqs[hartid - plic->hartid_base], level);
             break;
         default:
@@ -202,9 +223,11 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
              * out the access to unsupported priority bits.
              */
             plic->source_priority[irq] = value % (plic->num_priorities + 1);
+            trace_sifive_plic_set_priority(irq, plic->source_priority[irq]);
             sifive_plic_update(plic);
         } else if (value <= plic->num_priorities) {
             plic->source_priority[irq] = value;
+            trace_sifive_plic_set_priority(irq, plic->source_priority[irq]);
             sifive_plic_update(plic);
         }
     } else if (addr_between(addr, plic->pending_base,
@@ -219,6 +242,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
 
         if (wordid < plic->bitfield_words) {
             plic->enable[addrid * plic->bitfield_words + wordid] = value;
+            sifive_plic_update(plic);
         } else {
             qemu_log_mask(LOG_GUEST_ERROR,
                           "%s: Invalid enable write 0x%" HWADDR_PRIx "\n",
@@ -280,6 +304,7 @@ static void sifive_plic_reset(DeviceState *dev)
     memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words);
     memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
     memset(s->enable, 0, sizeof(uint32_t) * s->num_enables);
+    memset(s->level, 0, sizeof(uint32_t) * s->bitfield_words);
 
     for (i = 0; i < s->num_harts; i++) {
         qemu_set_irq(s->m_external_irqs[i], 0);
@@ -354,10 +379,19 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
 {
     SiFivePLICState *s = opaque;
 
-    if (level > 0) {
-        sifive_plic_set_pending(s, irq, true);
-        sifive_plic_update(s);
+    assert(irq < s->num_sources);
+
+    if (s->edge_triggered) {
+        if (level && !sifive_plic_get_level(s, irq)) {
+            sifive_plic_set_pending(s, irq, true);
+        }
+        sifive_plic_set_level(s, irq, !!level);
+    } else {
+        if (level > 0) {
+            sifive_plic_set_pending(s, irq, true);
+        }
     }
+    sifive_plic_update(s);
 }
 
 static void sifive_plic_realize(DeviceState *dev, Error **errp)
@@ -383,6 +417,7 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
     s->pending = g_new0(uint32_t, s->bitfield_words);
     s->claimed = g_new0(uint32_t, s->bitfield_words);
     s->enable = g_new0(uint32_t, s->num_enables);
+    s->level = g_new0(uint32_t, s->bitfield_words);
 
     qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
 
@@ -444,6 +479,7 @@ static const Property sifive_plic_properties[] = {
     DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
     DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
     DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
+    DEFINE_PROP_BOOL("edge-triggered", SiFivePLICState, edge_triggered, false),
 };
 
 static void sifive_plic_class_init(ObjectClass *klass, const void *data)
@@ -479,7 +515,8 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     uint32_t num_priorities, uint32_t priority_base,
     uint32_t pending_base, uint32_t enable_base,
     uint32_t enable_stride, uint32_t context_base,
-    uint32_t context_stride, uint32_t aperture_size)
+    uint32_t context_stride, uint32_t aperture_size,
+    bool edge_triggered)
 {
     DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
     int i;
@@ -498,6 +535,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     qdev_prop_set_uint32(dev, "context-base", context_base);
     qdev_prop_set_uint32(dev, "context-stride", context_stride);
     qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
+    qdev_prop_set_bit(dev, "edge-triggered", edge_triggered);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 018c609ca5eb9..ce406fd8ae939 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -330,3 +330,10 @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
 loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
 loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
 loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
+
+# sifive_plic.c
+
+sifive_plic_set_claimed(int irq, bool level) "irq %d: %u"
+sifive_plic_set_priority(uint32_t irq, uint32_t prio) "irq %u: %u"
+sifive_plic_set_pending(int irq, bool level) "irq %d: %u"
+sifive_plic_update(uint32_t hartid, int mode, bool level) "hart %u %c: %u"
diff --git a/hw/jtag/Kconfig b/hw/jtag/Kconfig
new file mode 100644
index 0000000000000..1e3eddbf965e8
--- /dev/null
+++ b/hw/jtag/Kconfig
@@ -0,0 +1,8 @@
+# JTAG devices
+
+config TAP_CTRL
+    bool
+
+config TAP_CTRL_RBB
+    select TAP_CTRL
+    bool
diff --git a/hw/jtag/meson.build b/hw/jtag/meson.build
new file mode 100644
index 0000000000000..677ea188ee5e2
--- /dev/null
+++ b/hw/jtag/meson.build
@@ -0,0 +1,2 @@
+system_ss.add(when: 'CONFIG_TAP_CTRL', if_true: files('tap_ctrl.c'))
+system_ss.add(when: 'CONFIG_TAP_CTRL_RBB', if_true: files('tap_ctrl_rbb.c'))
diff --git a/hw/jtag/tap_ctrl.c b/hw/jtag/tap_ctrl.c
new file mode 100644
index 0000000000000..e335e584045e7
--- /dev/null
+++ b/hw/jtag/tap_ctrl.c
@@ -0,0 +1,42 @@
+/*
+ * QEMU JTAG TAP controller interface
+ *
+ * Copyright (c) 2023 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/jtag/tap_ctrl.h"
+
+static const TypeInfo tap_ctrl_info = {
+    .name = TYPE_TAP_CTRL_IF,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(TapCtrlIfClass),
+};
+
+static void tap_ctrl_register_types(void)
+{
+    type_register_static(&tap_ctrl_info);
+}
+
+type_init(tap_ctrl_register_types);
diff --git a/hw/jtag/tap_ctrl_rbb.c b/hw/jtag/tap_ctrl_rbb.c
new file mode 100644
index 0000000000000..4554b2065b1ae
--- /dev/null
+++ b/hw/jtag/tap_ctrl_rbb.c
@@ -0,0 +1,723 @@
+/*
+ * QEMU JTAG TAP controller for the OpenOCD/Spike Remote BigBang protocol
+ *
+ * Copyright (c) 2022-2024 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * For details check the documentation here:
+ *    https://github.com/openocd-org/openocd/blob/master/
+ *       doc/manual/jtag/drivers/remote_bitbang.txt
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "qom/object.h"
+#include "chardev/char-fe.h"
+#include "chardev/char-socket.h"
+#include "chardev/char.h"
+#include "hw/jtag/tap_ctrl.h"
+#include "hw/jtag/tap_ctrl_rbb.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/resettable.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+
+typedef enum {
+    TEST_LOGIC_RESET,
+    RUN_TEST_IDLE,
+    SELECT_DR_SCAN,
+    CAPTURE_DR,
+    SHIFT_DR,
+    EXIT1_DR,
+    PAUSE_DR,
+    EXIT2_DR,
+    UPDATE_DR,
+    SELECT_IR_SCAN,
+    CAPTURE_IR,
+    SHIFT_IR,
+    EXIT1_IR,
+    PAUSE_IR,
+    EXIT2_IR,
+    UPDATE_IR,
+    _TAP_STATE_COUNT
+} TAPState;
+
+typedef TapDataHandler *tap_ctrl_data_reg_extender_t(uint64_t value);
+
+typedef struct TapCtrlRbbState {
+    DeviceState parent;
+
+    TAPState state; /* Current state */
+
+    /* signals */
+    bool trst; /* TAP controller reset */
+    bool srst; /* System reset */
+    bool tck; /* JTAG clock */
+    bool tms; /* JTAG state machine selector */
+    bool tdi; /* Register input */
+    bool tdo; /* Register output */
+
+    /* registers */
+    uint64_t ir; /* instruction register value */
+    uint64_t ir_hold; /* IR hold register */
+    uint64_t dr; /* current data register value */
+    size_t dr_len; /* count of meaningful bits in dr */
+
+    /* handlers */
+    TapDataHandler *tdh; /* Current data register handler */
+    GHashTable *tdhtable; /* Registered handlers */
+
+    guint watch_tag; /* tracker for comm device change */
+
+    /* properties */
+    CharFrontend chr;
+    uint32_t idcode; /* TAP controller identifier */
+    uint8_t ir_length; /* count of meaningful bits in ir */
+    uint8_t idcode_inst; /* instruction to get ID code */
+    bool enable_quit; /* whether VM quit can be remotely triggered */
+} TapCtrlRbbState;
+
+typedef struct _TAPRegisterState {
+    int base_reg;
+    int num_regs;
+    struct TAPRegisterState *next;
+} TAPRegisterState;
+
+typedef struct _TAPProcess {
+    uint32_t pid;
+    bool attached;
+} TAPProcess;
+
+#define STRINGIFY_(_val_)   #_val_
+#define STRINGIFY(_val_)    STRINGIFY_(_val_)
+#define NAME_FSMSTATE(_st_) [_st_] = STRINGIFY(_st_)
+
+#define DEFAULT_JTAG_BITBANG_PORT "3335"
+#define MAX_PACKET_LENGTH         4096u
+
+#define TAP_CTRL_BYPASS_INST 0u
+
+/*
+ * TAP controller state machine state/event matrix
+ *
+ * Current state -> Next States for either TMS == 0 or TMS == 1
+ */
+static const TAPState TAPFSM[_TAP_STATE_COUNT][2] = {
+    [TEST_LOGIC_RESET] = { RUN_TEST_IDLE, TEST_LOGIC_RESET },
+    [RUN_TEST_IDLE] = { RUN_TEST_IDLE, SELECT_DR_SCAN },
+    [SELECT_DR_SCAN] = { CAPTURE_DR, SELECT_IR_SCAN },
+    [CAPTURE_DR] = { SHIFT_DR, EXIT1_DR },
+    [SHIFT_DR] = { SHIFT_DR, EXIT1_DR },
+    [EXIT1_DR] = { PAUSE_DR, UPDATE_DR },
+    [PAUSE_DR] = { PAUSE_DR, EXIT2_DR },
+    [EXIT2_DR] = { SHIFT_DR, UPDATE_DR },
+    [UPDATE_DR] = { RUN_TEST_IDLE, SELECT_DR_SCAN },
+    [SELECT_IR_SCAN] = { CAPTURE_IR, TEST_LOGIC_RESET },
+    [CAPTURE_IR] = { SHIFT_IR, EXIT1_IR },
+    [SHIFT_IR] = { SHIFT_IR, EXIT1_IR },
+    [EXIT1_IR] = { PAUSE_IR, UPDATE_IR },
+    [PAUSE_IR] = { PAUSE_IR, EXIT2_IR },
+    [EXIT2_IR] = { SHIFT_IR, UPDATE_IR },
+    [UPDATE_IR] = { RUN_TEST_IDLE, SELECT_DR_SCAN }
+};
+
+static const char TAPFSM_NAMES[_TAP_STATE_COUNT][18U] = {
+    NAME_FSMSTATE(TEST_LOGIC_RESET), NAME_FSMSTATE(RUN_TEST_IDLE),
+    NAME_FSMSTATE(SELECT_DR_SCAN),   NAME_FSMSTATE(CAPTURE_DR),
+    NAME_FSMSTATE(SHIFT_DR),         NAME_FSMSTATE(EXIT1_DR),
+    NAME_FSMSTATE(PAUSE_DR),         NAME_FSMSTATE(EXIT2_DR),
+    NAME_FSMSTATE(UPDATE_DR),        NAME_FSMSTATE(SELECT_IR_SCAN),
+    NAME_FSMSTATE(CAPTURE_IR),       NAME_FSMSTATE(SHIFT_IR),
+    NAME_FSMSTATE(EXIT1_IR),         NAME_FSMSTATE(PAUSE_IR),
+    NAME_FSMSTATE(EXIT2_IR),         NAME_FSMSTATE(UPDATE_IR),
+};
+
+static void tap_ctrl_rbb_idcode_capture(TapDataHandler *tdh);
+
+/* Common TAP instructions */
+static const TapDataHandler TAP_CTRL_RBB_BYPASS = {
+    .name = "bypass",
+    .length = 1,
+    .value = 0,
+};
+
+static const TapDataHandler TAP_CTRL_RBB_IDCODE = {
+    .name = "idcode",
+    .length = 32,
+    .capture = &tap_ctrl_rbb_idcode_capture,
+};
+
+/*
+ * TAP State Machine implementation
+ */
+
+static void tap_ctrl_rbb_dump_register(const char *msg, const char *iname,
+                                       uint64_t value, size_t length)
+{
+    char buf[80];
+    if (length > 64u) {
+        length = 64u;
+    }
+    unsigned ix = 0;
+    while (ix < length) {
+        buf[ix] = (char)('0' + ((value >> (length - ix - 1)) & 0b1));
+        ix++;
+    }
+    buf[ix] = '\0';
+
+    if (iname) {
+        trace_tap_ctrl_rbb_idump_register(msg, iname, value, length, buf);
+    } else {
+        trace_tap_ctrl_rbb_dump_register(msg, value, length, buf);
+    }
+}
+
+static bool tap_ctrl_rbb_has_data_handler(TapCtrlRbbState *tap, unsigned code)
+{
+    return (bool)g_hash_table_contains(tap->tdhtable, GINT_TO_POINTER(code));
+}
+
+static TapDataHandler *
+tap_ctrl_rbb_get_data_handler(TapCtrlRbbState *tap, unsigned code)
+{
+    TapDataHandler *tdh;
+    tdh = (TapDataHandler *)g_hash_table_lookup(tap->tdhtable,
+                                                GINT_TO_POINTER(code));
+    return tdh;
+}
+
+static void tap_ctrl_rbb_idcode_capture(TapDataHandler *tdh)
+{
+    /* special case for ID code: opaque contains the ID code value */
+    tdh->value = (uint64_t)(uintptr_t)tdh->opaque;
+}
+
+static void tap_ctrl_rbb_tap_reset(TapCtrlRbbState *tap)
+{
+    tap->state = TEST_LOGIC_RESET;
+    tap->trst = false;
+    tap->srst = false;
+    tap->tck = false;
+    tap->tms = false;
+    tap->tdi = false;
+    tap->tdo = false;
+    tap->ir = tap->idcode_inst;
+    tap->ir_hold = tap->idcode_inst;
+    tap->dr = 0u;
+    tap->dr_len = 0u;
+    tap->tdh = tap_ctrl_rbb_get_data_handler(tap, tap->idcode_inst);
+    g_assert(tap->tdh);
+}
+
+static void tap_ctrl_rbb_system_reset(TapCtrlRbbState *tap)
+{
+    Object *ms = qdev_get_machine();
+    ObjectClass *mc = object_get_class(ms);
+    (void)tap;
+
+    if (!object_class_dynamic_cast(mc, TYPE_RESETTABLE_INTERFACE)) {
+        qemu_log_mask(LOG_UNIMP, "%s: Machine %s is not resettable\n", __func__,
+                      object_get_typename(ms));
+        return;
+    }
+
+    trace_tap_ctrl_rbb_system_reset();
+    resettable_reset(ms, RESET_TYPE_COLD);
+}
+
+static TAPState tap_ctrl_rbb_get_next_state(TapCtrlRbbState *tap, bool tms)
+{
+    tap->state = TAPFSM[tap->state][(unsigned)tms];
+    return tap->state;
+}
+
+static void tap_ctrl_rbb_capture_ir(TapCtrlRbbState *tap)
+{
+    tap->ir = tap->idcode_inst;
+}
+
+static void tap_ctrl_rbb_shift_ir(TapCtrlRbbState *tap, bool tdi)
+{
+    tap->ir >>= 1u;
+    tap->ir |= ((uint64_t)(tdi)) << (tap->ir_length - 1u);
+}
+
+static void tap_ctrl_rbb_update_ir(TapCtrlRbbState *tap)
+{
+    tap->ir_hold = tap->ir;
+    tap_ctrl_rbb_dump_register("Update IR", NULL, tap->ir_hold, tap->ir_length);
+}
+
+static void tap_ctrl_rbb_capture_dr(TapCtrlRbbState *tap)
+{
+    TapDataHandler *prev = tap->tdh;
+
+    if (tap->ir_hold >= (1 << tap->ir_length)) {
+        /* internal error, should never happen */
+        error_setg(&error_fatal, "Invalid IR 0x%02x\n", (unsigned)tap->ir_hold);
+        g_assert_not_reached();
+    }
+
+    TapDataHandler *tdh = tap_ctrl_rbb_get_data_handler(tap, tap->ir_hold);
+    if (!tdh) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown IR 0x%02x\n", __func__,
+                      (unsigned)tap->ir_hold);
+        tap->dr = 0;
+        return;
+    }
+
+    if (tdh != prev) {
+        trace_tap_ctrl_rbb_select_dr(tdh->name, tap->ir_hold);
+    }
+
+    tap->tdh = tdh;
+    tap->dr_len = tdh->length;
+
+    if (tdh->capture) {
+        tdh->capture(tdh);
+    }
+    tap->dr = tdh->value;
+    tap_ctrl_rbb_dump_register("Capture DR", tap->tdh->name, tap->dr,
+                               tap->dr_len);
+}
+
+static void tap_ctrl_rbb_shift_dr(TapCtrlRbbState *tap, bool tdi)
+{
+    tap->dr >>= 1u;
+    tap->dr |= ((uint64_t)(tdi)) << (tap->dr_len - 1u);
+}
+
+static void tap_ctrl_rbb_update_dr(TapCtrlRbbState *tap)
+{
+    tap_ctrl_rbb_dump_register("Update DR", tap->tdh->name, tap->dr,
+                               tap->dr_len);
+    TapDataHandler *tdh = tap->tdh;
+    tdh->value = tap->dr;
+    if (tdh->update) {
+        tdh->update(tdh);
+    }
+}
+
+static void tap_ctrl_rbb_step(TapCtrlRbbState *tap, bool tck, bool tms,
+                              bool tdi)
+{
+    trace_tap_ctrl_rbb_step(tck, tms, tdi);
+
+    if (tap->trst) {
+        return;
+    }
+
+    if (!tap->tck && tck) {
+        /* Rising clock edge */
+        if (tap->state == SHIFT_IR) {
+            tap_ctrl_rbb_shift_ir(tap, tap->tdi);
+        } else if (tap->state == SHIFT_DR) {
+            tap_ctrl_rbb_shift_dr(tap, tap->tdi);
+        }
+        TAPState prev = tap->state;
+        TAPState new = tap_ctrl_rbb_get_next_state(tap, tms);
+        if (prev != new) {
+            trace_tap_ctrl_rbb_change_state(TAPFSM_NAMES[prev],
+                                            TAPFSM_NAMES[new]);
+        }
+    } else {
+        /* Falling clock edge */
+        switch (tap->state) {
+        case RUN_TEST_IDLE:
+            /* do nothing */
+            break;
+        case TEST_LOGIC_RESET:
+            tap_ctrl_rbb_tap_reset(tap);
+            break;
+        case CAPTURE_DR:
+            tap_ctrl_rbb_capture_dr(tap);
+            break;
+        case SHIFT_DR:
+            tap->tdo = tap->dr & 0b1;
+            break;
+        case UPDATE_DR:
+            tap_ctrl_rbb_update_dr(tap);
+            break;
+        case CAPTURE_IR:
+            tap_ctrl_rbb_capture_ir(tap);
+            break;
+        case SHIFT_IR:
+            tap->tdo = tap->ir & 0b1;
+            break;
+        case UPDATE_IR:
+            tap_ctrl_rbb_update_ir(tap);
+            break;
+        default:
+            /* nothing to do on the other state transition */
+            break;
+        }
+    }
+    tap->tck = tck;
+    tap->tdi = tdi;
+    tap->tms = tms;
+}
+
+static void tap_ctrl_rbb_blink(TapCtrlRbbState *tap, bool light) {}
+
+static void tap_ctrl_rbb_read(TapCtrlRbbState *tap)
+{
+    trace_tap_ctrl_rbb_read(tap->tdo);
+}
+
+static void tap_ctrl_rbb_quit(TapCtrlRbbState *tap)
+{
+    (void)tap;
+
+    if (tap->enable_quit) {
+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+    } else {
+        info_report("%s: JTAG termination disabled\n", __func__);
+    }
+}
+
+static void tap_ctrl_rbb_write(TapCtrlRbbState *tap, bool tck, bool tms,
+                               bool tdi)
+{
+    tap_ctrl_rbb_step(tap, tck, tms, tdi);
+}
+
+static void tap_ctrl_rbb_reset_tap(TapCtrlRbbState *tap, bool trst, bool srst)
+{
+    trace_tap_ctrl_rbb_reset(trst, srst);
+    if (trst) {
+        tap_ctrl_rbb_tap_reset(tap);
+    }
+    if (srst) {
+        tap_ctrl_rbb_system_reset(tap);
+    }
+    tap->trst = trst;
+    tap->srst = srst;
+}
+
+/*
+ * TAP Server implementation
+ */
+
+static bool tap_ctrl_rbb_read_byte(TapCtrlRbbState *tap, uint8_t ch)
+{
+    switch ((char)ch) {
+    case 'B':
+        tap_ctrl_rbb_blink(tap, true);
+        break;
+    case 'b':
+        tap_ctrl_rbb_blink(tap, false);
+        break;
+    case 'R':
+        tap_ctrl_rbb_read(tap);
+        break;
+    case 'Q':
+        tap_ctrl_rbb_quit(tap);
+        break;
+    case '0':
+        tap_ctrl_rbb_write(tap, false, false, false);
+        break;
+    case '1':
+        tap_ctrl_rbb_write(tap, false, false, true);
+        break;
+    case '2':
+        tap_ctrl_rbb_write(tap, false, true, false);
+        break;
+    case '3':
+        tap_ctrl_rbb_write(tap, false, true, true);
+        break;
+    case '4':
+        tap_ctrl_rbb_write(tap, true, false, false);
+        break;
+    case '5':
+        tap_ctrl_rbb_write(tap, true, false, true);
+        break;
+    case '6':
+        tap_ctrl_rbb_write(tap, true, true, false);
+        break;
+    case '7':
+        tap_ctrl_rbb_write(tap, true, true, true);
+        break;
+    case 'r':
+        tap_ctrl_rbb_reset_tap(tap, false, false);
+        break;
+    case 's':
+        tap_ctrl_rbb_reset_tap(tap, false, true);
+        break;
+    case 't':
+        tap_ctrl_rbb_reset_tap(tap, true, false);
+        break;
+    case 'u':
+        tap_ctrl_rbb_reset_tap(tap, true, true);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: Unknown TAP code 0x%02x\n", __func__,
+                      (unsigned)ch);
+        break;
+    }
+
+    /* true if TDO level should be sent to the peer */
+    return (int)ch == 'R';
+}
+
+static int tap_ctrl_rbb_chr_can_receive(void *opaque)
+{
+    TapCtrlRbbState *tap = (TapCtrlRbbState *)opaque;
+
+    /* do not accept any input till a TAP controller is available */
+    return qemu_chr_fe_backend_connected(&tap->chr) ? MAX_PACKET_LENGTH : 0;
+}
+
+static void tap_ctrl_rbb_chr_receive(void *opaque, const uint8_t *buf, int size)
+{
+    TapCtrlRbbState *tap = (TapCtrlRbbState *)opaque;
+
+    for (unsigned ix = 0; ix < size; ix++) {
+        if (tap_ctrl_rbb_read_byte(tap, buf[ix])) {
+            uint8_t outbuf[1] = { '0' + (unsigned)tap->tdo };
+            qemu_chr_fe_write_all(&tap->chr, outbuf, (int)sizeof(outbuf));
+        }
+    }
+}
+
+static void tap_ctrl_rbb_chr_event_hander(void *opaque, QEMUChrEvent event)
+{
+    TapCtrlRbbState *tap = opaque;
+
+    if (event == CHR_EVENT_OPENED) {
+        if (!qemu_chr_fe_backend_connected(&tap->chr)) {
+            return;
+        }
+
+        Object *sock;
+        sock = object_dynamic_cast(OBJECT(tap->chr.chr), TYPE_CHARDEV_SOCKET);
+        if (sock) {
+            qio_channel_set_delay(SOCKET_CHARDEV(sock)->ioc, false);
+        }
+
+        tap_ctrl_rbb_tap_reset(tap);
+    }
+}
+
+static gboolean
+tap_ctrl_rbb_chr_watch_cb(void *do_not_use, GIOCondition cond, void *opaque)
+{
+    TapCtrlRbbState *tap = opaque;
+    (void)do_not_use;
+    (void)cond;
+
+    tap->watch_tag = 0;
+
+    return FALSE;
+}
+
+static int tap_ctrl_rbb_chr_be_change(void *opaque)
+{
+    TapCtrlRbbState *tap = opaque;
+
+    qemu_chr_fe_set_handlers(&tap->chr, &tap_ctrl_rbb_chr_can_receive,
+                             &tap_ctrl_rbb_chr_receive,
+                             &tap_ctrl_rbb_chr_event_hander,
+                             &tap_ctrl_rbb_chr_be_change, tap, NULL, true);
+
+    tap_ctrl_rbb_tap_reset(tap);
+
+    if (tap->watch_tag > 0) {
+        g_source_remove(tap->watch_tag);
+        // NOLINTNEXTLINE(clang-analyzer-optin.core.EnumCastOutOfRange)
+        tap->watch_tag = qemu_chr_fe_add_watch(&tap->chr, G_IO_OUT | G_IO_HUP,
+                                               &tap_ctrl_rbb_chr_watch_cb, tap);
+    }
+
+    return 0;
+}
+
+static void tap_ctrl_rbb_verify_handler(const TapCtrlRbbState *tap,
+                                        unsigned code, const char *name)
+{
+    if (code >= (1 << tap->ir_length)) {
+        error_setg(&error_fatal, "JTAG: Invalid IR code: 0x%x for %s", code,
+                   name);
+        g_assert_not_reached();
+    }
+}
+
+static void
+tap_ctrl_rbb_verify_handler_fn(gpointer key, gpointer value, gpointer user_data)
+{
+    unsigned code = GPOINTER_TO_INT(key);
+    const TapDataHandler *tdh = (const TapDataHandler *)value;
+    const TapCtrlRbbState *tap = (const TapCtrlRbbState *)user_data;
+
+    tap_ctrl_rbb_verify_handler(tap, code, tdh->name);
+}
+
+static void tap_ctrl_rbb_register_handler(TapCtrlRbbState *tap, unsigned code,
+                                          const TapDataHandler *tdh, bool check)
+{
+    if (check) {
+        tap_ctrl_rbb_verify_handler(tap, code, tdh->name);
+    }
+
+    if (tap_ctrl_rbb_has_data_handler(tap, code)) {
+        warn_report("JTAG: IR code already registered: 0x%x", code);
+        /* resume and override */
+    }
+
+    TapDataHandler *ltdh = g_new0(TapDataHandler, 1u);
+    memcpy(ltdh, tdh, sizeof(*tdh));
+    ltdh->name = g_strdup(tdh->name);
+    g_hash_table_insert(tap->tdhtable, GINT_TO_POINTER(code), ltdh);
+
+    trace_tap_ctrl_rbb_register(code, ltdh->name);
+}
+
+static void tap_ctrl_rbb_free_data_handler(gpointer entry)
+{
+    TapDataHandler *tdh = entry;
+    if (!entry) {
+        return;
+    }
+    g_free((char *)tdh->name);
+    g_free(tdh);
+}
+
+static bool tap_ctrl_rbb_is_enabled(TapCtrlIf *dev)
+{
+    TapCtrlRbbState *tap = TAP_CTRL_RBB(dev);
+
+    return qemu_chr_fe_backend_connected(&tap->chr);
+}
+
+static int tap_ctrl_rbb_register_instruction(TapCtrlIf *dev, unsigned code,
+                                             const TapDataHandler *tdh)
+{
+    TapCtrlRbbState *tap = TAP_CTRL_RBB(dev);
+
+    tap_ctrl_rbb_register_handler(tap, code, tdh, DEVICE(tap)->realized);
+
+    return 0;
+}
+
+static const Property tap_ctrl_rbb_properties[] = {
+    DEFINE_PROP_UINT32("idcode", TapCtrlRbbState, idcode, 0),
+    DEFINE_PROP_UINT8("ir_length", TapCtrlRbbState, ir_length, 0),
+    DEFINE_PROP_UINT8("idcode_inst", TapCtrlRbbState, idcode_inst, 1u),
+    DEFINE_PROP_BOOL("quit", TapCtrlRbbState, enable_quit, true),
+    DEFINE_PROP_CHR("chardev", TapCtrlRbbState, chr),
+};
+
+static void tap_ctrl_rbb_realize(DeviceState *dev, Error **errp)
+{
+    TapCtrlRbbState *tap = TAP_CTRL_RBB(dev);
+
+    if (tap->ir_length == 0 || tap->ir_length > 8u) {
+        error_setg(errp, "Unsupported IR length: %u", tap->ir_length);
+        return;
+    }
+
+    if (tap->idcode == 0u) {
+        error_setg(errp, "Invalid IDCODE: 0x%x", tap->idcode);
+        return;
+    }
+
+    if (tap->idcode_inst == TAP_CTRL_BYPASS_INST) {
+        error_setg(errp, "Invalid IDCODE instruction: 0x%x", tap->idcode_inst);
+        return;
+    }
+
+    trace_tap_ctrl_rbb_realize(tap->ir_length, tap->idcode);
+
+    /*
+     * Handlers may be registered before the TAP controller is configured.
+     * Need to check their configuration once the configuration is known
+     */
+    g_hash_table_foreach(tap->tdhtable, &tap_ctrl_rbb_verify_handler_fn,
+                         (gpointer)tap);
+
+    size_t irslots = 1u << tap->ir_length;
+    tap_ctrl_rbb_register_handler(tap, TAP_CTRL_BYPASS_INST,
+                                  &TAP_CTRL_RBB_BYPASS, true);
+    tap_ctrl_rbb_register_handler(tap, tap->idcode_inst, &TAP_CTRL_RBB_IDCODE,
+                                  true);
+    tap_ctrl_rbb_register_handler(tap, irslots - 1u, &TAP_CTRL_RBB_BYPASS,
+                                  true);
+    /* special case for ID code: opaque store the constant idcode value */
+    TapDataHandler *tdh = tap_ctrl_rbb_get_data_handler(tap, tap->idcode_inst);
+    g_assert(tdh);
+    tdh->opaque = (void *)(uintptr_t)tap->idcode;
+
+    qemu_chr_fe_set_handlers(&tap->chr, &tap_ctrl_rbb_chr_can_receive,
+                             &tap_ctrl_rbb_chr_receive,
+                             &tap_ctrl_rbb_chr_event_hander,
+                             &tap_ctrl_rbb_chr_be_change, tap, NULL, true);
+
+    tap_ctrl_rbb_tap_reset(tap);
+
+    qemu_chr_fe_accept_input(&tap->chr);
+}
+
+static void tap_ctrl_rbb_init(Object *obj)
+{
+    TapCtrlRbbState *tap = TAP_CTRL_RBB(obj);
+
+    tap->tdhtable = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
+                                          tap_ctrl_rbb_free_data_handler);
+}
+
+static void tap_ctrl_rbb_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &tap_ctrl_rbb_realize;
+    device_class_set_props(dc, tap_ctrl_rbb_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    TapCtrlIfClass *tcc = TAP_CTRL_IF_CLASS(klass);
+    tcc->is_enabled = &tap_ctrl_rbb_is_enabled;
+    tcc->register_instruction = &tap_ctrl_rbb_register_instruction;
+}
+
+static const TypeInfo tap_ctrl_rbb_info = {
+    .name = TYPE_TAP_CTRL_RBB,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(TapCtrlRbbState),
+    .instance_init = &tap_ctrl_rbb_init,
+    .class_init = &tap_ctrl_rbb_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_TAP_CTRL_IF },
+            {},
+        },
+};
+
+static void register_types(void)
+{
+    type_register_static(&tap_ctrl_rbb_info);
+}
+
+type_init(register_types);
diff --git a/hw/jtag/trace-events b/hw/jtag/trace-events
new file mode 100644
index 0000000000000..ab419c3454759
--- /dev/null
+++ b/hw/jtag/trace-events
@@ -0,0 +1,13 @@
+# tap_ctrl_rbb.c
+
+tap_ctrl_rbb_change(const char *msg, const char *value) "%s %s"
+tap_ctrl_rbb_change_state(const char *prev, const char *new) "%s -> %s"
+tap_ctrl_rbb_dump_register(const char *msg, uint64_t val, size_t len, const char *buf) "%s: 0x%" PRIx64 "/%zu [b%s]"
+tap_ctrl_rbb_idump_register(const char *msg, const char *iname, uint64_t val, size_t len, const char *buf) "%s (%s): 0x%" PRIx64 "/%zu [b%s]"
+tap_ctrl_rbb_read(bool tdo) "tdo %u"
+tap_ctrl_rbb_realize(size_t irlen, uint32_t ircode) "irlength %zu, idcode 0x%08x"
+tap_ctrl_rbb_register(unsigned code, const char *name) "register 0x%x: %s"
+tap_ctrl_rbb_reset(bool tap, bool sys) "tap: %u, system: %u"
+tap_ctrl_rbb_select_dr(const char *name, uint64_t value) "Select DR %s 0x%02" PRIx64
+tap_ctrl_rbb_step(bool tck, bool tms, bool tdi) "tck:%u tms:%u tdi:%u"
+tap_ctrl_rbb_system_reset(void) "SYSTEM RESET"
diff --git a/hw/jtag/trace.h b/hw/jtag/trace.h
new file mode 100644
index 0000000000000..b0a55dce5901c
--- /dev/null
+++ b/hw/jtag/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_jtag.h"
diff --git a/hw/meson.build b/hw/meson.build
index 1022bdb8069a1..9a0c33cbfd512 100644
--- a/hw/meson.build
+++ b/hw/meson.build
@@ -21,6 +21,10 @@ subdir('sparc64')
 subdir('tricore')
 subdir('xtensa')
 
+subdir('ibexdemo')
+subdir('jtag')
+subdir('opentitan')
+
 subdir('9pfs')
 subdir('acpi')
 subdir('adc')
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index fccd735c24c12..7b50a5b22ce7d 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -240,4 +240,8 @@ config IOSB
 config XLNX_VERSAL_TRNG
     bool
 
+config PULP_RV_DM
+    select RISCV_DM
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index b1d8d8e5d2a93..f40294a4b208b 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -35,6 +35,9 @@ system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c'))
 system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
 
+# Pulp devices
+system_ss.add(when: 'CONFIG_PULP_RV_DM', if_true: files('pulp_rv_dm.c'))
+
 subdir('macio')
 
 # ivshmem devices
diff --git a/hw/misc/pulp_rv_dm.c b/hw/misc/pulp_rv_dm.c
new file mode 100644
index 0000000000000..8350b75a4474c
--- /dev/null
+++ b/hw/misc/pulp_rv_dm.c
@@ -0,0 +1,555 @@
+/*
+ * QEMU Pulp Debug Module device
+ *
+ * Copyright (c) 2022-2024 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * For details check the documentation here:
+ *    https://docs.opentitan.org/hw/ip/rv_dm/doc/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file should be splitted so that RISCV info belong to target/riscv
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitmap.h"
+#include "qemu/guest-random.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "exec/memattrs.h"
+#include "hw/boards.h"
+#include "hw/core/cpu.h"
+#include "hw/irq.h"
+#include "hw/jtag/tap_ctrl.h"
+#include "hw/loader.h"
+#include "hw/misc/pulp_rv_dm.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/dm.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+
+/*
+ * Configuration
+ */
+
+#define DISCARD_REPEATED_IO_TRACES
+#define DISTANCE_ACCESS_IO_TRACES 40u
+
+/*
+ * Register definitions
+ */
+
+/* clang-format off */
+
+/* MMIO Regs */
+REG32(ALERT_TEST, 0x0u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+
+/* MMIO Mem (Actions) */
+REG32(HALTED, RISCV_DM_HALTED_OFFSET)
+REG32(GOING, RISCV_DM_GOING_OFFSET)
+REG32(RESUMING, RISCV_DM_RESUMING_OFFSET)
+REG32(EXCEPTION, RISCV_DM_EXCEPTION_OFFSET)
+
+/* Shared Mem (R/W access from debugger, R/X from Hart) */
+REG32(WHERETO, 0x300u)
+/*
+ * Abstract cmd registers are used as a private program buffer to implement
+ * abstract commands as semi-hardcoded SW, i.e. not in the debug ROM, w/
+ * PULP_RV_DM_ABSTRACTCMD_COUNT slots
+*/
+REG32(ABSTRACTCMD_0, 0x338u)
+/*
+ * Program buffer registers are used to execute short code sequence and may be
+ * uploaded from an external debugger, w/ PULP_RV_DM_PROGRAM_BUFFER_COUNT slots
+ */
+REG32(PROGRAM_BUFFER_0, PULP_RV_DM_PROGRAM_BUFFER_OFFSET)
+/*
+ * Data address registers is a view to the abstract data used w/ abstract
+ * commands
+ */
+REG32(DATAADDR_0, PULP_RV_DM_DATAADDR_OFFSET)
+
+/* MMIO mem (flags) */
+REG32(FLAGS, RISCV_DM_FLAGS_OFFSET)
+    FIELD(FLAGS, FLAG_GO, 0u, 1u)
+    FIELD(FLAGS, FLAG_RESUME, 1u, 1u)
+
+/* clang-format on */
+
+/*
+ * Macros
+ */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+#define MEM_OFF(_r_) ((_r_) - R_WHERETO)
+
+#define PULP_RV_DM_DMACT_BASE  (A_HALTED)
+#define PULP_RV_DM_DMACT_SIZE  (A_EXCEPTION - A_HALTED + sizeof(uint32_t))
+#define PULP_RV_DM_PROG_BASE   (A_WHERETO)
+#define PULP_RV_DM_PROG_SIZE   0x100u
+#define PULP_RV_DM_DMFLAG_BASE (A_FLAGS)
+#define PULP_RV_DM_DMFLAG_SIZE (PULP_RV_DM_FLAGS_COUNT * sizeof(uint32_t))
+
+/*
+ * Type definitions
+ */
+
+struct PulpRVDMState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion regs; /* MMIO */
+    MemoryRegion mem; /* Container for the following: */
+    MemoryRegion dmact; /* MMIO */
+    MemoryRegion prog; /* ROM device */
+    MemoryRegion dmflag; /* MMIO */
+    MemoryRegion rom; /* ROM */
+
+    qemu_irq *ack_out;
+    IbexIRQ alert;
+
+    uint32_t dmflag_regs[PULP_RV_DM_DMFLAG_SIZE / sizeof(uint32_t)];
+
+    unsigned hart_count;
+    uint64_t idle_bm;
+};
+
+#ifdef DISCARD_REPEATED_IO_TRACES
+typedef struct {
+    uint64_t pc;
+    uint32_t addr;
+    uint32_t value;
+    size_t count;
+} TraceCache;
+#endif /* DISCARD_REPEATED_IO_TRACES */
+
+/*
+ * Constants
+ */
+
+#define R_ABSTRACTCMD_LAST (R_ABSTRACTCMD_0 + PULP_RV_DM_ABSTRACTCMD_COUNT - 1u)
+#define R_PROGRAM_BUFFER_LAST \
+    (R_PROGRAM_BUFFER_0 + PULP_RV_DM_PROGRAM_BUFFER_COUNT - 1u)
+#define R_DATAADDR_LAST (R_DATAADDR_0 + PULP_RV_DM_DATA_COUNT - 1u)
+#define R_FLAGS_0       R_FLAGS
+#define R_FLAGS_LAST    (R_FLAGS_0 + PULP_RV_DM_FLAGS_COUNT - 1u)
+#define PULP_RV_DM_MEM_WORDS \
+    ((R_FLAGS_0 + PULP_RV_DM_FLAGS_COUNT) - R_WHERETO + sizeof(uint32_t))
+
+/**
+ * Debug ROM blob for 2 debug scratch registers.
+ *
+ * Note that entry points should match ROM defined constants, namely:
+ * - PULP_RV_DM_HALT_OFFSET
+ * - PULP_RV_DM_RESUME_OFFSET
+ * - PULP_RV_DM_EXCEPTION_OFFSET
+ * - PULP_RV_DM_WHERETO_OFFSET
+ */
+static const uint32_t DEBUG_ROM[] = {
+    /* clang-format off */
+  /* entry:    HALT_OFFSET */
+    /* 800 */  0x00c0006fu, /* j   80c <_entry>                   */
+  /* resume:   RESUME_OFFSET */
+    /* 804 */  0x07c0006fu, /* j   880 <_resume>                  */
+  /* exception: EXCEPTION */
+    /* 808 */  0x04c0006fu, /* j   854 <_exception>               */
+  /*_entry: */
+    /* 80c */  0x0ff0000fu, /* fence                              */
+    /* 810 */  0x7b241073u, /* csrw    dscratch0,s0               */
+    /* 814 */  0x7b351073u, /* csrw    dscratch1,a0               */
+    /* 818 */  0x00000517u, /* auipc   a0,0x0                     */
+    /* 81c */  0x00c55513u, /* srl     a0,a0,0xc                  */
+    /* 820 */  0x00c51513u, /* sll     a0,a0,0xc                  */
+  /* entry_loop: */
+    /* 824 */  0xf1402473u, /* csrr    s0,mhartid                 */
+    /* 828 */  0x10852023u, /* sw      s0,256(a0)    # HALTED     */
+    /* 82c */  0x00a40433u, /* add     s0,s0,a0                   */
+    /* 830 */  0x40044403u, /* lbu     s0,1024(s0)   # FLAGS      */
+    /* 834 */  0x00147413u, /* and     s0,s0,1                    */
+    /* 838 */  0x02041c63u, /* bnez    s0,870 <going>             */
+    /* 83c */  0xf1402473u, /* csrr    s0,mhartid                 */
+    /* 840 */  0x00a40433u, /* add     s0,s0,a0                   */
+    /* 844 */  0x40044403u, /* lbu     s0,1024(s0)   # FLAGS      */
+    /* 848 */  0x00247413u, /* and     s0,s0,2                    */
+    /* 84c */  0xfa041ce3u, /* bnez    s0,804 <resume>            */
+    /* 850 */  0xfd5ff06fu, /* j       824 <entry_loop>           */
+  /* _exception: */
+    /* 854 */  0x00000517u, /* auipc   a0,0x0                     */
+    /* 858 */  0x00c55513u, /* srl     a0,a0,0xc                  */
+    /* 85c */  0x00c51513u, /* sll     a0,a0,0xc                  */
+    /* 860 */  0x10052623u, /* sw      zero,268(a0)  # EXCEPTION  */
+    /* 864 */  0x7b302573u, /* csrr    a0,dscratch1               */
+    /* 868 */  0x7b202473u, /* csrr    s0,dscratch0               */
+    /* 86c */  0x00100073u, /* ebreak                             */
+  /* going: */
+    /* 870 */  0x10052223u, /* sw      zero,260(a0)  # GOING      */
+    /* 874 */  0x7b302573u, /* csrr    a0,dscratch1               */
+    /* 878 */  0x7b202473u, /* csrr    s0,dscratch0               */
+    /* 87c */  0xa85ff06fu, /* j       300 <whereto> # WHERETO    */
+ /* _resume: */
+    /* 880 */  0xf1402473u, /* csrr    s0,mhartid                 */
+    /* 884 */  0x10852423u, /* sw      s0,264(a0)    # RESUMING   */
+    /* 888 */  0x7b302573u, /* csrr    a0,dscratch1               */
+    /* 88c */  0x7b202473u, /* csrr    s0,dscratch0               */
+    /* 890 */  0x7b200073u, /* dret                               */
+    /* clang-format on */
+};
+
+/*
+ * Device implementation
+ */
+
+static void pulp_rv_dm_load_rom(PulpRVDMState *s)
+{
+    /* do not use rom_add_blob_fixed_as as absolute address is not yet known */
+    void *rom = memory_region_get_ram_ptr(&s->rom);
+    if (!rom) {
+        error_setg(&error_fatal, "cannot load debug ROM");
+        /* linter may not know error_fatal never returns */
+        abort();
+    }
+    memcpy(rom, DEBUG_ROM, sizeof(DEBUG_ROM));
+}
+
+/* NOLINTNEXTLINE */
+static uint64_t pulp_rv_dm_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    (void)opaque;
+    (void)size;
+    /* the unique register is W/O */
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%" HWADDR_PRIx "\n",
+                  __func__, addr);
+
+    return 0u;
+};
+
+static void pulp_rv_dm_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                  unsigned size)
+{
+    PulpRVDMState *s = opaque;
+    uint32_t val32 = (uint32_t)val64;
+    (void)size;
+
+    switch (R32_OFF(addr)) {
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+};
+
+static MemTxResult pulp_rv_dm_dmact_read_with_attrs(
+    void *opaque, hwaddr addr, uint64_t *val64, unsigned size, MemTxAttrs attrs)
+{
+    uint32_t val32;
+    MemTxResult res;
+    (void)size;
+    (void)opaque;
+    (void)attrs;
+
+    addr += PULP_RV_DM_DMACT_BASE;
+
+    if (addr & 0x1u) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad alignment 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        return MEMTX_ERROR;
+    }
+
+    switch (R32_OFF(addr)) {
+    case R_HALTED:
+    case R_GOING:
+    case R_RESUMING:
+    case R_EXCEPTION:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        val32 = 0u;
+        res = MEMTX_OK;
+        break;
+    default:
+        res = MEMTX_DECODE_ERROR;
+        val32 = 0;
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+
+    if (MEMTX_OK == res) {
+        *val64 = val32;
+    }
+
+    return res;
+};
+
+static MemTxResult pulp_rv_dm_dmact_write_with_attrs(
+    void *opaque, hwaddr addr, uint64_t val64, unsigned size, MemTxAttrs attrs)
+{
+    PulpRVDMState *s = opaque;
+    uint32_t val32 = (uint32_t)val64;
+    MemTxResult res;
+    uint64_t pc = attrs.unspecified ? ibex_get_current_pc() : 0u;
+    (void)size;
+
+    addr += PULP_RV_DM_DMACT_BASE;
+
+#ifdef DISCARD_REPEATED_IO_TRACES
+    static TraceCache trace_cache;
+
+    if (ABS((int)(trace_cache.pc) - (int)(pc)) >= DISTANCE_ACCESS_IO_TRACES ||
+        trace_cache.addr != addr || trace_cache.value != val32) {
+#endif /* DISCARD_REPEATED_IO_TRACES */
+        trace_pulp_rv_dm_mem_write((unsigned int)addr, val32, pc);
+#ifdef DISCARD_REPEATED_IO_TRACES
+        trace_cache.count = 1;
+    } else {
+        trace_cache.count += 1;
+    }
+    trace_cache.pc = pc;
+    trace_cache.addr = addr;
+    trace_cache.value = val32;
+#endif /* DISCARD_REPEATED_IO_TRACES */
+
+    switch (R32_OFF(addr)) {
+    case R_HALTED:
+        if (val32 < s->hart_count) {
+            if (!(s->idle_bm & (1u << val32))) {
+                /*
+                 * use a local cache to avoid flooding the DM with the park loop
+                 * running crazy
+                 */
+                qemu_set_irq(s->ack_out[ACK_HALTED], (int)val32);
+                s->idle_bm |= (1u << val32);
+            }
+        }
+        res = MEMTX_OK;
+        break;
+    case R_GOING:
+        s->idle_bm &= ~(1u << val32);
+        qemu_set_irq(s->ack_out[ACK_GOING], 1u);
+        res = MEMTX_OK;
+        break;
+    case R_RESUMING:
+        if (val32 < s->hart_count) {
+            s->idle_bm &= ~(1u << val32);
+            qemu_set_irq(s->ack_out[ACK_RESUMING], (int)val32);
+        }
+        res = MEMTX_OK;
+        break;
+    case R_EXCEPTION:
+        qemu_set_irq(s->ack_out[ACK_EXCEPTION], 1u);
+        res = MEMTX_OK;
+        break;
+    default:
+        res = MEMTX_DECODE_ERROR;
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+
+    return res;
+};
+
+static MemTxResult pulp_rv_dm_dmflag_read_with_attrs(
+    void *opaque, hwaddr addr, uint64_t *val64, unsigned size, MemTxAttrs attrs)
+{
+    PulpRVDMState *s = opaque;
+    uint32_t val32;
+    MemTxResult res;
+    (void)size;
+    (void)attrs;
+
+    addr += PULP_RV_DM_DMFLAG_BASE;
+
+    unsigned reg = R32_OFF(addr);
+
+    /* NOLINTNEXTLINE */
+    switch (reg) {
+    case R_FLAGS_0 ... R_FLAGS_LAST:
+        val32 = s->dmflag_regs[reg - R_FLAGS_0];
+        res = MEMTX_OK;
+        break;
+    default:
+        res = MEMTX_DECODE_ERROR;
+        val32 = 0;
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+
+    if (MEMTX_OK == res) {
+        *val64 = val32;
+    }
+
+    return res;
+};
+
+static MemTxResult pulp_rv_dm_dmflag_write_with_attrs(
+    void *opaque, hwaddr addr, uint64_t val64, unsigned size, MemTxAttrs attrs)
+{
+    PulpRVDMState *s = opaque;
+    uint32_t val32 = (uint32_t)val64;
+    MemTxResult res;
+    (void)size;
+
+    addr += PULP_RV_DM_DMFLAG_BASE;
+
+    unsigned reg = R32_OFF(addr);
+
+    /* NOLINTNEXTLINE */
+    switch (reg) {
+    case R_FLAGS_0 ... R_FLAGS_LAST:
+        if ((!attrs.unspecified) &&
+            (attrs.requester_id == PULP_RV_DM_REQUESTER_ID)) {
+            /* dm_access */
+            s->dmflag_regs[reg - R_FLAGS_0] = val32;
+        } else {
+            /* other (hart...) access */
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: R/O register 0x%" HWADDR_PRIx "\n", __func__,
+                          addr);
+        }
+        res = MEMTX_OK;
+        break;
+    default:
+        res = MEMTX_DECODE_ERROR;
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        break;
+    }
+
+    return res;
+};
+
+static const MemoryRegionOps pulp_rv_dm_regs_ops = {
+    .read = &pulp_rv_dm_regs_read,
+    .write = &pulp_rv_dm_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const MemoryRegionOps pulp_rv_dm_dmact_ops = {
+    .read_with_attrs = &pulp_rv_dm_dmact_read_with_attrs,
+    .write_with_attrs = &pulp_rv_dm_dmact_write_with_attrs,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const MemoryRegionOps pulp_rv_dm_dmflag_ops = {
+    .read_with_attrs = &pulp_rv_dm_dmflag_read_with_attrs,
+    .write_with_attrs = &pulp_rv_dm_dmflag_write_with_attrs,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static void pulp_rv_dm_reset(DeviceState *dev)
+{
+    PulpRVDMState *s = PULP_RV_DM(dev);
+
+    ibex_irq_set(&s->alert, false);
+
+    memset(memory_region_get_ram_ptr(&s->prog), 0, PULP_RV_DM_PROG_SIZE);
+    memset(s->dmflag_regs, 0, sizeof(s->dmflag_regs));
+
+    s->idle_bm = 0;
+}
+
+static void pulp_rv_dm_init(Object *obj)
+{
+    PulpRVDMState *s = PULP_RV_DM(obj);
+
+    MachineState *ms = MACHINE(qdev_get_machine());
+    unsigned max_cpus = ms->smp.max_cpus;
+    s->hart_count = MIN(max_cpus, 64u);
+
+    /* Top-level container */
+    memory_region_init(&s->mem, obj, TYPE_PULP_RV_DM, 0x1000);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mem);
+
+    /* Top-level MMIO */
+    memory_region_init_io(&s->regs, obj, &pulp_rv_dm_regs_ops, s,
+                          TYPE_PULP_RV_DM ".regs", PULP_RV_DM_REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->regs);
+
+    /* Mem container content */
+    memory_region_init_io(&s->dmact, obj, &pulp_rv_dm_dmact_ops, s,
+                          TYPE_PULP_RV_DM ".act", PULP_RV_DM_DMACT_SIZE);
+    memory_region_add_subregion(&s->mem, PULP_RV_DM_DMACT_BASE, &s->dmact);
+
+    memory_region_init_ram_nomigrate(&s->prog, obj, TYPE_PULP_RV_DM ".prog",
+                                     PULP_RV_DM_PROG_SIZE, &error_fatal);
+    memory_region_add_subregion(&s->mem, PULP_RV_DM_PROG_BASE, &s->prog);
+
+    memory_region_init_io(&s->dmflag, obj, &pulp_rv_dm_dmflag_ops, s,
+                          TYPE_PULP_RV_DM ".flag", PULP_RV_DM_DMFLAG_SIZE);
+    memory_region_add_subregion(&s->mem, PULP_RV_DM_DMFLAG_BASE, &s->dmflag);
+    s->dmflag.disable_reentrancy_guard = true;
+
+    memory_region_init_rom_nomigrate(&s->rom, obj, TYPE_PULP_RV_DM ".rom",
+                                     PULP_RV_DM_ROM_SIZE, &error_abort);
+    memory_region_add_subregion(&s->mem, PULP_RV_DM_ROM_BASE, &s->rom);
+
+    s->ack_out = g_new0(qemu_irq, ACK_COUNT);
+    qdev_init_gpio_out_named(DEVICE(obj), s->ack_out, PULP_RV_DM_ACK_OUT_LINES,
+                             ACK_COUNT);
+
+    pulp_rv_dm_load_rom(s);
+
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+}
+
+static void pulp_rv_dm_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    device_class_set_legacy_reset(dc, &pulp_rv_dm_reset);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static const TypeInfo pulp_rv_dm_info = {
+    .name = TYPE_PULP_RV_DM,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(PulpRVDMState),
+    .instance_init = &pulp_rv_dm_init,
+    .class_init = &pulp_rv_dm_class_init,
+};
+
+static void pulp_rv_dm_register_types(void)
+{
+    type_register_static(&pulp_rv_dm_info);
+}
+
+type_init(pulp_rv_dm_register_types);
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index eeb9243898e9c..cc21b7b489eb4 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -409,3 +409,7 @@ ivshmem_flat_interrupt_peer(uint16_t peer_id, uint16_t vector_id) "Interrupting
 i2c_echo_event(const char *id, const char *event) "%s: %s"
 i2c_echo_recv(const char *id, uint8_t data) "%s: recv 0x%02" PRIx8
 i2c_echo_send(const char *id, uint8_t data) "%s: send 0x%02" PRIx8
+
+# pulp_rv_dm.c
+pulp_rv_dm_mem_read_out(unsigned int addr, uint64_t val, uint64_t pc) "addr=0x%02x, val=0x%" PRIx64 ", pc=0x%" PRIx64
+pulp_rv_dm_mem_write(unsigned int addr, uint64_t val, uint64_t pc) "addr=0x%02x, val=0x%" PRIx64 ", pc=0x%" PRIx64
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
index 4370c14ef1667..89dc49d056767 100644
--- a/hw/misc/unimp.c
+++ b/hw/misc/unimp.c
@@ -22,9 +22,16 @@ static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
 {
     UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
 
+    if (s->warn_once && s->r_warned) {
+        return 0;
+    }
+
     qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read  "
                   "(size %d, offset 0x%0*" HWADDR_PRIx ")\n",
                   s->name, size, s->offset_fmt_width, offset);
+
+    s->r_warned = true;
+
     return 0;
 }
 
@@ -33,10 +40,16 @@ static void unimp_write(void *opaque, hwaddr offset,
 {
     UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
 
+    if (s->warn_once && s->w_warned) {
+        return;
+    }
+
     qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
                   "(size %d, offset 0x%0*" HWADDR_PRIx
                   ", value 0x%0*" PRIx64 ")\n",
                   s->name, size, s->offset_fmt_width, offset, size << 1, value);
+
+    s->w_warned = true;
 }
 
 static const MemoryRegionOps unimp_ops = {
@@ -73,6 +86,7 @@ static void unimp_realize(DeviceState *dev, Error **errp)
 static const Property unimp_properties[] = {
     DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0),
     DEFINE_PROP_STRING("name", UnimplementedDeviceState, name),
+    DEFINE_PROP_BOOL("warn-once", UnimplementedDeviceState, warn_once, false),
 };
 
 static void unimp_class_init(ObjectClass *klass, const void *data)
diff --git a/hw/opentitan/Kconfig b/hw/opentitan/Kconfig
new file mode 100644
index 0000000000000..3a98d8e0cb931
--- /dev/null
+++ b/hw/opentitan/Kconfig
@@ -0,0 +1,228 @@
+# OpenTitan devices
+
+config OT_ADDRESS_SPACE
+    bool
+
+config OT_AES
+    select OT_KEY_SINK
+    select OT_PRNG
+    bool
+
+config OT_ALERT
+    bool
+
+config OT_AON_TIMER
+    bool
+
+config OT_AST_DJ
+    select IBEX_CLOCK_SRC
+    select OT_CLOCK_CTRL
+    select OT_NOISE_SRC
+    bool
+
+config OT_AST_EG
+    select IBEX_CLOCK_SRC
+    select OT_CLOCK_CTRL
+    select OT_NOISE_SRC
+    bool
+
+config OT_CLKMGR
+    select IBEX_CLOCK_SRC
+    bool
+
+config OT_CLOCK_CTRL
+    bool
+
+config OT_COMMON
+    bool
+
+config OT_CSRNG
+    bool
+
+config OT_DEV_PROXY
+    bool
+
+config OT_DM_TL
+    select RISCV_DEBUG
+    bool
+
+config OT_DMA
+    select OT_ADDRESS_SPACE
+    bool
+
+config OT_EDN
+    bool
+
+config OT_EG_PAD_RING
+    bool
+
+config OT_ENTROPY_SRC
+    select OT_NOISE_SRC
+    select OT_OTP_IF
+    bool
+
+config OT_FLASH
+    bool
+
+config OT_GPIO_DJ
+    bool
+
+config OT_GPIO_EG
+    bool
+
+config OT_HMAC
+    bool
+
+config OT_I2C
+    imply I2C_ECHO
+    imply DS1338
+    select I2C
+    bool
+
+config OT_I2C_HOST_PROXY
+    select I2C
+    bool
+
+config OT_IBEX_WRAPPER
+    select OT_VMAPPER
+    bool
+
+config OT_KEY_SINK
+    bool
+
+config OT_KEYMGR
+    select OT_KEY_SINK
+    select OT_LC_CTRL
+    select OT_OTP_IF
+    select OT_ROM_CTRL
+    bool
+
+config OT_KEYMGR_DPE
+    select OT_KEY_SINK
+    select OT_LC_CTRL
+    select OT_ROM_CTRL
+    bool
+
+config OT_KMAC
+    select OT_KEY_SINK
+    bool
+
+config OT_LC_CTRL
+    select OT_OTP_IF
+    bool
+
+config OT_MBX
+    select OT_COMMON
+    bool
+
+config OT_NOISE_SRC
+    bool
+
+config OT_OTBN
+    select OT_KEY_SINK
+    select OT_BIGNUMBER
+    bool
+
+config OT_OTP_BE_IF
+    bool
+
+config OT_OTP_DJ
+    select OT_OTP_ENGINE
+    select OT_OTP_IF
+    select OT_OTP_IMPL_IF
+    select OT_PRESENT
+    bool
+
+config OT_OTP_EG
+    select OT_OTP_ENGINE
+    select OT_OTP_IF
+    select OT_OTP_IMPL_IF
+    select OT_PRESENT
+    bool
+
+config OT_OTP_ENGINE
+    select OT_EDN
+    select OT_OTP_IF
+    select OT_OTP_IMPL_IF
+    select OT_PRESENT
+    bool
+
+config OT_OTP_IF
+    bool
+
+config OT_OTP_IMPL_IF
+    bool
+
+config OT_OTP_OT_BE
+    select OT_OTP_BE_IF
+    select OT_OTP_IF
+    bool
+
+config OT_PINMUX_DJ
+    bool
+
+config OT_PINMUX_EG
+    bool
+
+config OT_PLIC_EXT
+    bool
+
+config OT_PRESENT
+    bool
+
+config OT_PRINCE
+    bool
+
+config OT_PRNG
+    bool
+
+config OT_PWRMGR
+    select OT_CLOCK_CTRL
+    bool
+
+config OT_ROM_CTRL
+    bool
+    select OT_COMMON
+    select OT_PRINCE
+
+config OT_RSTMGR
+    bool
+
+config OT_SENSOR_EG
+    bool
+
+config OT_SOC_PROXY
+    bool
+
+config OT_SOC_DBG_CTRL
+    bool
+
+config OT_SPI_DEVICE
+    bool
+    select OT_SPI_HOST
+
+config OT_SPI_HOST
+    bool
+    select SSI
+
+config OT_SRAM_CTRL
+    select OT_PRESENT
+    select OT_OTP_IF
+    bool
+
+config OT_TIMER
+    bool
+
+config OT_UART
+    bool
+
+config OT_USBDEV
+    bool
+
+config OT_UNIMP
+    bool
+
+config OT_VMAPPER
+    bool
+
+source otbn/Kconfig
diff --git a/hw/opentitan/meson.build b/hw/opentitan/meson.build
new file mode 100644
index 0000000000000..2d557ac037508
--- /dev/null
+++ b/hw/opentitan/meson.build
@@ -0,0 +1,67 @@
+# TomCrypt dependency
+
+libtomcrypt_dep = subproject('libtomcrypt').get_variable('libtomcrypt_dep')
+
+# OpenTitan devices
+
+system_ss.add(when: 'CONFIG_OT_ADDRESS_SPACE', if_true: files('ot_address_space.c'))
+system_ss.add(when: 'CONFIG_OT_AES', if_true: [files('ot_aes.c'), libtomcrypt_dep])
+system_ss.add(when: 'CONFIG_OT_ALERT', if_true: files('ot_alert.c'))
+system_ss.add(when: 'CONFIG_OT_AON_TIMER', if_true: files('ot_aon_timer.c'))
+system_ss.add(when: 'CONFIG_OT_AST_DJ', if_true: files('ot_ast_dj.c'))
+system_ss.add(when: 'CONFIG_OT_AST_EG', if_true: files('ot_ast_eg.c'))
+system_ss.add(when: 'CONFIG_OT_CLKMGR', if_true: files('ot_clkmgr.c'))
+system_ss.add(when: 'CONFIG_OT_CLOCK_CTRL', if_true: files('ot_clock_ctrl.c'))
+system_ss.add(when: 'CONFIG_OT_COMMON', if_true: files('ot_common.c'))
+system_ss.add(when: 'CONFIG_OT_CSRNG', if_true: [files('ot_csrng.c'), libtomcrypt_dep])
+system_ss.add(when: 'CONFIG_OT_DEV_PROXY', if_true: files('ot_dev_proxy.c'))
+system_ss.add(when: 'CONFIG_OT_DM_TL', if_true: files('ot_dm_tl.c'))
+system_ss.add(when: 'CONFIG_OT_DMA', if_true: [files('ot_dma.c'), libtomcrypt_dep])
+system_ss.add(when: 'CONFIG_OT_EDN', if_true: files('ot_edn.c'))
+system_ss.add(when: 'CONFIG_OT_EG_PAD_RING', if_true: files('ot_eg_pad_ring.c'))
+system_ss.add(when: 'CONFIG_OT_ENTROPY_SRC', if_true: [files('ot_entropy_src.c'), libtomcrypt_dep])
+system_ss.add(when: 'CONFIG_OT_FLASH', if_true: files('ot_flash.c'))
+system_ss.add(when: 'CONFIG_OT_GPIO_DJ', if_true: files('ot_gpio_dj.c'))
+system_ss.add(when: 'CONFIG_OT_GPIO_EG', if_true: files('ot_gpio_eg.c'))
+system_ss.add(when: 'CONFIG_OT_HMAC', if_true: [files('ot_hmac.c'), libtomcrypt_dep])
+system_ss.add(when: 'CONFIG_OT_I2C', if_true: files('ot_i2c.c'))
+system_ss.add(when: 'CONFIG_OT_I2C_HOST_PROXY', if_true: files('ot_i2c_host_proxy.c'))
+system_ss.add(when: 'CONFIG_OT_IBEX_WRAPPER', if_true: files('ot_ibex_wrapper.c'))
+system_ss.add(when: 'CONFIG_OT_KEY_SINK', if_true: files('ot_key_sink.c'))
+system_ss.add(when: 'CONFIG_OT_KEYMGR', if_true: files('ot_keymgr.c'))
+system_ss.add(when: 'CONFIG_OT_KEYMGR_DPE', if_true: files('ot_keymgr_dpe.c'))
+system_ss.add(when: 'CONFIG_OT_KMAC', if_true: [files('ot_kmac.c'), libtomcrypt_dep])
+system_ss.add(when: 'CONFIG_OT_LC_CTRL', if_true: files('ot_lc_ctrl.c'))
+system_ss.add(when: 'CONFIG_OT_MBX', if_true: files('ot_mbx.c'))
+system_ss.add(when: 'CONFIG_OT_NOISE_SRC', if_true: files('ot_noise_src.c'))
+system_ss.add(when: 'CONFIG_OT_OTBN', if_true: files('ot_otbn.c'))
+system_ss.add(when: 'CONFIG_OT_OTP_BE_IF', if_true: files('ot_otp_be_if.c'))
+system_ss.add(when: 'CONFIG_OT_OTP_DJ', if_true: files('ot_otp_dj.c'))
+system_ss.add(when: 'CONFIG_OT_OTP_EG', if_true: files('ot_otp_eg.c'))
+system_ss.add(when: 'CONFIG_OT_OTP_ENGINE', if_true: files('ot_otp_engine.c'))
+system_ss.add(when: 'CONFIG_OT_OTP_IF', if_true: files('ot_otp_if.c'))
+system_ss.add(when: 'CONFIG_OT_OTP_IMPL_IF', if_true: files('ot_otp_impl_if.c'))
+system_ss.add(when: 'CONFIG_OT_OTP_OT_BE', if_true: files('ot_otp_ot_be.c'))
+system_ss.add(when: 'CONFIG_OT_PINMUX_EG', if_true: files('ot_pinmux_eg.c'))
+system_ss.add(when: 'CONFIG_OT_PINMUX_DJ', if_true: files('ot_pinmux_dj.c'))
+system_ss.add(when: 'CONFIG_OT_PLIC_EXT', if_true: files('ot_plic_ext.c'))
+system_ss.add(when: 'CONFIG_OT_PRESENT', if_true: files('ot_present.c'))
+system_ss.add(when: 'CONFIG_OT_PRINCE', if_true: files('ot_prince.c'))
+system_ss.add(when: 'CONFIG_OT_PRNG', if_true: files('ot_prng.c'))
+system_ss.add(when: 'CONFIG_OT_PWRMGR', if_true: files('ot_pwrmgr.c'))
+system_ss.add(when: 'CONFIG_OT_ROM_CTRL', if_true: files('ot_rom_ctrl.c', 'ot_rom_ctrl_img.c'))
+system_ss.add(when: 'CONFIG_OT_RSTMGR', if_true: files('ot_rstmgr.c'))
+system_ss.add(when: 'CONFIG_OT_SENSOR_EG', if_true: files('ot_sensor_eg.c'))
+system_ss.add(when: 'CONFIG_OT_SOC_PROXY', if_true: files('ot_soc_proxy.c'))
+system_ss.add(when: 'CONFIG_OT_SOC_DBG_CTRL', if_true: files('ot_soc_dbg_ctrl.c'))
+system_ss.add(when: 'CONFIG_OT_SPI_DEVICE', if_true: files('ot_spi_device.c'))
+system_ss.add(when: 'CONFIG_OT_SPI_HOST', if_true: files('ot_spi_host.c'))
+system_ss.add(when: 'CONFIG_OT_SRAM_CTRL', if_true: files('ot_sram_ctrl.c'))
+system_ss.add(when: 'CONFIG_OT_TIMER', if_true: files('ot_timer.c'))
+system_ss.add(when: 'CONFIG_OT_UART', if_true: files('ot_uart.c'))
+system_ss.add(when: 'CONFIG_OT_UNIMP', if_true: files('ot_unimp.c'))
+system_ss.add(when: 'CONFIG_OT_USBDEV', if_true: files('ot_usbdev.c'))
+
+riscv_ss.add(when: 'CONFIG_OT_VMAPPER', if_true: files('ot_vmapper.c'))
+
+subdir('otbn')
diff --git a/hw/opentitan/ot_address_space.c b/hw/opentitan/ot_address_space.c
new file mode 100644
index 0000000000000..45b8bfebfed74
--- /dev/null
+++ b/hw/opentitan/ot_address_space.c
@@ -0,0 +1,77 @@
+/*
+ * QEMU OpenTitan Address Space container
+ *
+ * Copyright (c) 2023 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: for now, only a minimalist subset of Analog Sensor Top device is
+ *       implemented in order to enable OpenTitan's ROM boot to progress
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_address_space.h"
+#include "trace.h"
+
+struct OtAddressSpaceState {
+    Object parent_obj;
+
+    AddressSpace *as;
+};
+
+/* -------------------------------------------------------------------------- */
+/* Public API */
+/* -------------------------------------------------------------------------- */
+
+AddressSpace *ot_address_space_get(OtAddressSpaceState *s)
+{
+    if (!s->as) {
+        error_setg(&error_fatal, "Address space for %s not defined\n",
+                   object_get_canonical_path_component(OBJECT(s)));
+    }
+
+    return s->as;
+}
+
+void ot_address_space_set(OtAddressSpaceState *s, AddressSpace *as)
+{
+    s->as = as;
+}
+
+/* -------------------------------------------------------------------------- */
+/* Private implementation */
+/* -------------------------------------------------------------------------- */
+
+static const TypeInfo ot_address_space_info = {
+    .name = TYPE_OT_ADDRESS_SPACE,
+    .parent = TYPE_OBJECT,
+    .instance_size = sizeof(OtAddressSpaceState),
+};
+
+static void ot_address_space_register_types(void)
+{
+    type_register_static(&ot_address_space_info);
+}
+
+type_init(ot_address_space_register_types);
diff --git a/hw/opentitan/ot_aes.c b/hw/opentitan/ot_aes.c
new file mode 100644
index 0000000000000..c336773364963
--- /dev/null
+++ b/hw/opentitan/ot_aes.c
@@ -0,0 +1,1521 @@
+/*
+ * QEMU OpenTitan AES device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitmap.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_aes.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_clkmgr.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_key_sink.h"
+#include "hw/opentitan/ot_prng.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "tomcrypt.h"
+#include "trace.h"
+
+#undef DEBUG_AES
+
+#define PARAM_NUM_REGS_KEY  8u
+#define PARAM_NUM_REGS_IV   4u
+#define PARAM_NUM_REGS_DATA 4u
+#define PARAM_NUM_ALERTS    2u
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x0u)
+    SHARED_FIELD(ALERT_RECOV_CTRL_UPDATE_ERR, 0u, 1u)
+    SHARED_FIELD(ALERT_FATAL_FAULT, 1u, 1u)
+REG32(KEY_SHARE0_0, 0x4u)
+REG32(KEY_SHARE0_1, 0x8u)
+REG32(KEY_SHARE0_2, 0xcu)
+REG32(KEY_SHARE0_3, 0x10u)
+REG32(KEY_SHARE0_4, 0x14u)
+REG32(KEY_SHARE0_5, 0x18u)
+REG32(KEY_SHARE0_6, 0x1cu)
+REG32(KEY_SHARE0_7, 0x20u)
+REG32(KEY_SHARE1_0, 0x24u)
+REG32(KEY_SHARE1_1, 0x28u)
+REG32(KEY_SHARE1_2, 0x2cu)
+REG32(KEY_SHARE1_3, 0x30u)
+REG32(KEY_SHARE1_4, 0x34u)
+REG32(KEY_SHARE1_5, 0x38u)
+REG32(KEY_SHARE1_6, 0x3cu)
+REG32(KEY_SHARE1_7, 0x40u)
+REG32(IV_0, 0x44u)
+REG32(IV_1, 0x48u)
+REG32(IV_2, 0x4cu)
+REG32(IV_3, 0x50u)
+REG32(DATA_IN_0, 0x54u)
+REG32(DATA_IN_1, 0x58u)
+REG32(DATA_IN_2, 0x5cu)
+REG32(DATA_IN_3, 0x60u)
+REG32(DATA_OUT_0, 0x64u)
+REG32(DATA_OUT_1, 0x68u)
+REG32(DATA_OUT_2, 0x6cu)
+REG32(DATA_OUT_3, 0x70u)
+REG32(CTRL_SHADOWED, 0x74u)
+    FIELD(CTRL_SHADOWED, OPERATION, 0u, 2u)
+    FIELD(CTRL_SHADOWED, MODE, 2u, 6u)
+    FIELD(CTRL_SHADOWED, KEY_LEN, 8u, 3u)
+    FIELD(CTRL_SHADOWED, SIDELOAD, 11u, 1u)
+    FIELD(CTRL_SHADOWED, PRNG_RESEED_RATE, 12u, 3u)
+    FIELD(CTRL_SHADOWED, MANUAL_OPERATION, 15u, 1u)
+    FIELD(CTRL_SHADOWED, FORCE_ZERO_MASKS, 16u, 1u)
+REG32(CTRL_AUX_SHADOWED, 0x78u)
+    FIELD(CTRL_AUX_SHADOWED, KEY_TOUCH_FORCES_RESEED, 0u, 1u)
+    FIELD(CTRL_AUX_SHADOWED, FORCE_MASKS, 1u, 1u)
+REG32(CTRL_AUX_REGWEN, 0x7cu)
+    FIELD(CTRL_AUX_REGWEN, CTRL_AUX_REGWEN, 0u, 1u)
+REG32(TRIGGER, 0x80u)
+    FIELD(TRIGGER, START, 0u, 1u)
+    FIELD(TRIGGER, KEY_IV_DATA_IN_CLEAR, 1u, 1u)
+    FIELD(TRIGGER, DATA_OUT_CLEAR, 2u, 1u)
+    FIELD(TRIGGER, PRNG_RESEED, 3u, 1u)
+REG32(STATUS, 0x84u)
+    FIELD(STATUS, IDLE, 0u, 1u)
+    FIELD(STATUS, STALL, 1u, 1u)
+    FIELD(STATUS, OUTPUT_LOST, 2u, 1u)
+    FIELD(STATUS, OUTPUT_VALID, 3u, 1u)
+    FIELD(STATUS, INPUT_READY, 4u, 1u)
+    FIELD(STATUS, ALERT_RECOV_CTRL_UPDATE_ERR, 5u, 1u)
+    FIELD(STATUS, ALERT_FATAL_FAULT, 6u, 1u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define OT_AES_KEYSHARE_BM_MASK ((1u << (PARAM_NUM_REGS_KEY * 2u)) - 1u)
+#define OT_AES_IV_BM_MASK       ((1u << (PARAM_NUM_REGS_IV)) - 1u)
+#define OT_AES_DATA_BM_MASK     ((1u << (PARAM_NUM_REGS_DATA)) - 1u)
+
+#define OT_AES_ALERT_STATUS_OFFSET \
+    (R_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_SHIFT - \
+     ALERT_RECOV_CTRL_UPDATE_ERR_SHIFT)
+
+#define OT_AES_DATA_SIZE (PARAM_NUM_REGS_DATA * sizeof(uint32_t))
+#define OT_AES_IV_SIZE   (PARAM_NUM_REGS_IV * sizeof(uint32_t))
+
+static_assert(OT_AES_KEY_SIZE == (PARAM_NUM_REGS_KEY * sizeof(uint32_t)),
+              "Invalid key size");
+
+#define OT_AES_CLOCK_ACTIVE "clock-active"
+#define OT_AES_CLOCK_INPUT  "clock-in"
+
+/* arbitrary value long enough to give back execution to vCPU */
+#define OT_AES_RETARD_DELAY_NS 10000u /* 10 us */
+
+/* size of the debug buffer: hex key + NUL + extra */
+#define AES_DEBUG_HEXBUF_SIZE (OT_AES_DATA_SIZE * 2u + 4u)
+
+#define R_LAST_REG (R_STATUS)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(KEY_SHARE0_0),
+    REG_NAME_ENTRY(KEY_SHARE0_1),
+    REG_NAME_ENTRY(KEY_SHARE0_2),
+    REG_NAME_ENTRY(KEY_SHARE0_3),
+    REG_NAME_ENTRY(KEY_SHARE0_4),
+    REG_NAME_ENTRY(KEY_SHARE0_5),
+    REG_NAME_ENTRY(KEY_SHARE0_6),
+    REG_NAME_ENTRY(KEY_SHARE0_7),
+    REG_NAME_ENTRY(KEY_SHARE1_0),
+    REG_NAME_ENTRY(KEY_SHARE1_1),
+    REG_NAME_ENTRY(KEY_SHARE1_2),
+    REG_NAME_ENTRY(KEY_SHARE1_3),
+    REG_NAME_ENTRY(KEY_SHARE1_4),
+    REG_NAME_ENTRY(KEY_SHARE1_5),
+    REG_NAME_ENTRY(KEY_SHARE1_6),
+    REG_NAME_ENTRY(KEY_SHARE1_7),
+    REG_NAME_ENTRY(IV_0),
+    REG_NAME_ENTRY(IV_1),
+    REG_NAME_ENTRY(IV_2),
+    REG_NAME_ENTRY(IV_3),
+    REG_NAME_ENTRY(DATA_IN_0),
+    REG_NAME_ENTRY(DATA_IN_1),
+    REG_NAME_ENTRY(DATA_IN_2),
+    REG_NAME_ENTRY(DATA_IN_3),
+    REG_NAME_ENTRY(DATA_OUT_0),
+    REG_NAME_ENTRY(DATA_OUT_1),
+    REG_NAME_ENTRY(DATA_OUT_2),
+    REG_NAME_ENTRY(DATA_OUT_3),
+    REG_NAME_ENTRY(CTRL_SHADOWED),
+    REG_NAME_ENTRY(CTRL_AUX_SHADOWED),
+    REG_NAME_ENTRY(CTRL_AUX_REGWEN),
+    REG_NAME_ENTRY(TRIGGER),
+    REG_NAME_ENTRY(STATUS),
+};
+#undef REG_NAME_ENTRY
+
+static const char *OT_AES_MODE_NAMES[6u] = {
+    "NONE", "ECB", "CBC", "CFB", "OFB", "CTR",
+};
+
+#define OT_AES_KEY_DWORD_COUNT (OT_AES_KEY_SIZE / sizeof(uint64_t))
+#define OT_AES_IV_DWORD_COUNT  (OT_AES_IV_SIZE / sizeof(uint64_t))
+
+typedef struct OtAESRegisters {
+    /* public registers */
+    uint32_t keyshare[PARAM_NUM_REGS_KEY * 2u]; /* wo */
+    uint32_t iv[PARAM_NUM_REGS_IV]; /* rw */
+    uint32_t data_in[PARAM_NUM_REGS_DATA]; /* wo */
+    uint32_t data_out[PARAM_NUM_REGS_DATA]; /* ro */
+    OtShadowReg ctrl;
+    OtShadowReg ctrl_aux;
+    uint32_t ctrl_aux_regwen;
+    uint32_t trigger;
+    uint32_t status;
+
+    /* implementation */
+    DECLARE_BITMAP(keyshare_bm, (uint64_t)(PARAM_NUM_REGS_KEY * 2u));
+    DECLARE_BITMAP(iv_bm, PARAM_NUM_REGS_IV);
+    DECLARE_BITMAP(data_in_bm, PARAM_NUM_REGS_DATA);
+    DECLARE_BITMAP(data_out_bm, PARAM_NUM_REGS_DATA);
+    uint32_t key[PARAM_NUM_REGS_KEY];
+    bool data_out_rdy; /* AES output data exist, not yet published */
+} OtAESRegisters;
+
+typedef struct OtAESContext {
+    union {
+        symmetric_ECB ecb;
+        symmetric_CFB cfb;
+        symmetric_OFB ofb;
+        symmetric_CBC cbc;
+        symmetric_CTR ctr;
+    };
+    uint64_t key[OT_AES_KEY_DWORD_COUNT];
+    uint64_t iv[OT_AES_IV_DWORD_COUNT];
+    uint8_t src[OT_AES_DATA_SIZE];
+    uint8_t dst[OT_AES_DATA_SIZE];
+    bool key_ready; /* Key has been fully loaded */
+    bool iv_ready; /* IV has been fully loaded */
+    bool di_full; /* Input DATA FIFO fully filled */
+    bool do_full; /* Output DATA FIFO not empty */
+    int aes_cipher; /* AES handle for tomcrypt */
+} OtAESContext;
+
+typedef struct OtAESEDN {
+    OtEDNState *device;
+    uint8_t ep;
+    bool connected;
+    bool scheduled;
+} OtAESEDN;
+
+typedef struct {
+    uint64_t share0[OT_AES_KEY_DWORD_COUNT];
+    uint64_t share1[OT_AES_KEY_DWORD_COUNT];
+    bool valid;
+} OtAESKey;
+
+typedef enum {
+    AES_NONE,
+    AES_ECB,
+    AES_CBC,
+    AES_CFB,
+    AES_OFB,
+    AES_CTR,
+} OtAESMode;
+
+struct OtAESState {
+    SysBusDevice parent_obj;
+    MemoryRegion mmio;
+    IbexIRQ alerts[PARAM_NUM_ALERTS];
+    IbexIRQ clock_active;
+    QEMUBH *process_bh;
+    QEMUTimer *retard_timer; /* only used with disabled fast-mode */
+
+    OtAESRegisters *regs;
+    OtAESContext *ctx;
+    OtAESKey *sl_key;
+    OtAESEDN edn;
+    OtPrngState *prng;
+    const char *clock_src_name; /* IRQ name once connected */
+    char *hexstr;
+    unsigned pclk; /* Current input clock */
+    unsigned reseed_count;
+    bool fast_mode;
+
+    char *ot_id;
+    char *clock_name;
+    DeviceState *clock_src;
+};
+
+struct OtAESClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+#ifdef DEBUG_AES
+#define trace_ot_aes_buf(_s_, _a_, _m_, _b_) \
+    trace_ot_aes_buffer((_s_)->ot_id, (_a_), (_m_), \
+                        ot_common_uhexdump((const uint8_t *)(_b_), \
+                                           OT_AES_DATA_SIZE, false, \
+                                           (_s_)->hexstr, \
+                                           AES_DEBUG_HEXBUF_SIZE))
+#define trace_ot_aes_key(_s_, _a_, _b_, _l_) \
+    trace_ot_aes_buffer((_s_)->ot_id, (_a_), "key", \
+                        ot_common_uhexdump((const uint8_t *)(_b_), (_l_), \
+                                           false, (_s_)->hexstr, \
+                                           AES_DEBUG_HEXBUF_SIZE))
+#define trace_ot_aes_iv(_s_, _a_, _b_) \
+    trace_ot_aes_buffer((_s_)->ot_id, (_a_), "iv", \
+                        ot_common_uhexdump((const uint8_t *)(_b_), \
+                                           OT_AES_IV_SIZE, false, \
+                                           (_s_)->hexstr, \
+                                           AES_DEBUG_HEXBUF_SIZE))
+#else
+#define trace_ot_aes_buf(_s_, _a_, _m_, _b_)
+#define trace_ot_aes_key(_s_, _a_, _b_, _l_)
+#define trace_ot_aes_iv(_s_, _a_, _b_)
+#endif /* DEBUG_AES */
+#define xtrace_ot_aes_debug(_otid_, _msg_) \
+    trace_ot_aes_debug(__func__, __LINE__, _otid_, _msg_)
+#define xtrace_ot_aes_info(_otid_, _msg_) \
+    trace_ot_aes_info(__func__, __LINE__, _otid_, _msg_)
+#define xtrace_ot_aes_error(_otid_, _msg_) \
+    trace_ot_aes_error(__func__, __LINE__, _otid_, _msg_)
+
+static void ot_aes_reseed(OtAESState *s);
+
+static void ot_aes_randomize(OtAESState *s, uint32_t *regs, size_t count)
+{
+    ot_prng_random_u32_array(s->prng, regs, count);
+}
+
+static inline size_t ot_aes_get_key_length(OtAESRegisters *r)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&r->ctrl);
+    switch (FIELD_EX32(ctrl, CTRL_SHADOWED, KEY_LEN)) {
+    case 0x01u:
+        return 16u; /* 128 bits */
+    case 0x02u:
+        return 24u; /* 192 bits */
+    case 0x04u:
+    default:
+        return 32u; /* 256bits */
+    }
+};
+
+static inline uint32_t ot_aes_get_key_mask(OtAESRegisters *r)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&r->ctrl);
+    switch (FIELD_EX32(ctrl, CTRL_SHADOWED, KEY_LEN)) {
+    case 0x01u:
+        return 0x0fu; /* 128 bits, 16 bytes, 4 words */
+    case 0x02u:
+        return 0x3fu; /* 192 bits, 24 bytes, 6 words */
+    case 0x04u:
+    default:
+        return 0xffu; /* 256bits, 32 bytes, 8 words */
+    }
+};
+
+static void ot_aes_update_alert(OtAESState *s)
+{
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        bool level =
+            (bool)(s->regs->status & (1u << (ix + OT_AES_ALERT_STATUS_OFFSET)));
+        ibex_irq_set(&s->alerts[ix], (int)level);
+    }
+}
+
+static inline bool ot_aes_is_manual(OtAESRegisters *r)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&r->ctrl);
+    return FIELD_EX32(ctrl, CTRL_SHADOWED, MANUAL_OPERATION) == 1u;
+}
+
+static bool ot_aes_is_idle(OtAESState *s)
+{
+    return s->regs->trigger == 0u &&
+           /* retard_timer is never used if fast_mode is enabled */
+           (s->fast_mode || !timer_pending(s->retard_timer));
+}
+
+static inline bool ot_aes_is_encryption(OtAESRegisters *r)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&r->ctrl);
+    return FIELD_EX32(ctrl, CTRL_SHADOWED, OPERATION) != 0x2u;
+}
+
+static inline OtAESMode ot_aes_get_mode(OtAESRegisters *r)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&r->ctrl);
+    switch (FIELD_EX32(ctrl, CTRL_SHADOWED, MODE)) {
+    case 0x01u:
+        return AES_ECB;
+    case 0x02u:
+        return AES_CBC;
+    case 0x04u:
+        return AES_CFB;
+    case 0x08u:
+        return AES_OFB;
+    case 0x10u:
+        return AES_CTR;
+    case 0x20u:
+    default:
+        return AES_NONE;
+    }
+};
+
+static inline void ot_aes_load_reseed_rate(OtAESState *s)
+{
+    OtAESRegisters *r = s->regs;
+    uint32_t ctrl = ot_shadow_reg_peek(&r->ctrl);
+    uint32_t rate = FIELD_EX32(ctrl, CTRL_SHADOWED, PRNG_RESEED_RATE);
+    unsigned reseed;
+
+    switch (rate) {
+    case 0x3u:
+        /* should be "approximately" 8192 */
+        reseed = 8192u;
+        break;
+    case 0x2u:
+        /* should be "approximately" 64 */
+        reseed = 64u;
+        break;
+    case 0x1u:
+    case 0x0u:
+    default:
+        reseed = 1u;
+        break;
+    }
+
+    trace_ot_aes_reseed_rate(s->ot_id, reseed);
+
+    s->reseed_count = reseed;
+}
+
+static inline bool ot_aes_is_sideload(OtAESRegisters *r)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&r->ctrl);
+    return FIELD_EX32(ctrl, CTRL_SHADOWED, SIDELOAD) == 1u;
+}
+
+static inline bool ot_aes_is_data_in_ready(OtAESRegisters *r)
+{
+    return (r->data_in_bm[0] & OT_AES_DATA_BM_MASK) == OT_AES_DATA_BM_MASK;
+}
+
+static inline bool ot_aes_key_touch_force_reseed(OtAESRegisters *r)
+{
+    return (bool)(ot_shadow_reg_peek(&r->ctrl_aux) &
+                  R_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_MASK);
+}
+
+static void ot_aes_init_keyshare(OtAESState *s, bool randomize)
+{
+    OtAESRegisters *r = s->regs;
+    OtAESContext *c = s->ctx;
+
+    if (randomize) {
+        trace_ot_aes_init(s->ot_id, "keyshare init (randomize data)");
+        ot_aes_randomize(s, r->keyshare, ARRAY_SIZE(r->keyshare));
+    } else {
+        trace_ot_aes_init(s->ot_id, "keyshare init (data preserved)");
+    }
+    bitmap_zero(r->keyshare_bm, (int64_t)(PARAM_NUM_REGS_KEY * 2u));
+    c->key_ready = false;
+}
+
+static void ot_aes_init_iv(OtAESState *s, bool randomize)
+{
+    OtAESRegisters *r = s->regs;
+    OtAESContext *c = s->ctx;
+
+    if (randomize) {
+        trace_ot_aes_init(s->ot_id, "iv init (randomize data)");
+        ot_aes_randomize(s, r->iv, ARRAY_SIZE(r->iv));
+    } else {
+        trace_ot_aes_init(s->ot_id, "iv init (data preserved)");
+    }
+    bitmap_zero(r->iv_bm, PARAM_NUM_REGS_IV);
+    c->iv_ready = false;
+}
+
+static void ot_aes_init_data(OtAESState *s, bool io)
+{
+    OtAESRegisters *r = s->regs;
+
+    if (!io) {
+        trace_ot_aes_init(s->ot_id, "data_in");
+        ot_aes_randomize(s, r->data_in, ARRAY_SIZE(r->data_in));
+        bitmap_zero(r->data_in_bm, PARAM_NUM_REGS_DATA);
+    } else {
+        trace_ot_aes_init(s->ot_id, "data_out");
+        ot_aes_randomize(s, r->data_out, ARRAY_SIZE(r->data_out));
+        bitmap_zero(r->data_out_bm, PARAM_NUM_REGS_DATA);
+    }
+}
+
+static bool ot_aes_is_mode_ready(OtAESRegisters *r, bool *need_iv)
+{
+    OtAESMode mode = ot_aes_get_mode(r);
+
+    switch (mode) {
+    case AES_ECB:
+        if (need_iv) {
+            *need_iv = false;
+        }
+        return true;
+    case AES_CBC:
+    case AES_CFB:
+    case AES_OFB:
+    case AES_CTR:
+        if (need_iv) {
+            *need_iv = true;
+        }
+        return true;
+    case AES_NONE:
+    default:
+        return false;
+    }
+}
+
+static void ot_aes_trigger_reseed(OtAESState *s)
+{
+    OtAESRegisters *r = s->regs;
+    uint32_t ctrl_aux = ot_shadow_reg_peek(&r->ctrl_aux);
+
+    if (!(ctrl_aux & R_CTRL_AUX_SHADOWED_FORCE_MASKS_MASK)) {
+        ot_aes_reseed(s);
+    } else {
+        r->trigger &= ~R_TRIGGER_PRNG_RESEED_MASK;
+        xtrace_ot_aes_info(s->ot_id, "reseed on trigger disabled");
+    }
+}
+
+static void ot_aes_sideload_key(OtAESState *s)
+{
+    OtAESKey *key = s->sl_key;
+    OtAESContext *c = s->ctx;
+
+    for (unsigned ix = 0u; ix < OT_AES_KEY_DWORD_COUNT; ix++) {
+        c->key[ix] = key->share0[ix] ^ key->share1[ix];
+    }
+
+    c->key_ready = key->valid;
+}
+
+static void ot_aes_update_key(OtAESState *s)
+{
+    OtAESRegisters *r = s->regs;
+
+    uint32_t key_mask;
+    if (ot_aes_is_manual(r)) {
+        key_mask = ot_aes_get_key_mask(r);
+    } else {
+        key_mask = (1u << (PARAM_NUM_REGS_KEY * 2u)) - 1u;
+    }
+    if ((r->keyshare_bm[0u] & key_mask) != key_mask) {
+        /* missing key parts, nothing to do */
+        return;
+    }
+
+    OtAESContext *c = s->ctx;
+
+    for (unsigned ix = 0u; ix < ARRAY_SIZE(r->keyshare) / 2u; ix += 2u) {
+        uint64_t key;
+
+        key = (uint64_t)(r->keyshare[ix + 1u] ^
+                         r->keyshare[PARAM_NUM_REGS_KEY + ix + 1u]);
+        key <<= 32u;
+        key |= (uint64_t)(r->keyshare[ix + 0u] ^
+                          r->keyshare[PARAM_NUM_REGS_KEY + ix + 0u]);
+
+        c->key[ix >> 1u] = key;
+    }
+
+    if (!c->key_ready && ot_aes_key_touch_force_reseed(r)) {
+        r->trigger |= R_TRIGGER_PRNG_RESEED_MASK;
+        trace_ot_aes_reseed(s->ot_id, "new key");
+        ot_aes_trigger_reseed(s);
+    }
+
+    c->key_ready = true;
+}
+
+static void ot_aes_update_iv(OtAESState *s)
+{
+    OtAESRegisters *r = s->regs;
+
+    if ((r->iv_bm[0u] & OT_AES_IV_BM_MASK) != OT_AES_IV_BM_MASK) {
+        /* missing key parts, nothing to do */
+        return;
+    }
+
+    OtAESContext *c = s->ctx;
+
+    for (unsigned ix = 0u; ix < ARRAY_SIZE(r->iv); ix += 2u) {
+        c->iv[ix >> 1u] =
+            ((uint64_t)(r->iv[ix + 1u])) << 32u | (uint64_t)r->iv[ix + 0u];
+    }
+
+    c->iv_ready = true;
+}
+
+static inline bool ot_aes_can_process(const OtAESState *s)
+{
+    OtAESRegisters *r = s->regs;
+    bool need_iv;
+
+    if (!ot_aes_is_mode_ready(r, &need_iv)) {
+        xtrace_ot_aes_debug(s->ot_id, "mode not ready");
+        return false;
+    }
+
+    OtAESContext *c = s->ctx;
+
+    if (need_iv && !c->iv_ready) {
+        xtrace_ot_aes_debug(s->ot_id, "IV not ready");
+        return false;
+    }
+
+    if (ot_aes_is_manual(r)) {
+        if (!(r->trigger & R_TRIGGER_START_MASK)) {
+            /* cannot execute in manual mode w/o an explicit trigger */
+            xtrace_ot_aes_debug(s->ot_id, "manual not triggered");
+            return false;
+        }
+
+        /* No other checks for inputs or key validity in manual mode */
+        return true;
+    }
+    /* auto mode */
+
+    if (!c->key_ready) {
+        xtrace_ot_aes_debug(s->ot_id, "key not ready");
+        return false;
+    }
+
+    if (c->do_full) {
+        /* cannot schedule a round if output FIFO has not been emptied */
+        xtrace_ot_aes_debug(s->ot_id, "DO full");
+        return false;
+    }
+
+    if (!c->di_full) {
+        xtrace_ot_aes_debug(s->ot_id, "DI not filled");
+    }
+
+    return c->di_full;
+}
+
+static void ot_aes_handle_trigger(OtAESState *s)
+{
+    /*
+     * @todo looks like these operations needs to use a background worker
+     * as IDLE may need to be actionned
+     */
+    OtAESRegisters *r = s->regs;
+
+    ibex_irq_set(&s->clock_active, (int)true);
+
+    if (r->trigger & R_TRIGGER_PRNG_RESEED_MASK) {
+        trace_ot_aes_reseed(s->ot_id, "trigger write");
+        ot_aes_trigger_reseed(s);
+        if (s->edn.scheduled) {
+            xtrace_ot_aes_debug(s->ot_id, "EDN scheduled, defer");
+            return;
+        }
+    }
+
+    if (r->trigger & R_TRIGGER_KEY_IV_DATA_IN_CLEAR_MASK) {
+        ot_aes_init_keyshare(s, true);
+        ot_aes_init_iv(s, true);
+        ot_aes_init_data(s, false);
+        r->trigger &= ~R_TRIGGER_KEY_IV_DATA_IN_CLEAR_MASK;
+    }
+
+    if (r->trigger & R_TRIGGER_DATA_OUT_CLEAR_MASK) {
+        ot_aes_init_data(s, true);
+        r->trigger &= ~R_TRIGGER_DATA_OUT_CLEAR_MASK;
+    }
+
+    if (r->trigger & R_TRIGGER_START_MASK) {
+        if (ot_aes_get_mode(r) == AES_NONE || !ot_aes_is_manual(r)) {
+            /* ignore */
+            xtrace_ot_aes_debug(s->ot_id, "start trigger ignored");
+            return;
+        }
+    }
+
+    /* an AES round might have been delayed */
+    if (ot_aes_can_process(s)) {
+        trace_ot_aes_schedule(s->ot_id);
+        qemu_bh_schedule(s->process_bh);
+    }
+
+    xtrace_ot_aes_debug(s->ot_id, ot_aes_is_idle(s) ? "IDLE" : "NOT IDLE");
+    ibex_irq_set(&s->clock_active, (int)!ot_aes_is_idle(s));
+}
+
+static void ot_aes_update_config(OtAESState *s)
+{
+    OtAESRegisters *r = s->regs;
+
+    bool need_iv;
+
+    xtrace_ot_aes_debug(s->ot_id, "CONFIG");
+
+    if (!ot_aes_is_mode_ready(r, &need_iv)) {
+        return;
+    }
+
+    OtAESContext *c = s->ctx;
+
+    if (!ot_aes_is_manual(s->regs) && !c->key_ready) {
+        return;
+    }
+
+    if (need_iv && !c->iv_ready) {
+        return;
+    }
+
+    size_t key_size = ot_aes_get_key_length(r);
+    OtAESMode mode = ot_aes_get_mode(r);
+
+    int rc;
+
+    switch (mode) {
+    case AES_ECB:
+        rc = ecb_start(c->aes_cipher, (const uint8_t *)c->key, (int)key_size, 0,
+                       &c->ecb);
+        break;
+    case AES_CBC:
+        rc = cbc_start(c->aes_cipher, (const uint8_t *)c->iv,
+                       (const uint8_t *)c->key, (int)key_size, 0, &c->cbc);
+        break;
+    case AES_CFB:
+        rc = cfb_start(c->aes_cipher, (const uint8_t *)c->iv,
+                       (const uint8_t *)c->key, (int)key_size, 0, &c->cfb);
+        break;
+    case AES_OFB:
+        rc = ofb_start(c->aes_cipher, (const uint8_t *)c->iv,
+                       (const uint8_t *)c->key, (int)key_size, 0, &c->ofb);
+        break;
+    case AES_CTR:
+        rc = ctr_start(c->aes_cipher, (const uint8_t *)c->iv,
+                       (const uint8_t *)c->key, (int)key_size, 0,
+                       CTR_COUNTER_BIG_ENDIAN, &c->ctr);
+        break;
+    default:
+        /* cannot happen */
+        return;
+    }
+
+    trace_ot_aes_key(s, OT_AES_MODE_NAMES[mode], c->key, key_size);
+    trace_ot_aes_iv(s, OT_AES_MODE_NAMES[mode], c->iv);
+
+    if (rc != CRYPT_OK) {
+        error_report("OpenTitan AES [%s]: Unable to initialize AES API: %d",
+                     OT_AES_MODE_NAMES[mode], rc);
+        /* @todo how to report this? */
+    }
+}
+
+static void ot_aes_finalize(OtAESState *s, OtAESMode mode)
+{
+    int rc;
+
+    OtAESContext *c = s->ctx;
+
+    /*
+     * libtomcrypt's cipher filed needs to be tested, as the initialization
+     * function may have never been called prior to the finalization, in which
+     * case the matching *_done function should not be called
+     */
+
+    switch (mode) {
+    case AES_NONE:
+        return;
+    case AES_ECB:
+        rc = c->ecb.cipher == c->aes_cipher ? ecb_done(&c->ecb) : CRYPT_OK;
+        break;
+    case AES_CBC:
+        rc = c->cbc.cipher == c->aes_cipher ? cbc_done(&c->cbc) : CRYPT_OK;
+        break;
+    case AES_CFB:
+        rc = c->cfb.cipher == c->aes_cipher ? cfb_done(&c->cfb) : CRYPT_OK;
+        break;
+    case AES_OFB:
+        rc = c->ofb.cipher == c->aes_cipher ? ofb_done(&c->ofb) : CRYPT_OK;
+        break;
+    case AES_CTR:
+        rc = c->ctr.cipher == c->aes_cipher ? ctr_done(&c->ctr) : CRYPT_OK;
+        break;
+    default:
+        /* cannot happen */
+        return;
+    }
+
+    if (rc != CRYPT_OK) {
+        error_report("OpenTitan AES [%s]: Unable to finalize AES API: %d",
+                     OT_AES_MODE_NAMES[mode], rc);
+        /* @todo how to report this? */
+    }
+
+    c->di_full = false;
+    c->do_full = false;
+}
+
+static void ot_aes_compute_ctr_iv(OtAESState *s, uint8_t *iv)
+{
+    OtAESContext *c = s->ctx;
+    uint8_t liv[OT_AES_IV_SIZE];
+
+    unsigned long length = OT_AES_IV_SIZE;
+    ctr_getiv(liv, &length, &c->ctr);
+
+    g_assert(c->ctr.mode == CTR_COUNTER_BIG_ENDIAN);
+    g_assert(c->ctr.ctrlen == 0);
+
+    unsigned ix = OT_AES_IV_SIZE - 1u;
+    do {
+        liv[ix] = liv[ix] + 0x1u;
+        if (liv[ix] != 0) {
+            break;
+        }
+    } while (ix--);
+
+    memcpy(iv, liv, sizeof(liv));
+}
+
+static void ot_aes_pop(OtAESState *s)
+{
+    OtAESRegisters *r = s->regs;
+    OtAESContext *c = s->ctx;
+
+    memcpy(c->src, r->data_in, sizeof(c->src));
+    bitmap_zero(r->data_in_bm, PARAM_NUM_REGS_DATA);
+
+    c->di_full = true;
+}
+
+static void ot_aes_push(OtAESState *s)
+{
+    OtAESRegisters *r = s->regs;
+    OtAESContext *c = s->ctx;
+
+    memcpy(r->data_out, c->dst, sizeof(c->dst));
+    memcpy(r->iv, c->iv, sizeof(c->iv));
+    r->data_out_rdy = true;
+}
+
+static void ot_aes_process(OtAESState *s)
+{
+    OtAESRegisters *r = s->regs;
+    OtAESContext *c = s->ctx;
+
+    OtAESMode mode = ot_aes_get_mode(s->regs);
+    bool encrypt = ot_aes_is_encryption(r);
+
+    int rc;
+
+    xtrace_ot_aes_debug(s->ot_id, "process");
+
+    if (encrypt) {
+        trace_ot_aes_buf(s, OT_AES_MODE_NAMES[mode], "enc/in ", c->src);
+        switch (mode) {
+        case AES_ECB:
+            rc = ecb_encrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->ecb);
+            break;
+        case AES_CBC:
+            rc = cbc_encrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->cbc);
+            break;
+        case AES_CFB:
+            rc = cfb_encrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->cfb);
+            break;
+        case AES_OFB:
+            rc = ofb_encrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->ofb);
+            break;
+        case AES_CTR:
+            rc = ctr_encrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->ctr);
+            break;
+        case AES_NONE:
+        default:
+            rc = CRYPT_ERROR;
+            break;
+        }
+        trace_ot_aes_buf(s, OT_AES_MODE_NAMES[mode], "enc/out", c->dst);
+    } else {
+        trace_ot_aes_buf(s, OT_AES_MODE_NAMES[mode], "dec/in ", c->src);
+        switch (mode) {
+        case AES_ECB:
+            rc = ecb_decrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->ecb);
+            break;
+        case AES_CBC:
+            rc = cbc_decrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->cbc);
+            break;
+        case AES_CFB:
+            rc = cfb_decrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->cfb);
+            break;
+        case AES_OFB:
+            rc = ofb_decrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->ofb);
+            break;
+        case AES_CTR:
+            rc = ctr_decrypt(c->src, c->dst, OT_AES_DATA_SIZE, &c->ctr);
+            break;
+        case AES_NONE:
+        default:
+            rc = CRYPT_ERROR;
+            break;
+        }
+        trace_ot_aes_buf(s, OT_AES_MODE_NAMES[mode], "dec/out", c->dst);
+    }
+
+    c->di_full = false;
+
+    if (rc == CRYPT_OK) {
+        /*
+         * IV registers are updated on each round. For details, see:
+         * https://opentitan.org/book/hw/ip/aes/doc/theory_of_operation.html
+         * https://en.wikipedia.org/wiki/Block_cipher_mode_of_operation
+         */
+        switch (mode) {
+        case AES_CBC:
+            memcpy(c->iv, c->cbc.IV, sizeof(c->iv));
+            break;
+        case AES_CFB:
+            /* In CFB mode the next IV register value is the ciphertext */
+            memcpy(c->iv, encrypt ? c->dst : c->src, sizeof(c->iv));
+            break;
+        case AES_OFB:
+            memcpy(c->iv, c->ofb.IV, sizeof(c->iv));
+            break;
+        case AES_CTR:
+            ot_aes_compute_ctr_iv(s, (uint8_t *)&c->iv[0]);
+            break;
+        default:
+            break;
+        }
+        c->do_full = true;
+    } else {
+        error_report("OpenTitan AES [%s]: Unable to run AES: %d",
+                     OT_AES_MODE_NAMES[mode], rc);
+        /* @todo how to report this? */
+    }
+}
+
+static void ot_aes_commit_data_out(OtAESRegisters *r)
+{
+    if (r->data_out_rdy) {
+        bitmap_fill(r->data_out_bm, PARAM_NUM_REGS_DATA);
+        r->status |= R_STATUS_OUTPUT_VALID_MASK;
+        r->data_out_rdy = false;
+    }
+}
+
+static inline void ot_aes_do_process(OtAESState *s)
+{
+    ot_aes_process(s);
+    ot_aes_push(s);
+    if (s->reseed_count) {
+        s->reseed_count -= 1u;
+    }
+    if (!s->reseed_count) {
+        /*
+         * delay availability of pushed data till completion of reseed
+         * otherwise, IDLE status may be false once the vCPU has read the data,
+         * which would not match the HW behavior
+         */
+        trace_ot_aes_reseed(s->ot_id, "reseed_count reached");
+        s->regs->trigger |= R_TRIGGER_PRNG_RESEED_MASK;
+        ot_aes_trigger_reseed(s);
+        ot_aes_load_reseed_rate(s);
+    } else {
+        /* flag pushed data as immediately available */
+        ot_aes_commit_data_out(s->regs);
+    }
+
+    OtAESRegisters *r = s->regs;
+    if (ot_aes_is_manual(r)) {
+        xtrace_ot_aes_info(s->ot_id, "end of manual seq");
+        s->regs->trigger &= ~R_TRIGGER_START_MASK;
+    }
+}
+
+static void ot_aes_process_cond(OtAESState *s)
+{
+    if (!s->edn.scheduled) {
+        if (ot_aes_can_process(s)) {
+            if (!s->fast_mode) {
+                /*
+                 * if fast mode is disabled, delay execution of AES round
+                 * to give back execution to vCPU using a short timer. This
+                 * allows the vCPU to run and time-sensitive guest code in
+                 * OpenTitan libraries to poll for HW status, at the expense of
+                 * AES throughput.
+                 */
+                timer_del(s->retard_timer);
+                uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+                timer_mod(s->retard_timer,
+                          (int64_t)(now + OT_AES_RETARD_DELAY_NS));
+            } else {
+                /*
+                 * if fast mode is enabled, vCPU cannot resume execution before
+                 * the AES round is completed, which increase throughput and
+                 * reduce latency for AES compution, but may fail time-sensitive
+                 * OpenTitan library that expect the real CPU to execute code
+                 * while AES is performing in HW.
+                 */
+                ot_aes_do_process(s);
+            }
+        }
+    } else {
+        xtrace_ot_aes_info(s->ot_id, "defer exec, waiting for EDN");
+    }
+}
+
+static void ot_aes_fill_entropy(void *opaque, uint32_t bits, bool fips)
+{
+    /* called from EDN */
+    (void)fips;
+
+    OtAESState *s = opaque;
+    OtAESEDN *edn = &s->edn;
+    OtAESRegisters *r = s->regs;
+
+    if (!edn->scheduled) {
+        xtrace_ot_aes_error(s->ot_id, "unexpected entropy");
+        return;
+    }
+    trace_ot_aes_fill_entropy(s->ot_id, bits, fips);
+    edn->scheduled = false;
+    r->trigger &= ~R_TRIGGER_PRNG_RESEED_MASK;
+
+    /*
+     * if a previous AES data output generation had completed, flag the output
+     * as valid, as this state was delayed till entropy collection was
+     * completed to maintain a coherent IDLE state.
+     */
+    ot_aes_commit_data_out(r);
+
+    ot_prng_reseed(s->prng, bits);
+
+    ot_aes_handle_trigger(s);
+}
+
+static void ot_aes_handle_process(void *opaque)
+{
+    OtAESState *s = opaque;
+
+    ot_aes_do_process(s);
+}
+
+static void ot_aes_reseed(OtAESState *s)
+{
+    OtAESEDN *edn = &s->edn;
+
+    if (!edn->connected) {
+        ot_edn_connect_endpoint(edn->device, edn->ep, &ot_aes_fill_entropy, s);
+        edn->connected = true;
+    }
+    if (!edn->scheduled) {
+        trace_ot_aes_request_entropy(s->ot_id);
+        if (!ot_edn_request_entropy(edn->device, edn->ep)) {
+            edn->scheduled = true;
+        } else {
+            xtrace_ot_aes_error(s->ot_id, "cannot request new entropy");
+        }
+    }
+}
+
+static void ot_aes_clock_input(void *opaque, int irq, int level)
+{
+    OtAESState *s = opaque;
+
+    g_assert(irq == 0);
+
+    s->pclk = (unsigned)level;
+
+    /* TODO: disable AES execution when PCLK is 0 */
+}
+
+static void ot_aes_push_key(OtKeySinkIf *ifd, const uint8_t *share0,
+                            const uint8_t *share1, size_t key_len, bool valid)
+{
+    g_assert(!key_len || key_len == OT_AES_KEY_SIZE);
+
+    OtAESState *s = OT_AES(ifd);
+    OtAESKey *key = s->sl_key;
+
+    if (key_len && share0) {
+        memcpy(key->share0, share0, key_len);
+    } else {
+        memset(key->share0, 0, OT_AES_KEY_SIZE);
+    }
+    if (key_len && share1) {
+        memcpy(key->share1, share1, key_len);
+    } else {
+        memset(key->share1, 0, OT_AES_KEY_SIZE);
+    }
+    key->valid = valid;
+
+    if (ot_aes_is_sideload(s->regs)) {
+        ot_aes_sideload_key(s);
+        ot_aes_update_config(s);
+    }
+}
+
+static uint64_t ot_aes_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtAESState *s = opaque;
+    (void)size;
+    OtAESRegisters *r = s->regs;
+
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_ALERT_TEST:
+    case R_KEY_SHARE0_0:
+    case R_KEY_SHARE0_1:
+    case R_KEY_SHARE0_2:
+    case R_KEY_SHARE0_3:
+    case R_KEY_SHARE0_4:
+    case R_KEY_SHARE0_5:
+    case R_KEY_SHARE0_6:
+    case R_KEY_SHARE0_7:
+    case R_KEY_SHARE1_0:
+    case R_KEY_SHARE1_1:
+    case R_KEY_SHARE1_2:
+    case R_KEY_SHARE1_3:
+    case R_KEY_SHARE1_4:
+    case R_KEY_SHARE1_5:
+    case R_KEY_SHARE1_6:
+    case R_KEY_SHARE1_7:
+    case R_DATA_IN_0:
+    case R_DATA_IN_1:
+    case R_DATA_IN_2:
+    case R_DATA_IN_3:
+    case R_TRIGGER:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0u;
+        break;
+    case R_IV_0:
+    case R_IV_1:
+    case R_IV_2:
+    case R_IV_3:
+        val32 = r->iv[reg - R_IV_0];
+        break;
+    case R_DATA_OUT_0:
+    case R_DATA_OUT_1:
+    case R_DATA_OUT_2:
+    case R_DATA_OUT_3:
+        val32 = r->data_out[reg - R_DATA_OUT_0];
+        clear_bit((int64_t)(reg - R_DATA_OUT_0), r->data_out_bm);
+        if (bitmap_empty(r->data_out_bm, PARAM_NUM_REGS_DATA)) {
+            r->status &= ~R_STATUS_OUTPUT_VALID_MASK;
+            s->ctx->do_full = false;
+            ot_aes_process_cond(s);
+        }
+        break;
+    case R_CTRL_SHADOWED:
+        val32 = ot_shadow_reg_read(&r->ctrl);
+        break;
+    case R_CTRL_AUX_SHADOWED:
+        val32 = ot_shadow_reg_read(&r->ctrl_aux);
+        break;
+    case R_CTRL_AUX_REGWEN:
+        val32 = r->ctrl_aux_regwen;
+        break;
+    case R_STATUS:
+        val32 = r->status;
+        if (ot_aes_is_idle(s)) {
+            val32 |= R_STATUS_IDLE_MASK;
+        }
+        if (!ot_aes_is_data_in_ready(r)) {
+            val32 |= R_STATUS_INPUT_READY_MASK;
+        }
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0u;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_aes_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                             pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_aes_write(void *opaque, hwaddr addr, uint64_t val64,
+                         unsigned size)
+{
+    OtAESState *s = opaque;
+    (void)size;
+    OtAESRegisters *r = s->regs;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_aes_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_ALERT_TEST:
+        if (val32 & ALERT_RECOV_CTRL_UPDATE_ERR_MASK) {
+            r->status |= R_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK;
+        }
+        if (val32 & ALERT_FATAL_FAULT_MASK) {
+            r->status |= R_STATUS_ALERT_FATAL_FAULT_MASK;
+        }
+        ot_aes_update_alert(s);
+        break;
+    case R_DATA_OUT_0:
+    case R_DATA_OUT_1:
+    case R_DATA_OUT_2:
+    case R_DATA_OUT_3:
+    case R_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_KEY_SHARE0_0:
+    case R_KEY_SHARE0_1:
+    case R_KEY_SHARE0_2:
+    case R_KEY_SHARE0_3:
+    case R_KEY_SHARE0_4:
+    case R_KEY_SHARE0_5:
+    case R_KEY_SHARE0_6:
+    case R_KEY_SHARE0_7:
+    case R_KEY_SHARE1_0:
+    case R_KEY_SHARE1_1:
+    case R_KEY_SHARE1_2:
+    case R_KEY_SHARE1_3:
+    case R_KEY_SHARE1_4:
+    case R_KEY_SHARE1_5:
+    case R_KEY_SHARE1_6:
+    case R_KEY_SHARE1_7:
+        if (ot_aes_is_sideload(r)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: key share disabled, sideload is active\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        if (ot_aes_is_idle(s)) {
+            r->keyshare[reg - R_KEY_SHARE0_0] = val32;
+            set_bit((int64_t)(reg - R_KEY_SHARE0_0), r->keyshare_bm);
+            ot_aes_update_key(s);
+            ot_aes_update_config(s);
+        }
+        break;
+    case R_IV_0:
+    case R_IV_1:
+    case R_IV_2:
+    case R_IV_3:
+        if (ot_aes_is_idle(s)) {
+            r->iv[reg - R_IV_0] = val32;
+            set_bit((int64_t)(reg - R_IV_0), r->iv_bm);
+            ot_aes_update_iv(s);
+            ot_aes_update_config(s);
+        }
+        break;
+    case R_DATA_IN_0:
+    case R_DATA_IN_1:
+    case R_DATA_IN_2:
+    case R_DATA_IN_3:
+        r->data_in[reg - R_DATA_IN_0] = val32;
+        set_bit((int64_t)(reg - R_DATA_IN_0), r->data_in_bm);
+        if (ot_aes_is_data_in_ready(r)) {
+            ibex_irq_set(&s->clock_active, (int)true);
+            ot_aes_pop(s);
+        }
+        if (!ot_aes_is_manual(r)) {
+            ot_aes_process_cond(s);
+        }
+        break;
+    case R_CTRL_SHADOWED:
+        if (!ot_aes_is_idle(s)) {
+            break;
+        }
+        val32 &= R_CTRL_SHADOWED_OPERATION_MASK | R_CTRL_SHADOWED_MODE_MASK |
+                 R_CTRL_SHADOWED_KEY_LEN_MASK | R_CTRL_SHADOWED_SIDELOAD_MASK |
+                 R_CTRL_SHADOWED_PRNG_RESEED_RATE_MASK |
+                 R_CTRL_SHADOWED_MANUAL_OPERATION_MASK |
+                 R_CTRL_SHADOWED_FORCE_ZERO_MASKS_MASK;
+        OtAESMode prev_mode = ot_aes_get_mode(s->regs);
+        switch (ot_shadow_reg_write(&r->ctrl, val32)) {
+        case OT_SHADOW_REG_STAGED:
+            break;
+        case OT_SHADOW_REG_COMMITTED:
+            /*
+             * "A write to the Control Register is considered the start
+             * of a new message. Hence, software needs to provide new key,
+             * IV and input data afterwards."
+             */
+            ot_aes_finalize(s, prev_mode);
+            ot_aes_init_keyshare(s, false);
+            ot_aes_init_iv(s, false);
+            ot_aes_load_reseed_rate(s);
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            r->status |= R_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK;
+            ot_aes_update_alert(s);
+            break;
+        }
+        if (ot_aes_is_sideload(s->regs)) {
+            ot_aes_sideload_key(s);
+        }
+        ot_aes_update_config(s);
+        break;
+    case R_CTRL_AUX_SHADOWED:
+        if (!r->ctrl_aux_regwen) {
+            break;
+        }
+        val32 &= R_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_MASK |
+                 R_CTRL_AUX_SHADOWED_FORCE_MASKS_MASK;
+        switch (ot_shadow_reg_write(&r->ctrl_aux, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            r->status |= R_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK;
+            ot_aes_update_alert(s);
+        }
+        break;
+    case R_CTRL_AUX_REGWEN:
+        val32 &= R_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_MASK;
+        r->ctrl_aux_regwen = val32;
+        break;
+    case R_TRIGGER:
+        val32 &= R_TRIGGER_START_MASK | R_TRIGGER_KEY_IV_DATA_IN_CLEAR_MASK |
+                 R_TRIGGER_DATA_OUT_CLEAR_MASK | R_TRIGGER_PRNG_RESEED_MASK;
+        r->trigger |= val32;
+        ot_aes_handle_trigger(s);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static const Property ot_aes_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtAESState, ot_id),
+    DEFINE_PROP_STRING("clock-name", OtAESState, clock_name),
+    DEFINE_PROP_LINK("clock-src", OtAESState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+    DEFINE_PROP_LINK("edn", OtAESState, edn.device, TYPE_OT_EDN, OtEDNState *),
+    DEFINE_PROP_UINT8("edn-ep", OtAESState, edn.ep, UINT8_MAX),
+    /*
+     * some time-sensitive OT tests requires vCPU to be scheduled before AES
+     * round is executed, in which case this property should be reset. In most
+     * cases, using fast-mode reduces latency and increase AES throughput
+     */
+    DEFINE_PROP_BOOL("fast-mode", OtAESState, fast_mode, true),
+};
+
+static const MemoryRegionOps ot_aes_regs_ops = {
+    .read = &ot_aes_read,
+    .write = &ot_aes_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_aes_reset_enter(Object *obj, ResetType type)
+{
+    OtAESClass *c = OT_AES_GET_CLASS(obj);
+    OtAESState *s = OT_AES(obj);
+    OtAESEDN *e = &s->edn;
+    OtAESRegisters *r = s->regs;
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->retard_timer);
+
+    memset(s->ctx, 0, sizeof(*s->ctx));
+    memset(r, 0, sizeof(*r));
+    memset(s->sl_key, 0, sizeof(*s->sl_key));
+
+    ot_shadow_reg_init(&r->ctrl, 0x1181u);
+    ot_shadow_reg_init(&r->ctrl_aux, 1u);
+    r->ctrl_aux_regwen = 1u;
+    r->trigger = 0xeu;
+    r->status = 0u;
+    r->data_out_rdy = false;
+    e->scheduled = false;
+    ot_aes_load_reseed_rate(s);
+
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->alerts[ix], 0);
+    }
+
+    if (!s->clock_src_name) {
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_name =
+            ic->get_clock_source(ii, s->clock_name, DEVICE(s), &error_fatal);
+        qemu_irq in_irq =
+            qdev_get_gpio_in_named(DEVICE(s), OT_AES_CLOCK_INPUT, 0);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_name, 0, in_irq);
+
+        if (object_dynamic_cast(OBJECT(s->clock_src), TYPE_OT_CLKMGR)) {
+            char *hint_name =
+                g_strdup_printf(OT_CLOCK_HINT_PREFIX "%s", s->clock_name);
+            qemu_irq hint_irq =
+                qdev_get_gpio_in_named(s->clock_src, hint_name, 0);
+            g_assert(hint_irq);
+            qdev_connect_gpio_out_named(DEVICE(s), OT_AES_CLOCK_ACTIVE, 0,
+                                        hint_irq);
+            g_free(hint_name);
+        }
+    }
+}
+
+static void ot_aes_reset_exit(Object *obj, ResetType type)
+{
+    OtAESClass *c = OT_AES_GET_CLASS(obj);
+    OtAESState *s = OT_AES(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    qemu_bh_cancel(s->process_bh);
+
+    trace_ot_aes_reseed(s->ot_id, "reset");
+    ot_aes_handle_trigger(s);
+}
+
+static void ot_aes_realize(DeviceState *dev, Error **errp)
+{
+    OtAESState *s = OT_AES(dev);
+    OtAESEDN *e = &s->edn;
+
+    (void)errp;
+
+    g_assert(e->device);
+    g_assert(e->ep != UINT8_MAX);
+    g_assert(s->ot_id);
+    g_assert(s->clock_name);
+    g_assert(s->clock_src);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_aes_clock_input, OT_AES_CLOCK_INPUT,
+                            1);
+
+    s->prng = ot_prng_allocate();
+}
+
+static void ot_aes_init(Object *obj)
+{
+    OtAESState *s = OT_AES(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_aes_regs_ops, s, TYPE_OT_AES,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regs = g_new0(OtAESRegisters, 1u);
+    s->ctx = g_new0(OtAESContext, 1u);
+    s->sl_key = g_new0(OtAESKey, 1u);
+
+    /* aes_desc is defined in libtomcrypt */
+    s->ctx->aes_cipher = register_cipher(&aes_desc);
+    if (s->ctx->aes_cipher < 0) {
+        error_report("OpenTitan AES: Unable to use libtomcrypt AES API");
+    }
+
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    ibex_qdev_init_irq(obj, &s->clock_active, OT_AES_CLOCK_ACTIVE);
+
+    s->process_bh = qemu_bh_new(&ot_aes_handle_process, s);
+    s->retard_timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_aes_handle_process, s);
+
+#ifdef DEBUG_AES
+    s->hexstr = g_new0(char, AES_DEBUG_HEXBUF_SIZE);
+#endif
+}
+
+static void ot_aes_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_aes_realize;
+    device_class_set_props(dc, ot_aes_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtAESClass *ac = OT_AES_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_aes_reset_enter, NULL,
+                                       &ot_aes_reset_exit, &ac->parent_phases);
+
+    OtKeySinkIfClass *kc = OT_KEY_SINK_IF_CLASS(klass);
+    kc->push_key = &ot_aes_push_key;
+}
+
+static const TypeInfo ot_aes_info = {
+    .name = TYPE_OT_AES,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtAESState),
+    .instance_init = &ot_aes_init,
+    .class_size = sizeof(OtAESClass),
+    .class_init = &ot_aes_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_OT_KEY_SINK_IF },
+            {},
+        },
+};
+
+static void ot_aes_register_types(void)
+{
+    type_register_static(&ot_aes_info);
+}
+
+type_init(ot_aes_register_types);
diff --git a/hw/opentitan/ot_alert.c b/hw/opentitan/ot_alert.c
new file mode 100644
index 0000000000000..71eacd1501696
--- /dev/null
+++ b/hw/opentitan/ot_alert.c
@@ -0,0 +1,1240 @@
+/*
+ * QEMU OpenTitan Alert handler device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: for now, only a minimalist subset of Alert Handler device is
+ *       implemented in order to enable OpenTitan's ROM boot to progress
+ *       secondary clock source is not supported (secure.io_div4)
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+#define PARAM_ESC_CNT_DW  32u
+#define PARAM_ACCU_CNT_DW 16u
+#define PARAM_N_ESC_SEV   4u
+#define PARAM_PING_CNT_DW 16u
+#define PARAM_PHASE_DW    2u
+#define PARAM_CLASS_DW    2u
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(INTR_STATE_CLASSA, 0u, 1u)
+    SHARED_FIELD(INTR_STATE_CLASSB, 1u, 1u)
+    SHARED_FIELD(INTR_STATE_CLASSC, 2u, 1u)
+    SHARED_FIELD(INTR_STATE_CLASSD, 3u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(PING_TIMER_REGWEN, 0xcu)
+    FIELD(PING_TIMER_REGWEN, EN, 0u, 1u)
+REG32(PING_TIMEOUT_CYC_SHADOWED, 0x10u)
+    FIELD(PING_TIMEOUT_CYC_SHADOWED, VAL, 0u, 16u)
+REG32(PING_TIMER_EN_SHADOWED, 0x14u)
+    FIELD(PING_TIMER_EN_SHADOWED, EN, 0u, 1u)
+SHARED_FIELD(ALERT_REGWEN_EN, 0u, 1u)
+SHARED_FIELD(ALERT_EN_SHADOWED_EN, 0u, 1u)
+SHARED_FIELD(ALERT_CLASS_SHADOWED_EN, 0u, 2u)
+SHARED_FIELD(ALERT_CAUSE_EN, 0u, 1u)
+SHARED_FIELD(LOC_ALERT_REGWEN_EN, 0u, 1u)
+SHARED_FIELD(LOC_ALERT_EN_SHADOWED_EN, 0u, 1u)
+SHARED_FIELD(LOC_ALERT_CLASS_SHADOWED_EN, 0u, 2u)
+SHARED_FIELD(LOC_ALERT_CAUSE_EN, 0u, 1u)
+SHARED_FIELD(CLASS_REGWEN_EN, 0u, 1u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_EN, 0u, 1u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_LOCK, 1u, 1u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_EN_E0, 2u, 1u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_EN_E1, 3u, 1u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_EN_E2, 4u, 1u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_EN_E3, 5u, 1u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_MAP_E0, 6u, 2u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_MAP_E1, 8u, 2u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_MAP_E2, 10u, 2u)
+SHARED_FIELD(CLASS_CTRL_SHADOWED_MAP_E3, 12u, 2u)
+SHARED_FIELD(CLASS_CLR_REGWEN_EN, 0u, 1u)
+SHARED_FIELD(CLASS_CLR_SHADOWED_EN, 0u, 1u)
+SHARED_FIELD(CLASS_ACCUM_CNT, 0u, 16u)
+SHARED_FIELD(CLASS_ACCUM_THRESH_SHADOWED, 0u, 16u)
+SHARED_FIELD(CLASS_CRASHDUMP_TRIGGER_SHADOWED, 0u, 2u)
+SHARED_FIELD(CLASS_STATE, 0u, 3u)
+/* clang-format on */
+
+#define INTR_MASK ((1u << PARAM_N_CLASSES) - 1u)
+#define CLASS_CTRL_SHADOWED_MASK \
+    (CLASS_CTRL_SHADOWED_EN_MASK | CLASS_CTRL_SHADOWED_LOCK_MASK | \
+     CLASS_CTRL_SHADOWED_EN_E0_MASK | CLASS_CTRL_SHADOWED_EN_E1_MASK | \
+     CLASS_CTRL_SHADOWED_EN_E2_MASK | CLASS_CTRL_SHADOWED_EN_E3_MASK | \
+     CLASS_CTRL_SHADOWED_MAP_E0_MASK | CLASS_CTRL_SHADOWED_MAP_E1_MASK | \
+     CLASS_CTRL_SHADOWED_MAP_E2_MASK | CLASS_CTRL_SHADOWED_MAP_E3_MASK)
+
+#define R32_OFF(_r_)   ((_r_) / sizeof(uint32_t))
+#define REG_COUNT(_s_) (sizeof(_s_) / sizeof(OtShadowReg))
+
+/*
+ * as many registers are shadowed, it is easier to use shadow registers
+ * for all registers, and only use the shadow 'committed' attribute for
+ * the rest of them (the non-shadow registers)
+ */
+
+/* direct value of a 'fake' shadow register */
+#define DVAL(_shadow_) ((_shadow_).committed)
+
+#define ACLASS(_cls_) ((char)('A' + (_cls_)))
+
+typedef struct {
+    OtShadowReg state;
+    OtShadowReg enable;
+    OtShadowReg test;
+} OtAlertIntr;
+
+typedef struct {
+    OtShadowReg timer_regwen;
+    OtShadowReg timeout_cyc_shadowed;
+    OtShadowReg timer_en_shadowed;
+} OtAlertPing;
+
+/* not a real structure, only used to compute register spacing */
+typedef struct {
+    OtShadowReg regwen;
+    OtShadowReg en_shadowed;
+    OtShadowReg class_shadowed;
+    OtShadowReg cause;
+} OtAlertTemplate;
+
+typedef struct {
+    OtShadowReg *regwen;
+    OtShadowReg *en_shadowed;
+    OtShadowReg *class_shadowed;
+    OtShadowReg *cause;
+} OtAlertArrays;
+
+typedef struct {
+    OtShadowReg regwen;
+    OtShadowReg ctrl_shadowed;
+    OtShadowReg clr_regwen;
+    OtShadowReg clr_shadowed;
+    OtShadowReg accum_cnt;
+    OtShadowReg accum_thresh_shadowed;
+    OtShadowReg timeout_cyc_shadowed;
+    OtShadowReg crashdump_trigger_shadowed;
+    OtShadowReg phase_cyc_shadowed[4u];
+    OtShadowReg esc_cnt;
+    OtShadowReg state;
+} OtAlertAClass;
+
+typedef struct OtAlertRegs {
+    OtShadowReg *shadow;
+    /* shortcuts to the shadow entries */
+    OtAlertIntr *intr;
+    OtAlertPing *ping;
+    OtAlertArrays alerts;
+    OtAlertArrays loc_alerts;
+    OtAlertAClass *classes;
+} OtAlertRegs;
+
+typedef uint32_t (*ot_alert_reg_read_fn)(OtAlertState *s, unsigned reg);
+typedef void (*ot_alert_reg_write_fn)(OtAlertState *s, unsigned reg,
+                                      uint32_t value);
+
+typedef enum {
+    PWA_UPDATE_IRQ,
+    PWA_CLEAR_ALERT,
+} OtAlertPostWriteAction;
+
+typedef struct {
+    ot_alert_reg_read_fn read;
+    ot_alert_reg_write_fn write;
+    uint32_t mask; /* the mask to apply to the written value */
+    uint16_t protect; /* not 0 if write protected by another register */
+    uint8_t wpost; /* whether to perform post-write action */
+} OtAlertAccess;
+
+typedef struct {
+    /* count cycles: either timeout cycles or phase escalation cycles */
+    QEMUTimer timer;
+    QEMUBH *esc_releaser;
+    OtAlertState *parent;
+    IbexIRQ *esc_tx_release; /* Escalate signal to release */
+    unsigned nclass;
+} OtAlertScheduler;
+
+enum {
+    LOCAL_ALERT_ALERT_PINGFAIL,
+    LOCAL_ALERT_ESC_PINGFAIL,
+    LOCAL_ALERT_ALERT_INTEGFAIL,
+    LOCAL_ALERT_ESC_INTEGFAIL,
+    LOCAL_ALERT_BUS_INTEGFAIL,
+    LOCAL_ALERT_SHADOW_REG_UPDATE_ERROR,
+    LOCAL_ALERT_SHADOW_REG_STORAGE_ERROR,
+    LOCAL_ALERT_COUNT,
+};
+
+typedef enum {
+    STATE_IDLE,
+    STATE_TIMEOUT,
+    STATE_FSMERROR,
+    STATE_TERMINAL,
+    STATE_PHASE0,
+    STATE_PHASE1,
+    STATE_PHASE2,
+    STATE_PHASE3,
+    STATE_COUNT,
+} OtAlertAClassState;
+
+typedef enum {
+    OT_ALERT_CLOCK_SRC_IO,
+    OT_ALERT_CLOCK_SRC_EDN,
+    OT_ALERT_CLOCK_SRC_COUNT
+} OtAonTimerClockSrc;
+
+struct OtAlertState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ *irqs;
+    IbexIRQ *esc_txs;
+    OtAlertScheduler *schedulers;
+
+    OtAlertRegs regs; /* not ordered by register index */
+    OtAlertAccess *access_table; /* ordered by register index */
+    char **reg_names; /* ordered by register index */
+    unsigned reg_count; /* total count of registers */
+    unsigned reg_aclass_pos; /* index of the first register of OtAlertAClass */
+    uint32_t pclks[OT_ALERT_CLOCK_SRC_COUNT];
+    const char *clock_src_names[OT_ALERT_CLOCK_SRC_COUNT];
+
+    char *ot_id;
+    OtEDNState *edn;
+    char *clock_names[OT_ALERT_CLOCK_SRC_COUNT];
+    DeviceState *clock_src;
+    uint16_t n_alerts;
+    uint8_t edn_ep;
+    uint8_t n_low_power_groups;
+    uint8_t n_classes;
+};
+
+struct OtAlertClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+/* clang-format off */
+#define ST_NAME_ENTRY(_name_) [STATE_##_name_] = stringify(_name_)
+#define ST_NAME(_st_) ((_st_) < ARRAY_SIZE(ST_NAMES) ? ST_NAMES[(_st_)] : "?")
+
+static const char *ST_NAMES[] = {
+    ST_NAME_ENTRY(IDLE),
+    ST_NAME_ENTRY(TIMEOUT),
+    ST_NAME_ENTRY(FSMERROR),
+    ST_NAME_ENTRY(TERMINAL),
+    ST_NAME_ENTRY(PHASE0),
+    ST_NAME_ENTRY(PHASE1),
+    ST_NAME_ENTRY(PHASE2),
+    ST_NAME_ENTRY(PHASE3),
+};
+#undef ST_NAME_ENTRY
+
+#define R_ACC_MPA(_r_, _w_, _m_, _p_, _u_) (OtAlertAccess) { \
+    .read = &ot_alert_reg_ ## _r_, \
+    .write = &ot_alert_reg_ ## _w_, \
+    .mask = (_m_), \
+    .protect = (_p_), \
+    .wpost = (_u_) \
+}
+/* clang-format on */
+#define R_ACC_MP(_r_, _w_, _m_, _p_) R_ACC_MPA(_r_, _w_, _m_, _p_, 0)
+#define R_ACC_M_IRQ(_r_, _w_, _m_) \
+    R_ACC_MPA(_r_, _w_, _m_, 0, BIT(PWA_UPDATE_IRQ))
+#define R_ACC_P(_r_, _w_, _p_) R_ACC_MP(_r_, _w_, UINT32_MAX, _p_)
+#define R_ACC_M(_r_, _w_, _m_) R_ACC_MP(_r_, _w_, _m_, 0)
+#define R_ACC_IRQ(_r_, _w_)    R_ACC_M_IRQ(_r_, _w_, UINT32_MAX)
+#define R_ACC(_r_, _w_)        R_ACC_M(_r_, _w_, UINT32_MAX)
+
+#define REG_NAME_LENGTH 36u /* > "CLASS_X_CRASHDUMP_TRIGGER_SHADOWED" */
+
+#define REG_NAME(_s_, _reg_) \
+    ((_reg_) < (_s_)->reg_count ? (_s_)->reg_names[(_reg_)] : "?")
+#define CREATE_NAME_REGISTER(_s_, _reg_) \
+    strncpy((_s_)->reg_names[R_##_reg_], stringify(_reg_), REG_NAME_LENGTH - 1)
+#define CREATE_NAME_REG_IX_AT(_s_, _off_, _ix_, _reg_) \
+    do { \
+        int l = snprintf((_s_)->reg_names[(_off_)], REG_NAME_LENGTH, \
+                         stringify(_reg_) "_%02u", (_ix_)); \
+        g_assert((unsigned)l < REG_NAME_LENGTH); \
+    } while (0)
+#define CREATE_NAME_REG_CLS_AT(_s_, _off_, _ix_, _reg_) \
+    do { \
+        int l = snprintf((_s_)->reg_names[(_off_)], REG_NAME_LENGTH, \
+                         "CLASS_%c_" stringify(_reg_), 'A' + (_ix_)); \
+        g_assert((unsigned)l < REG_NAME_LENGTH); \
+    } while (0)
+#undef ALERT_SHOW_OT_ID_REG_NAME /* define as ot_id string here */
+
+static unsigned
+ot_alert_get_nclass_from_reg(const OtAlertState *s, unsigned reg)
+{
+    g_assert(reg >= s->reg_aclass_pos && reg < s->reg_count);
+    unsigned nclass = (reg - s->reg_aclass_pos) / REG_COUNT(OtAlertAClass);
+    g_assert(nclass < s->n_classes);
+    return nclass;
+}
+
+static OtAlertAClassState
+ot_alert_get_class_state(const OtAlertState *s, unsigned nclass)
+{
+    const OtAlertAClass *aclass = &s->regs.classes[nclass];
+
+    return DVAL(aclass->state);
+}
+
+static void ot_alert_set_class_state(OtAlertState *s, unsigned nclass,
+                                     OtAlertAClassState state)
+{
+    trace_ot_alert_set_class_state(s->ot_id, ACLASS(nclass),
+                                   ST_NAME(DVAL(s->regs.classes[nclass].state)),
+                                   ST_NAME(state));
+
+    g_assert(state >= 0 && state < STATE_COUNT);
+
+    DVAL(s->regs.classes[nclass].state) = state;
+}
+
+static void ot_alert_update_irqs(OtAlertState *s)
+{
+    uint32_t level = DVAL(s->regs.intr->state) & DVAL(s->regs.intr->enable);
+
+    trace_ot_alert_irqs(s->ot_id, DVAL(s->regs.intr->state),
+                        DVAL(s->regs.intr->enable), level);
+    for (unsigned ix = 0; ix < s->n_classes; ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((level >> ix) & 0x1));
+    }
+}
+
+static uint32_t ot_alert_reg_write_only(OtAlertState *s, unsigned reg)
+{
+    (void)s;
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%03x\n", __func__,
+                  (unsigned)(reg * sizeof(uint32_t)));
+    return 0;
+}
+
+static void ot_alert_reg_read_only(OtAlertState *s, unsigned reg,
+                                   uint32_t value)
+{
+    (void)s;
+    (void)value;
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%03x\n", __func__,
+                  (unsigned)(reg * sizeof(uint32_t)));
+}
+
+static uint32_t ot_alert_reg_direct_read(OtAlertState *s, unsigned reg)
+{
+    return DVAL(s->regs.shadow[reg]);
+}
+
+static uint32_t ot_alert_reg_shadow_read(OtAlertState *s, unsigned reg)
+{
+    return ot_shadow_reg_read(&s->regs.shadow[reg]);
+}
+
+static uint32_t ot_alert_reg_esc_count_read(OtAlertState *s, unsigned reg)
+{
+    unsigned nclass = ot_alert_get_nclass_from_reg(s, reg);
+    OtAlertAClass *aclass = &s->regs.classes[nclass];
+    unsigned state = DVAL(aclass->state);
+
+    QEMUTimer *timer = &s->schedulers[nclass].timer;
+
+    uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+    uint64_t expire = timer_expire_time_ns(timer);
+    if (expire == UINT64_MAX) {
+        trace_ot_alert_esc_count(s->ot_id, ACLASS(nclass), ST_NAME(state), 0);
+        return 0;
+    }
+
+    uint32_t cycles;
+
+    switch (state) {
+    case STATE_TIMEOUT:
+        cycles = ot_shadow_reg_peek(&aclass->timeout_cyc_shadowed);
+        break;
+    case STATE_PHASE0:
+    case STATE_PHASE1:
+    case STATE_PHASE2:
+    case STATE_PHASE3:
+        cycles = ot_shadow_reg_peek(
+            &aclass->phase_cyc_shadowed[state - STATE_PHASE0]);
+        break;
+    default:
+        trace_ot_alert_esc_count(s->ot_id, ACLASS(nclass), ST_NAME(state), 0);
+        return 0;
+    }
+
+    uint32_t cnt;
+    if ((expire >= now) && (s->pclks[OT_ALERT_CLOCK_SRC_IO] != 0)) {
+        uint64_t rem64 = muldiv64(expire - now, s->pclks[OT_ALERT_CLOCK_SRC_IO],
+                                  NANOSECONDS_PER_SECOND);
+        uint32_t rem32 = (uint32_t)MIN(rem64, (uint64_t)UINT32_MAX);
+        cnt = (rem32 < cycles) ? cycles - rem32 : 0;
+    } else {
+        cnt = cycles;
+    }
+
+    trace_ot_alert_esc_count(s->ot_id, ACLASS(nclass), ST_NAME(state), cnt);
+
+    return cnt;
+}
+
+static void ot_alert_reg_direct_write(OtAlertState *s, unsigned reg,
+                                      uint32_t value)
+{
+    if ((!s->access_table[reg].protect) ||
+        DVAL(s->regs.shadow[s->access_table[reg].protect]) & 0x1) {
+        value &= s->access_table[reg].mask;
+        DVAL(s->regs.shadow[reg]) = value;
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Register 0x%03x write protected by 0x%03x\n",
+                      __func__, (unsigned)(reg * sizeof(uint32_t)),
+                      (unsigned)(s->access_table[reg].protect *
+                                 sizeof(uint32_t)));
+    }
+}
+
+static void ot_alert_reg_shadow_write(OtAlertState *s, unsigned reg,
+                                      uint32_t value)
+{
+    value &= s->access_table[reg].mask;
+    ot_shadow_reg_write(&s->regs.shadow[reg], value);
+}
+
+static void
+ot_alert_reg_direct_rw0c_write(OtAlertState *s, unsigned reg, uint32_t value)
+{
+    value &= s->access_table[reg].mask;
+    DVAL(s->regs.shadow[reg]) &= value;
+}
+
+static void
+ot_alert_reg_direct_rw1c_write(OtAlertState *s, unsigned reg, uint32_t value)
+{
+    value &= s->access_table[reg].mask;
+    DVAL(s->regs.shadow[reg]) &= ~value;
+}
+
+static void
+ot_alert_reg_intr_state_write(OtAlertState *s, unsigned reg, uint32_t value)
+{
+    value &= s->access_table[reg].mask;
+    DVAL(s->regs.shadow[reg]) &= ~value;
+
+    for (unsigned ix = 0; ix < s->n_classes; ix++) {
+        /*
+         * "Software should clear the corresponding interrupt state bit
+         *  INTR_STATE.CLASSn before the timeout expires to avoid escalation."
+         */
+        if (value & (1u << ix)) {
+            OtAlertAClassState state = ot_alert_get_class_state(s, ix);
+            if (state == STATE_TIMEOUT) {
+                if (timer_pending(&s->schedulers[ix].timer)) {
+                    trace_ot_alert_cancel_timeout(s->ot_id, ACLASS(ix));
+                    timer_del(&s->schedulers[ix].timer);
+                }
+                ot_alert_set_class_state(s, ix, STATE_IDLE);
+            } else {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: %s: clearing IRQ for class %c in state %s "
+                              "did not stop escalation",
+                              __func__, s->ot_id, ACLASS(ix), ST_NAME(state));
+            }
+        }
+    }
+}
+
+static void ot_alert_set_class_timer(OtAlertState *s, unsigned nclass,
+                                     uint32_t timeout)
+{
+    if (s->pclks[OT_ALERT_CLOCK_SRC_IO] == 0) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: no clock\n", __func__,
+                      s->ot_id);
+        return;
+    }
+    OtAlertScheduler *atimer = &s->schedulers[nclass];
+    /* TODO: update running schedulers if timeout_cyc_shadowed is updated */
+    int64_t ns = (int64_t)muldiv64(timeout, NANOSECONDS_PER_SECOND,
+                                   s->pclks[OT_ALERT_CLOCK_SRC_IO]);
+
+    OtAlertAClassState state = ot_alert_get_class_state(s, nclass);
+    trace_ot_alert_set_class_timer(s->ot_id, ACLASS(nclass), ST_NAME(state),
+                                   ns / 1000, timeout);
+
+    ns += qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+    if (ns < timer_expire_time_ns(&atimer->timer)) {
+        timer_mod_anticipate_ns(&atimer->timer, ns);
+    }
+}
+
+static bool
+ot_alert_is_escalation_enabled(OtAlertState *s, unsigned nclass, unsigned esc)
+{
+    const OtAlertAClass *aclass = &s->regs.classes[nclass];
+    uint32_t ctrl = ot_shadow_reg_peek(&aclass->ctrl_shadowed);
+
+    bool enable;
+    switch (esc) {
+    case 0:
+        enable = (bool)SHARED_FIELD_EX32(ctrl, CLASS_CTRL_SHADOWED_EN_E0);
+        break;
+    case 1:
+        enable = (bool)SHARED_FIELD_EX32(ctrl, CLASS_CTRL_SHADOWED_EN_E1);
+        break;
+    case 2:
+        enable = (bool)SHARED_FIELD_EX32(ctrl, CLASS_CTRL_SHADOWED_EN_E2);
+        break;
+    case 3:
+        enable = (bool)SHARED_FIELD_EX32(ctrl, CLASS_CTRL_SHADOWED_EN_E3);
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+
+    return enable;
+}
+
+static IbexIRQ *
+ot_alert_get_escalation_output(OtAlertState *s, unsigned nclass, unsigned esc)
+{
+    const OtAlertAClass *aclass = &s->regs.classes[nclass];
+    uint32_t ctrl = ot_shadow_reg_peek(&aclass->ctrl_shadowed);
+
+    uint32_t out;
+    switch (esc) {
+    case 0:
+        out = SHARED_FIELD_EX32(ctrl, CLASS_CTRL_SHADOWED_MAP_E0);
+        break;
+    case 1:
+        out = SHARED_FIELD_EX32(ctrl, CLASS_CTRL_SHADOWED_MAP_E1);
+        break;
+    case 2:
+        out = SHARED_FIELD_EX32(ctrl, CLASS_CTRL_SHADOWED_MAP_E2);
+        break;
+    case 3:
+        out = SHARED_FIELD_EX32(ctrl, CLASS_CTRL_SHADOWED_MAP_E3);
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+
+    return &s->esc_txs[out];
+}
+
+static void ot_alert_clear_alert(OtAlertState *s, unsigned nclass)
+{
+    OtAlertAClass *aclass = &s->regs.classes[nclass];
+    OtAlertAClassState state = DVAL(aclass->state);
+
+    if (state == STATE_FSMERROR) {
+        trace_ot_alert_error(s->ot_id, ACLASS(nclass),
+                             "cannot exit FSMERROR state");
+        return;
+    }
+
+    uint32_t ctrl = ot_shadow_reg_peek(&aclass->ctrl_shadowed);
+
+    if (ctrl & CLASS_CTRL_SHADOWED_LOCK_MASK) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: class %c cannot clear escalation: locked\n",
+                      __func__, s->ot_id, ACLASS(nclass));
+        return;
+    }
+
+    OtAlertScheduler *atimer = &s->schedulers[nclass];
+    timer_del(&atimer->timer);
+    for (unsigned ix = 0; ix < PARAM_N_ESC_SEV; ix++) {
+        IbexIRQ *esc_tx = ot_alert_get_escalation_output(s, nclass, ix);
+        if (ibex_irq_get_level(esc_tx)) {
+            trace_ot_alert_escalation(s->ot_id, ACLASS(nclass), ix, "release");
+        }
+        ibex_irq_set(esc_tx, 0);
+    }
+    /*
+     * "Software can clear CLASSn_ACCUM_CNT with a write to CLASSA_CLR_SHADOWED"
+     */
+    DVAL(aclass->accum_cnt) = 0;
+    ot_alert_set_class_state(s, nclass, STATE_IDLE);
+}
+
+static void ot_alert_configure_phase_cycles(OtAlertState *s, unsigned nclass)
+{
+    OtAlertAClass *aclass = &s->regs.classes[nclass];
+    OtAlertAClassState state = DVAL(aclass->state);
+
+    unsigned phase;
+
+    switch (state) {
+    case STATE_PHASE0:
+    case STATE_PHASE1:
+    case STATE_PHASE2:
+    case STATE_PHASE3:
+        phase = state - STATE_PHASE0;
+        break;
+    default:
+        g_assert_not_reached();
+        return;
+    }
+
+    uint32_t cycles =
+        ot_shadow_reg_peek(&s->regs.classes[nclass].phase_cyc_shadowed[phase]);
+    ot_alert_set_class_timer(s, nclass, cycles);
+}
+
+static void ot_alert_fsm_update(OtAlertState *s, unsigned nclass,
+                                bool from_timer)
+{
+    OtAlertAClass *aclass = &s->regs.classes[nclass];
+    OtAlertAClassState state = DVAL(aclass->state);
+
+    bool accu_trig = DVAL(aclass->accum_cnt) >
+                     ot_shadow_reg_peek(&aclass->accum_thresh_shadowed);
+
+    trace_ot_alert_fsm_update(s->ot_id, ACLASS(nclass), ST_NAME(state),
+                              from_timer, accu_trig);
+
+    IbexIRQ *esc_tx;
+    switch (state) {
+    case STATE_IDLE:
+        if (accu_trig) {
+            unsigned esc = 0;
+            ot_alert_set_class_state(s, nclass, STATE_PHASE0);
+            if (ot_alert_is_escalation_enabled(s, nclass, esc)) {
+                esc_tx = ot_alert_get_escalation_output(s, nclass, esc);
+                ibex_irq_set(esc_tx, true);
+                trace_ot_alert_escalation(s->ot_id, ACLASS(nclass), esc,
+                                          "activate");
+            } else {
+                trace_ot_alert_escalation(s->ot_id, ACLASS(nclass), esc,
+                                          "disabled");
+            }
+            ot_alert_configure_phase_cycles(s, nclass);
+        } else {
+            uint32_t timeout = DVAL(aclass->timeout_cyc_shadowed);
+            if (timeout) {
+                ot_alert_set_class_state(s, nclass, STATE_TIMEOUT);
+                ot_alert_set_class_timer(s, nclass, timeout);
+            }
+        }
+        break;
+    case STATE_TIMEOUT:
+        if (from_timer || accu_trig) {
+            /* cancel timer, even if only useful on accu_trigg */
+            OtAlertScheduler *atimer = &s->schedulers[nclass];
+            timer_del(&atimer->timer);
+            ot_alert_set_class_state(s, nclass, STATE_PHASE0);
+            unsigned esc = 0;
+            if (ot_alert_is_escalation_enabled(s, nclass, esc)) {
+                esc_tx = ot_alert_get_escalation_output(s, nclass, esc);
+                ibex_irq_set(esc_tx, true);
+                trace_ot_alert_escalation(s->ot_id, ACLASS(nclass), esc,
+                                          "activate");
+            } else {
+                trace_ot_alert_escalation(s->ot_id, ACLASS(nclass), esc,
+                                          "disabled");
+            }
+            ot_alert_configure_phase_cycles(s, nclass);
+        }
+        break;
+    case STATE_PHASE0:
+    case STATE_PHASE1:
+    case STATE_PHASE2:
+    case STATE_PHASE3:
+        /* cycle count has reached threshold */
+        if (from_timer) {
+            if (state <= STATE_PHASE2) {
+                /*
+                 * Store escalation output to release before updating state.
+                 * HW raise next escalation output before releasing current one.
+                 * Use a BH to release with on "next" cycle.
+                 */
+                unsigned esc = state - STATE_PHASE0;
+                esc_tx = ot_alert_get_escalation_output(s, nclass, esc);
+                s->schedulers[nclass].esc_tx_release = esc_tx;
+                state += 1;
+                esc = state - STATE_PHASE0;
+                ot_alert_set_class_state(s, nclass, state);
+                if (ot_alert_is_escalation_enabled(s, nclass, esc)) {
+                    esc_tx = ot_alert_get_escalation_output(s, nclass, esc);
+                    ibex_irq_set(esc_tx, true);
+                    trace_ot_alert_escalation(s->ot_id, ACLASS(nclass), esc,
+                                              "activate");
+                } else {
+                    trace_ot_alert_escalation(s->ot_id, ACLASS(nclass), esc,
+                                              "disabled");
+                }
+                ot_alert_configure_phase_cycles(s, nclass);
+                qemu_bh_schedule(s->schedulers[nclass].esc_releaser);
+            } else /* PHASE3 */ {
+                ot_alert_set_class_state(s, nclass, STATE_TERMINAL);
+            }
+        }
+        break;
+    case STATE_TERMINAL:
+        break;
+    case STATE_FSMERROR:
+    default:
+        g_assert_not_reached();
+        break;
+    }
+}
+
+static void ot_alert_timer_expire(void *opaque)
+{
+    OtAlertScheduler *scheduler = opaque;
+    OtAlertState *s = scheduler->parent;
+
+    trace_ot_alert_timer_expire(s->ot_id, ACLASS(scheduler->nclass));
+
+    ot_alert_fsm_update(s, scheduler->nclass, true);
+}
+
+static void ot_alert_release_esc_fn(void *opaque)
+{
+    OtAlertScheduler *scheduler = opaque;
+
+    IbexIRQ *esc_tx = scheduler->esc_tx_release;
+    g_assert(esc_tx);
+
+    if (ibex_irq_get_level(esc_tx)) {
+        OtAlertState *s = scheduler->parent;
+        unsigned ix = (unsigned)(uintptr_t)(esc_tx - &s->esc_txs[0]);
+        trace_ot_alert_escalation(s->ot_id, ACLASS(scheduler->nclass), ix,
+                                  "release");
+    }
+    ibex_irq_set(esc_tx, false);
+    scheduler->esc_tx_release = NULL;
+}
+
+static void ot_alert_signal_tx(void *opaque, int n, int level)
+{
+    OtAlertState *s = opaque;
+
+    unsigned alert = (unsigned)n;
+
+    g_assert(alert < s->n_alerts);
+
+    OtAlertArrays *alerts = &s->regs.alerts;
+    bool alert_en = ot_shadow_reg_peek(&alerts->en_shadowed[alert]);
+
+    trace_ot_alert_signal_tx(s->ot_id, alert, (bool)level, alert_en);
+
+    if (!alert_en || !level) {
+        /* releasing the alert does not clear it */
+        return;
+    }
+
+    DVAL(alerts->cause[alert]) |= ALERT_CAUSE_EN_MASK;
+
+    unsigned nclass = ot_shadow_reg_peek(&alerts->class_shadowed[alert]);
+
+    OtAlertAClass *aclass = &s->regs.classes[nclass];
+
+    uint32_t ac_ctrl = ot_shadow_reg_peek(&aclass->ctrl_shadowed);
+    bool class_en = (bool)(ac_ctrl & CLASS_CTRL_SHADOWED_EN_MASK);
+
+    trace_ot_alert_signal_class(s->ot_id, alert, ACLASS(nclass), class_en);
+
+    DVAL(s->regs.intr->state) |= 1u << nclass;
+
+    if (class_en) {
+        /* saturate (no roll over) */
+        if (DVAL(aclass->accum_cnt) < CLASS_ACCUM_CNT_MASK) {
+            DVAL(aclass->accum_cnt) += 1u;
+        }
+
+        ot_alert_fsm_update(s, nclass, false);
+    }
+
+    ot_alert_update_irqs(s);
+}
+
+static void ot_alert_clock_input(void *opaque, int irq, int level)
+{
+    OtAlertState *s = opaque;
+
+    g_assert((unsigned)irq < OT_ALERT_CLOCK_SRC_COUNT);
+
+    s->pclks[irq] = (unsigned)level;
+
+    /* TODO: reinitialize timers on PCLK change */
+}
+
+static uint64_t ot_alert_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtAlertState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    if (reg >= s->reg_count) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid register 0x%03x\n",
+                      __func__, (uint32_t)addr);
+        return 0;
+    }
+
+    val32 = (*s->access_table[reg].read)(s, reg);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_alert_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(s, reg),
+                               val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_alert_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                unsigned size)
+{
+    OtAlertState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_alert_io_write(s->ot_id, (uint32_t)addr, REG_NAME(s, reg), val32,
+                            pc);
+
+    if (reg >= s->reg_count) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid register 0x%03x\n",
+                      __func__, (uint32_t)addr);
+        return;
+    }
+
+    (*s->access_table[reg].write)(s, reg, val32);
+
+    if (s->access_table[reg].wpost & BIT(PWA_UPDATE_IRQ)) {
+        ot_alert_update_irqs(s);
+    }
+
+    if (s->access_table[reg].wpost & BIT(PWA_CLEAR_ALERT)) {
+        unsigned nclass = ot_alert_get_nclass_from_reg(s, reg);
+        ot_alert_clear_alert(s, nclass);
+    }
+};
+
+static void ot_alert_fill_access_table(OtAlertState *s)
+{
+    OtAlertAccess *table = s->access_table;
+
+    table[R_INTR_STATE] = R_ACC_IRQ(direct_read, intr_state_write);
+    table[R_INTR_ENABLE] = R_ACC_IRQ(direct_read, direct_write);
+    table[R_INTR_TEST] = R_ACC(write_only, direct_write);
+    table[R_PING_TIMER_REGWEN] = R_ACC(direct_read, direct_write);
+    table[R_PING_TIMEOUT_CYC_SHADOWED] = R_ACC(shadow_read, shadow_write);
+    table[R_PING_TIMER_EN_SHADOWED] = R_ACC(shadow_read, shadow_write);
+    OtShadowReg *first_var_reg = s->regs.alerts.regwen;
+
+    unsigned offset = (unsigned)(first_var_reg - &s->regs.shadow[0]);
+
+    /* ALERT_REGWEN */
+    for (unsigned ix = 0; ix < s->n_alerts; ix++) {
+        table[offset + ix] =
+            R_ACC_M(direct_read, direct_rw0c_write, ALERT_REGWEN_EN_MASK);
+    }
+    offset += s->n_alerts;
+
+    /* ALERT_EN_SHADOWED */
+    for (unsigned ix = 0; ix < s->n_alerts; ix++) {
+        table[offset + ix] =
+            R_ACC_M(shadow_read, shadow_write, ALERT_EN_SHADOWED_EN_MASK);
+    }
+    offset += s->n_alerts;
+
+    /* ALERT_CLASS_SHADOWED */
+    for (unsigned ix = 0; ix < s->n_alerts; ix++) {
+        table[offset + ix] =
+            R_ACC_M(shadow_read, shadow_write, s->n_classes - 1u);
+    }
+    offset += s->n_alerts;
+
+    /* ALERT_CAUSE */
+    for (unsigned ix = 0; ix < s->n_alerts; ix++) {
+        table[offset + ix] =
+            R_ACC_M(direct_read, direct_rw1c_write, ALERT_CAUSE_EN_MASK);
+    }
+    offset += s->n_alerts;
+
+    /* LOC_ALERT_REGWEN */
+    for (unsigned ix = 0; ix < LOCAL_ALERT_COUNT; ix++) {
+        table[offset + ix] =
+            R_ACC_M(direct_read, direct_rw0c_write, LOC_ALERT_REGWEN_EN_MASK);
+    }
+    offset += LOCAL_ALERT_COUNT;
+
+    /* LOC_ALERT_EN_SHADOWED */
+    for (unsigned ix = 0; ix < LOCAL_ALERT_COUNT; ix++) {
+        table[offset + ix] =
+            R_ACC_M(shadow_read, shadow_write, LOC_ALERT_EN_SHADOWED_EN_MASK);
+    }
+    offset += LOCAL_ALERT_COUNT;
+
+    /* LOC_ALERT_CLASS_SHADOWED */
+    for (unsigned ix = 0; ix < LOCAL_ALERT_COUNT; ix++) {
+        table[offset + ix] =
+            R_ACC_M(shadow_read, shadow_write, s->n_classes - 1u);
+    }
+    offset += LOCAL_ALERT_COUNT;
+
+    /* LOC_ALERT_CAUSE */
+    for (unsigned ix = 0; ix < LOCAL_ALERT_COUNT; ix++) {
+        table[offset + ix] =
+            R_ACC_M(direct_read, direct_rw1c_write, LOC_ALERT_CAUSE_EN_MASK);
+    }
+    offset += LOCAL_ALERT_COUNT;
+
+    for (unsigned ix = 0; ix < s->n_classes; ix++) {
+        /* CLASS_REGWEN */
+        unsigned regwen = offset;
+        table[offset++] =
+            R_ACC_M(direct_read, direct_rw0c_write, CLASS_REGWEN_EN_MASK);
+
+        /* CLASS_CTRL_SHADOWED */
+        table[offset++] = R_ACC_MP(shadow_read, shadow_write,
+                                   CLASS_CTRL_SHADOWED_MASK, regwen);
+
+        /* CLASS_CLR_REGWEN */
+        unsigned clr_regwen = offset;
+        table[offset++] =
+            R_ACC_M(direct_read, direct_rw0c_write, CLASS_CLR_REGWEN_EN_MASK);
+
+        /* CLASS_CLR_SHADOWED */
+        table[offset++] =
+            R_ACC_MPA(shadow_read, shadow_write, CLASS_CLR_SHADOWED_EN_MASK,
+                      clr_regwen, BIT(PWA_CLEAR_ALERT));
+
+        /* CLASS_ACCUM_CNT */
+        table[offset++] = R_ACC(direct_read, read_only);
+
+        /* CLASS_ACCUM_THRESH_SHADOWED */
+        table[offset++] =
+            R_ACC_MP(shadow_read, shadow_write, UINT16_MAX, regwen);
+
+        /* CLASS_TIMEOUT_CYC_SHADOWED */
+        table[offset++] = R_ACC_P(shadow_read, shadow_write, regwen);
+
+        /* CLASS_CRASHDUMP_TRIGGER_SHADOWED */
+        table[offset++] =
+            R_ACC_MP(shadow_read, shadow_write,
+                     CLASS_CRASHDUMP_TRIGGER_SHADOWED_MASK, regwen);
+
+        /* CLASS_PHASE0_CYC_SHADOWED */
+        table[offset++] = R_ACC_P(shadow_read, shadow_write, regwen);
+
+        /* CLASS_PHASE1_CYC_SHADOWED */
+        table[offset++] = R_ACC_P(shadow_read, shadow_write, regwen);
+
+        /* CLASS_PHASE2_CYC_SHADOWED */
+        table[offset++] = R_ACC_P(shadow_read, shadow_write, regwen);
+
+        /* CLASS_PHASE3_CYC_SHADOWED */
+        table[offset++] = R_ACC_P(shadow_read, shadow_write, regwen);
+
+        /* CLASS_ESC_CNT */
+        table[offset++] = R_ACC(esc_count_read, read_only);
+
+        /* CLASS_STATE */
+        table[offset++] = R_ACC(direct_read, read_only);
+    }
+
+    g_assert(offset == s->reg_count);
+}
+
+static const Property ot_alert_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtAlertState, ot_id),
+    DEFINE_PROP_UINT16("n_alerts", OtAlertState, n_alerts, 0),
+    DEFINE_PROP_UINT8("n_lpg", OtAlertState, n_low_power_groups, 1u),
+    DEFINE_PROP_UINT8("n_classes", OtAlertState, n_classes, 4u),
+    DEFINE_PROP_STRING("clock-name", OtAlertState,
+                       clock_names[OT_ALERT_CLOCK_SRC_IO]),
+    DEFINE_PROP_STRING("clock-name-edn", OtAlertState,
+                       clock_names[OT_ALERT_CLOCK_SRC_EDN]),
+    DEFINE_PROP_LINK("clock-src", OtAlertState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+    DEFINE_PROP_LINK("edn", OtAlertState, edn, TYPE_OT_EDN, OtEDNState *),
+    DEFINE_PROP_UINT8("edn-ep", OtAlertState, edn_ep, UINT8_MAX),
+};
+
+static const MemoryRegionOps ot_alert_regs_ops = {
+    .read = &ot_alert_regs_read,
+    .write = &ot_alert_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_alert_reset_enter(Object *obj, ResetType type)
+{
+    OtAlertClass *c = OT_ALERT_GET_CLASS(obj);
+    OtAlertState *s = OT_ALERT(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    for (unsigned ix = 0; ix < s->n_classes; ix++) {
+        qemu_bh_cancel(s->schedulers[ix].esc_releaser);
+        timer_del(&s->schedulers[ix].timer);
+    }
+
+    memset(s->regs.shadow, 0, sizeof(OtShadowReg) * s->reg_count);
+
+    DVAL(s->regs.ping->timer_regwen) = R_PING_TIMER_REGWEN_EN_MASK;
+    ot_shadow_reg_init(&s->regs.ping->timeout_cyc_shadowed, 256u);
+    for (unsigned ix = 0; ix < s->n_alerts; ix++) {
+        /* direct register */
+        DVAL(s->regs.alerts.regwen[ix]) = ALERT_REGWEN_EN_MASK;
+    }
+    for (unsigned ix = 0; ix < LOCAL_ALERT_COUNT; ix++) {
+        /* direct register */
+        DVAL(s->regs.loc_alerts.regwen[ix]) = LOC_ALERT_REGWEN_EN_MASK;
+    }
+    for (unsigned ix = 0; ix < s->n_classes; ix++) {
+        DVAL(s->regs.classes[ix].regwen) = CLASS_REGWEN_EN_MASK;
+        ot_shadow_reg_init(&s->regs.classes[ix].ctrl_shadowed, 0x393cu);
+        DVAL(s->regs.classes[ix].clr_regwen) = CLASS_CLR_REGWEN_EN_MASK;
+    }
+
+    ot_alert_update_irqs(s);
+
+    for (unsigned ix = 0; ix < OT_ALERT_CLOCK_SRC_COUNT; ix++) {
+        if (s->clock_src_names[ix]) {
+            continue;
+        }
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_names[ix] = ic->get_clock_source(ii, s->clock_names[ix],
+                                                      DEVICE(s), &error_fatal);
+        qemu_irq in_irq =
+            qdev_get_gpio_in_named(DEVICE(s), "clock-in", (int)ix);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_names[ix], 0,
+                                    in_irq);
+    }
+}
+
+static void ot_alert_realize(DeviceState *dev, Error **errp)
+{
+    (void)errp;
+
+    OtAlertState *s = OT_ALERT(dev);
+
+    g_assert(s->ot_id);
+    g_assert(s->n_alerts != 0);
+    g_assert(s->n_classes > 0 && s->n_classes <= 32);
+    for (unsigned ix = 0; ix < OT_ALERT_CLOCK_SRC_COUNT; ix++) {
+        g_assert(s->clock_names[ix]);
+    }
+    g_assert(s->clock_src);
+    OBJECT_CHECK(IbexClockSrcIf, s->clock_src, TYPE_IBEX_CLOCK_SRC_IF);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_alert_clock_input, "clock-in",
+                            OT_ALERT_CLOCK_SRC_COUNT);
+
+    size_t size = sizeof(OtAlertIntr) + sizeof(OtAlertPing) +
+                  sizeof(OtAlertTemplate) * s->n_alerts +
+                  sizeof(OtAlertTemplate) * LOCAL_ALERT_COUNT +
+                  sizeof(OtAlertAClass) * s->n_classes;
+
+    memory_region_init_io(&s->mmio, OBJECT(dev), &ot_alert_regs_ops, s,
+                          TYPE_OT_ALERT, size);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->irqs = g_new0(IbexIRQ, s->n_classes);
+    for (unsigned ix = 0; ix < s->n_classes; ix++) {
+        ibex_sysbus_init_irq(OBJECT(dev), &s->irqs[ix]);
+    }
+
+    s->esc_txs = g_new0(IbexIRQ, PARAM_N_ESC_SEV);
+    ibex_qdev_init_irqs(OBJECT(dev), s->esc_txs, OT_ALERT_ESCALATE,
+                        PARAM_N_ESC_SEV);
+
+    qdev_init_gpio_in_named(dev, &ot_alert_signal_tx, OT_DEVICE_ALERT,
+                            s->n_alerts);
+
+    s->schedulers = g_new0(OtAlertScheduler, s->n_classes);
+    for (unsigned ix = 0; ix < s->n_classes; ix++) {
+        s->schedulers[ix].parent = s;
+        s->schedulers[ix].nclass = ix;
+        timer_init_full(&s->schedulers[ix].timer, NULL, OT_VIRTUAL_CLOCK,
+                        SCALE_NS, 0, &ot_alert_timer_expire,
+                        &s->schedulers[ix]);
+        s->schedulers[ix].esc_releaser =
+            qemu_bh_new(&ot_alert_release_esc_fn, &s->schedulers[ix]);
+        s->schedulers[ix].esc_tx_release = NULL;
+    }
+
+    s->reg_count = size / sizeof(OtShadowReg);
+    s->regs.shadow = g_new0(OtShadowReg, s->reg_count);
+    s->access_table = g_new0(OtAlertAccess, s->reg_count);
+    s->reg_names = g_new0(char *, s->reg_count);
+
+    OtShadowReg *reg = s->regs.shadow;
+    s->regs.intr = (OtAlertIntr *)reg;
+    reg += REG_COUNT(OtAlertIntr);
+    s->regs.ping = (OtAlertPing *)reg;
+    reg += REG_COUNT(OtAlertPing);
+    s->regs.alerts.regwen = reg;
+    reg += s->n_alerts;
+    s->regs.alerts.en_shadowed = reg;
+    reg += s->n_alerts;
+    s->regs.alerts.class_shadowed = reg;
+    reg += s->n_alerts;
+    s->regs.alerts.cause = reg;
+    reg += s->n_alerts;
+    s->regs.loc_alerts.regwen = reg;
+    reg += LOCAL_ALERT_COUNT;
+    s->regs.loc_alerts.en_shadowed = reg;
+    reg += LOCAL_ALERT_COUNT;
+    s->regs.loc_alerts.class_shadowed = reg;
+    reg += LOCAL_ALERT_COUNT;
+    s->regs.loc_alerts.cause = reg;
+    reg += LOCAL_ALERT_COUNT;
+    s->regs.classes = (OtAlertAClass *)reg;
+    s->reg_aclass_pos = (unsigned)(uintptr_t)(reg - s->regs.shadow);
+    reg += REG_COUNT(OtAlertAClass) * s->n_classes;
+
+    g_assert(reg - s->regs.shadow == s->reg_count);
+
+    char *name_buf = g_new0(char, (size_t)(REG_NAME_LENGTH * s->reg_count));
+    for (unsigned ix = 0; ix < s->reg_count;
+         ix++, name_buf += REG_NAME_LENGTH) {
+        s->reg_names[ix] = name_buf;
+    }
+    unsigned nreg = 0;
+    g_assert(s->reg_count > REG_COUNT(OtAlertIntr) + REG_COUNT(OtAlertPing));
+    CREATE_NAME_REGISTER(s, INTR_STATE);
+    CREATE_NAME_REGISTER(s, INTR_ENABLE);
+    CREATE_NAME_REGISTER(s, INTR_TEST);
+    nreg += REG_COUNT(OtAlertIntr);
+    CREATE_NAME_REGISTER(s, PING_TIMER_REGWEN);
+    CREATE_NAME_REGISTER(s, PING_TIMEOUT_CYC_SHADOWED);
+    CREATE_NAME_REGISTER(s, PING_TIMER_EN_SHADOWED);
+    nreg += REG_COUNT(OtAlertPing);
+    for (unsigned ix = 0; ix < s->n_alerts; ix++) {
+        CREATE_NAME_REG_IX_AT(s, nreg + s->n_alerts * 0u + ix, ix,
+                              ALERT_REGWEN);
+        CREATE_NAME_REG_IX_AT(s, nreg + s->n_alerts * 1u + ix, ix,
+                              ALERT_EN_SHADOWED);
+        CREATE_NAME_REG_IX_AT(s, nreg + s->n_alerts * 2u + ix, ix,
+                              ALERT_CLASS_SHADOWED);
+        CREATE_NAME_REG_IX_AT(s, nreg + s->n_alerts * 3u + ix, ix, ALERT_CAUSE);
+    }
+    nreg += REG_COUNT(OtAlertTemplate) * s->n_alerts;
+    for (unsigned ix = 0; ix < LOCAL_ALERT_COUNT; ix++) {
+        CREATE_NAME_REG_IX_AT(s, nreg + LOCAL_ALERT_COUNT * 0u + ix, ix,
+                              LOC_ALERT_REGWEN);
+        CREATE_NAME_REG_IX_AT(s, nreg + LOCAL_ALERT_COUNT * 1u + ix, ix,
+                              LOC_ALERT_EN_SHADOWED);
+        CREATE_NAME_REG_IX_AT(s, nreg + LOCAL_ALERT_COUNT * 2u + ix, ix,
+                              LOC_ALERT_CLASS_SHADOWED);
+        CREATE_NAME_REG_IX_AT(s, nreg + LOCAL_ALERT_COUNT * 3u + ix, ix,
+                              LOC_ALERT_CAUSE);
+    }
+    nreg += REG_COUNT(OtAlertTemplate) * LOCAL_ALERT_COUNT;
+    for (unsigned ix = 0; ix < s->n_classes; ix++) {
+        CREATE_NAME_REG_CLS_AT(s, nreg + 0u, ix, REGWEN);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 1u, ix, CTRL_SHADOWED);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 2u, ix, CLR_REGWEN);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 3u, ix, CLR_SHADOWED);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 4u, ix, ACCUM_CNT);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 5u, ix, ACCUM_THRESH_SHADOWED);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 6u, ix, TIMEOUT_CYC_SHADOWED);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 7u, ix, CRASHDUMP_TRIGGER_SHADOWED);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 8u, ix, PHASE0_CYC_SHADOWED);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 9u, ix, PHASE1_CYC_SHADOWED);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 10u, ix, PHASE2_CYC_SHADOWED);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 11u, ix, PHASE3_CYC_SHADOWED);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 12u, ix, ESC_CNT);
+        CREATE_NAME_REG_CLS_AT(s, nreg + 13u, ix, STATE);
+        nreg += 14u;
+    }
+    g_assert(nreg == s->reg_count);
+
+#ifdef ALERT_SHOW_OT_ID_REG_NAME
+    if (!strcmp(s->ot_id, ALERT_SHOW_OT_ID_REG_NAME)) {
+        fprintf(stderr, "nreg %u regcount %u\n", nreg, s->reg_count);
+        for (unsigned ix = 0; ix < nreg; ix++) {
+            fprintf(stderr, "reg[%03x]: %s\n", ix, s->reg_names[ix]);
+        }
+    }
+#endif
+
+    ot_alert_fill_access_table(s);
+}
+
+static void ot_alert_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_alert_realize;
+    device_class_set_props(dc, ot_alert_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtAlertClass *ac = OT_ALERT_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_alert_reset_enter, NULL, NULL,
+                                       &ac->parent_phases);
+}
+
+static const TypeInfo ot_alert_info = {
+    .name = TYPE_OT_ALERT,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtAlertState),
+    .class_size = sizeof(OtAlertClass),
+    .class_init = &ot_alert_class_init,
+};
+
+static void ot_alert_register_types(void)
+{
+    type_register_static(&ot_alert_info);
+}
+
+type_init(ot_alert_register_types);
diff --git a/hw/opentitan/ot_aon_timer.c b/hw/opentitan/ot_aon_timer.c
new file mode 100644
index 0000000000000..ac9e033a70cc5
--- /dev/null
+++ b/hw/opentitan/ot_aon_timer.c
@@ -0,0 +1,675 @@
+/*
+ * QEMU OpenTitan AON Timer device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Currently missing from implementation:
+ *   - "pause in sleep" and "pause during escalation" features
+ *     (i.e. "counter-run" and "low-power" inputs)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_aon_timer.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x00u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(WKUP_CTRL, 0x04u)
+    FIELD(WKUP_CTRL, ENABLE, 0u, 1u)
+    FIELD(WKUP_CTRL, PRESCALER, 1u, 12u)
+REG32(WKUP_THOLD_HI, 0x08u)
+REG32(WKUP_THOLD_LO, 0x0cu)
+REG32(WKUP_COUNT_HI, 0x10u)
+REG32(WKUP_COUNT_LO, 0x14u)
+REG32(WDOG_REGWEN, 0x18u)
+    FIELD(WDOG_REGWEN, REGWEN, 0u, 1u)
+REG32(WDOG_CTRL, 0x1cu)
+    FIELD(WDOG_CTRL, ENABLE, 0u, 1u)
+    FIELD(WDOG_CTRL, PAUSE_IN_SLEEP, 1u, 1u)
+REG32(WDOG_BARK_THOLD, 0x20u)
+REG32(WDOG_BITE_THOLD, 0x24u)
+REG32(WDOG_COUNT, 0x28u)
+REG32(INTR_STATE, 0x2cu)
+    SHARED_FIELD(INTR_WKUP_TIMER_EXPIRED, 0u, 1u)
+    SHARED_FIELD(INTR_WDOG_TIMER_BARK, 1u, 1u)
+REG32(INTR_TEST, 0x30u)
+REG32(WKUP_CAUSE, 0x34u)
+    FIELD(WKUP_CAUSE, CAUSE, 0u, 1u)
+/* clang-format on */
+
+#define INTR_MASK (INTR_WKUP_TIMER_EXPIRED_MASK | INTR_WDOG_TIMER_BARK_MASK)
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_WKUP_CAUSE)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char REG_NAMES[REGS_COUNT][20u] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(WKUP_CTRL),
+    REG_NAME_ENTRY(WKUP_THOLD_HI),
+    REG_NAME_ENTRY(WKUP_THOLD_LO),
+    REG_NAME_ENTRY(WKUP_COUNT_HI),
+    REG_NAME_ENTRY(WKUP_COUNT_LO),
+    REG_NAME_ENTRY(WDOG_REGWEN),
+    REG_NAME_ENTRY(WDOG_CTRL),
+    REG_NAME_ENTRY(WDOG_BARK_THOLD),
+    REG_NAME_ENTRY(WDOG_BITE_THOLD),
+    REG_NAME_ENTRY(WDOG_COUNT),
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(WKUP_CAUSE),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+typedef enum {
+    OT_AON_TIMER_CLOCK_SRC_IO,
+    OT_AON_TIMER_CLOCK_SRC_AON,
+    OT_AON_TIMER_CLOCK_SRC_COUNT
+} OtAonTimerClockSrc;
+
+struct OtAonTimerState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+
+    IbexIRQ irq_wkup;
+    IbexIRQ irq_bark;
+    IbexIRQ nmi_bark;
+    IbexIRQ pwrmgr_wkup;
+    IbexIRQ pwrmgr_bite;
+    IbexIRQ alert;
+
+    QEMUTimer *wkup_timer;
+    QEMUTimer *wdog_timer;
+
+    uint32_t regs[REGS_COUNT];
+
+    int64_t wkup_origin_ns;
+    int64_t wdog_origin_ns;
+    bool wdog_bite;
+    uint32_t pclks[OT_AON_TIMER_CLOCK_SRC_COUNT];
+    const char *clock_src_names[OT_AON_TIMER_CLOCK_SRC_COUNT];
+
+    char *ot_id;
+    char *clock_names[OT_AON_TIMER_CLOCK_SRC_COUNT];
+    DeviceState *clock_src;
+};
+
+struct OtAonTimerClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static uint64_t
+ot_aon_timer_ns_to_ticks(OtAonTimerState *s, uint32_t prescaler, int64_t ns)
+{
+    uint64_t ticks =
+        muldiv64((uint64_t)ns, s->pclks[OT_AON_TIMER_CLOCK_SRC_AON],
+                 NANOSECONDS_PER_SECOND);
+    return ticks / (prescaler + 1u);
+}
+
+static int64_t
+ot_aon_timer_ticks_to_ns(OtAonTimerState *s, uint32_t prescaler, uint64_t ticks)
+{
+    uint64_t ns = muldiv64(ticks * (prescaler + 1u), NANOSECONDS_PER_SECOND,
+                           s->pclks[OT_AON_TIMER_CLOCK_SRC_AON]);
+    if (ns > INT64_MAX) {
+        return INT64_MAX;
+    }
+    return (int64_t)ns;
+}
+
+static uint64_t ot_aon_timer_get_wkup_count(OtAonTimerState *s, uint64_t now)
+{
+    uint32_t prescaler = FIELD_EX32(s->regs[R_WKUP_CTRL], WKUP_CTRL, PRESCALER);
+    uint64_t wkup_count = ((uint64_t)s->regs[R_WKUP_COUNT_HI] << 32u) |
+                          (uint64_t)s->regs[R_WKUP_COUNT_LO];
+    return wkup_count +
+           ot_aon_timer_ns_to_ticks(s, prescaler,
+                                    (int64_t)(now - s->wkup_origin_ns));
+}
+
+static uint32_t ot_aon_timer_get_wdog_count(OtAonTimerState *s, uint64_t now)
+{
+    int64_t delta = (int64_t)(now - s->wdog_origin_ns);
+    uint64_t ticks = ot_aon_timer_ns_to_ticks(s, 0u, delta);
+
+    return s->regs[R_WDOG_COUNT] + (uint32_t)ticks;
+}
+
+static int64_t ot_aon_timer_compute_next_timeout(OtAonTimerState *s,
+                                                 int64_t now, int64_t delta)
+{
+    int64_t next;
+
+    g_assert(s->pclks[OT_AON_TIMER_CLOCK_SRC_AON]);
+
+    /* wait at least 1 peripheral clock tick */
+    delta = MAX(delta, (int64_t)(NANOSECONDS_PER_SECOND /
+                                 s->pclks[OT_AON_TIMER_CLOCK_SRC_AON]));
+
+    if (sadd64_overflow(now, delta, &next)) {
+        /* we overflowed the timer, just set it as large as we can */
+        return INT64_MAX;
+    }
+
+    return next;
+}
+
+static inline bool ot_aon_timer_is_wkup_enabled(OtAonTimerState *s)
+{
+    return (s->regs[R_WKUP_CTRL] & R_WKUP_CTRL_ENABLE_MASK) != 0;
+}
+
+static inline bool ot_aon_timer_is_wdog_enabled(OtAonTimerState *s)
+{
+    return (s->regs[R_WDOG_CTRL] & R_WDOG_CTRL_ENABLE_MASK) != 0;
+}
+
+static inline bool ot_aon_timer_wdog_register_write_enabled(OtAonTimerState *s)
+{
+    return (s->regs[R_WDOG_REGWEN] & R_WDOG_REGWEN_REGWEN_MASK) != 0;
+}
+
+static void ot_aon_timer_update_alert(OtAonTimerState *s)
+{
+    bool level = s->regs[R_ALERT_TEST] & R_ALERT_TEST_FATAL_FAULT_MASK;
+    ibex_irq_set(&s->alert, level);
+}
+
+static void ot_aon_timer_update_irqs(OtAonTimerState *s)
+{
+    bool wkup = (bool)(s->regs[R_INTR_STATE] & INTR_WKUP_TIMER_EXPIRED_MASK);
+    bool bark = (bool)(s->regs[R_INTR_STATE] & INTR_WDOG_TIMER_BARK_MASK);
+    trace_ot_aon_timer_irqs(s->ot_id, wkup, bark, s->wdog_bite);
+
+    ibex_irq_set(&s->irq_wkup, wkup);
+    ibex_irq_set(&s->irq_bark, bark);
+    ibex_irq_set(&s->nmi_bark, bark);
+    ibex_irq_set(&s->pwrmgr_wkup, wkup);
+    ibex_irq_set(&s->pwrmgr_bite, s->wdog_bite);
+}
+
+static void ot_aon_timer_rearm_wkup(OtAonTimerState *s, bool reset_origin)
+{
+    timer_del(s->wkup_timer);
+
+    if (!s->pclks[OT_AON_TIMER_CLOCK_SRC_AON]) {
+        return;
+    }
+
+    int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+
+    if (reset_origin) {
+        s->wkup_origin_ns = now;
+    }
+
+    /* if not enabled, ignore threshold */
+    if (!ot_aon_timer_is_wkup_enabled(s)) {
+        ot_aon_timer_update_irqs(s);
+        return;
+    }
+
+    uint64_t count = ot_aon_timer_get_wkup_count(s, now);
+    uint64_t threshold = ((uint64_t)s->regs[R_WKUP_THOLD_HI] << 32u) |
+                         (uint64_t)s->regs[R_WKUP_THOLD_LO];
+
+    if (count >= threshold) {
+        s->regs[R_INTR_STATE] |= INTR_WKUP_TIMER_EXPIRED_MASK;
+    } else {
+        uint32_t prescaler =
+            FIELD_EX32(s->regs[R_WKUP_CTRL], WKUP_CTRL, PRESCALER);
+        int64_t delta =
+            ot_aon_timer_ticks_to_ns(s, prescaler, threshold - count);
+        int64_t next = ot_aon_timer_compute_next_timeout(s, now, delta);
+        if (next < INT64_MAX) {
+            timer_mod(s->wkup_timer, next);
+        }
+    }
+
+    ot_aon_timer_update_irqs(s);
+}
+
+static void ot_aon_timer_wkup_cb(void *opaque)
+{
+    OtAonTimerState *s = opaque;
+    ot_aon_timer_rearm_wkup(s, false);
+}
+
+static void ot_aon_timer_rearm_wdog(OtAonTimerState *s, bool reset_origin)
+{
+    int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+
+    if (!s->pclks[OT_AON_TIMER_CLOCK_SRC_AON]) {
+        return;
+    }
+
+    if (reset_origin) {
+        s->wdog_origin_ns = now;
+    }
+
+    /* if not enabled, ignore threshold */
+    if (!ot_aon_timer_is_wdog_enabled(s)) {
+        timer_del(s->wdog_timer);
+        ot_aon_timer_update_irqs(s);
+        return;
+    }
+
+    uint32_t count = ot_aon_timer_get_wdog_count(s, now);
+    uint32_t bark_threshold = s->regs[R_WDOG_BARK_THOLD];
+    uint32_t bite_threshold = s->regs[R_WDOG_BITE_THOLD];
+    uint32_t threshold;
+    bool pending;
+
+    if (count >= bark_threshold) {
+        s->regs[R_INTR_STATE] |= INTR_WDOG_TIMER_BARK_MASK;
+        threshold = UINT32_MAX;
+        pending = false;
+    } else {
+        threshold = bark_threshold;
+        pending = true;
+    }
+
+    if (count >= bite_threshold) {
+        s->wdog_bite = true;
+    } else {
+        threshold = MIN(threshold, bite_threshold);
+        pending = true;
+    }
+
+    timer_del(s->wdog_timer);
+
+    if (pending) {
+        int64_t delta = ot_aon_timer_ticks_to_ns(s, 0u, threshold - count);
+        int64_t next = ot_aon_timer_compute_next_timeout(s, now, delta);
+        if (next < INT64_MAX) {
+            trace_ot_aon_timer_set_wdog(s->ot_id, now, next);
+            timer_mod(s->wdog_timer, next);
+        }
+    }
+
+    ot_aon_timer_update_irqs(s);
+}
+
+static void ot_aon_timer_wdog_cb(void *opaque)
+{
+    OtAonTimerState *s = opaque;
+    ot_aon_timer_rearm_wdog(s, false);
+}
+
+static void ot_aon_timer_clock_input(void *opaque, int irq, int level)
+{
+    OtAonTimerState *s = opaque;
+
+    g_assert((unsigned)irq < OT_AON_TIMER_CLOCK_SRC_COUNT);
+
+    s->pclks[irq] = (unsigned)level;
+
+    if (irq == OT_AON_TIMER_CLOCK_SRC_AON) {
+        if (!s->pclks[irq]) {
+            timer_del(s->wkup_timer);
+            timer_del(s->wdog_timer);
+        }
+    }
+
+    trace_ot_aon_timer_update_clock(s->ot_id, irq, s->pclks[irq]);
+    /* TODO: @loic: update on-going timer */
+}
+
+
+static uint64_t ot_aon_timer_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtAonTimerState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_WKUP_CTRL:
+    case R_WKUP_THOLD_HI:
+    case R_WKUP_THOLD_LO:
+    case R_WDOG_REGWEN:
+    case R_WDOG_CTRL:
+    case R_WDOG_BARK_THOLD:
+    case R_WDOG_BITE_THOLD:
+    case R_INTR_STATE:
+    case R_WKUP_CAUSE:
+        val32 = s->regs[reg];
+        break;
+    case R_WKUP_COUNT_HI: {
+        int64_t now = ot_aon_timer_is_wkup_enabled(s) ?
+                          qemu_clock_get_ns(OT_VIRTUAL_CLOCK) :
+                          s->wkup_origin_ns;
+        val32 =
+            (uint32_t)(ot_aon_timer_get_wkup_count(s, (uint64_t)now) >> 32u);
+        break;
+    }
+    case R_WKUP_COUNT_LO: {
+        int64_t now = ot_aon_timer_is_wkup_enabled(s) ?
+                          qemu_clock_get_ns(OT_VIRTUAL_CLOCK) :
+                          s->wkup_origin_ns;
+        val32 = (uint32_t)ot_aon_timer_get_wkup_count(s, (uint64_t)now);
+        break;
+    }
+    case R_WDOG_COUNT: {
+        int64_t now = ot_aon_timer_is_wdog_enabled(s) ?
+                          qemu_clock_get_ns(OT_VIRTUAL_CLOCK) :
+                          s->wdog_origin_ns;
+        val32 = ot_aon_timer_get_wdog_count(s, (uint64_t)now);
+        break;
+    }
+    case R_ALERT_TEST:
+    case R_INTR_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_aon_timer_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg),
+                                   val32, pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_aon_timer_write(void *opaque, hwaddr addr, uint64_t value,
+                               unsigned size)
+{
+    OtAonTimerState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)value;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_aon_timer_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                                pc);
+
+    switch (reg) {
+    case R_ALERT_TEST:
+        s->regs[R_ALERT_TEST] |= val32 & R_ALERT_TEST_FATAL_FAULT_MASK;
+        ot_aon_timer_update_alert(s);
+        break;
+    case R_WKUP_CTRL: {
+        uint32_t prev = s->regs[R_WKUP_CTRL];
+        s->regs[R_WKUP_CTRL] =
+            val32 & (R_WKUP_CTRL_ENABLE_MASK | R_WKUP_CTRL_PRESCALER_MASK);
+        uint32_t change = prev ^ s->regs[R_WKUP_CTRL];
+        if (change & R_WKUP_CTRL_ENABLE_MASK) {
+            if (ot_aon_timer_is_wkup_enabled(s)) {
+                /* start timer */
+                ot_aon_timer_rearm_wkup(s, true);
+            } else {
+                /* stop timer */
+                timer_del(s->wkup_timer);
+                if (s->pclks[OT_AON_TIMER_CLOCK_SRC_AON]) {
+                    /* save current count */
+                    int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+                    uint64_t count =
+                        ot_aon_timer_get_wkup_count(s, (uint64_t)now);
+                    s->regs[R_WKUP_COUNT_HI] = (uint32_t)(count >> 32u);
+                    s->regs[R_WKUP_COUNT_LO] = (uint32_t)count;
+                    s->wkup_origin_ns = now;
+                }
+            }
+        }
+        break;
+    }
+    case R_WKUP_THOLD_HI:
+    case R_WKUP_THOLD_LO:
+        s->regs[reg] = val32;
+        ot_aon_timer_rearm_wkup(s, false);
+        break;
+    case R_WKUP_COUNT_HI:
+    case R_WKUP_COUNT_LO:
+        s->regs[reg] = val32;
+        ot_aon_timer_rearm_wkup(s, true);
+        break;
+    case R_WDOG_REGWEN:
+        s->regs[R_WDOG_REGWEN] &= val32 & R_WDOG_REGWEN_REGWEN_MASK; /* rw0c */
+        break;
+    case R_WDOG_CTRL:
+        if (ot_aon_timer_wdog_register_write_enabled(s)) {
+            uint32_t prev = s->regs[R_WDOG_CTRL];
+            s->regs[R_WDOG_CTRL] =
+                val32 &
+                (R_WDOG_CTRL_ENABLE_MASK | R_WDOG_CTRL_PAUSE_IN_SLEEP_MASK);
+            uint32_t change = prev ^ s->regs[R_WDOG_CTRL];
+            if (change & R_WDOG_CTRL_ENABLE_MASK) {
+                if (ot_aon_timer_is_wdog_enabled(s)) {
+                    /* start timer */
+                    ot_aon_timer_rearm_wdog(s, true);
+                } else {
+                    /* stop timer */
+                    timer_del(s->wdog_timer);
+                    if (s->pclks[OT_AON_TIMER_CLOCK_SRC_AON]) {
+                        /* save current count */
+                        int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+                        s->regs[R_WDOG_COUNT] =
+                            ot_aon_timer_get_wdog_count(s, now);
+                        s->wdog_origin_ns = now;
+                    }
+                }
+            }
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "Ignoring write to locked WDOG_CTRL register\n");
+        }
+        break;
+    case R_WDOG_BARK_THOLD:
+    case R_WDOG_BITE_THOLD:
+        if (ot_aon_timer_wdog_register_write_enabled(s)) {
+            s->regs[reg] = val32;
+            ot_aon_timer_rearm_wdog(s, false);
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "Ignoring write to locked %s register\n",
+                          REG_NAME(reg));
+        }
+        break;
+    case R_WDOG_COUNT:
+        s->regs[R_WDOG_COUNT] = val32;
+        ot_aon_timer_rearm_wdog(s, true);
+        break;
+    case R_INTR_STATE: {
+        uint32_t prev = s->regs[R_INTR_STATE];
+        s->regs[R_INTR_STATE] &= ~(val32 & INTR_MASK); /* rw1c */
+        uint32_t change = prev ^ s->regs[R_INTR_STATE];
+        ot_aon_timer_update_irqs(s);
+        /*
+         * schedule the timer for the next peripheral clock tick to check again
+         * for interrupt condition
+         */
+        if (s->pclks[OT_AON_TIMER_CLOCK_SRC_AON]) {
+            int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+            int64_t next = ot_aon_timer_compute_next_timeout(s, now, 0);
+            if (change & INTR_WKUP_TIMER_EXPIRED_MASK) {
+                timer_mod_anticipate(s->wkup_timer, next);
+            }
+            if (change & INTR_WDOG_TIMER_BARK_MASK) {
+                timer_mod_anticipate(s->wdog_timer, next);
+            }
+        }
+        break;
+    }
+    case R_INTR_TEST:
+        s->regs[R_INTR_STATE] |= val32 & INTR_MASK;
+        ot_aon_timer_update_irqs(s);
+        break;
+    case R_WKUP_CAUSE:
+        /* ignore write, in QEMU wkup_cause is always 0 */
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+    }
+}
+
+static const MemoryRegionOps ot_aon_timer_ops = {
+    .read = &ot_aon_timer_read,
+    .write = &ot_aon_timer_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const Property ot_aon_timer_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtAonTimerState, ot_id),
+    DEFINE_PROP_STRING("clock-name", OtAonTimerState,
+                       clock_names[OT_AON_TIMER_CLOCK_SRC_IO]),
+    DEFINE_PROP_STRING("clock-name-aon", OtAonTimerState,
+                       clock_names[OT_AON_TIMER_CLOCK_SRC_AON]),
+    DEFINE_PROP_LINK("clock-src", OtAonTimerState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+};
+
+static void ot_aon_timer_reset_enter(Object *obj, ResetType type)
+{
+    OtAonTimerClass *c = OT_AON_TIMER_GET_CLASS(obj);
+    OtAonTimerState *s = OT_AON_TIMER(obj);
+
+    trace_ot_aon_timer_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->wkup_timer);
+    timer_del(s->wdog_timer);
+
+    memset(s->regs, 0, sizeof(s->regs));
+    s->regs[R_WDOG_REGWEN] = 1u;
+    s->wdog_bite = false;
+
+    ot_aon_timer_update_irqs(s);
+    ot_aon_timer_update_alert(s);
+
+    for (unsigned ix = 0; ix < OT_AON_TIMER_CLOCK_SRC_COUNT; ix++) {
+        if (s->clock_src_names[ix]) {
+            continue;
+        }
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_names[ix] = ic->get_clock_source(ii, s->clock_names[ix],
+                                                      DEVICE(s), &error_fatal);
+        qemu_irq in_irq =
+            qdev_get_gpio_in_named(DEVICE(s), "clock-in", (int)ix);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_names[ix], 0,
+                                    in_irq);
+    }
+}
+
+static void ot_aon_timer_realize(DeviceState *dev, Error **errp)
+{
+    OtAonTimerState *s = OT_AON_TIMER(dev);
+
+    (void)errp;
+
+    g_assert(s->ot_id);
+    for (unsigned ix = 0; ix < OT_AON_TIMER_CLOCK_SRC_COUNT; ix++) {
+        g_assert(s->clock_names[ix]);
+    }
+    g_assert(s->clock_src);
+    OBJECT_CHECK(IbexClockSrcIf, s->clock_src, TYPE_IBEX_CLOCK_SRC_IF);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_aon_timer_clock_input, "clock-in",
+                            OT_AON_TIMER_CLOCK_SRC_COUNT);
+}
+
+static void ot_aon_timer_init(Object *obj)
+{
+    OtAonTimerState *s = OT_AON_TIMER(obj);
+
+    ibex_sysbus_init_irq(obj, &s->irq_wkup);
+    ibex_sysbus_init_irq(obj, &s->irq_bark);
+    ibex_qdev_init_irq(obj, &s->nmi_bark, OT_AON_TIMER_BARK);
+    ibex_qdev_init_irq(obj, &s->pwrmgr_wkup, OT_AON_TIMER_WKUP);
+    ibex_qdev_init_irq(obj, &s->pwrmgr_bite, OT_AON_TIMER_BITE);
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    memory_region_init_io(&s->mmio, obj, &ot_aon_timer_ops, s,
+                          TYPE_OT_AON_TIMER, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    s->wkup_timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_aon_timer_wkup_cb, s);
+    s->wdog_timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_aon_timer_wdog_cb, s);
+}
+
+static void ot_aon_timer_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = ot_aon_timer_realize;
+    device_class_set_props(dc, ot_aon_timer_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtAonTimerClass *ac = OT_AON_TIMER_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_aon_timer_reset_enter, NULL,
+                                       NULL, &ac->parent_phases);
+}
+
+static const TypeInfo ot_aon_timer_info = {
+    .name = TYPE_OT_AON_TIMER,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtAonTimerState),
+    .instance_init = ot_aon_timer_init,
+    .class_size = sizeof(OtAonTimerClass),
+    .class_init = ot_aon_timer_class_init,
+};
+
+static void ot_aon_timer_register_types(void)
+{
+    type_register_static(&ot_aon_timer_info);
+}
+
+type_init(ot_aon_timer_register_types);
diff --git a/hw/opentitan/ot_ast_dj.c b/hw/opentitan/ot_ast_dj.c
new file mode 100644
index 0000000000000..231e04c3e7b88
--- /dev/null
+++ b/hw/opentitan/ot_ast_dj.c
@@ -0,0 +1,621 @@
+/*
+ * QEMU OpenTitan Darjeeling Analog Sensor Top device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: for now, only a minimalist subset of Analog Sensor Top device is
+ *       implemented in order to enable OpenTitan's ROM boot to progress
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/guest-random.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_ast_dj.h"
+#include "hw/opentitan/ot_clock_ctrl.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_noise_src.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(REGA0, 0x0u)
+REG32(REGA1, 0x4u)
+REG32(REGA2, 0x8u)
+REG32(REGA3, 0xcu)
+REG32(REGA4, 0x10u)
+REG32(REGA5, 0x14u)
+REG32(REGA6, 0x18u)
+REG32(REGA7, 0x1cu)
+REG32(REGA8, 0x20u)
+REG32(REGA9, 0x24u)
+REG32(REGA10, 0x28u)
+REG32(REGA11, 0x2cu)
+REG32(REGA12, 0x30u)
+REG32(REGA13, 0x34u)
+REG32(REGA14, 0x38u)
+REG32(REGA15, 0x3cu)
+REG32(REGA16, 0x40u)
+REG32(REGA17, 0x44u)
+REG32(REGA18, 0x48u)
+REG32(REGA19, 0x4cu)
+REG32(REGA20, 0x50u)
+REG32(REGA21, 0x54u)
+REG32(REGA22, 0x58u)
+REG32(REGA23, 0x5cu)
+REG32(REGA24, 0x60u)
+REG32(REGA25, 0x64u)
+REG32(REGA26, 0x68u)
+REG32(REGA27, 0x6cu)
+REG32(REGA28, 0x70u)
+REG32(REGA29, 0x74u)
+REG32(REGA30, 0x78u)
+REG32(REGA31, 0x7cu)
+REG32(REGA32, 0x80u)
+REG32(REGA33, 0x84u)
+REG32(REGA34, 0x88u)
+REG32(REGA35, 0x8cu)
+REG32(REGA36, 0x90u)
+REG32(REGA37, 0x94u)
+REG32(REGAL, 0x98u)
+REG32(REGB0, 0x200u)
+REG32(REGB1, 0x204u)
+REG32(REGB2, 0x208u)
+REG32(REGB3, 0x20cu)
+REG32(REGB4, 0x210u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define RA_LAST_REG (R_REGAL)
+#define REGSA_COUNT (RA_LAST_REG + 1u)
+#define REGSA_SIZE  (REGSA_COUNT * sizeof(uint32_t))
+#define REGA_NAME(_reg_) \
+    ((((_reg_) < REGSA_COUNT) && REGA_NAMES[_reg_]) ? REGA_NAMES[_reg_] : "?")
+
+#define RB_LAST_REG (R_REGB4)
+#define REGSB_COUNT (RB_LAST_REG + 1u)
+#define REGSB_SIZE  (REGSB_COUNT * sizeof(uint32_t))
+#define REGB_NAME(_reg_) \
+    ((((_reg_) < REGSB_COUNT) && REGB_NAMES[_reg_]) ? REGB_NAMES[_reg_] : "?")
+
+#define REGS_SIZE (A_REGB4 + sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((_reg_) >= R_REGB0 ? REGB_NAME((_reg_) - (R_REGB0)) : REGA_NAME(_reg_))
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char REGA_NAMES[REGSA_COUNT][8U] = {
+    REG_NAME_ENTRY(REGA0),  REG_NAME_ENTRY(REGA1),  REG_NAME_ENTRY(REGA2),
+    REG_NAME_ENTRY(REGA3),  REG_NAME_ENTRY(REGA4),  REG_NAME_ENTRY(REGA5),
+    REG_NAME_ENTRY(REGA6),  REG_NAME_ENTRY(REGA7),  REG_NAME_ENTRY(REGA8),
+    REG_NAME_ENTRY(REGA9),  REG_NAME_ENTRY(REGA10), REG_NAME_ENTRY(REGA11),
+    REG_NAME_ENTRY(REGA12), REG_NAME_ENTRY(REGA13), REG_NAME_ENTRY(REGA14),
+    REG_NAME_ENTRY(REGA15), REG_NAME_ENTRY(REGA16), REG_NAME_ENTRY(REGA17),
+    REG_NAME_ENTRY(REGA18), REG_NAME_ENTRY(REGA19), REG_NAME_ENTRY(REGA20),
+    REG_NAME_ENTRY(REGA21), REG_NAME_ENTRY(REGA22), REG_NAME_ENTRY(REGA23),
+    REG_NAME_ENTRY(REGA24), REG_NAME_ENTRY(REGA25), REG_NAME_ENTRY(REGA26),
+    REG_NAME_ENTRY(REGA27), REG_NAME_ENTRY(REGA28), REG_NAME_ENTRY(REGA29),
+    REG_NAME_ENTRY(REGA30), REG_NAME_ENTRY(REGA31), REG_NAME_ENTRY(REGA32),
+    REG_NAME_ENTRY(REGA33), REG_NAME_ENTRY(REGA34), REG_NAME_ENTRY(REGA35),
+    REG_NAME_ENTRY(REGA36), REG_NAME_ENTRY(REGA37), REG_NAME_ENTRY(REGAL),
+};
+
+static const char REGB_NAMES[REGSB_COUNT][6U] = {
+    REG_NAME_ENTRY(REGB0), REG_NAME_ENTRY(REGB1), REG_NAME_ENTRY(REGB2),
+    REG_NAME_ENTRY(REGB3), REG_NAME_ENTRY(REGB4),
+};
+#undef REG_NAME_ENTRY
+
+/* @todo check with HW what is the best default value */
+#define OT_AST_DJ_NOISE_BITRATE_DEFAULT 1000000u /* 1 MHz */
+
+typedef struct {
+    char *name;
+    unsigned frequency;
+    IbexIRQ out;
+    char *irq_name;
+    const DeviceState *sink;
+    bool aon;
+    bool active;
+} OtASTDjClock;
+
+struct OtASTDjState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+
+    GList *clocks; /* OtASTDjClock */
+
+    uint32_t *regsa;
+    uint32_t *regsb;
+
+    char *cfg_topclocks;
+    char *cfg_aonclocks;
+    uint32_t noise_bitrate;
+};
+
+struct OtASTDjClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static const char *CFGSEP = ",";
+
+static gint ot_ast_dj_match_clock_by_name(gconstpointer a, gconstpointer b)
+{
+    const OtASTDjClock *ca = a;
+    const OtASTDjClock *cb = b;
+
+    return strcmp(ca->name, cb->name);
+}
+
+static OtASTDjClock *ot_ast_dj_find_clock(OtASTDjState *s, const char *name)
+{
+    OtASTDjClock clock = { .name = (char *)name };
+
+    GList *glist =
+        g_list_find_custom(s->clocks, &clock, &ot_ast_dj_match_clock_by_name);
+
+    return glist ? glist->data : NULL;
+}
+
+static void ot_ast_dj_reset_clock(gpointer data, gpointer user_data)
+{
+    OtASTDjState *s = user_data;
+    OtASTDjClock *clk = data;
+    (void)s;
+
+    clk->active = clk->aon;
+}
+
+static void ot_ast_dj_update_clock(gpointer data, gpointer user_data)
+{
+    OtASTDjState *s = user_data;
+    OtASTDjClock *clk = data;
+    (void)s;
+
+    unsigned frequency = clk->active ? clk->frequency : 0;
+    trace_ot_ast_upate_clock(clk->name, frequency);
+
+    ibex_irq_set(&clk->out, (int)frequency);
+}
+
+static const char *
+ot_ast_dj_get_clock_source(IbexClockSrcIf *ifd, const char *name,
+                           const DeviceState *sink, Error **errp)
+{
+    OtASTDjState *s = OT_AST_DJ(ifd);
+
+    OtASTDjClock *clk = ot_ast_dj_find_clock(s, name);
+    if (!clk) {
+        error_setg(errp, "%s: AST: no such clock: %s", __func__, name);
+        return NULL;
+    }
+
+    if (clk->sink && clk->sink != sink) {
+        error_setg(errp, "%s: AST supports a unique sink per clock: %s",
+                   __func__, name);
+        return NULL;
+    }
+
+    clk->sink = sink;
+
+    return clk->irq_name;
+}
+
+static void ot_ast_dj_clock_enable(OtClockCtrlIf *dev, const char *clkname,
+                                   bool enable)
+{
+    OtASTDjState *s = OT_AST_DJ(dev);
+
+    OtASTDjClock *clk = ot_ast_dj_find_clock(s, clkname);
+    g_assert(clk);
+
+    clk->active = enable;
+    unsigned frequency = clk->active ? clk->frequency : 0;
+
+    trace_ot_ast_upate_clock(clk->name, frequency);
+
+    ibex_irq_set(&clk->out, (int)frequency);
+}
+
+static void ot_ast_dj_clock_ext_freq_select(OtClockCtrlIf *dev, bool enable)
+{
+    OtASTDjState *s = OT_AST_DJ(dev);
+
+    (void)s;
+
+    qemu_log_mask(LOG_UNIMP, "%s: not implemented: %u\n", __func__, enable);
+}
+
+static unsigned ot_ast_dj_get_fill_rate(OtNoiseSrcIf *dev)
+{
+    OtASTDjState *s = OT_AST_DJ(dev);
+
+    return s->noise_bitrate / 8u; /* bit to byte */
+}
+
+static void ot_ast_dj_get_noise(OtNoiseSrcIf *dev, uint8_t *buffer,
+                                size_t length)
+{
+    (void)dev;
+
+    qemu_guest_getrandom_nofail((void *)buffer, length);
+}
+
+static void ot_ast_dj_parse_clocks(OtASTDjState *s, Error **errp)
+{
+    if (!s->cfg_topclocks) {
+        error_setg(errp, "%s: topclocks config not defined", __func__);
+        return;
+    }
+
+    if (!s->cfg_aonclocks) {
+        error_setg(errp, "%s: aonclocks config not defined", __func__);
+        return;
+    }
+
+    char *config = g_strdup(s->cfg_topclocks);
+    for (char *clkbrk, *clkdesc = strtok_r(config, CFGSEP, &clkbrk); clkdesc;
+         clkdesc = strtok_r(NULL, CFGSEP, &clkbrk)) {
+        char clkname[16];
+        unsigned clkfreq = 0;
+        unsigned length = 0;
+        int ret;
+        /* NOLINTNEXTLINE(cert-err34-c) */
+        ret = sscanf(clkdesc, "%15[a-z0-9_]:%u%n", clkname, &clkfreq, &length);
+        if (ret != 2) {
+            error_setg(errp, "%s: invalid clock %s format: %d", __func__,
+                       clkdesc, ret);
+            g_free(config);
+            return;
+        }
+        if (clkdesc[length]) {
+            error_setg(errp, "%s: trailing chars in subclock %s", __func__,
+                       clkdesc);
+            g_free(config);
+            return;
+        }
+
+        OtASTDjClock *clk = g_new0(OtASTDjClock, 1u);
+        clk->name = strdup(clkname);
+        clk->frequency = clkfreq;
+        clk->irq_name = g_strdup_printf("clock-out-%s", clk->name);
+        ibex_qdev_init_irq(OBJECT(s), &clk->out, clk->irq_name);
+        s->clocks = g_list_append(s->clocks, clk);
+        trace_ot_ast_create_clock(clk->name, clk->frequency, clk->irq_name);
+    }
+    g_free(config);
+
+    config = g_strdup(s->cfg_aonclocks);
+    for (char *clkbrk, *clkname = strtok_r(config, CFGSEP, &clkbrk); clkname;
+         clkname = strtok_r(NULL, CFGSEP, &clkbrk)) {
+        OtASTDjClock *clk = ot_ast_dj_find_clock(s, clkname);
+        if (!clk) {
+            error_setg(errp, "%s: invalid AON clock name %s", __func__,
+                       clkname);
+            return;
+        }
+
+        clk->aon = true;
+        clk->active = true;
+    }
+    g_free(config);
+}
+
+static uint64_t ot_ast_dj_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtASTDjState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_REGA0:
+    case R_REGA1:
+    case R_REGA2:
+    case R_REGA3:
+    case R_REGA4:
+    case R_REGA5:
+    case R_REGA6:
+    case R_REGA7:
+    case R_REGA8:
+    case R_REGA9:
+    case R_REGA10:
+    case R_REGA11:
+    case R_REGA12:
+    case R_REGA13:
+    case R_REGA14:
+    case R_REGA15:
+    case R_REGA16:
+    case R_REGA17:
+    case R_REGA18:
+    case R_REGA19:
+    case R_REGA20:
+    case R_REGA21:
+    case R_REGA22:
+    case R_REGA23:
+    case R_REGA24:
+    case R_REGA25:
+    case R_REGA26:
+    case R_REGA27:
+    case R_REGA28:
+    case R_REGA29:
+    case R_REGA30:
+    case R_REGA31:
+    case R_REGA32:
+    case R_REGA33:
+    case R_REGA34:
+    case R_REGA35:
+    case R_REGA36:
+    case R_REGA37:
+    case R_REGAL:
+        val32 = s->regsa[reg];
+        break;
+    case R_REGB0:
+    case R_REGB1:
+    case R_REGB2:
+    case R_REGB3:
+    case R_REGB4:
+        val32 = s->regsb[reg - R_REGB0];
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_ast_io_read_out((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_ast_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                 unsigned size)
+{
+    OtASTDjState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_ast_io_write((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_REGA0:
+    case R_REGA1:
+    case R_REGA2:
+    case R_REGA3:
+    case R_REGA4:
+    case R_REGA5:
+    case R_REGA6:
+    case R_REGA7:
+    case R_REGA8:
+    case R_REGA9:
+    case R_REGA10:
+    case R_REGA11:
+    case R_REGA12:
+    case R_REGA13:
+    case R_REGA14:
+    case R_REGA15:
+    case R_REGA16:
+    case R_REGA17:
+    case R_REGA18:
+    case R_REGA19:
+    case R_REGA20:
+    case R_REGA21:
+    case R_REGA22:
+    case R_REGA23:
+    case R_REGA24:
+    case R_REGA25:
+    case R_REGA26:
+    case R_REGA27:
+    case R_REGA28:
+    case R_REGA29:
+    case R_REGA30:
+    case R_REGA31:
+    case R_REGA32:
+    case R_REGA33:
+    case R_REGA34:
+    case R_REGA35:
+    case R_REGA36:
+    case R_REGA37:
+    case R_REGAL:
+        s->regsa[reg] = val32 & 0xffu;
+        break;
+    case R_REGB0:
+    case R_REGB1:
+    case R_REGB2:
+    case R_REGB3:
+    case R_REGB4:
+        s->regsb[reg - R_REGB0] = val32;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+};
+
+static const Property ot_ast_dj_properties[] = {
+    DEFINE_PROP_STRING("topclocks", OtASTDjState, cfg_topclocks),
+    DEFINE_PROP_STRING("aonclocks", OtASTDjState, cfg_aonclocks),
+    DEFINE_PROP_UINT32("noise-bitrate", OtASTDjState, noise_bitrate,
+                       OT_AST_DJ_NOISE_BITRATE_DEFAULT),
+};
+
+static const MemoryRegionOps ot_ast_dj_regs_ops = {
+    .read = &ot_ast_dj_regs_read,
+    .write = &ot_ast_dj_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_ast_dj_reset_enter(Object *obj, ResetType type)
+{
+    OtASTDjClass *c = OT_AST_DJ_GET_CLASS(obj);
+    OtASTDjState *s = OT_AST_DJ(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->regsa, 0, REGSA_SIZE);
+    memset(s->regsb, 0, REGSB_SIZE);
+
+    s->regsa[R_REGA1] = 0x1u;
+    s->regsa[R_REGA2] = 0x2u;
+    s->regsa[R_REGA3] = 0x3u;
+    s->regsa[R_REGA4] = 0x4u;
+    s->regsa[R_REGA5] = 0x5u;
+    s->regsa[R_REGA6] = 0x6u;
+    s->regsa[R_REGA7] = 0x7u;
+    s->regsa[R_REGA8] = 0x8u;
+    s->regsa[R_REGA9] = 0x9u;
+    s->regsa[R_REGA10] = 0xau;
+    s->regsa[R_REGA11] = 0xbu;
+    s->regsa[R_REGA12] = 0xcu;
+    s->regsa[R_REGA13] = 0xdu;
+    s->regsa[R_REGA14] = 0xeu;
+    s->regsa[R_REGA15] = 0xfu;
+    s->regsa[R_REGA16] = 0x10u;
+    s->regsa[R_REGA17] = 0x11u;
+    s->regsa[R_REGA18] = 0x12u;
+    s->regsa[R_REGA19] = 0x13u;
+    s->regsa[R_REGA20] = 0x14u;
+    s->regsa[R_REGA21] = 0x15u;
+    s->regsa[R_REGA22] = 0x16u;
+    s->regsa[R_REGA23] = 0x17u;
+    s->regsa[R_REGA24] = 0x18u;
+    s->regsa[R_REGA25] = 0x19u;
+    s->regsa[R_REGA26] = 0x1au;
+    s->regsa[R_REGA27] = 0x1bu;
+    s->regsa[R_REGA28] = 0x1cu;
+    s->regsa[R_REGA29] = 0x1du;
+    s->regsa[R_REGA30] = 0x1eu;
+    s->regsa[R_REGA31] = 0x1fu;
+    s->regsa[R_REGA32] = 0x20u;
+    s->regsa[R_REGA33] = 0x21u;
+    s->regsa[R_REGA34] = 0x22u;
+    s->regsa[R_REGA35] = 0x23u;
+    s->regsa[R_REGA36] = 0x24u;
+    s->regsa[R_REGA37] = 0x25u;
+    s->regsa[R_REGAL] = 0x26u;
+
+    g_list_foreach(s->clocks, ot_ast_dj_reset_clock, s);
+}
+
+static void ot_ast_dj_reset_exit(Object *obj, ResetType type)
+{
+    OtASTDjClass *c = OT_AST_DJ_GET_CLASS(obj);
+    OtASTDjState *s = OT_AST_DJ(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    g_list_foreach(s->clocks, ot_ast_dj_update_clock, s);
+}
+
+static void ot_ast_dj_realize(DeviceState *dev, Error **errp)
+{
+    OtASTDjState *s = OT_AST_DJ(dev);
+    (void)errp;
+
+    ot_ast_dj_parse_clocks(s, &error_fatal);
+}
+
+static void ot_ast_dj_init(Object *obj)
+{
+    OtASTDjState *s = OT_AST_DJ(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_ast_dj_regs_ops, s, TYPE_OT_AST_DJ,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regsa = g_new0(uint32_t, REGSA_COUNT);
+    s->regsb = g_new0(uint32_t, REGSB_COUNT);
+}
+
+static void ot_ast_dj_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_ast_dj_realize;
+    device_class_set_props(dc, ot_ast_dj_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtASTDjClass *ac = OT_AST_DJ_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_ast_dj_reset_enter, NULL,
+                                       &ot_ast_dj_reset_exit,
+                                       &ac->parent_phases);
+
+    IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_CLASS(klass);
+    ic->get_clock_source = &ot_ast_dj_get_clock_source;
+
+    OtClockCtrlIfClass *cc = OT_CLOCK_CTRL_IF_CLASS(klass);
+    cc->clock_enable = &ot_ast_dj_clock_enable;
+    cc->clock_ext_freq_select = &ot_ast_dj_clock_ext_freq_select;
+
+    OtNoiseSrcIfClass *nc = OT_NOISE_SRC_IF_CLASS(klass);
+    nc->get_fill_rate = &ot_ast_dj_get_fill_rate;
+    nc->get_noise = &ot_ast_dj_get_noise;
+}
+
+static const TypeInfo ot_ast_dj_info = {
+    .name = TYPE_OT_AST_DJ,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtASTDjState),
+    .instance_init = &ot_ast_dj_init,
+    .class_size = sizeof(OtASTDjClass),
+    .class_init = &ot_ast_dj_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_IBEX_CLOCK_SRC_IF },
+            { TYPE_OT_CLOCK_CTRL_IF },
+            { TYPE_OT_NOISE_SRC_IF },
+            {},
+        },
+};
+
+static void ot_ast_dj_register_types(void)
+{
+    type_register_static(&ot_ast_dj_info);
+}
+
+type_init(ot_ast_dj_register_types);
diff --git a/hw/opentitan/ot_ast_eg.c b/hw/opentitan/ot_ast_eg.c
new file mode 100644
index 0000000000000..89b4bf02c78db
--- /dev/null
+++ b/hw/opentitan/ot_ast_eg.c
@@ -0,0 +1,617 @@
+/*
+ * QEMU OpenTitan EarlGrey Analog Sensor Top device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: for now, only a minimalist subset of Analog Sensor Top device is
+ *       implemented in order to enable OpenTitan's ROM boot to progress
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/guest-random.h"
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_ast_eg.h"
+#include "hw/opentitan/ot_clock_ctrl.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_noise_src.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(REGA0, 0x0u)
+REG32(REGA1, 0x4u)
+REG32(REGA2, 0x8u)
+REG32(REGA3, 0xcu)
+REG32(REGA4, 0x10u)
+REG32(REGA5, 0x14u)
+REG32(REGA6, 0x18u)
+REG32(REGA7, 0x1cu)
+REG32(REGA8, 0x20u)
+REG32(REGA9, 0x24u)
+REG32(REGA10, 0x28u)
+REG32(REGA11, 0x2cu)
+REG32(REGA12, 0x30u)
+REG32(REGA13, 0x34u)
+REG32(REGA14, 0x38u)
+REG32(REGA15, 0x3cu)
+REG32(REGA16, 0x40u)
+REG32(REGA17, 0x44u)
+REG32(REGA18, 0x48u)
+REG32(REGA19, 0x4cu)
+REG32(REGA20, 0x50u)
+REG32(REGA21, 0x54u)
+REG32(REGA22, 0x58u)
+REG32(REGA23, 0x5cu)
+REG32(REGA24, 0x60u)
+REG32(REGA25, 0x64u)
+REG32(REGA26, 0x68u)
+REG32(REGA27, 0x6cu)
+REG32(REGA28, 0x70u)
+REG32(REGA29, 0x74u)
+REG32(REGA30, 0x78u)
+REG32(REGA31, 0x7cu)
+REG32(REGA32, 0x80u)
+REG32(REGA33, 0x84u)
+REG32(REGA34, 0x88u)
+REG32(REGA35, 0x8cu)
+REG32(REGA36, 0x90u)
+REG32(REGA37, 0x94u)
+REG32(REGAL, 0x98u)
+REG32(REGB0, 0x200u)
+REG32(REGB1, 0x204u)
+REG32(REGB2, 0x208u)
+REG32(REGB3, 0x20cu)
+REG32(REGB4, 0x210u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define RA_LAST_REG (R_REGAL)
+#define REGSA_COUNT (RA_LAST_REG + 1u)
+#define REGSA_SIZE  (REGSA_COUNT * sizeof(uint32_t))
+#define REGA_NAME(_reg_) \
+    ((((_reg_) < REGSA_COUNT) && REGA_NAMES[_reg_]) ? REGA_NAMES[_reg_] : "?")
+
+#define RB_LAST_REG (R_REGB4)
+#define REGSB_COUNT (RB_LAST_REG + 1u)
+#define REGSB_SIZE  (REGSB_COUNT * sizeof(uint32_t))
+#define REGB_NAME(_reg_) \
+    ((((_reg_) < REGSB_COUNT) && REGB_NAMES[_reg_]) ? REGB_NAMES[_reg_] : "?")
+
+#define REGS_SIZE (A_REGB4 + sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((_reg_) >= R_REGB0 ? REGB_NAME((_reg_) - (R_REGB0)) : REGA_NAME(_reg_))
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char REGA_NAMES[REGSA_COUNT][8U] = {
+    REG_NAME_ENTRY(REGA0),  REG_NAME_ENTRY(REGA1),  REG_NAME_ENTRY(REGA2),
+    REG_NAME_ENTRY(REGA3),  REG_NAME_ENTRY(REGA4),  REG_NAME_ENTRY(REGA5),
+    REG_NAME_ENTRY(REGA6),  REG_NAME_ENTRY(REGA7),  REG_NAME_ENTRY(REGA8),
+    REG_NAME_ENTRY(REGA9),  REG_NAME_ENTRY(REGA10), REG_NAME_ENTRY(REGA11),
+    REG_NAME_ENTRY(REGA12), REG_NAME_ENTRY(REGA13), REG_NAME_ENTRY(REGA14),
+    REG_NAME_ENTRY(REGA15), REG_NAME_ENTRY(REGA16), REG_NAME_ENTRY(REGA17),
+    REG_NAME_ENTRY(REGA18), REG_NAME_ENTRY(REGA19), REG_NAME_ENTRY(REGA20),
+    REG_NAME_ENTRY(REGA21), REG_NAME_ENTRY(REGA22), REG_NAME_ENTRY(REGA23),
+    REG_NAME_ENTRY(REGA24), REG_NAME_ENTRY(REGA25), REG_NAME_ENTRY(REGA26),
+    REG_NAME_ENTRY(REGA27), REG_NAME_ENTRY(REGA28), REG_NAME_ENTRY(REGA29),
+    REG_NAME_ENTRY(REGA30), REG_NAME_ENTRY(REGA31), REG_NAME_ENTRY(REGA32),
+    REG_NAME_ENTRY(REGA33), REG_NAME_ENTRY(REGA34), REG_NAME_ENTRY(REGA35),
+    REG_NAME_ENTRY(REGA36), REG_NAME_ENTRY(REGA37), REG_NAME_ENTRY(REGAL),
+};
+
+static const char REGB_NAMES[REGSB_COUNT][6U] = {
+    REG_NAME_ENTRY(REGB0), REG_NAME_ENTRY(REGB1), REG_NAME_ENTRY(REGB2),
+    REG_NAME_ENTRY(REGB3), REG_NAME_ENTRY(REGB4),
+};
+#undef REG_NAME_ENTRY
+
+#define OT_AST_EG_NOISE_4BIT_RATE 50000u /* 50 kHz */
+
+typedef struct {
+    char *name;
+    unsigned frequency;
+    IbexIRQ out;
+    char *irq_name;
+    const DeviceState *sink;
+    bool aon;
+    bool active;
+} OtASTEgClock;
+
+struct OtASTEgState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+
+    GList *clocks; /* OtASTEgClock */
+
+    uint32_t *regsa;
+    uint32_t *regsb;
+
+    char *cfg_topclocks;
+    char *cfg_aonclocks;
+};
+
+struct OtASTEgClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static const char *CFGSEP = ",";
+
+static gint ot_ast_eg_match_clock_by_name(gconstpointer a, gconstpointer b)
+{
+    const OtASTEgClock *ca = a;
+    const OtASTEgClock *cb = b;
+
+    return strcmp(ca->name, cb->name);
+}
+
+static OtASTEgClock *ot_ast_eg_find_clock(OtASTEgState *s, const char *name)
+{
+    OtASTEgClock clock = { .name = (char *)name };
+
+    GList *glist =
+        g_list_find_custom(s->clocks, &clock, &ot_ast_eg_match_clock_by_name);
+
+    return glist ? glist->data : NULL;
+}
+
+static void ot_ast_eg_reset_clock(gpointer data, gpointer user_data)
+{
+    OtASTEgState *s = user_data;
+    OtASTEgClock *clk = data;
+    (void)s;
+
+    clk->active = clk->aon;
+}
+
+static void ot_ast_eg_update_clock(gpointer data, gpointer user_data)
+{
+    OtASTEgState *s = user_data;
+    OtASTEgClock *clk = data;
+    (void)s;
+
+    unsigned frequency = clk->active ? clk->frequency : 0;
+    trace_ot_ast_upate_clock(clk->name, frequency);
+
+    ibex_irq_set(&clk->out, (int)frequency);
+}
+
+static const char *
+ot_ast_eg_get_clock_source(IbexClockSrcIf *ifd, const char *name,
+                           const DeviceState *sink, Error **errp)
+{
+    OtASTEgState *s = OT_AST_EG(ifd);
+
+    OtASTEgClock *clk = ot_ast_eg_find_clock(s, name);
+    if (!clk) {
+        error_setg(errp, "%s: AST: no such clock: %s", __func__, name);
+        return NULL;
+    }
+
+    if (clk->sink && clk->sink != sink) {
+        error_setg(errp, "%s: AST supports a unique sink per clock: %s",
+                   __func__, name);
+        return NULL;
+    }
+
+    clk->sink = sink;
+
+    return clk->irq_name;
+}
+
+static void ot_ast_eg_clock_enable(OtClockCtrlIf *dev, const char *clkname,
+                                   bool enable)
+{
+    OtASTEgState *s = OT_AST_EG(dev);
+
+    OtASTEgClock *clk = ot_ast_eg_find_clock(s, clkname);
+    g_assert(clk);
+
+    clk->active = enable;
+    unsigned frequency = clk->active ? clk->frequency : 0;
+
+    trace_ot_ast_upate_clock(clk->name, frequency);
+
+    ibex_irq_set(&clk->out, (int)frequency);
+}
+
+static void ot_ast_eg_clock_ext_freq_select(OtClockCtrlIf *dev, bool enable)
+{
+    OtASTEgState *s = OT_AST_EG(dev);
+
+    (void)s;
+
+    qemu_log_mask(LOG_UNIMP, "%s: not implemented: %u\n", __func__, enable);
+}
+
+static unsigned ot_ast_eg_get_fill_rate(OtNoiseSrcIf *dev)
+{
+    (void)dev;
+
+    return OT_AST_EG_NOISE_4BIT_RATE / 2u; /* 4 bits to byte */
+}
+
+static void ot_ast_eg_get_noise(OtNoiseSrcIf *dev, uint8_t *buffer,
+                                size_t length)
+{
+    (void)dev;
+
+    qemu_guest_getrandom_nofail((void *)buffer, length);
+}
+
+static void ot_ast_eg_parse_clocks(OtASTEgState *s, Error **errp)
+{
+    if (!s->cfg_topclocks) {
+        error_setg(errp, "%s: topclocks config not defined", __func__);
+        return;
+    }
+
+    if (!s->cfg_aonclocks) {
+        error_setg(errp, "%s: aonclocks config not defined", __func__);
+        return;
+    }
+
+    char *config = g_strdup(s->cfg_topclocks);
+    for (char *clkbrk, *clkdesc = strtok_r(config, CFGSEP, &clkbrk); clkdesc;
+         clkdesc = strtok_r(NULL, CFGSEP, &clkbrk)) {
+        char clkname[16];
+        unsigned clkfreq = 0;
+        unsigned length = 0;
+        int ret;
+        /* NOLINTNEXTLINE(cert-err34-c) */
+        ret = sscanf(clkdesc, "%15[a-z0-9_]:%u%n", clkname, &clkfreq, &length);
+        if (ret != 2) {
+            error_setg(errp, "%s: invalid clock %s format: %d", __func__,
+                       clkdesc, ret);
+            g_free(config);
+            return;
+        }
+        if (clkdesc[length]) {
+            error_setg(errp, "%s: trailing chars in subclock %s", __func__,
+                       clkdesc);
+            g_free(config);
+            return;
+        }
+
+        OtASTEgClock *clk = g_new0(OtASTEgClock, 1u);
+        clk->name = strdup(clkname);
+        clk->frequency = clkfreq;
+        clk->irq_name = g_strdup_printf("clock-out-%s", clk->name);
+        ibex_qdev_init_irq(OBJECT(s), &clk->out, clk->irq_name);
+        s->clocks = g_list_append(s->clocks, clk);
+        trace_ot_ast_create_clock(clk->name, clk->frequency, clk->irq_name);
+    }
+    g_free(config);
+
+    config = g_strdup(s->cfg_aonclocks);
+    for (char *clkbrk, *clkname = strtok_r(config, CFGSEP, &clkbrk); clkname;
+         clkname = strtok_r(NULL, CFGSEP, &clkbrk)) {
+        OtASTEgClock *clk = ot_ast_eg_find_clock(s, clkname);
+        if (!clk) {
+            error_setg(errp, "%s: invalid AON clock name %s", __func__,
+                       clkname);
+            return;
+        }
+
+        clk->aon = true;
+        clk->active = true;
+    }
+    g_free(config);
+}
+
+
+static uint64_t ot_ast_eg_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtASTEgState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_REGA0:
+    case R_REGA1:
+    case R_REGA2:
+    case R_REGA3:
+    case R_REGA4:
+    case R_REGA5:
+    case R_REGA6:
+    case R_REGA7:
+    case R_REGA8:
+    case R_REGA9:
+    case R_REGA10:
+    case R_REGA11:
+    case R_REGA12:
+    case R_REGA13:
+    case R_REGA14:
+    case R_REGA15:
+    case R_REGA16:
+    case R_REGA17:
+    case R_REGA18:
+    case R_REGA19:
+    case R_REGA20:
+    case R_REGA21:
+    case R_REGA22:
+    case R_REGA23:
+    case R_REGA24:
+    case R_REGA25:
+    case R_REGA26:
+    case R_REGA27:
+    case R_REGA28:
+    case R_REGA29:
+    case R_REGA30:
+    case R_REGA31:
+    case R_REGA32:
+    case R_REGA33:
+    case R_REGA34:
+    case R_REGA35:
+    case R_REGA36:
+    case R_REGA37:
+    case R_REGAL:
+        val32 = s->regsa[reg];
+        break;
+    case R_REGB0:
+    case R_REGB1:
+    case R_REGB2:
+    case R_REGB3:
+    case R_REGB4:
+        val32 = s->regsb[reg - R_REGB0];
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_ast_io_read_out((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_ast_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                 unsigned size)
+{
+    OtASTEgState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_ast_io_write((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_REGA0:
+    case R_REGA1:
+    case R_REGA2:
+    case R_REGA3:
+    case R_REGA4:
+    case R_REGA5:
+    case R_REGA6:
+    case R_REGA7:
+    case R_REGA8:
+    case R_REGA9:
+    case R_REGA10:
+    case R_REGA11:
+    case R_REGA12:
+    case R_REGA13:
+    case R_REGA14:
+    case R_REGA15:
+    case R_REGA16:
+    case R_REGA17:
+    case R_REGA18:
+    case R_REGA19:
+    case R_REGA20:
+    case R_REGA21:
+    case R_REGA22:
+    case R_REGA23:
+    case R_REGA24:
+    case R_REGA25:
+    case R_REGA26:
+    case R_REGA27:
+    case R_REGA28:
+    case R_REGA29:
+    case R_REGA30:
+    case R_REGA31:
+    case R_REGA32:
+    case R_REGA33:
+    case R_REGA34:
+    case R_REGA35:
+    case R_REGA36:
+    case R_REGA37:
+    case R_REGAL:
+        s->regsa[reg] = val32 & 0xffu;
+        break;
+    case R_REGB0:
+    case R_REGB1:
+    case R_REGB2:
+    case R_REGB3:
+    case R_REGB4:
+        s->regsb[reg - R_REGB0] = val32;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+};
+
+static const Property ot_ast_eg_properties[] = {
+    DEFINE_PROP_STRING("topclocks", OtASTEgState, cfg_topclocks),
+    DEFINE_PROP_STRING("aonclocks", OtASTEgState, cfg_aonclocks),
+};
+
+static const MemoryRegionOps ot_ast_eg_regs_ops = {
+    .read = &ot_ast_eg_regs_read,
+    .write = &ot_ast_eg_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_ast_eg_reset_enter(Object *obj, ResetType type)
+{
+    OtASTEgClass *c = OT_AST_EG_GET_CLASS(obj);
+    OtASTEgState *s = OT_AST_EG(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->regsa, 0, REGSA_SIZE);
+    memset(s->regsb, 0, REGSB_SIZE);
+
+    s->regsa[R_REGA1] = 0x1u;
+    s->regsa[R_REGA2] = 0x2u;
+    s->regsa[R_REGA3] = 0x3u;
+    s->regsa[R_REGA4] = 0x4u;
+    s->regsa[R_REGA5] = 0x5u;
+    s->regsa[R_REGA6] = 0x6u;
+    s->regsa[R_REGA7] = 0x7u;
+    s->regsa[R_REGA8] = 0x8u;
+    s->regsa[R_REGA9] = 0x9u;
+    s->regsa[R_REGA10] = 0xau;
+    s->regsa[R_REGA11] = 0xbu;
+    s->regsa[R_REGA12] = 0xcu;
+    s->regsa[R_REGA13] = 0xdu;
+    s->regsa[R_REGA14] = 0xeu;
+    s->regsa[R_REGA15] = 0xfu;
+    s->regsa[R_REGA16] = 0x10u;
+    s->regsa[R_REGA17] = 0x11u;
+    s->regsa[R_REGA18] = 0x12u;
+    s->regsa[R_REGA19] = 0x13u;
+    s->regsa[R_REGA20] = 0x14u;
+    s->regsa[R_REGA21] = 0x15u;
+    s->regsa[R_REGA22] = 0x16u;
+    s->regsa[R_REGA23] = 0x17u;
+    s->regsa[R_REGA24] = 0x18u;
+    s->regsa[R_REGA25] = 0x19u;
+    s->regsa[R_REGA26] = 0x1au;
+    s->regsa[R_REGA27] = 0x1bu;
+    s->regsa[R_REGA28] = 0x1cu;
+    s->regsa[R_REGA29] = 0x1du;
+    s->regsa[R_REGA30] = 0x1eu;
+    s->regsa[R_REGA31] = 0x1fu;
+    s->regsa[R_REGA32] = 0x20u;
+    s->regsa[R_REGA33] = 0x21u;
+    s->regsa[R_REGA34] = 0x22u;
+    s->regsa[R_REGA35] = 0x23u;
+    s->regsa[R_REGA36] = 0x24u;
+    s->regsa[R_REGA37] = 0x25u;
+    s->regsa[R_REGAL] = 0x26u;
+
+    g_list_foreach(s->clocks, ot_ast_eg_reset_clock, s);
+}
+
+static void ot_ast_eg_reset_exit(Object *obj, ResetType type)
+{
+    OtASTEgClass *c = OT_AST_EG_GET_CLASS(obj);
+    OtASTEgState *s = OT_AST_EG(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    g_list_foreach(s->clocks, ot_ast_eg_update_clock, s);
+}
+
+static void ot_ast_eg_realize(DeviceState *dev, Error **errp)
+{
+    OtASTEgState *s = OT_AST_EG(dev);
+    (void)errp;
+
+    ot_ast_eg_parse_clocks(s, &error_fatal);
+}
+
+static void ot_ast_eg_init(Object *obj)
+{
+    OtASTEgState *s = OT_AST_EG(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_ast_eg_regs_ops, s, TYPE_OT_AST_EG,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regsa = g_new0(uint32_t, REGSA_COUNT);
+    s->regsb = g_new0(uint32_t, REGSB_COUNT);
+}
+
+static void ot_ast_eg_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_ast_eg_realize;
+    device_class_set_props(dc, ot_ast_eg_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtASTEgClass *ac = OT_AST_EG_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_ast_eg_reset_enter, NULL,
+                                       &ot_ast_eg_reset_exit,
+                                       &ac->parent_phases);
+
+    IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_CLASS(klass);
+    ic->get_clock_source = &ot_ast_eg_get_clock_source;
+
+    OtClockCtrlIfClass *cc = OT_CLOCK_CTRL_IF_CLASS(klass);
+    cc->clock_enable = &ot_ast_eg_clock_enable;
+    cc->clock_ext_freq_select = &ot_ast_eg_clock_ext_freq_select;
+
+    OtNoiseSrcIfClass *nc = OT_NOISE_SRC_IF_CLASS(klass);
+    nc->get_fill_rate = &ot_ast_eg_get_fill_rate;
+    nc->get_noise = &ot_ast_eg_get_noise;
+}
+
+static const TypeInfo ot_ast_eg_info = {
+    .name = TYPE_OT_AST_EG,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtASTEgState),
+    .instance_init = &ot_ast_eg_init,
+    .class_size = sizeof(OtASTEgClass),
+    .class_init = &ot_ast_eg_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_IBEX_CLOCK_SRC_IF },
+            { TYPE_OT_CLOCK_CTRL_IF },
+            { TYPE_OT_NOISE_SRC_IF },
+            {},
+        },
+};
+
+static void ot_ast_eg_register_types(void)
+{
+    type_register_static(&ot_ast_eg_info);
+}
+
+type_init(ot_ast_eg_register_types);
diff --git a/hw/opentitan/ot_clkmgr.c b/hw/opentitan/ot_clkmgr.c
new file mode 100644
index 0000000000000..b7c5a8558ea8a
--- /dev/null
+++ b/hw/opentitan/ot_clkmgr.c
@@ -0,0 +1,1447 @@
+/*
+ * QEMU OpenTitan Clock manager device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * For now, only clock hinting for transactional blocks is actually implemented.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_clkmgr.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x0u)
+    FIELD(ALERT_TEST, RECOV_FAULT, 0u, 1u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 1u, 1u)
+REG32(EXTCLK_CTRL_REGWEN, 0x4u)
+    FIELD(EXTCLK_CTRL, REGWEN_EN, 0u, 1u)
+REG32(EXTCLK_CTRL, 0x8u)
+    FIELD(EXTCLK_CTRL, SEL, 0u, 4u)
+    FIELD(EXTCLK_CTRL, HI_SPEED_SEL, 4u, 4u)
+REG32(EXTCLK_STATUS, 0xcu)
+    FIELD(EXTCLK_STATUS, ACK, 0u, 4u)
+REG32(JITTER_REGWEN, 0x10u)
+    FIELD(JITTER_REGWEN, EN, 0u, 1u)
+REG32(JITTER_ENABLE, 0x14u)
+    FIELD(JITTER_ENABLE, VAL, 0, 4u)
+REG32(CLK_ENABLES, 0x18u)
+    /* seems field order is randomized */
+    FIELD(CLK_ENABLES, CLK_IO_DIV4_PERI_EN, 0u, 1u)
+    FIELD(CLK_ENABLES, CLK_IO_DIV2_PERI_EN, 1u, 1u)
+    FIELD(CLK_ENABLES, CLK_IO_PERI_EN, 2u, 1u)
+    FIELD(CLK_ENABLES, CLK_USB_PERI_EN, 3u, 1u)
+REG32(CLK_HINTS, 0x1cu)
+REG32(CLK_HINTS_STATUS, 0x20u)
+REG32(MEASURE_CTRL_REGWEN, 0x24u)
+    FIELD(MEASURE_CTRL_REGWEN, EN, 0u, 1u)
+SHARED_FIELD(MEAS_CTRL_EN, 0u, 4u)
+SHARED_FIELD(MEAS_CTRL_SHADOWED_HI, 0u, 10u)
+SHARED_FIELD(MEAS_CTRL_SHADOWED_LO, 10u, 10u)
+/* not the real address, they are offset by (2 * measure_count) * 4 */
+REG32(RECOV_ERR_CODE, 0x28u)
+    FIELD(RECOV_ERR_CODE, SHADOW_UPDATE_ERR, 0u, 1u)
+REG32(FATAL_ERR_CODE, 0x2cu)
+    FIELD(FATAL_ERR_CODE, REG_INTG, 0u, 1u)
+    FIELD(FATAL_ERR_CODE, IDLE_CNT, 1u, 1u)
+    FIELD(FATAL_ERR_CODE, SHADOW_STORAGE_ERR, 2u, 1u)
+/* clang-format on */
+
+REG32(MEASURE_REG_BASE, A_RECOV_ERR_CODE)
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+/* last statically defined register */
+#define R_LAST_REG (R_FATAL_ERR_CODE)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define ALERT_TEST_MASK \
+    (R_ALERT_TEST_RECOV_FAULT_MASK | R_ALERT_TEST_FATAL_FAULT_MASK)
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(ALERT_TEST),       REG_NAME_ENTRY(EXTCLK_CTRL_REGWEN),
+    REG_NAME_ENTRY(EXTCLK_CTRL),      REG_NAME_ENTRY(EXTCLK_STATUS),
+    REG_NAME_ENTRY(JITTER_REGWEN),    REG_NAME_ENTRY(JITTER_ENABLE),
+    REG_NAME_ENTRY(CLK_ENABLES),      REG_NAME_ENTRY(CLK_HINTS),
+    REG_NAME_ENTRY(CLK_HINTS_STATUS), REG_NAME_ENTRY(MEASURE_CTRL_REGWEN),
+    REG_NAME_ENTRY(RECOV_ERR_CODE),   REG_NAME_ENTRY(FATAL_ERR_CODE),
+};
+#undef REG_NAME_ENTRY
+
+enum { ALERT_RECOVERABLE, ALERT_FATAL, ALERT_COUNT };
+
+/* note: cannot use strlcpy as CentOS 7 (...) does not support it */
+#define strbcpy(_b_, _d_, _s_) \
+    do { \
+        size_t l = ARRAY_SIZE(_b_) - 1u; \
+        const char *end = (_b_) + l; \
+        g_assert(end > (_d_)); \
+        strncpy((_d_), (_s_), (size_t)((uintptr_t)end) - ((uintptr_t)(_d_))); \
+    } while (0)
+
+/*
+ * Any clock.
+ *
+ * A clock may have derived clocks, denoted subclocks here, which are in sync
+ * with their parent, but beat at a lower frequency, the ratio being stored
+ * in the divider field.
+ *
+ * A clock may have outputs (leaf clocks) which are connected to other OT
+ * devices via OtClkMgrClockSink.
+ *
+ * All clocks are instantiated at device realization time, from the clock
+ * properties fields (which are usually loaded from a QEMU readconf file).
+ */
+typedef struct {
+    char *name; /* clock name */
+    GList *subclocks; /* weakrefs to OtClkMgrClock */
+    GList *outputs; /* wekrefs to OtClkMgrClockOutput */
+    unsigned divider; /* divider applied on parent clock if any (0 if top) */
+    unsigned ratio; /* ratio w/ reference clock (may be 0) */
+    bool ref; /* reference clock */
+    bool loose; /* clock which is declared but not connected */
+} OtClkMgrClock;
+
+/*
+ * Logical clock group.
+ *
+ * A group defines how clock can be activated/disabled, depending on the group
+ * property.
+ *
+ * Each group may reference one or more physical clocks, and each clock may be
+ * referenced in one or may groups.
+ *
+ * A group may be fully configured by SW, or only receive deactivation hints,
+ * depending on the group property.
+ *
+ * All groups are instantiated at device realization time, from the clock
+ * properties fields (which are usually loaded from a QEMU readconf file),
+ * which also define the group properties (if any).
+ */
+typedef struct {
+    char *name; /* group name */
+    GList *clocks; /* weakrefs to OtClkMgrClock */
+    bool sw_cg; /* software configurable */
+    bool hint; /* software hintable */
+} OtClkMgrClockGroup;
+
+/*
+ * Each clock output defines a unique physical (clock, group) pair. The clock
+ * output beats at the pace of its clock, while its activation is driven by its
+ * group.
+ *
+ * Each clock output may be connected to many output. To match the QEMU IRQ API,
+ * each IRQ connection to another device is managed as clock sinks. All clock
+ * sinks of a clock group behave (beat and active) the same.
+ *
+ * Clock outputs are lazily instantiated whenever a remote OT device queries the
+ * clock manager via the #get_clock_source API, or when an output is defined as
+ * a SW configurable output. This avoid creating useless clock output instances
+ * as most defined HW clocks are not actually used in the QEMU implementation.
+ */
+typedef struct {
+    OtClkMgrClock *clock; /* weak ref */
+    const OtClkMgrClockGroup *group; /* weak ref */
+    GList *sinks; /* OtClkMgrClockSink */
+    unsigned frequency; /* computed frequency */
+    bool disabled; /* whether the output is disabled */
+} OtClkMgrClockOutput;
+
+/*
+ * A clock sink represents a unique connection from a clock output to a single
+ * OT device clock input. Its name is dynmically generated based on its parent
+ * output and the number of connected OT devices of this output.
+ *
+ * Clock sinks are lazily instantiated, when a connection for the specified OT
+ * device and the selected clock output are queried via the #get_clock_source
+ * API.
+ *
+ * It is guaranteed that an OT device querying the same clock receives the same
+ * IRQ name.
+ */
+typedef struct {
+    const char *irq_name;
+    const DeviceState *dev;
+    IbexIRQ out;
+} OtClkMgrClockSink;
+
+/*
+ * Software configurable clock.
+ *
+ * This is used to handle clock enable/disable requests for clocks that can be
+ * driven this way.
+ *
+ * The name of a SW configurable clock is suffixed with the group name, as this
+ * identifier is used to sort the SW clocks. This identifier strongly matters to
+ * order the SW clocks in the management fields.
+ */
+typedef struct {
+    char *name; /* full clock name, built from <clock>_<group> */
+    OtClkMgrClockOutput *output; /* weakref to the managed clock output */
+} OtClkMgrSwCgClock;
+
+/* Measure register pair */
+typedef struct {
+    uint32_t ctrl_en; /* multibit bool4 */
+    OtShadowReg ctrl; /* value */
+    OtClkMgrClock *clock; /* driven clocks */
+} OtClkMgrMeasureRegs;
+
+struct OtClkMgrState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ alerts[ALERT_COUNT];
+
+    GList *clocks; /* OtClkMgrClock (top clocks and derived clocks) */
+    GList *groups; /* OtClkMgrClockGroup */
+    GList *outputs; /* OtClkMgrClockOutput */
+    GList *ordered; /* OtClkMgrClock ordered weakref for register/field usage */
+    OtClkMgrClock **tops; /* ordered array of wearef top clocks */
+    OtClkMgrClock **hints; /* ordered array of wearef hintable clocks */
+    OtClkMgrSwCgClock **swcgs; /* ordered array of SW configurable clocks */
+    unsigned clock_count; /* count of all clocks */
+    unsigned top_count; /* count of top clocks */
+    unsigned hint_count; /* count of hintable clocks */
+    unsigned swcg_count; /* count of SW configurable clocks */
+
+    uint32_t clock_states; /* bit set: active, reset: clock is idle */
+    uint32_t regs[REGS_COUNT]; /* shadowed slots are not used */
+    OtClkMgrMeasureRegs *measure_regs;
+    unsigned measure_count; /* count of measure_regs */
+    bool input_clock_connected; /* true once clock source are connected */
+
+    char *ot_id;
+    DeviceState *clock_src; /* Top clock source */
+    /* comma-separated definition list */
+    /* pair of name:ratio of top level clocks, ratio w/ ref clock */
+    char *cfg_topclocks;
+    /* name of reference clock, i.e. clock that is not measured */
+    char *cfg_refclock;
+    /* name of top level loose clocks, i.e. clocks not connected */
+    char *cfg_looseclocks;
+    /* triplets of name:parent_name:divider derivated clock definitions */
+    char *cfg_subclocks;
+    /* pairs of name:clocks definition, where clocks are joined with '+' char */
+    char *cfg_groups;
+    /* list of software-configurable groups */
+    char *cfg_swcg;
+    /* list of software-hintable groups */
+    char *cfg_hint;
+    uint8_t version;
+};
+
+/*
+ * Device state-index pair used as opaque data with the `ot_clkmgr_clock_hint`
+ * clock hint callback.
+ *
+ * To enable dynamic clock-hinting across IP based on the clocks defined in the
+ * property strings, we need to expose the clock hint signal as a named GPIO
+ * input to the QDev, but by creating individual named signals instead of an
+ * array we lose the context of the hint number.
+ *
+ * We hence must pass additional opaque data to describe the hint index.
+ */
+typedef struct {
+    OtClkMgrState *state;
+    unsigned hint_index;
+} OtClkMgrHintContext;
+
+struct OtClkMgrClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static const char *CFGSEP = ",";
+
+static void ot_clkmgr_update_alerts(OtClkMgrState *s)
+{
+    bool recov = (bool)(s->regs[R_RECOV_ERR_CODE] &
+                        R_RECOV_ERR_CODE_SHADOW_UPDATE_ERR_MASK);
+    ibex_irq_set(&s->alerts[ALERT_RECOVERABLE], recov);
+}
+
+/* NOLINTNEXTLINE(misc-no-recursion) */
+static void ot_clkmgr_update_clock_frequency(
+    OtClkMgrState *s, OtClkMgrClock *clk, unsigned input_freq)
+{
+    unsigned frequency =
+        clk->divider > 1 ? (input_freq / clk->divider) : input_freq;
+
+    trace_ot_clkmgr_update_clock(s->ot_id, clk->name, frequency);
+
+    /* propagate to derived clocks */
+    for (GList *cnode = clk->subclocks; cnode; cnode = cnode->next) {
+        OtClkMgrClock *sclk = (OtClkMgrClock *)(cnode->data);
+        ot_clkmgr_update_clock_frequency(s, sclk, frequency);
+    }
+
+    /* update clock outputs */
+    for (GList *onode = clk->outputs; onode; onode = onode->next) {
+        OtClkMgrClockOutput *out = (OtClkMgrClockOutput *)onode->data;
+
+        out->frequency = frequency;
+
+        /* update each sink */
+        for (GList *snode = out->sinks; snode; snode = snode->next) {
+            OtClkMgrClockSink *sink = (OtClkMgrClockSink *)(snode->data);
+            unsigned active_freq = out->disabled ? 0 : out->frequency;
+            trace_ot_clkmgr_update_sink(s->ot_id, sink->irq_name, active_freq);
+
+            ibex_irq_set(&sink->out, (int)active_freq);
+        }
+    }
+}
+
+static void ot_clkmgr_update_swcg(OtClkMgrState *s, uint32_t change)
+{
+    for (unsigned ix = 0; ix < s->swcg_count; ix++) {
+        uint32_t bm = 1u << ix;
+        if (!(change & bm)) {
+            continue;
+        }
+
+        bool enabled = (bool)(s->regs[R_CLK_ENABLES] & bm);
+
+        OtClkMgrSwCgClock *swcg_clk = s->swcgs[ix];
+        OtClkMgrClockOutput *out = swcg_clk->output;
+
+        out->disabled = !enabled;
+
+        /* update each sink */
+        for (GList *snode = out->sinks; snode; snode = snode->next) {
+            OtClkMgrClockSink *sink = (OtClkMgrClockSink *)(snode->data);
+            unsigned active_freq = out->disabled ? 0 : out->frequency;
+            trace_ot_clkmgr_update_sink(s->ot_id, sink->irq_name, active_freq);
+
+            ibex_irq_set(&sink->out, (int)active_freq);
+        }
+    }
+}
+
+static void ot_clkmgr_clock_hint(void *opaque, int irq, int level)
+{
+    OtClkMgrHintContext *hint_ctx = opaque;
+    OtClkMgrState *s = hint_ctx->state;
+    unsigned hint = hint_ctx->hint_index;
+
+    g_assert(irq == 0);
+    g_assert(hint < s->hint_count);
+
+    trace_ot_clkmgr_clock_hint(s->ot_id, s->hints[hint]->name, hint,
+                               (bool)level);
+
+    if (level) {
+        s->clock_states |= 1u << hint;
+    } else {
+        s->clock_states &= ~(1u << hint);
+    }
+}
+
+static void ot_clkmgr_clock_input(void *opaque, int irq, int level)
+{
+    OtClkMgrState *s = opaque;
+
+    unsigned clknum = (unsigned)irq;
+    g_assert(clknum < s->clock_count);
+
+    OtClkMgrClock *clk = g_list_nth_data(s->clocks, clknum);
+    g_assert(clk);
+
+    trace_ot_clkmgr_clock_input(s->ot_id, clk->name, (unsigned)level);
+
+    ot_clkmgr_update_clock_frequency(s, clk, (unsigned)level);
+}
+
+static uint32_t ot_clkmgr_get_clock_hints(OtClkMgrState *s)
+{
+    uint32_t hint_status = s->regs[R_CLK_HINTS] | s->clock_states;
+
+    trace_ot_clkmgr_get_clock_hints(s->ot_id, s->regs[R_CLK_HINTS],
+                                    s->clock_states, hint_status);
+
+    return hint_status;
+}
+
+static gint ot_clkmgr_compare_group_by_name(gconstpointer a, gconstpointer b)
+{
+    const OtClkMgrClockGroup *ga = a;
+    const OtClkMgrClockGroup *gb = b;
+
+    return strcmp(ga->name, gb->name);
+}
+
+static OtClkMgrClockGroup *
+ot_clkmgr_find_group(OtClkMgrState *s, const char *name)
+{
+    OtClkMgrClockGroup group = { .name = (char *)name };
+
+    GList *glist =
+        g_list_find_custom(s->groups, &group, &ot_clkmgr_compare_group_by_name);
+
+    return glist ? glist->data : NULL;
+}
+
+static gint ot_clkmgr_compare_clock_by_name(gconstpointer a, gconstpointer b)
+{
+    const OtClkMgrClock *ca = a;
+    const OtClkMgrClock *cb = b;
+
+    return strcmp(ca->name, cb->name);
+}
+
+static gint ot_clkmgr_compare_clock_by_name_with_data(
+    gconstpointer a, gconstpointer b, gpointer user_data)
+{
+    (void)user_data;
+    return ot_clkmgr_compare_clock_by_name(a, b);
+}
+
+
+static OtClkMgrClock *ot_clkmgr_find_clock(GList *clock_list, const char *name)
+{
+    OtClkMgrClock clk = { .name = (char *)name };
+
+    GList *glist =
+        g_list_find_custom(clock_list, &clk, &ot_clkmgr_compare_clock_by_name);
+
+    return glist ? glist->data : NULL;
+}
+
+static gint ot_clkmgr_match_output(gconstpointer a, gconstpointer b)
+{
+    const OtClkMgrClockOutput *oa = a;
+    const OtClkMgrClockOutput *ob = b;
+
+    return (int)((oa->clock != ob->clock) || (oa->group != ob->group));
+}
+
+static OtClkMgrClockOutput *ot_clkmgr_find_output(
+    GList *outlist, const OtClkMgrClockGroup *group, const OtClkMgrClock *clock)
+{
+    const OtClkMgrClockOutput output = {
+        .clock = (OtClkMgrClock *)clock,
+        .group = (OtClkMgrClockGroup *)group,
+    };
+
+    GList *glist =
+        g_list_find_custom(outlist, &output, &ot_clkmgr_match_output);
+
+    return glist ? glist->data : NULL;
+}
+
+static OtClkMgrClockOutput *ot_clkmgr_get_output(
+    OtClkMgrState *s, const OtClkMgrClockGroup *group, OtClkMgrClock *clock)
+{
+    OtClkMgrClockOutput *clk_out =
+        ot_clkmgr_find_output(s->outputs, group, clock);
+
+    if (!clk_out) {
+        clk_out = g_new0(OtClkMgrClockOutput, 1u);
+        clk_out->clock = clock;
+        clk_out->group = group;
+        s->outputs = g_list_append(s->outputs, clk_out);
+        clock->outputs = g_list_append(clock->outputs, clk_out);
+        char *outname = g_strdup_printf("%s.%s", group->name, clock->name);
+        trace_ot_clkmgr_create(s->ot_id, "output", outname);
+        g_free(outname);
+    }
+
+    return clk_out;
+}
+
+static gint ot_clkmgr_match_sink(gconstpointer a, gconstpointer b)
+{
+    const OtClkMgrClockSink *sa = a;
+    const OtClkMgrClockSink *sb = b;
+
+    return (int)(sa->dev != sb->dev);
+}
+
+static OtClkMgrClockSink *
+ot_clkmgr_find_sink(OtClkMgrClockOutput *clkout, const DeviceState *dev)
+{
+    const OtClkMgrClockSink sink = {
+        .dev = dev,
+    };
+
+    GList *glist =
+        g_list_find_custom(clkout->sinks, &sink, &ot_clkmgr_match_sink);
+
+    return glist ? glist->data : NULL;
+}
+
+static const char *
+ot_clkmgr_get_clock_source(IbexClockSrcIf *ifd, const char *name,
+                           const DeviceState *sinkdev, Error **errp)
+{
+    OtClkMgrState *s = OT_CLKMGR(ifd);
+
+    gchar **parts = g_strsplit(name, ".", 2);
+
+    if (g_strv_length(parts) < 2) {
+        g_strfreev(parts);
+        /* clock manager always require a group name */
+        error_setg(errp, "%s: %s: group not defined: %s", __func__, s->ot_id,
+                   name);
+        return NULL;
+    }
+
+    OtClkMgrClockGroup *group = ot_clkmgr_find_group(s, parts[0]);
+    if (!group) {
+        error_setg(errp, "%s: %s: no such group: %s", __func__, s->ot_id,
+                   parts[0]);
+        g_strfreev(parts);
+        return NULL;
+    };
+
+    OtClkMgrClock *clock = ot_clkmgr_find_clock(group->clocks, parts[1]);
+    if (!clock) {
+        error_setg(errp, "%s: %s: no such clock %s.%s", __func__, s->ot_id,
+                   parts[0], parts[1]);
+        g_strfreev(parts);
+        return NULL;
+    };
+
+    g_strfreev(parts);
+
+    OtClkMgrClockOutput *clk_out = ot_clkmgr_get_output(s, group, clock);
+
+    OtClkMgrClockSink *clk_sink = NULL;
+    bool first = g_list_length(clk_out->sinks) == 0;
+    if (first) {
+        clk_sink = ot_clkmgr_find_sink(clk_out, sinkdev);
+    }
+    if (!clk_sink) {
+        if (!first) {
+            if (clk_out->group->hint) {
+                error_setg(errp,
+                           "%s: %s: hintable clock %s can only have one sink, "
+                           "deny sink %s",
+                           __func__, s->ot_id, clk_out->clock->name,
+                           object_get_typename(OBJECT(sinkdev)));
+                return NULL;
+            }
+        }
+        clk_sink = g_new0(OtClkMgrClockSink, 1u);
+        clk_sink->irq_name =
+            g_strdup_printf("clock-out-%s-%s-%d", group->name, clock->name,
+                            g_list_length(clk_out->sinks));
+        ibex_qdev_init_irq(OBJECT(s), &clk_sink->out, clk_sink->irq_name);
+        clk_out->sinks = g_list_append(clk_out->sinks, clk_sink);
+        const char *sinktype = object_get_typename(OBJECT(sinkdev));
+        char *ot_id =
+            object_property_get_str(OBJECT(sinkdev), OT_COMMON_DEV_ID, NULL);
+        trace_ot_clkmgr_register_sink(s->ot_id, clk_sink->irq_name, sinktype,
+                                      ot_id ?: "?");
+        g_free(ot_id);
+    };
+
+    return clk_sink->irq_name;
+}
+
+static void ot_clkmgr_parse_top_clocks(OtClkMgrState *s, Error **errp)
+{
+    if (!s->cfg_topclocks) {
+        error_setg(errp, "%s: topclocks config not defined", __func__);
+        return;
+    }
+
+    char *config = g_strdup(s->cfg_topclocks);
+    for (char *clkbrk, *clkdesc = strtok_r(config, CFGSEP, &clkbrk); clkdesc;
+         clkdesc = strtok_r(NULL, CFGSEP, &clkbrk)) {
+        char clkname[16];
+        unsigned clkratio = 0;
+        unsigned length = 0;
+        int ret;
+        /* NOLINTNEXTLINE(cert-err34-c) */
+        ret = sscanf(clkdesc, "%15[a-z0-9_]:%u%n", clkname, &clkratio, &length);
+        if (ret != 2) {
+            error_setg(errp, "%s: %s: invalid top clock %s format: %d",
+                       __func__, s->ot_id, s->cfg_topclocks, ret);
+            break;
+        }
+        if (clkdesc[length]) {
+            error_setg(errp, "%s: %s: trailing chars in top clock %s", __func__,
+                       s->ot_id, clkdesc);
+            break;
+        }
+        if (!clkratio || clkratio > UINT16_MAX) {
+            error_setg(errp, "%s: %s: invalid ratio in top clock %s", __func__,
+                       s->ot_id, clkdesc);
+            break;
+        }
+        if (ot_clkmgr_find_clock(s->clocks, clkname)) {
+            error_setg(errp, "%s: %s: top clock redefinition '%s'", __func__,
+                       s->ot_id, clkname);
+            break;
+        }
+        OtClkMgrClock *clk = g_new0(OtClkMgrClock, 1u);
+        clk->name = g_strdup(clkname);
+        clk->ref = s->cfg_refclock && !strcmp(clkname, s->cfg_refclock);
+        clk->ratio = clkratio;
+        s->clocks = g_list_append(s->clocks, clk);
+        trace_ot_clkmgr_create(s->ot_id, "clock", clk->name);
+    }
+    g_free(config);
+}
+
+static void ot_clkmgr_parse_loose_clocks(OtClkMgrState *s, Error **errp)
+{
+    if (!s->cfg_looseclocks) {
+        return;
+    }
+
+    char *config = g_strdup(s->cfg_looseclocks);
+    for (char *clkbrk, *clkname = strtok_r(config, CFGSEP, &clkbrk); clkname;
+         clkname = strtok_r(NULL, CFGSEP, &clkbrk)) {
+        OtClkMgrClock *clk = ot_clkmgr_find_clock(s->clocks, clkname);
+        if (!clk) {
+            error_setg(errp, "%s: %s: no such loose clock '%s'", __func__,
+                       s->ot_id, clkname);
+            break;
+        }
+        clk->loose = true;
+        trace_ot_clkmgr_create(s->ot_id, "loose", clk->name);
+    }
+    g_free(config);
+}
+
+static void ot_clkmgr_parse_derived_clocks(OtClkMgrState *s, Error **errp)
+{
+    if (!s->cfg_subclocks) {
+        error_setg(errp, "%s: subclocks config not defined", __func__);
+        return;
+    }
+
+    /* parse derived clocks */
+    char *config = g_strdup(s->cfg_subclocks);
+    for (char *clkbrk, *clkdesc = strtok_r(config, CFGSEP, &clkbrk); clkdesc;
+         clkdesc = strtok_r(NULL, CFGSEP, &clkbrk)) {
+        char subclkname[16];
+        char clkname[16];
+        unsigned clkdiv = 0;
+        unsigned length = 0;
+        /* NOLINTNEXTLINE(cert-err34-c) */
+        int ret = sscanf(clkdesc, "%15[a-z0-9_]:%15[a-z0-9_]:%u%n", subclkname,
+                         clkname, &clkdiv, &length);
+        if (ret != 3) {
+            error_setg(errp, "%s: %s: invalid subclock %s format: %d", __func__,
+                       s->ot_id, clkdesc, ret);
+            break;
+        }
+        if (clkdesc[length]) {
+            error_setg(errp, "%s: %s: trailing chars in subclock %s", __func__,
+                       s->ot_id, clkdesc);
+            break;
+        }
+        if (!clkdiv || clkdiv > UINT16_MAX) {
+            error_setg(errp, "%s: %s: invalid divider in subclock %s", __func__,
+                       s->ot_id, clkdesc);
+            break;
+        }
+        if (ot_clkmgr_find_clock(s->clocks, subclkname)) {
+            error_setg(errp, "%s: %s: derived clock redefinition '%s'",
+                       __func__, s->ot_id, subclkname);
+            break;
+        }
+        OtClkMgrClock *parclk = ot_clkmgr_find_clock(s->clocks, clkname);
+        if (!parclk) {
+            error_setg(errp, "%s: %s: invalid parent clock '%s' for %s",
+                       __func__, s->ot_id, clkname, subclkname);
+            break;
+        }
+        OtClkMgrClock *clk = g_new0(OtClkMgrClock, 1u);
+        clk->name = g_strdup(subclkname);
+        clk->divider = clkdiv;
+        clk->ratio = parclk->ratio / clk->divider;
+        s->clocks = g_list_append(s->clocks, clk);
+        parclk->subclocks = g_list_append(parclk->subclocks, clk);
+        trace_ot_clkmgr_create(s->ot_id, "subclock", clk->name);
+    }
+    g_free(config);
+}
+
+static void ot_clkmgr_parse_groups(OtClkMgrState *s, Error **errp)
+{
+    if (!s->cfg_groups) {
+        error_setg(errp, "%s: groups config not defined", __func__);
+        return;
+    }
+
+    char *config = g_strdup(s->cfg_groups);
+    for (char *clkbrk, *clkdesc = strtok_r(config, CFGSEP, &clkbrk); clkdesc;
+         clkdesc = strtok_r(NULL, CFGSEP, &clkbrk)) {
+        char groupname[16];
+        unsigned length = 0;
+        int ret = sscanf(clkdesc, "%15[a-z0-9_]:%n", groupname, &length);
+        if (ret != 1 || !clkdesc[length]) {
+            error_setg(errp, "%s: %s: invalid group %s format: %d", __func__,
+                       s->ot_id, clkdesc, ret);
+            break;
+        }
+
+        if (ot_clkmgr_find_group(s, groupname)) {
+            error_setg(errp, "%s: %s: multiple group definitions '%s'",
+                       __func__, s->ot_id, groupname);
+            break;
+        }
+
+        OtClkMgrClockGroup *grp = g_new0(OtClkMgrClockGroup, 1u);
+        grp->name = g_strdup(groupname);
+        trace_ot_clkmgr_create(s->ot_id, "group", grp->name);
+
+        const char *gsep = "+";
+        for (char *grpbrk, *clkname = strtok_r(&clkdesc[length], gsep, &grpbrk);
+             clkname; clkname = strtok_r(NULL, gsep, &grpbrk)) {
+            OtClkMgrClock *clk = ot_clkmgr_find_clock(s->clocks, clkname);
+            if (!clk) {
+                error_setg(errp, "%s: %s: invalid group clock '%s' for %s",
+                           __func__, s->ot_id, clkname, groupname);
+                g_free(grp->name);
+                g_free(grp);
+                grp = NULL;
+                break;
+            }
+            grp->clocks = g_list_append(grp->clocks, clk);
+            trace_ot_clkmgr_add_group(s->ot_id, clk->name, grp->name);
+        }
+
+        if (grp) {
+            s->groups = g_list_append(s->groups, grp);
+        }
+    }
+    g_free(config);
+}
+
+static void ot_clkmgr_parse_sw_cg(OtClkMgrState *s, Error **errp)
+{
+    if (!s->cfg_swcg) {
+        error_setg(errp, "%s: sw configurable clocks not defined", __func__);
+        return;
+    }
+
+    char *config = g_strdup(s->cfg_swcg);
+    for (char *grpbrk, *grpname = strtok_r(config, CFGSEP, &grpbrk); grpname;
+         grpname = strtok_r(NULL, CFGSEP, &grpbrk)) {
+        OtClkMgrClockGroup *grp = ot_clkmgr_find_group(s, grpname);
+        if (!grp) {
+            error_setg(errp, "%s: %s: invalid group '%s' for sw_cg", __func__,
+                       s->ot_id, grpname);
+            break;
+        }
+
+        grp->sw_cg = true;
+    }
+    g_free(config);
+}
+
+static unsigned ot_clkmgr_parse_hint(OtClkMgrState *s, Error **errp)
+{
+    unsigned hint_count = 0;
+
+    if (!s->cfg_hint) {
+        error_setg(errp, "%s: hintable clocks not defined", __func__);
+        return hint_count;
+    }
+
+    char *config = g_strdup(s->cfg_hint);
+    for (char *grpbrk, *grpname = strtok_r(config, CFGSEP, &grpbrk); grpname;
+         grpname = strtok_r(NULL, CFGSEP, &grpbrk)) {
+        OtClkMgrClockGroup *grp = ot_clkmgr_find_group(s, grpname);
+        if (!grp) {
+            error_setg(errp, "%s: %s: invalid group '%s' for hint", __func__,
+                       s->ot_id, grpname);
+            break;
+        }
+
+        grp->hint = true;
+        hint_count = g_list_length(grp->clocks);
+    }
+    g_free(config);
+
+    return hint_count;
+}
+
+static void ot_clkmgr_assign_top(gpointer data, gpointer user_data)
+{
+    OtClkMgrState *s = user_data;
+    OtClkMgrClock *clk = data;
+
+    s->tops[s->top_count++] = clk;
+}
+
+static void ot_clkmgr_connect_input_clocks(OtClkMgrState *s)
+{
+    IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+    IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+    for (unsigned cix = 0; cix < s->top_count; cix++) {
+        OtClkMgrClock *clk = s->tops[cix];
+        if (clk->loose) {
+            /* do not attempt to connect this clock */
+            continue;
+        }
+        const char *irq_name =
+            ic->get_clock_source(ii, clk->name, DEVICE(s), &error_fatal);
+        qemu_irq in_irq =
+            qdev_get_gpio_in_named(DEVICE(s), "clock-in", (int)cix);
+        qdev_connect_gpio_out_named(s->clock_src, irq_name, 0, in_irq);
+        trace_ot_clkmgr_connect_input_clock(s->ot_id, irq_name, cix);
+    }
+}
+
+static void ot_clkmgr_configure_groups(gpointer data, gpointer user_data)
+{
+    OtClkMgrState *s = user_data;
+    OtClkMgrClockGroup *group = data;
+
+    if (group->hint) {
+        for (GList *cnode = group->clocks; cnode; cnode = cnode->next) {
+            OtClkMgrClock *clk = (OtClkMgrClock *)(cnode->data);
+
+            OtClkMgrHintContext *hint_ctx = g_new0(OtClkMgrHintContext, 1u);
+            hint_ctx->state = s;
+            hint_ctx->hint_index = s->hint_count;
+
+            char *hintname = g_strdup_printf(OT_CLOCK_HINT_PREFIX "%s.%s",
+                                             group->name, clk->name);
+            qdev_init_gpio_in_named_with_opaque(DEVICE(s),
+                                                &ot_clkmgr_clock_hint, hint_ctx,
+                                                hintname, 1);
+            trace_ot_clkmgr_create(s->ot_id, "hint", hintname);
+            g_free(hintname);
+
+            s->hints[s->hint_count++] = clk;
+        }
+    }
+}
+
+static void ot_clkmgr_add_clock(gpointer data, gpointer user_data)
+{
+    OtClkMgrClock *clk = data;
+    OtClkMgrState *s = user_data;
+
+    /* discard reference clock and duplicates */
+    if (!clk->ref && !ot_clkmgr_find_clock(s->ordered, clk->name)) {
+        bool hint = false;
+        for (unsigned hix = 0; hix < s->hint_count; hix++) {
+            if (clk == s->hints[hix]) {
+                hint = true;
+                break;
+            }
+        }
+        /* hint clocks are only aliases, not main clocks */
+        if (!hint) {
+            s->ordered = g_list_append(s->ordered, clk);
+        }
+    }
+
+    /* add derived clocks */
+    g_list_foreach(clk->subclocks, &ot_clkmgr_add_clock, s);
+}
+
+static void ot_clkmgr_sort_clocks(OtClkMgrState *s)
+{
+    g_assert(!s->ordered);
+
+    g_list_foreach(s->clocks, &ot_clkmgr_add_clock, s);
+
+    s->ordered =
+        g_list_sort_with_data(s->ordered,
+                              &ot_clkmgr_compare_clock_by_name_with_data, NULL);
+}
+
+static gint ot_clkmgr_compare_swcg_by_name(gconstpointer a, gconstpointer b)
+{
+    const OtClkMgrSwCgClock *sa = a;
+    const OtClkMgrSwCgClock *sb = b;
+
+    return strcmp(sa->name, sb->name);
+}
+
+static gint ot_clkmgr_compare_swcg_by_name_with_data(
+    gconstpointer a, gconstpointer b, gpointer user_data)
+{
+    (void)user_data;
+    return ot_clkmgr_compare_swcg_by_name(a, b);
+}
+
+static GList *
+ot_clkmgr_build_swcg_clock_name(OtClkMgrState *s, GList *swcgs,
+                                const OtClkMgrClockGroup *group, GList *clocks)
+{
+    for (GList *node = clocks; node; node = node->next) {
+        OtClkMgrClock *clk = (OtClkMgrClock *)(node->data);
+        /*
+         * hack to remove AON from the configurable list, there is something
+         * weird to address as peri_aon is defined as sw_cg but not present in
+         * the CLK_ENABLES register...
+         * */
+        if (!strcmp(clk->name, s->cfg_refclock)) {
+            continue;
+        }
+
+        OtClkMgrSwCgClock *swcg_clk = g_new0(OtClkMgrSwCgClock, 1u);
+        swcg_clk->name = g_strdup_printf("%s_%s", clk->name, group->name);
+        swcg_clk->output = ot_clkmgr_get_output(s, group, clk);
+        g_assert(swcg_clk->output);
+
+        /* ignore duplicates */
+        if (g_list_find_custom(swcgs, swcg_clk,
+                               &ot_clkmgr_compare_swcg_by_name)) {
+            g_free(swcg_clk->name);
+            g_free(swcg_clk);
+            continue;
+        }
+        swcgs = g_list_append(swcgs, swcg_clk);
+    }
+
+    return swcgs;
+}
+
+static void ot_clkmgr_generate_swcg_clocks(OtClkMgrState *s)
+{
+    GList *swcgs = NULL;
+
+    for (GList *node = s->groups; node; node = node->next) {
+        const OtClkMgrClockGroup *group =
+            (const OtClkMgrClockGroup *)(node->data);
+        if (!group->sw_cg) {
+            continue;
+        }
+
+        swcgs = ot_clkmgr_build_swcg_clock_name(s, swcgs, group, group->clocks);
+    }
+
+    swcgs =
+        g_list_sort_with_data(swcgs, &ot_clkmgr_compare_swcg_by_name_with_data,
+                              NULL);
+
+    s->swcg_count = g_list_length(swcgs);
+    s->swcgs = g_new0(OtClkMgrSwCgClock *, s->swcg_count);
+    unsigned ix = 0;
+    for (GList *node = swcgs; node; node = node->next, ix++) {
+        OtClkMgrSwCgClock *swcg = (OtClkMgrSwCgClock *)(node->data);
+        s->swcgs[ix] = swcg;
+        trace_ot_clkmgr_define_swcg(s->ot_id, ix, swcg->name);
+    }
+
+    /* discard the list, not the items that have been moved to the array */
+    g_list_free(swcgs);
+}
+
+static void ot_clkmgr_create_measure_regs(OtClkMgrState *s)
+{
+    /* generate the ordered list of clocks for register/field indexed access */
+    ot_clkmgr_sort_clocks(s);
+
+    s->measure_count = g_list_length(s->ordered);
+
+    /* the following registers are indexed by the s->ordered list */
+    s->measure_regs = g_new0(OtClkMgrMeasureRegs, s->measure_count);
+
+    unsigned ix = 0;
+    for (GList *node = s->ordered; node; node = node->next, ix++) {
+        OtClkMgrClock *clk = (OtClkMgrClock *)(node->data);
+
+        trace_ot_clkmgr_define_meas(s->ot_id, ix, clk->name);
+
+        s->measure_regs[ix].clock = clk;
+    }
+}
+
+static void ot_clkmgr_reset_measure_regs(OtClkMgrState *s)
+{
+    for (unsigned ix = 0; ix < s->measure_count; ix++) {
+        OtClkMgrMeasureRegs *mreg = &s->measure_regs[ix];
+
+        mreg->ctrl_en = OT_MULTIBITBOOL4_TRUE;
+
+        uint32_t hi = mreg->clock->ratio + 10u;
+        uint32_t lo = (uint32_t)MAX(0, ((int)mreg->clock->ratio) - 10);
+
+        uint32_t value = 0;
+        value = SHARED_FIELD_DP32(value, MEAS_CTRL_SHADOWED_HI, hi);
+        value = SHARED_FIELD_DP32(value, MEAS_CTRL_SHADOWED_LO, lo);
+
+        trace_ot_clkmgr_reset_meas(s->ot_id, ix, mreg->clock->name, lo, hi);
+
+        ot_shadow_reg_init(&s->measure_regs[ix].ctrl, value);
+    }
+}
+
+static uint64_t ot_clkmgr_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtClkMgrState *s = opaque;
+    (void)size;
+
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_EXTCLK_CTRL_REGWEN:
+    case R_EXTCLK_CTRL:
+    case R_EXTCLK_STATUS:
+    case R_JITTER_REGWEN:
+    case R_JITTER_ENABLE:
+    case R_CLK_ENABLES:
+    case R_CLK_HINTS:
+    case R_MEASURE_CTRL_REGWEN:
+        val32 = s->regs[reg];
+        break;
+    case R_CLK_HINTS_STATUS:
+        val32 = ot_clkmgr_get_clock_hints(s);
+        break;
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    /* statically defined register offsets, handled with switch statement */
+    if (reg < R_MEASURE_REG_BASE) {
+        trace_ot_clkmgr_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg),
+                                    val32, pc);
+        return (uint64_t)val32;
+    }
+
+    if (reg < (R_MEASURE_REG_BASE + (s->measure_count * 2u))) {
+        /* measure registers */
+        unsigned measure = (reg - R_MEASURE_REG_BASE) >> 1u;
+        unsigned offset = (reg - R_MEASURE_REG_BASE) & 1u;
+        g_assert(measure < s->measure_count);
+        OtClkMgrMeasureRegs *mreg = &s->measure_regs[measure];
+        GList *node = g_list_nth(s->ordered, measure);
+        g_assert(node);
+        const OtClkMgrClock *clk = (const OtClkMgrClock *)node->data;
+
+        char reg_name[40u];
+        unsigned ix = 0;
+        for (; clk->name[ix] && ix < 16u; ix++) {
+            reg_name[ix] = (char)toupper(clk->name[ix]);
+        }
+        strbcpy(reg_name, &reg_name[ix], "_MEAS_CTRL_");
+        strbcpy(reg_name, &reg_name[ix] + ARRAY_SIZE("_MEAS_CTRL_") - 1u,
+                offset ? "SHADOWED" : "EN");
+
+        switch (offset) {
+        case 0u:
+            val32 = mreg->ctrl_en;
+            break;
+        case 1u:
+            val32 = ot_shadow_reg_read(&mreg->ctrl);
+            break;
+        default:
+            g_assert_not_reached();
+            break;
+        }
+
+        trace_ot_clkmgr_io_read_out(s->ot_id, (uint32_t)addr, reg_name, val32,
+                                    pc);
+        return (uint64_t)val32;
+    }
+
+    /* remaining registers after the dynamic register range */
+    unsigned reg_err = reg - (s->measure_count * 2u);
+
+    switch (reg_err) {
+    case R_RECOV_ERR_CODE:
+    case R_FATAL_ERR_CODE:
+        val32 = s->regs[reg_err];
+        break;
+    default:
+        val32 = 0;
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+
+    trace_ot_clkmgr_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg_err),
+                                val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_clkmgr_write(void *opaque, hwaddr addr, uint64_t val64,
+                            unsigned size)
+{
+    OtClkMgrState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+
+    /* statically defined register offsets, handled with switch statement */
+    if (reg < R_MEASURE_REG_BASE) {
+        trace_ot_clkmgr_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                                 pc);
+    }
+
+    switch (reg) {
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        for (unsigned ix = 0; ix < ALERT_COUNT; ix++) {
+            ibex_irq_set(&s->alerts[ix], (int)((val32 >> ix) & 0x1u));
+        }
+        break;
+    case R_EXTCLK_CTRL_REGWEN:
+        val32 &= R_EXTCLK_CTRL_REGWEN_EN_MASK;
+        s->regs[reg] &= val32;
+        break;
+    case R_EXTCLK_CTRL:
+        if (s->regs[R_EXTCLK_CTRL_REGWEN]) {
+            val32 &= R_EXTCLK_CTRL_SEL_MASK | R_EXTCLK_CTRL_HI_SPEED_SEL_MASK;
+            s->regs[reg] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: EXTCLK_CTRL protected w/ REGWEN\n", __func__);
+        }
+        break;
+    case R_JITTER_REGWEN:
+        val32 &= R_JITTER_REGWEN_EN_MASK;
+        s->regs[reg] &= val32;
+        break;
+    case R_JITTER_ENABLE:
+        if (s->regs[R_JITTER_REGWEN] ||
+            s->version == OT_CLKMGR_VERSION_EG_1_0_0) {
+            if (s->version == OT_CLKMGR_VERSION_EG_1_0_0) {
+                qemu_log_mask(
+                    LOG_GUEST_ERROR,
+                    "%s: JITTER_ENABLE should be protected w/ REGWEN,\n"
+                    "but is allowed due to a known bug in Earlgrey 1.0.0\n",
+                    __func__);
+            }
+            val32 &= R_JITTER_ENABLE_VAL_MASK;
+            s->regs[reg] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: JITTER_ENABLE protected w/ REGWEN\n", __func__);
+        }
+        break;
+    case R_CLK_ENABLES: {
+        uint32_t prev = s->regs[reg];
+        val32 &= (1u << s->swcg_count) - 1u;
+        s->regs[reg] = val32;
+        ot_clkmgr_update_swcg(s, prev ^ s->regs[reg]);
+    } break;
+    case R_CLK_HINTS:
+        val32 &= (1u << s->hint_count) - 1u;
+        s->regs[reg] = val32;
+        break;
+    case R_MEASURE_CTRL_REGWEN:
+        val32 &= R_MEASURE_CTRL_REGWEN_EN_MASK;
+        s->regs[reg] &= val32;
+        break;
+    case R_EXTCLK_STATUS:
+    case R_CLK_HINTS_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        break;
+    }
+
+    /* low, statically defined register offsets, handled above */
+    if (reg < R_MEASURE_REG_BASE) {
+        return;
+    }
+
+    if (reg < (R_MEASURE_REG_BASE + (s->measure_count * 2u))) {
+        /* measure registers */
+        unsigned measure = (reg - R_MEASURE_REG_BASE) >> 1u;
+        unsigned offset = (reg - R_MEASURE_REG_BASE) & 1u;
+        g_assert(measure < s->measure_count);
+        OtClkMgrMeasureRegs *mreg = &s->measure_regs[measure];
+        GList *node = g_list_nth(s->ordered, measure);
+        g_assert(node);
+        const OtClkMgrClock *clk = (const OtClkMgrClock *)(node->data);
+
+        char reg_name[40u];
+        unsigned ix = 0;
+        for (; clk->name[ix] && ix < 20u; ix++) {
+            reg_name[ix] = (char)toupper(clk->name[ix]);
+        }
+        strbcpy(reg_name, &reg_name[ix], "_MEAS_CTRL_");
+        strbcpy(reg_name, &reg_name[ix] + ARRAY_SIZE("_MEAS_CTRL_") - 1u,
+                offset ? "SHADOWED" : "EN");
+        trace_ot_clkmgr_io_write(s->ot_id, (uint32_t)addr, reg_name, val32, pc);
+
+        if (!s->regs[R_MEASURE_CTRL_REGWEN]) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ REGWEN\n",
+                          __func__, s->ot_id, reg_name);
+            return;
+        }
+
+        switch (offset) {
+        case 0u:
+            if (mreg->ctrl_en == OT_MULTIBITBOOL4_TRUE) {
+                val32 &= MEAS_CTRL_EN_MASK;
+                mreg->ctrl_en = val32;
+            } else {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ EN\n",
+                              __func__, s->ot_id, reg_name);
+            }
+            break;
+        case 1u:
+            if (mreg->ctrl_en) {
+                val32 &=
+                    MEAS_CTRL_SHADOWED_HI_MASK | MEAS_CTRL_SHADOWED_LO_MASK;
+                switch (ot_shadow_reg_write(&mreg->ctrl, val32)) {
+                case OT_SHADOW_REG_STAGED:
+                case OT_SHADOW_REG_COMMITTED:
+                    break;
+                case OT_SHADOW_REG_ERROR:
+                default:
+                    s->regs[R_RECOV_ERR_CODE] |=
+                        R_RECOV_ERR_CODE_SHADOW_UPDATE_ERR_MASK;
+                    ot_clkmgr_update_alerts(s);
+                }
+            } else {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ EN\n",
+                              __func__, s->ot_id, reg_name);
+            }
+            break;
+        default:
+            g_assert_not_reached();
+            break;
+        }
+
+        return;
+    }
+
+    /* remaining registers after the dynamic register range */
+    unsigned reg_err = reg - (s->measure_count * 2u);
+
+    trace_ot_clkmgr_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg_err), val32,
+                             pc);
+
+    switch (reg_err) {
+    case R_RECOV_ERR_CODE:
+        val32 &= (1u << ((R_RECOV_ERR_CODE_SHADOW_UPDATE_ERR_SHIFT + 1u +
+                          (s->measure_count * 2u)))) -
+                 1u;
+        s->regs[reg_err] &= ~val32; /* RW1C */
+        break;
+    case R_FATAL_ERR_CODE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+};
+
+static const Property ot_clkmgr_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtClkMgrState, ot_id),
+    DEFINE_PROP_LINK("clock-src", OtClkMgrState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+    DEFINE_PROP_STRING("topclocks", OtClkMgrState, cfg_topclocks),
+    DEFINE_PROP_STRING("refclock", OtClkMgrState, cfg_refclock),
+    DEFINE_PROP_STRING("looseclocks", OtClkMgrState, cfg_looseclocks),
+    DEFINE_PROP_STRING("subclocks", OtClkMgrState, cfg_subclocks),
+    DEFINE_PROP_STRING("groups", OtClkMgrState, cfg_groups),
+    DEFINE_PROP_STRING("swcg", OtClkMgrState, cfg_swcg),
+    DEFINE_PROP_STRING("hint", OtClkMgrState, cfg_hint),
+    DEFINE_PROP_UINT8("version", OtClkMgrState, version, UINT8_MAX),
+};
+
+static const MemoryRegionOps ot_clkmgr_regs_ops = {
+    .read = &ot_clkmgr_read,
+    .write = &ot_clkmgr_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_clkmgr_reset_enter(Object *obj, ResetType type)
+{
+    OtClkMgrClass *c = OT_CLKMGR_GET_CLASS(obj);
+    OtClkMgrState *s = OT_CLKMGR(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->regs, 0, sizeof(s->regs));
+
+    s->regs[R_EXTCLK_CTRL_REGWEN] = 0x1u;
+    s->regs[R_EXTCLK_CTRL] = 0x99u;
+    s->regs[R_EXTCLK_STATUS] = 0x9u;
+    s->regs[R_JITTER_REGWEN] = 0x1u;
+    s->regs[R_JITTER_ENABLE] = 0x9u;
+    s->regs[R_CLK_ENABLES] = 0xfu;
+    s->regs[R_CLK_HINTS] = 0xfu;
+    s->regs[R_CLK_HINTS_STATUS] = 0xfu;
+    s->regs[R_MEASURE_CTRL_REGWEN] = 0x1u;
+
+    for (unsigned ix = 0; ix < s->swcg_count; ix++) {
+        g_assert(s->swcgs[ix] && s->swcgs[ix]->output);
+        s->swcgs[ix]->output->disabled = 0;
+    }
+
+    ot_clkmgr_reset_measure_regs(s);
+
+    for (unsigned ix = 0; ix < ALERT_COUNT; ix++) {
+        ibex_irq_set(&s->alerts[ix], 0);
+    }
+
+    if (!s->input_clock_connected) {
+        ot_clkmgr_connect_input_clocks(s);
+        s->input_clock_connected = true;
+    }
+}
+
+static void ot_clkmgr_realize(DeviceState *dev, Error **errp)
+{
+    OtClkMgrState *s = OT_CLKMGR(dev);
+    (void)errp; /* do not want to use abort */
+
+    g_assert(s->clock_src);
+    OBJECT_CHECK(IbexClockSrcIf, s->clock_src, TYPE_IBEX_CLOCK_SRC_IF);
+
+    g_assert(s->version < OT_CLKMGR_VERSION_COUNT);
+
+    ot_clkmgr_parse_top_clocks(s, &error_fatal);
+    unsigned top_count = g_list_length(s->clocks);
+    qdev_init_gpio_in_named(DEVICE(s), &ot_clkmgr_clock_input, "clock-in",
+                            (int)top_count);
+    s->tops = g_new0(OtClkMgrClock *, top_count);
+    s->top_count = 0u;
+    g_list_foreach(s->clocks, &ot_clkmgr_assign_top, s);
+    g_assert(s->top_count == top_count);
+
+    Error *err_warn;
+
+    ot_clkmgr_parse_loose_clocks(s, &error_fatal);
+    /* not fatal per se, but highly likely to lead to missing clocks */
+    err_warn = NULL;
+    ot_clkmgr_parse_derived_clocks(s, &err_warn);
+    if (err_warn) {
+        warn_report_err(err_warn);
+    }
+    /* at least one group is required */
+    ot_clkmgr_parse_groups(s, &error_fatal);
+    /* following configs are not mandatory, however always defined */
+    err_warn = NULL;
+    ot_clkmgr_parse_sw_cg(s, &err_warn);
+    if (err_warn) {
+        warn_report_err(err_warn);
+    }
+    err_warn = NULL;
+    unsigned hint_count = ot_clkmgr_parse_hint(s, &err_warn);
+    if (err_warn) {
+        warn_report_err(err_warn);
+    }
+
+    s->clock_count = g_list_length(s->clocks);
+
+    s->hints = g_new0(OtClkMgrClock *, hint_count);
+    s->hint_count = 0u;
+    g_list_foreach(s->groups, &ot_clkmgr_configure_groups, s);
+    g_assert(s->hint_count == hint_count);
+
+    ot_clkmgr_generate_swcg_clocks(s);
+
+    ot_clkmgr_create_measure_regs(s);
+
+    memory_region_init_io(&s->mmio, OBJECT(dev), &ot_clkmgr_regs_ops, s,
+                          TYPE_OT_CLKMGR,
+                          REGS_SIZE + s->measure_count * 2u * sizeof(uint32_t));
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+}
+
+static void ot_clkmgr_init(Object *obj)
+{
+    OtClkMgrState *s = OT_CLKMGR(obj);
+
+    for (unsigned ix = 0; ix < ALERT_COUNT; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+}
+
+static void ot_clkmgr_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_clkmgr_realize;
+    device_class_set_props(dc, ot_clkmgr_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtClkMgrClass *cc = OT_CLKMGR_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_clkmgr_reset_enter, NULL, NULL,
+                                       &cc->parent_phases);
+
+    IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_CLASS(klass);
+    ic->get_clock_source = &ot_clkmgr_get_clock_source;
+}
+
+static const TypeInfo ot_clkmgr_info = {
+    .name = TYPE_OT_CLKMGR,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtClkMgrState),
+    .instance_init = &ot_clkmgr_init,
+    .class_size = sizeof(OtClkMgrClass),
+    .class_init = &ot_clkmgr_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_IBEX_CLOCK_SRC_IF },
+            {},
+        },
+};
+
+static void ot_clkmgr_register_types(void)
+{
+    type_register_static(&ot_clkmgr_info);
+}
+
+type_init(ot_clkmgr_register_types);
diff --git a/hw/opentitan/ot_clock_ctrl.c b/hw/opentitan/ot_clock_ctrl.c
new file mode 100644
index 0000000000000..11f0fdcf56e01
--- /dev/null
+++ b/hw/opentitan/ot_clock_ctrl.c
@@ -0,0 +1,42 @@
+/*
+ * QEMU OpenTitan Clock controller interface
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/opentitan/ot_clock_ctrl.h"
+
+static const TypeInfo ot_clock_ctrl_info = {
+    .name = TYPE_OT_CLOCK_CTRL_IF,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(OtClockCtrlIfClass),
+};
+
+static void ot_clock_ctrl_register_types(void)
+{
+    type_register_static(&ot_clock_ctrl_info);
+}
+
+type_init(ot_clock_ctrl_register_types);
diff --git a/hw/opentitan/ot_common.c b/hw/opentitan/ot_common.c
new file mode 100644
index 0000000000000..7b73913f3f408
--- /dev/null
+++ b/hw/opentitan/ot_common.c
@@ -0,0 +1,433 @@
+/*
+ * QEMU OpenTitan utilities
+ *
+ * Copyright (c) 2023-2024 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/config-file.h"
+#include "qemu/cutils.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/option.h"
+#include "qemu/option_int.h"
+#include "qemu/queue.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "qapi/util.h"
+#include "qom/object.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_rom_ctrl.h"
+#include "hw/opentitan/ot_rom_ctrl_img.h"
+#include "hw/riscv/ibex_common.h"
+#include "trace.h"
+
+typedef struct OtCommonObjectNode {
+    Object *obj;
+    QSIMPLEQ_ENTRY(OtCommonObjectNode) node;
+} OtCommonObjectNode;
+
+typedef QSIMPLEQ_HEAD(OtCommonObjectList,
+                      OtCommonObjectNode) OtCommonObjectList;
+
+typedef struct {
+    const char *type; /* which type of object should be matched */
+    unsigned count; /* how many object should be matched */
+    OtCommonObjectList list; /* list of matched objects */
+} OtCommonObjectNodes;
+
+static const char *OT_COMMON_PROP_STRINGS[] = {
+    "str",
+    "string",
+};
+
+static const char *OT_COMMON_PROP_UINT[] = {
+    "uint8",
+    "uint16",
+    "uint32",
+    "uint64",
+};
+
+static const char *OT_COMMON_PROP_BOOL[] = { "bool" };
+
+static int ot_common_node_child_walker(Object *child, void *opaque)
+{
+    OtCommonObjectNodes *nodes = opaque;
+    if (!object_dynamic_cast(child, nodes->type)) {
+        /* continue walking the children hierarchy */
+        return 0;
+    }
+
+    OtCommonObjectNode *node = g_new0(OtCommonObjectNode, 1u);
+    node->obj = child;
+    object_ref(child);
+
+    QSIMPLEQ_INSERT_TAIL(&nodes->list, node, node);
+
+    nodes->count--;
+
+    /* stop walking the hierarchy immediately if max count has been reached */
+    return nodes->count ? 0 : 1;
+}
+
+CPUState *ot_common_get_local_cpu(DeviceState *s)
+{
+    BusState *bus = s->parent_bus;
+    if (!bus) {
+        return NULL;
+    }
+
+    Object *parent;
+    if (bus->parent) {
+        parent = OBJECT(bus->parent);
+    } else if (bus == sysbus_get_default()) {
+        parent = qdev_get_machine();
+    } else {
+        return NULL;
+    }
+
+    OtCommonObjectNodes nodes = {
+        .type = TYPE_CPU,
+        .count = 1u,
+    };
+    QSIMPLEQ_INIT(&nodes.list);
+
+    /* find one of the closest CPU (should be only one with OT platforms) */
+    if (object_child_foreach_recursive(OBJECT(parent),
+                                       &ot_common_node_child_walker, &nodes)) {
+        g_assert(!QSIMPLEQ_EMPTY(&nodes.list));
+        OtCommonObjectNode *node = QSIMPLEQ_FIRST(&nodes.list);
+        object_unref(node->obj);
+        CPUState *cpu = CPU(node->obj);
+        g_free(node);
+        return cpu;
+    }
+
+    return NULL;
+}
+
+unsigned ot_common_check_rom_configuration(void)
+{
+    /* find all ROM defined images */
+    OtCommonObjectNodes img_nodes = {
+        .type = TYPE_OT_ROM_IMG,
+    };
+    QSIMPLEQ_INIT(&img_nodes.list);
+
+    object_child_foreach_recursive(object_get_objects_root(),
+                                   &ot_common_node_child_walker, &img_nodes);
+
+    /* find all ROM controllers */
+    OtCommonObjectNodes ctrl_nodes = {
+        .type = TYPE_OT_ROM_CTRL,
+    };
+    QSIMPLEQ_INIT(&ctrl_nodes.list);
+
+    object_child_foreach_recursive(object_get_root(),
+                                   &ot_common_node_child_walker, &ctrl_nodes);
+
+    /* NOLINTBEGIN(clang-analyzer-unix.Malloc) */
+
+    /*
+     * For each declared ROM image, check if there is a ROM controller that
+     * can make use of it
+     */
+    OtCommonObjectNode *img_node, *img_next;
+    QSIMPLEQ_FOREACH_SAFE(img_node, &img_nodes.list, node, img_next) {
+        const char *comp = object_get_canonical_path_component(img_node->obj);
+        OtCommonObjectNode *ctrl_node, *ctrl_next;
+        QSIMPLEQ_FOREACH_SAFE(ctrl_node, &ctrl_nodes.list, node, ctrl_next) {
+            Error *errp;
+            char *ot_id = object_property_get_str(ctrl_node->obj,
+                                                  OT_COMMON_DEV_ID, &errp);
+            bool remove_img = !ot_id;
+            bool remove_ctrl = false;
+            if (ot_id) {
+                if (!strcmp(ot_id, comp)) {
+                    /* ROM image matches current ROM controller image */
+                    remove_img = true;
+                    remove_ctrl = true;
+                }
+            }
+            g_free(ot_id);
+            if (remove_img) {
+                object_unref(img_node->obj);
+                QSIMPLEQ_REMOVE(&img_nodes.list, img_node, OtCommonObjectNode,
+                                node);
+                g_free(img_node);
+            }
+            if (remove_ctrl) {
+                object_unref(ctrl_node->obj);
+                QSIMPLEQ_REMOVE(&ctrl_nodes.list, ctrl_node, OtCommonObjectNode,
+                                node);
+                g_free(ctrl_node);
+            }
+        }
+    }
+
+    /*
+     * Any ROM image that have not been "consumed" by a ROM controller is an
+     * unexpected declaration (likely an error in CLI options)
+     */
+    QSIMPLEQ_FOREACH_SAFE(img_node, &img_nodes.list, node, img_next) {
+        const char *comp = object_get_canonical_path_component(img_node->obj);
+        warn_report("Unused ROM image: %s", comp);
+        object_unref(img_node->obj);
+        g_free(img_node);
+    }
+
+    /*
+     * Cleanup and count remaining ROM controllers for which no image has been
+     * declared
+     */
+    OtCommonObjectNode *ctrl_node, *ctrl_next;
+    unsigned count = 0;
+    QSIMPLEQ_FOREACH_SAFE(ctrl_node, &ctrl_nodes.list, node, ctrl_next) {
+        object_unref(ctrl_node->obj);
+        g_free(ctrl_node);
+        count++;
+    }
+
+    /* NOLINTEND(clang-analyzer-unix.Malloc) */
+
+    return count;
+}
+
+AddressSpace *ot_common_get_local_address_space(DeviceState *s)
+{
+    CPUState *cpu = ot_common_get_local_cpu(s);
+
+    return cpu ? cpu->as : NULL;
+}
+
+void ot_common_configure_device_opts(DeviceState **devices, unsigned count)
+{
+    /* TODO need to use qemu_find_opts_err if no config is ok */
+    QemuOptsList *optlist = qemu_find_opts("ot_device");
+    if (!optlist) {
+        qemu_log("%s: no config\n", __func__);
+        return;
+    }
+
+    for (unsigned ix = 0; ix < count; ix++) {
+        Object *obj = OBJECT(devices[ix]);
+        if (!obj) {
+            continue;
+        }
+
+        QemuOpts *opts = NULL;
+
+        const char *typename = object_get_typename(obj);
+        char *ot_id = object_property_get_str(obj, OT_COMMON_DEV_ID, NULL);
+        char *obj_id = NULL;
+        if (ot_id && ot_id[0]) {
+            /* try to locate option with the <type>:<id> syntax */
+            obj_id = g_strdup_printf("%s.%s", typename, ot_id);
+            opts = qemu_opts_find(optlist, obj_id);
+        }
+        g_free(ot_id);
+
+        if (!opts) {
+            g_free(obj_id);
+            /*
+             * either there's no <type>:<id> option, or the device does not have
+             * a unique identifier
+             */
+            opts = qemu_opts_find(optlist, typename);
+            obj_id = opts ? g_strdup(typename) : NULL;
+        }
+
+        if (!opts) {
+            g_free(obj_id);
+            continue;
+        }
+
+        QemuOpt *opt = QTAILQ_FIRST(&opts->head);
+        while (opt) {
+            const char *type;
+            type = object_property_get_type(obj, opt->name, NULL);
+            if (!type) {
+                error_setg(&error_fatal, "%s: unknown property %s for %s",
+                           __func__, opt->name, obj_id);
+                goto next;
+            }
+            for (unsigned tx = 0; tx < ARRAY_SIZE(OT_COMMON_PROP_STRINGS);
+                 tx++) {
+                if (!strcmp(type, OT_COMMON_PROP_STRINGS[tx])) {
+                    object_property_set_str(obj, opt->name, opt->str,
+                                            &error_fatal);
+                    trace_ot_common_configure_device_str(obj_id, opt->name,
+                                                         opt->str);
+                    goto next;
+                }
+            }
+            for (unsigned tx = 0; tx < ARRAY_SIZE(OT_COMMON_PROP_UINT); tx++) {
+                if (!strcmp(type, OT_COMMON_PROP_UINT[tx])) {
+                    uint64_t value;
+                    if (qemu_strtou64(opt->str, NULL, 0, &value)) {
+                        error_setg(
+                            &error_fatal,
+                            "%s: invalid unsigned integer property %s for %s",
+                            __func__, opt->name, obj_id);
+                        goto next;
+                    }
+                    object_property_set_uint(obj, opt->name, value,
+                                             &error_fatal);
+                    trace_ot_common_configure_device_uint(obj_id, opt->name,
+                                                          opt->value.uint);
+                    goto next;
+                }
+            }
+            for (unsigned tx = 0; tx < ARRAY_SIZE(OT_COMMON_PROP_BOOL); tx++) {
+                if (!strcmp(type, OT_COMMON_PROP_BOOL[tx])) {
+                    bool value;
+                    qapi_bool_parse(opt->name, opt->str, &value, &error_fatal);
+                    object_property_set_bool(obj, opt->name, value,
+                                             &error_fatal);
+                    trace_ot_common_configure_device_bool(obj_id, opt->name,
+                                                          opt->value.boolean);
+                    goto next;
+                }
+            }
+
+            g_free(obj_id);
+            error_setg(&error_fatal,
+                       "unsupported type %s for property %s of %s", type,
+                       opt->name, obj_id);
+            return;
+
+        next:
+            opt = QTAILQ_NEXT(opt, next);
+        }
+
+        g_free(obj_id);
+    }
+}
+
+void ot_common_configure_devices_with_id(
+    DeviceState **devices, BusState *bus, const char *id_value, bool id_prepend,
+    const IbexDeviceDef *defs, size_t count)
+{
+    ibex_link_devices(devices, defs, count);
+    ibex_define_device_props(devices, defs, count);
+    if (id_value) {
+        ibex_identify_devices(devices, OT_COMMON_DEV_ID, id_value, id_prepend,
+                              count);
+    }
+    ot_common_configure_device_opts(devices, count);
+    ibex_realize_devices(devices, bus, defs, count);
+    ibex_clock_devices(devices, defs, count);
+    ibex_connect_devices(devices, defs, count);
+}
+
+int ot_common_string_ends_with(const char *str, const char *suffix)
+{
+    size_t str_len = strlen(str);
+    size_t suffix_len = strlen(suffix);
+
+    return (str_len >= suffix_len) &&
+           (!memcmp(str + str_len - suffix_len, suffix, suffix_len));
+}
+
+int ot_common_parse_hexa_str(uint8_t *out, const char *xstr, size_t olen,
+                             bool reverse, bool exact)
+{
+    for (size_t ix = 0; ix < olen; ix++) {
+        gint hi = g_ascii_xdigit_value(xstr[ix * 2u]);
+        if (hi < 0) {
+            return hi;
+        }
+        gint lo = g_ascii_xdigit_value(xstr[ix * 2u + 1u]);
+        if (lo < 0) {
+            return lo;
+        }
+        out[reverse ? olen - ix - 1u : ix] = (uint8_t)(hi << 4) | (uint8_t)(lo);
+    }
+
+    return (!exact || !xstr[olen * 2u]) ? 0 : 1;
+}
+
+static const char *
+ot_common_hexdump(const uint8_t *buf, size_t size, char *hexstr, bool order,
+                  size_t hexstr_size, const char *hex)
+{
+    if (size > ((hexstr_size / 2u) - 1u)) {
+        size = (hexstr_size / 2u) - 1u;
+    }
+
+    if (!order) {
+        for (unsigned ix = 0u; ix < (unsigned)size; ix++) {
+            hexstr[(ix * 2u)] = hex[(buf[ix] >> 4u) & 0xfu];
+            hexstr[(ix * 2u) + 1u] = hex[buf[ix] & 0xfu];
+        }
+    } else {
+        for (unsigned ix = 0u; ix < (unsigned)size; ix++) {
+            hexstr[(ix * 2u)] = hex[(buf[size - 1u - ix] >> 4u) & 0xfu];
+            hexstr[(ix * 2u) + 1u] = hex[buf[size - 1u - ix] & 0xfu];
+        }
+    }
+
+
+    hexstr[size * 2u] = '\0';
+    return hexstr;
+}
+
+const char *ot_common_uhexdump(const uint8_t *buf, size_t size, bool order,
+                               char *hexstr, size_t hexstr_size)
+{
+    static const char uhex[] = "0123456789ABCDEF";
+    return ot_common_hexdump(buf, size, hexstr, order, hexstr_size, uhex);
+}
+
+const char *ot_common_lhexdump(const uint8_t *buf, size_t size, bool order,
+                               char *hexstr, size_t hexstr_size)
+{
+    static const char lhex[] = "0123456789abcdef";
+    return ot_common_hexdump(buf, size, hexstr, order, hexstr_size, lhex);
+}
+
+/*
+ * Unfortunately, there is no QEMU API to properly disable serial control lines
+ */
+#ifndef _WIN32
+#include <termios.h>
+#include "chardev/char-fd.h"
+#include "chardev/char-fe.h"
+#include "io/channel-file.h"
+#endif
+
+void ot_common_ignore_chr_status_lines(CharFrontend *chr)
+{
+/* it might be useful to move this to char-serial.c */
+#ifndef _WIN32
+    FDChardev *cd = FD_CHARDEV(chr->chr);
+    QIOChannelFile *fioc = QIO_CHANNEL_FILE(cd->ioc_in);
+
+    struct termios tty = { 0 };
+    tcgetattr(fioc->fd, &tty);
+    tty.c_cflag |= CLOCAL; /* ignore modem status lines */
+    tcsetattr(fioc->fd, TCSANOW, &tty);
+#endif
+}
diff --git a/hw/opentitan/ot_csrng.c b/hw/opentitan/ot_csrng.c
new file mode 100644
index 0000000000000..5f7ab6b236de4
--- /dev/null
+++ b/hw/opentitan/ot_csrng.c
@@ -0,0 +1,2100 @@
+/*
+ * QEMU OpenTitan Cryptographically Secure Random Number Generator
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: ** It is by NO MEANS cryptographically secure! **
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/queue.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_csrng.h"
+#include "hw/opentitan/ot_entropy_src.h"
+#include "hw/opentitan/ot_fifo32.h"
+#include "hw/opentitan/ot_otp_if.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "tomcrypt.h"
+#include "trace.h"
+
+
+#define PARAM_NUM_IRQS   4u
+#define PARAM_NUM_ALERTS 2u
+#define N_APP_COUNT      (OT_CSRNG_HW_APP_MAX + 1u)
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(INTR_CS_CMD_REQ_DONE, 0u, 1u)
+    SHARED_FIELD(INTR_CS_ENTROPY_REQ, 1u, 1u)
+    SHARED_FIELD(INTR_CS_HW_INST_EXC, 2u, 1u)
+    SHARED_FIELD(INTR_CS_FATAL_ERR, 3u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, RECOV_ALERT, 0u, 1u)
+    FIELD(ALERT_TEST, FATAL_ALERT, 1u, 1u)
+REG32(REGWEN, 0x10u)
+    FIELD(REGWEN, EN, 0u, 1u)
+REG32(CTRL, 0x14u)
+    FIELD(CTRL, ENABLE, 0u, 4u)
+    FIELD(CTRL, SW_APP_ENABLE, 4u, 4u)
+    FIELD(CTRL, READ_INT_STATE, 8u, 4u)
+    FIELD(CTRL, FIPS_FORCE_ENABLE, 12u, 4u)
+REG32(CMD_REQ, 0x18u)
+REG32(RESEED_INTERVAL, 0x1cu)
+REG32(RESEED_COUNTER_0, 0x20u)
+REG32(RESEED_COUNTER_1, 0x24u)
+REG32(RESEED_COUNTER_2, 0x28u)
+REG32(SW_CMD_STS, 0x2cu)
+    FIELD(SW_CMD_STS, CMD_RDY, 1u, 1u)
+    FIELD(SW_CMD_STS, CMD_ACK, 2u, 1u)
+    FIELD(SW_CMD_STS, CMD_STS, 3u, 3u)
+REG32(GENBITS_VLD, 0x30u)
+    FIELD(GENBITS_VLD, GENBITS_VLD, 0u, 1u)
+    FIELD(GENBITS_VLD, GENBITS_FIPS, 1u, 1u)
+REG32(GENBITS, 0x34u)
+REG32(INT_STATE_READ_ENABLE, 0x38u)
+    FIELD(INT_STATE_READ_ENABLE, VAL, 0u, N_APP_COUNT)
+REG32(INT_STATE_READ_ENABLE_REGWEN, 0x3cu)
+    FIELD(INT_STATE_READ_ENABLE_REGWEN, EN, 0u, 1u)
+REG32(INT_STATE_NUM, 0x40u)
+    FIELD(INT_STATE_NUM, VAL, 0u, 4u)
+REG32(INT_STATE_VAL, 0x44u)
+REG32(FIPS_FORCE, 0x48u)
+    FIELD(FIPS_FORCE, VAL, 0u, N_APP_COUNT)
+REG32(HW_EXC_STS, 0x4cu)
+    FIELD(HW_EXC_STS, VAL, 0u, 16u)
+REG32(RECOV_ALERT_STS, 0x50u)
+    FIELD(RECOV_ALERT_STS, ENABLE_FIELD_ALERT, 0u, 1u)
+    FIELD(RECOV_ALERT_STS, SW_APP_ENABLE_FIELD_ALERT, 1u, 1u)
+    FIELD(RECOV_ALERT_STS, READ_INT_STATE_FIELD_ALERT, 2u, 1u)
+    FIELD(RECOV_ALERT_STS, FIPS_FORCE_ENABLE_FIELD_ALERT, 3u, 1u)
+    FIELD(RECOV_ALERT_STS, ACMD_FLAG0_FIELD_ALERT, 4u, 1u)
+    FIELD(RECOV_ALERT_STS, CS_BUS_CMP_ALERT, 12u, 1u)
+    FIELD(RECOV_ALERT_STS, CMD_STAGE_INVALID_ACMD_ALERT, 13u, 1u)
+    FIELD(RECOV_ALERT_STS, CMD_STAGE_INVALID_CMD_SEQ_ALERT, 14u, 1u)
+    FIELD(RECOV_ALERT_STS, CMD_STAGE_INVALID_RESEED_CNT_ALERT, 15u, 1u)
+REG32(ERR_CODE, 0x54u)
+    FIELD(ERR_CODE, SFIFO_CMD_ERR, 0u, 1u)
+    FIELD(ERR_CODE, SFIFO_GENBITS_ERR, 1u, 1u)
+    FIELD(ERR_CODE, SFIFO_CMDREQ_ERR, 2u, 1u)
+    FIELD(ERR_CODE, SFIFO_RCSTAGE_ERR, 3u, 1u)
+    FIELD(ERR_CODE, SFIFO_KEYVRC_ERR, 4u, 1u)
+    FIELD(ERR_CODE, SFIFO_UPDREQ_ERR, 5u, 1u)
+    FIELD(ERR_CODE, SFIFO_BENCREQ_ERR, 6u, 1u)
+    FIELD(ERR_CODE, SFIFO_BENCACK_ERR, 7u, 1u)
+    FIELD(ERR_CODE, SFIFO_PDATA_ERR, 8u, 1u)
+    FIELD(ERR_CODE, SFIFO_FINAL_ERR, 9u, 1u)
+    FIELD(ERR_CODE, SFIFO_GBENCACK_ERR, 10u, 1u)
+    FIELD(ERR_CODE, SFIFO_GRCSTAGE_ERR, 11u, 1u)
+    FIELD(ERR_CODE, SFIFO_GGENREQ_ERR, 12u, 1u)
+    FIELD(ERR_CODE, SFIFO_GADSTAGE_ERR, 13u, 1u)
+    FIELD(ERR_CODE, SFIFO_GGENBITS_ERR, 14u, 1u)
+    FIELD(ERR_CODE, SFIFO_BLKENC_ERR, 15u, 1u)
+    FIELD(ERR_CODE, CMD_STAGE_SM_ERR, 20u, 1u)
+    FIELD(ERR_CODE, MAIN_SM_ERR, 21u, 1u)
+    FIELD(ERR_CODE, DRBG_GEN_SM_ERR, 22u, 1u)
+    FIELD(ERR_CODE, DRBG_UPDBE_SM_ERR, 23u, 1u)
+    FIELD(ERR_CODE, DRBG_UPDOB_SM_ERR, 24u, 1u)
+    FIELD(ERR_CODE, AES_CIPHER_SM_ERR, 25u, 1u)
+    FIELD(ERR_CODE, CMD_GEN_CNT_ERR, 26u, 1u)
+    FIELD(ERR_CODE, FIFO_WRITE_ERR, 28u, 1u)
+    FIELD(ERR_CODE, FIFO_READ_ERR, 29u, 1u)
+    FIELD(ERR_CODE, FIFO_STATE_ERR, 30u, 1u)
+REG32(ERR_CODE_TEST, 0x58u)
+    FIELD(ERR_CODE_TEST, VAL, 0u, 5u)
+REG32(MAIN_SM_STATE, 0x5cu)
+    FIELD(MAIN_SM_STATE, VAL, 0u, 8u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_MAIN_SM_STATE)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define INTR_MASK \
+    (INTR_CS_CMD_REQ_DONE_MASK | INTR_CS_ENTROPY_REQ_MASK | \
+     INTR_CS_HW_INST_EXC_MASK | INTR_CS_FATAL_ERR_MASK)
+#define ALERT_TEST_MASK \
+    (R_ALERT_TEST_RECOV_ALERT_MASK | R_ALERT_TEST_FATAL_ALERT_MASK)
+#define CTRL_MASK \
+    (R_CTRL_ENABLE_MASK | R_CTRL_SW_APP_ENABLE_MASK | \
+     R_CTRL_READ_INT_STATE_MASK | R_CTRL_FIPS_FORCE_ENABLE_MASK)
+#define GENBITS_VLD_MASK \
+    (R_GENBITS_VLD_GENBITS_VLD_MASK | R_GENBITS_VLD_GENBITS_FIPS_MASK)
+#define RECOV_ALERT_STS_MASK \
+    (R_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_SW_APP_ENABLE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_READ_INT_STATE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_FIPS_FORCE_ENABLE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_ACMD_FLAG0_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_CS_BUS_CMP_ALERT_MASK | \
+     R_RECOV_ALERT_STS_CMD_STAGE_INVALID_ACMD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_CMD_STAGE_INVALID_CMD_SEQ_ALERT_MASK | \
+     R_RECOV_ALERT_STS_CMD_STAGE_INVALID_RESEED_CNT_ALERT_MASK)
+#define ERR_CODE_MASK 0x77e0ffffu
+
+#define OT_CSRNG_AES_KEY_SIZE   32u /* 256 bits */
+#define OT_CSRNG_AES_BLOCK_SIZE 16u /* 128 bits */
+
+#define OT_CSRNG_AES_BLOCK_WORD  (OT_CSRNG_AES_BLOCK_SIZE / sizeof(uint32_t))
+#define OT_CSRNG_AES_BLOCK_DWORD (OT_CSRNG_AES_BLOCK_SIZE / sizeof(uint64_t))
+
+/*
+ * Should be limited to OT_CSRNG_CMD_WORD_MAX, but the HW does not enforce it
+ * so be sure to accept CLEN up to 15, not 12. CLEN being coded on 4 bits, and
+ * command using 1 slot, the actual CLEN is limited to 15. HW ignores the
+ * trailing additional data words ([12..15])
+ */
+#define CMD_FIFO_CAPACITY (R_OT_CSNRG_CMD_CLEN_MASK + 1u)
+
+#define SW_INSTANCE_ID OT_CSRNG_HW_APP_MAX
+
+#define ALERT_STATUS_BIT(_x_) R_RECOV_ALERT_STS_##_x_##_FIELD_ALERT_MASK
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(REGWEN),
+    REG_NAME_ENTRY(CTRL),
+    REG_NAME_ENTRY(CMD_REQ),
+    REG_NAME_ENTRY(RESEED_INTERVAL),
+    REG_NAME_ENTRY(RESEED_COUNTER_0),
+    REG_NAME_ENTRY(RESEED_COUNTER_1),
+    REG_NAME_ENTRY(RESEED_COUNTER_2),
+    REG_NAME_ENTRY(SW_CMD_STS),
+    REG_NAME_ENTRY(GENBITS_VLD),
+    REG_NAME_ENTRY(GENBITS),
+    REG_NAME_ENTRY(INT_STATE_READ_ENABLE),
+    REG_NAME_ENTRY(INT_STATE_READ_ENABLE_REGWEN),
+    REG_NAME_ENTRY(INT_STATE_NUM),
+    REG_NAME_ENTRY(INT_STATE_VAL),
+    REG_NAME_ENTRY(FIPS_FORCE),
+    REG_NAME_ENTRY(HW_EXC_STS),
+    REG_NAME_ENTRY(RECOV_ALERT_STS),
+    REG_NAME_ENTRY(ERR_CODE),
+    REG_NAME_ENTRY(ERR_CODE_TEST),
+    REG_NAME_ENTRY(MAIN_SM_STATE),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+#define CMD_NAME_ENTRY(_cmd_) [OT_CSRNG_CMD_##_cmd_] = stringify(_cmd_)
+static const char *CMD_NAMES[] = {
+    CMD_NAME_ENTRY(NONE),   CMD_NAME_ENTRY(INSTANTIATE),
+    CMD_NAME_ENTRY(RESEED), CMD_NAME_ENTRY(GENERATE),
+    CMD_NAME_ENTRY(UPDATE), CMD_NAME_ENTRY(UNINSTANTIATE),
+};
+#undef CMD_NAME_ENTRY
+#define CMD_NAME(_cmd_) \
+    (((size_t)(_cmd_)) < ARRAY_SIZE(CMD_NAMES) ? CMD_NAMES[(_cmd_)] : "?")
+
+static_assert(OT_CSRNG_PACKET_WORD_COUNT <= OT_ENTROPY_SRC_WORD_COUNT,
+              "CSRNG packet cannot be larger than entropy_src packet");
+static_assert((OT_ENTROPY_SRC_WORD_COUNT % OT_CSRNG_PACKET_WORD_COUNT) == 0,
+              "CSRNG packet should be a multiple of entropy_src packet");
+static_assert(OT_CSRNG_AES_BLOCK_SIZE + OT_CSRNG_AES_KEY_SIZE ==
+                  OT_CSRNG_SEED_BYTE_COUNT,
+              "Invalid seed size");
+
+#define xtrace_ot_csrng_error(_msg_) \
+    trace_ot_csrng_error(__func__, __LINE__, _msg_)
+#define xtrace_ot_csrng_info(_msg_, _val_) \
+    trace_ot_csrng_info(__func__, __LINE__, _msg_, _val_)
+#define xtrace_ot_csrng_show_buffer(_id_, _msg_, _buf_, _len_) \
+    ot_csrng_show_buffer(__func__, __LINE__, _id_, _msg_, _buf_, _len_)
+
+#define ENTROPY_SRC_INITIAL_REQUEST_COUNT 5u
+
+enum {
+    ALERT_RECOVERABLE,
+    ALERT_FATAL,
+    ALERT_COUNT,
+};
+
+static_assert(ALERT_COUNT == PARAM_NUM_ALERTS, "Invalid alert count");
+
+/*
+ * Command execution result.
+ *
+ * Zero value signals the success and immediate completion of a command
+ * Positive values signal a deferred completion of a command
+ * Negative values signal an error, encoding a OtCSRNGCmdStatus value
+ */
+typedef enum {
+    /* entropy stack is stalled */
+    CSRNG_CMD_STALLED = -CSRNG_STATUS_COUNT,
+    /* command errors, not recoverable */
+    CSRNG_CMD_RESEED_CNT_EXCEEDED = -CSRNG_STATUS_RESEED_CNT_EXCEEDED,
+    CSRNG_CMD_INVALID_CMD_SEQ = -CSRNG_STATUS_INVALID_CMD_SEQ,
+    CSRNG_CMD_INVALID_GEN_CMD = -CSRNG_STATUS_INVALID_GEN_CMD,
+    CSRNG_CMD_INVALID_ACMD = -CSRNG_STATUS_INVALID_ACMD,
+    /* command completed ok */
+    CSRNG_CMD_OK = 0,
+    /* command cannot be executed for now */
+    CSRNG_CMD_RETRY = 1,
+    /* command completion deferred */
+    CSRNG_CMD_DEFERRED = 2,
+} OtCSRNDCmdResult;
+
+typedef enum {
+    CSRNG_IDLE, /* idle */
+    CSRNG_PARSE_CMD, /* parse the cmd */
+    CSRNG_INSTANT_PREP, /* instantiate prep */
+    CSRNG_INSTANT_REQ, /* instantiate request (takes adata or entropy) */
+    CSRNG_RESEED_PREP, /* reseed prep */
+    CSRNG_RESEED_REQ, /* reseed request (takes adata & entropy & Key,V,RC)*/
+    CSRNG_GENERATE_PREP, /* generate request (takes adata? & Key,V,RC) */
+    CSRNG_GENERATE_REQ, /* generate request (takes adata? & Key,V,RC) */
+    CSRNG_UPDATE_PREP, /* update prep */
+    CSRNG_UPDATE_REQ, /* update request (takes adata & Key,V,RC) */
+    CSRNG_UNINSTANT_PREP, /* uninstantiate prep */
+    CSRNG_UNINSTANT_REQ, /* uninstantiate request */
+    CSRNG_CLR_A_DATA, /* clear out the additional data packer fifo */
+    CSRNG_CMD_COMP_WAIT, /* wait for command to complete */
+    CSRNG_ERROR, /* error state, results in fatal alert */
+} OtCSRNGFsmState;
+
+typedef struct {
+    symmetric_ECB ecb; /* AES ECB context for tomcrypt */
+    uint8_t v_counter[OT_CSRNG_AES_BLOCK_SIZE]; /* V a.k.a. the counter */
+    uint8_t key[OT_CSRNG_AES_KEY_SIZE];
+    uint32_t material[OT_CSRNG_SEED_WORD_COUNT];
+    unsigned material_len; /* in word count */
+    unsigned reseed_counter; /* generate command count since last reseed */
+    unsigned rem_packet_count; /* remaining packets to generate */
+    bool instantiated;
+    bool seeded; /* ready to generate randomness */
+    bool no_fips;
+    bool force_fips;
+} OtCSRNGDrng;
+
+typedef struct OtCSRNGInstance {
+    OtFifo32 cmd_fifo;
+    union {
+        struct {
+            OtFifo32 bits_fifo;
+            bool fips;
+        } sw;
+        struct {
+            OtCsrngGenbitFiller filler;
+            void *opaque;
+            QEMUBH *filler_bh;
+            qemu_irq req_sts;
+            bool genbits_ready;
+        } hw;
+    };
+    OtCSRNGDrng drng;
+    bool defer_completion;
+    QSIMPLEQ_ENTRY(OtCSRNGInstance) cmd_request;
+    OtCSRNGState *parent;
+} OtCSRNGInstance;
+
+typedef QSIMPLEQ_HEAD(OtCSRNGQueue, OtCSRNGInstance) OtCSRNGQueue;
+
+struct OtCSRNGState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ irqs[PARAM_NUM_IRQS];
+    IbexIRQ alerts[PARAM_NUM_ALERTS];
+    QEMUBH *cmd_scheduler;
+    QEMUTimer *entropy_scheduler;
+
+    uint32_t *regs;
+    bool enabled;
+    bool sw_app_granted;
+    bool read_int_granted;
+    uint32_t scheduled_cmd;
+    unsigned entropy_delay;
+    unsigned es_retry_count;
+    unsigned state_db_ix;
+    int aes_cipher; /* AES handle for tomcrypt */
+    OtCSRNGFsmState state;
+    OtCSRNGInstance *instances;
+    OtCSRNGQueue cmd_requests;
+
+    OtEntropySrcState *entropy_src;
+    DeviceState *otp_ctrl;
+};
+
+/* clang-format off */
+static const uint8_t OtCSRNGFsmStateCode[] = {
+    [CSRNG_IDLE]           = 0b01001110, // 0x4e: idle
+    [CSRNG_PARSE_CMD]      = 0b10111011, // 0xbb: parse the cmd
+    [CSRNG_INSTANT_PREP]   = 0b11000001, // 0xc1: instantiate prep
+    [CSRNG_INSTANT_REQ]    = 0b01010100, // 0x54: instantiate request
+    [CSRNG_RESEED_PREP]    = 0b11011101, // 0xdd: reseed prep
+    [CSRNG_RESEED_REQ]     = 0b01011011, // 0x5b: reseed request
+    [CSRNG_GENERATE_PREP]  = 0b11101111, // 0xef: generate prep
+    [CSRNG_GENERATE_REQ]   = 0b00100100, // 0x24: generate request
+    [CSRNG_UPDATE_PREP]    = 0b00110001, // 0x31: update prep
+    [CSRNG_UPDATE_REQ]     = 0b00100100, // 0x24: update request
+    [CSRNG_UNINSTANT_PREP] = 0b11110110, // 0xf6: uninstantiate prep
+    [CSRNG_UNINSTANT_REQ]  = 0b01100011, // 0x63: uninstantiate request
+    [CSRNG_CLR_A_DATA]     = 0b00000010, // 0x02: clear out the add. data fifo
+    [CSRNG_CMD_COMP_WAIT]  = 0b10111100, // 0xbc: wait for command to complete
+    [CSRNG_ERROR]          = 0b01111000  // 0x78: error state
+};
+/* clang-format on */
+
+#define STATE_NAME_ENTRY(_st_) [_st_] = stringify(_st_)
+static const char *STATE_NAMES[] = {
+    STATE_NAME_ENTRY(CSRNG_IDLE),
+    STATE_NAME_ENTRY(CSRNG_PARSE_CMD),
+    STATE_NAME_ENTRY(CSRNG_INSTANT_PREP),
+    STATE_NAME_ENTRY(CSRNG_INSTANT_REQ),
+    STATE_NAME_ENTRY(CSRNG_RESEED_PREP),
+    STATE_NAME_ENTRY(CSRNG_RESEED_REQ),
+    STATE_NAME_ENTRY(CSRNG_GENERATE_PREP),
+    STATE_NAME_ENTRY(CSRNG_GENERATE_REQ),
+    STATE_NAME_ENTRY(CSRNG_UPDATE_PREP),
+    STATE_NAME_ENTRY(CSRNG_UPDATE_REQ),
+    STATE_NAME_ENTRY(CSRNG_UNINSTANT_PREP),
+    STATE_NAME_ENTRY(CSRNG_UNINSTANT_REQ),
+    STATE_NAME_ENTRY(CSRNG_CLR_A_DATA),
+    STATE_NAME_ENTRY(CSRNG_CMD_COMP_WAIT),
+    STATE_NAME_ENTRY(CSRNG_ERROR),
+
+};
+#undef STATE_NAME_ENTRY
+#define STATE_NAME(_st_) \
+    ((_st_) >= 0 && (_st_) < ARRAY_SIZE(STATE_NAMES) ? STATE_NAMES[(_st_)] : \
+                                                       "?")
+#define CHECK_MULTIBOOT(_s_, _r_, _b_) \
+    ot_csrng_check_multibitboot((_s_), FIELD_EX32(s->regs[R_##_r_], _r_, _b_), \
+                                ALERT_STATUS_BIT(_b_));
+#define CHANGE_STATE(_s_, _st_) ot_csrng_change_state_line(_s_, _st_, __LINE__)
+
+#define OT_CSRNG_HEXBUF_SIZE ((8u * 2u + 1u) * OT_CSRNG_SEED_WORD_COUNT + 4u)
+
+static bool ot_csrng_check_multibitboot(OtCSRNGState *s, uint8_t mbbool,
+                                        uint32_t alert_bit);
+static void ot_csrng_command_schedule(OtCSRNGState *s, OtCSRNGInstance *inst);
+static bool
+ot_csrng_instance_is_command_ready(const OtCSRNGInstance *inst, bool fatal);
+static void ot_csrng_complete_command(OtCSRNGInstance *inst,
+                                      OtCSRNGCmdStatus sts);
+static void ot_csrng_change_state_line(OtCSRNGState *s, OtCSRNGFsmState state,
+                                       int line);
+static unsigned ot_csrng_get_slot(const OtCSRNGInstance *inst);
+static bool ot_csrng_drng_is_instantiated(const OtCSRNGInstance *inst);
+static void ot_csrng_release_hw_app(OtCSRNGInstance *inst);
+static void ot_csrng_update_irqs(OtCSRNGState *s);
+static void ot_csrng_update_alerts(OtCSRNGState *s);
+
+static OtCSRNDCmdResult ot_csrng_drng_reseed(OtCSRNGInstance *inst, bool flag0);
+
+/* -------------------------------------------------------------------------- */
+/* Client API */
+/* -------------------------------------------------------------------------- */
+
+static qemu_irq
+ot_csrng_connect_hw_app(OtCSRNGState *s, unsigned app_id, qemu_irq req_sts,
+                        OtCsrngGenbitFiller filler_fn, void *opaque)
+{
+    g_assert(app_id < OT_CSRNG_HW_APP_MAX);
+
+    OtCSRNGInstance *inst = &s->instances[app_id];
+
+    if (!filler_fn) {
+        if (!inst->hw.filler) {
+            xtrace_ot_csrng_info("HW app was not connected", app_id);
+            return NULL;
+        }
+
+        trace_ot_csrng_disconnection(app_id, true);
+        ot_csrng_release_hw_app(inst);
+
+        return NULL;
+    }
+
+    g_assert(req_sts);
+
+    /* if connection is invoked many times, there is no reason for changes */
+    if (inst->hw.filler) {
+        g_assert(inst->hw.filler == filler_fn);
+    }
+    if (inst->hw.req_sts) {
+        g_assert(inst->hw.req_sts == req_sts);
+    }
+
+    trace_ot_csrng_connection(app_id, inst->hw.filler == NULL);
+
+    inst->hw.filler = filler_fn;
+    inst->hw.opaque = opaque;
+    inst->hw.req_sts = req_sts;
+
+    return qdev_get_gpio_in_named(DEVICE(s), TYPE_OT_CSRNG "-genbits_ready",
+                                  (int)app_id);
+}
+
+static OtCSRNGCmdStatus
+ot_csrng_push_command(OtCSRNGState *s, unsigned app_id, uint32_t word)
+{
+    g_assert(app_id < OT_CSRNG_HW_APP_MAX);
+
+    if (s->state == CSRNG_ERROR) {
+        return CSRNG_STATUS_INVALID_CMD_SEQ;
+    }
+
+    OtCSRNGInstance *inst = &s->instances[app_id];
+    g_assert(inst->hw.filler);
+    g_assert(inst->hw.req_sts);
+
+    /* FIFO is emptied in #ot_csrng_complete_command */
+    if (ot_fifo32_is_full(&inst->cmd_fifo)) {
+        xtrace_ot_csrng_error("Command FIFO is full");
+        return CSRNG_STATUS_INVALID_CMD_SEQ;
+    }
+
+    bool check_cmd = ot_fifo32_is_empty(&inst->cmd_fifo);
+
+    ot_fifo32_push(&inst->cmd_fifo, word);
+    uint32_t cmd = ot_fifo32_peek(&inst->cmd_fifo);
+
+    uint32_t acmd = FIELD_EX32(cmd, OT_CSNRG_CMD, ACMD);
+    uint32_t length = FIELD_EX32(cmd, OT_CSNRG_CMD, CLEN) + 1u;
+
+    if (check_cmd) {
+        /* NOLINTNEXTLINE */
+        switch (acmd) {
+        case OT_CSRNG_CMD_INSTANTIATE:
+        case OT_CSRNG_CMD_RESEED:
+            ot_csrng_check_multibitboot(s,
+                                        (uint8_t)FIELD_EX32(cmd, OT_CSNRG_CMD,
+                                                            FLAG0),
+                                        ALERT_STATUS_BIT(ACMD_FLAG0));
+            break;
+        case OT_CSRNG_CMD_GENERATE ... OT_CSRNG_CMD_UNINSTANTIATE:
+            break;
+        default:
+            xtrace_ot_csrng_error("Invalid command opcode");
+            ot_fifo32_reset(&inst->cmd_fifo);
+            return CSRNG_STATUS_INVALID_ACMD;
+        }
+
+        if (length > CMD_FIFO_CAPACITY) {
+            xtrace_ot_csrng_error("Invalid command length (overflow)");
+            /*
+             * as CLEN width cannot encode more than CMD_FIFO_CAPACITY, this
+             * error should never occur.
+             */
+            g_assert_not_reached();
+        }
+    }
+
+    if (ot_fifo32_num_used(&inst->cmd_fifo) > length) {
+        xtrace_ot_csrng_error("Invalid command length (too many)");
+        /*
+         * as the FIFO should have been handled and emptied in a previous call
+         * to this function, this error should never occur.
+         */
+        g_assert_not_reached();
+    }
+    if (ot_fifo32_num_used(&inst->cmd_fifo) < length) {
+        /* more payload is expected */
+        return CSRNG_STATUS_SUCCESS;
+    }
+
+    if (acmd == OT_CSRNG_CMD_GENERATE) {
+        uint32_t glen = FIELD_EX32(cmd, OT_CSNRG_CMD, GLEN);
+        trace_ot_csrng_push_command(app_id, CMD_NAME(acmd), acmd, 'g', glen);
+
+        const OtCSRNGDrng *drng = &inst->drng;
+        if (drng->reseed_counter >= s->regs[R_RESEED_INTERVAL]) {
+            s->regs[R_INTR_STATE] |= INTR_CS_HW_INST_EXC_MASK;
+            s->regs[R_RECOV_ALERT_STS] |=
+                R_RECOV_ALERT_STS_CMD_STAGE_INVALID_RESEED_CNT_ALERT_MASK;
+            ot_fifo32_reset(&inst->cmd_fifo);
+            ot_csrng_update_irqs(s);
+            ot_csrng_update_alerts(s);
+            return CSRNG_STATUS_RESEED_CNT_EXCEEDED;
+        }
+    } else {
+        trace_ot_csrng_push_command(app_id, CMD_NAME(acmd), acmd, 'c', length);
+    }
+
+    if (acmd == OT_CSRNG_CMD_UNINSTANTIATE) {
+        if (!ot_csrng_drng_is_instantiated(inst)) {
+            /*
+             * Very special hacky case:
+             *
+             * Uninstantiation is requested before instantiation has been
+             * completed (instantiation command in still in the command queue).
+             * Flush the command queue to discard the instantiation command,
+             * which stays uncompleted on the client side, and resume (the
+             * uninstantiation request should complete this new command).
+             *
+             * It might be useful to implement a "cancel outstanding request"
+             * API so that the EDN can tell CSRNG its last command needs to be
+             * cancelled before completion - and remove this workaround.
+             */
+            QSIMPLEQ_REMOVE(&s->cmd_requests, inst, OtCSRNGInstance,
+                            cmd_request);
+
+            if (QSIMPLEQ_EMPTY(&s->cmd_requests)) {
+                qemu_bh_cancel(s->cmd_scheduler);
+                timer_del(s->entropy_scheduler);
+            }
+        }
+    }
+
+    ot_csrng_command_schedule(s, inst);
+
+    return CSRNG_STATUS_SUCCESS;
+}
+
+/* -------------------------------------------------------------------------- */
+/* DRBG (Deterministic Random Bit Generator) */
+/* -------------------------------------------------------------------------- */
+
+static void ot_csrng_show_buffer(const char *func, int line, unsigned int appid,
+                                 const char *msg, const void *buf,
+                                 unsigned size)
+{
+    if (trace_event_get_state(TRACE_OT_CSRNG_SHOW_BUFFER) &&
+        qemu_loglevel_mask(LOG_TRACE)) {
+        static const char _hex[] = "0123456789ABCDEF";
+        char hexstr[OT_CSRNG_HEXBUF_SIZE];
+        unsigned len = MIN(size, OT_CSRNG_HEXBUF_SIZE / 2u - 4u);
+        const uint8_t *pbuf = (const uint8_t *)buf;
+        memset(hexstr, 0, sizeof(hexstr));
+        unsigned hix = 0;
+        for (unsigned ix = 0u; ix < len; ix++) {
+            if (ix && !(ix & 0x3u)) {
+                hexstr[hix++] = '-';
+            }
+            hexstr[hix++] = _hex[(pbuf[ix] >> 4u) & 0xfu];
+            hexstr[hix++] = _hex[pbuf[ix] & 0xfu];
+        }
+        if (len < size) {
+            hexstr[hix++] = '.';
+            hexstr[hix++] = '.';
+            hexstr[hix++] = '.';
+        }
+
+        trace_ot_csrng_show_buffer(func, line, appid, msg, hexstr);
+    }
+}
+
+static void ot_csrng_drng_store_material(OtCSRNGInstance *inst,
+                                         const uint32_t *buf, unsigned len)
+{
+    OtCSRNGDrng *drng = &inst->drng;
+
+    /* convert OpenTitan order into natural order */
+    for (unsigned ix = 0; ix < len; ix++) {
+        drng->material[ix] = bswap32(buf[len - ix - 1]);
+    }
+    drng->material_len = len;
+}
+
+static void ot_csrng_drng_clear_material(OtCSRNGInstance *inst)
+{
+    OtCSRNGDrng *drng = &inst->drng;
+
+    memset(drng->material, 0, sizeof(drng->material));
+    drng->material_len = 0;
+}
+
+static unsigned ot_csrng_drng_remaining_count(const OtCSRNGInstance *inst)
+{
+    return inst->drng.rem_packet_count;
+}
+
+static bool ot_csrng_drng_is_instantiated(const OtCSRNGInstance *inst)
+{
+    return inst->drng.instantiated;
+}
+
+static void ot_csrng_drng_increment(OtCSRNGDrng *drng)
+{
+    unsigned pos = OT_CSRNG_AES_BLOCK_SIZE - 1u;
+    while (pos) {
+        if (++drng->v_counter[pos] != 0) {
+            break;
+        }
+        pos -= 1u;
+    }
+}
+
+static OtCSRNDCmdResult
+ot_csrng_drng_instantiate(OtCSRNGInstance *inst, bool flag0)
+{
+    OtCSRNGDrng *drng = &inst->drng;
+    if (drng->instantiated) {
+        return CSRNG_CMD_INVALID_CMD_SEQ;
+    }
+
+    memset(drng->v_counter, 0, sizeof(drng->v_counter));
+    drng->no_fips = false;
+
+    uint8_t key[OT_CSRNG_AES_KEY_SIZE];
+    memset(key, 0, sizeof(key));
+
+    int res;
+    res = ecb_start(inst->parent->aes_cipher, key, (int)sizeof(key), 0,
+                    &drng->ecb);
+    g_assert(res == CRYPT_OK);
+
+    memcpy(drng->key, key, OT_CSRNG_AES_KEY_SIZE);
+    drng->instantiated = true;
+
+    res = ot_csrng_drng_reseed(inst, flag0);
+    if (res) {
+        drng->instantiated = false;
+        return res;
+    }
+
+    if (inst->hw.genbits_ready) {
+        /*
+         * a HW client app of this instance has already requested randomness
+         * through #ot_csrng_hwapp_ready_irq. This request had been deferred
+         * till the instanciation stage has completed, it is now safe to
+         * schedule the actual generation
+         */
+        qemu_bh_schedule(inst->hw.filler_bh);
+    }
+
+    return res;
+}
+
+static void ot_csrng_drng_uninstantiate(OtCSRNGInstance *inst)
+{
+    OtCSRNGDrng *drng = &inst->drng;
+
+    if (drng->instantiated) {
+        ecb_done(&drng->ecb);
+    }
+
+    drng->instantiated = false;
+    drng->seeded = false;
+    drng->no_fips = false;
+    drng->rem_packet_count = 0;
+
+    /* only to help debugging */
+    memset(drng->v_counter, 0, sizeof(drng->v_counter));
+}
+
+static void ot_csrng_drng_update(OtCSRNGInstance *inst)
+{
+    OtCSRNGDrng *drng = &inst->drng;
+
+    unsigned appid = ot_csrng_get_slot(inst);
+    xtrace_ot_csrng_show_buffer(appid, "seed", drng->material,
+                                drng->material_len * sizeof(uint32_t));
+    xtrace_ot_csrng_show_buffer(appid, "c-V", drng->v_counter,
+                                OT_CSRNG_AES_BLOCK_SIZE);
+
+    uint32_t tmp[OT_CSRNG_SEED_WORD_COUNT];
+    int res;
+    memset(tmp, 0, sizeof(tmp));
+    uint8_t *ptmp = (uint8_t *)tmp;
+    for (unsigned ix = 0; ix < OT_CSRNG_SEED_BYTE_COUNT;
+         ix += OT_CSRNG_AES_BLOCK_SIZE) {
+        ot_csrng_drng_increment(drng);
+
+        res = ecb_encrypt(drng->v_counter, ptmp, OT_CSRNG_AES_BLOCK_SIZE,
+                          &drng->ecb);
+        g_assert(res == CRYPT_OK);
+        ptmp += OT_CSRNG_AES_BLOCK_SIZE;
+    }
+
+    for (unsigned ix = 0; ix < drng->material_len; ix++) {
+        tmp[ix] ^= drng->material[ix];
+    }
+
+    ot_csrng_drng_clear_material(inst);
+
+    res = ecb_done(&drng->ecb);
+    g_assert(res == CRYPT_OK);
+
+    ptmp = (uint8_t *)tmp;
+    res = ecb_start(inst->parent->aes_cipher, ptmp, (int)OT_CSRNG_AES_KEY_SIZE,
+                    0, &drng->ecb);
+    g_assert(res == CRYPT_OK);
+
+    memcpy(drng->key, ptmp, OT_CSRNG_AES_KEY_SIZE);
+    memcpy(drng->v_counter, &ptmp[OT_CSRNG_AES_KEY_SIZE],
+           OT_CSRNG_AES_BLOCK_SIZE);
+
+    xtrace_ot_csrng_show_buffer(appid, "n-key", drng->key,
+                                OT_CSRNG_AES_KEY_SIZE);
+    xtrace_ot_csrng_show_buffer(appid, "n-V", drng->v_counter,
+                                OT_CSRNG_AES_BLOCK_SIZE);
+}
+
+static OtCSRNDCmdResult ot_csrng_drng_reseed(OtCSRNGInstance *inst, bool flag0)
+{
+    OtCSRNGState *s = inst->parent;
+    OtCSRNGDrng *drng = &inst->drng;
+    g_assert(drng->instantiated);
+
+    unsigned slot = ot_csrng_get_slot(inst);
+    drng->seeded = false;
+
+    if (!flag0) {
+        uint64_t buffer[OT_ENTROPY_SRC_DWORD_COUNT];
+        memset(buffer, 0, sizeof(buffer));
+        unsigned len = drng->material_len * sizeof(uint32_t);
+        memcpy(buffer, drng->material, MIN(len, sizeof(buffer)));
+
+
+        uint64_t entropy[OT_ENTROPY_SRC_DWORD_COUNT];
+        int res;
+        bool fips;
+        trace_ot_csrng_request_entropy(slot);
+        OtEntropySrcState *ess = inst->parent->entropy_src;
+        OtEntropySrcClass *esc = OT_ENTROPY_SRC_GET_CLASS(ess);
+        res = esc->get_entropy(ess, entropy, &fips);
+
+        if (res < 0) {
+            s->entropy_delay = 0;
+            trace_ot_csrng_entropy_rejected(slot, "error", res);
+            return CSRNG_CMD_STALLED;
+        }
+
+        if (res > 0) {
+            s->entropy_delay = (res > 1) ? (unsigned)res : 0;
+            trace_ot_csrng_entropy_rejected(slot, "not ready", res);
+            return CSRNG_CMD_RETRY;
+        }
+
+        /* always perform XOR which is a no-op if material_len is zero */
+        for (unsigned ix = 0; ix < OT_ENTROPY_SRC_DWORD_COUNT; ix++) {
+            buffer[ix] ^= entropy[ix];
+        }
+        memcpy(drng->material, buffer, sizeof(entropy));
+        drng->material_len = sizeof(entropy) / (sizeof(uint32_t));
+        ot_csrng_drng_update(inst);
+        drng->no_fips |= !fips;
+    } else {
+        ot_csrng_drng_update(inst);
+        drng->no_fips = true;
+    }
+
+    drng->reseed_counter = 0u;
+    drng->seeded = true;
+    drng->force_fips = (bool)((s->regs[R_FIPS_FORCE] >> slot) & 0x1u);
+
+    return CSRNG_CMD_OK;
+}
+
+static void ot_csrng_drng_generate(OtCSRNGInstance *inst, uint32_t *out,
+                                   bool *fips)
+{
+    OtCSRNGDrng *drng = &inst->drng;
+
+    ot_csrng_drng_increment(drng);
+    drng->rem_packet_count -= 1u;
+
+    int res;
+
+    res = ecb_encrypt(drng->v_counter, (uint8_t *)out, OT_CSRNG_AES_BLOCK_SIZE,
+                      &drng->ecb);
+    g_assert(res == CRYPT_OK);
+
+    xtrace_ot_csrng_show_buffer(ot_csrng_get_slot(inst), "out", out,
+                                OT_CSRNG_AES_BLOCK_SIZE);
+
+    *fips = (!drng->no_fips) || drng->force_fips;
+
+    if (!ot_csrng_drng_remaining_count(inst)) {
+        ot_csrng_drng_update(inst);
+        /* last packet generation for the current command */
+        drng->reseed_counter += 1u;
+    }
+}
+
+/* -------------------------------------------------------------------------- */
+/* Private implementation */
+/* -------------------------------------------------------------------------- */
+
+static unsigned ot_csrng_get_slot(const OtCSRNGInstance *inst)
+{
+    unsigned slot = (unsigned)(uintptr_t)(inst - &inst->parent->instances[0]);
+    g_assert(slot <= SW_INSTANCE_ID);
+    return slot;
+}
+
+static void ot_csrng_update_irqs(OtCSRNGState *s)
+{
+    uint32_t level = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+    trace_ot_csrng_irqs(s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE], level);
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_csrng_update_alerts(OtCSRNGState *s)
+{
+    uint32_t level = s->regs[R_ALERT_TEST];
+    s->regs[R_ALERT_TEST] = 0u;
+
+    if (s->regs[R_RECOV_ALERT_STS]) {
+        level |= 1u << ALERT_RECOVERABLE;
+    }
+
+    if (s->state == CSRNG_ERROR) {
+        level |= 1u << ALERT_FATAL;
+    }
+
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+        ibex_irq_set(&s->alerts[ix], 0);
+    }
+}
+
+static void ot_csrng_change_state_line(OtCSRNGState *s, OtCSRNGFsmState state,
+                                       int line)
+{
+    trace_ot_csrng_change_state(line, STATE_NAME(s->state), s->state,
+                                STATE_NAME(state), state);
+
+    s->state = state;
+
+    if (s->state == CSRNG_ERROR) {
+        s->regs[R_INTR_STATE] |= INTR_CS_FATAL_ERR_MASK;
+        ot_csrng_update_irqs(s);
+        ot_csrng_update_alerts(s);
+    }
+}
+
+static bool
+ot_csrng_check_multibitboot(OtCSRNGState *s, uint8_t mbbool, uint32_t alert_bit)
+{
+    switch (mbbool) {
+    case OT_MULTIBITBOOL4_TRUE:
+        return true;
+    case OT_MULTIBITBOOL4_FALSE:
+        return false;
+    default:
+        break;
+    }
+
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid multiboot4: 0x%01x\n", __func__,
+                  (unsigned)mbbool);
+
+    s->regs[R_RECOV_ALERT_STS] |= 1u << alert_bit;
+    ot_csrng_update_alerts(s);
+
+    /* for CSRNG, default to false for invalid multibit boolean */
+    return false;
+}
+
+static bool ot_csrng_is_ctrl_enabled(OtCSRNGState *s)
+{
+    return FIELD_EX32(s->regs[R_CTRL], CTRL, ENABLE) == OT_MULTIBITBOOL4_TRUE;
+}
+
+static bool ot_csrng_is_ctrl_disabled(OtCSRNGState *s)
+{
+    return FIELD_EX32(s->regs[R_CTRL], CTRL, ENABLE) == OT_MULTIBITBOOL4_FALSE;
+}
+
+static bool ot_csrng_is_sw_app_enabled(OtCSRNGState *s)
+{
+    return s->sw_app_granted &&
+           FIELD_EX32(s->regs[R_CTRL], CTRL, SW_APP_ENABLE) ==
+               OT_MULTIBITBOOL4_TRUE;
+}
+
+static bool ot_csrng_is_in_queue(OtCSRNGInstance *inst)
+{
+    return QSIMPLEQ_NEXT(inst, cmd_request) ||
+           QSIMPLEQ_LAST(&inst->parent->cmd_requests, OtCSRNGInstance,
+                         cmd_request) == inst;
+}
+
+static void ot_csrng_release_hw_app(OtCSRNGInstance *inst)
+{
+    /* remove the command from the queue since it is handled right here */
+    OtCSRNGState *s = inst->parent;
+    if (ot_csrng_is_in_queue(inst)) {
+        QSIMPLEQ_REMOVE(&s->cmd_requests, inst, OtCSRNGInstance, cmd_request);
+    }
+
+    if (QSIMPLEQ_EMPTY(&s->cmd_requests)) {
+        qemu_bh_cancel(s->cmd_scheduler);
+        timer_del(s->entropy_scheduler);
+    }
+
+    unsigned slot = ot_csrng_get_slot(inst);
+    trace_ot_csrng_uninstantiate(slot, false);
+    ot_csrng_drng_uninstantiate(inst);
+
+    ot_fifo32_reset(&inst->cmd_fifo);
+    inst->defer_completion = false;
+
+    inst->hw.filler = NULL;
+    inst->hw.opaque = NULL;
+    inst->hw.req_sts = NULL;
+}
+
+static void ot_csrng_handle_enable(OtCSRNGState *s)
+{
+    if (ot_csrng_is_ctrl_enabled(s)) {
+        xtrace_ot_csrng_info("enabling CSRNG", 0);
+        s->enabled = true;
+        s->regs[R_SW_CMD_STS] |= R_SW_CMD_STS_CMD_RDY_MASK;
+        s->es_retry_count = ENTROPY_SRC_INITIAL_REQUEST_COUNT;
+    }
+
+    if (ot_csrng_is_ctrl_disabled(s)) {
+        xtrace_ot_csrng_info("disabling CSRNG", 0);
+        /* skip SW instance */
+        for (unsigned ix = 0u; ix < OT_CSRNG_HW_APP_MAX; ix++) {
+            OtCSRNGInstance *inst = &s->instances[ix];
+            if (inst->hw.filler) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: Forcing CSRNG disablement while EDN #%u "
+                              "still active\n",
+                              __func__, ot_csrng_get_slot(inst));
+
+                trace_ot_csrng_disconnection(ix, false);
+                ot_csrng_release_hw_app(inst);
+            }
+        }
+        s->enabled = false;
+        s->regs[R_SW_CMD_STS] &= ~R_SW_CMD_STS_CMD_RDY_MASK;
+        s->es_retry_count = 0;
+
+        /* cancel any outstanding asynchronous request */
+        qemu_bh_cancel(s->cmd_scheduler);
+        timer_del(s->entropy_scheduler);
+
+        /* discard any on-going command request */
+        OtCSRNGInstance *inst, *next;
+        QSIMPLEQ_FOREACH_SAFE(inst, &s->cmd_requests, cmd_request, next) {
+            xtrace_ot_csrng_info("discarding request for APP",
+                                 ot_csrng_get_slot(inst));
+            if (s->state != CSRNG_ERROR) {
+                /*
+                 * any ongoing command should be reported as failed, except if
+                 * is an unstantiate command, in which case it is immediately
+                 * completed
+                 */
+                OtCSRNGCmdStatus sts;
+                if (!ot_fifo32_is_empty(&inst->cmd_fifo)) {
+                    uint32_t cmd = ot_fifo32_peek(&inst->cmd_fifo);
+                    uint32_t acmd = FIELD_EX32(cmd, OT_CSNRG_CMD, ACMD);
+                    sts = acmd == OT_CSRNG_CMD_UNINSTANTIATE ?
+                              CSRNG_STATUS_SUCCESS :
+                              CSRNG_STATUS_INVALID_CMD_SEQ;
+                } else {
+                    sts = CSRNG_STATUS_INVALID_CMD_SEQ;
+                }
+                qemu_set_irq(inst->hw.req_sts, (int)sts);
+            }
+
+            QSIMPLEQ_REMOVE_HEAD(&s->cmd_requests, cmd_request);
+        }
+
+        /* reset all instances */
+        for (unsigned ix = 0u; ix < N_APP_COUNT; ix++) {
+            inst = &s->instances[ix];
+            ot_csrng_drng_uninstantiate(inst);
+            ot_fifo32_reset(&inst->cmd_fifo);
+            if (ix == SW_INSTANCE_ID) {
+                ot_fifo32_reset(&inst->sw.bits_fifo);
+                inst->sw.fips = false;
+            } else {
+                inst->hw.genbits_ready = false;
+            }
+        }
+
+        CHANGE_STATE(s, CSRNG_IDLE);
+
+        xtrace_ot_csrng_info("CSRNG disabled", 0);
+    }
+}
+
+static void ot_csrng_complete_sw_command(OtCSRNGInstance *inst, bool res)
+{
+    OtCSRNGState *s = inst->parent;
+
+    if (res == CSRNG_CMD_OK) {
+        s->regs[R_SW_CMD_STS] &= R_SW_CMD_STS_CMD_STS_MASK;
+    } else {
+        s->regs[R_SW_CMD_STS] |= R_SW_CMD_STS_CMD_STS_MASK;
+    }
+    s->regs[R_SW_CMD_STS] |= R_SW_CMD_STS_CMD_RDY_MASK;
+    s->regs[R_INTR_STATE] |= INTR_CS_CMD_REQ_DONE_MASK;
+
+    ot_csrng_update_irqs(s);
+}
+
+static void
+ot_csrng_complete_hw_command(OtCSRNGInstance *inst, OtCSRNGCmdStatus sts)
+{
+    qemu_set_irq(inst->hw.req_sts, (int)sts);
+}
+
+static void ot_csrng_complete_command(OtCSRNGInstance *inst,
+                                      OtCSRNGCmdStatus sts)
+{
+    uint32_t num;
+    const uint32_t *buffer =
+        ot_fifo32_peek_buf(&inst->cmd_fifo, ot_fifo32_num_used(&inst->cmd_fifo),
+                           &num);
+    uint32_t acmd = FIELD_EX32(buffer[0], OT_CSNRG_CMD, ACMD);
+
+    OtCSRNGState *s = inst->parent;
+
+    if (num > 1u) {
+        CHANGE_STATE(s, CSRNG_CLR_A_DATA);
+        buffer += 1u;
+        memset((uint32_t *)buffer, 0, sizeof(uint32_t) * (num - 1u));
+    }
+
+    ot_fifo32_reset(&inst->cmd_fifo);
+    inst->defer_completion = false;
+
+    unsigned slot = ot_csrng_get_slot(inst);
+
+    trace_ot_csrng_show_command("complete", slot, CMD_NAME(acmd), acmd);
+
+    if (slot == SW_INSTANCE_ID) {
+        trace_ot_csrng_complete_command(slot, "sw", CMD_NAME(acmd), acmd, sts);
+        ot_csrng_complete_sw_command(inst, sts);
+    } else {
+        trace_ot_csrng_complete_command(slot, "hw", CMD_NAME(acmd), acmd, sts);
+        ot_csrng_complete_hw_command(inst, sts);
+    }
+
+    CHANGE_STATE(s, CSRNG_IDLE);
+}
+
+static OtCSRNDCmdResult
+ot_csrng_handle_instantiate(OtCSRNGState *s, unsigned slot)
+{
+    OtCSRNGInstance *inst = &s->instances[slot];
+
+    trace_ot_csrng_instantiate(slot);
+
+    uint32_t command = ot_fifo32_peek(&inst->cmd_fifo);
+    uint32_t clen = FIELD_EX32(command, OT_CSNRG_CMD, CLEN);
+    bool flag0 =
+        FIELD_EX32(command, OT_CSNRG_CMD, FLAG0) == OT_MULTIBITBOOL4_TRUE;
+
+    uint32_t num;
+    const uint32_t *buffer =
+        ot_fifo32_peek_buf(&inst->cmd_fifo, ot_fifo32_num_used(&inst->cmd_fifo),
+                           &num);
+    g_assert(num - 1u == clen);
+    buffer += 1u;
+
+    if (clen) {
+        /* ignore trailing additional words, as HW does */
+        clen = MIN(clen, OT_CSRNG_CMD_WORD_MAX);
+        xtrace_ot_csrng_show_buffer(ot_csrng_get_slot(inst), "mat", buffer,
+                                    clen * sizeof(uint32_t));
+    }
+
+    ot_csrng_drng_store_material(inst, buffer, clen);
+
+    int res;
+
+    res = ot_csrng_drng_instantiate(inst, flag0);
+    if ((res == CSRNG_CMD_OK) && !flag0) {
+        /* if flag0 is set, entropy source is not used for reseeding */
+        s->regs[R_INTR_STATE] |= INTR_CS_ENTROPY_REQ_MASK;
+        ot_csrng_update_irqs(s);
+    }
+
+    return res;
+}
+
+static OtCSRNDCmdResult
+ot_csrng_handle_uninstantiate(OtCSRNGState *s, unsigned slot)
+{
+    OtCSRNGInstance *inst = &s->instances[slot];
+
+    trace_ot_csrng_uninstantiate(slot, true);
+
+    ot_csrng_drng_uninstantiate(inst);
+
+    return CSRNG_CMD_OK;
+}
+
+static OtCSRNDCmdResult ot_csrng_handle_generate(OtCSRNGState *s, unsigned slot)
+{
+    OtCSRNGInstance *inst = &s->instances[slot];
+
+    uint32_t command = ot_fifo32_peek(&inst->cmd_fifo);
+    uint32_t packet_count = FIELD_EX32(command, OT_CSNRG_CMD, GLEN);
+
+    if (!packet_count) {
+        xtrace_ot_csrng_error("generation for no packet");
+        CHANGE_STATE(s, CSRNG_ERROR);
+        ot_csrng_update_alerts(s);
+        return CSRNG_CMD_INVALID_GEN_CMD;
+    }
+
+    uint32_t clen = FIELD_EX32(command, OT_CSNRG_CMD, CLEN);
+    if (clen) {
+        uint32_t num;
+        const uint32_t *buffer =
+            ot_fifo32_peek_buf(&inst->cmd_fifo,
+                               ot_fifo32_num_used(&inst->cmd_fifo), &num);
+        g_assert(num - 1u == clen);
+        buffer += 1u;
+        /* ignore trailing additional words, as HW does */
+        clen = MIN(clen, OT_CSRNG_CMD_WORD_MAX);
+
+        xtrace_ot_csrng_show_buffer(ot_csrng_get_slot(inst), "mat", buffer,
+                                    clen * sizeof(uint32_t));
+        ot_csrng_drng_store_material(inst, buffer, clen);
+    }
+
+    trace_ot_csrng_generate(ot_csrng_get_slot(inst), packet_count);
+
+    OtCSRNGDrng *drng = &inst->drng;
+    g_assert(drng->instantiated);
+
+    if (ot_csrng_drng_remaining_count(inst)) {
+        xtrace_ot_csrng_info("remaining packets to generate",
+                             ot_csrng_drng_remaining_count(inst));
+        xtrace_ot_csrng_error("New generate request before completion");
+        /* should we resume? */
+    }
+
+    inst->drng.rem_packet_count = packet_count;
+
+    /*
+     * do not ack command yet,
+     * should only be completed once remamining packets reach zero
+     */
+    return CSRNG_CMD_DEFERRED;
+}
+
+static OtCSRNDCmdResult ot_csrng_handle_reseed(OtCSRNGState *s, unsigned slot)
+{
+    OtCSRNGInstance *inst = &s->instances[slot];
+
+    uint32_t command = ot_fifo32_peek(&inst->cmd_fifo);
+    bool flag0 =
+        FIELD_EX32(command, OT_CSNRG_CMD, FLAG0) == OT_MULTIBITBOOL4_TRUE;
+
+    xtrace_ot_csrng_info("reseed", flag0);
+
+    uint32_t clen = FIELD_EX32(command, OT_CSNRG_CMD, CLEN);
+    if (clen) {
+        uint32_t num;
+        const uint32_t *buffer =
+            ot_fifo32_peek_buf(&inst->cmd_fifo,
+                               ot_fifo32_num_used(&inst->cmd_fifo), &num);
+        g_assert(num - 1u == clen);
+        buffer += 1u;
+        /* ignore trailing additional words, as HW does */
+        clen = MIN(clen, OT_CSRNG_CMD_WORD_MAX);
+
+        xtrace_ot_csrng_show_buffer(ot_csrng_get_slot(inst), "mat", buffer,
+                                    clen * sizeof(uint32_t));
+
+        ot_csrng_drng_store_material(inst, buffer, clen);
+    }
+
+    int res;
+    res = ot_csrng_drng_reseed(inst, flag0);
+    if ((res == CSRNG_CMD_OK) && !flag0) {
+        /* if flag0 is set, entropy source is not used for reseeding */
+        s->regs[R_INTR_STATE] |= INTR_CS_ENTROPY_REQ_MASK;
+        ot_csrng_update_irqs(s);
+    }
+
+    return res;
+}
+
+static OtCSRNDCmdResult ot_csrng_handle_update(OtCSRNGState *s, unsigned slot)
+{
+    OtCSRNGInstance *inst = &s->instances[slot];
+
+    xtrace_ot_csrng_info("update", 0);
+
+    uint32_t command = ot_fifo32_peek(&inst->cmd_fifo);
+    uint32_t clen = FIELD_EX32(command, OT_CSNRG_CMD, CLEN);
+
+    if (clen) {
+        uint32_t num;
+        const uint32_t *buffer =
+            ot_fifo32_peek_buf(&inst->cmd_fifo,
+                               ot_fifo32_num_used(&inst->cmd_fifo), &num);
+        g_assert(num - 1u == clen);
+        buffer += 1u;
+        /* ignore trailing additional words, as HW does */
+        clen = MIN(clen, OT_CSRNG_CMD_WORD_MAX);
+
+        xtrace_ot_csrng_show_buffer(ot_csrng_get_slot(inst), "mat", buffer,
+                                    clen * sizeof(uint32_t));
+
+        ot_csrng_drng_store_material(inst, buffer, clen);
+    }
+
+    ot_csrng_drng_update(inst);
+
+    return CSRNG_CMD_OK;
+}
+
+static void ot_csrng_hwapp_ready_irq(void *opaque, int n, int level)
+{
+    /* signaled by a CSRNG HW APP client */
+    OtCSRNGState *s = opaque;
+
+    unsigned slot = (unsigned)n;
+    g_assert(slot < OT_CSRNG_HW_APP_MAX);
+    bool ready = (bool)level;
+
+    OtCSRNGInstance *inst = &s->instances[slot];
+    inst->hw.genbits_ready = ready;
+
+    trace_ot_csrng_hwapp_ready(slot, ready,
+                               ot_csrng_drng_remaining_count(inst));
+
+    if (ready) {
+        if (!inst->drng.seeded) {
+            /*
+             * instanciation has not completed yet, wait for generation.
+             * see #ot_csrng_drng_instanciate
+             */
+            trace_ot_csrng_defer_generation(slot);
+        } else {
+            qemu_bh_schedule(inst->hw.filler_bh);
+        }
+    }
+}
+
+static void ot_csrng_hwapp_filler_bh(void *opaque)
+{
+    /* scheduled following a CSRNG HW APP client ready to receive entropy */
+    OtCSRNGInstance *inst = opaque;
+
+    /*
+     * client may have updated its readiness status since this BH has been
+     * scheduled, readiness should always be tested
+     */
+    if (inst->hw.genbits_ready && ot_csrng_drng_remaining_count(inst)) {
+        uint32_t bits[OT_CSRNG_PACKET_WORD_COUNT];
+        bool fips;
+        ot_csrng_drng_generate(inst, bits, &fips);
+
+        /*
+         * client callback may trigger ot_csrng_hwapp_ready_irq to update its
+         * readiness status, so client state past this point may have been
+         * updated
+         */
+        inst->hw.filler(inst->hw.opaque, bits, fips);
+
+        /*
+         * reschedule self if the client does not update its readiness, it
+         * expects more entropy from this instance.
+         */
+        if (ot_csrng_drng_remaining_count(inst)) {
+            qemu_bh_schedule(inst->hw.filler_bh);
+        }
+    }
+
+    /* check if the instance is running a deferred completion command */
+    if (inst->defer_completion) {
+        /*
+         * if no more entropy packets can be generated with the current
+         * command signal the command completion to the client, whatever
+         * its readiness status (only generate commands complete async.)
+         */
+        if (!ot_csrng_drng_remaining_count(inst)) {
+            ot_csrng_complete_command(inst, CSRNG_STATUS_SUCCESS);
+        }
+    }
+}
+
+static void ot_csrng_swapp_fill(OtCSRNGInstance *inst)
+{
+    unsigned count = ot_csrng_drng_remaining_count(inst);
+
+    if (count > 0) {
+        /* refill SW FIFO */
+        trace_ot_csrng_swapp_fill(count);
+        uint32_t bits[OT_CSRNG_PACKET_WORD_COUNT];
+        ot_csrng_drng_generate(inst, bits, &inst->sw.fips);
+        for (unsigned ix = 0; ix < OT_CSRNG_PACKET_WORD_COUNT; ix++) {
+            /* reverse all bytes to fit OpenTitan order */
+            ot_fifo32_push(&inst->sw.bits_fifo,
+                           bswap32(bits[OT_CSRNG_PACKET_WORD_COUNT - ix - 1u]));
+        }
+        xtrace_ot_csrng_info("swfifo empty",
+                             ot_fifo32_is_empty(&inst->sw.bits_fifo));
+    } else {
+        /* check if the instance is running an deferred completion command */
+        if (inst->defer_completion) {
+            ot_csrng_complete_command(inst, CSRNG_STATUS_SUCCESS);
+        }
+    }
+}
+
+static bool
+ot_csrng_instance_is_command_ready(const OtCSRNGInstance *inst, bool fatal)
+{
+    /* there should be a full command stored in the command FIFO */
+    if (ot_fifo32_is_empty(&inst->cmd_fifo)) {
+        return false;
+    }
+    uint32_t command = ot_fifo32_peek(&inst->cmd_fifo);
+    uint32_t length = FIELD_EX32(command, OT_CSNRG_CMD, CLEN) + 1u;
+
+    bool is_ready = ot_fifo32_num_used(&inst->cmd_fifo) == length;
+
+    if (fatal && !is_ready) {
+        unsigned word_count = ot_fifo32_num_used(&inst->cmd_fifo);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %u: command 0x%06x empty: %u, length %u, exp: %u\n",
+                      __func__, ot_csrng_get_slot(inst), command,
+                      ot_fifo32_is_empty(&inst->cmd_fifo), word_count, length);
+        if (word_count < length) {
+            xtrace_ot_csrng_error("cannot execute an incomplete command");
+        } else {
+            xtrace_ot_csrng_error("cannot execute an overflowed command");
+        }
+    }
+
+    return is_ready;
+}
+
+static OtCSRNDCmdResult ot_csrng_handle_command(OtCSRNGState *s, unsigned slot)
+{
+    OtCSRNGInstance *inst = &s->instances[slot];
+
+    /* note: cmd_fifo is only emptied when command has been completed */
+    uint32_t command = ot_fifo32_peek(&inst->cmd_fifo);
+
+    uint32_t acmd = FIELD_EX32(command, OT_CSNRG_CMD, ACMD);
+
+    trace_ot_csrng_show_command("handle", slot, CMD_NAME(acmd), acmd);
+
+    switch (acmd) {
+    case OT_CSRNG_CMD_INSTANTIATE:
+    case OT_CSRNG_CMD_RESEED:
+        break;
+    case OT_CSRNG_CMD_GENERATE:
+        g_assert(slot == SW_INSTANCE_ID || inst->hw.filler);
+        break;
+    case OT_CSRNG_CMD_UPDATE:
+    case OT_CSRNG_CMD_UNINSTANTIATE:
+        break;
+    case OT_CSRNG_CMD_NONE:
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "Unknown command: %u\n", acmd);
+        // JW: check this shouldn't be CMD_STAGE_INVALID_CMD_SEQ_ALERT.
+        s->regs[R_RECOV_ALERT_STS] |=
+            R_RECOV_ALERT_STS_CMD_STAGE_INVALID_ACMD_ALERT_MASK;
+        CHANGE_STATE(s, CSRNG_ERROR);
+        ot_csrng_update_alerts(s);
+        return CSRNG_CMD_INVALID_ACMD;
+    }
+
+    if (!s->enabled) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: not enabled\n", __func__);
+        return CSRNG_CMD_INVALID_ACMD;
+    }
+
+    switch (acmd) {
+    case OT_CSRNG_CMD_INSTANTIATE:
+        if (ot_csrng_drng_is_instantiated(inst)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: instance %u already active\n",
+                          __func__, slot);
+            return CSRNG_CMD_INVALID_CMD_SEQ;
+        }
+        break;
+    case OT_CSRNG_CMD_UNINSTANTIATE:
+        break;
+    default:
+        if (!ot_csrng_drng_is_instantiated(inst)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: instance %u not instantiated\n",
+                          __func__, slot);
+            CHANGE_STATE(s, CSRNG_ERROR);
+            ot_csrng_update_alerts(s);
+            return CSRNG_CMD_INVALID_CMD_SEQ;
+        }
+    }
+
+    OtCSRNDCmdResult res;
+
+    switch (acmd) {
+    case OT_CSRNG_CMD_INSTANTIATE:
+        CHANGE_STATE(s, CSRNG_INSTANT_REQ);
+        res = ot_csrng_handle_instantiate(s, slot);
+        break;
+    case OT_CSRNG_CMD_RESEED:
+        CHANGE_STATE(s, CSRNG_RESEED_REQ);
+        res = ot_csrng_handle_reseed(s, slot);
+        break;
+    case OT_CSRNG_CMD_GENERATE:
+        CHANGE_STATE(s, CSRNG_GENERATE_REQ);
+        res = ot_csrng_handle_generate(s, slot);
+        if (res == CSRNG_CMD_DEFERRED) {
+            if (ot_csrng_drng_remaining_count(inst)) {
+                if (slot != SW_INSTANCE_ID) {
+                    /* HW instance */
+                    if (inst->hw.genbits_ready) {
+                        qemu_bh_schedule(inst->hw.filler_bh);
+                    } else {
+                        xtrace_ot_csrng_info("genbit not ready", slot);
+                    }
+                } else {
+                    /* SW instance */
+                    ot_csrng_swapp_fill(inst);
+                }
+            }
+        }
+        break;
+    case OT_CSRNG_CMD_UPDATE:
+        CHANGE_STATE(s, CSRNG_UPDATE_REQ);
+        res = ot_csrng_handle_update(s, slot);
+        break;
+    case OT_CSRNG_CMD_UNINSTANTIATE:
+        CHANGE_STATE(s, CSRNG_UNINSTANT_REQ);
+        res = ot_csrng_handle_uninstantiate(s, slot);
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+
+    return res;
+}
+
+static void ot_csrng_command_schedule(OtCSRNGState *s, OtCSRNGInstance *inst)
+{
+    bool queued = ot_csrng_is_in_queue(inst);
+    if (queued) {
+        /* execution resumes, but this is likely internal bug...*/
+        error_report("%s: instance executing several commands at once",
+                     __func__);
+        s->regs[R_INTR_STATE] |= INTR_CS_HW_INST_EXC_MASK;
+        ot_csrng_update_irqs(s);
+        g_assert(false);
+        return;
+    }
+
+    QSIMPLEQ_INSERT_TAIL(&s->cmd_requests, inst, cmd_request);
+
+    trace_ot_csrng_schedule(ot_csrng_get_slot(inst), "command");
+    timer_del(s->entropy_scheduler);
+    qemu_bh_schedule(s->cmd_scheduler);
+}
+
+static void ot_csrng_command_scheduler(void *opaque)
+{
+    OtCSRNGState *s = opaque;
+
+    /* handle a single instance per cycle */
+    OtCSRNGInstance *inst = QSIMPLEQ_FIRST(&s->cmd_requests);
+    if (!inst) {
+        xtrace_ot_csrng_error("scheduled request w/o request?");
+        g_assert_not_reached();
+    }
+
+    if (s->state != CSRNG_IDLE) {
+        trace_ot_csrng_invalid_state(__func__, STATE_NAME(s->state), s->state);
+        g_assert_not_reached();
+    }
+
+    uint32_t command = ot_fifo32_peek(&inst->cmd_fifo);
+    uint32_t acmd = FIELD_EX32(command, OT_CSNRG_CMD, ACMD);
+    unsigned slot = ot_csrng_get_slot(inst);
+
+    trace_ot_csrng_show_command("pop", slot, CMD_NAME(acmd), acmd);
+
+    if (!ot_csrng_instance_is_command_ready(inst, true)) {
+        g_assert_not_reached();
+    }
+
+    CHANGE_STATE(s, CSRNG_PARSE_CMD);
+
+    /*
+     * instance's command has been checked, remove it from the queue.
+     * it is re-inserted to the tail if it cannot be completed for now. Doing so
+     * allow a round-robin sequencing between several instances each requiring
+     * command processing.
+     */
+    QSIMPLEQ_REMOVE_HEAD(&s->cmd_requests, cmd_request);
+
+    /*
+     * current instance has a pending command.
+     * handle it, and prevent any other instances to be handled
+     * in this round.
+     */
+    trace_ot_csrng_command_scheduler(slot, "cmd ready, execute");
+    OtCSRNDCmdResult res;
+    res = ot_csrng_handle_command(s, slot);
+    switch (res) {
+    case CSRNG_CMD_RETRY:
+        CHANGE_STATE(s, CSRNG_IDLE);
+        /* command re-insertion */
+        trace_ot_csrng_show_command("push back", slot, CMD_NAME(acmd), acmd);
+        QSIMPLEQ_INSERT_TAIL(&s->cmd_requests, inst, cmd_request);
+        break;
+    case CSRNG_CMD_DEFERRED:
+        inst->defer_completion = true;
+        CHANGE_STATE(s, CSRNG_IDLE);
+        break;
+    case CSRNG_CMD_STALLED:
+        xtrace_ot_csrng_error("entropy stack stalled");
+        /* discard any remaining requests, nothing can be done any further */
+        while (!QSIMPLEQ_EMPTY(&s->cmd_requests)) {
+            QSIMPLEQ_REMOVE_HEAD(&s->cmd_requests, cmd_request);
+        }
+        /* do not complete command either */
+        break;
+    case CSRNG_CMD_OK:
+        ot_csrng_complete_command(inst, CSRNG_STATUS_SUCCESS);
+        break;
+    default:
+        trace_ot_csrng_reject_command(slot, command, res);
+        /*
+         * Negative res values are errors, encoding the type of command error.
+         * Convert the encoded error back into a OtCSRNGCmdStatus.
+         */
+        ot_csrng_complete_command(inst, -res);
+        break;
+    }
+
+    if (!QSIMPLEQ_EMPTY(&s->cmd_requests)) {
+        if (s->state != CSRNG_ERROR) {
+            trace_ot_csrng_scheduling_command(slot);
+            if (CSRNG_CMD_RETRY == res && s->entropy_delay) {
+                timer_mod(s->entropy_scheduler,
+                          qemu_clock_get_ns(OT_VIRTUAL_CLOCK) +
+                              (int64_t)s->entropy_delay);
+                s->entropy_delay = 0;
+            } else {
+                qemu_bh_schedule(s->cmd_scheduler);
+            }
+        } else {
+            xtrace_ot_csrng_error("cannot schedule new command on error");
+        }
+    }
+}
+
+static uint32_t ot_csrng_read_state_db(OtCSRNGState *s)
+{
+    unsigned appid = s->regs[R_INT_STATE_NUM];
+    if (appid >= N_APP_COUNT) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid appid %d\n", __func__,
+                      appid);
+        return 0;
+    }
+    if (!s->read_int_granted) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: read state db disabled\n",
+                      __func__);
+        return 0;
+    }
+    if (!((s->regs[R_INT_STATE_READ_ENABLE] >> appid) & 0x1)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: read state db not enable for %d\n",
+                      __func__, appid);
+        return 0;
+    }
+
+    OtCSRNGInstance *inst = &s->instances[appid];
+    OtCSRNGDrng *drng = &inst->drng;
+    uint32_t val32;
+    unsigned base;
+    switch (s->state_db_ix) {
+    case 0: /* Reseed counter */
+        val32 = drng->reseed_counter;
+        break;
+    case 1u ... 4u: /* V (counter) */
+        /* use big endian and reverse order to match OpenTitan order */
+        base = 4u - s->state_db_ix;
+        val32 = ldl_be_p(&drng->v_counter[base * sizeof(uint32_t)]);
+        break;
+    case 5u ... 12u: /* Key */
+        /* use big endian and reverse order to match OpenTitan order */
+        base = 12u - s->state_db_ix;
+        val32 = ldl_be_p(&drng->key[base * sizeof(uint32_t)]);
+        break;
+    case 13u: /* Status + Compliance, only 8 LSBs matter */
+        val32 = (uint32_t)((((uint8_t)drng->instantiated) << 0u) |
+                           (((uint8_t)!drng->no_fips) << 1u));
+        break;
+    default:
+        val32 = 0;
+        break;
+    }
+
+    trace_ot_csrng_read_state_db(ot_csrng_get_slot(inst), s->state_db_ix,
+                                 val32);
+
+    s->state_db_ix += 1u;
+    if (s->state_db_ix >= 14u) {
+        s->state_db_ix = 0;
+    }
+
+    return val32;
+}
+
+static uint64_t ot_csrng_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtCSRNGState *s = opaque;
+    (void)size;
+    uint32_t val32;
+    OtCSRNGInstance *inst;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_REGWEN:
+    case R_CTRL:
+    case R_RESEED_INTERVAL:
+    case R_SW_CMD_STS:
+    case R_INT_STATE_NUM:
+    case R_HW_EXC_STS:
+    case R_RECOV_ALERT_STS:
+    case R_ERR_CODE:
+    case R_ERR_CODE_TEST:
+        val32 = s->regs[reg];
+        break;
+    case R_RESEED_COUNTER_0:
+    case R_RESEED_COUNTER_1:
+    case R_RESEED_COUNTER_2: {
+        unsigned appid = reg - R_RESEED_COUNTER_0;
+        g_assert(appid < N_APP_COUNT);
+        inst = &s->instances[appid];
+        const OtCSRNGDrng *drng = &inst->drng;
+        val32 = drng->reseed_counter;
+    } break;
+    case R_INT_STATE_VAL:
+        val32 = ot_csrng_read_state_db(s);
+        break;
+    case R_MAIN_SM_STATE:
+        switch (s->state) {
+        case CSRNG_IDLE ... CSRNG_ERROR:
+            val32 = OtCSRNGFsmStateCode[s->state];
+            break;
+        default:
+            val32 = OtCSRNGFsmStateCode[CSRNG_ERROR];
+            break;
+        }
+        break;
+    case R_GENBITS_VLD:
+        inst = &s->instances[SW_INSTANCE_ID];
+        if (ot_csrng_is_sw_app_enabled(s)) {
+            bool avail = !ot_fifo32_is_empty(&inst->sw.bits_fifo);
+            val32 = FIELD_DP32(0, GENBITS_VLD, GENBITS_VLD, (uint32_t)avail);
+            val32 = FIELD_DP32(val32, GENBITS_VLD, GENBITS_FIPS, inst->sw.fips);
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "SW APP not enabled\n");
+            val32 = 0;
+        }
+        break;
+    case R_GENBITS:
+        if (ot_csrng_is_sw_app_enabled(s)) {
+            inst = &s->instances[SW_INSTANCE_ID];
+            if (!ot_fifo32_is_empty(&inst->sw.bits_fifo)) {
+                val32 = ot_fifo32_pop(&inst->sw.bits_fifo);
+                xtrace_ot_csrng_info("pop", val32);
+                if (ot_fifo32_is_empty(&inst->sw.bits_fifo)) {
+                    /* keep the SW FIFO filled up till end of generation */
+                    ot_csrng_swapp_fill(inst);
+                }
+            } else {
+                /* TBC: need to check if some error is signaled in ERR_CODE */
+                qemu_log_mask(LOG_GUEST_ERROR, "FIFO read w/ entropy bits\n");
+                val32 = 0;
+            }
+        } else {
+            val32 = 0;
+        }
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+    case R_CMD_REQ:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_csrng_io_read_out((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_csrng_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                unsigned size)
+{
+    OtCSRNGState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+    OtCSRNGInstance *inst;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_csrng_io_write((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_csrng_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[reg] = val32;
+        ot_csrng_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] |= val32;
+        ot_csrng_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        s->regs[reg] = val32;
+        ot_csrng_update_alerts(s);
+        break;
+    case R_REGWEN:
+        val32 &= R_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* rw0c */
+        break;
+    case R_CTRL:
+        if (!s->regs[R_REGWEN]) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s protected w/ REGWEN\n",
+                          __func__, REG_NAME(reg));
+            break;
+        }
+        uint32_t prev = s->regs[reg];
+        val32 &= CTRL_MASK;
+        s->regs[reg] = val32;
+        CHECK_MULTIBOOT(s, CTRL, ENABLE);
+        CHECK_MULTIBOOT(s, CTRL, SW_APP_ENABLE);
+        CHECK_MULTIBOOT(s, CTRL, READ_INT_STATE);
+        CHECK_MULTIBOOT(s, CTRL, FIPS_FORCE_ENABLE);
+        uint32_t change = val32 ^ prev;
+        if (change) {
+            xtrace_ot_csrng_info("handling CTRL change", val32);
+            ot_csrng_handle_enable(s);
+
+            OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+            OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+            const OtOTPHWCfg *hw_cfg = oc->get_hw_cfg(oi);
+            g_assert(hw_cfg);
+            if (hw_cfg->en_csrng_sw_app_read_mb8 == OT_MULTIBITBOOL8_TRUE) {
+                uint32_t sw_app_en = FIELD_EX32(val32, CTRL, SW_APP_ENABLE);
+                s->sw_app_granted = sw_app_en == OT_MULTIBITBOOL4_TRUE;
+                uint32_t read_int = FIELD_EX32(val32, CTRL, READ_INT_STATE);
+                s->read_int_granted = read_int == OT_MULTIBITBOOL4_TRUE;
+            } else {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: SW APP disabled in OTP\n",
+                              __func__);
+                s->sw_app_granted = false;
+                s->read_int_granted = false;
+            }
+        }
+        break;
+    case R_CMD_REQ:
+        inst = &s->instances[SW_INSTANCE_ID];
+        if (!ot_fifo32_is_full(&inst->cmd_fifo)) {
+            ot_fifo32_push(&inst->cmd_fifo, val32);
+            if (ot_csrng_instance_is_command_ready(inst, false)) {
+                /*
+                 * assume CMD RDY works the same way as the csrng_req_ready
+                 * wire, which is a blind guess, need to check RTL here
+                 */
+                s->regs[R_SW_CMD_STS] &= ~R_SW_CMD_STS_CMD_RDY_MASK;
+                ot_csrng_command_schedule(s, inst);
+            }
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: cmd req overflow\n", __func__);
+            s->regs[R_SW_CMD_STS] &= ~R_SW_CMD_STS_CMD_RDY_MASK;
+            /* TBC: how to signal this error */
+        }
+        break;
+    case R_RESEED_INTERVAL:
+        s->regs[reg] = val32;
+        ot_csrng_update_irqs(s);
+        break;
+    case R_INT_STATE_READ_ENABLE:
+        if (!s->regs[R_INT_STATE_READ_ENABLE_REGWEN]) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s protected w/ REGWEN\n",
+                          __func__, REG_NAME(reg));
+            break;
+        }
+        val32 &= R_INT_STATE_READ_ENABLE_VAL_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_INT_STATE_READ_ENABLE_REGWEN:
+        val32 &= R_INT_STATE_READ_ENABLE_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* rw0c */
+        break;
+    case R_INT_STATE_NUM:
+        if (s->read_int_granted) {
+            val32 &= R_INT_STATE_NUM_VAL_MASK;
+            s->regs[reg] = val32;
+            s->state_db_ix = 0;
+            if (val32 > OT_CSRNG_HW_APP_MAX) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid INT_STATE_NUM %u\n",
+                              __func__, val32);
+            }
+        }
+        break;
+    case R_FIPS_FORCE:
+        if (!s->regs[R_REGWEN]) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s protected w/ REGWEN\n",
+                          __func__, REG_NAME(reg));
+            break;
+        }
+        val32 &= R_FIPS_FORCE_VAL_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_HW_EXC_STS:
+        val32 &= R_HW_EXC_STS_VAL_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_RECOV_ALERT_STS:
+        val32 &= RECOV_ALERT_STS_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        ot_csrng_update_alerts(s);
+        break;
+    case R_ERR_CODE_TEST:
+        if (!s->regs[R_REGWEN]) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s protected w/ REGWEN\n",
+                          __func__, REG_NAME(reg));
+            break;
+        }
+        val32 &= R_ERR_CODE_TEST_VAL_MASK;
+        val32 = 1u << val32;
+        val32 &= ERR_CODE_MASK;
+        s->regs[R_ERR_CODE] = val32;
+        break;
+    case R_RESEED_COUNTER_0:
+    case R_RESEED_COUNTER_1:
+    case R_RESEED_COUNTER_2:
+    case R_SW_CMD_STS:
+    case R_GENBITS_VLD:
+    case R_GENBITS:
+    case R_INT_STATE_VAL:
+    case R_ERR_CODE:
+    case R_MAIN_SM_STATE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        // JW: handle new registers.
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+};
+
+static const Property ot_csrng_properties[] = {
+    DEFINE_PROP_LINK("entropy-src", OtCSRNGState, entropy_src,
+                     TYPE_OT_ENTROPY_SRC, OtEntropySrcState *),
+    DEFINE_PROP_LINK("otp-ctrl", OtCSRNGState, otp_ctrl, TYPE_OT_OTP_IF,
+                     DeviceState *),
+};
+
+static const MemoryRegionOps ot_csrng_regs_ops = {
+    .read = &ot_csrng_regs_read,
+    .write = &ot_csrng_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_csrng_reset_enter(Object *obj, ResetType type)
+{
+    OtCSRNGClass *c = OT_CSRNG_GET_CLASS(obj);
+    OtCSRNGState *s = OT_CSRNG(obj);
+
+    trace_ot_csrng_reset();
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    qemu_bh_cancel(s->cmd_scheduler);
+    timer_del(s->entropy_scheduler);
+    for (unsigned ix = 0; ix < OT_CSRNG_HW_APP_MAX; ix++) {
+        g_assert(ix != SW_INSTANCE_ID);
+        OtCSRNGInstance *inst = &s->instances[ix];
+        qemu_bh_cancel(inst->hw.filler_bh);
+    }
+    s->entropy_delay = 0;
+
+    memset(s->regs, 0, REGS_SIZE);
+
+    s->regs[R_REGWEN] = 0x1u;
+    s->regs[R_CTRL] = 0x9999u;
+    s->regs[R_RESEED_INTERVAL] = 0xffffffffu;
+    s->regs[R_INT_STATE_READ_ENABLE_REGWEN] = 0x1u;
+    s->regs[R_INT_STATE_READ_ENABLE] = 0x7u;
+    s->regs[R_MAIN_SM_STATE] = 0x4eu;
+    s->enabled = false;
+    s->sw_app_granted = false;
+    s->read_int_granted = false;
+    s->es_retry_count = 0;
+    s->state = CSRNG_IDLE;
+
+    for (unsigned ix = 0; ix < N_APP_COUNT; ix++) {
+        OtCSRNGInstance *inst = &s->instances[ix];
+        g_assert(inst->parent);
+        ot_fifo32_reset(&inst->cmd_fifo);
+        if (ix == SW_INSTANCE_ID) {
+            ot_fifo32_reset(&inst->sw.bits_fifo);
+            inst->sw.fips = false;
+        }
+        OtCSRNGDrng *drng = &inst->drng;
+        memset(drng, 0, sizeof(*drng));
+    }
+    ot_csrng_update_irqs(s);
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->alerts[ix], 0);
+    }
+
+    while (!QSIMPLEQ_EMPTY(&s->cmd_requests)) {
+        QSIMPLEQ_REMOVE_HEAD(&s->cmd_requests, cmd_request);
+    }
+}
+
+static void ot_csrng_realize(DeviceState *dev, Error **errp)
+{
+    OtCSRNGState *s = OT_CSRNG(dev);
+    (void)errp;
+
+    g_assert(s->entropy_src);
+    g_assert(s->otp_ctrl);
+
+    (void)OBJECT_CHECK(OtOTPIf, s->otp_ctrl, TYPE_OT_OTP_IF);
+}
+
+static void ot_csrng_init(Object *obj)
+{
+    OtCSRNGState *s = OT_CSRNG(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_csrng_regs_ops, s, TYPE_OT_CSRNG,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    /* aes_desc is defined in libtomcrypt */
+    s->aes_cipher = register_cipher(&aes_desc);
+    if (s->aes_cipher < 0) {
+        error_report("%s: unable to use libtomcrypt AES API", __func__);
+    }
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    qdev_init_gpio_in_named_with_opaque(DEVICE(s), &ot_csrng_hwapp_ready_irq, s,
+                                        TYPE_OT_CSRNG "-genbits_ready",
+                                        OT_CSRNG_HW_APP_MAX);
+
+    static_assert(CMD_FIFO_CAPACITY >= OT_CSRNG_CMD_WORD_MAX,
+                  "Invalid CMD FIFO size");
+    /* HW instances + 1 internal SW instance */
+    s->instances = g_new0(OtCSRNGInstance, N_APP_COUNT);
+    OtCSRNGInstance *inst = &s->instances[SW_INSTANCE_ID];
+    for (unsigned ix = 0; ix < N_APP_COUNT; ix++) {
+        inst = &s->instances[ix];
+        inst->parent = s;
+        ot_fifo32_create(&inst->cmd_fifo, CMD_FIFO_CAPACITY);
+        if (ix != SW_INSTANCE_ID) {
+            inst->hw.filler_bh = qemu_bh_new(&ot_csrng_hwapp_filler_bh, inst);
+        }
+    }
+    /* current instance is the SW instance */
+    ot_fifo32_create(&inst->sw.bits_fifo, OT_CSRNG_PACKET_WORD_COUNT);
+
+    s->cmd_scheduler = qemu_bh_new(&ot_csrng_command_scheduler, s);
+    s->entropy_scheduler =
+        timer_new_ns(OT_VIRTUAL_CLOCK, &ot_csrng_command_scheduler, s);
+
+    QSIMPLEQ_INIT(&s->cmd_requests);
+}
+
+static void ot_csrng_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_csrng_realize;
+    device_class_set_props(dc, ot_csrng_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtCSRNGClass *cc = OT_CSRNG_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_csrng_reset_enter, NULL, NULL,
+                                       &cc->parent_phases);
+
+    cc->connect_hw_app = &ot_csrng_connect_hw_app;
+    cc->push_command = &ot_csrng_push_command;
+}
+
+static const TypeInfo ot_csrng_info = {
+    .name = TYPE_OT_CSRNG,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtCSRNGState),
+    .instance_init = &ot_csrng_init,
+    .class_size = sizeof(OtCSRNGClass),
+    .class_init = &ot_csrng_class_init,
+};
+
+static void ot_csrng_register_types(void)
+{
+    type_register_static(&ot_csrng_info);
+}
+
+type_init(ot_csrng_register_types);
diff --git a/hw/opentitan/ot_dev_proxy.c b/hw/opentitan/ot_dev_proxy.c
new file mode 100644
index 0000000000000..039f8c4346a8e
--- /dev/null
+++ b/hw/opentitan/ot_dev_proxy.c
@@ -0,0 +1,2080 @@
+/*
+ * QEMU OpenTitan Device Proxy
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/fifo8.h"
+#include "qemu/log-for-trace.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "qapi/qapi-commands-misc.h"
+#include "qom/object.h"
+#include "chardev/char-fe.h"
+#include "hw/core/cpu.h"
+#include "hw/irq.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_dev_proxy.h"
+#include "hw/opentitan/ot_mbx.h"
+#include "hw/opentitan/ot_soc_proxy.h"
+#include "hw/opentitan/ot_sram_ctrl.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/sysbus.h"
+#include "system/memory.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+/* ------------------------------------------------------------------------ */
+/* Register definitions */
+/* ------------------------------------------------------------------------ */
+
+/* clang-format off */
+/*
+ * External DoE interface, as seen from the requester.
+ * Should match PCIe 6.1 section 7.9.24
+ */
+REG32(MBX_DOE_CONTROL, 0x08u)
+    SHARED_FIELD(MBX_CONTROL_ABORT, 0u, 1u)
+    SHARED_FIELD(MBX_CONTROL_INT_EN, 1u, 1u)
+    FIELD(MBX_DOE_CONTROL, GO, 31u, 1u)
+REG32(MBX_DOE_STATUS, 0x0cu)
+    SHARED_FIELD(MBX_STATUS_BUSY, 0u, 1u)
+    SHARED_FIELD(MBX_STATUS_INT_STATUS, 1u, 1u)
+    SHARED_FIELD(MBX_STATUS_ERROR, 2u, 1u)
+    SHARED_FIELD(MBX_STATUS_READY, 31u, 1u)
+REG32(MBX_DOE_WRITE_DATA, 0x010u)
+REG32(MBX_DOE_READ_DATA, 0x014u)
+
+/* clang-format on */
+
+/* ------------------------------------------------------------------------ */
+/* Mailbox proxy */
+/* ------------------------------------------------------------------------ */
+
+#define DEV_PROXY_DESC_LEN 16u
+
+typedef struct _DevProxyHeader {
+    uint16_t command;
+    uint16_t length;
+    uint32_t uid;
+} DevProxyHeader;
+
+static_assert(sizeof(DevProxyHeader) == 8u, "Invalid header size");
+
+typedef struct {
+    MemoryRegion *mr; /* memory region to access */
+    /* the following fields are only meaningful for SUS_BUS_DEVICE items */
+    unsigned reg_count; /* count of accessible device registers */
+    uint32_t irq_mask; /* mask of routable IRQs on this device */
+} OtDevProxyCaps;
+
+typedef struct {
+    Object *obj; /* proxied object */
+    OtDevProxyCaps caps; /* object capabilities */
+    const char *prefix; /* prefix name for idenfifying the device */
+    GHashTable *iirq_ht; /* intercepted IRQs, may be NULL */
+    char desc[DEV_PROXY_DESC_LEN]; /* user friendly name, for debug purposes */
+} OtDevProxyItem;
+
+typedef struct {
+    qemu_irq irq_orig; /* original IRQ destination (to QEMU device) */
+    unsigned dev_num; /* device number (in device array) */
+    uint16_t irq_num; /* IRQ number (in proxied device) */
+    uint8_t grp_num; /* IRQ group (in proxied device) */
+    bool assigned; /* Proxy IRQ slot in use */
+} OtDevProxyIrq;
+
+typedef struct {
+    MemoryRegion *mr;
+    BusState *bus;
+} OtDevProxySystem;
+
+struct OtDevProxyWatcherState {
+    DeviceState parent_obj;
+    MemoryRegion mmio;
+
+    QSIMPLEQ_ENTRY(OtDevProxyWatcherState) watcher;
+
+    OtDevProxyState *devproxy;
+    MemoryRegion *root;
+    unsigned wid;
+    unsigned address;
+    unsigned size;
+    unsigned priority;
+    unsigned stop;
+    bool read;
+    bool write;
+};
+
+struct OtDevProxyState {
+    DeviceState parent_obj;
+
+    OtDevProxyItem *items; /* proxied devices */
+    OtDevProxyIrq *proxy_irq_map; /* IRQ interception mapping */
+    OtDevProxySystem *subsys; /*subsystem array */
+    QSIMPLEQ_HEAD(, OtDevProxyWatcherState) watchers;
+    unsigned dev_count; /* count of IRQ in items */
+    unsigned subsys_count; /* count of memory roots */
+    unsigned last_wid;
+
+    Fifo8 rx_fifo; /* input FIFO */
+    DevProxyHeader rx_hdr; /* received proxy header */
+    unsigned requester_uid; /* requester input counter */
+    unsigned initiator_uid; /* initiator output counter */
+    uint32_t *rx_buffer; /* received payload */
+
+    CharFrontend chr; /* communication device */
+    guint watch_tag; /* tracker for comm device change */
+};
+
+struct OtDevProxyClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+typedef void ot_dev_proxy_register_device_fn(GArray *array, Object *obj);
+
+typedef struct {
+    const char *typename;
+    ot_dev_proxy_register_device_fn *reg_dev;
+} OtDevProxyDevice;
+
+enum OtDevProxyErr {
+    /* No error */
+    PE_NO_ERROR,
+    /* Undefined errors */
+    PE_UNKNOWN = 0x1,
+    /* Request errors */
+    PE_INVALID_COMMAND_LENGTH = 0x101,
+    PE_INVALID_COMMAND_CODE,
+    PE_INVALID_REQUEST_ID,
+    PE_INVALID_SPECIFIER_ID,
+    PE_INVALID_DEVICE_ID,
+    PE_INVALID_IRQ,
+    PE_INVALID_REG_ADDRESS,
+    /* State error */
+    PE_DEVICE_IN_ERROR = 0x201,
+    /* Local error */
+    PE_CANNOT_READ_DEVICE = 0x401,
+    PE_CANNOT_WRITE_DEVICE,
+    PE_TRUNCATED_RESPONSE,
+    PE_INCOMPLETE_WRITE,
+    PE_OOM, /* out of resources */
+    /* internal error */
+    PE_UNSUPPORTED_DEVICE = 0x801,
+};
+
+#define PROXY_VER_MAJ 0
+#define PROXY_VER_MIN 15u
+
+#define PROXY_IRQ_INTERCEPT_COUNT 32u
+#define PROXY_IRQ_INTERCEPT_NAME  "irq-intercept"
+
+#define PROXY_DISABLED_ROLE 0xfu
+
+#define PROXY_COMMAND(_a_, _b_) ((((uint16_t)(_a_)) << 8u) | ((uint8_t)(_b_)))
+#define PROXY_UID(_u_)          ((_u_) & ~(1u << 31u))
+#define PROXY_MAKE_UID(_uid_, _req_) \
+    (((_uid_) & ~(1u << 31u)) | (((uint32_t)(bool)(_req_)) << 31u))
+
+#define LOG_OP_SHIFT 30u
+#define LOG_MASK     ((1u << LOG_OP_SHIFT) - 1u)
+
+enum { LOG_MASK_READ, LOG_MASK_ADD, LOG_MASK_REMOVE, LOG_MASK_DIRECT };
+
+static void ot_dev_proxy_reg_mr(GArray *array, Object *obj);
+static void ot_dev_proxy_reg_mbx(GArray *array, Object *obj);
+static void ot_dev_proxy_reg_soc_proxy(GArray *array, Object *obj);
+static void ot_dev_proxy_reg_sram_ctrl(GArray *array, Object *obj);
+
+static OtDevProxyDevice SUPPORTED_DEVICES[] = {
+    {
+        .typename = TYPE_OT_MBX,
+        .reg_dev = &ot_dev_proxy_reg_mbx,
+    },
+    {
+        .typename = TYPE_OT_SOC_PROXY,
+        .reg_dev = &ot_dev_proxy_reg_soc_proxy,
+    },
+    {
+        .typename = TYPE_OT_SRAM_CTRL,
+        .reg_dev = &ot_dev_proxy_reg_sram_ctrl,
+    },
+};
+
+static void ot_dev_proxy_send(OtDevProxyState *s, unsigned uid, int dir,
+                              uint16_t command, const void *payload,
+                              size_t length)
+{
+    DevProxyHeader tx_hdr = { command, length, PROXY_MAKE_UID(uid, dir) };
+    const uint8_t *buf = (const uint8_t *)&tx_hdr;
+    int len = (int)sizeof(tx_hdr);
+    int ret;
+
+    /* "synchronous" write */
+    while (len > 0) {
+        if (!qemu_chr_fe_backend_connected(&s->chr)) {
+            return;
+        }
+        ret = qemu_chr_fe_write(&s->chr, buf, len);
+        if (ret < 0) {
+            trace_ot_dev_proxy_fe_error(ret);
+            return;
+        }
+        len -= ret;
+        buf += ret;
+    }
+
+    len = (int)length;
+    buf = (const uint8_t *)payload;
+    while (len > 0) {
+        if (!qemu_chr_fe_backend_connected(&s->chr)) {
+            return;
+        }
+        ret = qemu_chr_fe_write(&s->chr, buf, len);
+        if (ret < 0) {
+            trace_ot_dev_proxy_fe_error(ret);
+            return;
+        }
+        len -= ret;
+        buf += ret;
+    }
+}
+
+static void ot_dev_proxy_reply_payload(OtDevProxyState *s, uint16_t command,
+                                       const void *payload, size_t length)
+{
+    ot_dev_proxy_send(s, s->requester_uid, 0, command, payload, length);
+}
+
+static void ot_dev_proxy_signal(OtDevProxyState *s, uint16_t command,
+                                const OtDevProxyIrq *proxy_irq, int value)
+{
+    uint32_t buffer[3u] = { ((uint32_t)(proxy_irq->dev_num & 0xfffu) << 16u),
+                            ((uint32_t)(proxy_irq->irq_num)) |
+                                ((uint32_t)(proxy_irq->grp_num) << 16u),
+                            (uint32_t)value };
+
+    ot_dev_proxy_send(s, s->initiator_uid, 1, command, buffer, sizeof(buffer));
+
+    /* as a signal, do not expect a peer response */
+    s->initiator_uid++;
+}
+
+static void ot_dev_proxy_reply_error(OtDevProxyState *s, uint32_t error,
+                                     const char *msg)
+{
+    if (msg) {
+        size_t len = strlen(msg);
+        size_t size = sizeof(uint32_t) + ROUND_UP(len, sizeof(uint32_t));
+        uint32_t *buf = g_new0(uint32_t, size / sizeof(uint32_t));
+        buf[0] = error;
+        memcpy((char *)&buf[1], msg, len);
+        ot_dev_proxy_reply_payload(s, PROXY_COMMAND('x', 'x'), buf, size);
+        g_free(buf);
+    } else {
+        ot_dev_proxy_reply_payload(s, PROXY_COMMAND('x', 'x'), &error,
+                                   sizeof(error));
+    }
+}
+
+static void ot_dev_proxy_handshake(OtDevProxyState *s)
+{
+    /* initial client connection, reset uid trackers */
+    s->requester_uid = PROXY_UID(s->rx_hdr.uid);
+    s->initiator_uid = 0;
+    uint32_t payload = (PROXY_VER_MIN << 0u) | (PROXY_VER_MAJ << 16u);
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('h', 's'), &payload,
+                               sizeof(payload));
+}
+
+static void ot_dev_proxy_logmask(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    uint32_t prevlogmask = ((uint32_t)qemu_loglevel) & LOG_MASK;
+    uint32_t logmask = s->rx_buffer[0] & LOG_MASK;
+    unsigned op = s->rx_buffer[0] >> 30u;
+    switch (op) {
+    case LOG_MASK_ADD:
+        qemu_loglevel = (int)(prevlogmask | logmask);
+        break;
+    case LOG_MASK_REMOVE:
+        qemu_loglevel = (int)(prevlogmask & ~logmask);
+        break;
+    case LOG_MASK_DIRECT:
+        qemu_loglevel = (int)logmask;
+        break;
+    case LOG_MASK_READ:
+    default:
+        break;
+    }
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('h', 'l'), &prevlogmask,
+                               sizeof(prevlogmask));
+}
+
+static void ot_dev_proxy_enumerate_devices(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != 0) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    struct entry {
+        uint32_t header;
+        uint32_t base;
+        uint32_t count;
+        char desc[DEV_PROXY_DESC_LEN];
+    };
+    g_assert(sizeof(struct entry) == 7u * sizeof(uint32_t));
+
+    struct entry *entries = g_new0(struct entry, s->dev_count);
+    unsigned count = 0;
+    unsigned mrcount = 0;
+    char desc[32u];
+    for (unsigned ix = 0; ix < s->dev_count; ix++) {
+        OtDevProxyItem *item = &s->items[ix];
+        const OtDevProxyCaps *caps = &item->caps;
+        struct entry *entry = &entries[count];
+        memset(entry, 0, sizeof(*entry));
+        memset(desc, 0, sizeof(desc));
+        const char *oid = NULL;
+        for (unsigned dix = 0; dix < ARRAY_SIZE(SUPPORTED_DEVICES); dix++) {
+            if (object_dynamic_cast(item->obj,
+                                    SUPPORTED_DEVICES[dix].typename)) {
+                oid = object_property_get_str(item->obj, OT_COMMON_DEV_ID,
+                                              &error_fatal);
+                (void)snprintf(desc, sizeof(desc), "%s%s", item->prefix, oid);
+                break;
+            }
+        }
+        if (!oid) {
+            if (object_dynamic_cast(item->obj, TYPE_MEMORY_REGION)) {
+                char name[16u];
+                unsigned pos = 0;
+                const char *src = item->caps.mr->name;
+                memset(name, 0, sizeof(name));
+                while (src && *src) {
+                    switch (*src) {
+                    case '-':
+                    case '.':
+                    case '_':
+                    case ' ':
+                        break;
+                    default:
+                        if (pos < sizeof(name)) {
+                            name[pos++] = *src;
+                        }
+                        break;
+                    }
+                    src++;
+                }
+                (void)snprintf(desc, sizeof(desc), "%s%s%u", item->prefix, name,
+                               mrcount);
+                mrcount++;
+            }
+            if (!desc[0]) {
+                warn_report("%s: ignoring discovered device: %s\n", __func__,
+                            object_get_typename(item->obj));
+                continue;
+            }
+        }
+        /*
+         * desc field does not need to be zero-ended, but its content should not
+         * exceed the field storage, otherwise truncature may occur with
+         * multiple instances ending up with the same descriptor.
+         */
+        if (desc[sizeof(entry->desc)]) {
+            error_setg(&error_fatal, "Device %s cannot be described: %s\n",
+                       object_get_typename(item->obj), desc);
+        }
+        memcpy(entry->desc, desc, sizeof(entry->desc));
+        strncpy(item->desc, desc, sizeof(entry->desc));
+        item->desc[sizeof(entry->desc) - 1] = '\0';
+        entry->header = ix << 16u;
+        entry->base = (uint32_t)caps->mr->addr;
+        entry->count = caps->reg_count;
+        count++;
+        if (ix >= 0xfffu) {
+            break;
+        }
+    }
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('e', 'd'), entries,
+                               count * sizeof(struct entry));
+    g_free(entries);
+}
+
+static void ot_dev_proxy_enumerate_memory_spaces(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != 0) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    struct entry {
+        uint32_t header;
+        uint32_t address;
+        uint32_t size;
+        char desc[32u];
+    };
+    g_assert(sizeof(struct entry) == 11u * sizeof(uint32_t));
+
+    struct entry *entries = g_new0(struct entry, s->subsys_count);
+    unsigned count = 0;
+    for (unsigned ix = 0; ix < s->subsys_count; ix++) {
+        const OtDevProxySystem *subsys = &s->subsys[ix];
+        struct entry *entry = &entries[count];
+        entry->header = ix << 24u;
+        entry->address = subsys->mr->addr;
+        uint64_t size = memory_region_size(subsys->mr);
+        entry->size = (uint32_t)MIN(size, UINT32_MAX);
+        const char *name = memory_region_name(subsys->mr);
+        size_t namelen = strlen(name);
+        if (namelen > sizeof(entry->desc)) {
+            memcpy(entry->desc, &name[namelen - sizeof(entry->desc)],
+                   sizeof(entry->desc));
+        } else {
+            memcpy(entry->desc, name, namelen);
+        }
+        count++;
+        if (ix >= 0xffu) {
+            /* only 256 root regions are supported for now */
+            break;
+        }
+    }
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('e', 's'), entries,
+                               count * sizeof(struct entry));
+    g_free(entries);
+}
+
+static void ot_dev_proxy_enumerate_interrupts(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != 1u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    unsigned devix = (s->rx_buffer[0] >> 16u) & 0xfffu;
+
+    if (devix >= s->dev_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    OtDevProxyItem *item = &s->items[devix];
+
+    if (!object_dynamic_cast(item->obj, TYPE_DEVICE)) {
+        ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+        return;
+    }
+
+    DeviceState *dev = DEVICE(item->obj);
+
+    unsigned group_count = 0;
+    NamedGPIOList *ngl;
+    QLIST_FOREACH(ngl, &dev->gpios, node) {
+        group_count++;
+    }
+
+    struct irq_id {
+        uint16_t count;
+        uint8_t group;
+        uint8_t dir;
+        char name[32u];
+    };
+    static_assert(sizeof(struct irq_id) == 9u * sizeof(uint32_t),
+                  "invalid struct irq_id, need packing");
+
+    struct irq_id *entries;
+
+    if (group_count) {
+        entries = g_new0(struct irq_id, group_count);
+        struct irq_id *irq_id = entries;
+        unsigned group = 0;
+        QLIST_FOREACH(ngl, &dev->gpios, node) {
+            if (group > UINT8_MAX) {
+                /* cannot handle more groups (unlikely) */
+                break;
+            }
+            if (ngl->num_out) {
+                irq_id->count = ngl->num_out;
+                irq_id->dir = (1u << 7u);
+            } else {
+                irq_id->count = ngl->num_in;
+                irq_id->dir = (0u << 7u);
+            }
+            /* input sysbus IRQs are typically unnamed */
+            strncpy(irq_id->name, ngl->name ?: "", sizeof(irq_id->name) - 1u);
+            irq_id->group = group++;
+            irq_id++;
+        }
+    } else {
+        entries = NULL;
+    }
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('i', 'e'), entries,
+                               group_count * sizeof(struct irq_id));
+    g_free(entries);
+}
+
+static void ot_dev_proxy_read_reg(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    hwaddr reg = (hwaddr)(s->rx_buffer[0] & 0xffffu);
+    unsigned role = s->rx_buffer[0] >> 28u;
+    unsigned devix = (s->rx_buffer[0] >> 16u) & 0xfffu;
+
+    if (devix >= s->dev_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    OtDevProxyItem *item = &s->items[devix];
+    OtDevProxyCaps *caps = &item->caps;
+    if (reg >= caps->reg_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_REG_ADDRESS, NULL);
+        return;
+    }
+
+    MemoryRegion *mr = caps->mr;
+    if (!mr) {
+        ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+        return;
+    }
+
+    trace_ot_dev_proxy_read_reg(item->desc, reg);
+
+    const MemoryRegionOps *ops = mr->ops;
+    if (role != PROXY_DISABLED_ROLE ? !ops->read_with_attrs : !ops->read) {
+        ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, "no accessor");
+        return;
+    }
+
+    uint64_t tmp;
+
+    if (role != PROXY_DISABLED_ROLE) {
+        MemTxAttrs attrs = MEMTXATTRS_WITH_ROLE(role);
+        MemTxResult res;
+
+        res = ops->read_with_attrs(mr->opaque, reg << 2u, &tmp,
+                                   sizeof(uint32_t), attrs);
+        if (res != MEMTX_OK) {
+            ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, NULL);
+            return;
+        }
+    } else {
+        tmp = ops->read(mr->opaque, reg << 2u, sizeof(uint32_t));
+    }
+
+    uint32_t buf = (uint32_t)tmp;
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('r', 'w'), &buf, sizeof(buf));
+}
+
+static void ot_dev_proxy_write_reg(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != 3u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    hwaddr reg = (hwaddr)(s->rx_buffer[0] & 0xffffu);
+    unsigned role = s->rx_buffer[0] >> 28u;
+    unsigned devix = (s->rx_buffer[0] >> 16u) & 0xfffu;
+    uint32_t value = s->rx_buffer[1u];
+    uint32_t mask = s->rx_buffer[2u];
+
+    if (devix >= s->dev_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    OtDevProxyItem *item = &s->items[devix];
+    OtDevProxyCaps *caps = &item->caps;
+    if (reg >= caps->reg_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_REG_ADDRESS, NULL);
+        return;
+    }
+
+    MemoryRegion *mr = caps->mr;
+    if (!mr) {
+        ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+        return;
+    }
+
+    trace_ot_dev_proxy_write_reg(item->desc, reg, value);
+
+    const MemoryRegionOps *ops = mr->ops;
+    if (role != PROXY_DISABLED_ROLE ? !ops->write_with_attrs : !ops->write) {
+        ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, "no accessor");
+        return;
+    }
+
+    MemTxAttrs attrs = MEMTXATTRS_WITH_ROLE(role);
+    MemTxResult res;
+    uint64_t tmp;
+
+    if (mask != 0xffffffffu) {
+        if (role != PROXY_DISABLED_ROLE ? !ops->read_with_attrs : !ops->read) {
+            ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, "no accessor");
+            return;
+        }
+        if (role != PROXY_DISABLED_ROLE) {
+            res = ops->read_with_attrs(mr->opaque, reg << 2u, &tmp,
+                                       sizeof(uint32_t), attrs);
+            if (res != MEMTX_OK) {
+                ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, NULL);
+                return;
+            }
+        } else {
+            tmp = ops->read(mr->opaque, reg << 2u, sizeof(uint32_t));
+        }
+
+        tmp &= (uint64_t)~mask;
+        tmp |= (uint64_t)(value & mask);
+    } else {
+        tmp = (uint64_t)value;
+    }
+
+    if (role != PROXY_DISABLED_ROLE) {
+        res = ops->write_with_attrs(mr->opaque, reg << 2u, tmp,
+                                    sizeof(uint32_t), attrs);
+        if (res != MEMTX_OK) {
+            ot_dev_proxy_reply_error(s, PE_CANNOT_WRITE_DEVICE, NULL);
+            return;
+        }
+    } else {
+        ops->write(mr->opaque, reg << 2u, tmp, sizeof(uint32_t));
+    }
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('w', 'w'), NULL, 0);
+}
+
+static void ot_dev_proxy_read_buffer(OtDevProxyState *s, bool mbx_mode)
+{
+    if (s->rx_hdr.length != 2u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    hwaddr reg = (hwaddr)(s->rx_buffer[0] & 0xffffu);
+    unsigned role = s->rx_buffer[0] >> 28u;
+    unsigned devix = (s->rx_buffer[0] >> 16u) & 0xfffu;
+    unsigned count = s->rx_buffer[1u];
+
+    if (devix >= s->dev_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    OtDevProxyItem *item = &s->items[devix];
+    OtDevProxyCaps *caps = &item->caps;
+    Object *obj = item->obj;
+    MemTxAttrs attrs = MEMTXATTRS_WITH_ROLE(role);
+    MemoryRegion *mr = NULL;
+    MemTxResult res = MEMTX_OK;
+
+    if (object_dynamic_cast(obj, TYPE_OT_MBX)) {
+        if (mbx_mode && reg != R_MBX_DOE_READ_DATA) {
+            ot_dev_proxy_reply_error(s, PE_INVALID_REG_ADDRESS, NULL);
+            return;
+        }
+        mr = caps->mr;
+    }
+    if (!mr) {
+        ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+        return;
+    }
+
+    trace_ot_dev_proxy_read_buffer(item->desc, mbx_mode, reg, count);
+
+    const MemoryRegionOps *ops = mr->ops;
+    if (role != PROXY_DISABLED_ROLE ? !ops->read_with_attrs : !ops->read) {
+        ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, "no accessor");
+        return;
+    }
+    if (mbx_mode) {
+        if (role != PROXY_DISABLED_ROLE ? !ops->write_with_attrs :
+                                          !ops->write) {
+            ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, "no accessor");
+            return;
+        }
+    }
+
+    uint32_t *buf = g_new0(uint32_t, count);
+    hwaddr addr = reg << 2u;
+    for (unsigned ix = 0; ix < count; ix++) {
+        uint64_t tmp;
+        if (mbx_mode) {
+            /* read DOE status */
+            if (role != PROXY_DISABLED_ROLE) {
+                res = ops->read_with_attrs(mr->opaque, A_MBX_DOE_STATUS, &tmp,
+                                           sizeof(uint32_t), attrs);
+                if (res != MEMTX_OK) {
+                    ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, NULL);
+                    goto end;
+                }
+            } else {
+                tmp = ops->read(mr->opaque, A_MBX_DOE_STATUS, sizeof(uint32_t));
+            }
+            uint32_t status = (uint32_t)tmp;
+            if (status & MBX_STATUS_ERROR_MASK) {
+                ot_dev_proxy_reply_error(s, PE_DEVICE_IN_ERROR, NULL);
+                goto end;
+            }
+            if (!(status & MBX_STATUS_READY_MASK)) {
+                /* update requested count with actual count */
+                count = ix;
+                break;
+            }
+        }
+        /* read value */
+        if (role != PROXY_DISABLED_ROLE) {
+            res = ops->read_with_attrs(mr->opaque, addr, &tmp, sizeof(uint32_t),
+                                       attrs);
+            if (res != MEMTX_OK) {
+                ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, NULL);
+                break;
+            }
+        } else {
+            tmp = ops->read(mr->opaque, addr, sizeof(uint32_t));
+        }
+        buf[ix] = (uint32_t)tmp;
+        if (mbx_mode) {
+            /* mark as read */
+            if (role != PROXY_DISABLED_ROLE) {
+                res = ops->write_with_attrs(mr->opaque, addr, tmp,
+                                            sizeof(uint32_t), attrs);
+                if (res != MEMTX_OK) {
+                    ot_dev_proxy_reply_error(s, PE_CANNOT_WRITE_DEVICE, NULL);
+                    goto end;
+                }
+            } else {
+                ops->write(mr->opaque, addr, tmp, sizeof(uint32_t));
+            }
+        } else {
+            addr += sizeof(uint32_t);
+        }
+    }
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('r', mbx_mode ? 'x' : 's'), buf,
+                               count * sizeof(uint32_t));
+end:
+    g_free(buf);
+}
+
+static void ot_dev_proxy_write_buffer(OtDevProxyState *s, bool mbx_mode)
+{
+    if (s->rx_hdr.length < 2u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    hwaddr reg = (hwaddr)(s->rx_buffer[0] & 0xffffu);
+    unsigned role = s->rx_buffer[0] >> 28u;
+    unsigned devix = (s->rx_buffer[0] >> 16u) & 0xfffu;
+    unsigned count = s->rx_hdr.length / sizeof(uint32_t) - 1u;
+
+    if (devix >= s->dev_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    OtDevProxyItem *item = &s->items[devix];
+    OtDevProxyCaps *caps = &item->caps;
+    Object *obj = item->obj;
+    MemTxAttrs attrs = MEMTXATTRS_WITH_ROLE(role);
+    MemoryRegion *mr = NULL;
+    MemTxResult res = MEMTX_OK;
+
+    if (object_dynamic_cast(obj, TYPE_OT_MBX)) {
+        if (mbx_mode && reg != R_MBX_DOE_WRITE_DATA) {
+            ot_dev_proxy_reply_error(s, PE_INVALID_REG_ADDRESS, NULL);
+            return;
+        }
+        mr = caps->mr;
+    }
+
+    if (!mr) {
+        ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+        return;
+    }
+
+    trace_ot_dev_proxy_write_buffer(item->desc, mbx_mode, reg, count);
+
+    const MemoryRegionOps *ops = mr->ops;
+    if (role != PROXY_DISABLED_ROLE ? !ops->write_with_attrs : !ops->write) {
+        ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, "no accessor");
+        return;
+    }
+    if (mbx_mode) {
+        if (role != PROXY_DISABLED_ROLE ? !ops->read_with_attrs : !ops->read) {
+            ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, "no accessor");
+            return;
+        }
+    }
+
+    uint32_t *buf = &s->rx_buffer[1];
+    hwaddr addr = reg << 2u;
+    uint64_t tmp;
+    for (unsigned ix = 0; ix < count; ix++) {
+        if (mbx_mode) {
+            /* read DOE status */
+            if (role != PROXY_DISABLED_ROLE) {
+                res = ops->read_with_attrs(mr->opaque, A_MBX_DOE_STATUS, &tmp,
+                                           sizeof(uint32_t), attrs);
+                if (res != MEMTX_OK) {
+                    ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, NULL);
+                    return;
+                }
+            } else {
+                tmp = ops->read(mr->opaque, A_MBX_DOE_STATUS, sizeof(uint32_t));
+            }
+            uint32_t status = (uint32_t)tmp;
+            if (status & MBX_STATUS_BUSY_MASK) {
+                count = ix;
+                break;
+            }
+            if (status & MBX_STATUS_ERROR_MASK) {
+                ot_dev_proxy_reply_error(s, PE_DEVICE_IN_ERROR, NULL);
+                return;
+            }
+        }
+        /* write data */
+        tmp = (uint64_t)*buf++;
+
+        if (role != PROXY_DISABLED_ROLE) {
+            res = ops->write_with_attrs(mr->opaque, addr, tmp, sizeof(uint32_t),
+                                        attrs);
+            if (res != MEMTX_OK) {
+                ot_dev_proxy_reply_error(s, PE_CANNOT_WRITE_DEVICE, NULL);
+                return;
+            }
+        } else {
+            ops->write(mr->opaque, addr, tmp, sizeof(uint32_t));
+        }
+    }
+    if (mbx_mode) {
+        /* update GO */
+        if (role != PROXY_DISABLED_ROLE) {
+            res = ops->read_with_attrs(mr->opaque, A_MBX_DOE_CONTROL, &tmp,
+                                       sizeof(uint32_t), attrs);
+
+            if (res != MEMTX_OK) {
+                ot_dev_proxy_reply_error(s, PE_CANNOT_READ_DEVICE, NULL);
+                return;
+            }
+        } else {
+            tmp = ops->read(mr->opaque, A_MBX_DOE_CONTROL, sizeof(uint32_t));
+        }
+        tmp |= (uint64_t)R_MBX_DOE_CONTROL_GO_MASK;
+        if (role != PROXY_DISABLED_ROLE) {
+            res = ops->write_with_attrs(mr->opaque, A_MBX_DOE_CONTROL, tmp,
+                                        sizeof(uint32_t), attrs);
+            if (res != MEMTX_OK) {
+                ot_dev_proxy_reply_error(s, PE_CANNOT_WRITE_DEVICE, NULL);
+                return;
+            }
+        } else {
+            ops->write(mr->opaque, A_MBX_DOE_CONTROL, tmp, sizeof(uint32_t));
+        }
+    }
+
+    uint32_t obuf[1] = { count };
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('w', mbx_mode ? 'x' : 's'),
+                               &obuf, sizeof(obuf));
+}
+
+static void ot_dev_proxy_read_memory(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != 3u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    unsigned devix = (s->rx_buffer[0] >> 16u) & 0xfffu;
+    unsigned offset = s->rx_buffer[1u];
+    unsigned count = s->rx_buffer[2u];
+
+    if (devix >= s->dev_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    OtDevProxyItem *item = &s->items[devix];
+    OtDevProxyCaps *caps = &item->caps;
+    Object *obj = item->obj;
+    unsigned woffset = offset / sizeof(uint32_t);
+    if (woffset > item->caps.reg_count) {
+        count = 0;
+    } else {
+        unsigned maxcount = item->caps.reg_count - woffset;
+        if (count > maxcount) {
+            count = maxcount;
+        }
+    }
+
+    trace_ot_dev_proxy_read_memory(item->desc, offset, count);
+
+    uint32_t *buf = g_new0(uint32_t, count);
+    if (count) {
+        if (object_dynamic_cast(obj, TYPE_OT_SRAM_CTRL)) {
+            MemoryRegion *mr = caps->mr;
+            if (!mr) {
+                ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+                goto end;
+            }
+            uintptr_t base = (uintptr_t)memory_region_get_ram_ptr(mr);
+            base += offset;
+            /* for now, there is no way to control role access */
+            memcpy(buf, (const void *)base, count * sizeof(uint32_t));
+        } else {
+            ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+            goto end;
+        }
+    }
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('r', 'm'), buf,
+                               count * sizeof(uint32_t));
+end:
+    g_free(buf);
+}
+
+static void ot_dev_proxy_write_memory(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length < 3u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    unsigned devix = (s->rx_buffer[0] >> 16u) & 0xfffu;
+    unsigned offset = s->rx_buffer[1];
+    unsigned count = s->rx_hdr.length / sizeof(uint32_t) - 2u;
+    const uint32_t *buffer = &s->rx_buffer[2];
+
+    if (devix >= s->dev_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    OtDevProxyItem *item = &s->items[devix];
+    OtDevProxyCaps *caps = &item->caps;
+    Object *obj = item->obj;
+    unsigned woffset = offset / sizeof(uint32_t);
+    if (woffset > item->caps.reg_count) {
+        count = 0;
+    } else {
+        unsigned maxcount = item->caps.reg_count - woffset;
+        if (count > maxcount) {
+            count = maxcount;
+        }
+    }
+
+    trace_ot_dev_proxy_write_memory(item->desc, offset, count);
+
+    if (object_dynamic_cast(obj, TYPE_OT_SRAM_CTRL)) {
+        MemoryRegion *mr = caps->mr;
+        if (!mr) {
+            ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+            return;
+        }
+        uintptr_t base = (uintptr_t)memory_region_get_ram_ptr(mr);
+        base += offset;
+        /* for now, there is no way to control role access */
+        memcpy((void *)base, buffer, count * sizeof(uint32_t));
+        if (mr->ram_block) {
+            memory_region_set_dirty(mr, (hwaddr)offset * sizeof(uint32_t),
+                                    (hwaddr)count * sizeof(uint32_t));
+        }
+    } else {
+        ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+        return;
+    }
+
+    uint32_t obuf[1] = { count };
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('w', 'm'), &obuf, sizeof(obuf));
+}
+
+static void
+ot_dev_proxy_route_interrupt(OtDevProxyState *s, OtDevProxyItem *item,
+                             const char *group, unsigned grp_n, unsigned irq_n)
+{
+    const char *dev_name = object_get_typename(item->obj);
+    char *dev_id = object_property_get_str(item->obj, OT_COMMON_DEV_ID, NULL);
+    char *irq_name = g_strdup_printf("%s[%u]", group, irq_n);
+
+    OtDevProxyIrq *proxy_irq =
+        item->iirq_ht ? g_hash_table_lookup(item->iirq_ht, irq_name) : NULL;
+    /* do not reroute IRQ if it is already routed */
+    if (proxy_irq) {
+        g_free(irq_name);
+        g_free(dev_id);
+        return;
+    }
+
+    unsigned six;
+    for (six = 0; six < PROXY_IRQ_INTERCEPT_COUNT; six++) {
+        if (!s->proxy_irq_map[six].assigned) {
+            proxy_irq = &s->proxy_irq_map[six];
+            break;
+        }
+    }
+    /* caller should have verified that there are enough free slots */
+    g_assert(proxy_irq);
+
+    DeviceState *dev = DEVICE(item->obj);
+
+    qemu_irq icpt_irq;
+    icpt_irq =
+        qdev_get_gpio_in_named(DEVICE(s), PROXY_IRQ_INTERCEPT_NAME, (int)six);
+    proxy_irq->assigned = true;
+    proxy_irq->irq_orig =
+        qdev_intercept_gpio_out(dev, icpt_irq, group, (int)irq_n);
+    proxy_irq->dev_num = (unsigned)(uintptr_t)(item - s->items);
+    proxy_irq->grp_num = grp_n;
+    proxy_irq->irq_num = irq_n;
+    trace_ot_dev_proxy_intercept_irq(dev_name, dev_id ?: "?", irq_name, true);
+    if (!item->iirq_ht) {
+        /*
+         * delete key (g_char strings), but never delete value that are
+         * persisent, reassigned items
+         */
+        item->iirq_ht =
+            g_hash_table_new_full(g_str_hash, g_str_equal, g_free, NULL);
+    }
+    char *ht_key = g_strdup(irq_name);
+    g_hash_table_insert(item->iirq_ht, ht_key, proxy_irq);
+
+    g_free(irq_name);
+    g_free(dev_id);
+}
+
+static void ot_dev_proxy_restore_interrupt(OtDevProxyItem *item,
+                                           const char *group, unsigned irq_n)
+{
+    const char *dev_name = object_get_typename(item->obj);
+    char *dev_id = object_property_get_str(item->obj, OT_COMMON_DEV_ID, NULL);
+    char *irq_name = g_strdup_printf("%s[%u]", group, irq_n);
+
+    if (!item->iirq_ht) {
+        warn_report("Cannot restore interrupt, none intercepted: %s %s %s",
+                    dev_name, dev_id ?: "?", irq_name);
+        g_free(irq_name);
+        g_free(dev_id);
+        return;
+    }
+
+    OtDevProxyIrq *proxy_irq = g_hash_table_lookup(item->iirq_ht, irq_name);
+    if (proxy_irq) {
+        DeviceState *dev = DEVICE(item->obj);
+
+        /* irq_orig == NULL is a valid use case */
+        qdev_intercept_gpio_out(dev, proxy_irq->irq_orig, group, (int)irq_n);
+        /* hash table takes care of deleting the key */
+        g_hash_table_remove(item->iirq_ht, irq_name);
+        memset(proxy_irq, 0, sizeof(*proxy_irq)); /* mark as free_slot */
+        trace_ot_dev_proxy_intercept_irq(dev_name, dev_id ?: "?", irq_name,
+                                         false);
+    } else {
+        warn_report("Cannot restore interrupt, not intercepted: %s %s %s",
+                    dev_name, dev_id ?: "?", irq_name);
+    }
+
+    g_free(irq_name);
+    g_free(dev_id);
+}
+
+static void ot_dev_proxy_intercept_interrupts(OtDevProxyState *s, bool enable)
+{
+    if (s->rx_hdr.length < 2u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    unsigned devix = (s->rx_buffer[0] >> 16u) & 0xfffu;
+
+    if (devix >= s->dev_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    OtDevProxyItem *item = &s->items[devix];
+    if (!object_dynamic_cast(item->obj, TYPE_DEVICE)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    unsigned group = s->rx_buffer[0] & 0xffu;
+
+    /* check that the group identifier is actually valid for the device */
+    DeviceState *dev = DEVICE(item->obj);
+    NamedGPIOList *ngl = NULL;
+    NamedGPIOList *tngl;
+    unsigned grp = 0;
+    QLIST_FOREACH(tngl, &dev->gpios, node) {
+        if (!tngl->name) {
+            /* anonymous IRQs are ignored, see enumerate_interrupts */
+            continue;
+        }
+        if (grp++ < group) {
+            continue;
+        }
+        ngl = tngl;
+        break;
+    }
+
+    if (!ngl) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_IRQ, NULL);
+        return;
+    }
+
+    /* check that all selected interrupts exits for the selected group */
+    unsigned mask_count;
+    mask_count = (s->rx_hdr.length - sizeof(uint32_t)) / sizeof(uint32_t);
+    unsigned max_irq = 0;
+    unsigned irq_count = 0;
+    uint32_t *irqbms = &s->rx_buffer[1u];
+    for (unsigned ix = 0; ix < mask_count; ix++) {
+        uint32_t bm = irqbms[ix];
+        if (bm) {
+            unsigned hi = ctz32(bm);
+            max_irq = ix * 32u + hi;
+            while (bm) {
+                irq_count += 1;
+                bm &= ~(1u << ctz32(bm));
+            }
+        }
+    }
+
+    /*
+     * count how many IRQ can be intercepted and tracked. Already intercepted
+     * IRQs may be counted twice, remote peer should be more careful.
+     */
+    unsigned free_slot = 0;
+    for (unsigned ix = 0; ix < PROXY_IRQ_INTERCEPT_COUNT; ix++) {
+        if (!s->proxy_irq_map[ix].assigned) {
+            free_slot += 1;
+        }
+    }
+    if (irq_count > free_slot) {
+        warn_report("IRQ interception slots exhausted %u for %u free",
+                    irq_count, free_slot);
+        ot_dev_proxy_reply_error(s, PE_OOM, NULL);
+        return;
+    }
+
+    char *irq_name;
+    irq_name = g_strdup_printf("%s[%u]", ngl->name, max_irq);
+    ObjectProperty *prop = object_property_find(item->obj, irq_name);
+    g_free(irq_name);
+    irq_name = NULL;
+
+    if (!prop) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_IRQ, NULL);
+        return;
+    }
+
+    /* reroute all marked IRQs */
+    for (unsigned ix = 0; ix < mask_count; ix++) {
+        while (irqbms[ix]) {
+            unsigned irq_n = ctz32(irqbms[ix]);
+            irqbms[ix] &= ~(1u << irq_n);
+            if (enable) {
+                ot_dev_proxy_route_interrupt(s, item, ngl->name, group, irq_n);
+            } else {
+                ot_dev_proxy_restore_interrupt(item, ngl->name, irq_n);
+            }
+        }
+    }
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('i', enable ? 'i' : 'r'), NULL,
+                               0);
+}
+
+static void ot_dev_proxy_signal_interrupt(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != 3u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    unsigned devix = (s->rx_buffer[0] >> 16u) & 0xfffu;
+    unsigned gid = s->rx_buffer[0u] & 0xffffu;
+
+    if (devix >= s->dev_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, NULL);
+        return;
+    }
+
+    OtDevProxyItem *item = &s->items[devix];
+
+    if (!object_dynamic_cast(item->obj, TYPE_DEVICE)) {
+        ot_dev_proxy_reply_error(s, PE_UNSUPPORTED_DEVICE, NULL);
+        return;
+    }
+
+    DeviceState *dev = DEVICE(item->obj);
+
+    unsigned irq_num = s->rx_buffer[1u] & 0xffffu;
+    int irq_level = (int)s->rx_buffer[2u];
+
+    NamedGPIOList *gl = NULL;
+    NamedGPIOList *ngl;
+    QLIST_FOREACH(ngl, &dev->gpios, node) {
+        if (!gid) {
+            gl = ngl;
+            break;
+        }
+        gid--;
+    }
+
+    if (!gl) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_SPECIFIER_ID, "no such group");
+        return;
+    }
+
+    if (irq_num >= gl->num_in) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_IRQ, "no such irq");
+        return;
+    }
+
+    const char *dev_name = object_get_typename(item->obj);
+    Error *errp = NULL;
+    char *dev_id = object_property_get_str(item->obj, OT_COMMON_DEV_ID, &errp);
+    if (errp) {
+        error_free(errp);
+    }
+
+    trace_ot_dev_proxy_signal_irq(dev_name, dev_id ?: "?", irq_num, irq_level);
+
+    qemu_irq irq = gl->in[irq_num];
+    qemu_set_irq(irq, irq_level);
+
+    g_free(dev_id);
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('i', 's'), NULL, 0);
+}
+
+static void ot_dev_proxy_intercept_mmio(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != 3u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    unsigned mspc = s->rx_buffer[0] >> 24u;
+    if (mspc >= s->subsys_count) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, "Invalid MSpc");
+        return;
+    }
+
+    MemoryRegion *mr = s->subsys[mspc].mr;
+    g_assert(mr->addr == 0);
+
+    uint64_t lmrsize = memory_region_size(mr);
+    uint64_t mrsize = MAX(lmrsize, UINT32_MAX);
+
+    uint32_t address = s->rx_buffer[1];
+    uint32_t size = s->rx_buffer[2];
+
+    if (((uint64_t)address + (uint64_t)size) > mrsize) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_REG_ADDRESS,
+                                 "Invalid addr/size");
+        return;
+    }
+
+    bool read = (bool)(s->rx_buffer[0] & 0b01);
+    bool write = (bool)(s->rx_buffer[0] & 0b10);
+    if (!(read || write)) {
+        /* nothing to intercept */
+        ot_dev_proxy_reply_error(s, PE_INVALID_SPECIFIER_ID,
+                                 "Neither read nor write");
+        return;
+    }
+
+    OtDevProxyWatcherState *watcher;
+    watcher = (OtDevProxyWatcherState *)qdev_new(TYPE_OT_DEV_PROXY_WATCHER);
+
+    unsigned prio = (s->rx_buffer[0] >> 2u) & 0x3f;
+    unsigned stop = (s->rx_buffer[0] >> 8u) & 0x7f;
+    if (!stop) {
+        stop = UINT32_MAX;
+    }
+
+    object_property_set_link(OBJECT(watcher), "devproxy", OBJECT(s),
+                             &error_fatal);
+    object_property_set_link(OBJECT(watcher), "root", OBJECT(mr), &error_fatal);
+    object_property_set_uint(OBJECT(watcher), "wid", s->last_wid, &error_fatal);
+    object_property_set_uint(OBJECT(watcher), "address", address, &error_fatal);
+    object_property_set_uint(OBJECT(watcher), "size", size, &error_fatal);
+    object_property_set_uint(OBJECT(watcher), "priority", prio, &error_fatal);
+    object_property_set_uint(OBJECT(watcher), "stop", stop, &error_fatal);
+    object_property_set_bool(OBJECT(watcher), "read", read, &error_fatal);
+    object_property_set_bool(OBJECT(watcher), "write", write, &error_fatal);
+
+    Error *err = NULL;
+    char *name =
+        g_strdup_printf("%s.%u", TYPE_OT_DEV_PROXY_WATCHER, s->last_wid);
+    object_property_add_child(OBJECT(s), name, OBJECT(watcher));
+
+    qdev_realize_and_unref(DEVICE(watcher), s->subsys[mspc].bus, &err);
+    g_free(name);
+    if (err) {
+        const char *msg = error_get_pretty(err);
+        ot_dev_proxy_reply_error(s, PE_UNKNOWN, msg);
+        error_free(err);
+        return;
+    }
+
+    QSIMPLEQ_INSERT_TAIL(&s->watchers, watcher, watcher);
+
+    uint32_t obuf[1] = { s->last_wid << 16u };
+
+    s->last_wid += 1u;
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('m', 'i'), &obuf, sizeof(obuf));
+}
+
+static void ot_dev_proxy_release_mmio(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != 3u * sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    unsigned wid = (s->rx_buffer[0] >> 16u) & 0xfffu;
+
+    OtDevProxyWatcherState *watcher = NULL;
+    OtDevProxyWatcherState *node;
+    QSIMPLEQ_FOREACH(node, &s->watchers, watcher) {
+        if (node->wid == wid) {
+            watcher = node;
+            break;
+        }
+    }
+    if (!watcher) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_DEVICE_ID, "unkwown watcher");
+        return;
+    }
+
+    qdev_unrealize(DEVICE(watcher));
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('m', 'r'), NULL, 0);
+}
+
+
+static void ot_dev_proxy_cont(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != 0) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    Error *err = NULL;
+    qmp_cont(&err);
+    if (err) {
+        const char *msg = error_get_pretty(err);
+        ot_dev_proxy_reply_error(s, PE_UNKNOWN, msg);
+        error_free(err);
+        return;
+    }
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('c', 'x'), NULL, 0);
+}
+
+static void ot_dev_proxy_quit(OtDevProxyState *s)
+{
+    if (s->rx_hdr.length != sizeof(uint32_t)) {
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_LENGTH, NULL);
+        return;
+    }
+
+    int code = (int)s->rx_buffer[0];
+
+    ot_dev_proxy_reply_payload(s, PROXY_COMMAND('q', 't'), NULL, 0);
+    usleep(200000);
+
+    qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_GUEST_SHUTDOWN, code);
+}
+
+static void ot_dev_proxy_intercepted_irq(void *opaque, int irq, int level)
+{
+    OtDevProxyState *s = opaque;
+    g_assert(irq < PROXY_IRQ_INTERCEPT_COUNT);
+
+    OtDevProxyIrq *proxy_irq = &s->proxy_irq_map[irq];
+    if (!proxy_irq->assigned) {
+        trace_ot_dev_proxy_unassigned_irq(irq);
+        return;
+    }
+    g_assert(proxy_irq->dev_num < s->dev_count);
+
+    OtDevProxyItem *item = &s->items[proxy_irq->dev_num];
+
+    const char *dev_name = object_get_typename(item->obj);
+    Error *errp = NULL;
+    char *dev_id = object_property_get_str(item->obj, OT_COMMON_DEV_ID, &errp);
+    if (errp) {
+        error_free(errp);
+    }
+
+    trace_ot_dev_proxy_route_irq(dev_name, dev_id, proxy_irq->irq_num, level);
+
+    ot_dev_proxy_signal(s, PROXY_COMMAND('^', 'W'), proxy_irq, level);
+
+    g_free(dev_id);
+}
+
+static void ot_dev_proxy_notify_mmio_access(
+    OtDevProxyState *s, unsigned wid, bool write, unsigned role,
+    unsigned address, unsigned size, uint32_t val32)
+{
+    g_assert(wid < s->last_wid);
+
+    uint32_t buffer[3] = { 0, address, val32 };
+
+    buffer[0] |= (uint32_t)(write << 1u);
+    buffer[0] |= (uint32_t)(size << 4u);
+    buffer[0] |= (uint32_t)(wid << 16u);
+    buffer[0] |= (uint32_t)(role << 28u);
+
+    ot_dev_proxy_send(s, s->initiator_uid, 1, PROXY_COMMAND('^', 'R'), buffer,
+                      sizeof(buffer));
+
+    /* as a signal, do not expect a peer response */
+    s->initiator_uid++;
+}
+
+static void ot_dev_proxy_dispatch_request(OtDevProxyState *s)
+{
+    trace_ot_dev_proxy_dispatch_request((char)(s->rx_hdr.command >> 8u),
+                                        (char)(s->rx_hdr.command & 0xffu));
+
+    switch (s->rx_hdr.command) {
+    case PROXY_COMMAND('H', 'S'):
+        ot_dev_proxy_handshake(s);
+        break;
+    case PROXY_COMMAND('H', 'L'):
+        ot_dev_proxy_logmask(s);
+        break;
+    case PROXY_COMMAND('E', 'D'):
+        ot_dev_proxy_enumerate_devices(s);
+        break;
+    case PROXY_COMMAND('E', 'S'):
+        ot_dev_proxy_enumerate_memory_spaces(s);
+        break;
+    case PROXY_COMMAND('R', 'W'):
+        ot_dev_proxy_read_reg(s);
+        break;
+    case PROXY_COMMAND('W', 'W'):
+        ot_dev_proxy_write_reg(s);
+        break;
+    case PROXY_COMMAND('R', 'S'):
+        ot_dev_proxy_read_buffer(s, false);
+        break;
+    case PROXY_COMMAND('W', 'S'):
+        ot_dev_proxy_write_buffer(s, false);
+        break;
+    case PROXY_COMMAND('R', 'X'):
+        ot_dev_proxy_read_buffer(s, true);
+        break;
+    case PROXY_COMMAND('W', 'X'):
+        ot_dev_proxy_write_buffer(s, true);
+        break;
+    case PROXY_COMMAND('R', 'M'):
+        ot_dev_proxy_read_memory(s);
+        break;
+    case PROXY_COMMAND('W', 'M'):
+        ot_dev_proxy_write_memory(s);
+        break;
+    case PROXY_COMMAND('I', 'I'):
+        ot_dev_proxy_intercept_interrupts(s, true);
+        break;
+    case PROXY_COMMAND('I', 'R'):
+        ot_dev_proxy_intercept_interrupts(s, false);
+        break;
+    case PROXY_COMMAND('I', 'S'):
+        ot_dev_proxy_signal_interrupt(s);
+        break;
+    case PROXY_COMMAND('I', 'E'):
+        ot_dev_proxy_enumerate_interrupts(s);
+        break;
+    case PROXY_COMMAND('M', 'I'):
+        ot_dev_proxy_intercept_mmio(s);
+        break;
+    case PROXY_COMMAND('M', 'R'):
+        ot_dev_proxy_release_mmio(s);
+        break;
+    case PROXY_COMMAND('C', 'X'):
+        ot_dev_proxy_cont(s);
+        break;
+    case PROXY_COMMAND('Q', 'T'):
+        ot_dev_proxy_quit(s);
+        break;
+    default:
+        ot_dev_proxy_reply_error(s, PE_INVALID_COMMAND_CODE, NULL);
+        break;
+    }
+}
+
+static void ot_dev_proxy_dispatch_response(OtDevProxyState *s) {}
+
+static int ot_dev_proxy_can_receive(void *opaque)
+{
+    OtDevProxyState *s = opaque;
+
+    return (int)fifo8_num_free(&s->rx_fifo);
+}
+
+static void ot_dev_proxy_receive(void *opaque, const uint8_t *buf, int size)
+{
+    OtDevProxyState *s = opaque;
+
+    if (fifo8_num_free(&s->rx_fifo) < size) {
+        error_report("%s: Unexpected chardev receive\n", __func__);
+        return;
+    }
+
+    for (unsigned ix = 0; ix < size; ix++) {
+        fifo8_push(&s->rx_fifo, buf[ix]);
+    }
+
+    uint32_t length = fifo8_num_used(&s->rx_fifo);
+
+    if (!s->rx_hdr.length) {
+        /* header has not been popped out yet */
+        if (length < sizeof(DevProxyHeader)) {
+            /* no full header in input FIFO */
+            return;
+        }
+        uint8_t *hdr = (uint8_t *)&s->rx_hdr;
+        for (unsigned ix = 0; ix < sizeof(DevProxyHeader); ix++) {
+            *hdr++ = fifo8_pop(&s->rx_fifo);
+        }
+        length -= sizeof(DevProxyHeader);
+    }
+
+    if (length < (uint32_t)s->rx_hdr.length) {
+        /* no full command in input FIFO */
+        return;
+    }
+
+    uint8_t *rxbuf = (uint8_t *)s->rx_buffer;
+    for (unsigned ix = 0; ix < (unsigned)s->rx_hdr.length; ix++) {
+        *rxbuf++ = fifo8_pop(&s->rx_fifo);
+    }
+
+    bool resp = (bool)(s->rx_hdr.uid >> 31u);
+    unsigned uid = PROXY_UID(s->rx_hdr.uid);
+    if (!resp) {
+        /* request */
+        if ((uid != s->requester_uid + 1u) &&
+            (s->rx_hdr.command != PROXY_COMMAND('H', 'S'))) {
+            trace_ot_dev_proxy_uid_error("request", s->requester_uid, uid);
+            ot_dev_proxy_reply_error(s, PE_INVALID_REQUEST_ID, NULL);
+        } else {
+            s->requester_uid++;
+            ot_dev_proxy_dispatch_request(s);
+        }
+    } else {
+        /* response */
+        if (uid != s->initiator_uid) {
+            trace_ot_dev_proxy_uid_error("response", s->requester_uid, uid);
+        } else {
+            ot_dev_proxy_dispatch_response(s);
+        }
+    }
+
+    memset(&s->rx_hdr, 0, sizeof(s->rx_hdr));
+}
+
+static gboolean ot_dev_proxy_watch_cb(void *do_not_use, GIOCondition cond,
+                                      void *opaque)
+{
+    OtDevProxyState *s = opaque;
+    (void)do_not_use;
+    (void)cond;
+
+    s->watch_tag = 0;
+
+    return FALSE;
+}
+
+static int ot_dev_proxy_be_change(void *opaque)
+{
+    OtDevProxyState *s = opaque;
+
+    qemu_chr_fe_set_handlers(&s->chr, &ot_dev_proxy_can_receive,
+                             &ot_dev_proxy_receive, NULL,
+                             &ot_dev_proxy_be_change, s, NULL, true);
+
+    if (s->watch_tag > 0) {
+        g_source_remove(s->watch_tag);
+        /* NOLINTNEXTLINE(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+                                             &ot_dev_proxy_watch_cb, s);
+    }
+
+    return 0;
+}
+
+static int ot_dev_proxy_discover_device(Object *child, void *opaque)
+{
+    GArray *array = opaque;
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(SUPPORTED_DEVICES); ix++) {
+        const OtDevProxyDevice *pd = &SUPPORTED_DEVICES[ix];
+        if (object_dynamic_cast(child, pd->typename)) {
+            (*pd->reg_dev)(array, child);
+            return 0;
+        }
+    }
+    if (object_dynamic_cast(child, TYPE_MEMORY_REGION)) {
+        ot_dev_proxy_reg_mr(array, child);
+        return 0;
+    }
+
+    return 0;
+}
+
+static void ot_dev_proxy_reg_mr(GArray *array, Object *obj)
+{
+    MemoryRegion *mr = MEMORY_REGION(obj);
+    if (mr->ram && obj->parent) {
+        if (!object_dynamic_cast(obj->parent, TYPE_OT_SRAM_CTRL)) {
+            OtDevProxyItem *item = g_new0(OtDevProxyItem, 1);
+            object_ref(obj);
+            item->obj = obj;
+            item->caps.mr = mr;
+            g_assert(item->caps.mr);
+            item->caps.reg_count = memory_region_size(mr) / sizeof(uint32_t);
+            item->prefix = "M/";
+            g_array_append_val(array, item);
+        }
+    }
+}
+
+static void ot_dev_proxy_reg_mbx(GArray *array, Object *obj)
+{
+    SysBusDevice *sysdev = SYS_BUS_DEVICE(obj);
+    g_assert(sysdev->num_mmio == 2u);
+    OtDevProxyItem *item;
+    /* host side */
+    item = g_new0(OtDevProxyItem, 1);
+    object_ref(obj);
+    item->obj = obj;
+    item->caps.mr = sysdev->mmio[0u].memory; /* 0: host */
+    item->caps.reg_count = OT_MBX_HOST_REGS_COUNT;
+    item->caps.irq_mask = UINT32_MAX; /* all IRQs can be routed */
+    item->prefix = "MBH/";
+    g_array_append_val(array, item);
+    /* sys side */
+    item = g_new0(OtDevProxyItem, 1);
+    object_ref(obj);
+    item->obj = obj;
+    item->caps.mr = sysdev->mmio[1u].memory; /* 1: sys */
+    item->caps.reg_count = OT_MBX_SYS_REGS_COUNT;
+    item->caps.irq_mask = 0; /* no IRQ on sys side */
+    item->prefix = "MBS/";
+    g_array_append_val(array, item);
+}
+
+static void ot_dev_proxy_reg_soc_proxy(GArray *array, Object *obj)
+{
+    OtDevProxyItem *item = g_new0(OtDevProxyItem, 1);
+    object_ref(obj);
+    item->obj = obj;
+    SysBusDevice *sysdev = SYS_BUS_DEVICE(obj);
+    g_assert(sysdev->num_mmio == 1u);
+    item->caps.mr = sysdev->mmio[0u].memory;
+    item->caps.reg_count = OT_SOC_PROXY_REGS_COUNT; /* per slot */
+    item->caps.irq_mask = UINT32_MAX; /* all IRQs can be routed */
+    item->prefix = "SOC/";
+    g_array_append_val(array, item);
+}
+
+static void ot_dev_proxy_reg_sram_ctrl(GArray *array, Object *obj)
+{
+    SysBusDevice *sysdev = SYS_BUS_DEVICE(obj);
+    if (sysdev->mmio[0].memory && /* ctrl */
+        sysdev->mmio[1].memory /* mem */) {
+        OtDevProxyItem *item;
+        item = g_new0(OtDevProxyItem, 1);
+        object_ref(obj);
+        item->obj = obj;
+        item->caps.mr = sysdev->mmio[0].memory;
+        item->caps.reg_count =
+            memory_region_size(item->caps.mr) / sizeof(uint32_t);
+        item->prefix = "SRC/"; /* SRAM control */
+        g_array_append_val(array, item);
+        item = g_new0(OtDevProxyItem, 1);
+        object_ref(obj);
+        item->obj = obj;
+        item->caps.mr = sysdev->mmio[1].memory;
+        item->caps.reg_count =
+            memory_region_size(item->caps.mr) / sizeof(uint32_t);
+        item->prefix = "SRM/"; /* SRAM memory */
+        g_array_append_val(array, item);
+    }
+}
+
+static int ot_dev_proxy_discover_memory_root(Object *child, void *opaque)
+{
+    GArray *array = opaque;
+
+    if (object_dynamic_cast(child, TYPE_MEMORY_REGION)) {
+        MemoryRegion *mr = MEMORY_REGION(child);
+        /*
+         * This is a hack. A proper implementation would require to search
+         * the address spaces for memory root regions, unfortunately QEMU APIs
+         * do not expose address_spaces, which are hidden in memory.c
+         */
+        if (mr->container || mr->ram || mr->mapped_via_alias) {
+            /* not a root memory region */
+            return 0;
+        }
+        if (memory_region_size(mr) == 0) {
+            /* empty region, useless */
+            return 0;
+        }
+        if (mr->addr != 0) {
+            /* not supported for a root region */
+            return 0;
+        }
+        const char *name = memory_region_name(mr);
+        if (!g_strcmp0(name, "io")) {
+            /*
+             * io region is a legacy region that is automatically created and
+             * useless (should be ignored)
+             */
+            return 0;
+        }
+        g_array_append_val(array, mr);
+    }
+
+    return 0;
+}
+
+static int ot_dev_proxy_find_bus(Object *child, void *opaque)
+{
+    if (object_dynamic_cast(child, TYPE_BUS)) {
+        BusState **bus = opaque;
+        *bus = BUS(child);
+        return 1;
+    }
+
+    return 0;
+}
+
+static int ot_dev_proxy_map_bus(Object *child, void *opaque)
+{
+    if (!object_dynamic_cast(child, TYPE_CPU)) {
+        return 0;
+    }
+
+    OtDevProxyState *s = opaque;
+    CPUState *cpu = CPU(child);
+    MemoryRegion *mr = cpu->memory;
+
+    for (unsigned ix = 0; ix < s->subsys_count; ix++) {
+        OtDevProxySystem *sys = &s->subsys[ix];
+        if (sys->bus) {
+            continue;
+        }
+        if (sys->mr == mr) {
+            Object *obj = OBJECT(&cpu->parent_obj)->parent;
+            BusState *bus = NULL;
+            while (obj) {
+                object_child_foreach(obj, &ot_dev_proxy_find_bus, &bus);
+                if (bus) {
+                    sys->bus = bus;
+                    break;
+                }
+                obj = obj->parent;
+            }
+        }
+    }
+
+    return 0;
+}
+
+static gint ot_dev_proxy_device_compare(gconstpointer a, gconstpointer b)
+{
+    const OtDevProxyItem **ia = (const OtDevProxyItem **)a;
+    const OtDevProxyItem **ib = (const OtDevProxyItem **)b;
+
+    const MemoryRegion *ma = (*ia)->caps.mr;
+    const MemoryRegion *mb = (*ib)->caps.mr;
+
+    /* increasing host addresses */
+    return (gint)(ma->addr > mb->addr);
+}
+
+static void ot_dev_proxy_discover(OtDevProxyState *s)
+{
+    Object *ms = qdev_get_machine();
+    /* search for 'proxyfi-able' devices */
+    GArray *array;
+
+    array = g_array_new(FALSE, TRUE, sizeof(OtDevProxyItem *));
+    object_child_foreach_recursive(ms, &ot_dev_proxy_discover_device, array);
+
+    g_array_sort(array, &ot_dev_proxy_device_compare);
+
+    s->dev_count = array->len;
+    s->items = g_new0(OtDevProxyItem, s->dev_count);
+
+    for (unsigned ix = 0; ix < array->len; ix++) {
+        OtDevProxyItem *item;
+        item = (OtDevProxyItem *)(g_array_index(array, OtDevProxyItem *, ix));
+        /* deep copy */
+        s->items[ix] = *item;
+        /* allocated from ot_dev_proxy_discover */
+        g_free(item);
+    }
+    g_array_free(array, TRUE);
+
+    s->proxy_irq_map = g_new0(OtDevProxyIrq, PROXY_IRQ_INTERCEPT_COUNT);
+    qdev_init_gpio_in_named(DEVICE(s), &ot_dev_proxy_intercepted_irq,
+                            PROXY_IRQ_INTERCEPT_NAME,
+                            PROXY_IRQ_INTERCEPT_COUNT);
+
+    array = g_array_new(FALSE, TRUE, sizeof(MemoryRegion *));
+    object_child_foreach_recursive(ms, &ot_dev_proxy_discover_memory_root,
+                                   array);
+
+    s->subsys_count = array->len;
+    s->subsys = g_new0(OtDevProxySystem, s->subsys_count);
+    for (unsigned ix = 0; ix < array->len; ix++) {
+        MemoryRegion *mr;
+        mr = (MemoryRegion *)(g_array_index(array, MemoryRegion *, ix));
+        s->subsys[ix].mr = mr;
+        object_ref(OBJECT(mr));
+    }
+    g_array_free(array, TRUE);
+
+    object_child_foreach_recursive(ms, &ot_dev_proxy_map_bus, s);
+}
+
+static const Property ot_dev_proxy_properties[] = {
+    DEFINE_PROP_CHR("chardev", OtDevProxyState, chr),
+};
+
+static void ot_dev_proxy_reset_enter(Object *obj, ResetType type)
+{
+    OtDevProxyClass *c = OT_DEV_PROXY_GET_CLASS(obj);
+    OtDevProxyState *s = OT_DEV_PROXY(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    if (!s->items) {
+        /* only done once */
+        ot_dev_proxy_discover(s);
+    }
+
+    fifo8_reset(&s->rx_fifo);
+    memset(&s->rx_hdr, 0, sizeof(s->rx_hdr));
+    s->requester_uid = 0;
+    s->initiator_uid = 0;
+}
+
+static void ot_dev_proxy_realize(DeviceState *dev, Error **errp)
+{
+    OtDevProxyState *s = OT_DEV_PROXY(dev);
+    (void)errp;
+
+    qemu_chr_fe_set_handlers(&s->chr, &ot_dev_proxy_can_receive,
+                             &ot_dev_proxy_receive, NULL,
+                             &ot_dev_proxy_be_change, s, NULL, true);
+}
+
+static void ot_dev_proxy_init(Object *obj)
+{
+    OtDevProxyState *s = OT_DEV_PROXY(obj);
+
+    fifo8_create(&s->rx_fifo, 256u);
+    s->rx_buffer = g_new(uint32_t, 256u / sizeof(uint32_t));
+    QSIMPLEQ_INIT(&s->watchers);
+}
+
+static void ot_dev_proxy_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_dev_proxy_realize;
+    device_class_set_props(dc, ot_dev_proxy_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtDevProxyClass *pc = OT_DEV_PROXY_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_dev_proxy_reset_enter, NULL,
+                                       NULL, &pc->parent_phases);
+}
+
+static const TypeInfo ot_dev_proxy_info = {
+    .name = TYPE_OT_DEV_PROXY,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(OtDevProxyState),
+    .instance_init = &ot_dev_proxy_init,
+    .class_size = sizeof(OtDevProxyClass),
+    .class_init = &ot_dev_proxy_class_init,
+};
+
+static void ot_dev_proxy_register_types(void)
+{
+    type_register_static(&ot_dev_proxy_info);
+}
+
+type_init(ot_dev_proxy_register_types);
+
+/* ------------------------------------------------------------------------ */
+/* OtDevProxyStateWatcher */
+/* ------------------------------------------------------------------------ */
+
+static MemTxResult ot_dev_proxy_watcher_read_with_attrs(
+    void *opaque, hwaddr addr, uint64_t *val64, unsigned size, MemTxAttrs attrs)
+{
+    OtDevProxyWatcherState *s = opaque;
+
+    if (s->read && s->stop) {
+        unsigned role = MEMTXATTRS_GET_ROLE(attrs);
+        uint32_t address = s->address + (uint32_t)addr;
+        s->stop -= 1u;
+        ot_dev_proxy_notify_mmio_access(s->devproxy, s->wid, false, role,
+                                        address, size, 0);
+    }
+
+    *val64 = 0;
+    return MEMTX_OK;
+}
+
+static MemTxResult ot_dev_proxy_watcher_write_with_attrs(
+    void *opaque, hwaddr addr, uint64_t val64, unsigned size, MemTxAttrs attrs)
+{
+    OtDevProxyWatcherState *s = opaque;
+
+    if (s->write && s->stop) {
+        unsigned role = MEMTXATTRS_GET_ROLE(attrs);
+        uint32_t address = s->address + (uint32_t)addr;
+        ot_dev_proxy_notify_mmio_access(s->devproxy, s->wid, true, role,
+                                        address, size, (uint32_t)val64);
+        s->stop -= 1u;
+    }
+
+    return MEMTX_OK;
+}
+
+static const Property ot_dev_proxy_watcher_properties[] = {
+    DEFINE_PROP_LINK("devproxy", OtDevProxyWatcherState, devproxy,
+                     TYPE_OT_DEV_PROXY, OtDevProxyState *),
+    DEFINE_PROP_LINK("root", OtDevProxyWatcherState, root, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_UINT32("wid", OtDevProxyWatcherState, wid, UINT32_MAX),
+    DEFINE_PROP_UINT32("address", OtDevProxyWatcherState, address, UINT32_MAX),
+    DEFINE_PROP_UINT32("size", OtDevProxyWatcherState, size, 0),
+    DEFINE_PROP_UINT32("priority", OtDevProxyWatcherState, priority, 1),
+    DEFINE_PROP_UINT32("stop", OtDevProxyWatcherState, stop, UINT32_MAX),
+    DEFINE_PROP_BOOL("read", OtDevProxyWatcherState, read, UINT32_MAX),
+    DEFINE_PROP_BOOL("write", OtDevProxyWatcherState, write, UINT32_MAX),
+};
+
+static const MemoryRegionOps ot_dev_proxy_watcher_ops = {
+    .read_with_attrs = &ot_dev_proxy_watcher_read_with_attrs,
+    .write_with_attrs = &ot_dev_proxy_watcher_write_with_attrs,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 1u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_dev_proxy_watcher_realize(DeviceState *dev, Error **errp)
+{
+    OtDevProxyWatcherState *s = OT_DEV_PROXY_WATCHER(dev);
+    (void)errp;
+
+    g_assert(s->devproxy);
+    g_assert(s->root);
+    g_assert(s->wid != UINT32_MAX);
+    g_assert(s->address != UINT32_MAX);
+    g_assert(s->size != 0);
+
+    char *name = g_strdup_printf("%s.%u", TYPE_OT_DEV_PROXY_WATCHER, s->wid);
+    memory_region_init_io(&s->mmio, OBJECT(dev), &ot_dev_proxy_watcher_ops, s,
+                          name, s->size);
+    g_free(name);
+    memory_region_add_subregion_overlap(s->root, (hwaddr)s->address, &s->mmio,
+                                        (int)s->priority);
+}
+
+static void ot_dev_proxy_watcher_unrealize(DeviceState *dev)
+{
+    OtDevProxyWatcherState *s = OT_DEV_PROXY_WATCHER(dev);
+    OtDevProxyState *proxy = s->devproxy;
+
+    memory_region_del_subregion(s->root, &s->mmio);
+
+    /* remove self from proxy watcher list */
+    QSIMPLEQ_REMOVE(&proxy->watchers, s, OtDevProxyWatcherState, watcher);
+}
+
+static void
+ot_dev_proxy_watcher_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_dev_proxy_watcher_realize;
+    dc->unrealize = &ot_dev_proxy_watcher_unrealize;
+    device_class_set_props(dc, ot_dev_proxy_watcher_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static const TypeInfo ot_dev_proxy_watcher_info = {
+    .name = TYPE_OT_DEV_PROXY_WATCHER,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(OtDevProxyWatcherState),
+    .class_init = &ot_dev_proxy_watcher_class_init,
+};
+
+static void ot_dev_proxy_watcher_register_types(void)
+{
+    type_register_static(&ot_dev_proxy_watcher_info);
+}
+
+type_init(ot_dev_proxy_watcher_register_types);
diff --git a/hw/opentitan/ot_dm_tl.c b/hw/opentitan/ot_dm_tl.c
new file mode 100644
index 0000000000000..411eac108d879
--- /dev/null
+++ b/hw/opentitan/ot_dm_tl.c
@@ -0,0 +1,246 @@
+/*
+ * QEMU OpenTitan Debug Module to TileLink bridge
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_address_space.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_dm_tl.h"
+#include "hw/qdev-properties.h"
+#include "hw/riscv/debug.h"
+#include "hw/riscv/dtm.h"
+#include "hw/sysbus.h"
+#include "system/memory.h"
+#include "trace.h"
+
+/** Debug Module */
+struct OtDMTLState {
+    RISCVDebugDeviceState parent;
+    AddressSpace *as; /* Hart address space */
+    hwaddr tl_offset;
+    uint32_t value;
+    MemTxAttrs attrs;
+    char *dev_name;
+    bool dtm_ok; /* DTM is available */
+
+    RISCVDTMState *dtm;
+    SysBusDevice *tl_dev;
+    char *tl_as_name;
+    uint64_t tl_base;
+    uint32_t dmi_addr;
+    unsigned dmi_size;
+    bool enable;
+    uint8_t role;
+};
+
+struct OtDMTLClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+/* -------------------------------------------------------------------------- */
+/* DTM interface implementation */
+/* -------------------------------------------------------------------------- */
+
+static RISCVDebugResult
+ot_dm_tl_write_rq(RISCVDebugDeviceState *dev, uint32_t addr, uint32_t value)
+{
+    OtDMTLState *dmtl = OT_DM_TL(dev);
+
+    if (!dmtl->dtm_ok) {
+        trace_ot_dm_tl_dtm_not_available(dmtl->dev_name);
+        return RISCV_DEBUG_FAILED;
+    }
+
+    if (addr >= dmtl->dmi_size) {
+        trace_ot_dm_tl_invalid_addr(dmtl->dev_name, addr);
+        return RISCV_DEBUG_FAILED;
+    }
+
+    /* store address for next read back */
+    dmtl->tl_offset = addr * sizeof(uint32_t);
+
+    MemTxResult res;
+
+    res = address_space_rw(dmtl->as, dmtl->tl_base + dmtl->tl_offset,
+                           dmtl->attrs, &value, sizeof(value), true);
+
+    trace_ot_dm_tl_update(dmtl->dev_name, addr, value, "write", res);
+
+    return (res == MEMTX_OK) ? RISCV_DEBUG_NOERR : RISCV_DEBUG_FAILED;
+}
+
+static RISCVDebugResult
+ot_dm_tl_read_rq(RISCVDebugDeviceState *dev, uint32_t addr)
+{
+    OtDMTLState *dmtl = OT_DM_TL(dev);
+
+    if (!dmtl->dtm_ok) {
+        trace_ot_dm_tl_dtm_not_available(dmtl->dev_name);
+        return RISCV_DEBUG_FAILED;
+    }
+
+    if (addr >= dmtl->dmi_size) {
+        trace_ot_dm_tl_invalid_addr(dmtl->dev_name, addr);
+        return RISCV_DEBUG_FAILED;
+    }
+
+    /* store address for next read back */
+    dmtl->tl_offset = addr * sizeof(uint32_t);
+
+    MemTxResult res;
+
+    res =
+        address_space_rw(dmtl->as, dmtl->tl_base + dmtl->tl_offset, dmtl->attrs,
+                         &dmtl->value, sizeof(dmtl->value), false);
+
+    trace_ot_dm_tl_update(dmtl->dev_name, addr, 0, "read", res);
+
+    return (res == MEMTX_OK) ? RISCV_DEBUG_NOERR : RISCV_DEBUG_FAILED;
+}
+
+static uint32_t ot_dm_tl_read_value(RISCVDebugDeviceState *dev)
+{
+    OtDMTLState *dmtl = OT_DM_TL(dev);
+
+    uint32_t value = dmtl->value;
+
+    trace_ot_dm_tl_capture(dmtl->dev_name, dmtl->tl_offset, value);
+
+    return value;
+}
+
+static const Property ot_dm_tl_properties[] = {
+    DEFINE_PROP_LINK("dtm", OtDMTLState, dtm, TYPE_RISCV_DTM, RISCVDTMState *),
+    DEFINE_PROP_UINT32("dmi_addr", OtDMTLState, dmi_addr, 0),
+    DEFINE_PROP_UINT32("dmi_size", OtDMTLState, dmi_size, 0),
+    DEFINE_PROP_STRING("tl_as_name", OtDMTLState, tl_as_name),
+    DEFINE_PROP_UINT64("tl_addr", OtDMTLState, tl_base, UINT64_MAX),
+    DEFINE_PROP_LINK("tl_dev", OtDMTLState, tl_dev, TYPE_SYS_BUS_DEVICE,
+                     SysBusDevice *),
+    DEFINE_PROP_BOOL("enable", OtDMTLState, enable, true),
+    DEFINE_PROP_UINT8("role", OtDMTLState, role, UINT8_MAX),
+};
+
+static void ot_dm_tl_reset_exit(Object *obj, ResetType type)
+{
+    OtDMTLClass *c = OT_DM_TL_GET_CLASS(obj);
+    OtDMTLState *dmtl = OT_DM_TL(obj);
+
+    g_assert(dmtl->dtm != NULL);
+    g_assert(dmtl->dmi_size);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    if (!dmtl->dtm_ok) {
+        RISCVDTMClass *dtmc = RISCV_DTM_GET_CLASS(OBJECT(dmtl->dtm));
+        dmtl->dtm_ok =
+            (*dtmc->register_dm)(DEVICE(dmtl->dtm), RISCV_DEBUG_DEVICE(obj),
+                                 dmtl->dmi_addr, dmtl->dmi_size, dmtl->enable);
+        trace_ot_dm_tl_register(dmtl->dev_name, dmtl->dmi_addr, dmtl->dmi_size,
+                                dmtl->enable, dmtl->dtm_ok);
+    }
+
+    if (dmtl->dtm_ok) {
+        Object *soc = obj->parent;
+        Object *as;
+        OtAddressSpaceState *oas;
+
+        g_assert(dmtl->tl_as_name);
+        as = object_property_get_link(soc, dmtl->tl_as_name, &error_fatal);
+        oas = OBJECT_CHECK(OtAddressSpaceState, as, TYPE_OT_ADDRESS_SPACE);
+        dmtl->as = ot_address_space_get(oas);
+        g_assert(dmtl->as);
+    }
+}
+
+static void ot_dm_tl_realize(DeviceState *dev, Error **errp)
+{
+    OtDMTLState *dmtl = OT_DM_TL(dev);
+    (void)errp;
+
+    /* NOLINTNEXTLINE */
+    if (dmtl->role == UINT8_MAX) {
+        dmtl->attrs = MEMTXATTRS_UNSPECIFIED;
+    } else {
+        dmtl->attrs = MEMTXATTRS_WITH_ROLE(dmtl->role);
+    }
+
+    if (dmtl->tl_dev) {
+        dmtl->dev_name = g_strdup(object_get_typename(OBJECT(dmtl->tl_dev)));
+    } else {
+        dmtl->dev_name = g_strdup("");
+    }
+
+    if (dmtl->tl_base == UINT64_MAX) {
+        dmtl->tl_base = dmtl->dmi_addr * sizeof(uint32_t);
+    }
+}
+
+static void ot_dm_tl_init(Object *obj)
+{
+    OtDMTLState *s = OT_DM_TL(obj);
+    (void)s;
+}
+
+static void ot_dm_tl_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_dm_tl_realize;
+    device_class_set_props(dc, ot_dm_tl_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtDMTLClass *tc = OT_DM_TL_CLASS(klass);
+    resettable_class_set_parent_phases(rc, NULL, NULL, &ot_dm_tl_reset_exit,
+                                       &tc->parent_phases);
+
+    RISCVDebugDeviceClass *dmc = RISCV_DEBUG_DEVICE_CLASS(klass);
+    dmc->write_rq = &ot_dm_tl_write_rq;
+    dmc->read_rq = &ot_dm_tl_read_rq;
+    dmc->read_value = &ot_dm_tl_read_value;
+}
+
+static const TypeInfo ot_dm_tl_info = {
+    .name = TYPE_OT_DM_TL,
+    .parent = TYPE_RISCV_DEBUG_DEVICE,
+    .instance_init = &ot_dm_tl_init,
+    .instance_size = sizeof(OtDMTLState),
+    .class_size = sizeof(OtDMTLClass),
+    .class_init = &ot_dm_tl_class_init,
+};
+
+static void ot_dm_tl_register_types(void)
+{
+    type_register_static(&ot_dm_tl_info);
+}
+
+type_init(ot_dm_tl_register_types);
diff --git a/hw/opentitan/ot_dma.c b/hw/opentitan/ot_dma.c
new file mode 100644
index 0000000000000..fe1248070e3ae
--- /dev/null
+++ b/hw/opentitan/ot_dma.c
@@ -0,0 +1,1510 @@
+/*
+ * QEMU OpenTitan DMA device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Limitations: only MEM-to-MEM operations (including SHA hashing) are
+ *              supported. "Handshake" (i.e. DEVICE/FIFO operations) are not
+ *              supported, nor planned.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_address_space.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_dma.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "system/dma.h"
+#include "tomcrypt.h"
+#include "trace.h"
+
+#define PARAM_NUM_INT_CLEAR_SRCS 11u
+#define PARAM_NUM_IRQS           3u
+#define PARAM_NUM_ALERTS         1u
+
+/* clang-format off */
+
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(INTR_DMA_DONE, 0u, 1u)
+    SHARED_FIELD(INTR_DMA_ERROR, 1u, 1u)
+    SHARED_FIELD(INTR_DMA_MEM_BUF_LIMIT, 2u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(SRC_ADDR_LO, 0x10u)
+REG32(SRC_ADDR_HI, 0x14u)
+REG32(DEST_ADDR_LO, 0x18u)
+REG32(DEST_ADDR_HI, 0x1cu)
+REG32(ADDR_SPACE_ID, 0x20u)
+    FIELD(ADDR_SPACE_ID, SRC, 0u, 4u)
+    FIELD(ADDR_SPACE_ID, DEST, 4u, 4u)
+REG32(ENABLED_MEMORY_RANGE_BASE, 0x24u)
+REG32(ENABLED_MEMORY_RANGE_LIMIT, 0x28u)
+REG32(RANGE_VALID, 0x2cu)
+    FIELD(RANGE_VALID, VALID, 0u, 1u)
+REG32(RANGE_REGWEN, 0x30u)
+    FIELD(RANGE_REGWEN, EN, 0u, 4u)
+REG32(CFG_REGWEN, 0x34u)
+    FIELD(CFG_REGWEN, EN, 0u, 4u)
+REG32(TOTAL_DATA_SIZE, 0x38u)
+REG32(CHUNK_DATA_SIZE, 0x3cu)
+REG32(TRANSFER_WIDTH, 0x40u)
+    FIELD(TRANSFER_WIDTH, WIDTH, 0u, 2u)
+REG32(DEST_ADDR_LIMIT_LO, 0x44u)
+REG32(DEST_ADDR_LIMIT_HI, 0x48u)
+REG32(DEST_ADDR_THRESHOLD_LO, 0x4cu)
+REG32(DEST_ADDR_THRESHOLD_HI, 0x50u)
+REG32(CONTROL, 0x54u)
+    FIELD(CONTROL, OPCODE, 0u, 4u)
+    FIELD(CONTROL, HW_HANDSHAKE_EN, 4u, 1u)
+    FIELD(CONTROL, MEM_BUF_AUTO_INC_EN, 5u, 1u)
+    FIELD(CONTROL, FIFO_AUTO_INC_EN, 6u, 1u)
+    FIELD(CONTROL, DATA_DIR, 7u, 1u)
+    FIELD(CONTROL, INITIAL_TRANSFER, 8u, 1u)
+    FIELD(CONTROL, ABORT, 27u, 1u)
+    FIELD(CONTROL, GO, 31u, 1u)
+REG32(STATUS, 0x58u)
+    FIELD(STATUS, BUSY, 0u, 1u)
+    FIELD(STATUS, DONE, 1u, 1u)
+    FIELD(STATUS, ABORTED, 2u, 1u)
+    FIELD(STATUS, ERROR, 3u, 1u)
+    FIELD(STATUS, SHA2_DIGEST_VALID, 4u, 1u)
+REG32(ERROR_CODE, 0x5cu)
+    FIELD(ERROR_CODE, SRC_ADDRESS, 0u, 1u)
+    FIELD(ERROR_CODE, DST_ADDRESS, 1u, 1u)
+    FIELD(ERROR_CODE, OPCODE, 2u, 1u)
+    FIELD(ERROR_CODE, SIZE, 3u, 1u)
+    FIELD(ERROR_CODE, BUS, 4u, 1u)
+    FIELD(ERROR_CODE, BASE_LIMIT, 5u, 1u)
+    FIELD(ERROR_CODE, RANGE_VALID, 6u, 1u)
+    FIELD(ERROR_CODE, ASID, 7u, 1u)
+REG32(SHA2_DIGEST_0, 0x60u)
+REG32(SHA2_DIGEST_1, 0x64u)
+REG32(SHA2_DIGEST_2, 0x68u)
+REG32(SHA2_DIGEST_3, 0x6cu)
+REG32(SHA2_DIGEST_4, 0x70u)
+REG32(SHA2_DIGEST_5, 0x74u)
+REG32(SHA2_DIGEST_6, 0x78u)
+REG32(SHA2_DIGEST_7, 0x7cu)
+REG32(SHA2_DIGEST_8, 0x80u)
+REG32(SHA2_DIGEST_9, 0x84u)
+REG32(SHA2_DIGEST_10, 0x88u)
+REG32(SHA2_DIGEST_11, 0x8cu)
+REG32(SHA2_DIGEST_12, 0x90u)
+REG32(SHA2_DIGEST_13, 0x94u)
+REG32(SHA2_DIGEST_14, 0x98u)
+REG32(SHA2_DIGEST_15, 0x9cu)
+REG32(HANDSHAKE_INTR, 0xa0u)
+    FIELD(HANDSHAKE_INTR, ENABLE, 0, PARAM_NUM_INT_CLEAR_SRCS)
+REG32(CLEAR_INT_SRC, 0xa4u)
+    FIELD(CLEAR_INT_SRC, ENABLE, 0, PARAM_NUM_INT_CLEAR_SRCS)
+REG32(CLEAR_INT_BUS, 0xa8u)
+    FIELD(CLEAR_INT_BUS, ENABLE, 0, PARAM_NUM_INT_CLEAR_SRCS)
+REG32(INT_SRC_ADDR_0, 0xacu)
+REG32(INT_SRC_ADDR_1, 0xb0u)
+REG32(INT_SRC_ADDR_2, 0xb4u)
+REG32(INT_SRC_ADDR_3, 0xb8u)
+REG32(INT_SRC_ADDR_4, 0xbcu)
+REG32(INT_SRC_ADDR_5, 0xc0u)
+REG32(INT_SRC_ADDR_6, 0xc4u)
+REG32(INT_SRC_ADDR_7, 0xc8u)
+REG32(INT_SRC_ADDR_8, 0xccu)
+REG32(INT_SRC_ADDR_9, 0xd0u)
+REG32(INT_SRC_ADDR_10, 0xd8u)
+REG32(INT_SRC_WR_VAL_0, 0x12cu)
+REG32(INT_SRC_WR_VAL_1, 0x130u)
+REG32(INT_SRC_WR_VAL_2, 0x134u)
+REG32(INT_SRC_WR_VAL_3, 0x138u)
+REG32(INT_SRC_WR_VAL_4, 0x13cu)
+REG32(INT_SRC_WR_VAL_5, 0x140u)
+REG32(INT_SRC_WR_VAL_6, 0x144u)
+REG32(INT_SRC_WR_VAL_7, 0x148u)
+REG32(INT_SRC_WR_VAL_8, 0x14cu)
+REG32(INT_SRC_WR_VAL_9, 0x150u)
+REG32(INT_SRC_WR_VAL_10, 0x154u)
+
+/*
+ * Check presence of .role bitfield extension to MemTxAttrs.
+ * It may only exist in downstream extensions, where it defines the role of the
+ * initiator for every memory request.
+ */
+#if defined(MEMTXATTRS_HAS_ROLE) && (MEMTXATTRS_HAS_ROLE != 0)
+#define OT_DMA_HAS_ROLE
+#else
+#undef OT_DMA_HAS_ROLE
+#endif
+
+typedef enum {
+    TRANSACTION_WIDTH_BYTE = 0x0,
+    TRANSACTION_WIDTH_HALF = 0x1,
+    TRANSACTION_WIDTH_WORD = 0x2,
+    TRANSACTION_WIDTH_ERROR = 0x3,
+} OtDMATransferWidth;
+
+typedef enum {
+    OPCODE_COPY = 0x0,
+    OPCODE_COPY_SHA256 = 0x1,
+    OPCODE_COPY_SHA384 = 0x2,
+    OPCODE_COPY_SHA512 = 0x3,
+} OtDMAOpcode;
+
+typedef enum {
+    ASID_OT = 0x7,
+    ASID_CTRL = 0xa,
+    ASID_SYS = 0x9,
+} OtDMAAddrSpaceId;
+
+typedef enum {
+    ERR_SRC_ADDR,
+    ERR_DEST_ADDR,
+    ERR_OPCODE,
+    ERR_SIZE,
+    ERR_BUS,
+    ERR_BASE_LIMIT,
+    ERR_RANGE_VALID,
+    ERR_ASID,
+    ERR_COUNT
+} OtDMAError;
+
+typedef enum {
+    AS_OT,
+    AS_CTN,
+    AS_SYS,
+    AS_COUNT,
+    AS_INVALID = AS_COUNT
+} OtDMAAddrSpace;
+
+typedef enum {
+    SM_IDLE,
+    SM_CLEAR_INTR_SRC,
+    SM_WAIT_INTR_SRC_RESP,
+    SM_ADDR_SETUP,
+    SM_SEND_READ,
+    SM_WAIT_READ_RESP,
+    SM_SEND_WRITE,
+    SM_WAIT_WRITE_RESP,
+    SM_ERROR,
+    SM_SHA_FINALIZE,
+    SM_SHA_WAIT,
+} OtDMASM;
+
+/* clang-format on */
+
+typedef struct {
+    AddressSpace *as;
+    OtDMAAddrSpace asix;
+    MemoryRegion *mr;
+    void *buf;
+    dma_addr_t addr;
+    dma_addr_t size;
+    MemTxAttrs attrs;
+    MemTxResult res;
+    unsigned chunk;
+    bool write;
+} OtDMAOp;
+
+typedef struct {
+    hash_state state;
+    const struct ltc_hash_descriptor *desc;
+} OtDMASHA;
+
+typedef struct {
+    uint32_t memory_range_base;
+    uint32_t memory_range_limit;
+    uint8_t opcode;
+    bool handshake_en;
+    bool data_dir;
+    bool fifo_auto_inc_en;
+    bool membuf_auto_inc_en;
+    bool range_valid;
+} OtDMAControl;
+
+struct OtDMAState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ irqs[PARAM_NUM_IRQS];
+    IbexIRQ alerts[PARAM_NUM_ALERTS];
+    AddressSpace *ases[AS_COUNT];
+    QEMUTimer *timer;
+
+    OtDMASM state;
+    OtDMAOp op;
+    OtDMASHA sha;
+    uint32_t *regs;
+    unsigned tb_size; /* DMA transfer block size */
+    OtDMAControl control; /* captured regs on initial IDLE-GO transition */
+    bool abort;
+
+    char *ot_id;
+    char *ot_as_name; /* private AS unique name */
+    char *ctn_as_name; /* externel port AS unique name */
+    char *sys_as_name; /* external system AS unique name */
+    uint32_t pace_delay; /* pace DMA scheduling (ns) */
+    uint8_t block_size_lg2; /* log2 of DMA transfer block size */
+#ifdef OT_DMA_HAS_ROLE
+    uint8_t role;
+#endif
+};
+
+struct OtDMAClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_INT_SRC_WR_VAL_10)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define INTR_MASK \
+    (INTR_DMA_DONE_MASK | INTR_DMA_ERROR_MASK | INTR_DMA_MEM_BUF_LIMIT_MASK)
+#define ALERT_TEST_MASK R_ALERT_TEST_FATAL_FAULT_MASK
+#define CONTROL_MASK \
+    (R_CONTROL_OPCODE_MASK | R_CONTROL_HW_HANDSHAKE_EN_MASK | \
+     R_CONTROL_MEM_BUF_AUTO_INC_EN_MASK | R_CONTROL_FIFO_AUTO_INC_EN_MASK | \
+     R_CONTROL_DATA_DIR_MASK | R_CONTROL_INITIAL_TRANSFER_MASK | \
+     R_CONTROL_GO_MASK)
+
+#define DMA_ERROR(_err_) (1u << (_err_))
+
+/* default values, can be overridden with properties */
+#define DMA_PACE_NS             10000u /* 10us: slow down DMA, handle aborts */
+#define DMA_TRANSFER_BLOCK_LOG2 12u /* log2(size) of a single DMA block */
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(SRC_ADDR_LO),
+    REG_NAME_ENTRY(SRC_ADDR_HI),
+    REG_NAME_ENTRY(DEST_ADDR_LO),
+    REG_NAME_ENTRY(DEST_ADDR_HI),
+    REG_NAME_ENTRY(ADDR_SPACE_ID),
+    REG_NAME_ENTRY(ENABLED_MEMORY_RANGE_BASE),
+    REG_NAME_ENTRY(ENABLED_MEMORY_RANGE_LIMIT),
+    REG_NAME_ENTRY(RANGE_VALID),
+    REG_NAME_ENTRY(RANGE_REGWEN),
+    REG_NAME_ENTRY(CFG_REGWEN),
+    REG_NAME_ENTRY(TOTAL_DATA_SIZE),
+    REG_NAME_ENTRY(CHUNK_DATA_SIZE),
+    REG_NAME_ENTRY(TRANSFER_WIDTH),
+    REG_NAME_ENTRY(DEST_ADDR_LIMIT_LO),
+    REG_NAME_ENTRY(DEST_ADDR_LIMIT_HI),
+    REG_NAME_ENTRY(DEST_ADDR_THRESHOLD_LO),
+    REG_NAME_ENTRY(DEST_ADDR_THRESHOLD_HI),
+    REG_NAME_ENTRY(CONTROL),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(ERROR_CODE),
+    REG_NAME_ENTRY(SHA2_DIGEST_0),
+    REG_NAME_ENTRY(SHA2_DIGEST_1),
+    REG_NAME_ENTRY(SHA2_DIGEST_2),
+    REG_NAME_ENTRY(SHA2_DIGEST_3),
+    REG_NAME_ENTRY(SHA2_DIGEST_4),
+    REG_NAME_ENTRY(SHA2_DIGEST_5),
+    REG_NAME_ENTRY(SHA2_DIGEST_6),
+    REG_NAME_ENTRY(SHA2_DIGEST_7),
+    REG_NAME_ENTRY(SHA2_DIGEST_8),
+    REG_NAME_ENTRY(SHA2_DIGEST_9),
+    REG_NAME_ENTRY(SHA2_DIGEST_10),
+    REG_NAME_ENTRY(SHA2_DIGEST_11),
+    REG_NAME_ENTRY(SHA2_DIGEST_12),
+    REG_NAME_ENTRY(SHA2_DIGEST_13),
+    REG_NAME_ENTRY(SHA2_DIGEST_14),
+    REG_NAME_ENTRY(SHA2_DIGEST_15),
+    REG_NAME_ENTRY(HANDSHAKE_INTR),
+    REG_NAME_ENTRY(CLEAR_INT_SRC),
+    REG_NAME_ENTRY(CLEAR_INT_BUS),
+    REG_NAME_ENTRY(INT_SRC_ADDR_0),
+    REG_NAME_ENTRY(INT_SRC_ADDR_1),
+    REG_NAME_ENTRY(INT_SRC_ADDR_2),
+    REG_NAME_ENTRY(INT_SRC_ADDR_3),
+    REG_NAME_ENTRY(INT_SRC_ADDR_4),
+    REG_NAME_ENTRY(INT_SRC_ADDR_5),
+    REG_NAME_ENTRY(INT_SRC_ADDR_6),
+    REG_NAME_ENTRY(INT_SRC_ADDR_7),
+    REG_NAME_ENTRY(INT_SRC_ADDR_8),
+    REG_NAME_ENTRY(INT_SRC_ADDR_9),
+    REG_NAME_ENTRY(INT_SRC_ADDR_10),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_0),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_1),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_2),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_3),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_4),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_5),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_6),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_7),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_8),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_9),
+    REG_NAME_ENTRY(INT_SRC_WR_VAL_10),
+};
+#undef REG_NAME_ENTRY
+
+#define AS_NAME_ENTRY(_st_) [_st_] = stringify(_st_)
+static const char *AS_NAMES[] = {
+    AS_NAME_ENTRY(AS_OT),
+    AS_NAME_ENTRY(AS_CTN),
+    AS_NAME_ENTRY(AS_SYS),
+};
+#undef AS_NAME_ENTRY
+#define AS_NAME(_st_) \
+    ((_st_) >= 0 && (_st_) < ARRAY_SIZE(AS_NAMES) ? AS_NAMES[(_st_)] : "?")
+
+#define STATE_NAME_ENTRY(_st_) [_st_] = stringify(_st_)
+/* clang-format off */
+static const char *STATE_NAMES[] = {
+    STATE_NAME_ENTRY(SM_IDLE),
+    STATE_NAME_ENTRY(SM_CLEAR_INTR_SRC),
+    STATE_NAME_ENTRY(SM_WAIT_INTR_SRC_RESP),
+    STATE_NAME_ENTRY(SM_ADDR_SETUP),
+    STATE_NAME_ENTRY(SM_SEND_READ),
+    STATE_NAME_ENTRY(SM_WAIT_READ_RESP),
+    STATE_NAME_ENTRY(SM_SEND_WRITE),
+    STATE_NAME_ENTRY(SM_WAIT_WRITE_RESP),
+    STATE_NAME_ENTRY(SM_ERROR),
+    STATE_NAME_ENTRY(SM_SHA_FINALIZE),
+    STATE_NAME_ENTRY(SM_SHA_WAIT),
+};
+/* clang-format on */
+#undef STATE_NAME_ENTRY
+
+#define STATE_NAME(_st_) \
+    ((_st_) >= 0 && (_st_) < ARRAY_SIZE(STATE_NAMES) ? STATE_NAMES[(_st_)] : \
+                                                       "?")
+
+#define CHANGE_STATE(_f_, _sst_) \
+    ot_dma_change_state_line(_f_, SM_##_sst_, __LINE__)
+
+#define DMA_FATAL_ERROR(_s_) ot_dma_trigger_fatal_error(_s_, __func__, __LINE__)
+
+#define ot_dma_set_xerror(_s_, _err_) \
+    trace_ot_dma_set_error((_s_)->ot_id, __func__, __LINE__, \
+                           DMA_ERROR(_err_)); \
+    ot_dma_set_error(_s_, (_err_))
+
+
+/* -------------------------------------------------------------------------- */
+/* Private implementation */
+/* -------------------------------------------------------------------------- */
+
+static void ot_dma_change_state_line(OtDMAState *s, OtDMASM state, int line)
+{
+    if (s->state != state) {
+        trace_ot_dma_change_state(s->ot_id, line, STATE_NAME(state), state);
+        s->state = state;
+    }
+}
+
+static void ot_dma_update_irqs(OtDMAState *s)
+{
+    uint32_t level = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+    trace_ot_dma_irqs(s->ot_id, s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE],
+                      level);
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-function"
+
+static hwaddr ot_dma_get_src_address(const OtDMAState *s)
+{
+    return (hwaddr)s->regs[R_SRC_ADDR_LO] |
+           (((hwaddr)s->regs[R_SRC_ADDR_HI]) << 32u);
+}
+
+static hwaddr ot_dma_get_dest_address(const OtDMAState *s)
+{
+    return (hwaddr)s->regs[R_DEST_ADDR_LO] |
+           (((hwaddr)s->regs[R_DEST_ADDR_HI]) << 32u);
+}
+
+static unsigned ot_dma_get_src_asid(const OtDMAState *s)
+{
+    return (unsigned)FIELD_EX32(s->regs[R_ADDR_SPACE_ID], ADDR_SPACE_ID, SRC);
+}
+
+static unsigned ot_dma_get_dest_asid(const OtDMAState *s)
+{
+    return (unsigned)FIELD_EX32(s->regs[R_ADDR_SPACE_ID], ADDR_SPACE_ID, DEST);
+}
+
+static hwaddr ot_dma_get_dest_limit_address(const OtDMAState *s)
+{
+    return (hwaddr)s->regs[R_DEST_ADDR_LIMIT_LO] |
+           (((hwaddr)s->regs[R_DEST_ADDR_LIMIT_HI]) << 32u);
+}
+
+static hwaddr ot_dma_get_dest_threshold_address(const OtDMAState *s)
+{
+    return (hwaddr)s->regs[R_DEST_ADDR_THRESHOLD_LO] |
+           (((hwaddr)s->regs[R_DEST_ADDR_THRESHOLD_HI]) << 32u);
+}
+
+static bool ot_dma_is_range_locked(const OtDMAState *s)
+{
+    return s->regs[R_RANGE_REGWEN] != OT_MULTIBITBOOL4_TRUE;
+}
+
+static bool ot_dma_is_busy(const OtDMAState *s)
+{
+    return (bool)(s->regs[R_STATUS] & R_STATUS_BUSY_MASK);
+}
+
+static bool ot_dma_is_configurable(const OtDMAState *s)
+{
+    return !ot_dma_is_busy(s);
+}
+
+static bool ot_dma_is_on_error(const OtDMAState *s, unsigned err)
+{
+    g_assert(err < ERR_COUNT);
+
+    return ((bool)(s->regs[R_STATUS] & R_STATUS_ERROR_MASK)) &&
+           ((bool)(s->regs[R_ERROR_CODE] & DMA_ERROR(err)));
+}
+
+static void ot_dma_set_error(OtDMAState *s, unsigned err)
+{
+    g_assert(err < ERR_COUNT);
+
+    s->regs[R_STATUS] |= R_STATUS_ERROR_MASK;
+    s->regs[R_ERROR_CODE] |= DMA_ERROR(err);
+    s->regs[R_INTR_STATE] |= INTR_DMA_ERROR_MASK;
+
+    CHANGE_STATE(s, ERROR);
+
+    ot_dma_update_irqs(s);
+}
+
+static void ot_dma_check_range(OtDMAState *s, bool d_or_s, bool cross_ot)
+{
+    uint32_t lstart = s->control.memory_range_base;
+    uint32_t lend = s->control.memory_range_limit;
+
+    if (lstart > lend) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s DMA invalid range\n",
+                      __func__, s->ot_id, d_or_s ? "Dest" : "Src");
+        ot_dma_set_xerror(s, ERR_BASE_LIMIT);
+        return;
+    }
+
+    uint32_t tsize = s->regs[R_TOTAL_DATA_SIZE];
+    /* *_ADDR_HI ignored here, SBZ */
+    uint32_t tstart = s->regs[d_or_s ? R_DEST_ADDR_LO : R_SRC_ADDR_LO];
+    uint32_t tend = tstart + tsize;
+
+    if (!cross_ot) {
+        /* no check performed if transfer does not cross OT boundary */
+        return;
+    }
+
+    if (tend < tstart) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s DMA end overflow\n",
+                      __func__, s->ot_id, d_or_s ? "Dest" : "Src");
+        ot_dma_set_xerror(s, ERR_SIZE);
+        return;
+    }
+
+    if (tstart < lstart) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: %s DMA starts in prohibited region "
+                      "0x%08x < 0x%08x\n",
+                      __func__, s->ot_id, d_or_s ? "Dest" : "Src", tstart,
+                      lstart);
+        ot_dma_set_xerror(s, d_or_s ? ERR_DEST_ADDR : ERR_SRC_ADDR);
+        return;
+    }
+
+    if (tend > lend) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: %s DMA ends in prohibited region "
+                      "0x%08x > 0x%08x\n",
+                      __func__, s->ot_id, d_or_s ? "Dest" : "Src", tend, lend);
+        ot_dma_set_xerror(s, d_or_s ? ERR_DEST_ADDR : ERR_SRC_ADDR);
+        return;
+    }
+}
+
+static OtDMAAddrSpace ot_dma_get_asid(OtDMAState *s, bool d_or_s)
+{
+    uint32_t asid = d_or_s ? ot_dma_get_dest_asid(s) : ot_dma_get_src_asid(s);
+
+    switch (asid) {
+    case ASID_OT:
+        return AS_OT;
+    case ASID_CTRL:
+        return AS_CTN;
+        break;
+    case ASID_SYS:
+        return AS_SYS;
+    default:
+        return AS_COUNT;
+    }
+}
+
+static MemoryRegion *
+ot_dma_check_device(OtDMAState *s, bool d_or_s, OtDMAAddrSpace *asix,
+                    bool *is_dev, hwaddr *offset)
+{
+    OtDMAAddrSpace aix = ot_dma_get_asid(s, d_or_s);
+    if (aix >= AS_COUNT) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid address space\n",
+                      __func__, s->ot_id);
+        ot_dma_set_xerror(s, ERR_ASID);
+        return NULL;
+    }
+
+    if (!s->ases[aix]) {
+        error_setg(&error_fatal, "%s: %s address space not configured",
+                   s->ot_id, AS_NAME(aix));
+        return NULL;
+    }
+
+    AddressSpace *as = s->ases[aix];
+
+    hwaddr start =
+        d_or_s ? ot_dma_get_dest_address(s) : ot_dma_get_src_address(s);
+    hwaddr size = s->regs[R_TOTAL_DATA_SIZE];
+
+    MemoryRegionSection mrs = { 0 };
+    mrs = memory_region_find(as->root, start, size);
+
+    if (!mrs.mr || !int128_getlo(mrs.size)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Invalid %s address as:%s "
+                      "addr: 0x%" HWADDR_PRIx " size: 0x%" HWADDR_PRIx "\n",
+                      __func__, s->ot_id, d_or_s ? "dest" : "src", AS_NAME(aix),
+                      start, size);
+        /* the HW cannot detect this case; inform the guest and resume */
+    }
+
+    if (mrs.offset_within_region + int128_getlo(mrs.size) < size) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid size\n", __func__,
+                      s->ot_id);
+        /* the HW cannot detect this case; inform the guest and resume */
+    }
+
+    trace_ot_dma_check_device(s->ot_id, d_or_s ? "Dest" : "Src", AS_NAME(aix),
+                              start, size, mrs.mr ? mrs.mr->name : "invalid",
+                              mrs.mr ? mrs.mr->ram : false);
+    *asix = aix;
+    *is_dev = mrs.mr ? !mrs.mr->ram : false; /* neither RAM nor device... */
+    *offset = mrs.offset_within_region;
+
+    /* caller should invoke memory_region_unref(mrs.mr) once done with mr */
+    return mrs.mr;
+}
+
+static bool ot_dma_go(OtDMAState *s)
+{
+    /* fake DMA bug, see https://github.com/lowRISC/opentitan/pull/23854 */
+    if (s->regs[R_STATUS] & R_STATUS_DONE_MASK) {
+        s->regs[R_INTR_STATE] |= INTR_DMA_DONE_MASK;
+        ot_dma_update_irqs(s);
+    }
+
+    /*
+     * error checking follows HW: errors are accumulated, not rejected on first
+     * detected one.
+     */
+
+    CHANGE_STATE(s, ADDR_SETUP);
+
+    bool init_tf = (bool)(s->regs[R_CONTROL] & R_CONTROL_INITIAL_TRANSFER_MASK);
+    if (init_tf) {
+        s->control.memory_range_base = s->regs[R_ENABLED_MEMORY_RANGE_BASE];
+        s->control.memory_range_limit = s->regs[R_ENABLED_MEMORY_RANGE_LIMIT];
+        s->control.opcode =
+            (uint8_t)FIELD_EX32(s->regs[R_CONTROL], CONTROL, OPCODE);
+        s->control.handshake_en =
+            (bool)(s->regs[R_CONTROL] & R_CONTROL_HW_HANDSHAKE_EN_MASK);
+        s->control.range_valid =
+            (bool)(s->regs[R_RANGE_VALID] & R_RANGE_VALID_VALID_MASK);
+        /* following fields are not used: handshake mode only */
+        s->control.data_dir =
+            (bool)(s->regs[R_CONTROL] & R_CONTROL_DATA_DIR_MASK);
+        s->control.fifo_auto_inc_en =
+            (bool)(s->regs[R_CONTROL] & R_CONTROL_FIFO_AUTO_INC_EN_MASK);
+        s->control.membuf_auto_inc_en =
+            (bool)(s->regs[R_CONTROL] & R_CONTROL_MEM_BUF_AUTO_INC_EN_MASK);
+    }
+
+    switch (s->regs[R_TRANSFER_WIDTH]) {
+    case TRANSACTION_WIDTH_BYTE:
+    case TRANSACTION_WIDTH_HALF:
+    case TRANSACTION_WIDTH_WORD:
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid transaction width\n",
+                      __func__, s->ot_id);
+        ot_dma_set_xerror(s, ERR_SIZE);
+    }
+
+    /* DEVICE mode not yet supported */
+    if (s->control.handshake_en) {
+        qemu_log_mask(LOG_UNIMP, "%s: %s: Handshake mode is not supported\n",
+                      __func__, s->ot_id);
+        ot_dma_set_xerror(s, ERR_BUS);
+    }
+
+    if (s->regs[R_TOTAL_DATA_SIZE] == 0) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid total size\n", __func__,
+                      s->ot_id);
+        ot_dma_set_xerror(s, ERR_SIZE);
+    }
+
+    if (s->regs[R_CHUNK_DATA_SIZE] == 0) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid chunk size\n", __func__,
+                      s->ot_id);
+        ot_dma_set_xerror(s, ERR_SIZE);
+    }
+
+    if (s->regs[R_TOTAL_DATA_SIZE] != s->regs[R_CHUNK_DATA_SIZE]) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Chunk size differs from total size\n", __func__,
+                      s->ot_id);
+        ot_dma_set_xerror(s, ERR_SIZE);
+    }
+
+    const struct ltc_hash_descriptor *hdesc;
+    switch (s->control.opcode) {
+    case OPCODE_COPY:
+        trace_ot_dma_operation("copy", init_tf);
+        hdesc = NULL;
+        break;
+    case OPCODE_COPY_SHA256:
+        trace_ot_dma_operation("sha256", init_tf);
+        hdesc = &sha256_desc;
+        break;
+    case OPCODE_COPY_SHA384:
+        trace_ot_dma_operation("sha384", init_tf);
+        hdesc = &sha384_desc;
+        break;
+    case OPCODE_COPY_SHA512:
+        trace_ot_dma_operation("sha512", init_tf);
+        hdesc = &sha512_desc;
+        break;
+    default:
+        hdesc = NULL;
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid opcode %u\n", __func__,
+                      s->ot_id, s->control.opcode);
+        ot_dma_set_xerror(s, ERR_OPCODE);
+    }
+
+    if (hdesc) {
+        if (s->regs[R_TRANSFER_WIDTH] != TRANSACTION_WIDTH_WORD) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Invalid transaction width for hashing\n",
+                          __func__, s->ot_id);
+            ot_dma_set_xerror(s, ERR_SIZE);
+        }
+    }
+
+    OtDMASHA *sha = &s->sha;
+    if (init_tf) {
+        sha->desc = hdesc;
+        s->regs[R_STATUS] &= ~R_STATUS_SHA2_DIGEST_VALID_MASK;
+        if (sha->desc) {
+            int res = sha->desc->init(&sha->state);
+            g_assert(res == CRYPT_OK);
+        }
+    } else if (sha->desc != hdesc) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: SHA mode change w/o initial transfer\n", __func__);
+    }
+
+    MemoryRegion *smr;
+    hwaddr soffset = HWADDR_MAX;
+    OtDMAAddrSpace sasix = AS_INVALID;
+    bool sdev = false;
+    smr = ot_dma_check_device(s, false, &sasix, &sdev, &soffset);
+
+    MemoryRegion *dmr;
+    hwaddr doffset = HWADDR_MAX;
+    OtDMAAddrSpace dasix = AS_INVALID;
+    bool ddev = false;
+    dmr = ot_dma_check_device(s, true, &dasix, &ddev, &doffset);
+
+    /*
+     * Some src/dest combinations are not supported for now.
+     * Transfer from external 64-bit memory to external 64-bit memory would
+     * require a more complex implementation with two transfers with QEMU APIs
+     * on the 32 bit machine such as OT:
+     *  -1 from the source memory to a temporary buffer
+     *  -2 from the temporary buffer to the destination memory
+     * The temporary buffer would be an artifact for QEMU.
+     * This feature is not supported for now
+     */
+    if ((sasix == AS_SYS) && (dasix == AS_SYS)) {
+        qemu_log_mask(LOG_UNIMP, "%s: %s: SYS-to-SYS is not supported\n",
+                      __func__, s->ot_id);
+        ot_dma_set_xerror(s, ERR_ASID);
+    }
+
+    ot_dma_check_range(s, false, sasix == AS_OT && dasix != AS_OT);
+
+    ot_dma_check_range(s, true, sasix != AS_OT && dasix == AS_OT);
+
+    if (sdev && ddev) {
+        /* could be done w/ an intermediate buffer, but likely useless */
+        qemu_log_mask(LOG_UNIMP, "%s: %s: DEV-to-DEV is not supported\n",
+                      __func__, s->ot_id);
+        ot_dma_set_xerror(s, ERR_BUS);
+    }
+
+    OtDMAOp *op = &s->op;
+
+    memset(op, 0u, sizeof(OtDMAOp));
+
+    if (s->state != SM_ERROR) {
+        op->attrs.unspecified = false;
+#ifdef OT_DMA_HAS_ROLE
+        op->attrs.role = (unsigned)s->role;
+#endif
+        op->size = s->regs[R_TOTAL_DATA_SIZE];
+    }
+
+    /*
+     * The emulation ignores the transfer width as this is already managed
+     * with QEMU, see flatview_read_continue and flatview_write_continue.
+     * QEMU performs the best depending on the maximum transfer width as
+     * reported by the device region with is copied.
+     *
+     * Here nevertheless checks that requested transfer width is not larger
+     * than the maximum width supported by the emulated device and rejects the
+     * transfer if the requested width is not coherent with the device.
+     *
+     * This also means that the targetted device needs to provide the proper
+     * width for DMA-able registers so that there is no aligment/stride issues.
+     */
+    unsigned twidth = s->regs[R_TRANSFER_WIDTH];
+    uint32_t tmask = (1u << twidth) - 1u;
+
+    if (!ot_dma_is_on_error(s, ERR_SRC_ADDR) && (soffset & tmask)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Src 0x%" HWADDR_PRIx
+                      " not aligned on TRANSFER_WIDTH\n",
+                      __func__, s->ot_id, soffset);
+        ot_dma_set_xerror(s, ERR_SRC_ADDR);
+    }
+
+    if (!ot_dma_is_on_error(s, ERR_DEST_ADDR) && (doffset & tmask)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Dest 0x%" HWADDR_PRIx
+                      " not aligned on TRANSFER_WIDTH\n",
+                      __func__, s->ot_id, doffset);
+        ot_dma_set_xerror(s, ERR_DEST_ADDR);
+    }
+
+    if (!ot_dma_is_on_error(s, ERR_SRC_ADDR) && (sasix != AS_SYS)) {
+        if (s->regs[R_SRC_ADDR_HI] != 0) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Src address is too large\n",
+                          __func__, s->ot_id);
+            ot_dma_set_xerror(s, ERR_SRC_ADDR);
+        }
+    }
+
+    if (!ot_dma_is_on_error(s, ERR_DEST_ADDR) && (dasix != AS_SYS)) {
+        if (s->regs[R_DEST_ADDR_HI] != 0) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Dest address is too large\n", __func__,
+                          s->ot_id);
+            ot_dma_set_xerror(s, ERR_DEST_ADDR);
+        }
+    }
+
+    if (!s->control.range_valid) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Memory range not validated\n",
+                      __func__, s->ot_id);
+        ot_dma_set_xerror(s, ERR_RANGE_VALID);
+    }
+
+    if (sdev && smr) {
+        /* check first and last slots of the requested transfer */
+        int swidth = memory_access_size(smr, sizeof(uint32_t), soffset);
+        int ewidth = memory_access_size(smr, sizeof(uint32_t),
+                                        soffset + op->size - sizeof(uint32_t));
+        int dwidth = MIN(swidth, ewidth);
+        if (!ot_dma_is_on_error(s, ERR_SRC_ADDR) && (dwidth < (int)twidth)) {
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: Src device does not supported "
+                          "requested width: %u, max %d\n",
+                          __func__, s->ot_id, twidth, dwidth);
+            ot_dma_set_xerror(s, ERR_SRC_ADDR);
+        }
+    }
+    if (ddev && dmr) {
+        /* check first and last slots of the requested transfer */
+        int swidth = memory_access_size(dmr, sizeof(uint32_t), doffset);
+        int ewidth = memory_access_size(dmr, sizeof(uint32_t),
+                                        doffset + op->size - sizeof(uint32_t));
+        int dwidth = MIN(swidth, ewidth);
+        if (!ot_dma_is_on_error(s, ERR_DEST_ADDR) && (dwidth < (int)twidth)) {
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: Dest device does not supported "
+                          "requested width: %u, max %d\n",
+                          __func__, s->ot_id, twidth, dwidth);
+            ot_dma_set_xerror(s, ERR_DEST_ADDR);
+        }
+    }
+
+
+    if (!smr || !dmr) {
+        /*
+         * Real HW would start a DMA transaction and receive a bus error.
+         * Here it is impossible to start a transaction as memory buffer would
+         * not be valid, so trigger the error ealier.
+         * When device-to-device DMA is implemented, it might be possible to
+         * use a dummy, invalid region similar with no ops (see the default
+         * QEMU unassigned_mem_ops) to start a DMA operation and handle the
+         * error once it fails.
+         */
+        ot_dma_set_xerror(s, ERR_BUS);
+    }
+
+    if (s->state == SM_ERROR) {
+        if (smr) {
+            memory_region_unref(smr);
+        }
+        if (dmr) {
+            memory_region_unref(dmr);
+        }
+        return false;
+    }
+
+    /*
+     * src = dev, dest = mem -> read dev, write mem: read
+     * src = mem, dest = dev -> read mem, write dev: write
+     * src = mem, dest = mem -> read mem, write mem: write
+     * src = dev, dest = dev -> not yet supported
+     */
+    op->write = !sdev;
+
+    if (op->write) {
+        op->as = s->ases[dasix];
+        op->asix = dasix;
+        op->addr = ot_dma_get_dest_address(s);
+        op->mr = smr;
+        uintptr_t smem = (uintptr_t)memory_region_get_ram_ptr(smr);
+        smem += soffset;
+        op->buf = (void *)smem;
+        memory_region_unref(dmr);
+    } else {
+        op->addr = ot_dma_get_src_address(s);
+        op->as = s->ases[sasix];
+        op->asix = sasix;
+        op->mr = dmr;
+        uintptr_t dmem = (uintptr_t)memory_region_get_ram_ptr(dmr);
+        dmem += doffset;
+        op->buf = (void *)dmem;
+        memory_region_unref(smr);
+    }
+
+    g_assert(op->as);
+
+    trace_ot_dma_new_op(s->ot_id, op->write ? "write" : "read",
+                        AS_NAME(op->asix), op->mr->name, op->addr, op->size);
+
+    s->regs[R_STATUS] &=
+        ~(R_STATUS_DONE_MASK | R_STATUS_ABORTED_MASK | R_STATUS_ERROR_MASK);
+    s->regs[R_ERROR_CODE] = 0;
+    s->regs[R_STATUS] |= R_STATUS_BUSY_MASK;
+
+    CHANGE_STATE(s, SEND_READ);
+
+    timer_del(s->timer);
+    uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+    timer_mod_anticipate(s->timer, (int64_t)(now + s->pace_delay));
+
+    return true;
+}
+
+static void ot_dma_abort(OtDMAState *s)
+{
+    trace_ot_dma_abort(s->ot_id);
+
+    s->abort = true;
+
+    timer_del(s->timer);
+
+    uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+    if (ot_dma_is_busy(s)) {
+        /* simulate a delayed response */
+        now += s->pace_delay;
+    }
+
+    timer_mod(s->timer, (int64_t)now);
+}
+
+static void ot_dma_trigger_fatal_error(OtDMAState *s, const char *func,
+                                       int line)
+{
+    const OtDMAOp *op = &s->op;
+
+    error_report("%s: %s: DMA fatal error @ line %d", func, s->ot_id, line);
+    error_report("  %s addr 0x" DMA_ADDR_FMT " size 0x" DMA_ADDR_FMT
+                 " chunk %u",
+                 op->write ? "WR" : "RD", op->addr, op->size, op->chunk);
+    error_report("  asix %s mr %s (%p)", AS_NAME(op->asix),
+                 op->mr ? op->mr->name : "null", op->mr);
+#ifdef OT_DMA_HAS_ROLE
+    error_report("  res %d (role 0x%x)", op->res, (unsigned)op->attrs.role);
+#else
+    error_report("  res %d", op->res);
+#endif
+    g_assert_not_reached();
+}
+
+static void ot_dma_complete(OtDMAState *s)
+{
+    OtDMAOp *op = &s->op;
+
+    s->regs[R_STATUS] &= ~R_STATUS_BUSY_MASK;
+
+    if (s->abort) {
+        s->abort = false;
+        s->regs[R_STATUS] |= R_STATUS_ABORTED_MASK;
+        s->regs[R_INTR_STATE] |= INTR_DMA_ERROR_MASK;
+
+        trace_ot_dma_complete(s->ot_id, -1);
+
+        CHANGE_STATE(s, IDLE);
+    } else if (s->regs[R_CONTROL] & R_CONTROL_GO_MASK) {
+        if (!s->control.handshake_en) {
+            s->regs[R_CONTROL] &= ~R_CONTROL_GO_MASK;
+        }
+
+        trace_ot_dma_complete(s->ot_id, (int)op->res);
+
+        switch (op->res) {
+        case MEMTX_OK:
+            /* on success, there should be no more data to transfer */
+            if (op->size) {
+                DMA_FATAL_ERROR(s);
+            }
+            s->regs[R_STATUS] |= R_STATUS_DONE_MASK;
+            break;
+        /* device returned an error */
+        case MEMTX_ERROR:
+            ot_dma_set_xerror(s, ERR_BUS);
+            break;
+        /* nothing at that address */
+        case MEMTX_DECODE_ERROR:
+            ot_dma_set_xerror(s, op->write ? ERR_DEST_ADDR : ERR_SRC_ADDR);
+            break;
+        /* access denied */
+        case MEMTX_ACCESS_ERROR:
+            ot_dma_set_xerror(s, ERR_BUS);
+            break;
+        /* undocumented address_space_rw() error */
+        default:
+            DMA_FATAL_ERROR(s);
+        }
+
+        /* any DMA completion (success or failure) should have run with a MR */
+        if (!op->mr) {
+            DMA_FATAL_ERROR(s);
+        }
+
+        memory_region_unref(op->mr);
+        op->mr = NULL;
+
+        /* on failure, do not resume transfer with next chunk */
+        if (op->res != MEMTX_OK) {
+            return;
+        }
+
+        OtDMASHA *sha = &s->sha;
+        if (sha->desc) {
+            CHANGE_STATE(s, SHA_FINALIZE);
+
+            uint32_t md[64u / sizeof(uint32_t)];
+            int res = sha->desc->done(&sha->state, (uint8_t *)md);
+            g_assert(res == CRYPT_OK);
+
+            unsigned md_count = sha->desc->hashsize / sizeof(uint32_t);
+            for (unsigned ix = 0; ix < md_count; ix++) {
+                stl_be_p(&s->regs[R_SHA2_DIGEST_0 + ix], md[ix]);
+            }
+
+            s->regs[R_STATUS] |= R_STATUS_SHA2_DIGEST_VALID_MASK;
+
+            sha->desc = NULL;
+        }
+
+        s->regs[R_INTR_STATE] |= INTR_DMA_DONE_MASK;
+
+        CHANGE_STATE(s, IDLE);
+    } else {
+        DMA_FATAL_ERROR(s);
+    }
+
+    ot_dma_update_irqs(s);
+}
+
+static void ot_dma_transfer(void *opaque)
+{
+    OtDMAState *s = opaque;
+
+    if (!s->abort) {
+        OtDMAOp *op = &s->op;
+
+        g_assert(op->mr != NULL);
+
+        smp_mb();
+
+        hwaddr size = MIN(op->size, s->tb_size);
+
+        CHANGE_STATE(s, SEND_WRITE);
+
+        trace_ot_dma_transfer(s->ot_id, op->write ? "write" : "read",
+                              AS_NAME(op->asix), op->addr, size);
+        op->res = address_space_rw(op->as, op->addr, op->attrs, op->buf, size,
+                                   op->write);
+
+        op->chunk += 1;
+
+        if (op->res == MEMTX_OK) {
+            OtDMASHA *sha = &s->sha;
+            if (sha->desc) {
+                int res = sha->desc->process(&sha->state, op->buf, size);
+                g_assert(res == CRYPT_OK);
+            }
+
+            op->size -= size;
+            op->addr += size;
+            op->buf += size;
+
+            if (op->size) {
+                CHANGE_STATE(s, SEND_READ);
+
+                /* schedule next block if any */
+                uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+                timer_mod(s->timer, (int64_t)(now + s->pace_delay));
+                return;
+            }
+        }
+
+        /* when DMA is over or in error, ot_dma_complete handles it */
+    }
+
+    ot_dma_complete(s);
+}
+
+#pragma GCC diagnostic pop
+
+static uint64_t ot_dma_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtDMAState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_SRC_ADDR_LO:
+    case R_SRC_ADDR_HI:
+    case R_DEST_ADDR_LO:
+    case R_DEST_ADDR_HI:
+    case R_ADDR_SPACE_ID:
+    case R_ENABLED_MEMORY_RANGE_BASE:
+    case R_ENABLED_MEMORY_RANGE_LIMIT:
+    case R_RANGE_REGWEN:
+    case R_RANGE_VALID:
+    case R_TOTAL_DATA_SIZE:
+    case R_CHUNK_DATA_SIZE:
+    case R_TRANSFER_WIDTH:
+    case R_DEST_ADDR_LIMIT_LO:
+    case R_DEST_ADDR_LIMIT_HI:
+    case R_DEST_ADDR_THRESHOLD_LO:
+    case R_DEST_ADDR_THRESHOLD_HI:
+    case R_STATUS:
+    case R_ERROR_CODE:
+    case R_HANDSHAKE_INTR:
+    case R_CLEAR_INT_SRC:
+    case R_CLEAR_INT_BUS:
+    case R_SHA2_DIGEST_0 ... R_SHA2_DIGEST_15:
+    case R_INT_SRC_ADDR_0 ... R_INT_SRC_ADDR_10:
+    case R_INT_SRC_WR_VAL_0 ... R_INT_SRC_WR_VAL_10:
+        val32 = s->regs[reg];
+        break;
+    case R_CFG_REGWEN:
+        val32 = ot_dma_is_configurable(s) ? OT_MULTIBITBOOL4_TRUE :
+                                            OT_MULTIBITBOOL4_FALSE;
+        break;
+    case R_CONTROL:
+        val32 = s->regs[reg];
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_dma_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                             pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_dma_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                              unsigned size)
+{
+    OtDMAState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_dma_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+    case R_CONTROL:
+    case R_STATUS:
+    case R_RANGE_REGWEN:
+    case R_RANGE_VALID:
+    case R_ENABLED_MEMORY_RANGE_BASE:
+    case R_ENABLED_MEMORY_RANGE_LIMIT:
+        break;
+    default:
+        if (!ot_dma_is_configurable(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: %s (0x%03x) not configurable", __func__,
+                          s->ot_id, REG_NAME(reg), (uint32_t)addr);
+            return;
+        }
+        break;
+    }
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_dma_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[reg] = val32;
+        ot_dma_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] |= val32;
+        ot_dma_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+            ibex_irq_set(&s->alerts[ix], (int)((val32 >> ix) & 0x1u));
+        }
+        break;
+    case R_SRC_ADDR_LO ... R_SRC_ADDR_HI:
+    case R_DEST_ADDR_LO ... R_DEST_ADDR_HI:
+        s->regs[reg] = val32;
+        break;
+    case R_DEST_ADDR_LIMIT_LO ... R_DEST_ADDR_LIMIT_HI:
+    case R_DEST_ADDR_THRESHOLD_LO ... R_DEST_ADDR_THRESHOLD_HI:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: %s: Limit reg 0x%03x (%s) is not supported\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        s->regs[reg] = val32;
+        break;
+    case R_ENABLED_MEMORY_RANGE_BASE:
+    case R_ENABLED_MEMORY_RANGE_LIMIT:
+        if (!ot_dma_is_range_locked(s)) {
+            s->regs[reg] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: 0x%03x (%s) is locked\n",
+                          __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+            /* not sure what to do here, should we set an error? */
+        }
+        break;
+    case R_TOTAL_DATA_SIZE:
+    case R_CHUNK_DATA_SIZE:
+        s->regs[reg] = val32;
+        break;
+    case R_HANDSHAKE_INTR:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: %s: Handshake reg 0x%03x (%s) is not "
+                      "supported\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 &= R_HANDSHAKE_INTR_ENABLE_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_ADDR_SPACE_ID:
+        val32 &= R_ADDR_SPACE_ID_SRC_MASK | R_ADDR_SPACE_ID_DEST_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_RANGE_VALID:
+        if (!ot_dma_is_range_locked(s)) {
+            val32 &= R_RANGE_VALID_VALID_MASK;
+            s->regs[reg] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: 0x%03x (%s) is locked\n",
+                          __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        }
+        break;
+    case R_RANGE_REGWEN:
+        val32 &= R_RANGE_REGWEN_EN_MASK;
+        s->regs[reg] = ot_multibitbool_w0c_write(s->regs[reg], val32, 4u);
+        break;
+    case R_TRANSFER_WIDTH:
+        val32 &= R_TRANSFER_WIDTH_WIDTH_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_CONTROL: {
+        s->regs[reg] = val32 & ~R_CONTROL_ABORT_MASK;
+        if (val32 & R_CONTROL_ABORT_MASK) {
+            if (!s->abort) {
+                ot_dma_abort(s);
+            }
+        } else {
+            if (val32 & R_CONTROL_GO_MASK) {
+                if (s->state == SM_IDLE) {
+                    ot_dma_go(s);
+                } else {
+                    qemu_log_mask(LOG_GUEST_ERROR,
+                                  "%s: %s: cannot start DMA from state %s\n",
+                                  __func__, s->ot_id, STATE_NAME(s->state));
+                }
+            }
+        }
+    } break;
+    case R_STATUS:
+        val32 &=
+            (R_STATUS_DONE_MASK | R_STATUS_ABORTED_MASK | R_STATUS_ERROR_MASK);
+        s->regs[reg] &= ~val32; /* RW1C */
+        if (val32 & R_STATUS_ERROR_MASK) {
+            s->regs[R_ERROR_CODE] = 0;
+        }
+        break;
+    /* NOLINTNEXTLINE */
+    case R_CLEAR_INT_SRC:
+        val32 &= (1u << PARAM_NUM_INT_CLEAR_SRCS) - 1u;
+        s->regs[reg] = val32;
+        break;
+    case R_CLEAR_INT_BUS:
+        /* each bit: 0: CTN/system, 1: OT-internal */
+        val32 &= (1u << PARAM_NUM_INT_CLEAR_SRCS) - 1u;
+        s->regs[reg] = val32;
+        break;
+    case R_INT_SRC_ADDR_0 ... R_INT_SRC_ADDR_10:
+    case R_INT_SRC_WR_VAL_0 ... R_INT_SRC_WR_VAL_10:
+        s->regs[reg] = val32;
+        break;
+    case R_CFG_REGWEN:
+    case R_ERROR_CODE:
+    case R_SHA2_DIGEST_0 ... R_SHA2_DIGEST_15:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static const Property ot_dma_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtDMAState, ot_id),
+    DEFINE_PROP_STRING("ot_as_name", OtDMAState, ot_as_name),
+    DEFINE_PROP_STRING("ctn_as_name", OtDMAState, ctn_as_name),
+    DEFINE_PROP_STRING("sys_as_name", OtDMAState, sys_as_name),
+    DEFINE_PROP_UINT32("pace_delay", OtDMAState, pace_delay, DMA_PACE_NS),
+    DEFINE_PROP_UINT8("block_size_lg2", OtDMAState, block_size_lg2,
+                      DMA_TRANSFER_BLOCK_LOG2),
+#ifdef OT_DMA_HAS_ROLE
+    DEFINE_PROP_UINT8("role", OtDMAState, role, UINT8_MAX),
+#endif
+};
+
+static const MemoryRegionOps ot_dma_regs_ops = {
+    .read = &ot_dma_regs_read,
+    .write = &ot_dma_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_dma_reset_enter(Object *obj, ResetType type)
+{
+    OtDMAClass *c = OT_DMA_GET_CLASS(obj);
+    OtDMAState *s = OT_DMA(obj);
+
+    g_assert(s->ot_id);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->timer);
+
+    CHANGE_STATE(s, IDLE);
+
+    memset(s->regs, 0, REGS_SIZE);
+    memset(&s->control, 0, sizeof(s->control));
+    memset(&s->sha, 0, sizeof(s->sha));
+
+    s->regs[R_ADDR_SPACE_ID] = (ASID_OT << 4u) | (ASID_OT << 0u);
+    s->regs[R_RANGE_REGWEN] = OT_MULTIBITBOOL4_TRUE;
+    s->regs[R_CFG_REGWEN] = OT_MULTIBITBOOL4_TRUE; /* not used */
+    s->regs[R_TRANSFER_WIDTH] = TRANSACTION_WIDTH_WORD;
+    s->regs[R_HANDSHAKE_INTR] = (1u << PARAM_NUM_INT_CLEAR_SRCS) - 1u;
+
+    ot_dma_update_irqs(s);
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->alerts[ix], 0);
+    }
+}
+
+static void ot_dma_reset_exit(Object *obj, ResetType type)
+{
+    OtDMAClass *c = OT_DMA_GET_CLASS(obj);
+    OtDMAState *s = OT_DMA(obj);
+
+    g_assert(s->ot_id);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    Object *soc = obj->parent;
+    Object *as;
+    OtAddressSpaceState *oas;
+
+    if (!s->ases[AS_OT]) {
+        as = object_property_get_link(soc, s->ot_as_name, &error_fatal);
+        oas = OBJECT_CHECK(OtAddressSpaceState, as, TYPE_OT_ADDRESS_SPACE);
+        s->ases[AS_OT] = ot_address_space_get(oas);
+    }
+
+    if (!s->ases[AS_CTN] && s->ctn_as_name) {
+        as = object_property_get_link(soc, s->ctn_as_name, &error_fatal);
+        oas = OBJECT_CHECK(OtAddressSpaceState, as, TYPE_OT_ADDRESS_SPACE);
+        s->ases[AS_CTN] = ot_address_space_get(oas);
+    }
+
+    if (!s->ases[AS_SYS] && s->sys_as_name) {
+        as = object_property_get_link(soc, s->sys_as_name, &error_fatal);
+        oas = OBJECT_CHECK(OtAddressSpaceState, as, TYPE_OT_ADDRESS_SPACE);
+        s->ases[AS_SYS] = ot_address_space_get(oas);
+    }
+}
+
+static void ot_dma_realize(DeviceState *dev, Error **errp)
+{
+    OtDMAState *s = OT_DMA(dev);
+    (void)errp;
+
+    if (s->block_size_lg2 < 8u || s->block_size_lg2 > 20u) {
+        error_setg(&error_fatal, "%s: invalid DMA transfer block size: %u",
+                   __func__, 1u << s->block_size_lg2);
+        return;
+    }
+
+    s->tb_size = 1u << s->block_size_lg2;
+}
+
+static void ot_dma_init(Object *obj)
+{
+    OtDMAState *s = OT_DMA(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_dma_regs_ops, s, TYPE_OT_DMA,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    s->timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_dma_transfer, s);
+}
+
+static void ot_dma_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_dma_realize;
+    device_class_set_props(dc, ot_dma_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtDMAClass *mc = OT_DMA_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_dma_reset_enter, NULL,
+                                       &ot_dma_reset_exit, &mc->parent_phases);
+}
+
+static const TypeInfo ot_dma_info = {
+    .name = TYPE_OT_DMA,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtDMAState),
+    .instance_init = &ot_dma_init,
+    .class_size = sizeof(OtDMAClass),
+    .class_init = &ot_dma_class_init,
+};
+
+static void ot_dma_register_types(void)
+{
+    type_register_static(&ot_dma_info);
+}
+
+type_init(ot_dma_register_types);
diff --git a/hw/opentitan/ot_edn.c b/hw/opentitan/ot_edn.c
new file mode 100644
index 0000000000000..2acdf25ee95bb
--- /dev/null
+++ b/hw/opentitan/ot_edn.c
@@ -0,0 +1,1598 @@
+/*
+ * QEMU OpenTitan Entropy Distribution Network device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/typedefs.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_csrng.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_fifo32.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+
+/* TODO: need to better understand HW behavior */
+#undef EDN_DISCARD_PENDING_REQUEST_ON_DISABLE
+
+#define PARAM_NUM_IRQS   2u
+#define PARAM_NUM_ALERTS 2u
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(INTR_EDN_CMD_REQ_DONE, 0u, 1u)
+    SHARED_FIELD(INTR_EDN_FATAL_ERR, 1u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, RECOV_ALERT, 0u, 1u)
+    FIELD(ALERT_TEST, FATAL_ALERT, 1u, 1u)
+REG32(REGWEN, 0x10u)
+    FIELD(REGWEN, EN, 0u, 1u)
+REG32(CTRL, 0x14u)
+    FIELD(CTRL, EDN_ENABLE, 0u, 4u)
+    FIELD(CTRL, BOOT_REQ_MODE, 4u, 4u)
+    FIELD(CTRL, AUTO_REQ_MODE, 8u, 4u)
+    FIELD(CTRL, CMD_FIFO_RST, 12u, 4u)
+REG32(BOOT_INS_CMD, 0x18u)
+REG32(BOOT_GEN_CMD, 0x1cu)
+REG32(SW_CMD_REQ, 0x20u)
+REG32(SW_CMD_STS, 0x24u)
+    FIELD(SW_CMD_STS, CMD_REG_RDY, 0u, 1u)
+    FIELD(SW_CMD_STS, CMD_RDY, 1u, 1u)
+    FIELD(SW_CMD_STS, CMD_ACK, 2u, 1u)
+    FIELD(SW_CMD_STS, CMD_STS, 3u, 3u)
+REG32(HW_CMD_STS, 0x28u)
+    FIELD(HW_CMD_STS, BOOT_MODE, 0u, 1u)
+    FIELD(HW_CMD_STS, AUTO_MODE, 1u, 1u)
+    FIELD(HW_CMD_STS, CMD_TYPE, 2u, 4u)
+    FIELD(HW_CMD_STS, CMD_ACK, 6u, 1u)
+    FIELD(HW_CMD_STS, CMD_STS, 7u, 3u)
+REG32(RESEED_CMD, 0x2cu)
+REG32(GENERATE_CMD, 0x30u)
+REG32(MAX_NUM_REQS_BETWEEN_RESEEDS, 0x34u)
+REG32(RECOV_ALERT_STS, 0x38u)
+    FIELD(RECOV_ALERT_STS, EDN_ENABLE_FIELD_ALERT, 0u, 1u)
+    FIELD(RECOV_ALERT_STS, BOOT_REQ_MODE_FIELD_ALERT, 1u, 1u)
+    FIELD(RECOV_ALERT_STS, AUTO_REQ_MODE_FIELD_ALERT, 2u, 1u)
+    FIELD(RECOV_ALERT_STS, CMD_FIFO_RST_FIELD_ALERT, 3u, 1u)
+    FIELD(RECOV_ALERT_STS, EDN_BUS_CMP_ALERT, 12u, 1u)
+    FIELD(RECOV_ALERT_STS, CSRNG_ACK_ERR, 13u, 1u)
+REG32(ERR_CODE, 0x3cu)
+    FIELD(ERR_CODE, SFIFO_RESCMD_ERR, 0u, 1u)
+    FIELD(ERR_CODE, SFIFO_GENCMD_ERR, 1u, 1u)
+    FIELD(ERR_CODE, EDN_ACK_SM_ERR, 20u, 1u)
+    FIELD(ERR_CODE, EDN_MAIN_SM_ERR, 21u, 1u)
+    FIELD(ERR_CODE, EDN_CNTR_ERR, 22u, 1u)
+    FIELD(ERR_CODE, FIFO_WRITE_ERR, 28u, 1u)
+    FIELD(ERR_CODE, FIFO_READ_ERR, 29u, 1u)
+    FIELD(ERR_CODE, FIFO_STATE_ERR, 30u, 1u)
+REG32(ERR_CODE_TEST, 0x40u)
+    FIELD(ERR_CODE_TEST, VAL, 0u, 5u)
+REG32(MAIN_SM_STATE, 0x44u)
+    FIELD(MAIN_SM_STATE, VAL, 0u, 9u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_MAIN_SM_STATE)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define INTR_MASK (INTR_EDN_CMD_REQ_DONE_MASK | INTR_EDN_FATAL_ERR_MASK)
+#define ALERT_TEST_MASK \
+    (R_ALERT_TEST_RECOV_ALERT_MASK | R_ALERT_TEST_FATAL_ALERT_MASK)
+#define CTRL_MASK \
+    (R_CTRL_EDN_ENABLE_MASK | R_CTRL_BOOT_REQ_MODE_MASK | \
+     R_CTRL_AUTO_REQ_MODE_MASK | R_CTRL_CMD_FIFO_RST_MASK)
+#define RECOV_ALERT_STS_MASK \
+    (R_RECOV_ALERT_STS_EDN_ENABLE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_BOOT_REQ_MODE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_AUTO_REQ_MODE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_CMD_FIFO_RST_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_EDN_BUS_CMP_ALERT_MASK)
+#define ERR_CODE_MASK \
+    (R_ERR_CODE_SFIFO_RESCMD_ERR_MASK | R_ERR_CODE_SFIFO_GENCMD_ERR_MASK | \
+     R_ERR_CODE_EDN_ACK_SM_ERR_MASK | R_ERR_CODE_EDN_MAIN_SM_ERR_MASK | \
+     R_ERR_CODE_EDN_CNTR_ERR_MASK | R_ERR_CODE_FIFO_WRITE_ERR_MASK | \
+     R_ERR_CODE_FIFO_READ_ERR_MASK | R_ERR_CODE_FIFO_STATE_ERR_MASK)
+#define ERR_CODE_ACTIVE_MASK \
+    (R_ERR_CODE_EDN_ACK_SM_ERR_MASK | R_ERR_CODE_EDN_MAIN_SM_ERR_MASK | \
+     R_ERR_CODE_EDN_CNTR_ERR_MASK)
+
+#define ALERT_STATUS_BIT(_x_) R_RECOV_ALERT_STS_##_x_##_FIELD_ALERT_MASK
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(REGWEN),
+    REG_NAME_ENTRY(CTRL),
+    REG_NAME_ENTRY(BOOT_INS_CMD),
+    REG_NAME_ENTRY(BOOT_GEN_CMD),
+    REG_NAME_ENTRY(SW_CMD_REQ),
+    REG_NAME_ENTRY(SW_CMD_STS),
+    REG_NAME_ENTRY(RESEED_CMD),
+    REG_NAME_ENTRY(GENERATE_CMD),
+    REG_NAME_ENTRY(MAX_NUM_REQS_BETWEEN_RESEEDS),
+    REG_NAME_ENTRY(RECOV_ALERT_STS),
+    REG_NAME_ENTRY(ERR_CODE),
+    REG_NAME_ENTRY(ERR_CODE_TEST),
+    REG_NAME_ENTRY(MAIN_SM_STATE),
+};
+#undef REG_NAME_ENTRY
+
+#define ENDPOINT_COUNT_MAX 8u
+
+#define xtrace_ot_edn_error(_id_, _msg_) \
+    trace_ot_edn_error(_id_, __func__, __LINE__, _msg_)
+#define xtrace_ot_edn_xinfo(_id_, _msg_, _val_) \
+    trace_ot_edn_xinfo(_id_, __func__, __LINE__, _msg_, _val_)
+#define xtrace_ot_edn_dinfo(_id_, _msg_, _val_) \
+    trace_ot_edn_dinfo(_id_, __func__, __LINE__, _msg_, _val_)
+
+enum {
+    ALERT_RECOVERABLE,
+    ALERT_FATAL,
+    ALERT_COUNT,
+    ALERT_FATAL_STICKY = ALERT_COUNT,
+};
+
+static_assert(ALERT_COUNT == PARAM_NUM_ALERTS, "Invalid alert count");
+
+typedef enum {
+    EDN_IDLE, /* idle */
+    /* Boot */
+    EDN_BOOT_LOAD_INS, /* boot: load the instantiate command */
+    EDN_BOOT_INS_ACK_WAIT, /* boot: wait for instantiate command ack */
+    EDN_BOOT_LOAD_GEN, /* boot: load the generate command */
+    EDN_BOOT_GEN_ACK_WAIT, /* boot: wait for generate command ack */
+    EDN_BOOT_PULSE, /* boot: signal a done pulse */
+    EDN_BOOT_DONE, /* boot: stay in done state until leaving boot */
+    EDN_BOOT_LOAD_UNI, /* boot: load the uninstantiate command */
+    EDN_BOOT_UNI_ACK_WAIT, /* boot: wait for uninstantiate command ack */
+    /* Auto */
+    EDN_AUTO_LOAD_INS, /* auto: load the instantiate command */
+    EDN_AUTO_FIRST_ACK_WAIT, /* auto: wait for first instantiate command ack */
+    EDN_AUTO_ACK_WAIT, /* auto: wait for instantiate command ack */
+    EDN_AUTO_DISPATCH, /* auto: determine next command to be sent */
+    EDN_AUTO_CAPT_GEN_CNT, /* auto: capture the gen fifo count */
+    EDN_AUTO_SEND_GEN_CMD, /* auto: send the generate command */
+    EDN_AUTO_CAPT_RESEED_CNT, /* auto: capture the reseed fifo count */
+    EDN_AUTO_SEND_RESEED_CMD, /* auto: send the reseed command */
+    /* Misc */
+    EDN_SW_PORT_MODE, /* swport: no hw request mode */
+    EDN_REJECT_CSRNG_ENTROPY, /* stop accepting entropy from CSRNG */
+    EDN_ERROR, /* illegal state reached and hang */
+} OtEDNFsmState;
+
+typedef struct {
+    OtCSRNGClass *csrng; /* CSRNG class */
+    OtCSRNGState *device; /* CSRNG instance */
+    qemu_irq genbits_ready; /* Set when ready to receive entropy */
+    uint32_t appid; /* unique HW application id to identify on CSRNG */
+    unsigned rem_packet_count; /* remaining expected packets in generate cmd */
+    OtCSRNGCmdStatus hw_cmd_status; /* status of the last CSRNG command */
+    OtCSRNGCmdStatus sw_cmd_status; /* status of the last SW command */
+    uint32_t buffer[OT_CSRNG_CMD_WORD_MAX]; /* temp buffer for commands */
+    OtFifo32 bits_fifo; /* input FIFO with entropy received from CSRNG */
+    OtFifo32 cmd_gen_fifo; /* "Replay" FIFO to store generate command */
+    OtFifo32 cmd_reseed_fifo; /* "Replay" FIFO to store reseed command */
+    uint8_t hw_cmd_type; /* type of the last CSRNG HW command */
+    bool hw_ack; /* last SW command has been completed */
+    bool sw_ack; /* last SW command has been completed */
+    bool instantiated; /* instantiated state, not yet uninstantiated */
+    bool no_fips; /* true if 1+ rcv entropy packets were no FIPS-compliant */
+} OtEDNCSRNG;
+
+typedef struct OtEDNEndPoint {
+    ot_edn_push_entropy_fn fn; /* function to call when entropy is available */
+    void *opaque; /* opaque pointer forwaded with the fn() call */
+    OtFifo32 fifo; /* output unpacker */
+    size_t gen_count; /* Number of 32-bit entropy word in current generation */
+    size_t total_count; /* Total number of 32-bit entropy words */
+    QSIMPLEQ_ENTRY(OtEDNEndPoint) request;
+    bool fips; /* whether stored entropy is FIPS-compliant */
+} OtEDNEndPoint;
+
+typedef QSIMPLEQ_HEAD(OtEndpointQueue, OtEDNEndPoint) OtEndpointQueue;
+
+struct OtEDNState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ irqs[PARAM_NUM_IRQS];
+    IbexIRQ alerts[PARAM_NUM_ALERTS];
+    QEMUBH *ep_bh; /**< Endpoint requests */
+
+    uint32_t *regs;
+    uint32_t recov_alert_sts; /* track signalled recovery alert */
+
+    unsigned max_reqs_cnt; /* track remaining requests before reseeding */
+    OtEDNFsmState state; /* Main FSM state */
+    OtEDNCSRNG rng;
+    OtEDNEndPoint endpoints[ENDPOINT_COUNT_MAX];
+    OtEndpointQueue ep_requests;
+    bool sw_cmd_ready; /* ready to receive command in SW port mode */
+};
+
+struct OtEDNClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static const uint16_t OtEDNFsmStateCode[] = {
+    [EDN_IDLE] = 0b011000001,
+    [EDN_BOOT_LOAD_INS] = 0b111000111,
+    [EDN_BOOT_INS_ACK_WAIT] = 0b001111001,
+    [EDN_BOOT_LOAD_GEN] = 0b000000011,
+    [EDN_BOOT_GEN_ACK_WAIT] = 0b001110111,
+    [EDN_BOOT_PULSE] = 0b010101001,
+    [EDN_BOOT_DONE] = 0b011110000,
+    [EDN_BOOT_LOAD_UNI] = 0b100110101,
+    [EDN_BOOT_UNI_ACK_WAIT] = 0b000101100,
+    [EDN_AUTO_LOAD_INS] = 0b110111100,
+    [EDN_AUTO_FIRST_ACK_WAIT] = 0b110100011,
+    [EDN_AUTO_ACK_WAIT] = 0b010010010,
+    [EDN_AUTO_DISPATCH] = 0b101100001,
+    [EDN_AUTO_CAPT_GEN_CNT] = 0b100001110,
+    [EDN_AUTO_SEND_GEN_CMD] = 0b111011101,
+    [EDN_AUTO_CAPT_RESEED_CNT] = 0b010111111,
+    [EDN_AUTO_SEND_RESEED_CMD] = 0b001101010,
+    [EDN_SW_PORT_MODE] = 0b010010101,
+    [EDN_REJECT_CSRNG_ENTROPY] = 0b000011000,
+    [EDN_ERROR] = 0b101111110,
+};
+
+#define STATE_NAME_ENTRY(_st_) [_st_] = stringify(_st_)
+static const char *STATE_NAMES[] = {
+    STATE_NAME_ENTRY(EDN_IDLE),
+    STATE_NAME_ENTRY(EDN_BOOT_LOAD_INS),
+    STATE_NAME_ENTRY(EDN_BOOT_INS_ACK_WAIT),
+    STATE_NAME_ENTRY(EDN_BOOT_LOAD_GEN),
+    STATE_NAME_ENTRY(EDN_BOOT_GEN_ACK_WAIT),
+    STATE_NAME_ENTRY(EDN_BOOT_PULSE),
+    STATE_NAME_ENTRY(EDN_BOOT_DONE),
+    STATE_NAME_ENTRY(EDN_BOOT_LOAD_UNI),
+    STATE_NAME_ENTRY(EDN_BOOT_UNI_ACK_WAIT),
+    STATE_NAME_ENTRY(EDN_AUTO_LOAD_INS),
+    STATE_NAME_ENTRY(EDN_AUTO_FIRST_ACK_WAIT),
+    STATE_NAME_ENTRY(EDN_AUTO_ACK_WAIT),
+    STATE_NAME_ENTRY(EDN_AUTO_DISPATCH),
+    STATE_NAME_ENTRY(EDN_AUTO_CAPT_GEN_CNT),
+    STATE_NAME_ENTRY(EDN_AUTO_SEND_GEN_CMD),
+    STATE_NAME_ENTRY(EDN_AUTO_CAPT_RESEED_CNT),
+    STATE_NAME_ENTRY(EDN_AUTO_SEND_RESEED_CMD),
+    STATE_NAME_ENTRY(EDN_SW_PORT_MODE),
+    STATE_NAME_ENTRY(EDN_REJECT_CSRNG_ENTROPY),
+    STATE_NAME_ENTRY(EDN_ERROR),
+};
+#undef STATE_NAME_ENTRY
+#define STATE_NAME(_st_) \
+    ((_st_) >= 0 && (_st_) < ARRAY_SIZE(STATE_NAMES) ? STATE_NAMES[(_st_)] : \
+                                                       "?")
+
+static void ot_edn_fill_bits(void *opaque, const uint32_t *bits, bool fips);
+static void ot_edn_csrng_ack_irq(void *opaque, int n, int level);
+
+/* -------------------------------------------------------------------------- */
+/* Public API */
+/* -------------------------------------------------------------------------- */
+
+void ot_edn_connect_endpoint(OtEDNState *s, unsigned ep_id,
+                             ot_edn_push_entropy_fn fn, void *opaque)
+{
+    g_assert(ep_id < ENDPOINT_COUNT_MAX);
+    g_assert(fn);
+
+    OtEDNEndPoint *ep = &s->endpoints[ep_id];
+    if (ep->fn) {
+        g_assert(ep->fn == fn);
+    } else {
+        trace_ot_edn_connect_endpoint(s->rng.appid, ep_id);
+    }
+
+    ep->fn = fn;
+    ep->opaque = opaque;
+}
+
+int ot_edn_request_entropy(OtEDNState *s, unsigned ep_id)
+{
+    trace_ot_edn_request_entropy(s->rng.appid, ep_id);
+
+    g_assert(ep_id < ENDPOINT_COUNT_MAX);
+    OtEDNEndPoint *ep = &s->endpoints[ep_id];
+    if (!ep->fn) {
+        xtrace_ot_edn_error(s->rng.appid,
+                            "entropy request w/o initial connection");
+        return -1;
+    }
+
+    if (QSIMPLEQ_NEXT(ep, request) ||
+        QSIMPLEQ_LAST(&s->ep_requests, OtEDNEndPoint, request) == ep) {
+        xtrace_ot_edn_error(s->rng.appid, "endpoint already scheduled");
+        return -1;
+    }
+
+    QSIMPLEQ_INSERT_TAIL(&s->ep_requests, ep, request);
+
+    trace_ot_edn_schedule(s->rng.appid, "external entropy request");
+    qemu_bh_schedule(s->ep_bh);
+
+    return 0;
+}
+
+/* -------------------------------------------------------------------------- */
+/* Private implementation */
+/* -------------------------------------------------------------------------- */
+
+static void ot_edn_update_irqs(OtEDNState *s)
+{
+    uint32_t level = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+    trace_ot_edn_irqs(s->rng.appid, s->regs[R_INTR_STATE],
+                      s->regs[R_INTR_ENABLE], level);
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_edn_update_alerts(OtEDNState *s)
+{
+    uint32_t level = s->regs[R_ALERT_TEST];
+    s->regs[R_ALERT_TEST] = 0u;
+
+    /* only these errors seem to generate an alert (from HW observation) */
+    if (s->regs[R_ERR_CODE] & ERR_CODE_ACTIVE_MASK) {
+        level |= 1u << ALERT_FATAL;
+    }
+    if (s->regs[R_ERR_CODE_TEST] & ERR_CODE_ACTIVE_MASK) {
+        level |= 1u << ALERT_FATAL;
+        /*
+         * "The action of writing this register will force an error pulse."
+         * This documented assertion does not seem to hold true. Alert seems
+         * sticky
+         */
+    }
+    if (s->regs[R_RECOV_ALERT_STS] & RECOV_ALERT_STS_MASK) {
+        /* recoverable alerts do not trigger stick alert */
+        if (!(s->recov_alert_sts & (1u << ALERT_RECOVERABLE))) {
+            level |= 1u << ALERT_RECOVERABLE;
+            s->recov_alert_sts |= 1u << ALERT_RECOVERABLE;
+        }
+    }
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static bool ot_edn_check_multibitboot(OtEDNState *s, uint8_t mbbool,
+                                      uint32_t alert_bit)
+{
+    switch (mbbool) {
+    case OT_MULTIBITBOOL4_TRUE:
+        return true;
+    case OT_MULTIBITBOOL4_FALSE:
+        return false;
+    default:
+        break;
+    }
+
+    s->regs[R_RECOV_ALERT_STS] |= 1u << alert_bit;
+    ot_edn_update_alerts(s);
+    return false;
+}
+
+static bool ot_edn_is_enabled(const OtEDNState *s)
+{
+    uint32_t enable = FIELD_EX32(s->regs[R_CTRL], CTRL, EDN_ENABLE);
+
+    return enable == OT_MULTIBITBOOL4_TRUE;
+}
+
+static bool ot_edn_is_boot_req_mode(const OtEDNState *s)
+{
+    uint32_t auto_req = FIELD_EX32(s->regs[R_CTRL], CTRL, BOOT_REQ_MODE);
+
+    return auto_req == OT_MULTIBITBOOL4_TRUE;
+}
+
+static bool ot_edn_is_auto_req_mode(const OtEDNState *s)
+{
+    uint32_t auto_req = FIELD_EX32(s->regs[R_CTRL], CTRL, AUTO_REQ_MODE);
+
+    return auto_req == OT_MULTIBITBOOL4_TRUE;
+}
+
+static bool ot_edn_is_boot_mode(const OtEDNState *s)
+{
+    /* NOLINTNEXTLINE */
+    switch (s->state) {
+    case EDN_BOOT_INS_ACK_WAIT ... EDN_BOOT_UNI_ACK_WAIT:
+        return true;
+    default:
+        return false;
+    }
+}
+
+static bool ot_edn_is_auto_mode(const OtEDNState *s)
+{
+    /* NOLINTNEXTLINE */
+    switch (s->state) {
+    case EDN_AUTO_ACK_WAIT ... EDN_AUTO_SEND_RESEED_CMD:
+        return true;
+    default:
+        return false;
+    }
+}
+
+static bool ot_edn_is_sw_cmd_mode(const OtEDNState *s)
+{
+    /* NOLINTNEXTLINE */
+    switch (s->state) {
+    case EDN_AUTO_LOAD_INS:
+    case EDN_AUTO_FIRST_ACK_WAIT:
+    case EDN_SW_PORT_MODE:
+        return true;
+    default:
+        return false;
+    }
+}
+
+static OtCSRNGCmd ot_edn_get_last_csrng_command(const OtEDNState *s)
+{
+    const OtEDNCSRNG *c = &s->rng;
+
+    uint32_t last_cmd = FIELD_EX32(c->buffer[0], OT_CSNRG_CMD, ACMD);
+
+    /* NOLINTNEXTLINE */
+    switch (last_cmd) {
+    case OT_CSRNG_CMD_NONE:
+    case OT_CSRNG_CMD_INSTANTIATE:
+    case OT_CSRNG_CMD_RESEED:
+    case OT_CSRNG_CMD_GENERATE:
+    case OT_CSRNG_CMD_UPDATE:
+    case OT_CSRNG_CMD_UNINSTANTIATE:
+        return (OtCSRNGCmd)last_cmd;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static bool ot_edn_is_cmd_reg_rdy(const OtEDNState *s)
+{
+    /* NOLINTNEXTLINE */
+    switch (s->state) {
+    case EDN_AUTO_LOAD_INS:
+    case EDN_AUTO_FIRST_ACK_WAIT:
+    case EDN_AUTO_DISPATCH:
+        return true;
+    case EDN_SW_PORT_MODE:
+        return s->sw_cmd_ready;
+    default:
+        return false;
+    }
+}
+
+static bool ot_edn_is_cmd_rdy(const OtEDNState *s)
+{
+    /* NOLINTNEXTLINE */
+    switch (s->state) {
+    case EDN_AUTO_LOAD_INS:
+    case EDN_AUTO_DISPATCH:
+        return true;
+    case EDN_SW_PORT_MODE:
+        return s->sw_cmd_ready;
+    default:
+        return false;
+    }
+}
+
+static void ot_edn_reset_replay_fifos(OtEDNState *s)
+{
+    /*
+     * "The generate and reseed FIFOs are reset under four circumstances. These
+     *  circumstances are:
+     *  (a) when the EDN is disabled,
+     *  (b) when the SWPortMode state is entered,
+     *  (c) when the boot sequence has completed, or
+     *  (d) when the EDN enters the Idle state after it finishes operation in
+     *      auto mode."
+     */
+    OtEDNCSRNG *c = &s->rng;
+
+    trace_ot_edn_reset_replay_fifos(c->appid);
+
+    ot_fifo32_reset(&c->cmd_gen_fifo);
+    ot_fifo32_reset(&c->cmd_reseed_fifo);
+}
+
+static void ot_edn_manage_error(OtEDNState *s)
+{
+    s->regs[R_INTR_STATE] |= INTR_EDN_FATAL_ERR_MASK;
+    if (s->regs[R_ERR_CODE] & R_ERR_CODE_EDN_MAIN_SM_ERR_MASK) {
+        /* real HW seems to add this error on clock cycle after main error */
+        s->regs[R_ERR_CODE] |= R_ERR_CODE_EDN_ACK_SM_ERR_MASK;
+    }
+    ot_edn_update_irqs(s);
+    ot_edn_update_alerts(s);
+}
+
+static void ot_edn_change_state_line(OtEDNState *s, OtEDNFsmState state,
+                                     int line)
+{
+    if (state != s->state) {
+        trace_ot_edn_change_state(s->rng.appid, line, STATE_NAME(s->state),
+                                  s->state, STATE_NAME(state), state);
+    }
+
+    s->state = state;
+
+    switch (s->state) {
+    case EDN_ERROR:
+        s->rng.hw_cmd_type = (uint8_t)OT_CSRNG_CMD_NONE;
+        ot_edn_manage_error(s);
+        break;
+    case EDN_IDLE:
+    case EDN_REJECT_CSRNG_ENTROPY:
+        s->rng.hw_cmd_type = (uint8_t)OT_CSRNG_CMD_NONE;
+        break;
+    default:
+        break;
+    }
+}
+
+#define ot_edn_change_state(_s_, _st_) \
+    ot_edn_change_state_line(_s_, _st_, __LINE__)
+
+static void ot_edn_connect_csrng(OtEDNState *s)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    /* if the IRQ is not initialized, the EDN has yet to connected to CSRNG */
+    if (!c->genbits_ready) {
+        qemu_irq req_sts;
+        req_sts = qdev_get_gpio_in_named(DEVICE(s), TYPE_OT_EDN "-req_sts", 0);
+        c->genbits_ready =
+            c->csrng->connect_hw_app(c->device, c->appid, req_sts,
+                                     &ot_edn_fill_bits, s);
+        g_assert(c->genbits_ready);
+    }
+}
+
+static bool ot_edn_update_genbits_ready(OtEDNState *s)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    bool accept_entropy =
+        ot_edn_is_enabled(s) && (c->rem_packet_count > 0) &&
+        ot_fifo32_num_free(&c->bits_fifo) > OT_CSRNG_PACKET_WORD_COUNT;
+
+    trace_ot_edn_update_genbits_ready(c->appid, c->rem_packet_count,
+                                      ot_fifo32_num_free(&c->bits_fifo) /
+                                          sizeof(uint32_t),
+                                      accept_entropy);
+    qemu_set_irq(c->genbits_ready, accept_entropy);
+
+    return accept_entropy;
+}
+
+static OtCSRNGCmdStatus
+ot_edn_push_csrng_request(OtEDNState *s, bool auto_mode, uint32_t length)
+{
+    ot_edn_connect_csrng(s);
+
+    OtEDNCSRNG *c = &s->rng;
+
+    OtCSRNGCmdStatus res = CSRNG_STATUS_INVALID_ACMD;
+
+    for (unsigned cix = 0; cix < length; cix++) {
+        trace_ot_edn_push_csrng_command(c->appid, auto_mode ? "auto" : "boot",
+                                        c->buffer[cix]);
+        res = c->csrng->push_command(c->device, c->appid, c->buffer[cix]);
+        if (res != CSRNG_STATUS_SUCCESS) {
+            trace_ot_edn_push_csrng_error(c->appid, (int)res);
+            ot_edn_change_state(s, EDN_REJECT_CSRNG_ENTROPY);
+            s->regs[R_RECOV_ALERT_STS] |= R_RECOV_ALERT_STS_CSRNG_ACK_ERR_MASK;
+            /* do not expect any delayed completion */
+            memset(c->buffer, 0, sizeof(*c->buffer));
+            ot_edn_update_alerts(s);
+            break;
+        }
+    }
+
+    return res;
+}
+
+static bool ot_edn_check_command_ready(OtEDNState *s)
+{
+    const OtEDNCSRNG *c = &s->rng;
+    uint32_t command = FIELD_EX32(c->buffer[0], OT_CSNRG_CMD, ACMD);
+    if (command != OT_CSRNG_CMD_NONE) {
+        xtrace_ot_edn_error(c->appid, "Another command is already scheduled");
+        s->regs[R_ERR_CODE] |= R_ERR_CODE_EDN_MAIN_SM_ERR_MASK;
+        ot_edn_change_state(s, EDN_ERROR);
+        return false;
+    }
+
+    return true;
+}
+
+static void ot_edn_send_boot_req(OtEDNState *s, unsigned reg)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    if (!ot_edn_check_command_ready(s)) {
+        return;
+    }
+
+    c->buffer[0u] = s->regs[reg];
+    uint32_t command = FIELD_EX32(c->buffer[0], OT_CSNRG_CMD, ACMD);
+    uint32_t clen = FIELD_EX32(command, OT_CSNRG_CMD, CLEN);
+    if (clen) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %u: boot command CLEN is non-zero\n", __func__,
+                      c->appid);
+        /*
+         * the HW does not consider this case as an error and resume execution,
+         * which causes the CSRNG to stall
+         */
+    }
+
+    if (command == OT_CSRNG_CMD_GENERATE) {
+        c->rem_packet_count = FIELD_EX32(c->buffer[0], OT_CSNRG_CMD, GLEN);
+        xtrace_ot_edn_dinfo(c->appid, "Boot generation w/ packets",
+                            c->rem_packet_count);
+        ot_edn_update_genbits_ready(s);
+        ot_edn_change_state(s, EDN_BOOT_LOAD_GEN);
+        for (unsigned epix = 0; epix < ARRAY_SIZE(s->endpoints); epix++) {
+            s->endpoints[epix].gen_count = 0;
+        }
+    }
+
+    c->hw_cmd_type = (uint8_t)FIELD_EX32(command, OT_CSNRG_CMD, ACMD);
+    c->hw_cmd_status = ot_edn_push_csrng_request(s, false, 1u);
+    if (c->hw_cmd_status) {
+        return;
+    }
+
+    /*
+     * CSRNG request should be completed asynchronously, changing the state here
+     * should occur before ot_edn_csrng_ack_irq is called.
+     */
+    switch (command) {
+    case OT_CSRNG_CMD_INSTANTIATE:
+        c->no_fips = false;
+        ot_edn_change_state(s, EDN_BOOT_INS_ACK_WAIT);
+        break;
+    case OT_CSRNG_CMD_GENERATE:
+        ot_edn_change_state(s, EDN_BOOT_GEN_ACK_WAIT);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void ot_edn_send_auto_reseed_cmd(OtEDNState *s)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    if (!ot_edn_check_command_ready(s)) {
+        return;
+    }
+
+    bool fatal_error = false;
+    uint32_t command;
+    uint32_t length;
+
+    if (ot_fifo32_is_empty(&c->cmd_reseed_fifo)) {
+        s->regs[R_ERR_CODE] |=
+            R_ERR_CODE_SFIFO_RESCMD_ERR_MASK | R_ERR_CODE_FIFO_READ_ERR_MASK;
+        fatal_error = true;
+        command = (uint32_t)OT_CSRNG_CMD_NONE;
+        length = 1u; /* always push the command */
+    } else {
+        command = ot_fifo32_peek(&c->cmd_reseed_fifo);
+        length = FIELD_EX32(command, OT_CSNRG_CMD, CLEN) + 1u;
+        if (ot_fifo32_num_used(&c->cmd_reseed_fifo) < length) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_SFIFO_RESCMD_ERR_MASK |
+                                   R_ERR_CODE_FIFO_READ_ERR_MASK;
+            fatal_error = true;
+        }
+        uint32_t num = length;
+        const uint32_t *cmd;
+        cmd = ot_fifo32_peek_buf(&c->cmd_reseed_fifo, num, &length);
+        if (num != length) {
+            xtrace_ot_edn_error(c->appid, "incoherent reseed FIFO length");
+        }
+        memcpy(c->buffer, cmd, length * sizeof(uint32_t));
+    }
+
+
+    if (fatal_error) {
+        ot_edn_change_state(s, EDN_ERROR);
+        return;
+    }
+
+    ot_edn_change_state(s, EDN_AUTO_SEND_RESEED_CMD);
+
+    c->hw_cmd_type = (uint8_t)FIELD_EX32(command, OT_CSNRG_CMD, ACMD);
+    c->hw_cmd_status = ot_edn_push_csrng_request(s, true, length);
+    if (c->hw_cmd_status) {
+        return;
+    }
+    c->no_fips = false;
+
+    ot_edn_change_state(s, EDN_AUTO_ACK_WAIT);
+}
+
+static void ot_edn_send_auto_generate_cmd(OtEDNState *s)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    if (!ot_edn_check_command_ready(s)) {
+        return;
+    }
+
+    bool fatal_error = false;
+    uint32_t command;
+    uint32_t length;
+
+    if (ot_fifo32_is_empty(&c->cmd_gen_fifo)) {
+        s->regs[R_ERR_CODE] |=
+            R_ERR_CODE_SFIFO_GENCMD_ERR_MASK | R_ERR_CODE_FIFO_READ_ERR_MASK;
+        fatal_error = true;
+        command = (uint32_t)OT_CSRNG_CMD_NONE;
+        length = 1u; /* always push the command */
+    } else {
+        command = ot_fifo32_peek(&c->cmd_gen_fifo);
+        length = FIELD_EX32(command, OT_CSNRG_CMD, CLEN) + 1u;
+        if (ot_fifo32_num_used(&c->cmd_gen_fifo) < length) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_SFIFO_GENCMD_ERR_MASK |
+                                   R_ERR_CODE_FIFO_READ_ERR_MASK;
+            fatal_error = true;
+        }
+        uint32_t num = length;
+        const uint32_t *cmd =
+            ot_fifo32_peek_buf(&c->cmd_gen_fifo, num, &length);
+        if (num != length) {
+            xtrace_ot_edn_error(c->appid, "incoherent generate FIFO length");
+        }
+        memcpy(c->buffer, cmd, length * sizeof(uint32_t));
+        c->rem_packet_count = FIELD_EX32(c->buffer[0], OT_CSNRG_CMD, GLEN);
+        xtrace_ot_edn_dinfo(c->appid, "Generate cmd w/ packets",
+                            c->rem_packet_count);
+    }
+
+    if (fatal_error) {
+        ot_edn_change_state(s, EDN_ERROR);
+        return;
+    }
+
+    xtrace_ot_edn_xinfo(c->appid, "COMMAND", c->buffer[0]);
+
+    ot_edn_update_genbits_ready(s);
+    ot_edn_change_state(s, EDN_AUTO_SEND_RESEED_CMD);
+
+    for (unsigned epix = 0; epix < ARRAY_SIZE(s->endpoints); epix++) {
+        s->endpoints[epix].gen_count = 0;
+    }
+
+    c->hw_cmd_type = (uint8_t)FIELD_EX32(command, OT_CSNRG_CMD, ACMD);
+    c->hw_cmd_status = ot_edn_push_csrng_request(s, true, length);
+    if (c->hw_cmd_status) {
+        return;
+    }
+
+    if (s->max_reqs_cnt) {
+        s->max_reqs_cnt -= 1u;
+    }
+
+    ot_edn_change_state(s, EDN_AUTO_ACK_WAIT);
+}
+
+static void ot_edn_send_boot_uninstanciate_cmd(OtEDNState *s)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    g_assert(s->state == EDN_BOOT_LOAD_UNI);
+
+    if (!ot_edn_check_command_ready(s)) {
+        return;
+    }
+
+    c->buffer[0u] =
+        FIELD_DP32(0, OT_CSNRG_CMD, ACMD, OT_CSRNG_CMD_UNINSTANTIATE);
+
+    c->hw_cmd_type = (uint8_t)OT_CSRNG_CMD_UNINSTANTIATE;
+    c->hw_cmd_status = ot_edn_push_csrng_request(s, false, 1u);
+    if (c->hw_cmd_status) {
+        return;
+    }
+
+    ot_edn_change_state(s, EDN_BOOT_UNI_ACK_WAIT);
+}
+
+static void ot_edn_handle_disable(OtEDNState *s)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    g_assert(ot_edn_get_last_csrng_command(s) != OT_CSRNG_CMD_UNINSTANTIATE);
+
+    c->no_fips = false;
+    c->rem_packet_count = 0;
+    xtrace_ot_edn_dinfo(c->appid, "discard all entropy packets",
+                        ot_fifo32_num_used(&c->bits_fifo));
+    ot_fifo32_reset(&c->bits_fifo);
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->endpoints); ix++) {
+        OtEDNEndPoint *ep = &s->endpoints[ix];
+        ot_fifo32_reset(&ep->fifo);
+        ep->fips = false;
+    }
+
+/* discard any on-going EP request */
+#ifdef EDN_DISCARD_PENDING_REQUEST_ON_DISABLE
+    OtEDNEndPoint *tmp, *next;
+    QSIMPLEQ_FOREACH_SAFE(tmp, &s->ep_requests, request, next) {
+        QSIMPLEQ_REMOVE_HEAD(&s->ep_requests, request);
+    }
+#endif
+
+    /* signal CSRNG that EDN is no longer ready to receive entropy */
+    ot_edn_update_genbits_ready(s);
+
+    /* disconnect */
+    qemu_irq rdy;
+    rdy = c->csrng->connect_hw_app(c->device, c->appid, NULL, NULL, NULL);
+    g_assert(!rdy);
+
+    c->genbits_ready = NULL;
+}
+
+static void ot_edn_clean_up(OtEDNState *s, bool discard_requests)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    trace_ot_edn_clean_up(c->appid, discard_requests);
+
+    c->instantiated = false;
+    s->sw_cmd_ready = false;
+    c->hw_cmd_status = CSRNG_STATUS_SUCCESS;
+    c->sw_cmd_status = CSRNG_STATUS_SUCCESS;
+    c->hw_ack = false;
+    c->sw_ack = false;
+    s->recov_alert_sts = 0u;
+    s->max_reqs_cnt = 0;
+    memset(c->buffer, 0, sizeof(*c->buffer));
+    ot_fifo32_reset(&c->bits_fifo);
+    ot_edn_update_irqs(s);
+    ot_edn_update_alerts(s);
+
+    if (discard_requests) {
+        /* clear all pending end point requests */
+        while (QSIMPLEQ_FIRST(&s->ep_requests)) {
+            QSIMPLEQ_REMOVE_HEAD(&s->ep_requests, request);
+        }
+    }
+
+    for (unsigned epix = 0; epix < ARRAY_SIZE(s->endpoints); epix++) {
+        ot_fifo32_reset(&s->endpoints[epix].fifo);
+        s->endpoints[epix].fips = false;
+    }
+
+    bool accept_entropy = ot_edn_update_genbits_ready(s);
+    g_assert(!accept_entropy);
+    c->genbits_ready = NULL;
+}
+
+static bool ot_edn_update_mode(OtEDNState *s)
+{
+    /*
+     * CTRL may have disabled EDN, while the EDN was in an active state.
+     * If disablement has been requested, now is time to handle it, if not
+     * already done or in a fatal error state.
+     */
+    if (!ot_edn_is_enabled(s)) {
+        if (s->state != EDN_IDLE) {
+            ot_edn_handle_disable(s);
+            ot_edn_clean_up(s, false);
+            if (s->state != EDN_ERROR) {
+                ot_edn_change_state(s, EDN_IDLE);
+            }
+        }
+        return true;
+    }
+
+    /* EDN is enabled */
+
+    OtEDNCSRNG *c = &s->rng;
+
+    if (s->state == EDN_IDLE) {
+        if (ot_edn_is_boot_req_mode(s)) {
+            trace_ot_edn_enable(c->appid, "boot mode");
+            ot_edn_change_state(s, EDN_BOOT_LOAD_INS);
+            ot_edn_send_boot_req(s, R_BOOT_INS_CMD);
+        } else if (ot_edn_is_auto_req_mode(s)) {
+            trace_ot_edn_enable(c->appid, "auto mode");
+            s->sw_cmd_ready = true;
+            ot_edn_change_state(s, EDN_AUTO_LOAD_INS);
+        } else {
+            trace_ot_edn_enable(c->appid, "sw mode");
+            s->sw_cmd_ready = true;
+            ot_edn_reset_replay_fifos(s);
+            ot_edn_change_state(s, EDN_SW_PORT_MODE);
+        }
+        return true;
+    }
+
+    if (s->state == EDN_BOOT_DONE && !ot_edn_is_boot_req_mode(s)) {
+        trace_ot_edn_enable(c->appid, "boot uninstantiate");
+        ot_edn_change_state(s, EDN_BOOT_LOAD_UNI);
+        ot_edn_send_boot_uninstanciate_cmd(s);
+        return true;
+    }
+
+    return s->state == EDN_SW_PORT_MODE;
+}
+
+static void ot_edn_handle_ctrl(OtEDNState *s, uint32_t val32)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    bool enabled =
+        FIELD_EX32(s->regs[R_CTRL], CTRL, EDN_ENABLE) == OT_MULTIBITBOOL4_TRUE;
+
+    s->regs[R_CTRL] = val32;
+
+#define CHECK_MULTIBOOT(_s_, _r_, _b_) \
+    ot_edn_check_multibitboot((_s_), FIELD_EX32(val32, _r_, _b_), \
+                              ALERT_STATUS_BIT(_b_));
+    bool enable = CHECK_MULTIBOOT(s, CTRL, EDN_ENABLE);
+    bool boot_req_mode = CHECK_MULTIBOOT(s, CTRL, BOOT_REQ_MODE);
+    bool auto_req_mode = CHECK_MULTIBOOT(s, CTRL, AUTO_REQ_MODE);
+    bool cmd_fifo_rst = CHECK_MULTIBOOT(s, CTRL, CMD_FIFO_RST);
+    bool disabling = !enable && enabled;
+
+    trace_ot_edn_ctrl_in_state(c->appid, STATE_NAME(s->state), s->state, enable,
+                               boot_req_mode, auto_req_mode, cmd_fifo_rst,
+                               disabling);
+
+    if ((FIELD_EX32(s->regs[R_CTRL], CTRL, CMD_FIFO_RST) ==
+         OT_MULTIBITBOOL4_TRUE) ||
+        disabling) {
+        ot_edn_reset_replay_fifos(s);
+    }
+
+    if (!ot_edn_update_mode(s)) {
+        trace_ot_edn_delay_mode_change(c->appid, STATE_NAME(s->state), val32);
+    }
+}
+
+static void ot_edn_complete_sw_req(OtEDNState *s, OtCSRNGCmdStatus cmd_status)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    c->sw_cmd_status = cmd_status;
+    c->sw_ack = true;
+    s->sw_cmd_ready = cmd_status == CSRNG_STATUS_SUCCESS;
+    s->regs[R_INTR_STATE] |= INTR_EDN_CMD_REQ_DONE_MASK;
+
+    ot_edn_update_irqs(s);
+}
+
+static void ot_edn_handle_sw_cmd_req(OtEDNState *s, uint32_t value)
+{
+    OtEDNCSRNG *c = &s->rng;
+
+    if (!ot_edn_is_sw_cmd_mode(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %u: ignore SW REQ in %s\n",
+                      __func__, c->appid, STATE_NAME(s->state));
+        return;
+    }
+
+    ot_edn_connect_csrng(s);
+
+    c->sw_ack = false;
+
+    trace_ot_edn_push_csrng_command(c->appid, "sw", value);
+    OtCSRNGCmdStatus res = c->csrng->push_command(c->device, c->appid, value);
+    if (res != CSRNG_STATUS_SUCCESS) {
+        xtrace_ot_edn_error(c->appid, "CSRNG rejected command");
+        s->sw_cmd_ready = false;
+        s->regs[R_RECOV_ALERT_STS] |= R_RECOV_ALERT_STS_CSRNG_ACK_ERR_MASK;
+        ot_edn_change_state(s, EDN_REJECT_CSRNG_ENTROPY);
+        ot_edn_complete_sw_req(s, res);
+        ot_edn_update_alerts(s);
+        return;
+    }
+
+    if (s->state == EDN_SW_PORT_MODE) {
+        if (s->sw_cmd_ready) {
+            /*
+             * first word for this command sequence:
+             * 1. value contains the actual command
+             * 2. flag SW command as not ready till the command is completed
+             */
+            s->sw_cmd_ready = false;
+            uint32_t command = FIELD_EX32(value, OT_CSNRG_CMD, ACMD);
+            switch (command) {
+            case OT_CSRNG_CMD_INSTANTIATE:
+            case OT_CSRNG_CMD_RESEED:
+                c->no_fips = false;
+                break;
+            case OT_CSRNG_CMD_GENERATE:
+                c->rem_packet_count = FIELD_EX32(value, OT_CSNRG_CMD, GLEN);
+                xtrace_ot_edn_dinfo(c->appid, "SW generation w/ packets",
+                                    c->rem_packet_count);
+                ot_edn_update_genbits_ready(s);
+                for (unsigned epix = 0; epix < ARRAY_SIZE(s->endpoints);
+                     epix++) {
+                    s->endpoints[epix].gen_count = 0;
+                }
+                break;
+            default:
+                break;
+            }
+        }
+    }
+
+    if (s->state == EDN_AUTO_LOAD_INS) {
+        ot_edn_change_state(s, EDN_AUTO_FIRST_ACK_WAIT);
+    }
+}
+
+static void ot_edn_auto_dispatch(OtEDNState *s)
+{
+    const OtEDNCSRNG *c = &s->rng;
+
+    bool auto_req_mode = ot_edn_is_auto_req_mode(s);
+    trace_ot_edn_auto_dispatch(c->appid, auto_req_mode, s->max_reqs_cnt);
+
+    ot_edn_update_irqs(s);
+
+    if (!auto_req_mode) {
+        ot_edn_change_state(s, EDN_IDLE);
+        ot_edn_reset_replay_fifos(s);
+        ot_edn_update_mode(s);
+        return;
+    }
+
+    if (s->state == EDN_AUTO_DISPATCH) {
+        if (s->max_reqs_cnt == 0) {
+            ot_edn_change_state(s, EDN_AUTO_CAPT_RESEED_CNT);
+            ot_edn_send_auto_reseed_cmd(s);
+            s->max_reqs_cnt = s->regs[R_MAX_NUM_REQS_BETWEEN_RESEEDS];
+        } else {
+            ot_edn_change_state(s, EDN_AUTO_CAPT_GEN_CNT);
+            ot_edn_send_auto_generate_cmd(s);
+        }
+    }
+}
+
+static void ot_edn_fill_bits(void *opaque, const uint32_t *bits, bool fips)
+{
+    OtEDNState *s = opaque;
+    OtEDNCSRNG *c = &s->rng;
+
+    switch (s->state) {
+    case EDN_BOOT_GEN_ACK_WAIT:
+    case EDN_AUTO_ACK_WAIT:
+    case EDN_SW_PORT_MODE:
+        break;
+    default:
+        xtrace_ot_edn_error(c->appid, "unexpected state");
+        s->regs[R_ERR_CODE] |= R_ERR_CODE_EDN_MAIN_SM_ERR_MASK;
+        ot_edn_change_state(s, EDN_ERROR);
+        break;
+    }
+
+    if (!c->rem_packet_count ||
+        ot_fifo32_num_free(&c->bits_fifo) < OT_CSRNG_PACKET_WORD_COUNT) {
+        xtrace_ot_edn_error(c->appid, "unexpected entropy");
+        return;
+    }
+
+    for (unsigned ix = 0; ix < OT_CSRNG_PACKET_WORD_COUNT; ix++) {
+        if (ot_fifo32_is_full(&c->bits_fifo)) {
+            xtrace_ot_edn_error(c->appid, "entropy input fifo overflow");
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_SFIFO_GENCMD_ERR_MASK |
+                                   R_ERR_CODE_FIFO_WRITE_ERR_MASK;
+            s->regs[R_INTR_STATE] |= INTR_EDN_FATAL_ERR_MASK;
+            ot_edn_update_irqs(s);
+            ot_edn_update_alerts(s);
+            return;
+        }
+        ot_fifo32_push(&c->bits_fifo, bits[ix]);
+    }
+    c->rem_packet_count -= 1u;
+    c->no_fips |= !fips;
+
+    trace_ot_edn_fill_bits(c->appid, c->rem_packet_count, fips, !c->no_fips);
+
+    ot_edn_update_genbits_ready(s);
+
+    /* serve any queued enpoints if any */
+    if (!QSIMPLEQ_EMPTY(&s->ep_requests)) {
+        trace_ot_edn_schedule(c->appid, "queued entropy request");
+        qemu_bh_schedule(s->ep_bh);
+    }
+}
+
+static void ot_edn_handle_ep_request(void *opaque)
+{
+    /* called from ep_bh */
+    OtEDNState *s = opaque;
+    OtEDNCSRNG *c = &s->rng;
+
+    while (!QSIMPLEQ_EMPTY(&s->ep_requests)) {
+        OtEDNEndPoint *ep = QSIMPLEQ_FIRST(&s->ep_requests);
+
+        if (!ep->fn) {
+            xtrace_ot_edn_error(c->appid, "no filler function");
+            QSIMPLEQ_REMOVE_HEAD(&s->ep_requests, request);
+            continue;
+        }
+
+        unsigned ep_id = (unsigned)(uintptr_t)(ep - &s->endpoints[0]);
+        trace_ot_edn_handle_ep_request(c->appid, ep_id);
+
+        uint32_t bits;
+        bool available; /* entropy is available in EP unpacker output */
+        if (ot_fifo32_is_empty(&ep->fifo)) {
+            /* if the local packer is empty ... */
+            if (ot_fifo32_num_used(&c->bits_fifo) >=
+                OT_CSRNG_PACKET_WORD_COUNT) {
+                /*
+                 * .... try to refill if from the input entropy FIFO, 128 bits
+                 * at a time, first 32-bit packet is pushed to the EP client,
+                 * remaining 96-bits are stored in the unpacker FIFO
+                 */
+                bits = ot_fifo32_pop(&c->bits_fifo);
+                for (unsigned int ix = 1; ix < OT_CSRNG_PACKET_WORD_COUNT;
+                     ix++) {
+                    ot_fifo32_push(&ep->fifo, ot_fifo32_pop(&c->bits_fifo));
+                }
+                ep->fips = !c->no_fips;
+                available = true;
+                trace_ot_edn_ep_fifo(c->appid, "reload",
+                                     ot_fifo32_num_used(&ep->fifo));
+            } else {
+                /* ... otherwise, the input FIFO being empty, defer handling */
+                available = false;
+                trace_ot_edn_ep_fifo(c->appid, "empty", 0);
+            }
+        } else {
+            bits = ot_fifo32_pop(&ep->fifo);
+            available = true;
+            trace_ot_edn_ep_fifo(c->appid, "pop",
+                                 ot_fifo32_num_used(&ep->fifo));
+        }
+
+        bool refill = ot_edn_update_genbits_ready(s);
+
+        trace_ot_edn_ep_request(c->appid, available, STATE_NAME(s->state),
+                                s->state, refill, c->rem_packet_count);
+
+        if (!available) {
+            break;
+        }
+
+        /* remove the request from the queue only if it has been handled */
+        QSIMPLEQ_REMOVE_HEAD(&s->ep_requests, request);
+
+        /* signal the endpoint with the requested entropy */
+        ep->gen_count += 1u;
+        ep->total_count += 1u;
+        trace_ot_edn_fill_endpoint(c->appid, ep_id, bits, ep->fips,
+                                   ep->gen_count, ep->total_count);
+        (*ep->fn)(ep->opaque, bits, ep->fips);
+    }
+}
+
+static void ot_edn_csrng_ack_irq(void *opaque, int n, int level)
+{
+    OtEDNState *s = opaque;
+    OtEDNCSRNG *c = &s->rng;
+    (void)n;
+
+    trace_ot_edn_csrng_ack(c->appid, STATE_NAME(s->state), level);
+
+    /*
+     * cleaning up the first world would be enough, clearing the whole buffer
+     * help debugging
+     */
+    memset(c->buffer, 0, sizeof(*c->buffer));
+
+    OtCSRNGCmdStatus cmd_status;
+
+    /* NOLINTNEXTLINE */
+    switch (level) {
+    case CSRNG_STATUS_SUCCESS:
+    case CSRNG_STATUS_INVALID_ACMD:
+    case CSRNG_STATUS_INVALID_GEN_CMD:
+    case CSRNG_STATUS_INVALID_CMD_SEQ:
+    case CSRNG_STATUS_RESEED_CNT_EXCEEDED:
+        cmd_status = (OtCSRNGCmdStatus)level;
+        break;
+    default:
+        qemu_log("%s: unexpected CSRNG ack value: %d\n", __func__, level);
+        g_assert_not_reached();
+        return;
+    }
+
+    if (cmd_status != CSRNG_STATUS_SUCCESS) {
+        trace_ot_edn_push_csrng_error(c->appid, level);
+        if (s->state != EDN_ERROR) {
+            ot_edn_change_state(s, EDN_REJECT_CSRNG_ENTROPY);
+        }
+    }
+
+    switch (s->state) {
+    case EDN_BOOT_INS_ACK_WAIT:
+        ot_edn_change_state(s, EDN_BOOT_LOAD_GEN);
+        ot_edn_send_boot_req(s, R_BOOT_GEN_CMD);
+        c->hw_cmd_status = cmd_status;
+        break;
+    case EDN_BOOT_GEN_ACK_WAIT:
+        ot_edn_change_state(s, EDN_BOOT_PULSE);
+        ot_edn_change_state(s, EDN_BOOT_DONE);
+        c->hw_cmd_status = cmd_status;
+        ot_edn_update_mode(s);
+        break;
+    case EDN_BOOT_UNI_ACK_WAIT:
+        ot_edn_reset_replay_fifos(s);
+        ot_edn_change_state(s, EDN_IDLE);
+        c->hw_cmd_status = cmd_status;
+        ot_edn_update_mode(s);
+        break;
+    case EDN_AUTO_FIRST_ACK_WAIT:
+        ot_edn_change_state(s, EDN_AUTO_DISPATCH);
+        ot_edn_complete_sw_req(s, cmd_status);
+        ot_edn_auto_dispatch(s);
+        break;
+    case EDN_AUTO_ACK_WAIT:
+        ot_edn_change_state(s, EDN_AUTO_DISPATCH);
+        c->hw_cmd_status = cmd_status;
+        ot_edn_auto_dispatch(s);
+        break;
+    case EDN_SW_PORT_MODE:
+        ot_edn_complete_sw_req(s, cmd_status);
+        break;
+    default:
+        break;
+    }
+}
+
+static uint64_t ot_edn_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtEDNState *s = opaque;
+    OtEDNCSRNG *c = &s->rng;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_REGWEN:
+    case R_CTRL:
+    case R_BOOT_INS_CMD:
+    case R_BOOT_GEN_CMD:
+    case R_MAX_NUM_REQS_BETWEEN_RESEEDS:
+    case R_RECOV_ALERT_STS:
+    case R_ERR_CODE:
+    case R_ERR_CODE_TEST:
+        val32 = s->regs[reg];
+        break;
+    case R_HW_CMD_STS:
+        val32 = FIELD_DP32(0u, HW_CMD_STS, BOOT_MODE, ot_edn_is_boot_mode(s));
+        val32 =
+            FIELD_DP32(val32, HW_CMD_STS, AUTO_MODE, ot_edn_is_auto_mode(s));
+        val32 =
+            FIELD_DP32(val32, HW_CMD_STS, CMD_TYPE, (uint32_t)c->hw_cmd_type);
+        val32 = FIELD_DP32(val32, HW_CMD_STS, CMD_ACK, c->hw_ack);
+        val32 = FIELD_DP32(val32, HW_CMD_STS, CMD_STS, c->hw_cmd_status);
+        break;
+    case R_SW_CMD_STS:
+        val32 =
+            FIELD_DP32(0u, SW_CMD_STS, CMD_REG_RDY, ot_edn_is_cmd_reg_rdy(s));
+        val32 = FIELD_DP32(val32, SW_CMD_STS, CMD_RDY, ot_edn_is_cmd_rdy(s));
+        val32 = FIELD_DP32(val32, SW_CMD_STS, CMD_ACK, c->sw_ack);
+        val32 = FIELD_DP32(val32, SW_CMD_STS, CMD_STS, c->sw_cmd_status);
+        break;
+    case R_MAIN_SM_STATE:
+        switch (s->state) {
+        case EDN_IDLE ... EDN_ERROR:
+            val32 = OtEDNFsmStateCode[s->state];
+            break;
+        default:
+            val32 = OtEDNFsmStateCode[EDN_ERROR];
+            break;
+        }
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+    case R_SW_CMD_REQ:
+    case R_RESEED_CMD:
+    case R_GENERATE_CMD:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_edn_io_read_out(s->rng.appid, (uint32_t)addr, REG_NAME(reg), val32,
+                             pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_edn_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                              unsigned size)
+{
+    OtEDNState *s = opaque;
+    OtEDNCSRNG *c = &s->rng;
+    uint32_t val32 = (uint32_t)val64;
+    (void)size;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_edn_io_write(c->appid, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_edn_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[reg] = val32;
+        ot_edn_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] |= val32;
+        ot_edn_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        s->regs[R_ALERT_TEST] = val32;
+        ot_edn_update_alerts(s);
+        break;
+    case R_REGWEN:
+        val32 &= R_REGWEN_EN_MASK;
+        s->regs[reg] &= val32;
+        break;
+    case R_CTRL:
+        if (!s->regs[R_REGWEN]) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "Cannot change CTRL, REGWEN disabled");
+            break;
+        }
+        val32 &= CTRL_MASK;
+        ot_edn_handle_ctrl(s, val32);
+        break;
+    case R_BOOT_INS_CMD:
+    case R_BOOT_GEN_CMD:
+        s->regs[reg] = val32;
+        break;
+    case R_SW_CMD_REQ:
+        ot_edn_handle_sw_cmd_req(s, val32);
+        break;
+    case R_RESEED_CMD:
+        if (ot_fifo32_is_full(&c->cmd_reseed_fifo)) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_SFIFO_RESCMD_ERR_MASK;
+            ot_edn_update_alerts(s);
+        } else {
+            ot_fifo32_push(&c->cmd_reseed_fifo, val32);
+        }
+        break;
+    case R_GENERATE_CMD:
+        if (ot_fifo32_is_full(&c->cmd_gen_fifo)) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_SFIFO_GENCMD_ERR_MASK;
+            ot_edn_update_alerts(s);
+        } else {
+            xtrace_ot_edn_xinfo(c->appid, "PUSH GEN CMD", val32);
+            ot_fifo32_push(&c->cmd_gen_fifo, val32);
+        }
+        break;
+    case R_MAX_NUM_REQS_BETWEEN_RESEEDS:
+        s->regs[reg] = val32;
+        s->max_reqs_cnt = val32;
+        break;
+    case R_RECOV_ALERT_STS:
+        val32 &= RECOV_ALERT_STS_MASK;
+        s->regs[reg] &= val32; /* rw0c */
+        s->recov_alert_sts &= val32;
+        ot_edn_update_alerts(s);
+        break;
+    case R_ERR_CODE_TEST:
+        val32 &= R_ERR_CODE_TEST_VAL_MASK;
+        s->regs[reg] = val32;
+        if ((1u << val32) & ERR_CODE_ACTIVE_MASK) {
+            if (s->state != EDN_ERROR) {
+                s->regs[R_ERR_CODE] |= 1u << val32;
+                ot_edn_change_state(s, EDN_ERROR);
+            }
+        }
+        ot_edn_update_irqs(s);
+        ot_edn_update_alerts(s);
+        break;
+    case R_SW_CMD_STS:
+    case R_ERR_CODE:
+    case R_MAIN_SM_STATE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+};
+
+static const Property ot_edn_properties[] = {
+    DEFINE_PROP_LINK("csrng", OtEDNState, rng.device, TYPE_OT_CSRNG,
+                     OtCSRNGState *),
+    DEFINE_PROP_UINT32("csrng-app", OtEDNState, rng.appid, UINT32_MAX),
+};
+
+static const MemoryRegionOps ot_edn_regs_ops = {
+    .read = &ot_edn_regs_read,
+    .write = &ot_edn_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_edn_reset_enter(Object *obj, ResetType type)
+{
+    OtEDNClass *c = OT_EDN_GET_CLASS(obj);
+    OtEDNState *s = OT_EDN(obj);
+    OtEDNCSRNG *r = &s->rng;
+
+    trace_ot_edn_reset(s->rng.appid, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    qemu_bh_cancel(s->ep_bh);
+
+    memset(s->regs, 0, REGS_SIZE);
+    s->regs[R_REGWEN] = 0x1u;
+    s->regs[R_CTRL] = 0x9999u;
+    s->regs[R_BOOT_INS_CMD] = 0x901u;
+    s->regs[R_BOOT_GEN_CMD] = 0xfff003u;
+
+    ot_edn_clean_up(s, true);
+    ot_edn_change_state(s, EDN_IDLE);
+
+    /* do not reset connection info since reset order is not known */
+    (void)r->genbits_ready;
+    ot_fifo32_reset(&r->cmd_gen_fifo);
+    ot_fifo32_reset(&r->cmd_reseed_fifo);
+}
+
+static void ot_edn_realize(DeviceState *dev, Error **errp)
+{
+    OtEDNState *s = OT_EDN(dev);
+    OtEDNCSRNG *r = &s->rng;
+
+    (void)errp;
+
+    /* check that properties have been initialized */
+    g_assert(r->device);
+    g_assert(r->appid < OT_CSRNG_HW_APP_MAX);
+    r->csrng = OT_CSRNG_GET_CLASS(r->device);
+    g_assert(r->csrng->connect_hw_app);
+    g_assert(r->csrng->push_command);
+}
+
+static void ot_edn_init(Object *obj)
+{
+    OtEDNState *s = OT_EDN(obj);
+    OtEDNCSRNG *c = &s->rng;
+
+    memory_region_init_io(&s->mmio, obj, &ot_edn_regs_ops, s, TYPE_OT_EDN,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+    qdev_init_gpio_in_named_with_opaque(DEVICE(s), &ot_edn_csrng_ack_irq, s,
+                                        TYPE_OT_EDN "-req_sts", 1);
+
+    s->ep_bh = qemu_bh_new(&ot_edn_handle_ep_request, s);
+
+    ot_fifo32_create(&c->bits_fifo, OT_CSRNG_PACKET_WORD_COUNT * 2u);
+    ot_fifo32_create(&c->cmd_gen_fifo, OT_CSRNG_CMD_WORD_MAX);
+    ot_fifo32_create(&c->cmd_reseed_fifo, OT_CSRNG_CMD_WORD_MAX);
+
+    for (unsigned epix = 0; epix < ARRAY_SIZE(s->endpoints); epix++) {
+        memset(&s->endpoints[epix], 0, sizeof(OtEDNEndPoint));
+        ot_fifo32_create(&s->endpoints[epix].fifo, OT_CSRNG_PACKET_WORD_COUNT);
+    }
+
+    QSIMPLEQ_INIT(&s->ep_requests);
+}
+
+static void ot_edn_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_edn_realize;
+    device_class_set_props(dc, ot_edn_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtEDNClass *ec = OT_EDN_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_edn_reset_enter, NULL, NULL,
+                                       &ec->parent_phases);
+}
+
+static const TypeInfo ot_edn_info = {
+    .name = TYPE_OT_EDN,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtEDNState),
+    .instance_init = &ot_edn_init,
+    .class_size = sizeof(OtEDNClass),
+    .class_init = &ot_edn_class_init,
+};
+
+static void ot_edn_register_types(void)
+{
+    type_register_static(&ot_edn_info);
+}
+
+type_init(ot_edn_register_types);
diff --git a/hw/opentitan/ot_eg_pad_ring.c b/hw/opentitan/ot_eg_pad_ring.c
new file mode 100644
index 0000000000000..61c05219a5771
--- /dev/null
+++ b/hw/opentitan/ot_eg_pad_ring.c
@@ -0,0 +1,205 @@
+/*
+ * QEMU OpenTitan Earlgrey Pad Ring device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This device currently only implements the Power-on-Reset (POR) pad, and does
+ * not support any of the Muxed IO pads.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_eg_pad_ring.h"
+#include "hw/opentitan/ot_rstmgr.h"
+#include "hw/qdev-properties.h"
+#include "hw/riscv/ibex_gpio.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+struct OtEgPadRingState {
+    DeviceState parent_obj;
+
+    IbexIRQ outputs[OT_EG_PAD_RING_PAD_COUNT];
+    IbexIRQ por; /* Separate PoR IRQ to send the correct rstmgr reset req */
+
+    ibex_gpio default_levels[OT_EG_PAD_RING_PAD_COUNT];
+
+    /* properties */
+    char *ot_id;
+};
+
+struct OtEgPadRingClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static const ibex_gpio DEFAULT_LEVELS[OT_EG_PAD_RING_PAD_COUNT] = {
+    [OT_EG_PAD_RING_PAD_POR_N] = IBEX_GPIO_PULL_UP,
+};
+
+#define PAD_NAME_ENTRY(_pad_) [OT_EG_PAD_RING_PAD_##_pad_] = stringify(_pad_)
+static const char *PAD_NAMES[] = {
+    /* clang-format off */
+    PAD_NAME_ENTRY(POR_N),
+    /* clang-format on */
+};
+#define PAD_NAME(_pad_) \
+    ((((_pad_) < ARRAY_SIZE(PAD_NAMES)) && PAD_NAMES[_pad_]) ? \
+         PAD_NAMES[_pad_] : \
+         "?")
+
+static void ot_eg_pad_ring_por_update(OtEgPadRingState *s)
+{
+    int level = ibex_irq_get_level(&s->outputs[OT_EG_PAD_RING_PAD_POR_N]);
+    bool blevel = ibex_gpio_level(level);
+
+    /**
+     * @todo: The current implementation directly invokes a rstmgr reset req
+     * on a falling edge on the PoR pad. In reality, this pin can be held high
+     * which should hold the device in reset, but this is not currently
+     * supported via the rstmgr interface. Hence, if the host wishes to rely on
+     * holding the device in reset, it must stop the VM when setting PoR high &
+     * later resume when setting it low again.
+     */
+    if (ibex_gpio_is_hiz(level) || blevel) {
+        return;
+    }
+
+    ibex_irq_set(&s->por, OT_RSTMGR_RESET_POR);
+}
+
+static const Property ot_eg_pad_ring_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtEgPadRingState, ot_id),
+};
+
+static void ot_eg_pad_ring_reset_enter(Object *obj, ResetType type)
+{
+    OtEgPadRingClass *c = OT_EG_PAD_RING_GET_CLASS(obj);
+    OtEgPadRingState *s = OT_EG_PAD_RING(obj);
+
+    trace_ot_eg_pad_ring_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    for (unsigned ix = 0; ix < OT_EG_PAD_RING_PAD_COUNT; ix++) {
+        /* POR may cause and thus should be maintained through reset */
+        if (ix != OT_EG_PAD_RING_PAD_POR_N) {
+            /* current pad outputs should be cleared (Hi-Z) upon reset */
+            ibex_irq_set(&s->outputs[ix], IBEX_GPIO_HIZ);
+        }
+    }
+
+    /* Reset the dedicated PoR signal */
+    ibex_irq_set(&s->por, 0);
+}
+
+static void ot_eg_pad_ring_reset_exit(Object *obj, ResetType type)
+{
+    OtEgPadRingClass *c = OT_EG_PAD_RING_GET_CLASS(obj);
+    OtEgPadRingState *s = OT_EG_PAD_RING(obj);
+
+    trace_ot_eg_pad_ring_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    for (unsigned ix = 0; ix < OT_EG_PAD_RING_PAD_COUNT; ix++) {
+        trace_ot_eg_pad_ring_reset_value(s->ot_id, PAD_NAME(ix),
+                                         ibex_gpio_repr(s->default_levels[ix]));
+        ibex_irq_set(&s->outputs[ix], s->default_levels[ix]);
+    }
+
+    /* Handle special cases where dedicated output signals are used */
+    ot_eg_pad_ring_por_update(s);
+}
+
+static void ot_eg_pad_ring_realize(DeviceState *dev, Error **errp)
+{
+    OtEgPadRingState *s = OT_EG_PAD_RING(dev);
+    (void)errp;
+
+    ibex_qdev_init_irqs_default(OBJECT(dev), s->outputs,
+                                OT_EG_PAD_RING_PAD_EGRESS,
+                                OT_EG_PAD_RING_PAD_COUNT, -1);
+}
+
+static void ot_eg_pad_ring_init(Object *obj)
+{
+    OtEgPadRingState *s = OT_EG_PAD_RING(obj);
+
+    ibex_qdev_init_irq(obj, &s->por, OT_EG_PAD_RING_POR_REQ);
+
+    for (unsigned ix = 0; ix < OT_EG_PAD_RING_PAD_COUNT; ix++) {
+        gchar *pad_name = g_ascii_strdown(PAD_NAME(ix), -1);
+        s->default_levels[ix] = DEFAULT_LEVELS[ix];
+        object_property_add_ibex_gpio(obj, pad_name, &s->default_levels[ix]);
+        g_free(pad_name);
+    }
+}
+
+static void ot_eg_pad_ring_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_eg_pad_ring_realize;
+    device_class_set_props(dc, ot_eg_pad_ring_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    /*
+     * Implement the resettable interface to ensure the package configuration is
+     * forwarded to the PinMux/GPIO on each reset sequence (this is not yet used
+     * in Earlgrey, but is added for future-proofing).
+     * The enter stage fully reinitializes the package config to HiZ default
+     * values, and the exit stage pushes the actual package configuration to the
+     * connected pinmux/IOs.
+     */
+    ResettableClass *rc = RESETTABLE_CLASS(dc);
+    OtEgPadRingClass *pc = OT_EG_PAD_RING_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_eg_pad_ring_reset_enter, NULL,
+                                       &ot_eg_pad_ring_reset_exit,
+                                       &pc->parent_phases);
+}
+
+static const TypeInfo ot_eg_pad_ring_info = {
+    .name = TYPE_OT_EG_PAD_RING,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(OtEgPadRingState),
+    .instance_init = &ot_eg_pad_ring_init,
+    .class_init = &ot_eg_pad_ring_class_init,
+    .class_size = sizeof(OtEgPadRingClass)
+};
+
+static void ot_eg_pad_ring_register_types(void)
+{
+    type_register_static(&ot_eg_pad_ring_info);
+}
+
+type_init(ot_eg_pad_ring_register_types);
diff --git a/hw/opentitan/ot_entropy_src.c b/hw/opentitan/ot_entropy_src.c
new file mode 100644
index 0000000000000..3acb7936a1335
--- /dev/null
+++ b/hw/opentitan/ot_entropy_src.c
@@ -0,0 +1,1982 @@
+/*
+ * QEMU OpenTitan Entropy Source device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Notes:
+ * - missing correct handling of ALERT_FAIL_COUNTS, currently never incremented.
+ * - missing some error handling? ES_MAIN_SM_ERR is the only error that can be
+ *   triggered.
+ *
+ * v2: based on OpenTitan 011b6ea1fe
+ * v3: based on OpenTitan 5fe6fe8605
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_entropy_src.h"
+#include "hw/opentitan/ot_fifo32.h"
+#include "hw/opentitan/ot_noise_src.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "tomcrypt.h"
+#include "trace.h"
+
+
+#define NUM_ALERTS          2u
+#define NUM_IRQS            4u
+#define DISTR_FIFO_V2_DEPTH 2u
+#define DISTR_FIFO_V3_DEPTH 3u
+#define ES_FIFO_DEPTH       3u
+#define OBSERVE_FIFO_DEPTH  32u
+/* only in v3 */
+#define RNG_BUS_WIDTH            4u
+#define RNG_BUS_BIT_SEL_WIDTH    2u
+#define HEALTH_TEST_WINDOW_WIDTH 18u
+
+/*
+ * Note about the register split into different groups:
+ * ENTROPY_SRC module is supported in two variants, v2 and v3
+ * There are very similar, but unfortunately v2 introduces a "version register"
+ * which has been subsequently removed in v3, and this register is inserted
+ * between other registers. This cause the address of all the subsequent
+ * registers that follow to shift down 4 bytes. In order for QEMU to support
+ * both versions with the same implementation, registers are therefore split
+ * into two groups, called "lo" and "hi", which are located on each side of
+ * the deprecated REV register. The register groups are mapped using two
+ * different memory regions, in order to simplify support for both versions.
+ *
+ * There are a couple of register bitfields that also differ between versions,
+ * namely the CONF and RECOV_ALERT_STS register, whose handling is specific
+ * to the instantiated module version.
+ */
+
+/* clang-format off */
+
+/* first group of registers, "lo" */
+REG32(INTR_STATE, 0x00u)
+    SHARED_FIELD(INTR_ES_ENTROPY_VALID, 0u, 1u)
+    SHARED_FIELD(INTR_ES_HEALTH_TEST_FAILED, 1u, 1u)
+    SHARED_FIELD(INTR_ES_OBSERVE_FIFO_READY, 2u, 1u)
+    SHARED_FIELD(INTR_ES_FATAL_ERR, 3u, 1u)
+REG32(INTR_ENABLE, 0x04u)
+REG32(INTR_TEST, 0x08u)
+REG32(ALERT_TEST, 0x0cu)
+    FIELD(ALERT_TEST, RECOV_ALERT, 0u, 1u)
+    FIELD(ALERT_TEST, FATAL_ALERT, 1u, 1u)
+REG32(ME_REGWEN, 0x10u)
+    FIELD(ME_REGWEN, EN, 0u, 1u)
+REG32(SW_REGUPD, 0x14u)
+    FIELD(SW_REGUPD, VAL, 0u, 1u)
+REG32(REGWEN, 0x18u)
+    FIELD(REGWEN, EN, 0u, 1u)
+
+/* second group of registers, "rev", only used with v2 */
+REG32(REV, 0x00u)
+    FIELD(REV, ABI_REVISION, 0u, 8u)
+    FIELD(REV, HW_REVISION, 8u, 8u)
+    FIELD(REV, CHIP_TYPE, 16u, 8u)
+
+/* third group of registers, "hi" */
+REG32(MODULE_ENABLE, 0x00u)
+    FIELD(MODULE_ENABLE, MODULE_ENABLE, 0u, 4u)
+REG32(CONF, 0x04u)
+    /* common bitfields for all versions */
+    FIELD(CONF, FIPS_ENABLE, 0u, 4u)
+    FIELD(CONF, FIPS_FLAG, 4u, 4u)
+    FIELD(CONF, RNG_FIPS, 8u, 4u)
+    FIELD(CONF, RNG_BIT_ENABLE, 12u, 4u)
+    /* bitfields only defined on version 2 */
+    FIELD(CONF, V2_RNG_BIT_SEL, 16u, 2u)
+    FIELD(CONF, V2_THRESHOLD_SCOPE, 18u, 4u)
+    FIELD(CONF, V2_ENTROPY_DATA_REG_ENABLE, 22u, 4u)
+    /* bitfields only defined on for version 3 */
+    FIELD(CONF, V3_THRESHOLD_SCOPE, 16u, 4u)
+    FIELD(CONF, V3_ENTROPY_DATA_REG_ENABLE, 20u, 4u)
+    FIELD(CONF, V3_RNG_BIT_SEL, 24u, 8u)
+REG32(ENTROPY_CONTROL, 0x08u)
+    FIELD(ENTROPY_CONTROL, ES_ROUTE, 0u, 4u)
+    FIELD(ENTROPY_CONTROL, ES_TYPE, 4u, 4u)
+REG32(ENTROPY_DATA, 0x0cu)
+REG32(HEALTH_TEST_WINDOWS, 0x10u)
+    FIELD(HEALTH_TEST_WINDOWS, FIPS_WINDOW, 0u, 16u)
+    FIELD(HEALTH_TEST_WINDOWS, BYPASS_WINDOW, 16u, 16u)
+REG32(REPCNT_THRESHOLDS, 0x14u)
+    SHARED_FIELD(THRESHOLDS_FIPS, 0u, 16u)
+    SHARED_FIELD(THRESHOLDS_BYPASS, 16u, 16u)
+REG32(REPCNTS_THRESHOLDS, 0x18u)
+REG32(ADAPTP_HI_THRESHOLDS, 0x1cu)
+REG32(ADAPTP_LO_THRESHOLDS, 0x20u)
+REG32(BUCKET_THRESHOLDS, 0x24u)
+REG32(MARKOV_HI_THRESHOLDS, 0x28u)
+REG32(MARKOV_LO_THRESHOLDS, 0x2cu)
+REG32(EXTHT_HI_THRESHOLDS, 0x30u)
+REG32(EXTHT_LO_THRESHOLDS, 0x34u)
+REG32(REPCNT_HI_WATERMARKS, 0x38u)
+    SHARED_FIELD(WATERMARK_FIPS, 0u, 16u)
+    SHARED_FIELD(WATERMARK_BYPASS, 16u, 16u)
+REG32(REPCNTS_HI_WATERMARKS, 0x3cu)
+REG32(ADAPTP_HI_WATERMARKS, 0x40u)
+REG32(ADAPTP_LO_WATERMARKS, 0x44u)
+REG32(EXTHT_HI_WATERMARKS, 0x48u)
+REG32(EXTHT_LO_WATERMARKS, 0x4cu)
+REG32(BUCKET_HI_WATERMARKS, 0x50u)
+REG32(MARKOV_HI_WATERMARKS, 0x54u)
+REG32(MARKOV_LO_WATERMARKS, 0x58u)
+REG32(REPCNT_TOTAL_FAILS, 0x5cu)
+REG32(REPCNTS_TOTAL_FAILS, 0x60u)
+REG32(ADAPTP_HI_TOTAL_FAILS, 0x64u)
+REG32(ADAPTP_LO_TOTAL_FAILS, 0x68u)
+REG32(BUCKET_TOTAL_FAILS, 0x6cu)
+REG32(MARKOV_HI_TOTAL_FAILS, 0x70u)
+REG32(MARKOV_LO_TOTAL_FAILS, 0x74u)
+REG32(EXTHT_HI_TOTAL_FAILS, 0x78u)
+REG32(EXTHT_LO_TOTAL_FAILS, 0x7cu)
+REG32(ALERT_THRESHOLD, 0x80u)
+    FIELD(ALERT_THRESHOLD, VAL, 0u, 16u)
+    FIELD(ALERT_THRESHOLD, INV, 16u, 16u)
+REG32(ALERT_SUMMARY_FAIL_COUNTS, 0x84u)
+    FIELD(ALERT_SUMMARY_FAIL_COUNTS, ANY_FAIL_COUNT, 0u, 16u)
+REG32(ALERT_FAIL_COUNTS, 0x88u)
+    FIELD(ALERT_FAIL_COUNTS, REPCNT_FAIL_COUNT, 4u, 4u)
+    FIELD(ALERT_FAIL_COUNTS, ADAPTP_HI_FAIL_COUNT, 8u, 4u)
+    FIELD(ALERT_FAIL_COUNTS, ADAPTP_LO_FAIL_COUNT, 12u, 4u)
+    FIELD(ALERT_FAIL_COUNTS, BUCKET_FAIL_COUNT, 16u, 4u)
+    FIELD(ALERT_FAIL_COUNTS, MARKOV_HI_FAIL_COUNT, 20u, 4u)
+    FIELD(ALERT_FAIL_COUNTS, MARKOV_LO_FAIL_COUNT, 24u, 4u)
+    FIELD(ALERT_FAIL_COUNTS, REPCNTS_FAIL_COUNT, 28u, 4u)
+REG32(EXTHT_FAIL_COUNTS, 0x8cu)
+    FIELD(EXTHT_FAIL_COUNTS, EXTHT_HI_FAIL_COUNT, 0u, 4u)
+    FIELD(EXTHT_FAIL_COUNTS, EXTHT_LO_FAIL_COUNT, 4u, 4u)
+REG32(FW_OV_CONTROL, 0x90u)
+    FIELD(FW_OV_CONTROL, FW_OV_MODE, 0u, 4u)
+    FIELD(FW_OV_CONTROL, FW_OV_ENTROPY_INSERT, 4u, 4u)
+REG32(FW_OV_SHA3_START, 0x94u)
+    FIELD(FW_OV_SHA3_START, FW_OV_INSERT_START, 0u, 4u)
+REG32(FW_OV_WR_FIFO_FULL, 0x98u)
+    FIELD(FW_OV_WR_FIFO_FULL, VAL, 0u, 1u)
+REG32(FW_OV_RD_FIFO_OVERFLOW, 0x9cu)
+    FIELD(FW_OV_RD_FIFO_OVERFLOW, VAL, 0u, 1u)
+REG32(FW_OV_RD_DATA, 0xa0u)
+REG32(FW_OV_WR_DATA, 0xa4u)
+REG32(OBSERVE_FIFO_THRESH, 0xa8u)
+    FIELD(OBSERVE_FIFO_THRESH, VAL, 0u, 6u)
+REG32(OBSERVE_FIFO_DEPTH, 0xacu)
+    FIELD(OBSERVE_FIFO_DEPTH, VAL, 0u, 6u)
+REG32(DEBUG_STATUS, 0xb0u)
+    FIELD(DEBUG_STATUS, ENTROPY_FIFO_DEPTH, 0u, 2u)
+    FIELD(DEBUG_STATUS, SHA3_FSM, 3u, 3u)
+    FIELD(DEBUG_STATUS, SHA3_BLOCK_PR, 6u, 1u)
+    FIELD(DEBUG_STATUS, SHA3_SQUEEZING, 7u, 1u)
+    FIELD(DEBUG_STATUS, SHA3_ABSORBED, 8u, 1u)
+    FIELD(DEBUG_STATUS, SHA3_ERR, 9u, 1u)
+    FIELD(DEBUG_STATUS, MAIN_SM_IDLE, 16u, 1u)
+    FIELD(DEBUG_STATUS, MAIN_SM_BOOT_DONE, 17u, 1u)
+REG32(RECOV_ALERT_STS, 0xb4u)
+    FIELD(RECOV_ALERT_STS, FIPS_ENABLE_FIELD_ALERT, 0u, 1u)
+    FIELD(RECOV_ALERT_STS, ENTROPY_DATA_REG_ENABLE_FIELD_ALERT, 1u, 1u)
+    FIELD(RECOV_ALERT_STS, MODULE_ENABLE_FIELD_ALERT, 2u, 1u)
+    FIELD(RECOV_ALERT_STS, THRESHOLD_SCOPE_FIELD_ALERT, 3u, 1u)
+    FIELD(RECOV_ALERT_STS, RNG_BIT_ENABLE_FIELD_ALERT, 5u, 1u)
+    FIELD(RECOV_ALERT_STS, FW_OV_SHA3_START_FIELD_ALERT, 7u, 1u)
+    FIELD(RECOV_ALERT_STS, FW_OV_MODE_FIELD_ALERT, 8u, 1u)
+    FIELD(RECOV_ALERT_STS, FW_OV_ENTROPY_INSERT_FIELD_ALERT, 9u, 1u)
+    FIELD(RECOV_ALERT_STS, ES_ROUTE_FIELD_ALERT, 10u, 1u)
+    FIELD(RECOV_ALERT_STS, ES_TYPE_FIELD_ALERT, 11u, 1u)
+    FIELD(RECOV_ALERT_STS, ES_MAIN_SM_ALERT, 12u, 1u)
+    FIELD(RECOV_ALERT_STS, ES_BUS_CMP_ALERT, 13u, 1u)
+    FIELD(RECOV_ALERT_STS, ES_THRESH_CFG_ALERT, 14u, 1u)
+    FIELD(RECOV_ALERT_STS, ES_FW_OV_WR_ALERT, 15u, 1u)
+    FIELD(RECOV_ALERT_STS, ES_FW_OV_DISABLE_ALERT, 16u, 1u)
+    FIELD(RECOV_ALERT_STS, FIPS_FLAG_FIELD_ALERT, 17u, 1u)
+    FIELD(RECOV_ALERT_STS, RNG_FIPS_FIELD_ALERT, 18u, 1u)
+    FIELD(RECOV_ALERT_STS, POSTHT_ENTROPY_DROP_ALERT, 31u, 1u)
+REG32(ERR_CODE, 0xb8u)
+    FIELD(ERR_CODE, SFIFO_ESRNG_ERR, 0u, 1u)
+    FIELD(ERR_CODE, SFIFO_DISTR_ERR, 1u, 1u)
+    FIELD(ERR_CODE, SFIFO_OBSERVE_ERR, 2u, 1u)
+    FIELD(ERR_CODE, SFIFO_ESFINAL_ERR, 3u, 1u)
+    FIELD(ERR_CODE, ES_ACK_SM_ERR, 20u, 1u)
+    FIELD(ERR_CODE, ES_MAIN_SM_ERR, 21u, 1u)
+    FIELD(ERR_CODE, ES_CNTR_ERR, 22u, 1u)
+    FIELD(ERR_CODE, SHA3_STATE_ERR, 23u, 1u)
+    FIELD(ERR_CODE, SHA3_RST_STORAGE_ERR, 24u, 1u)
+    FIELD(ERR_CODE, FIFO_WRITE_ERR, 28u, 1u)
+    FIELD(ERR_CODE, FIFO_READ_ERR, 29u, 1u)
+    FIELD(ERR_CODE, FIFO_STATE_ERR, 30u, 1u)
+REG32(ERR_CODE_TEST, 0xbcu)
+    FIELD(ERR_CODE_TEST, VAL, 0u, 5u)
+REG32(MAIN_SM_STATE, 0xc0u)
+    FIELD(MAIN_SM_STATE, VAL, 0u, 9u)
+/* clang-format on */
+
+#define INTR_WMASK \
+    (INTR_ES_ENTROPY_VALID_MASK | INTR_ES_HEALTH_TEST_FAILED_MASK | \
+     INTR_ES_OBSERVE_FIFO_READY_MASK | INTR_ES_FATAL_ERR_MASK)
+#define ALERT_TEST_WMASK \
+    (R_ALERT_TEST_RECOV_ALERT_MASK | R_ALERT_TEST_FATAL_ALERT_MASK)
+#define CONF_V2_WMASK \
+    (R_CONF_FIPS_ENABLE_MASK | R_CONF_FIPS_FLAG_MASK | R_CONF_RNG_FIPS_MASK | \
+     R_CONF_RNG_BIT_ENABLE_MASK | R_CONF_V2_RNG_BIT_SEL_MASK | \
+     R_CONF_V2_THRESHOLD_SCOPE_MASK | R_CONF_V2_ENTROPY_DATA_REG_ENABLE_MASK)
+#define CONF_V3_WMASK UINT32_MAX
+#define ENTROPY_CONTROL_WMASK \
+    (R_ENTROPY_CONTROL_ES_ROUTE_MASK | R_ENTROPY_CONTROL_ES_TYPE_MASK)
+#define FW_OV_CONTROL_WMASK \
+    (R_FW_OV_CONTROL_FW_OV_MODE_MASK | \
+     R_FW_OV_CONTROL_FW_OV_ENTROPY_INSERT_MASK)
+#define RECOV_ALERT_STS_WMASK \
+    (R_RECOV_ALERT_STS_FIPS_ENABLE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_ENTROPY_DATA_REG_ENABLE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_MODULE_ENABLE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_THRESHOLD_SCOPE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_RNG_BIT_ENABLE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_FW_OV_SHA3_START_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_FW_OV_MODE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_FW_OV_ENTROPY_INSERT_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_ES_ROUTE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_ES_TYPE_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_ES_MAIN_SM_ALERT_MASK | \
+     R_RECOV_ALERT_STS_ES_BUS_CMP_ALERT_MASK | \
+     R_RECOV_ALERT_STS_ES_THRESH_CFG_ALERT_MASK | \
+     R_RECOV_ALERT_STS_ES_FW_OV_WR_ALERT_MASK | \
+     R_RECOV_ALERT_STS_ES_FW_OV_DISABLE_ALERT_MASK | \
+     R_RECOV_ALERT_STS_FIPS_FLAG_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_RNG_FIPS_FIELD_ALERT_MASK | \
+     R_RECOV_ALERT_STS_POSTHT_ENTROPY_DROP_ALERT_MASK)
+#define ERR_CODE_MASK \
+    (R_ERR_CODE_SFIFO_ESRNG_ERR_MASK | R_ERR_CODE_SFIFO_DISTR_ERR_MASK | \
+     R_ERR_CODE_SFIFO_OBSERVE_ERR_MASK | R_ERR_CODE_SFIFO_ESFINAL_ERR_MASK | \
+     R_ERR_CODE_ES_ACK_SM_ERR_MASK | R_ERR_CODE_ES_MAIN_SM_ERR_MASK | \
+     R_ERR_CODE_ES_CNTR_ERR_MASK | R_ERR_CODE_SHA3_STATE_ERR_MASK | \
+     R_ERR_CODE_SHA3_RST_STORAGE_ERR_MASK | R_ERR_CODE_FIFO_WRITE_ERR_MASK | \
+     R_ERR_CODE_FIFO_READ_ERR_MASK | R_ERR_CODE_FIFO_STATE_ERR_MASK)
+#define ERR_CODE_FATAL_ERROR_MASK \
+    (R_ERR_CODE_ES_ACK_SM_ERR_MASK | R_ERR_CODE_ES_MAIN_SM_ERR_MASK | \
+     R_ERR_CODE_ES_CNTR_ERR_MASK | R_ERR_CODE_SHA3_STATE_ERR_MASK | \
+     R_ERR_CODE_SHA3_RST_STORAGE_ERR_MASK)
+
+/*
+ * this is an alias for the CHECK_MULTIBOOT macro, as the RECOV_ALERT_STS
+ * bit for the FW_OV_SHA3_START register is the only register bit that does
+ * not follow the same naming as its relative register
+ * */
+#define R_RECOV_ALERT_STS_FW_OV_INSERT_START_FIELD_ALERT_SHIFT \
+    R_RECOV_ALERT_STS_FW_OV_SHA3_START_FIELD_ALERT_SHIFT
+
+#define ALERT_STATUS_BIT(_x_) R_RECOV_ALERT_STS_##_x_##_FIELD_ALERT_SHIFT
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_LO_REG (R_REGWEN)
+#define REGS_LO_COUNT (R_LAST_LO_REG + 1u)
+#define REGS_LO_SIZE  (REGS_LO_COUNT * sizeof(uint32_t))
+#define REGS_LO_BASE  0x00u
+#define REG_LO_NAME(_reg_) \
+    ((((_reg_) < REGS_LO_COUNT) && REG_LO_NAMES[_reg_]) ? \
+         REG_LO_NAMES[_reg_] : \
+         "?")
+
+/* only used in version 2 */
+#define R_LAST_REV_REG (R_REV)
+#define REGS_REV_COUNT (R_LAST_REV_REG + 1u)
+#define REGS_REV_SIZE  (REGS_REV_COUNT * sizeof(uint32_t))
+#define REGS_REV_BASE  0x1cu
+#define REG_REV_NAME(_reg_) \
+    ((((_reg_) < REGS_REV_COUNT) && REG_REV_NAMES[_reg_]) ? \
+         REG_REV_NAMES[_reg_] : \
+         "?")
+
+#define R_LAST_HI_REG   (R_MAIN_SM_STATE)
+#define REGS_HI_COUNT   (R_LAST_HI_REG + 1u)
+#define REGS_HI_SIZE    (REGS_HI_COUNT * sizeof(uint32_t))
+#define REGS_HI_V2_BASE 0x20u
+#define REGS_HI_V3_BASE 0x1cu
+#define REG_HI_NAME(_reg_) \
+    ((((_reg_) < REGS_HI_COUNT) && REG_HI_NAMES[_reg_]) ? \
+         REG_HI_NAMES[_reg_] : \
+         "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_LO_NAMES[REGS_LO_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(ME_REGWEN),
+    REG_NAME_ENTRY(SW_REGUPD),
+    REG_NAME_ENTRY(REGWEN),
+    /* clang-format on */
+};
+
+/* only used in version 2 */
+static const char *REG_REV_NAMES[REGS_REV_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(REV),
+    /* clang-format on */
+};
+
+static const char *REG_HI_NAMES[REGS_HI_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(MODULE_ENABLE),
+    REG_NAME_ENTRY(CONF),
+    REG_NAME_ENTRY(ENTROPY_CONTROL),
+    REG_NAME_ENTRY(ENTROPY_DATA),
+    REG_NAME_ENTRY(HEALTH_TEST_WINDOWS),
+    REG_NAME_ENTRY(REPCNT_THRESHOLDS),
+    REG_NAME_ENTRY(REPCNTS_THRESHOLDS),
+    REG_NAME_ENTRY(ADAPTP_HI_THRESHOLDS),
+    REG_NAME_ENTRY(ADAPTP_LO_THRESHOLDS),
+    REG_NAME_ENTRY(BUCKET_THRESHOLDS),
+    REG_NAME_ENTRY(MARKOV_HI_THRESHOLDS),
+    REG_NAME_ENTRY(MARKOV_LO_THRESHOLDS),
+    REG_NAME_ENTRY(EXTHT_HI_THRESHOLDS),
+    REG_NAME_ENTRY(EXTHT_LO_THRESHOLDS),
+    REG_NAME_ENTRY(REPCNT_HI_WATERMARKS),
+    REG_NAME_ENTRY(REPCNTS_HI_WATERMARKS),
+    REG_NAME_ENTRY(ADAPTP_HI_WATERMARKS),
+    REG_NAME_ENTRY(ADAPTP_LO_WATERMARKS),
+    REG_NAME_ENTRY(EXTHT_HI_WATERMARKS),
+    REG_NAME_ENTRY(EXTHT_LO_WATERMARKS),
+    REG_NAME_ENTRY(BUCKET_HI_WATERMARKS),
+    REG_NAME_ENTRY(MARKOV_HI_WATERMARKS),
+    REG_NAME_ENTRY(MARKOV_LO_WATERMARKS),
+    REG_NAME_ENTRY(REPCNT_TOTAL_FAILS),
+    REG_NAME_ENTRY(REPCNTS_TOTAL_FAILS),
+    REG_NAME_ENTRY(ADAPTP_HI_TOTAL_FAILS),
+    REG_NAME_ENTRY(ADAPTP_LO_TOTAL_FAILS),
+    REG_NAME_ENTRY(BUCKET_TOTAL_FAILS),
+    REG_NAME_ENTRY(MARKOV_HI_TOTAL_FAILS),
+    REG_NAME_ENTRY(MARKOV_LO_TOTAL_FAILS),
+    REG_NAME_ENTRY(EXTHT_HI_TOTAL_FAILS),
+    REG_NAME_ENTRY(EXTHT_LO_TOTAL_FAILS),
+    REG_NAME_ENTRY(ALERT_THRESHOLD),
+    REG_NAME_ENTRY(ALERT_SUMMARY_FAIL_COUNTS),
+    REG_NAME_ENTRY(ALERT_FAIL_COUNTS),
+    REG_NAME_ENTRY(EXTHT_FAIL_COUNTS),
+    REG_NAME_ENTRY(FW_OV_CONTROL),
+    REG_NAME_ENTRY(FW_OV_SHA3_START),
+    REG_NAME_ENTRY(FW_OV_WR_FIFO_FULL),
+    REG_NAME_ENTRY(FW_OV_RD_FIFO_OVERFLOW),
+    REG_NAME_ENTRY(FW_OV_RD_DATA),
+    REG_NAME_ENTRY(FW_OV_WR_DATA),
+    REG_NAME_ENTRY(OBSERVE_FIFO_THRESH),
+    REG_NAME_ENTRY(OBSERVE_FIFO_DEPTH),
+    REG_NAME_ENTRY(DEBUG_STATUS),
+    REG_NAME_ENTRY(RECOV_ALERT_STS),
+    REG_NAME_ENTRY(ERR_CODE),
+    REG_NAME_ENTRY(ERR_CODE_TEST),
+    REG_NAME_ENTRY(MAIN_SM_STATE),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+/**
+ * Use a 128-bit incoming packet size (HW uses 4-bit packet) in order to limit
+ * feed rate to ~0.7 ms max. 128-bit packet can be divided down to 32-bit
+ * FIFO packets. They are assembled into either 384-bit or 2048-bit packets.
+ */
+#define ES_FILL_BITS                   128u
+#define ES_FINAL_FIFO_DEPTH            4u
+#define OT_ENTROPY_SRC_FILL_WORD_COUNT (ES_FILL_BITS / (8u * sizeof(uint32_t)))
+#define ES_WORD_COUNT                  (OT_ENTROPY_SRC_WORD_COUNT)
+#define ES_SWREAD_FIFO_WORD_COUNT      ES_WORD_COUNT
+#define ES_FINAL_FIFO_WORD_COUNT       (ES_WORD_COUNT * ES_FINAL_FIFO_DEPTH)
+#define ES_HEXBUF_SIZE                 ((8U * 2u + 1u) * ES_WORD_COUNT + 4u)
+
+/*
+ * see hw/ip/edn/doc/#multiple-edns-in-boot-time-request-mode
+ * reduce initial delay in QEMU since it takes time to manage the entropy
+ */
+#define OT_ENTROPY_SRC_BOOT_DELAY_NS 500000LL /* 500 us */
+/*
+ * default delay to pace the entropy src client (CSRNG) when no entropy is
+ * available. A better implementation would compute the remaining time before
+ * the next available entropy packet.
+ */
+#define OT_ENTROPY_SRC_WAIT_DELAY_NS 2000LL /* 2 us */
+
+enum {
+    ALERT_RECOVERABLE,
+    ALERT_FATAL,
+    ALERT_COUNT,
+};
+
+static_assert(ALERT_COUNT == NUM_ALERTS, "Invalid alert count");
+
+typedef enum {
+    ENTROPY_SRC_IDLE,
+    ENTROPY_SRC_BOOT_HT_RUNNING,
+    ENTROPY_SRC_BOOT_POST_HT_CHK,
+    ENTROPY_SRC_BOOT_PHASE_DONE,
+    ENTROPY_SRC_STARTUP_HT_START,
+    ENTROPY_SRC_STARTUP_PHASE1,
+    ENTROPY_SRC_STARTUP_PASS1,
+    ENTROPY_SRC_STARTUP_FAIL1,
+    ENTROPY_SRC_CONT_HT_START,
+    ENTROPY_SRC_CONT_HT_RUNNING,
+    ENTROPY_SRC_FW_INSERT_START,
+    ENTROPY_SRC_FW_INSERT_MSG,
+    ENTROPY_SRC_SHA3_MSG_DONE,
+    ENTROPY_SRC_SHA3_PROCESS,
+    ENTROPY_SRC_SHA3_VALID,
+    ENTROPY_SRC_SHA3_DONE,
+    ENTROPY_SRC_ALERT_STATE,
+    ENTROPY_SRC_ALERT_HANG,
+    ENTROPY_SRC_ERROR,
+} OtEntropySrcFsmState;
+
+struct OtEntropySrcState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    MemoryRegion mmio_lo;
+    MemoryRegion mmio_rev; /* only in v2 */
+    MemoryRegion mmio_hi;
+    IbexIRQ irqs[NUM_IRQS];
+    IbexIRQ alerts[NUM_ALERTS];
+    QEMUTimer *scheduler;
+
+    uint32_t *regs_lo;
+    uint32_t *regs_rev; /* only on v2 */
+    uint32_t *regs_hi;
+
+    OtFifo32 input_fifo; /* not in real HW, used to reduce feed rate */
+    OtFifo32 precon_fifo; /* 32-to-64 SHA3 input packer */
+    OtFifo32 bypass_fifo; /* 32-to-384 packer */
+    OtFifo32 observe_fifo;
+    OtFifo32 swread_fifo;
+    OtFifo32 final_fifo; /* output FIFO */
+    hash_state sha3_state; /* libtomcrypt hash state */
+    OtEntropySrcFsmState state;
+    uint64_t noise_fill_pace_ns;
+    unsigned cond_word; /* count of words processed with SHA3 till hash */
+    unsigned noise_count; /* count of consumed noise words since enabled */
+    unsigned packet_count; /* count of output packets since enabled */
+    bool obs_fifo_en; /* observe FIFO accept incoming data */
+
+    char *ot_id;
+    unsigned version; /* emulated version */
+    DeviceState *noise_src;
+};
+
+static const uint16_t OtEDNFsmStateCode[] = {
+    [ENTROPY_SRC_IDLE] = 0b011110101,
+    [ENTROPY_SRC_BOOT_HT_RUNNING] = 0b111010010,
+    [ENTROPY_SRC_BOOT_POST_HT_CHK] = 0b101101110,
+    [ENTROPY_SRC_BOOT_PHASE_DONE] = 0b010001110,
+    [ENTROPY_SRC_STARTUP_HT_START] = 0b000101100,
+    [ENTROPY_SRC_STARTUP_PHASE1] = 0b100000001,
+    [ENTROPY_SRC_STARTUP_PASS1] = 0b110100101,
+    [ENTROPY_SRC_STARTUP_FAIL1] = 0b000010111,
+    [ENTROPY_SRC_CONT_HT_START] = 0b001000000,
+    [ENTROPY_SRC_CONT_HT_RUNNING] = 0b110100010,
+    [ENTROPY_SRC_FW_INSERT_START] = 0b011000011,
+    [ENTROPY_SRC_FW_INSERT_MSG] = 0b001011001,
+    [ENTROPY_SRC_SHA3_MSG_DONE] = 0b100001111,
+    [ENTROPY_SRC_SHA3_PROCESS] = 0b011111000,
+    [ENTROPY_SRC_SHA3_VALID] = 0b010111111,
+    [ENTROPY_SRC_SHA3_DONE] = 0b110011000,
+    [ENTROPY_SRC_ALERT_STATE] = 0b111001101,
+    [ENTROPY_SRC_ALERT_HANG] = 0b111111011,
+    [ENTROPY_SRC_ERROR] = 0b001110011,
+};
+
+#define STATE_NAME_ENTRY(_st_) [ENTROPY_SRC_##_st_] = stringify(_st_)
+static const char *STATE_NAMES[] = {
+    STATE_NAME_ENTRY(IDLE),
+    STATE_NAME_ENTRY(BOOT_HT_RUNNING),
+    STATE_NAME_ENTRY(BOOT_POST_HT_CHK),
+    STATE_NAME_ENTRY(BOOT_PHASE_DONE),
+    STATE_NAME_ENTRY(STARTUP_HT_START),
+    STATE_NAME_ENTRY(STARTUP_PHASE1),
+    STATE_NAME_ENTRY(STARTUP_PASS1),
+    STATE_NAME_ENTRY(STARTUP_FAIL1),
+    STATE_NAME_ENTRY(CONT_HT_START),
+    STATE_NAME_ENTRY(CONT_HT_RUNNING),
+    STATE_NAME_ENTRY(FW_INSERT_START),
+    STATE_NAME_ENTRY(FW_INSERT_MSG),
+    STATE_NAME_ENTRY(SHA3_MSG_DONE),
+    STATE_NAME_ENTRY(SHA3_PROCESS),
+    STATE_NAME_ENTRY(SHA3_VALID),
+    STATE_NAME_ENTRY(SHA3_DONE),
+    STATE_NAME_ENTRY(ALERT_STATE),
+    STATE_NAME_ENTRY(ALERT_HANG),
+    STATE_NAME_ENTRY(ERROR),
+};
+#undef STATE_NAME_ENTRY
+#define STATE_NAME(_st_) \
+    ((_st_) >= 0 && (_st_) < ARRAY_SIZE(STATE_NAMES) ? STATE_NAMES[(_st_)] : \
+                                                       "?")
+#define REG_MB4_IS_TRUE(_s_, _g_, _reg_, _fld_) \
+    (FIELD_EX32((_s_)->regs##_##_g_[R_##_reg_], _reg_, _fld_) == \
+     OT_MULTIBITBOOL4_TRUE)
+#define REG_MB4_IS_FALSE(_s_, _g_, _reg_, _fld_) \
+    (FIELD_EX32((_s_)->regs##_##_g_[R_##_reg_], _reg_, _fld_) == \
+     OT_MULTIBITBOOL4_FALSE)
+
+#define xtrace_ot_entropy_src_show_buffer(_s_, _msg_, _buf_, _len_) \
+    ot_entropy_src_show_buffer(_s_, __func__, __LINE__, _msg_, _buf_, _len_)
+
+static bool ot_entropy_src_is_module_enabled(const OtEntropySrcState *s);
+static bool ot_entropy_src_is_fips_enabled(const OtEntropySrcState *s);
+static bool ot_entropy_src_is_hw_route(const OtEntropySrcState *s);
+static bool ot_entropy_src_is_fips_capable(const OtEntropySrcState *s);
+static void ot_entropy_src_update_alerts(OtEntropySrcState *s);
+static void ot_entropy_src_update_filler(OtEntropySrcState *s);
+
+static int ot_entropy_src_get_entropy(
+    OtEntropySrcState *ess, uint64_t random[OT_ENTROPY_SRC_DWORD_COUNT],
+    bool *fips)
+{
+    if (!ot_entropy_src_is_module_enabled(ess)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: entropy_src is down\n", __func__);
+        return -1;
+    }
+
+    bool fips_compliant;
+
+    switch (ess->state) {
+    case ENTROPY_SRC_BOOT_PHASE_DONE:
+        fips_compliant = false;
+        break;
+    case ENTROPY_SRC_CONT_HT_RUNNING:
+    case ENTROPY_SRC_CONT_HT_START:
+    case ENTROPY_SRC_SHA3_MSG_DONE:
+    case ENTROPY_SRC_SHA3_PROCESS:
+    case ENTROPY_SRC_SHA3_VALID:
+    case ENTROPY_SRC_SHA3_DONE:
+        fips_compliant = true;
+        break;
+    case ENTROPY_SRC_BOOT_HT_RUNNING:
+    case ENTROPY_SRC_BOOT_POST_HT_CHK:
+    case ENTROPY_SRC_STARTUP_HT_START:
+    case ENTROPY_SRC_STARTUP_PHASE1:
+    case ENTROPY_SRC_STARTUP_PASS1:
+    case ENTROPY_SRC_STARTUP_FAIL1: {
+        int64_t wait_ns;
+        if (timer_pending(ess->scheduler)) {
+            /* computed delay fits into a 31-bit value */
+            wait_ns = ((int64_t)timer_expire_time_ns(ess->scheduler)) -
+                      qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+            wait_ns = MAX(wait_ns, OT_ENTROPY_SRC_WAIT_DELAY_NS);
+        } else {
+            wait_ns = OT_ENTROPY_SRC_WAIT_DELAY_NS;
+        }
+        trace_ot_entropy_src_init_ongoing(ess->ot_id, STATE_NAME(ess->state),
+                                          ess->state, (int)wait_ns);
+        /* not ready */
+        return (int)wait_ns;
+    }
+    case ENTROPY_SRC_IDLE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: module is not enabled\n", __func__);
+        return -1;
+    case ENTROPY_SRC_FW_INSERT_START:
+    case ENTROPY_SRC_FW_INSERT_MSG:
+    case ENTROPY_SRC_ALERT_STATE:
+    case ENTROPY_SRC_ALERT_HANG:
+    case ENTROPY_SRC_ERROR:
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid state: [%s:%d]\n", __func__,
+                      STATE_NAME(ess->state), ess->state);
+        return -1;
+    }
+
+    if (!ot_entropy_src_is_hw_route(ess)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: HW route not selected\n", __func__);
+        return -1;
+    }
+
+    if (ot_fifo32_num_used(&ess->final_fifo) < ES_WORD_COUNT) {
+        trace_ot_entropy_src_no_entropy(ess->ot_id,
+                                        ot_fifo32_num_used(&ess->final_fifo));
+        return OT_ENTROPY_SRC_WAIT_DELAY_NS;
+    }
+
+    uint32_t *randu32 = (uint32_t *)random;
+    size_t pos = 0;
+    while (pos < ES_WORD_COUNT) {
+        g_assert(!ot_fifo32_is_empty(&ess->final_fifo));
+        randu32[pos++] = ot_fifo32_pop(&ess->final_fifo);
+    }
+
+    bool fips_capable = ot_entropy_src_is_fips_capable(ess);
+
+    /* note: fips compliancy is only simulated here for now */
+    *fips = fips_compliant && fips_capable;
+
+    trace_ot_entropy_src_get_random_fips(
+        ess->ot_id, STATE_NAME(ess->state), ot_entropy_src_is_fips_enabled(ess),
+        REG_MB4_IS_TRUE(ess, hi, ENTROPY_CONTROL, ES_ROUTE),
+        REG_MB4_IS_TRUE(ess, hi, ENTROPY_CONTROL, ES_TYPE),
+        REG_MB4_IS_FALSE(ess, hi, CONF, RNG_BIT_ENABLE), fips_capable,
+        fips_compliant, *fips);
+
+    if (ot_fifo32_num_used(&ess->final_fifo) < ES_WORD_COUNT) {
+        ot_entropy_src_update_filler(ess);
+    }
+
+    return 0;
+}
+
+static void ot_entropy_src_show_buffer(
+    const OtEntropySrcState *s, const char *func, int line, const char *msg,
+    const void *buf, unsigned size)
+{
+    if (trace_event_get_state(TRACE_OT_ENTROPY_SRC_SHOW_BUFFER) &&
+        qemu_loglevel_mask(LOG_TRACE)) {
+        static const char _hex[] = "0123456789ABCDEF";
+        char hexstr[ES_HEXBUF_SIZE];
+        unsigned len = MIN(size, ES_HEXBUF_SIZE / 2u - 4u);
+        const uint8_t *pbuf = (const uint8_t *)buf;
+        memset(hexstr, 0, sizeof(hexstr));
+        unsigned hix = 0;
+        for (unsigned ix = 0u; ix < len; ix++) {
+            if (ix && !(ix & 0x3u)) {
+                hexstr[hix++] = '-';
+            }
+            hexstr[hix++] = _hex[(pbuf[ix] >> 4u) & 0xfu];
+            hexstr[hix++] = _hex[pbuf[ix] & 0xfu];
+        }
+        if (len < size) {
+            hexstr[hix++] = '.';
+            hexstr[hix++] = '.';
+            hexstr[hix++] = '.';
+        }
+
+        trace_ot_entropy_src_show_buffer(s->ot_id, func, line, msg, hexstr);
+    }
+}
+
+static inline uint32_t ot_entropy_src_hi_reg_base(const OtEntropySrcState *s)
+{
+    return (s->version < 3) ? REGS_HI_V2_BASE : REGS_HI_V3_BASE;
+}
+
+static inline uint32_t
+ot_entropy_src_hi_reg_addr(const OtEntropySrcState *s, uint32_t addr)
+{
+    return ot_entropy_src_hi_reg_base(s) + addr;
+}
+
+static bool ot_entropy_src_is_module_enabled(const OtEntropySrcState *s)
+{
+    return REG_MB4_IS_TRUE(s, hi, MODULE_ENABLE, MODULE_ENABLE);
+}
+
+static bool ot_entropy_src_is_module_disabled(const OtEntropySrcState *s)
+{
+    return REG_MB4_IS_FALSE(s, hi, MODULE_ENABLE, MODULE_ENABLE);
+}
+
+static bool ot_entropy_src_is_fips_enabled(const OtEntropySrcState *s)
+{
+    return REG_MB4_IS_TRUE(s, hi, CONF, FIPS_ENABLE);
+}
+
+static void ot_entropy_src_update_irqs(OtEntropySrcState *s)
+{
+    uint32_t levels = s->regs_lo[R_INTR_STATE] & s->regs_lo[R_INTR_ENABLE];
+    for (unsigned ix = 0; ix < NUM_IRQS; ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((levels >> ix) & 0x1u));
+    }
+}
+
+static bool
+ot_entropy_src_is_final_fifo_slot_available(const OtEntropySrcState *s)
+{
+    return ot_fifo32_num_free(&s->final_fifo) >= ES_WORD_COUNT;
+}
+
+static bool ot_entropy_src_is_hw_route(const OtEntropySrcState *s)
+{
+    return REG_MB4_IS_FALSE(s, hi, ENTROPY_CONTROL, ES_ROUTE);
+}
+
+static bool ot_entropy_src_is_fw_route(const OtEntropySrcState *s)
+{
+    return REG_MB4_IS_TRUE(s, hi, ENTROPY_CONTROL, ES_ROUTE);
+}
+
+static bool ot_entropy_src_is_bypass_mode(const OtEntropySrcState *s)
+{
+    return !ot_entropy_src_is_fips_enabled(s) ||
+           (ot_entropy_src_is_fw_route(s) &&
+            REG_MB4_IS_TRUE(s, hi, ENTROPY_CONTROL, ES_TYPE));
+}
+
+static bool ot_entropy_src_is_fw_ov_mode(const OtEntropySrcState *s)
+{
+    return REG_MB4_IS_TRUE(s, hi, FW_OV_CONTROL, FW_OV_MODE);
+}
+
+static bool ot_entropy_src_is_fw_ov_entropy_insert(const OtEntropySrcState *s)
+{
+    return REG_MB4_IS_TRUE(s, hi, FW_OV_CONTROL, FW_OV_ENTROPY_INSERT);
+}
+
+static bool ot_entropy_src_is_fips_capable(const OtEntropySrcState *s)
+{
+    return ot_entropy_src_is_fips_enabled(s) &&
+           !(REG_MB4_IS_TRUE(s, hi, ENTROPY_CONTROL, ES_ROUTE) &&
+             REG_MB4_IS_TRUE(s, hi, ENTROPY_CONTROL, ES_TYPE)) &&
+           REG_MB4_IS_FALSE(s, hi, CONF, RNG_BIT_ENABLE);
+}
+
+static unsigned ot_alert_get_alert_fail_count(const OtEntropySrcState *s)
+{
+    unsigned count;
+
+    count = FIELD_EX32(s->regs_hi[R_ALERT_FAIL_COUNTS], ALERT_FAIL_COUNTS,
+                       REPCNT_FAIL_COUNT);
+    count += FIELD_EX32(s->regs_hi[R_ALERT_FAIL_COUNTS], ALERT_FAIL_COUNTS,
+                        ADAPTP_HI_FAIL_COUNT);
+    count += FIELD_EX32(s->regs_hi[R_ALERT_FAIL_COUNTS], ALERT_FAIL_COUNTS,
+                        ADAPTP_LO_FAIL_COUNT);
+    count += FIELD_EX32(s->regs_hi[R_ALERT_FAIL_COUNTS], ALERT_FAIL_COUNTS,
+                        BUCKET_FAIL_COUNT);
+    count += FIELD_EX32(s->regs_hi[R_ALERT_FAIL_COUNTS], ALERT_FAIL_COUNTS,
+                        MARKOV_HI_FAIL_COUNT);
+    count += FIELD_EX32(s->regs_hi[R_ALERT_FAIL_COUNTS], ALERT_FAIL_COUNTS,
+                        MARKOV_LO_FAIL_COUNT);
+    count += FIELD_EX32(s->regs_hi[R_ALERT_FAIL_COUNTS], ALERT_FAIL_COUNTS,
+                        REPCNTS_FAIL_COUNT);
+
+    return count;
+}
+
+static void ot_entropy_src_change_state_line(
+    OtEntropySrcState *s, OtEntropySrcFsmState state, int line)
+{
+    OtEntropySrcFsmState old_state = s->state;
+
+    switch (s->state) {
+    case ENTROPY_SRC_ALERT_STATE:
+        s->state = ENTROPY_SRC_ALERT_HANG;
+        break;
+    case ENTROPY_SRC_ALERT_HANG:
+        if ((state == ENTROPY_SRC_IDLE) &&
+            ot_entropy_src_is_module_disabled(s)) {
+            s->state = state;
+        }
+        break;
+    default:
+        s->state = state;
+        break;
+    }
+
+    if (old_state != s->state) {
+        trace_ot_entropy_src_change_state(s->ot_id, line, STATE_NAME(old_state),
+                                          old_state, STATE_NAME(s->state),
+                                          s->state);
+    }
+
+    if (s->state == ENTROPY_SRC_ERROR) {
+        s->regs_hi[R_ERR_CODE] |= R_ERR_CODE_ES_MAIN_SM_ERR_MASK;
+        ot_entropy_src_update_alerts(s);
+    }
+}
+
+#define ot_entropy_src_change_state(_s_, _st_) \
+    ot_entropy_src_change_state_line(_s_, _st_, __LINE__)
+
+static void ot_entropy_src_update_alerts(OtEntropySrcState *s)
+{
+    unsigned alert_threshold =
+        FIELD_EX32(s->regs_hi[R_ALERT_THRESHOLD], ALERT_THRESHOLD, VAL);
+    unsigned alert_count = ot_alert_get_alert_fail_count(s);
+    bool recoverable = (bool)s->regs_hi[R_RECOV_ALERT_STS];
+    uint32_t level = s->regs_lo[R_ALERT_TEST];
+    if (alert_count >= alert_threshold || recoverable) {
+        level |= 1u << ALERT_RECOVERABLE;
+    }
+    uint32_t fatal_alert = s->regs_hi[R_ERR_CODE] & ERR_CODE_FATAL_ERROR_MASK;
+    fatal_alert |=
+        (1u << s->regs_hi[R_ERR_CODE_TEST]) & ERR_CODE_FATAL_ERROR_MASK;
+    if (fatal_alert) {
+        level |= 1u << ALERT_FATAL;
+    }
+
+    for (unsigned ix = 0; ix < NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static bool ot_entropy_src_check_multibitboot(
+    OtEntropySrcState *s, uint8_t mbbool, uint32_t alert_bit)
+{
+    switch (mbbool) {
+    case OT_MULTIBITBOOL4_TRUE:
+    case OT_MULTIBITBOOL4_FALSE:
+        return true;
+    default:
+        break;
+    }
+
+    s->regs_hi[R_RECOV_ALERT_STS] |= 1u << alert_bit;
+    ot_entropy_src_update_alerts(s);
+    return false;
+}
+
+static bool ot_entropy_src_can_consume_entropy(const OtEntropySrcState *s)
+{
+    return ot_entropy_src_is_module_enabled(s) &&
+           !(ot_entropy_src_is_fw_ov_entropy_insert(s) &&
+             !ot_entropy_src_is_fw_ov_mode(s));
+}
+
+static void ot_entropy_src_update_filler(OtEntropySrcState *s)
+{
+    /* fill granule is OT_ENTROPY_SRC_FILL_WORD_COUNT bits */
+    bool input =
+        ot_fifo32_num_free(&s->input_fifo) >= OT_ENTROPY_SRC_FILL_WORD_COUNT;
+    bool output = ot_fifo32_num_free(&s->final_fifo) >= ES_WORD_COUNT;
+    bool process = ot_entropy_src_can_consume_entropy(s);
+
+    bool accept_entropy = input && output && process;
+    trace_ot_entropy_src_update_filler(s->ot_id, input, output, process,
+                                       accept_entropy);
+
+    if (!accept_entropy) {
+        /* if cannot accept entropy, stop the entropy scheduler */
+        if (timer_pending(s->scheduler)) {
+            trace_ot_entropy_src_info(s->ot_id, "stop scheduler");
+            timer_del(s->scheduler);
+        }
+    } else {
+        /*
+         * if entropy can be handled, start the entropy scheduler if
+         * it is not already active
+         */
+        if (!timer_pending(s->scheduler)) {
+            trace_ot_entropy_src_info(s->ot_id, "reschedule");
+            uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+            timer_mod(s->scheduler, (int64_t)(now + s->noise_fill_pace_ns));
+        }
+    }
+}
+
+static bool ot_entropy_src_can_condition_entropy(const OtEntropySrcState *s)
+{
+    if (!ot_fifo32_is_full(&s->precon_fifo)) {
+        /* room in preconditioner packer */
+        return true;
+    }
+    if (ot_entropy_src_is_final_fifo_slot_available(s)) {
+        /* room in output FIFO */
+        return true;
+    }
+
+    return false;
+}
+
+static bool ot_entropy_src_can_bypass_entropy(const OtEntropySrcState *s)
+{
+    if (!ot_fifo32_is_full(&s->bypass_fifo)) {
+        /* room in bypass packer */
+        return true;
+    }
+    if (ot_entropy_src_is_final_fifo_slot_available(s)) {
+        /* room in output FIFO */
+        return true;
+    }
+
+    return false;
+}
+
+static bool
+ot_entropy_src_push_entropy_to_conditioner(OtEntropySrcState *s, uint32_t word)
+{
+    int res;
+    if (s->cond_word == 0) {
+        res = sha3_384_init(&s->sha3_state);
+        g_assert(res == CRYPT_OK);
+    }
+
+    g_assert(!ot_fifo32_is_full(&s->precon_fifo));
+
+    ot_fifo32_push(&s->precon_fifo, word);
+
+    if (!ot_fifo32_is_full(&s->precon_fifo)) {
+        return false;
+    }
+
+    ot_entropy_src_change_state(s, ENTROPY_SRC_SHA3_PROCESS);
+
+    uint32_t size;
+    const uint32_t *buf;
+    buf = ot_fifo32_peek_buf(&s->precon_fifo, s->precon_fifo.num, &size);
+    g_assert(size == s->precon_fifo.num);
+    xtrace_ot_entropy_src_show_buffer(s, "sha3 in", buf,
+                                      size * sizeof(uint32_t));
+    res = sha3_process(&s->sha3_state, (const uint8_t *)buf,
+                       size * sizeof(uint32_t));
+    g_assert(res == CRYPT_OK);
+    s->cond_word += size;
+    ot_fifo32_reset(&s->precon_fifo);
+
+    return true;
+}
+
+static bool ot_entropy_src_can_hash(const OtEntropySrcState *s)
+{
+    return ot_fifo32_is_empty(&s->precon_fifo) &&
+           (s->cond_word >= (2048 / (8u * sizeof(uint32_t))));
+}
+
+static void ot_entropy_src_perform_hash(OtEntropySrcState *s)
+{
+    uint32_t hash[OT_ENTROPY_SRC_WORD_COUNT];
+    int res;
+    res = sha3_done(&s->sha3_state, (uint8_t *)hash);
+    g_assert(res == CRYPT_OK);
+    s->cond_word = 0;
+
+    xtrace_ot_entropy_src_show_buffer(s, "sha3 md", hash,
+                                      OT_ENTROPY_SRC_WORD_COUNT *
+                                          sizeof(uint32_t));
+
+    ot_entropy_src_change_state(s, ENTROPY_SRC_SHA3_MSG_DONE);
+
+    for (unsigned ix = 0; ix < OT_ENTROPY_SRC_WORD_COUNT; ix++) {
+        g_assert(!ot_fifo32_is_full(&s->final_fifo));
+        ot_fifo32_push(&s->final_fifo, hash[ix]);
+    }
+    s->packet_count += 1u;
+
+    ot_entropy_src_change_state(s, REG_MB4_IS_TRUE(s, hi, FW_OV_SHA3_START,
+                                                   FW_OV_INSERT_START) ?
+                                       ENTROPY_SRC_IDLE :
+                                       ENTROPY_SRC_CONT_HT_START);
+}
+
+static bool
+ot_entropy_src_push_bypass_entropy(OtEntropySrcState *s, uint32_t word)
+{
+    g_assert(!ot_fifo32_is_full(&s->bypass_fifo));
+
+    ot_fifo32_push(&s->bypass_fifo, word);
+    if (!ot_fifo32_is_full(&s->bypass_fifo)) {
+        /* need a whole OT_ENTROPY_SRC_PACKET_SIZE_BITS packet to move on */
+        return false;
+    }
+
+    /* bypass conditioner full/ready, empty it into the final FIFO */
+    while (!ot_fifo32_is_empty(&s->bypass_fifo)) {
+        g_assert(!ot_fifo32_is_full(&s->final_fifo));
+        ot_fifo32_push(&s->final_fifo, ot_fifo32_pop(&s->bypass_fifo));
+    }
+    s->packet_count += 1u;
+
+    trace_ot_entropy_src_push_bypass_entropy(s->ot_id,
+                                             ot_fifo32_num_used(
+                                                 &s->final_fifo) /
+                                                 OT_ENTROPY_SRC_WORD_COUNT);
+
+    return true;
+}
+
+static void ot_entropy_src_update_fw_route(OtEntropySrcState *s)
+{
+    if (ot_fifo32_num_used(&s->final_fifo) >= ES_WORD_COUNT) {
+        trace_ot_entropy_src_info(s->ot_id, "FW ROUTE");
+        if (ot_fifo32_is_empty(&s->swread_fifo)) {
+            /* refill swread FIFO */
+            unsigned count = ES_WORD_COUNT;
+            while (count--) {
+                ot_fifo32_push(&s->swread_fifo, ot_fifo32_pop(&s->final_fifo));
+            }
+            s->regs_lo[R_INTR_STATE] |= INTR_ES_ENTROPY_VALID_MASK;
+            trace_ot_entropy_src_available(s->ot_id, STATE_NAME(s->state),
+                                           s->state);
+            ot_entropy_src_update_filler(s);
+        }
+    }
+}
+
+static bool ot_entropy_src_consume_entropy(OtEntropySrcState *s, uint32_t word)
+{
+    bool fill_obs_fifo = ot_entropy_src_is_fw_ov_mode(s);
+    bool hw_path = !ot_entropy_src_is_fw_ov_entropy_insert(s);
+    bool bypass = ot_entropy_src_is_bypass_mode(s);
+
+    if (hw_path) {
+        /* check that HW accept data */
+        hw_path = bypass ? ot_entropy_src_can_bypass_entropy(s) :
+                           ot_entropy_src_can_condition_entropy(s);
+    }
+
+    if (!(fill_obs_fifo || hw_path)) {
+        /* no way to consume noise, stop here */
+        trace_ot_entropy_src_info(s->ot_id, "cannot consume noise for now");
+        return false;
+    }
+
+    s->noise_count += 1u;
+    trace_ot_entropy_src_consume_entropy(s->ot_id, fill_obs_fifo, bypass,
+                                         hw_path, s->noise_count);
+
+    if (fill_obs_fifo) {
+        if (ot_fifo32_is_full(&s->observe_fifo)) {
+            trace_ot_entropy_src_error(s->ot_id, "observe FIFO overflow",
+                                       STATE_NAME(s->state), s->state);
+            s->regs_hi[R_FW_OV_RD_FIFO_OVERFLOW] |=
+                R_FW_OV_RD_FIFO_OVERFLOW_VAL_MASK;
+        } else {
+            if (s->obs_fifo_en) {
+                unsigned threshold = s->regs_hi[R_OBSERVE_FIFO_THRESH];
+                ot_fifo32_push(&s->observe_fifo, word);
+                trace_ot_entropy_src_obs_fifo(s->ot_id,
+                                              ot_fifo32_num_used(
+                                                  &s->observe_fifo),
+                                              threshold);
+                if (ot_fifo32_is_full(&s->observe_fifo)) {
+                    /* can only be enabled back once the FIFO is emptied */
+                    trace_ot_entropy_src_info(s->ot_id, "observe FIFO is full");
+                    s->obs_fifo_en = false;
+                }
+                /* is it > or >= ? */
+                if (ot_fifo32_num_used(&s->observe_fifo) >= threshold) {
+                    s->regs_lo[R_INTR_STATE] |= INTR_ES_OBSERVE_FIFO_READY_MASK;
+                }
+            } else {
+                trace_ot_entropy_src_info(s->ot_id, "observe FIFO not enabled");
+            }
+        }
+    }
+
+    if (hw_path) {
+        if (ot_entropy_src_is_bypass_mode(s)) {
+            ot_entropy_src_push_bypass_entropy(s, word);
+        } else {
+            if (ot_entropy_src_push_entropy_to_conditioner(s, word)) {
+                if (ot_entropy_src_can_hash(s)) {
+                    trace_ot_entropy_src_info(s->ot_id, "can hash");
+                    ot_entropy_src_perform_hash(s);
+                }
+            }
+        }
+    }
+
+    if (ot_entropy_src_is_fw_route(s)) {
+        ot_entropy_src_update_fw_route(s);
+    }
+
+    return true;
+}
+
+static uint32_t ot_entropy_src_get_entropy_data(OtEntropySrcState *s)
+{
+    bool is_entropy_data_enabled =
+        (s->version < 3) ?
+            REG_MB4_IS_TRUE(s, hi, CONF, V2_ENTROPY_DATA_REG_ENABLE) :
+            REG_MB4_IS_TRUE(s, hi, CONF, V3_ENTROPY_DATA_REG_ENABLE);
+
+    if (ot_entropy_src_is_module_enabled(s) && is_entropy_data_enabled &&
+        ot_entropy_src_is_fw_route(s)) {
+        if (!ot_fifo32_is_empty(&s->swread_fifo)) {
+            return ot_fifo32_pop(&s->swread_fifo);
+        }
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Entropy data not available\n",
+                      __func__);
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Entropy data not configured\n",
+                      __func__);
+    }
+
+    return 0u;
+}
+
+static bool ot_entropy_src_fill_noise(OtEntropySrcState *s)
+{
+    unsigned count = ot_fifo32_num_free(&s->input_fifo);
+    if (count < OT_ENTROPY_SRC_FILL_WORD_COUNT) {
+        /* no room left, should be resheduled */
+        return false;
+    }
+
+    uint32_t buffer[OT_ENTROPY_SRC_FILL_WORD_COUNT];
+    /* synchronous read */
+    OtNoiseSrcIfClass *nsc = OT_NOISE_SRC_IF_GET_CLASS(s->noise_src);
+    OtNoiseSrcIf *nsi = OT_NOISE_SRC_IF(s->noise_src);
+    nsc->get_noise(nsi, (uint8_t *)buffer, sizeof(buffer));
+
+    /* push the whole entropy buffer into the input FIFO */
+    unsigned pos = 0;
+    while (!ot_fifo32_is_full(&s->input_fifo) && pos < ARRAY_SIZE(buffer)) {
+        ot_fifo32_push(&s->input_fifo, buffer[pos++]);
+    }
+
+    trace_ot_entropy_src_fill_noise(s->ot_id, count,
+                                    ot_fifo32_num_used(&s->input_fifo));
+
+    for (unsigned ix = 0;
+         ix < ES_WORD_COUNT && !ot_fifo32_is_empty(&s->input_fifo); ix++) {
+        if (!ot_entropy_src_consume_entropy(s, ot_fifo32_pop(&s->input_fifo))) {
+            break;
+        }
+    }
+
+    ot_entropy_src_update_irqs(s);
+
+    return true;
+}
+
+static void ot_entropy_src_noise_refill(void *opaque)
+{
+    OtEntropySrcState *s = opaque;
+
+    if (!ot_entropy_src_fill_noise(s)) {
+        trace_ot_entropy_src_info(s->ot_id, "FIFO already filled up");
+        return;
+    }
+
+    switch (s->state) {
+    case ENTROPY_SRC_BOOT_HT_RUNNING:
+        if (s->packet_count > 0) {
+            ot_entropy_src_change_state(s, ENTROPY_SRC_BOOT_PHASE_DONE);
+        }
+        break;
+    case ENTROPY_SRC_STARTUP_HT_START:
+        ot_entropy_src_change_state(s, ENTROPY_SRC_CONT_HT_RUNNING);
+        break;
+    case ENTROPY_SRC_CONT_HT_RUNNING:
+    case ENTROPY_SRC_CONT_HT_START:
+    case ENTROPY_SRC_BOOT_PHASE_DONE:
+    case ENTROPY_SRC_SHA3_VALID:
+    case ENTROPY_SRC_SHA3_PROCESS:
+    case ENTROPY_SRC_SHA3_DONE:
+    case ENTROPY_SRC_SHA3_MSG_DONE:
+        break;
+    default:
+        trace_ot_entropy_src_error(s->ot_id, "unexpected state",
+                                   STATE_NAME(s->state), s->state);
+        break;
+    }
+
+    ot_entropy_src_update_filler(s);
+}
+
+static void ot_entropy_src_scheduler(void *opaque)
+{
+    OtEntropySrcState *s = opaque;
+
+    switch (s->state) {
+    case ENTROPY_SRC_BOOT_HT_RUNNING:
+    case ENTROPY_SRC_BOOT_PHASE_DONE:
+    case ENTROPY_SRC_STARTUP_HT_START:
+    case ENTROPY_SRC_CONT_HT_START:
+    case ENTROPY_SRC_CONT_HT_RUNNING:
+    case ENTROPY_SRC_SHA3_VALID:
+    case ENTROPY_SRC_SHA3_PROCESS:
+    case ENTROPY_SRC_SHA3_DONE:
+    case ENTROPY_SRC_SHA3_MSG_DONE:
+        ot_entropy_src_noise_refill(s);
+        break;
+    case ENTROPY_SRC_IDLE:
+        break;
+    case ENTROPY_SRC_BOOT_POST_HT_CHK:
+    case ENTROPY_SRC_STARTUP_PHASE1:
+    case ENTROPY_SRC_STARTUP_PASS1:
+    case ENTROPY_SRC_STARTUP_FAIL1:
+    case ENTROPY_SRC_FW_INSERT_START:
+    case ENTROPY_SRC_FW_INSERT_MSG:
+    case ENTROPY_SRC_ALERT_STATE:
+    case ENTROPY_SRC_ALERT_HANG:
+    case ENTROPY_SRC_ERROR:
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid state: [%s:%d]\n", __func__,
+                      STATE_NAME(s->state), s->state);
+    }
+
+    ot_entropy_src_update_alerts(s);
+    ot_entropy_src_update_irqs(s);
+}
+
+static uint64_t
+ot_entropy_src_lo_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtEntropySrcState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_ME_REGWEN:
+    case R_SW_REGUPD:
+        val32 = s->regs_lo[reg];
+        break;
+    case R_REGWEN:
+        val32 = (uint32_t)(s->regs_lo[R_SW_REGUPD] == R_SW_REGUPD_VAL_MASK &&
+                           ot_entropy_src_is_module_disabled(s));
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_LO_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_entropy_src_io_read_out(s->ot_id, (uint32_t)addr, REG_LO_NAME(reg),
+                                     val32, pc);
+
+    return (uint64_t)val32;
+}
+
+static uint64_t
+ot_entropy_src_rev_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtEntropySrcState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    g_assert(s->version < 3 && s->regs_rev);
+
+    hwaddr reg = R32_OFF(addr);
+
+    /* NOLINTNEXTLINE(hicpp-multiway-paths-covered) */
+    switch (reg) {
+    case R_REV:
+        val32 = s->regs_rev[reg];
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr + REGS_REV_BASE);
+        val32 = 0;
+        break;
+    }
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_entropy_src_io_read_out(s->ot_id, (uint32_t)addr + REGS_REV_BASE,
+                                     REG_REV_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+}
+
+static uint64_t
+ot_entropy_src_hi_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtEntropySrcState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_MODULE_ENABLE:
+    case R_CONF:
+    case R_ENTROPY_CONTROL:
+    case R_HEALTH_TEST_WINDOWS:
+    case R_REPCNT_THRESHOLDS:
+    case R_REPCNTS_THRESHOLDS:
+    case R_ADAPTP_HI_THRESHOLDS:
+    case R_ADAPTP_LO_THRESHOLDS:
+    case R_BUCKET_THRESHOLDS:
+    case R_MARKOV_HI_THRESHOLDS:
+    case R_MARKOV_LO_THRESHOLDS:
+    case R_EXTHT_HI_THRESHOLDS:
+    case R_EXTHT_LO_THRESHOLDS:
+    case R_REPCNT_HI_WATERMARKS:
+    case R_REPCNTS_HI_WATERMARKS:
+    case R_ADAPTP_HI_WATERMARKS:
+    case R_ADAPTP_LO_WATERMARKS:
+    case R_EXTHT_HI_WATERMARKS:
+    case R_EXTHT_LO_WATERMARKS:
+    case R_BUCKET_HI_WATERMARKS:
+    case R_MARKOV_HI_WATERMARKS:
+    case R_MARKOV_LO_WATERMARKS:
+    case R_REPCNT_TOTAL_FAILS:
+    case R_REPCNTS_TOTAL_FAILS:
+    case R_ADAPTP_HI_TOTAL_FAILS:
+    case R_ADAPTP_LO_TOTAL_FAILS:
+    case R_BUCKET_TOTAL_FAILS:
+    case R_MARKOV_HI_TOTAL_FAILS:
+    case R_MARKOV_LO_TOTAL_FAILS:
+    case R_EXTHT_HI_TOTAL_FAILS:
+    case R_EXTHT_LO_TOTAL_FAILS:
+    case R_ALERT_THRESHOLD:
+    case R_ALERT_FAIL_COUNTS:
+    case R_EXTHT_FAIL_COUNTS:
+    case R_FW_OV_CONTROL:
+    case R_FW_OV_SHA3_START:
+    case R_FW_OV_RD_FIFO_OVERFLOW:
+    case R_OBSERVE_FIFO_THRESH:
+    case R_RECOV_ALERT_STS:
+    case R_ERR_CODE:
+    case R_ERR_CODE_TEST:
+        val32 = s->regs_hi[reg];
+        break;
+    case R_DEBUG_STATUS:
+        /* SHA3 block reporting is not supported */
+        val32 = FIELD_DP32(0, DEBUG_STATUS, ENTROPY_FIFO_DEPTH,
+                           ot_fifo32_num_used(&s->final_fifo));
+        val32 = FIELD_DP32(val32, DEBUG_STATUS, MAIN_SM_IDLE,
+                           (uint32_t)(s->state == ENTROPY_SRC_IDLE));
+        val32 = FIELD_DP32(val32, DEBUG_STATUS, MAIN_SM_BOOT_DONE,
+                           (uint32_t)(s->state == ENTROPY_SRC_BOOT_PHASE_DONE));
+        break;
+    case R_MAIN_SM_STATE:
+        if (s->state < ARRAY_SIZE(OtEDNFsmStateCode)) {
+            val32 = OtEDNFsmStateCode[s->state];
+        } else {
+            val32 = OtEDNFsmStateCode[ENTROPY_SRC_ERROR];
+        }
+        break;
+    case R_ALERT_SUMMARY_FAIL_COUNTS:
+        val32 = (uint32_t)ot_alert_get_alert_fail_count(s);
+        break;
+    case R_ENTROPY_DATA:
+        val32 = ot_entropy_src_get_entropy_data(s);
+        break;
+    case R_FW_OV_WR_FIFO_FULL: {
+        bool can_write;
+        if (ot_entropy_src_is_fw_ov_mode(s) &&
+            ot_entropy_src_is_fw_ov_entropy_insert(s)) {
+            if (ot_entropy_src_is_bypass_mode(s)) {
+                can_write = ot_entropy_src_can_bypass_entropy(s);
+            } else {
+                can_write = ot_entropy_src_can_condition_entropy(s);
+            }
+        } else {
+            can_write = false;
+        }
+        val32 = can_write ? 0u : R_FW_OV_WR_FIFO_FULL_VAL_MASK;
+    } break;
+    case R_FW_OV_RD_DATA:
+        if (ot_entropy_src_is_fw_ov_mode(s)) {
+            if (!ot_fifo32_is_empty(&s->observe_fifo)) {
+                val32 = ot_fifo32_pop(&s->observe_fifo);
+            } else {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: Read from empty observe FIFO\n", __func__);
+                val32 = 0;
+            }
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: FW override mode not active\n",
+                          __func__);
+            val32 = 0;
+        }
+        break;
+    case R_OBSERVE_FIFO_DEPTH:
+        val32 = ot_fifo32_num_used(&s->observe_fifo);
+        break;
+    case R_FW_OV_WR_DATA:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, ot_entropy_src_hi_reg_addr(s, addr),
+                      REG_HI_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%x\n", __func__,
+                      s->ot_id, ot_entropy_src_hi_reg_addr(s, addr));
+        val32 = 0;
+        break;
+    }
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_entropy_src_io_read_out(s->ot_id,
+                                     ot_entropy_src_hi_reg_addr(s, addr),
+                                     REG_HI_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+}
+
+#define CHECK_MULTIBOOT(_s_, _g_, _r_, _b_) \
+    do { \
+        if (!ot_entropy_src_check_multibitboot( \
+                (_s_), FIELD_EX32(s->regs##_##_g_[R_##_r_], _r_, _b_), \
+                ALERT_STATUS_BIT(_b_))) { \
+            qemu_log_mask(LOG_GUEST_ERROR, \
+                          "%s: %s: invalid multiboot value 0x%1x\n", __func__, \
+                          (_s_)->ot_id, \
+                          FIELD_EX32((_s_)->regs##_##_g_[R_##_r_], _r_, _b_)); \
+        } \
+    } while (0)
+
+#define CHECK_MULTIBOOT_VER(_s_, _g_, _r_, _v_, _b_) \
+    do { \
+        if (!ot_entropy_src_check_multibitboot( \
+                (_s_), FIELD_EX32(s->regs##_##_g_[R_##_r_], _r_, _v_##_##_b_), \
+                ALERT_STATUS_BIT(_b_))) { \
+            qemu_log_mask(LOG_GUEST_ERROR, \
+                          "%s: %s: invalid multiboot value 0x%1x\n", __func__, \
+                          (_s_)->ot_id, \
+                          FIELD_EX32((_s_)->regs##_##_g_[R_##_r_], _r_, \
+                                     _v_##_##_b_)); \
+        } \
+    } while (0)
+
+static void ot_entropy_src_lo_regs_write(void *opaque, hwaddr addr,
+                                         uint64_t val64, unsigned size)
+{
+    OtEntropySrcState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_entropy_src_io_write(s->ot_id, (uint32_t)addr, REG_LO_NAME(reg),
+                                  val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_WMASK;
+        s->regs_lo[reg] &= ~val32; /* RW1C */
+        /* not sure about this behavior, seems to be what the tests expect... */
+        if (!ot_fifo32_is_empty(&s->swread_fifo)) {
+            s->regs_lo[R_INTR_STATE] |= INTR_ES_ENTROPY_VALID_MASK;
+        }
+        if (!ot_fifo32_is_empty(&s->observe_fifo)) {
+            s->regs_lo[R_INTR_STATE] |= INTR_ES_OBSERVE_FIFO_READY_MASK;
+        }
+        ot_entropy_src_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_WMASK;
+        s->regs_lo[reg] = val32;
+        ot_entropy_src_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_WMASK;
+        s->regs_lo[R_INTR_STATE] |= val32;
+        ot_entropy_src_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_WMASK;
+        s->regs_lo[reg] = val32;
+        ot_entropy_src_update_alerts(s);
+        break;
+    case R_ME_REGWEN:
+        val32 &= R_ME_REGWEN_EN_MASK;
+        s->regs_lo[reg] &= val32; /* RW0C */
+        break;
+    case R_SW_REGUPD:
+        val32 &= R_SW_REGUPD_VAL_MASK;
+        s->regs_lo[reg] &= val32; /* RW0C */
+        break;
+    case R_REGWEN:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_LO_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static void ot_entropy_src_rev_regs_write(void *opaque, hwaddr addr,
+                                          uint64_t val64, unsigned size)
+{
+    OtEntropySrcState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_entropy_src_io_write(s->ot_id, (uint32_t)addr + REGS_REV_BASE,
+                                  REG_REV_NAME(reg), val32, pc);
+
+    /* NOLINTNEXTLINE(hicpp-multiway-paths-covered) */
+    switch (reg) {
+    case R_REV:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr + REGS_REV_BASE,
+                      REG_REV_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr + REGS_REV_BASE);
+        break;
+    }
+};
+
+static void ot_entropy_src_hi_regs_write(void *opaque, hwaddr addr,
+                                         uint64_t val64, unsigned size)
+{
+    OtEntropySrcState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_entropy_src_io_write(s->ot_id, ot_entropy_src_hi_reg_addr(s, addr),
+                                  REG_HI_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_MODULE_ENABLE:
+        if (s->regs_lo[R_ME_REGWEN]) {
+            uint32_t old = s->regs_hi[reg];
+            val32 &= R_MODULE_ENABLE_MODULE_ENABLE_MASK;
+            s->regs_hi[reg] = val32;
+            CHECK_MULTIBOOT(s, hi, MODULE_ENABLE, MODULE_ENABLE);
+            if (ot_entropy_src_is_module_disabled(s)) {
+                /* reset takes care of cancelling the scheduler timer */
+                resettable_reset(OBJECT(s), RESET_TYPE_COLD);
+                break;
+            }
+            if ((old ^ s->regs_hi[reg]) &&
+                ot_entropy_src_is_module_enabled(s)) {
+                if (ot_entropy_src_is_fips_enabled(s)) {
+                    /* start up phase */
+                    ot_entropy_src_change_state(s,
+                                                ENTROPY_SRC_STARTUP_HT_START);
+                } else {
+                    /* boot phase */
+                    ot_entropy_src_change_state(s, ENTROPY_SRC_BOOT_HT_RUNNING);
+                }
+                uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+                timer_mod(s->scheduler,
+                          (int64_t)(now +
+                                    (uint64_t)OT_ENTROPY_SRC_BOOT_DELAY_NS));
+            }
+            break;
+        }
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: ME_REGWEN not enabled\n", __func__);
+        break;
+    case R_CONF:
+        if (s->regs_lo[R_REGWEN]) {
+            val32 &= (s->version < 3) ? CONF_V2_WMASK : CONF_V3_WMASK;
+            s->regs_hi[reg] = val32;
+            CHECK_MULTIBOOT(s, hi, CONF, FIPS_ENABLE);
+            CHECK_MULTIBOOT(s, hi, CONF, RNG_BIT_ENABLE);
+            if (s->version < 3) {
+                CHECK_MULTIBOOT_VER(s, hi, CONF, V2, ENTROPY_DATA_REG_ENABLE);
+                CHECK_MULTIBOOT_VER(s, hi, CONF, V2, THRESHOLD_SCOPE);
+            } else {
+                CHECK_MULTIBOOT_VER(s, hi, CONF, V3, ENTROPY_DATA_REG_ENABLE);
+                CHECK_MULTIBOOT_VER(s, hi, CONF, V3, THRESHOLD_SCOPE);
+            }
+        }
+        break;
+    case R_ENTROPY_CONTROL:
+        if (s->regs_lo[R_REGWEN]) {
+            val32 &= ENTROPY_CONTROL_WMASK;
+            s->regs_hi[reg] = val32;
+            CHECK_MULTIBOOT(s, hi, ENTROPY_CONTROL, ES_ROUTE);
+            CHECK_MULTIBOOT(s, hi, ENTROPY_CONTROL, ES_TYPE);
+        }
+        break;
+    case R_HEALTH_TEST_WINDOWS:
+        if (s->regs_lo[R_REGWEN]) {
+            s->regs_hi[reg] = val32;
+        }
+        break;
+    case R_REPCNT_THRESHOLDS:
+    case R_REPCNTS_THRESHOLDS:
+    case R_ADAPTP_HI_THRESHOLDS:
+    case R_ADAPTP_LO_THRESHOLDS:
+    case R_BUCKET_THRESHOLDS:
+    case R_MARKOV_HI_THRESHOLDS:
+    case R_MARKOV_LO_THRESHOLDS:
+    case R_EXTHT_HI_THRESHOLDS:
+    case R_EXTHT_LO_THRESHOLDS:
+        if (s->regs_lo[R_REGWEN]) {
+            s->regs_hi[reg] = val32;
+            ot_entropy_src_update_alerts(s);
+        }
+        break;
+    case R_ALERT_THRESHOLD:
+        if (s->regs_lo[R_REGWEN]) {
+            if ((uint16_t)(val32) != (uint16_t)(~(val32 >> 16u))) {
+                s->regs_hi[R_RECOV_ALERT_STS] |=
+                    R_RECOV_ALERT_STS_ES_THRESH_CFG_ALERT_MASK;
+            } else {
+                s->regs_hi[reg] = val32;
+            }
+            ot_entropy_src_update_alerts(s);
+        }
+        break;
+    case R_FW_OV_CONTROL:
+        if (s->regs_lo[R_REGWEN]) {
+            val32 &= FW_OV_CONTROL_WMASK;
+            s->regs_hi[reg] = val32;
+            CHECK_MULTIBOOT(s, hi, FW_OV_CONTROL, FW_OV_MODE);
+            CHECK_MULTIBOOT(s, hi, FW_OV_CONTROL, FW_OV_ENTROPY_INSERT);
+            s->obs_fifo_en = ot_entropy_src_is_fw_ov_mode(s);
+        }
+        break;
+    case R_FW_OV_SHA3_START:
+        if (!ot_entropy_src_is_module_enabled(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: module not enabled\n",
+                          __func__);
+            break;
+        }
+        val32 &= R_FW_OV_SHA3_START_FW_OV_INSERT_START_MASK;
+        s->regs_hi[reg] = val32;
+        CHECK_MULTIBOOT(s, hi, FW_OV_SHA3_START, FW_OV_INSERT_START);
+        if (REG_MB4_IS_TRUE(s, hi, FW_OV_SHA3_START, FW_OV_INSERT_START)) {
+            OtEntropySrcFsmState new_state;
+            new_state = ot_entropy_src_is_bypass_mode(s) ?
+                            ENTROPY_SRC_IDLE :
+                            ENTROPY_SRC_FW_INSERT_START;
+            ot_entropy_src_change_state(s, new_state);
+        } else { /* default to false */
+            if (s->state == ENTROPY_SRC_SHA3_PROCESS) {
+                /* handle SHA3 processing */
+                if (ot_fifo32_is_empty(&s->precon_fifo)) {
+                    ot_entropy_src_perform_hash(s);
+                    if (ot_entropy_src_is_fw_route(s)) {
+                        ot_entropy_src_update_fw_route(s);
+                    }
+                } else {
+                    qemu_log_mask(LOG_GUEST_ERROR, "%s: need 1 more word\n",
+                                  __func__);
+                }
+            } else {
+                OtEntropySrcFsmState new_state;
+                new_state = ot_entropy_src_is_bypass_mode(s) ?
+                                ENTROPY_SRC_BOOT_HT_RUNNING :
+                                ENTROPY_SRC_STARTUP_HT_START;
+                ot_entropy_src_change_state(s, new_state);
+            }
+        }
+        break;
+    case R_FW_OV_RD_FIFO_OVERFLOW:
+        val32 &= R_FW_OV_RD_FIFO_OVERFLOW_VAL_MASK;
+        s->regs_hi[reg] &= val32; /* RW0C */
+        break;
+    case R_FW_OV_WR_DATA:
+        if (!ot_entropy_src_is_module_enabled(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: module not enabled\n",
+                          __func__);
+            break;
+        }
+        if (ot_entropy_src_is_fw_ov_mode(s) &&
+            ot_entropy_src_is_fw_ov_entropy_insert(s)) {
+            bool can_write;
+            if (ot_entropy_src_is_bypass_mode(s)) {
+                can_write = ot_entropy_src_can_bypass_entropy(s);
+                if (can_write) {
+                    ot_entropy_src_push_bypass_entropy(s, val32);
+                }
+            } else {
+                can_write = ot_entropy_src_can_condition_entropy(s);
+                if (can_write) {
+                    ot_entropy_src_push_entropy_to_conditioner(s, val32);
+                }
+            }
+            if (!can_write) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: FW override: FIFO full\n",
+                              __func__);
+            }
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: FW override mode not active\n",
+                          __func__);
+        }
+        break;
+    case R_OBSERVE_FIFO_THRESH:
+        if (s->regs_lo[R_REGWEN]) {
+            val32 &= R_OBSERVE_FIFO_THRESH_VAL_MASK;
+            s->regs_hi[reg] = val32;
+            ot_entropy_src_update_irqs(s);
+        }
+        break;
+    case R_RECOV_ALERT_STS:
+        val32 &= RECOV_ALERT_STS_WMASK;
+        s->regs_hi[reg] &= val32; /* RW0C */
+        break;
+    case R_ERR_CODE_TEST:
+        val32 &= R_ERR_CODE_TEST_VAL_MASK;
+        s->regs_hi[R_ERR_CODE_TEST] = val32;
+        ot_entropy_src_update_irqs(s);
+        ot_entropy_src_update_alerts(s);
+        break;
+    case R_ENTROPY_DATA:
+    case R_REPCNT_HI_WATERMARKS:
+    case R_REPCNTS_HI_WATERMARKS:
+    case R_ADAPTP_HI_WATERMARKS:
+    case R_ADAPTP_LO_WATERMARKS:
+    case R_EXTHT_HI_WATERMARKS:
+    case R_EXTHT_LO_WATERMARKS:
+    case R_BUCKET_HI_WATERMARKS:
+    case R_MARKOV_HI_WATERMARKS:
+    case R_MARKOV_LO_WATERMARKS:
+    case R_REPCNT_TOTAL_FAILS:
+    case R_REPCNTS_TOTAL_FAILS:
+    case R_ADAPTP_HI_TOTAL_FAILS:
+    case R_ADAPTP_LO_TOTAL_FAILS:
+    case R_BUCKET_TOTAL_FAILS:
+    case R_MARKOV_HI_TOTAL_FAILS:
+    case R_MARKOV_LO_TOTAL_FAILS:
+    case R_EXTHT_HI_TOTAL_FAILS:
+    case R_EXTHT_LO_TOTAL_FAILS:
+    case R_ALERT_SUMMARY_FAIL_COUNTS:
+    case R_ALERT_FAIL_COUNTS:
+    case R_EXTHT_FAIL_COUNTS:
+    case R_FW_OV_WR_FIFO_FULL:
+    case R_FW_OV_RD_DATA:
+    case R_OBSERVE_FIFO_DEPTH:
+    case R_DEBUG_STATUS:
+    case R_ERR_CODE:
+    case R_MAIN_SM_STATE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, ot_entropy_src_hi_reg_addr(s, addr),
+                      REG_HI_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      ot_entropy_src_hi_reg_addr(s, addr));
+        break;
+    }
+};
+
+static const MemoryRegionOps ot_entropy_src_lo_ops = {
+    .read = &ot_entropy_src_lo_regs_read,
+    .write = &ot_entropy_src_lo_regs_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4u,
+        .max_access_size = 4u,
+    },
+};
+
+static const MemoryRegionOps ot_entropy_src_rev_ops = {
+    .read = &ot_entropy_src_rev_regs_read,
+    .write = &ot_entropy_src_rev_regs_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4u,
+        .max_access_size = 4u,
+    },
+};
+
+static const MemoryRegionOps ot_entropy_src_hi_ops = {
+    .read = &ot_entropy_src_hi_regs_read,
+    .write = &ot_entropy_src_hi_regs_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4u,
+        .max_access_size = 4u,
+    },
+};
+
+static const Property ot_entropy_src_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtEntropySrcState, ot_id),
+    DEFINE_PROP_UINT32("version", OtEntropySrcState, version, 0),
+    DEFINE_PROP_LINK("noise-src", OtEntropySrcState, noise_src, TYPE_DEVICE,
+                     DeviceState *),
+};
+
+static void ot_entropy_src_reset_enter(Object *obj, ResetType type)
+{
+    OtEntropySrcClass *c = OT_ENTROPY_SRC_GET_CLASS(obj);
+    OtEntropySrcState *s = OT_ENTROPY_SRC(obj);
+
+    trace_ot_entropy_src_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->regs_lo, 0, REGS_LO_SIZE);
+    if (s->version < 3) {
+        memset(s->regs_rev, 0, REGS_REV_SIZE);
+    }
+    memset(s->regs_hi, 0, REGS_HI_SIZE);
+
+    s->regs_lo[R_ME_REGWEN] = 0x00000001u;
+    s->regs_lo[R_SW_REGUPD] = 0x00000001u;
+    s->regs_lo[R_REGWEN] = 0x00000001u;
+    if (s->version < 3) {
+        s->regs_rev[R_REV] = 0x10303u;
+        s->regs_hi[R_CONF] = 0x2649999u;
+        s->regs_hi[R_HEALTH_TEST_WINDOWS] = 0x600200u;
+    } else {
+        s->regs_hi[R_CONF] = 0x999999u;
+        s->regs_hi[R_HEALTH_TEST_WINDOWS] = 0x1800200u;
+    }
+
+    s->regs_hi[R_MODULE_ENABLE] = 0x9u;
+    s->regs_hi[R_ENTROPY_CONTROL] = 0x99u;
+    s->regs_hi[R_REPCNT_THRESHOLDS] = 0xffffffffu;
+    s->regs_hi[R_REPCNTS_THRESHOLDS] = 0xffffffffu;
+    s->regs_hi[R_ADAPTP_HI_THRESHOLDS] = 0xffffffffu;
+    s->regs_hi[R_BUCKET_THRESHOLDS] = 0xffffffffu;
+    s->regs_hi[R_MARKOV_HI_THRESHOLDS] = 0xffffffffu;
+    s->regs_hi[R_EXTHT_HI_THRESHOLDS] = 0xffffffffu;
+    s->regs_hi[R_ADAPTP_LO_WATERMARKS] = 0xffffffffu;
+    s->regs_hi[R_EXTHT_LO_WATERMARKS] = 0xffffffffu;
+    s->regs_hi[R_MARKOV_LO_WATERMARKS] = 0xffffffffu;
+    s->regs_hi[R_ALERT_THRESHOLD] = 0xfffd0002u;
+    s->regs_hi[R_FW_OV_CONTROL] = 0x99u;
+    s->regs_hi[R_FW_OV_SHA3_START] = 0x9u;
+    s->regs_hi[R_OBSERVE_FIFO_THRESH] = 0x10u;
+    s->regs_hi[R_DEBUG_STATUS] = 0x10000u;
+    s->regs_hi[R_MAIN_SM_STATE] = 0xf5u;
+    ot_fifo32_reset(&s->input_fifo);
+    ot_fifo32_reset(&s->precon_fifo);
+    ot_fifo32_reset(&s->bypass_fifo);
+    ot_fifo32_reset(&s->observe_fifo);
+    ot_fifo32_reset(&s->swread_fifo);
+    ot_fifo32_reset(&s->final_fifo);
+
+    s->cond_word = 0u;
+    s->noise_count = 0u;
+    s->packet_count = 0u;
+    s->obs_fifo_en = false;
+
+    ot_entropy_src_update_irqs(s);
+    for (unsigned ix = 0; ix < NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->alerts[ix], 0);
+    }
+
+    ot_entropy_src_change_state(s, ENTROPY_SRC_IDLE);
+}
+
+static void ot_entropy_src_reset_exit(Object *obj, ResetType type)
+{
+    OtEntropySrcClass *c = OT_ENTROPY_SRC_GET_CLASS(obj);
+    OtEntropySrcState *s = OT_ENTROPY_SRC(obj);
+
+    trace_ot_entropy_src_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    OtNoiseSrcIfClass *nsc = OT_NOISE_SRC_IF_GET_CLASS(s->noise_src);
+    OtNoiseSrcIf *nsi = OT_NOISE_SRC_IF(s->noise_src);
+    uint64_t noise_file_rate = nsc->get_fill_rate(nsi);
+    s->noise_fill_pace_ns =
+        (NANOSECONDS_PER_SECOND * ES_FILL_BITS) / (noise_file_rate * 8ull);
+}
+
+static void ot_entropy_src_realize(DeviceState *dev, Error **errp)
+{
+    (void)errp;
+
+    OtEntropySrcState *s = OT_ENTROPY_SRC(dev);
+
+    /* emulated version should be specified */
+    g_assert(s->version > 0);
+    g_assert(s->noise_src);
+
+    memory_region_init_io(&s->mmio_lo, OBJECT(dev), &ot_entropy_src_lo_ops, s,
+                          TYPE_OT_ENTROPY_SRC "-regs-lo", REGS_LO_SIZE);
+    memory_region_add_subregion(&s->mmio, REGS_LO_BASE, &s->mmio_lo);
+
+    if (s->version < 3) {
+        memory_region_init_io(&s->mmio_rev, OBJECT(dev),
+                              &ot_entropy_src_rev_ops, s,
+                              TYPE_OT_ENTROPY_SRC "-regs-rev", REGS_REV_SIZE);
+        memory_region_add_subregion(&s->mmio, REGS_REV_BASE, &s->mmio_rev);
+    }
+
+    memory_region_init_io(&s->mmio_hi, OBJECT(dev), &ot_entropy_src_hi_ops, s,
+                          TYPE_OT_ENTROPY_SRC "-regs-hi", REGS_HI_SIZE);
+    memory_region_add_subregion(&s->mmio, ot_entropy_src_hi_reg_base(s),
+                                &s->mmio_hi);
+
+    (void)OBJECT_CHECK(OtNoiseSrcIf, s->noise_src, TYPE_OT_NOISE_SRC_IF);
+}
+
+static void ot_entropy_src_init(Object *obj)
+{
+    OtEntropySrcState *s = OT_ENTROPY_SRC(obj);
+
+#define OT_ENTROPY_SRC_APERTURE 0x100u
+
+    memory_region_init(&s->mmio, obj, TYPE_OT_ENTROPY_SRC "-regs",
+                       OT_ENTROPY_SRC_APERTURE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    /*
+     * note: MMIO operations are defined when the device is realized, as the
+     * version needs to be known to map the registers at the proper addresses.
+     */
+    s->regs_lo = g_new0(uint32_t, REGS_LO_COUNT);
+    if (s->version < 3) {
+        s->regs_rev = g_new0(uint32_t, REGS_REV_COUNT);
+    }
+    s->regs_hi = g_new0(uint32_t, REGS_HI_COUNT);
+
+    for (unsigned ix = 0; ix < NUM_IRQS; ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+
+    for (unsigned ix = 0; ix < NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    ot_fifo32_create(&s->input_fifo, OT_ENTROPY_SRC_FILL_WORD_COUNT * 2u);
+    ot_fifo32_create(&s->precon_fifo, sizeof(uint64_t) / sizeof(uint32_t));
+    ot_fifo32_create(&s->bypass_fifo, ES_WORD_COUNT);
+    ot_fifo32_create(&s->observe_fifo, OBSERVE_FIFO_DEPTH);
+    ot_fifo32_create(&s->swread_fifo, ES_SWREAD_FIFO_WORD_COUNT);
+    ot_fifo32_create(&s->final_fifo, ES_FINAL_FIFO_WORD_COUNT);
+
+    s->scheduler = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_entropy_src_scheduler, s);
+}
+
+static void ot_entropy_src_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_entropy_src_realize;
+    device_class_set_props(dc, ot_entropy_src_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    OtEntropySrcClass *ec = OT_ENTROPY_SRC_CLASS(klass);
+    ec->get_entropy = &ot_entropy_src_get_entropy;
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_entropy_src_reset_enter, NULL,
+                                       &ot_entropy_src_reset_exit,
+                                       &ec->parent_phases);
+}
+
+static const TypeInfo ot_entropy_src_info = {
+    .name = TYPE_OT_ENTROPY_SRC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtEntropySrcState),
+    .instance_init = &ot_entropy_src_init,
+    .class_size = sizeof(OtEntropySrcClass),
+    .class_init = &ot_entropy_src_class_init,
+};
+
+static void ot_entropy_src_register_types(void)
+{
+    type_register_static(&ot_entropy_src_info);
+}
+
+type_init(ot_entropy_src_register_types);
diff --git a/hw/opentitan/ot_flash.c b/hw/opentitan/ot_flash.c
new file mode 100644
index 0000000000000..4558915138fd2
--- /dev/null
+++ b/hw/opentitan/ot_flash.c
@@ -0,0 +1,3438 @@
+/*
+ * QEMU OpenTitan Flash controller device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Known limitations:
+ *  - ECC/ICV/Scrambling functionality is completely unsupported in QEMU,
+ *    including ECC single error support.
+ *  - In addition, the loading of flash address and flash data scrambling keys
+ *    from OTP is likewise not included in initialisation.
+ *  - The lc_ctrl `LC_NVM_DEBUG_EN` is currently unused. The `LC_ESCALATE_EN`
+ *    signal is partially implemented (disables the flash).
+ *  - Alert functionality is only partially modelled.
+ *  - Life cycle RMA Entry is not implemented.
+ *
+ * Other notes:
+ *  - Program Repair / High Endurance enables are meaningless in the OT
+ *  Generic Flash Bank and so are not emulated.
+ *  - Erase suspend is not emulated as erases are done synchronously, so
+ *  you can suspend, but the bit will be immediately cleared.
+ *  - Flash operations are generally treated as synchronous, so arbitration
+ *  between SW and HW is entirely unsupported.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/memalign.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "elf.h"
+#include "hw/loader.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_fifo32.h"
+#include "hw/opentitan/ot_flash.h"
+#include "hw/opentitan/ot_lc_ctrl.h"
+#include "hw/opentitan/ot_vmapper.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "system/block-backend.h"
+#include "trace.h"
+
+/* set to use I/O to access the flash partition */
+#define DATA_PART_USE_IO_OPS 0
+
+/* set to log hart GPR on flash data access */
+#define LOG_GPR_ON_FLASH_DATA_ACCESS 0
+
+/* temp. */
+#pragma GCC diagnostic ignored "-Wunused-variable"
+
+#define PARAM_NUM_IRQS   6u
+#define PARAM_NUM_ALERTS 5u
+
+#define FLASH_SEED_BANK           0u
+#define FLASH_SEED_INFO_PARTITION 0u
+#define FLASH_SEED_WIDTH          256u
+#define FLASH_SEED_BYTES          ((FLASH_SEED_WIDTH) / 8u)
+#define FLASH_SEED_WORDS          ((FLASH_SEED_BYTES) / sizeof(uint32_t))
+
+static_assert(FLASH_SEED_BYTES == OT_FLASH_KEYMGR_SECRET_BYTES,
+              "Flash seed & keymgr secret sizes do not match");
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(INTR_PROG_EMPTY, 0u, 1u)
+    SHARED_FIELD(INTR_PROG_LVL, 1u, 1u)
+    SHARED_FIELD(INTR_RD_FULL, 2u, 1u)
+    SHARED_FIELD(INTR_RD_LVL, 3u, 1u)
+    SHARED_FIELD(INTR_OP_DONE, 4u, 1u)
+    SHARED_FIELD(INTR_CORR_ERR, 5u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    SHARED_FIELD(ALERT_RECOV_ERR, 0u, 1u)
+    SHARED_FIELD(ALERT_FATAL_STD_ERR, 1u, 1u)
+    SHARED_FIELD(ALERT_FATAL_ERR, 2u, 1u)
+    SHARED_FIELD(ALERT_FATAL_PRIM, 3u, 1u)
+    SHARED_FIELD(ALERT_RECOV_PRIM, 4u, 1u)
+REG32(DIS, 0x10u)
+    FIELD(DIS, VAL, 0u, 4u)
+REG32(EXEC, 0x14u)
+REG32(INIT, 0x18u)
+    FIELD(INIT, VAL, 0u, 1u)
+REG32(CTRL_REGWEN, 0x1cu)
+    FIELD(CTRL_REGWEN, EN, 0u, 1u)
+REG32(CONTROL, 0x20u)
+    FIELD(CONTROL, START, 0u, 1u)
+    FIELD(CONTROL, OP, 4u, 2u)
+    FIELD(CONTROL, PROG_SEL, 6u, 1u)
+    FIELD(CONTROL, ERASE_SEL, 7u, 1u)
+    FIELD(CONTROL, PARTITION_SEL, 8u, 1u)
+    FIELD(CONTROL, INFO_SEL, 9u, 2u)
+    FIELD(CONTROL, NUM, 16u, 12u)
+REG32(ADDR, 0x24u)
+    FIELD(ADDR, START, 0u, 20u)
+REG32(PROG_TYPE_EN, 0x28u)
+    FIELD(PROG_TYPE_EN, NORMAL, 0u, 1u)
+    FIELD(PROG_TYPE_EN, REPAIR, 1u, 1u)
+REG32(ERASE_SUSPEND, 0x2cu)
+    FIELD(ERASE_SUSPEND, REQ, 0u, 1u)
+REG32(REGION_CFG_REGWEN_0, 0x30u)
+    SHARED_FIELD(REGWEN_EN, 0u, 1u)
+REG32(REGION_CFG_REGWEN_1, 0x34u)
+REG32(REGION_CFG_REGWEN_2, 0x38u)
+REG32(REGION_CFG_REGWEN_3, 0x3cu)
+REG32(REGION_CFG_REGWEN_4, 0x40u)
+REG32(REGION_CFG_REGWEN_5, 0x44u)
+REG32(REGION_CFG_REGWEN_6, 0x48u)
+REG32(REGION_CFG_REGWEN_7, 0x4cu)
+REG32(MP_REGION_CFG_0, 0x50u)
+    SHARED_FIELD(MP_REGION_CFG_EN, 0u, 4u)
+    SHARED_FIELD(MP_REGION_CFG_RD_EN, 4u, 4u)
+    SHARED_FIELD(MP_REGION_CFG_PROG_EN, 8u, 4u)
+    SHARED_FIELD(MP_REGION_CFG_ERASE_EN, 12u, 4u)
+    SHARED_FIELD(MP_REGION_CFG_SCRAMBLE_EN, 16u, 4u)
+    SHARED_FIELD(MP_REGION_CFG_ECC_EN, 20u, 4u)
+    SHARED_FIELD(MP_REGION_CFG_HE_EN, 24u, 4u)
+REG32(MP_REGION_CFG_1, 0x54u)
+REG32(MP_REGION_CFG_2, 0x58u)
+REG32(MP_REGION_CFG_3, 0x5cu)
+REG32(MP_REGION_CFG_4, 0x60u)
+REG32(MP_REGION_CFG_5, 0x64u)
+REG32(MP_REGION_CFG_6, 0x68u)
+REG32(MP_REGION_CFG_7, 0x6cu)
+REG32(MP_REGION_0, 0x70u)
+    SHARED_FIELD(MP_REGION_BASE, 0u, 9u)
+    SHARED_FIELD(MP_REGION_SIZE, 9u, 10u)
+REG32(MP_REGION_1, 0x74u)
+REG32(MP_REGION_2, 0x78u)
+REG32(MP_REGION_3, 0x7cu)
+REG32(MP_REGION_4, 0x80u)
+REG32(MP_REGION_5, 0x84u)
+REG32(MP_REGION_6, 0x88u)
+REG32(MP_REGION_7, 0x8cu)
+REG32(DEFAULT_REGION, 0x90u)
+    FIELD(DEFAULT_REGION, RD_EN, 0u, 4u)
+    FIELD(DEFAULT_REGION, PROG_EN, 4u, 4u)
+    FIELD(DEFAULT_REGION, ERASE_EN, 8u, 4u)
+    FIELD(DEFAULT_REGION, SCRAMBLE_EN, 12u, 4u)
+    FIELD(DEFAULT_REGION, ECC_EN, 16u, 4u)
+    FIELD(DEFAULT_REGION, HE_EN, 20u, 4u)
+REG32(BANK0_INFO0_REGWEN_0, 0x94u)
+    SHARED_FIELD(BANK_REGWEN, 0u, 1u)
+REG32(BANK0_INFO0_REGWEN_1, 0x98u)
+REG32(BANK0_INFO0_REGWEN_2, 0x9cu)
+REG32(BANK0_INFO0_REGWEN_3, 0xa0u)
+REG32(BANK0_INFO0_REGWEN_4, 0xa4u)
+REG32(BANK0_INFO0_REGWEN_5, 0xa8u)
+REG32(BANK0_INFO0_REGWEN_6, 0xacu)
+REG32(BANK0_INFO0_REGWEN_7, 0xb0u)
+REG32(BANK0_INFO0_REGWEN_8, 0xb4u)
+REG32(BANK0_INFO0_REGWEN_9, 0xb8u)
+REG32(BANK0_INFO0_PAGE_CFG_0, 0xbcu)
+    SHARED_FIELD(BANK_INFO_PAGE_CFG_EN, 0u, 4u)
+    SHARED_FIELD(BANK_INFO_PAGE_CFG_RD_EN, 4u, 4u)
+    SHARED_FIELD(BANK_INFO_PAGE_CFG_PROG_EN, 8u, 4u)
+    SHARED_FIELD(BANK_INFO_PAGE_CFG_ERASE_EN, 12u, 4u)
+    SHARED_FIELD(BANK_INFO_PAGE_CFG_SCRAMBLE_EN, 16u, 4u)
+    SHARED_FIELD(BANK_INFO_PAGE_CFG_ECC_EN, 20u, 4u)
+    SHARED_FIELD(BANK_INFO_PAGE_CFG_HE_EN, 24u, 4u)
+REG32(BANK0_INFO0_PAGE_CFG_1, 0xc0u)
+REG32(BANK0_INFO0_PAGE_CFG_2, 0xc4u)
+REG32(BANK0_INFO0_PAGE_CFG_3, 0xc8u)
+REG32(BANK0_INFO0_PAGE_CFG_4, 0xccu)
+REG32(BANK0_INFO0_PAGE_CFG_5, 0xd0u)
+REG32(BANK0_INFO0_PAGE_CFG_6, 0xd4u)
+REG32(BANK0_INFO0_PAGE_CFG_7, 0xd8u)
+REG32(BANK0_INFO0_PAGE_CFG_8, 0xdcu)
+REG32(BANK0_INFO0_PAGE_CFG_9, 0xe0u)
+REG32(BANK0_INFO1_REGWEN, 0xe4u)
+REG32(BANK0_INFO1_PAGE_CFG, 0xe8u)
+REG32(BANK0_INFO2_REGWEN_0, 0xecu)
+REG32(BANK0_INFO2_REGWEN_1, 0xf0u)
+REG32(BANK0_INFO2_PAGE_CFG_0, 0xf4u)
+REG32(BANK0_INFO2_PAGE_CFG_1, 0xf8u)
+REG32(BANK1_INFO0_REGWEN_0, 0xfcu)
+REG32(BANK1_INFO0_REGWEN_1, 0x100u)
+REG32(BANK1_INFO0_REGWEN_2, 0x104u)
+REG32(BANK1_INFO0_REGWEN_3, 0x108u)
+REG32(BANK1_INFO0_REGWEN_4, 0x10cu)
+REG32(BANK1_INFO0_REGWEN_5, 0x110u)
+REG32(BANK1_INFO0_REGWEN_6, 0x114u)
+REG32(BANK1_INFO0_REGWEN_7, 0x118u)
+REG32(BANK1_INFO0_REGWEN_8, 0x11cu)
+REG32(BANK1_INFO0_REGWEN_9, 0x120u)
+REG32(BANK1_INFO0_PAGE_CFG_0, 0x124u)
+REG32(BANK1_INFO0_PAGE_CFG_1, 0x128u)
+REG32(BANK1_INFO0_PAGE_CFG_2, 0x12cu)
+REG32(BANK1_INFO0_PAGE_CFG_3, 0x130u)
+REG32(BANK1_INFO0_PAGE_CFG_4, 0x134u)
+REG32(BANK1_INFO0_PAGE_CFG_5, 0x138u)
+REG32(BANK1_INFO0_PAGE_CFG_6, 0x13cu)
+REG32(BANK1_INFO0_PAGE_CFG_7, 0x140u)
+REG32(BANK1_INFO0_PAGE_CFG_8, 0x144u)
+REG32(BANK1_INFO0_PAGE_CFG_9, 0x148u)
+REG32(BANK1_INFO1_REGWEN, 0x14cu)
+REG32(BANK1_INFO1_PAGE_CFG, 0x150u)
+REG32(BANK1_INFO2_REGWEN_0, 0x154u)
+REG32(BANK1_INFO2_REGWEN_1, 0x158u)
+REG32(BANK1_INFO2_PAGE_CFG_0, 0x15cu)
+REG32(BANK1_INFO2_PAGE_CFG_1, 0x160u)
+REG32(HW_INFO_CFG_OVERRIDE, 0x164u)
+    FIELD(HW_INFO_CFG_OVERRIDE, SCRAMBLE_DIS, 0u, 4u)
+    FIELD(HW_INFO_CFG_OVERRIDE, ECC_DIS, 4u, 4u)
+REG32(BANK_CFG_REGWEN, 0x168u)
+REG32(MP_BANK_CFG_SHADOWED, 0x16cu)
+    FIELD(MP_BANK_CFG_SHADOWED, ERASE_EN_0, 0u, 1u)
+    FIELD(MP_BANK_CFG_SHADOWED, ERASE_EN_1, 1u, 1u)
+REG32(OP_STATUS, 0x170u)
+    FIELD(OP_STATUS, DONE, 0u, 1u)
+    FIELD(OP_STATUS, ERR, 1u, 1u)
+REG32(STATUS, 0x174u)
+    FIELD(STATUS, RD_FULL, 0u, 1u)
+    FIELD(STATUS, RD_EMPTY, 1u, 1u)
+    FIELD(STATUS, PROG_FULL, 2u, 1u)
+    FIELD(STATUS, PROG_EMPTY, 3u, 1u)
+    FIELD(STATUS, INIT_WIP, 4u, 1u)
+    FIELD(STATUS, INITIALIZED, 5u, 1u)
+REG32(DEBUG_STATE, 0x178u)
+    FIELD(DEBUG_STATE, LCMGR_STATE_MASK, 0u, 11u)
+REG32(ERR_CODE, 0x17cu)
+    FIELD(ERR_CODE, OP_ERR, 0u, 1u)
+    FIELD(ERR_CODE, MP_ERR, 1u, 1u)
+    FIELD(ERR_CODE, RD_ERR, 2u, 1u)
+    FIELD(ERR_CODE, PROG_ERR, 3u, 1u)
+    FIELD(ERR_CODE, PROG_WIN_ERR, 4u, 1u)
+    FIELD(ERR_CODE, PROG_TYPE_ERR, 5u, 1u)
+    FIELD(ERR_CODE, UPDATE_ERR, 6u, 1u)
+    FIELD(ERR_CODE, MACRO_ERR, 7u, 1u)
+REG32(STD_FAULT_STATUS, 0x180u)
+    FIELD(STD_FAULT_STATUS, REG_INTG_ERR, 0u, 1u)
+    FIELD(STD_FAULT_STATUS, PROG_INTG_ERR, 1u, 1u)
+    FIELD(STD_FAULT_STATUS, LCMGR_ERR, 2u, 1u)
+    FIELD(STD_FAULT_STATUS, LCMGR_INTG_ERR, 3u, 1u)
+    FIELD(STD_FAULT_STATUS, ARB_FSM_ERR, 4u, 1u)
+    FIELD(STD_FAULT_STATUS, STORAGE_ERR, 5u, 1u)
+    FIELD(STD_FAULT_STATUS, PHY_FSM_ERR, 6u, 1u)
+    FIELD(STD_FAULT_STATUS, CTRL_CNT_ERR, 7u, 1u)
+    FIELD(STD_FAULT_STATUS, FIFO_ERR, 8u, 1u)
+REG32(FAULT_STATUS, 0x184u)
+    FIELD(FAULT_STATUS, OP_ERR, 0u, 1u)
+    FIELD(FAULT_STATUS, MP_ERR, 1u, 1u)
+    FIELD(FAULT_STATUS, RD_ERR, 2u, 1u)
+    FIELD(FAULT_STATUS, PROG_ERR, 3u, 1u)
+    FIELD(FAULT_STATUS, PROG_WIN_ERR, 4u, 1u)
+    FIELD(FAULT_STATUS, PROG_TYPE_ERR, 5u, 1u)
+    FIELD(FAULT_STATUS, SEED_ERR, 6u, 1u)
+    FIELD(FAULT_STATUS, PHY_RELBL_ERR, 7u, 1u)
+    FIELD(FAULT_STATUS, PHY_STORAGE_ERR, 8u, 1u)
+    FIELD(FAULT_STATUS, SPURIOUS_ACK, 9u, 1u)
+    FIELD(FAULT_STATUS, ARB_ERR, 10u, 1u)
+    FIELD(FAULT_STATUS, HOST_GNT_ERR, 11u, 1u)
+REG32(ERR_ADDR, 0x188u)
+    FIELD(ERR_ADDR, ERR_ADDR, 0u, 20u)
+REG32(ECC_SINGLE_ERR_CNT, 0x18cu)
+    FIELD(ECC_SINGLE_ERR_CNT, CNT_0, 0u, 8u)
+    FIELD(ECC_SINGLE_ERR_CNT, CNT_1, 8u, 8u)
+REG32(ECC_SINGLE_ERR_ADDR_0, 0x190u)
+    SHARED_FIELD(ECC_SINGLE_ERR_ADDR, 0u, 20u)
+REG32(ECC_SINGLE_ERR_ADDR_1, 0x194u)
+REG32(PHY_ALERT_CFG, 0x198u)
+    FIELD(PHY_ALERT_CFG, ALERT_ACK, 0u, 1u)
+    FIELD(PHY_ALERT_CFG, ALERT_TRIG, 1u, 1u)
+REG32(PHY_STATUS, 0x19cu)
+    FIELD(PHY_STATUS, INIT_WIP, 0u, 1u)
+    FIELD(PHY_STATUS, PROG_NORMAL_AVAIL, 1u, 1u)
+    FIELD(PHY_STATUS, PROG_REPAIR_AVAIL, 2u, 1u)
+REG32(SCRATCH, 0x1a0u)
+REG32(FIFO_LVL, 0x1a4u)
+    SHARED_FIELD(FIFO_LVL_PROG, 0u, 5u)
+    SHARED_FIELD(FIFO_LVL_RD, 8u, 5u)
+REG32(FIFO_RST, 0x1a8u)
+    FIELD(FIFO_RST, EN, 0u, 1u)
+REG32(CURR_FIFO_LVL, 0x1acu)
+REG32(PROG_FIFO, 0x1b0u)
+REG32(RD_FIFO, 0x1b4u)
+
+#define INTR_MASK \
+    (INTR_PROG_EMPTY_MASK | \
+     INTR_PROG_LVL_MASK | \
+     INTR_RD_FULL_MASK | \
+     INTR_RD_LVL_MASK | \
+     INTR_OP_DONE_MASK | \
+     INTR_CORR_ERR_MASK)
+#define ALERT_MASK \
+    (ALERT_RECOV_ERR_MASK | \
+     ALERT_FATAL_STD_ERR_MASK | \
+     ALERT_FATAL_ERR_MASK | \
+     ALERT_FATAL_PRIM_MASK | \
+     ALERT_RECOV_PRIM_MASK)
+#define BANK_INFO_PAGE_CFG_MASK \
+    (BANK_INFO_PAGE_CFG_EN_MASK | \
+     BANK_INFO_PAGE_CFG_RD_EN_MASK | \
+     BANK_INFO_PAGE_CFG_PROG_EN_MASK | \
+     BANK_INFO_PAGE_CFG_ERASE_EN_MASK | \
+     BANK_INFO_PAGE_CFG_SCRAMBLE_EN_MASK | \
+     BANK_INFO_PAGE_CFG_ECC_EN_MASK | \
+     BANK_INFO_PAGE_CFG_HE_EN_MASK)
+#define MP_REGION_CFG_MASK \
+    (MP_REGION_CFG_EN_MASK | \
+     MP_REGION_CFG_RD_EN_MASK | \
+     MP_REGION_CFG_PROG_EN_MASK | \
+     MP_REGION_CFG_ERASE_EN_MASK | \
+     MP_REGION_CFG_SCRAMBLE_EN_MASK | \
+     MP_REGION_CFG_ECC_EN_MASK | \
+     MP_REGION_CFG_HE_EN_MASK)
+#define MP_REGION_MASK \
+     (MP_REGION_BASE_MASK | \
+      MP_REGION_SIZE_MASK)
+#define DEFAULT_REGION_MASK \
+    (R_DEFAULT_REGION_RD_EN_MASK | \
+     R_DEFAULT_REGION_PROG_EN_MASK | \
+     R_DEFAULT_REGION_ERASE_EN_MASK | \
+     R_DEFAULT_REGION_SCRAMBLE_EN_MASK | \
+     R_DEFAULT_REGION_ECC_EN_MASK | \
+     R_DEFAULT_REGION_HE_EN_MASK)
+#define CONTROL_MASK \
+    (R_CONTROL_START_MASK | \
+     R_CONTROL_OP_MASK | \
+     R_CONTROL_PROG_SEL_MASK | \
+     R_CONTROL_ERASE_SEL_MASK | \
+     R_CONTROL_PARTITION_SEL_MASK | \
+     R_CONTROL_INFO_SEL_MASK | \
+     R_CONTROL_NUM_MASK);
+#define ERR_CODE_MASK \
+    (R_ERR_CODE_OP_ERR_MASK | \
+     R_ERR_CODE_MP_ERR_MASK | \
+     R_ERR_CODE_RD_ERR_MASK | \
+     R_ERR_CODE_PROG_ERR_MASK | \
+     R_ERR_CODE_PROG_WIN_ERR_MASK | \
+     R_ERR_CODE_PROG_TYPE_ERR_MASK | \
+     R_ERR_CODE_UPDATE_ERR_MASK | \
+     R_ERR_CODE_MACRO_ERR_MASK)
+
+REG32(CSR0_REGWEN, 0x0u)
+    FIELD(CSR0_REGWEN, FIELD0, 0u, 1u)
+REG32(CSR1, 0x4u)
+    FIELD(CSR1, FIELD0, 0u, 8u)
+    FIELD(CSR1, FIELD1, 8u, 5u)
+REG32(CSR2, 0x8u)
+    FIELD(CSR2, FIELD0, 0u, 1u)
+    FIELD(CSR2, FIELD1, 1u, 1u)
+    FIELD(CSR2, FIELD2, 2u, 1u)
+    FIELD(CSR2, FIELD3, 3u, 1u)
+    FIELD(CSR2, FIELD4, 4u, 1u)
+    FIELD(CSR2, FIELD5, 5u, 1u)
+    FIELD(CSR2, FIELD6, 6u, 1u)
+    FIELD(CSR2, FIELD7, 7u, 1u)
+REG32(CSR3, 0xcu)
+    FIELD(CSR3, FIELD0, 0u, 4u)
+    FIELD(CSR3, FIELD1, 4u, 4u)
+    FIELD(CSR3, FIELD2, 8u, 3u)
+    FIELD(CSR3, FIELD3, 11u, 3u)
+    FIELD(CSR3, FIELD4, 14u, 3u)
+    FIELD(CSR3, FIELD5, 17u, 3u)
+    FIELD(CSR3, FIELD6, 20u, 1u)
+    FIELD(CSR3, FIELD7, 21u, 3u)
+    FIELD(CSR3, FIELD8, 24u, 2u)
+    FIELD(CSR3, FIELD9, 26u, 2u)
+REG32(CSR4, 0x10u)
+    FIELD(CSR4, FIELD0, 0u, 3u)
+    FIELD(CSR4, FIELD1, 3u, 3u)
+    FIELD(CSR4, FIELD2, 6u, 3u)
+    FIELD(CSR4, FIELD3, 9u, 3u)
+REG32(CSR5, 0x14u)
+    FIELD(CSR5, FIELD0, 0u, 3u)
+    FIELD(CSR5, FIELD1, 3u, 2u)
+    FIELD(CSR5, FIELD2, 5u, 9u)
+    FIELD(CSR5, FIELD3, 14u, 5u)
+    FIELD(CSR5, FIELD4, 19u, 4u)
+REG32(CSR6, 0x18u)
+    FIELD(CSR6, FIELD0, 0u, 3u)
+    FIELD(CSR6, FIELD1, 3u, 3u)
+    FIELD(CSR6, FIELD2, 6u, 8u)
+    FIELD(CSR6, FIELD3, 14u, 3u)
+    FIELD(CSR6, FIELD4, 17u, 2u)
+    FIELD(CSR6, FIELD5, 19u, 2u)
+    FIELD(CSR6, FIELD6, 21u, 2u)
+    FIELD(CSR6, FIELD7, 23u, 1u)
+    FIELD(CSR6, FIELD8, 24u, 1u)
+REG32(CSR7, 0x1cu)
+    FIELD(CSR7, FIELD0, 0u, 8u)
+    FIELD(CSR7, FIELD1, 8u, 9u)
+REG32(CSR8, 0x20u)
+REG32(CSR9, 0x24u)
+REG32(CSR10, 0x28u)
+REG32(CSR11, 0x2cu)
+REG32(CSR12, 0x30u)
+    FIELD(CSR12, FIELD0, 0u, 10u)
+REG32(CSR13, 0x34u)
+    FIELD(CSR13, FIELD0, 0u, 20u)
+    FIELD(CSR13, FIELD1, 20u, 1u)
+REG32(CSR14, 0x38u)
+    FIELD(CSR14, FIELD0, 0u, 8u)
+    FIELD(CSR14, FIELD1, 8u, 1u)
+REG32(CSR15, 0x3cu)
+    FIELD(CSR15, FIELD0, 0u, 8u)
+    FIELD(CSR15, FIELD1, 8u, 1u)
+REG32(CSR16, 0x40u)
+    FIELD(CSR16, FIELD0, 0u, 8u)
+    FIELD(CSR16, FIELD1, 8u, 1u)
+REG32(CSR17, 0x44u)
+    FIELD(CSR17, FIELD0, 0u, 8u)
+    FIELD(CSR17, FIELD1, 8u, 1u)
+REG32(CSR18, 0x48u)
+    FIELD(CSR18, FIELD0, 0u, 1u)
+REG32(CSR19, 0x4cu)
+    FIELD(CSR19, FIELD0, 0u, 1u)
+REG32(CSR20, 0x50u)
+    FIELD(CSR20, FIELD0, 0u, 1u)
+    FIELD(CSR20, FIELD1, 1u, 1u)
+    FIELD(CSR20, FIELD2, 2u, 1u)
+
+#define REG_NUM_BANKS 2u
+#define REG_PAGES_PER_BANK 256u
+#define REG_BUS_PGM_RES_BYTES 64u
+#define REG_PAGE_WIDTH 8u
+#define REG_BANK_WIDTH 1u
+#define NUM_REGIONS 8u
+#define NUM_INFO_TYPES 3u
+#define NUM_INFOS0 10u
+#define NUM_INFOS1 1u
+#define NUM_INFOS2 2u
+#define WORDS_PER_PAGE 256u
+#define BYTES_PER_WORD 8u
+#define BYTES_PER_PAGE 0x800u /* 2048u */
+#define BYTES_PER_BANK 0x80000u /* 524288u */
+#define EXEC_EN 0xa26a38f7u /* 2724870391u */
+#define MAX_FIFO_DEPTH 16u
+#define MAX_FIFO_WIDTH 5u
+#define MAX_INFO_PART_COUNT 12u
+#define NUM_ALERTS 5u
+
+/* clang-format on */
+
+typedef enum {
+    LC_PHASE_SEED,
+    LC_PHASE_RMA,
+    LC_PHASE_NONE,
+    LC_PHASE_INVALID
+} OtFlashLifeCyclePhase;
+
+/*
+ * todo: init is a command handled by the lcmgr and should not be treated the
+ * same as other ops (each SW-commanded `INIT` operation can lead to multiple
+ * HW flash program operations for example).
+ *
+ * this enum should be removed and everything using it should be refactored
+ * to directly use s->op.kind (OtFlashControlOperation) instead.
+ */
+typedef enum {
+    OP_NONE,
+    OP_INIT,
+    OP_READ,
+    OP_PROG,
+    OP_ERASE,
+} OtFlashOperation;
+
+typedef enum {
+    CONTROL_OP_READ = 0x0,
+    CONTROL_OP_PROG = 0x1,
+    CONTROL_OP_ERASE = 0x2,
+} OtFlashControlOperation;
+
+typedef enum {
+    ERASE_SEL_PAGE = 0x0,
+    ERASE_SEL_BANK = 0x1,
+} OtFlashControlEraseSelection;
+
+typedef enum {
+    PROG_SEL_NORMAL = 0x0,
+    PROG_SEL_REPAIR = 0x1,
+} OtFlashControlProgramSelection;
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_RD_FIFO)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(DIS),
+    REG_NAME_ENTRY(EXEC),
+    REG_NAME_ENTRY(INIT),
+    REG_NAME_ENTRY(CTRL_REGWEN),
+    REG_NAME_ENTRY(CONTROL),
+    REG_NAME_ENTRY(ADDR),
+    REG_NAME_ENTRY(PROG_TYPE_EN),
+    REG_NAME_ENTRY(ERASE_SUSPEND),
+    REG_NAME_ENTRY(REGION_CFG_REGWEN_0),
+    REG_NAME_ENTRY(REGION_CFG_REGWEN_1),
+    REG_NAME_ENTRY(REGION_CFG_REGWEN_2),
+    REG_NAME_ENTRY(REGION_CFG_REGWEN_3),
+    REG_NAME_ENTRY(REGION_CFG_REGWEN_4),
+    REG_NAME_ENTRY(REGION_CFG_REGWEN_5),
+    REG_NAME_ENTRY(REGION_CFG_REGWEN_6),
+    REG_NAME_ENTRY(REGION_CFG_REGWEN_7),
+    REG_NAME_ENTRY(MP_REGION_CFG_0),
+    REG_NAME_ENTRY(MP_REGION_CFG_1),
+    REG_NAME_ENTRY(MP_REGION_CFG_2),
+    REG_NAME_ENTRY(MP_REGION_CFG_3),
+    REG_NAME_ENTRY(MP_REGION_CFG_4),
+    REG_NAME_ENTRY(MP_REGION_CFG_5),
+    REG_NAME_ENTRY(MP_REGION_CFG_6),
+    REG_NAME_ENTRY(MP_REGION_CFG_7),
+    REG_NAME_ENTRY(MP_REGION_0),
+    REG_NAME_ENTRY(MP_REGION_1),
+    REG_NAME_ENTRY(MP_REGION_2),
+    REG_NAME_ENTRY(MP_REGION_3),
+    REG_NAME_ENTRY(MP_REGION_4),
+    REG_NAME_ENTRY(MP_REGION_5),
+    REG_NAME_ENTRY(MP_REGION_6),
+    REG_NAME_ENTRY(MP_REGION_7),
+    REG_NAME_ENTRY(DEFAULT_REGION),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_0),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_1),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_2),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_3),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_4),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_5),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_6),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_7),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_8),
+    REG_NAME_ENTRY(BANK0_INFO0_REGWEN_9),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_0),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_1),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_2),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_3),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_4),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_5),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_6),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_7),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_8),
+    REG_NAME_ENTRY(BANK0_INFO0_PAGE_CFG_9),
+    REG_NAME_ENTRY(BANK0_INFO1_REGWEN),
+    REG_NAME_ENTRY(BANK0_INFO1_PAGE_CFG),
+    REG_NAME_ENTRY(BANK0_INFO2_REGWEN_0),
+    REG_NAME_ENTRY(BANK0_INFO2_REGWEN_1),
+    REG_NAME_ENTRY(BANK0_INFO2_PAGE_CFG_0),
+    REG_NAME_ENTRY(BANK0_INFO2_PAGE_CFG_1),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_0),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_1),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_2),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_3),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_4),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_5),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_6),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_7),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_8),
+    REG_NAME_ENTRY(BANK1_INFO0_REGWEN_9),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_0),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_1),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_2),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_3),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_4),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_5),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_6),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_7),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_8),
+    REG_NAME_ENTRY(BANK1_INFO0_PAGE_CFG_9),
+    REG_NAME_ENTRY(BANK1_INFO1_REGWEN),
+    REG_NAME_ENTRY(BANK1_INFO1_PAGE_CFG),
+    REG_NAME_ENTRY(BANK1_INFO2_REGWEN_0),
+    REG_NAME_ENTRY(BANK1_INFO2_REGWEN_1),
+    REG_NAME_ENTRY(BANK1_INFO2_PAGE_CFG_0),
+    REG_NAME_ENTRY(BANK1_INFO2_PAGE_CFG_1),
+    REG_NAME_ENTRY(HW_INFO_CFG_OVERRIDE),
+    REG_NAME_ENTRY(BANK_CFG_REGWEN),
+    REG_NAME_ENTRY(MP_BANK_CFG_SHADOWED),
+    REG_NAME_ENTRY(OP_STATUS),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(DEBUG_STATE),
+    REG_NAME_ENTRY(ERR_CODE),
+    REG_NAME_ENTRY(STD_FAULT_STATUS),
+    REG_NAME_ENTRY(FAULT_STATUS),
+    REG_NAME_ENTRY(ERR_ADDR),
+    REG_NAME_ENTRY(ECC_SINGLE_ERR_CNT),
+    REG_NAME_ENTRY(ECC_SINGLE_ERR_ADDR_0),
+    REG_NAME_ENTRY(ECC_SINGLE_ERR_ADDR_1),
+    REG_NAME_ENTRY(PHY_ALERT_CFG),
+    REG_NAME_ENTRY(PHY_STATUS),
+    REG_NAME_ENTRY(SCRATCH),
+    REG_NAME_ENTRY(FIFO_LVL),
+    REG_NAME_ENTRY(FIFO_RST),
+    REG_NAME_ENTRY(CURR_FIFO_LVL),
+    REG_NAME_ENTRY(PROG_FIFO),
+    REG_NAME_ENTRY(RD_FIFO),
+};
+#undef REG_NAME_ENTRY
+
+#define R_LAST_CSR (R_CSR20)
+#define CSRS_COUNT (R_LAST_CSR + 1u)
+#define CSRS_SIZE  (CSRS_COUNT * sizeof(uint32_t))
+#define CSR_NAME(_reg_) \
+    ((((_reg_) < CSRS_COUNT) && CSR_NAMES[_reg_]) ? CSR_NAMES[_reg_] : "?")
+
+#define CSR_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *CSR_NAMES[CSRS_COUNT] = {
+    CSR_NAME_ENTRY(CSR0_REGWEN), CSR_NAME_ENTRY(CSR1),  CSR_NAME_ENTRY(CSR2),
+    CSR_NAME_ENTRY(CSR3),        CSR_NAME_ENTRY(CSR4),  CSR_NAME_ENTRY(CSR5),
+    CSR_NAME_ENTRY(CSR6),        CSR_NAME_ENTRY(CSR7),  CSR_NAME_ENTRY(CSR8),
+    CSR_NAME_ENTRY(CSR9),        CSR_NAME_ENTRY(CSR10), CSR_NAME_ENTRY(CSR11),
+    CSR_NAME_ENTRY(CSR12),       CSR_NAME_ENTRY(CSR13), CSR_NAME_ENTRY(CSR14),
+    CSR_NAME_ENTRY(CSR15),       CSR_NAME_ENTRY(CSR16), CSR_NAME_ENTRY(CSR17),
+    CSR_NAME_ENTRY(CSR18),       CSR_NAME_ENTRY(CSR19), CSR_NAME_ENTRY(CSR20),
+};
+#undef CSR_NAME_ENTRY
+
+#define FLASH_NAME_ENTRY(_st_) [_st_] = stringify(_st_)
+
+static const char *LC_PHASE_NAMES[] = {
+    FLASH_NAME_ENTRY(LC_PHASE_SEED),
+    FLASH_NAME_ENTRY(LC_PHASE_RMA),
+    FLASH_NAME_ENTRY(LC_PHASE_NONE),
+    FLASH_NAME_ENTRY(LC_PHASE_INVALID),
+};
+
+static const char *OP_NAMES[] = {
+    FLASH_NAME_ENTRY(OP_NONE),  FLASH_NAME_ENTRY(OP_INIT),
+    FLASH_NAME_ENTRY(OP_READ),  FLASH_NAME_ENTRY(OP_PROG),
+    FLASH_NAME_ENTRY(OP_ERASE),
+};
+
+static const char *CONTROL_OP_NAMES[] = {
+    FLASH_NAME_ENTRY(CONTROL_OP_READ),
+    FLASH_NAME_ENTRY(CONTROL_OP_PROG),
+    FLASH_NAME_ENTRY(CONTROL_OP_ERASE),
+};
+
+static const char *ERASE_SELECTION_NAMES[] = {
+    FLASH_NAME_ENTRY(ERASE_SEL_PAGE),
+    FLASH_NAME_ENTRY(ERASE_SEL_BANK),
+};
+
+static const char *PROGRAM_SELECTION_NAMES[] = {
+    FLASH_NAME_ENTRY(PROG_SEL_NORMAL),
+    FLASH_NAME_ENTRY(PROG_SEL_REPAIR),
+};
+
+#undef FLASH_NAME_ENTRY
+
+#define LC_PHASE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(LC_PHASE_NAMES) ? \
+         LC_PHASE_NAMES[(_st_)] : \
+         "?")
+
+#define OP_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(OP_NAMES) ? OP_NAMES[(_st_)] : "?")
+
+#define CONTROL_OP_NAME(_st_) \
+    ((unsigned)(_st_) < ARRAY_SIZE(CONTROL_OP_NAMES) ? \
+         CONTROL_OP_NAMES[(_st_)] : \
+         "?")
+
+#define ERASE_NAME(_st_) \
+    ((unsigned)(_st_) < ARRAY_SIZE(ERASE_SELECTION_NAMES) ? \
+         ERASE_SELECTION_NAMES[(_st_)] : \
+         "?")
+
+#define PROGRAM_NAME(_st_) \
+    ((unsigned)(_st_) < ARRAY_SIZE(PROGRAM_SELECTION_NAMES) ? \
+         PROGRAM_SELECTION_NAMES[(_st_)] : \
+         "?")
+
+#define SECRET_NAME_ENTRY(_st_) [FLASH_KEYMGR_SECRET_##_st_] = stringify(_st_)
+
+static const char *FLASH_KEYMGR_SECRET_NAMES[] = {
+    SECRET_NAME_ENTRY(CREATOR_SEED),
+    SECRET_NAME_ENTRY(OWNER_SEED),
+};
+
+#undef SECRET_NAME_ENTRY
+#define FLASH_KEYMGR_SECRET_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(FLASH_KEYMGR_SECRET_NAMES) ? \
+         FLASH_KEYMGR_SECRET_NAMES[(_st_)] : \
+         "?")
+
+/**
+ * Bank 0 information partition type 0 pages.
+ *
+ * (InfoPageFactoryId,            0x9dc41c33, 0, 0)
+ * (InfoPageCreatorSecret,        0xf56af4bb, 0, 1)
+ * (InfoPageOwnerSecret,          0x10adc6aa, 0, 2)
+ * (InfoPageWaferAuthSecret,      0x118b5dbb, 0, 3)
+ * (InfoPageBank0Type0Page4,      0xad3b5bee, 0, 4)
+ * (InfoPageBank0Type0Page5,      0xa4f6f6c3, 0, 5)
+ * (InfoPageOwnerReserved0,       0xf646f11b, 0, 6)
+ * (InfoPageOwnerReserved1,       0x6c86d980, 0, 7)
+ * (InfoPageOwnerReserved2,       0xdd7f34dc, 0, 8)
+ * (InfoPageOwnerReserved3,       0x5f07277e, 0, 9)
+ *
+ * Bank 1 information partition type 0 pages.
+ *
+ * (InfoPageBootData0,            0xfa38c9f6, 1, 0)
+ * (InfoPageBootData1,            0x389c449e, 1, 1)
+ * (InfoPageOwnerSlot0,           0x238cf15c, 1, 2)
+ * (InfoPageOwnerSlot1,           0xad886d3b, 1, 3)
+ * (InfoPageBank1Type0Page4,      0x7dfbdf9b, 1, 4)
+ * (InfoPageBank1Type0Page5,      0xad5dd31d, 1, 5)
+ * (InfoPageCreatorCertificate,   0xe3ffac86, 1, 6)
+ * (InfoPageBootServices,         0xf4f48c3d, 1, 7)
+ * (InfoPageOwnerCerificate0,     0x9fbb840e, 1, 8)
+ * (InfoPageOwnerCerificate1,     0xec309461, 1, 9)
+ */
+
+#define xtrace_ot_flash_error(_id_, _msg_) \
+    trace_ot_flash_error(_id_, __func__, __LINE__, _msg_)
+#define xtrace_ot_flash_info(_id_, _msg_, _val_) \
+    trace_ot_flash_info(_id_, __func__, __LINE__, _msg_, _val_)
+
+enum {
+    BIN_APP_OTRE,
+    BIN_APP_OTB0,
+    BIN_APP_COUNT,
+};
+
+#define OP_INIT_DURATION_NS     10000u /* 10 us */
+#define ELFNAME_SIZE            256u
+#define OT_FLASH_READ_FIFO_SIZE 16u
+#define OT_FLASH_PROG_FIFO_SIZE 16u
+#define BUS_PGM_RES             ((REG_BUS_PGM_RES_BYTES) / (OT_TL_UL_D_WIDTH_BYTES))
+
+#define LC_BROADCAST_DELAY 200u /* 200 ns */
+
+#define WORD_ALIGN_ADDR(_addr_) ((_addr_) & ~3u)
+
+typedef struct {
+    unsigned offset; /* storage offset in bank, relative to first info page */
+    unsigned size; /* size in bytes of the partition */
+} OtFlashInfoPart;
+
+/**
+ * See `ot_flash_update_info_page_qualification`. These pages have additional
+ * restricted access based upon the current incoming lc_ctrl lifecycle signals.
+ */
+typedef enum {
+    FLASH_QUAL_INFO_PAGE_CREATOR = 1,
+    FLASH_QUAL_INFO_PAGE_OWNER = 2,
+    FLASH_QUAL_INFO_PAGE_ISOLATED = 3,
+} OtFlashQualifiedInfoPage;
+
+typedef union {
+    unsigned bitmap;
+    struct {
+        unsigned en:1;
+        unsigned rd_en:1;
+        unsigned prog_en:1;
+        unsigned erase_en:1;
+        unsigned scramble_en:1;
+        unsigned ecc_en:1;
+        unsigned he_en:1;
+    };
+} OtFlashPropertyCfg;
+
+static_assert(sizeof(OtFlashPropertyCfg) == sizeof(unsigned int),
+              "The flash property config should fit in an unsigned int.");
+
+typedef struct {
+    uint32_t *storage; /* overall buffer for the storage backend */
+    uint32_t *data; /* data buffer (all partitions/banks) */
+    uint32_t *info; /* info buffer (all partitions/banks) */
+    unsigned bank_count; /* count of banks */
+    unsigned size; /* overall storage size in bytes (excl. header) */
+    unsigned data_size; /* data buffer size of a bank in bytes */
+    unsigned info_size; /* info buffer size of a bank in bytes */
+    unsigned info_part_count; /* count of info partition (per bank) */
+    OtFlashInfoPart info_parts[MAX_INFO_PART_COUNT];
+} OtFlashStorage;
+
+typedef struct {
+    char magic[4u]; /* vFSH */
+    uint32_t hlength; /* count of header bytes after this point */
+    uint32_t version; /* version of the header */
+    uint8_t bank; /* count of bank */
+    uint8_t info; /* count of info partitions per bank */
+    uint16_t page; /* count of pages per bank */
+    uint32_t psize; /* page size in bytes */
+    uint8_t ipp[MAX_INFO_PART_COUNT]; /* count of pages for each info part */
+} OtFlashBackendHeader;
+
+typedef struct {
+    uint32_t *data;
+    uint32_t capacity;
+    uint32_t head;
+    uint32_t num;
+} OtFlashFifo;
+
+typedef struct {
+    QEMUTimer *timer;
+    uint16_t incoming_signal_bm; /* each bit tells if signal needs handling */
+    uint16_t incoming_level_bm; /* level (0/1) of the incoming signals */
+    uint16_t current_level_bm; /* current (latched) level of all signals */
+} OtFlashLcBroadcast;
+
+static_assert(OT_FLASH_LC_BROADCAST_COUNT < 8 * sizeof(uint16_t),
+              "Invalid OT_FLASH_LC_BROADCAST_COUNT");
+
+struct OtFlashState {
+    SysBusDevice parent_obj;
+
+    struct {
+        MemoryRegion regs;
+        MemoryRegion csrs;
+        MemoryRegion mem;
+    } mmio;
+    QEMUTimer *op_delay; /* simulated long lasting operation */
+    IbexIRQ irqs[PARAM_NUM_IRQS];
+    IbexIRQ alerts[PARAM_NUM_ALERTS];
+
+    uint32_t *regs;
+    uint32_t *csrs;
+
+    /* "sticky" alerts that should stay signaled after firing */
+    uint32_t latched_alerts;
+
+    OtFlashKeyMgrSecret keymgr_seeds[FLASH_KEYMGR_SECRET_COUNT];
+
+    struct {
+        OtFlashOperation kind;
+        unsigned count;
+        unsigned remaining;
+        unsigned address;
+        unsigned info_sel;
+        bool info_part;
+        bool prog_sel;
+        bool erase_sel;
+        bool failed;
+        bool hw; /* hw- or sw-requested operation? */
+    } op;
+    OtFlashLifeCyclePhase phase; /* HW LC phase for memory protection / RMA */
+    OtFlashLcBroadcast lc_broadcast;
+    OtFifo32 rd_fifo;
+    OtFifo32 prog_fifo;
+    OtFlashStorage flash;
+
+    /*
+     * HW and SW operations share a program FIFO, but read to separate
+     * locations (e.g. keymgr keys, RMA requests).
+     */
+    OtFifo32 hw_rd_fifo;
+
+    char *hexstr;
+
+    /* properties */
+    char *ot_id;
+    BlockBackend *blk; /* Flash backend */
+    OtVMapperState *vmapper; /* to disable execution from flash */
+    bool no_mem_prot; /* Flag to disable mem protection features */
+    bool fatal_escalate;
+};
+
+#define OT_FLASH_HEXSTR_SIZE (FLASH_SEED_BYTES * 2u + 2u)
+
+#define ot_flash_dump_bigint(_s_, _b_, _l_) \
+    ot_common_lhexdump(_b_, _l_, true, (_s_)->hexstr, OT_FLASH_HEXSTR_SIZE)
+
+/* Flash memory protection rules */
+
+static const OtFlashPropertyCfg OT_FLASH_CFG_ALLOW_READ = {
+    .en = true,
+    .rd_en = true,
+    .prog_en = false,
+    .erase_en = false,
+    .scramble_en = true,
+    .ecc_en = true,
+    .he_en = true,
+};
+
+static const OtFlashPropertyCfg OT_FLASH_CFG_ALLOW_READ_PROG_ERASE = {
+    .en = true,
+    .rd_en = true,
+    .prog_en = true,
+    .erase_en = true,
+    .scramble_en = true,
+    .ecc_en = true,
+    .he_en = true,
+};
+
+static const OtFlashPropertyCfg OT_FLASH_CFG_INFO_DISABLE = {
+    .en = false,
+    .rd_en = false,
+    .prog_en = false,
+    .erase_en = false,
+    .scramble_en = false,
+    .ecc_en = false,
+    .he_en = false,
+};
+
+typedef struct {
+    /* the page to give HW access to */
+    unsigned bank;
+    unsigned info_partition;
+    unsigned page;
+    OtFlashLifeCyclePhase phase; /* the phase this rule applies in */
+    OtFlashPropertyCfg cfg; /* cfg to apply to the page */
+} OtFlashHwInfoPageRule;
+
+static const OtFlashHwInfoPageRule OT_FLASH_HW_INFO_PAGE_RULES[] = {
+    {
+        .bank = FLASH_SEED_BANK,
+        .info_partition = FLASH_SEED_INFO_PARTITION,
+        .page = FLASH_QUAL_INFO_PAGE_CREATOR,
+        .phase = LC_PHASE_SEED,
+        .cfg = OT_FLASH_CFG_ALLOW_READ,
+    },
+    {
+        .bank = FLASH_SEED_BANK,
+        .info_partition = FLASH_SEED_INFO_PARTITION,
+        .page = FLASH_QUAL_INFO_PAGE_OWNER,
+        .phase = LC_PHASE_SEED,
+        .cfg = OT_FLASH_CFG_ALLOW_READ,
+    },
+    {
+        .bank = FLASH_SEED_BANK,
+        .info_partition = FLASH_SEED_INFO_PARTITION,
+        .page = FLASH_QUAL_INFO_PAGE_CREATOR,
+        .phase = LC_PHASE_RMA,
+        .cfg = OT_FLASH_CFG_ALLOW_READ_PROG_ERASE,
+    },
+    {
+        .bank = FLASH_SEED_BANK,
+        .info_partition = FLASH_SEED_INFO_PARTITION,
+        .page = FLASH_QUAL_INFO_PAGE_OWNER,
+        .phase = LC_PHASE_RMA,
+        .cfg = OT_FLASH_CFG_ALLOW_READ_PROG_ERASE,
+    },
+    {
+        .bank = FLASH_SEED_BANK,
+        .info_partition = FLASH_SEED_INFO_PARTITION,
+        .page = FLASH_QUAL_INFO_PAGE_ISOLATED,
+        .phase = LC_PHASE_RMA,
+        .cfg = OT_FLASH_CFG_ALLOW_READ_PROG_ERASE,
+    },
+};
+
+static void ot_flash_update_irqs(OtFlashState *s)
+{
+    uint32_t level = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+    trace_ot_flash_irqs(s->ot_id, s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE],
+                        level);
+    for (unsigned ix = 0u; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_flash_update_alerts(OtFlashState *s)
+{
+    uint32_t levels = s->regs[R_ALERT_TEST];
+
+    levels |= s->latched_alerts;
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        int level = (int)((levels >> ix) & 0x1u);
+        if (level != ibex_irq_get_level(&s->alerts[ix])) {
+            trace_ot_flash_update_alert(s->ot_id,
+                                        ibex_irq_get_level(&s->alerts[ix]),
+                                        level);
+        }
+        ibex_irq_set(&s->alerts[ix], level);
+    }
+
+    /* alert test is transient */
+    if (s->regs[R_ALERT_TEST]) {
+        s->regs[R_ALERT_TEST] = 0;
+
+        levels = s->latched_alerts;
+        for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+            int level = (int)((levels >> ix) & 0x1u);
+            if (level != ibex_irq_get_level(&s->alerts[ix])) {
+                trace_ot_flash_update_alert(s->ot_id,
+                                            ibex_irq_get_level(&s->alerts[ix]),
+                                            level);
+            }
+            ibex_irq_set(&s->alerts[ix], level);
+        }
+    }
+}
+
+static bool ot_flash_is_backend_writable(const OtFlashState *s)
+{
+    return (s->blk != NULL) && blk_is_writable(s->blk);
+}
+
+static bool ot_flash_write_backend(OtFlashState *s, const void *buffer,
+                                   unsigned offset, size_t size)
+{
+    /* NOLINTBEGIN(clang-analyzer-optin.core.EnumCastOutOfRange) */
+    return blk_pwrite(s->blk, (int64_t)(intptr_t)offset, (int64_t)size, buffer,
+                      (BdrvRequestFlags)0);
+    /* NOLINTEND(clang-analyzer-optin.core.EnumCastOutOfRange) */
+}
+
+static bool ot_flash_is_disabled(const OtFlashState *s)
+{
+    bool reg_dis = s->regs[R_DIS] != OT_MULTIBITBOOL4_FALSE;
+    bool lc_escalate_dis =
+        s->lc_broadcast.current_level_bm & BIT(OT_FLASH_LC_ESCALATE_EN);
+    return reg_dis || lc_escalate_dis;
+}
+
+static bool ot_flash_regs_is_wr_enabled(const OtFlashState *s, unsigned regwen)
+{
+    return (bool)(s->regs[regwen] & REGWEN_EN_MASK);
+}
+
+static void ot_flash_update_rd_watermark(OtFlashState *s)
+{
+    unsigned rd_watermark_level =
+        SHARED_FIELD_EX32(s->regs[R_FIFO_LVL], FIFO_LVL_RD);
+    unsigned lvl = ot_fifo32_num_used(&s->rd_fifo);
+
+    /* Read FIFO watermark generates an interrupt when the Read FIFO fills to
+    (equal to or greater than) the watermark level. */
+    if (lvl >= rd_watermark_level) {
+        s->regs[R_INTR_STATE] |= INTR_RD_LVL_MASK;
+    } else {
+        s->regs[R_INTR_STATE] &= ~INTR_RD_LVL_MASK;
+    }
+    trace_ot_flash_update_rd_watermark(s->ot_id, lvl, rd_watermark_level);
+    ot_flash_update_irqs(s);
+}
+
+static void ot_flash_update_prog_watermark(OtFlashState *s)
+{
+    unsigned prog_watermark_level =
+        SHARED_FIELD_EX32(s->regs[R_FIFO_LVL], FIFO_LVL_PROG);
+    unsigned lvl = ot_fifo32_num_used(&s->prog_fifo);
+
+    /* Prog FIFO watermark generates an interrupt when the Prog FIFO drains to
+    (equal to or less than) the watermark level. */
+    if (lvl <= prog_watermark_level) {
+        s->regs[R_INTR_STATE] |= INTR_PROG_LVL_MASK;
+    } else {
+        s->regs[R_INTR_STATE] &= ~INTR_PROG_LVL_MASK;
+    }
+    trace_ot_flash_update_prog_watermark(s->ot_id, lvl, prog_watermark_level);
+    ot_flash_update_irqs(s);
+}
+
+static bool ot_flash_is_initialized(const OtFlashState *s)
+{
+    return (bool)(s->regs[R_STATUS] & R_STATUS_INITIALIZED_MASK);
+}
+
+static bool ot_flash_fifo_in_reset(const OtFlashState *s)
+{
+    return (bool)s->regs[R_FIFO_RST];
+}
+
+static bool ot_flash_in_operation(const OtFlashState *s)
+{
+    return s->op.kind != OP_NONE;
+}
+
+static bool ot_flash_in_hw_operation(const OtFlashState *s)
+{
+    return s->op.kind != OP_NONE && s->op.hw;
+}
+
+static bool ot_flash_operation_ongoing(const OtFlashState *s)
+{
+    return s->op.kind != OP_NONE && s->op.count;
+}
+
+static void ot_flash_reset_rd_fifo(OtFlashState *s)
+{
+    ot_fifo32_reset(&s->rd_fifo);
+    s->regs[R_STATUS] |= R_STATUS_RD_EMPTY_MASK;
+    s->regs[R_STATUS] &= ~R_STATUS_RD_FULL_MASK;
+    s->regs[R_INTR_STATE] &= ~INTR_RD_FULL_MASK;
+    trace_ot_flash_reset_fifo(s->ot_id, "rd");
+    ot_flash_update_rd_watermark(s);
+}
+
+static void ot_flash_reset_prog_fifo(OtFlashState *s)
+{
+    ot_fifo32_reset(&s->prog_fifo);
+    s->regs[R_STATUS] |= R_STATUS_PROG_EMPTY_MASK;
+    s->regs[R_STATUS] &= ~R_STATUS_PROG_FULL_MASK;
+    s->regs[R_INTR_STATE] |= INTR_PROG_EMPTY_MASK;
+    trace_ot_flash_reset_fifo(s->ot_id, "prog");
+    ot_flash_update_prog_watermark(s);
+}
+
+static void ot_flash_set_error(OtFlashState *s, uint32_t ebit, uint32_t eaddr)
+{
+    if (ebit) {
+        if (s->op.hw) {
+            s->regs[R_FAULT_STATUS] |= ebit;
+            s->latched_alerts |= ALERT_FATAL_ERR_MASK;
+        } else {
+            s->regs[R_OP_STATUS] |= R_OP_STATUS_ERR_MASK;
+            s->regs[R_INTR_STATE] |= INTR_CORR_ERR_MASK;
+            s->regs[R_ERR_ADDR] = FIELD_DP32(0, ERR_ADDR, ERR_ADDR, eaddr);
+            s->regs[R_ERR_CODE] = ebit;
+            s->regs[R_ALERT_TEST] |= ALERT_RECOV_ERR_MASK;
+            ot_flash_update_irqs(s);
+        }
+        ot_flash_update_alerts(s);
+    }
+    trace_ot_flash_set_error(s->ot_id, OP_NAME(s->op.kind), s->op.hw, ebit,
+                             eaddr);
+}
+
+static void ot_flash_op_complete(OtFlashState *s)
+{
+    /*
+     * done is always signalled when the full operation is completed, even
+     * if there was an error at some point in the operation.
+     */
+    if (!s->op.hw) {
+        s->regs[R_OP_STATUS] |= R_OP_STATUS_DONE_MASK;
+        s->regs[R_INTR_STATE] |= INTR_OP_DONE_MASK;
+        ot_flash_update_irqs(s);
+        /* completing a sw op clears the remaining sw prog fifo */
+        ot_flash_reset_prog_fifo(s);
+    }
+    s->regs[R_CTRL_REGWEN] |= R_CTRL_REGWEN_EN_MASK;
+    trace_ot_flash_op_complete(s->ot_id, OP_NAME(s->op.kind), s->op.hw,
+                               !s->regs[R_ERR_CODE]);
+    s->op.kind = OP_NONE;
+}
+
+static uint32_t ot_flash_get_info_page_cfg_reg(
+    OtFlashState *s, unsigned bank, unsigned info_partition, unsigned page)
+{
+    switch (bank) {
+    case 0u:
+        switch (info_partition) {
+        case 0u:
+            return R_BANK0_INFO0_PAGE_CFG_0 + page;
+        case 1u:
+            return R_BANK0_INFO1_PAGE_CFG;
+        case 2u:
+            return R_BANK0_INFO2_PAGE_CFG_0 + page;
+        default:
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: invalid info partition: %u\n", __func__,
+                          s->ot_id, info_partition);
+            return 0u;
+        }
+    case 1u:
+        switch (info_partition) {
+        case 0u:
+            return R_BANK1_INFO0_PAGE_CFG_0 + page;
+        case 1u:
+            return R_BANK1_INFO1_PAGE_CFG;
+        case 2u:
+            return R_BANK1_INFO2_PAGE_CFG_0 + page;
+        default:
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: invalid info partition: %u\n", __func__,
+                          s->ot_id, info_partition);
+            return 0u;
+        }
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid bank: %d\n", __func__,
+                      s->ot_id, bank);
+        return 0u;
+    }
+}
+
+static OtFlashPropertyCfg ot_flash_get_hw_info_page_cfg(
+    OtFlashState *s, unsigned bank, unsigned info_partition, unsigned page)
+{
+    for (unsigned ix = 0; ix < ARRAY_SIZE(OT_FLASH_HW_INFO_PAGE_RULES); ++ix) {
+        const OtFlashHwInfoPageRule *rule = &OT_FLASH_HW_INFO_PAGE_RULES[ix];
+        if (bank == rule->bank && info_partition == rule->info_partition &&
+            page == rule->page && s->phase == rule->phase) {
+            return rule->cfg;
+        }
+    }
+    return OT_FLASH_CFG_INFO_DISABLE;
+}
+
+static OtFlashPropertyCfg ot_flash_get_info_page_reg_cfg(
+    const OtFlashState *s, uint32_t info_page_cfg_reg)
+{
+    unsigned en_mubi4 =
+        SHARED_FIELD_EX32(s->regs[info_page_cfg_reg], BANK_INFO_PAGE_CFG_EN);
+    unsigned rd_en_mubi4 =
+        SHARED_FIELD_EX32(s->regs[info_page_cfg_reg], BANK_INFO_PAGE_CFG_RD_EN);
+    unsigned prog_en_mubi4 = SHARED_FIELD_EX32(s->regs[info_page_cfg_reg],
+                                               BANK_INFO_PAGE_CFG_PROG_EN);
+    unsigned erase_en_mubi4 = SHARED_FIELD_EX32(s->regs[info_page_cfg_reg],
+                                                BANK_INFO_PAGE_CFG_ERASE_EN);
+    unsigned scramble_en_mubi4 =
+        SHARED_FIELD_EX32(s->regs[info_page_cfg_reg],
+                          BANK_INFO_PAGE_CFG_SCRAMBLE_EN);
+    unsigned ecc_en_mubi4 = SHARED_FIELD_EX32(s->regs[info_page_cfg_reg],
+                                              BANK_INFO_PAGE_CFG_ECC_EN);
+    unsigned he_en_mubi4 =
+        SHARED_FIELD_EX32(s->regs[info_page_cfg_reg], BANK_INFO_PAGE_CFG_HE_EN);
+
+    return (OtFlashPropertyCfg){
+        .en = (uint8_t)(en_mubi4 == OT_MULTIBITBOOL4_TRUE),
+        .rd_en = (uint8_t)(rd_en_mubi4 == OT_MULTIBITBOOL4_TRUE),
+        .prog_en = (uint8_t)(prog_en_mubi4 == OT_MULTIBITBOOL4_TRUE),
+        .erase_en = (uint8_t)(erase_en_mubi4 == OT_MULTIBITBOOL4_TRUE),
+        .scramble_en = (uint8_t)(scramble_en_mubi4 == OT_MULTIBITBOOL4_TRUE),
+        .ecc_en = (uint8_t)(ecc_en_mubi4 == OT_MULTIBITBOOL4_TRUE),
+        .he_en = (uint8_t)(he_en_mubi4 == OT_MULTIBITBOOL4_TRUE),
+    };
+}
+
+/**
+ * Update the current SW register configuration for an info page based on
+ * additional "qualification" protections, which limit access to certain flash
+ * info pages holding secrets in certain lc_ctrl lifecycle states.
+ *
+ * This will determine any additional protections for info pages and mask the
+ * given config, only enabling an operation if both the SW configuration and
+ * the qualifications allow it.
+ *
+ * See also:
+ * https://opentitan.org/book/hw/top_earlgrey/ip_autogen/flash_ctrl/
+ * index.html#secret-information-partitions
+ *
+ * @s The flash device
+ * @bank The bank being accessed
+ * @info_partition The info partition being accessed
+ * @page The page being accessed
+ * @cfg The configuration to update/mask (outparam).
+ */
+static void ot_flash_update_info_page_qualification(
+    const OtFlashState *s, unsigned bank, unsigned info_partition,
+    unsigned page, OtFlashPropertyCfg *cfg)
+{
+    OtFlashPropertyCfg qual;
+    qual.scramble_en = true;
+    qual.ecc_en = true;
+    qual.he_en = true;
+
+    /* extra quals depend on lc_ctrl broadcast signals */
+    bool creator_en = s->lc_broadcast.current_level_bm &
+                      BIT(OT_FLASH_LC_CREATOR_SEED_SW_RW_EN);
+    bool owner_en =
+        s->lc_broadcast.current_level_bm & BIT(OT_FLASH_LC_OWNER_SEED_SW_RW_EN);
+    bool isolated_rd_en =
+        s->lc_broadcast.current_level_bm & BIT(OT_FLASH_LC_ISO_PART_SW_RD_EN);
+    bool isolated_wr_en =
+        s->lc_broadcast.current_level_bm & BIT(OT_FLASH_LC_ISO_PART_SW_WR_EN);
+
+    /* retrieve additional qualifications for pages containing secrets */
+    if (bank != FLASH_SEED_BANK ||
+        info_partition != FLASH_SEED_INFO_PARTITION) {
+        return;
+    }
+    switch (page) {
+    case FLASH_QUAL_INFO_PAGE_CREATOR:
+        qual.en = creator_en;
+        qual.rd_en = creator_en;
+        qual.prog_en = creator_en;
+        qual.erase_en = creator_en;
+        break;
+    case FLASH_QUAL_INFO_PAGE_OWNER:
+        qual.en = owner_en;
+        qual.rd_en = owner_en;
+        qual.prog_en = owner_en;
+        qual.erase_en = owner_en;
+        break;
+    case FLASH_QUAL_INFO_PAGE_ISOLATED:
+        qual.en = true;
+        qual.rd_en = isolated_rd_en;
+        qual.prog_en = isolated_wr_en;
+        qual.erase_en = isolated_wr_en;
+        break;
+    default:
+        return;
+    }
+
+    /* merge the reg cfg and the page qualifications */
+    uint8_t prev_cfg = cfg->bitmap;
+    cfg->bitmap &= qual.bitmap;
+    trace_ot_flash_merge_info_qual(s->ot_id, bank, info_partition, page,
+                                   prev_cfg, qual.bitmap, cfg->bitmap);
+}
+
+static bool ot_flash_info_page_cfg_op_enabled(const OtFlashState *s,
+                                              const OtFlashPropertyCfg *cfg)
+{
+    switch (s->op.kind) {
+    case OP_READ:
+        return cfg->rd_en;
+    case OP_PROG:
+        return cfg->prog_en;
+    case OP_ERASE:
+        return cfg->erase_en;
+    case OP_NONE:
+        xtrace_ot_flash_error(s->ot_id, "cannot check mp without operation");
+        return false;
+    default:
+        xtrace_ot_flash_error(s->ot_id, "unsupported operation?");
+        return false;
+    }
+}
+
+static bool
+ot_flash_mp_region_cfg_op_enabled(const OtFlashState *s, uint32_t mp_cfg_reg)
+{
+    unsigned en_field;
+    switch (s->op.kind) {
+    case OP_READ:
+        en_field = SHARED_FIELD_EX32(s->regs[mp_cfg_reg], MP_REGION_CFG_RD_EN);
+        break;
+    case OP_PROG:
+        en_field =
+            SHARED_FIELD_EX32(s->regs[mp_cfg_reg], MP_REGION_CFG_PROG_EN);
+        break;
+    case OP_ERASE:
+        en_field =
+            SHARED_FIELD_EX32(s->regs[mp_cfg_reg], MP_REGION_CFG_ERASE_EN);
+        break;
+    case OP_NONE:
+        xtrace_ot_flash_error(s->ot_id, "cannot check mp without operation");
+        return false;
+    default:
+        xtrace_ot_flash_error(s->ot_id, "unsupported operation?");
+        return false;
+    }
+    return en_field == OT_MULTIBITBOOL4_TRUE;
+}
+
+static bool ot_flash_default_region_cfg_op_enabled(const OtFlashState *s)
+{
+    unsigned en_field;
+    switch (s->op.kind) {
+    case OP_READ:
+        en_field = FIELD_EX32(s->regs[R_DEFAULT_REGION], DEFAULT_REGION, RD_EN);
+        break;
+    case OP_PROG:
+        en_field =
+            FIELD_EX32(s->regs[R_DEFAULT_REGION], DEFAULT_REGION, PROG_EN);
+        break;
+    case OP_ERASE:
+        en_field =
+            FIELD_EX32(s->regs[R_DEFAULT_REGION], DEFAULT_REGION, ERASE_EN);
+        break;
+    case OP_NONE:
+        xtrace_ot_flash_error(s->ot_id, "cannot check mp without operation");
+        return false;
+    default:
+        xtrace_ot_flash_error(s->ot_id, "unsupported operation?");
+        return false;
+    }
+    return en_field == OT_MULTIBITBOOL4_TRUE;
+}
+
+static bool ot_flash_can_erase_bank(const OtFlashState *s, unsigned bank)
+{
+    switch (bank) {
+    case 0u:
+        return (bool)FIELD_EX32(s->regs[R_MP_BANK_CFG_SHADOWED],
+                                MP_BANK_CFG_SHADOWED, ERASE_EN_0);
+    case 1u:
+        return (bool)FIELD_EX32(s->regs[R_MP_BANK_CFG_SHADOWED],
+                                MP_BANK_CFG_SHADOWED, ERASE_EN_1);
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: unknown bank %u for bank erase operation",
+                      __func__, s->ot_id, bank);
+        return false;
+    }
+}
+
+static unsigned ot_flash_next_info_address(OtFlashState *s)
+{
+    OtFlashStorage *storage = &s->flash;
+    unsigned bank_size = storage->data_size;
+    unsigned info_partition = s->op.info_sel;
+    uint32_t mp_err_ebit =
+        s->op.hw ? R_FAULT_STATUS_MP_ERR_MASK : R_ERR_CODE_MP_ERR_MASK;
+
+    /* offset the address by the number of processed ops to get next addr */
+    unsigned op_offset = (s->op.count - s->op.remaining) * sizeof(uint32_t);
+    unsigned op_address = s->op.address + op_offset;
+
+    if (info_partition >= storage->info_part_count) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid info partition: %u\n",
+                      __func__, s->ot_id, s->op.info_sel);
+        ot_flash_set_error(s, mp_err_ebit, op_address);
+        s->op.failed = true;
+        return op_address;
+    }
+
+    /* extract the bank & bank-relative address from the address */
+    unsigned bank = op_address / bank_size;
+    if (bank >= storage->bank_count) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid bank: %d\n", __func__,
+                      s->ot_id, bank);
+        ot_flash_set_error(s, mp_err_ebit, op_address);
+        s->op.failed = true;
+        return op_address;
+    }
+    unsigned address_in_bank = op_address % bank_size;
+    if (address_in_bank >= storage->info_parts[info_partition].size) {
+        /*
+         * Purposefuly do not check the whole transaction's address width here:
+         * the RTL only errors when it attempts to read an invalid address.
+         */
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: invalid address in partition: %u %u\n", __func__,
+                      s->ot_id, op_address, info_partition);
+        ot_flash_set_error(s, mp_err_ebit, op_address);
+        s->op.failed = true;
+        return op_address;
+    }
+
+    /* Retrieve the raw backend byte address in the info partitions. */
+    unsigned bank_offset = bank * storage->info_size;
+    unsigned info_part_offset = storage->info_parts[info_partition].offset;
+    unsigned address = address_in_bank + bank_offset + info_part_offset;
+    trace_ot_flash_info_part(s->ot_id, s->op.address, s->op.count,
+                             s->op.remaining, bank, info_partition, address);
+    if (s->no_mem_prot ||
+        (s->op.kind == OP_ERASE && s->op.erase_sel == ERASE_SEL_BANK)) {
+        return address;
+    }
+
+    unsigned page = address_in_bank / BYTES_PER_PAGE;
+
+    /*
+     * Check the matching info partition page configuration.
+     * For software reads, this depends on the config registers and any
+     * additional secret qualifiers. For hardware reads, this depends
+     * on the defined hardware rules & any HW overrides.
+     */
+    OtFlashPropertyCfg cfg;
+    if (s->op.hw) {
+        cfg = ot_flash_get_hw_info_page_cfg(s, bank, info_partition, page);
+        uint32_t override = s->regs[R_HW_INFO_CFG_OVERRIDE];
+        bool scramble_disable =
+            FIELD_EX32(override, HW_INFO_CFG_OVERRIDE, SCRAMBLE_DIS) ==
+            OT_MULTIBITBOOL4_TRUE;
+        bool ecc_disable = FIELD_EX32(override, HW_INFO_CFG_OVERRIDE,
+                                      ECC_DIS) == OT_MULTIBITBOOL4_TRUE;
+        cfg.scramble_en &= !scramble_disable;
+        cfg.ecc_en &= !ecc_disable;
+    } else {
+        uint32_t info_page_cfg_reg =
+            ot_flash_get_info_page_cfg_reg(s, bank, info_partition, page);
+        if (!info_page_cfg_reg) {
+            ot_flash_set_error(s, mp_err_ebit, op_address);
+            s->op.failed = true;
+            return address;
+        }
+        cfg = ot_flash_get_info_page_reg_cfg(s, info_page_cfg_reg);
+        ot_flash_update_info_page_qualification(s, bank, info_partition, page,
+                                                &cfg);
+    }
+
+    if (!cfg.en || !ot_flash_info_page_cfg_op_enabled(s, &cfg)) {
+        const char *op_type = (s->op.hw) ? "hardware" : "software";
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: %s operation %s on info page %u in partition %u of "
+            "bank %u is disabled by page config\n",
+            __func__, s->ot_id, op_type, OP_NAME(s->op.kind), page, bank,
+            info_partition);
+        ot_flash_set_error(s, mp_err_ebit, op_address);
+        s->op.failed = true;
+        return address;
+    }
+
+    return address;
+}
+
+static unsigned ot_flash_next_data_address(OtFlashState *s)
+{
+    OtFlashStorage *storage = &s->flash;
+    unsigned bank_size = storage->data_size;
+    uint32_t mp_err_ebit =
+        s->op.hw ? R_FAULT_STATUS_MP_ERR_MASK : R_ERR_CODE_MP_ERR_MASK;
+
+    /* offset the address by the number of proessed ops to get next addr */
+    unsigned op_offset = (s->op.count - s->op.remaining) * sizeof(uint32_t);
+    unsigned address = s->op.address + op_offset;
+    unsigned bank = address / bank_size;
+    if (bank >= storage->bank_count) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid bank: %d\n", __func__,
+                      s->ot_id, bank);
+        ot_flash_set_error(s, mp_err_ebit, address);
+        s->op.failed = true;
+        return address;
+    }
+    trace_ot_flash_data_part(s->ot_id, s->op.address, s->op.count,
+                             s->op.remaining, bank, address);
+
+    if (s->no_mem_prot ||
+        (s->op.kind == OP_ERASE && s->op.erase_sel == ERASE_SEL_BANK)) {
+        return address;
+    }
+
+    /*
+     * Hardware can only access the data pages in the RMA LC phase, at which
+     * point it has full access.
+     */
+    if (s->op.hw) {
+        if (s->phase == LC_PHASE_RMA) {
+            return address;
+        }
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: hardware operation %s on data pages is not permitted "
+            "in the %s flash_ctrl lc phase\n",
+            __func__, s->ot_id, OP_NAME(s->op.kind), LC_PHASE_NAME(s->phase));
+        ot_flash_set_error(s, mp_err_ebit, address);
+        s->op.failed = true;
+        return address;
+    }
+
+    /*
+     * Check through the memory protection regions 0->9, and see if the current
+     * page falls within a region. If so, and it is enabled, apply its perms.
+     * Otherwise apply the default region's permissions. Note that MP region
+     * page indexes are cumulative across banks.
+     *
+     * If any two MP regions overlap, the lower index region has priority.
+     */
+    unsigned page = address / BYTES_PER_PAGE;
+    bool matching_region_found = false;
+    for (unsigned region = 0u; region < NUM_REGIONS; region++) {
+        /* Ignore disabled regions */
+        unsigned r_region_cfg = R_MP_REGION_CFG_0 + region;
+        if (SHARED_FIELD_EX32(s->regs[r_region_cfg], MP_REGION_CFG_EN) !=
+            OT_MULTIBITBOOL4_TRUE) {
+            continue;
+        }
+
+        /*
+         * Check if the current flash word falls in this region.
+         * Size is inclusive at the base, but exclusive at (base+size).
+         */
+        unsigned r_region = R_MP_REGION_0 + region;
+        unsigned region_base_page =
+            SHARED_FIELD_EX32(s->regs[r_region], MP_REGION_BASE);
+        unsigned region_size =
+            SHARED_FIELD_EX32(s->regs[r_region], MP_REGION_SIZE);
+        if (page < region_base_page ||
+            page >= (region_base_page + region_size)) {
+            continue;
+        }
+        matching_region_found = true;
+
+        /* Page does fall in this region, so check if enabled for operation. */
+        if (!ot_flash_mp_region_cfg_op_enabled(s, r_region_cfg)) {
+            qemu_log_mask(
+                LOG_GUEST_ERROR,
+                "%s: %s: software operation %s on page %u of data partition "
+                "in bank %u is disabled by MP region %u\n",
+                __func__, s->ot_id, OP_NAME(s->op.kind), page, bank, region);
+            ot_flash_set_error(s, mp_err_ebit, address);
+            s->op.failed = true;
+            return address;
+        }
+        break;
+    }
+
+    /* If page not in any region, apply the default region's permissions. */
+    if (!matching_region_found && !ot_flash_default_region_cfg_op_enabled(s)) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: software operation %s on page %u of data partition "
+            "in bank %u is disabled by default region\n",
+            __func__, s->ot_id, OP_NAME(s->op.kind), page, bank);
+        ot_flash_set_error(s, mp_err_ebit, address);
+        s->op.failed = true;
+        return address;
+    }
+    return address;
+}
+
+static void ot_flash_op_read(OtFlashState *s)
+{
+    OtFifo32 *rd_fifo = (s->op.hw) ? &s->hw_rd_fifo : &s->rd_fifo;
+    g_assert(rd_fifo);
+
+    if (ot_fifo32_is_full(rd_fifo)) {
+        xtrace_ot_flash_error(s->ot_id, "read while RD FIFO full");
+        return;
+    }
+
+    OtFlashStorage *storage = &s->flash;
+    uint32_t *src = s->op.info_part ? storage->info : storage->data;
+
+    while (s->op.remaining) {
+        uint32_t word = 0xFFFFFFFFu;
+        if (!s->op.failed) {
+            unsigned address = s->op.info_part ? ot_flash_next_info_address(s) :
+                                                 ot_flash_next_data_address(s);
+            address /= sizeof(uint32_t); /* convert to word address */
+
+            /* For multi-word read access permission errors, return all 1s. */
+            if (!s->op.failed) {
+                word = src[address];
+            }
+        }
+
+        s->op.remaining--;
+        if (!s->op.hw && ot_flash_fifo_in_reset(s)) {
+            /* If fifo in reset, still read but don't push rdata */
+            continue;
+        }
+        ot_fifo32_push(rd_fifo, word);
+
+        if (ot_fifo32_is_full(rd_fifo)) {
+            break;
+        }
+    }
+
+    /*
+     * If we finished the entire read operation (i.e. no early exit as FIFO
+     * is full), mark the operation as completed.
+     */
+    if (!s->op.remaining) {
+        ot_flash_op_complete(s);
+    }
+}
+
+static void ot_flash_op_prog(OtFlashState *s)
+{
+    if (ot_fifo32_is_empty(&s->prog_fifo)) {
+        xtrace_ot_flash_error(s->ot_id, "prog while prog FIFO empty");
+        return;
+    }
+
+    OtFlashStorage *storage = &s->flash;
+    uint32_t *dest = s->op.info_part ? storage->info : storage->data;
+
+    while (s->op.remaining) {
+        uint32_t word = ot_fifo32_pop(&s->prog_fifo);
+        bool fifo_empty = ot_fifo32_is_empty(&s->prog_fifo);
+
+        /* Must calculate next addr before decrementing the remaining count. */
+        unsigned word_address = 0u;
+        unsigned address = 0u;
+        if (!s->op.failed) {
+            address = s->op.info_part ? ot_flash_next_info_address(s) :
+                                        ot_flash_next_data_address(s);
+            word_address = address / sizeof(uint32_t);
+        }
+        s->op.remaining--;
+
+        /*
+         * On encountering a multi-word write error, we must continue to empty
+         * the prog FIFO regardless, hence we retrieve the word to program
+         * before checking for errors.
+         */
+        trace_ot_flash_op_prog(s->ot_id, s->op.address, s->op.count,
+                               s->op.remaining, s->op.failed, fifo_empty);
+        if (s->op.failed) {
+            if (!fifo_empty) {
+                continue;
+            }
+            break;
+        }
+
+        /*
+         * Bits cannot be programmed back to 1 once programmed to 0; they must
+         * be erased instead.
+         */
+        g_assert(word_address <
+                 ((s->op.info_part ? storage->info_size : storage->data_size) *
+                  storage->bank_count));
+        dest[word_address] &= word;
+        if (!s->op.info_part) {
+            /*
+             * for data, we must flush relevant TLB pages to ensure host reads
+             * for XIP execution of mutated code in flash are correct.
+             */
+            memory_region_set_dirty(&s->mmio.mem, (hwaddr)address,
+                                    sizeof(uint32_t));
+        }
+        trace_ot_flash_prog_word(s->ot_id, s->op.info_part, word_address, word);
+        if (ot_flash_is_backend_writable(s)) {
+            uintptr_t dest_offset = (uintptr_t)dest - (uintptr_t)storage->data;
+            if (ot_flash_write_backend(s, &dest[word_address],
+                                       (unsigned)(dest_offset + word_address),
+                                       sizeof(uint32_t))) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: %s: cannot update flash backend\n", __func__,
+                              s->ot_id);
+                uint32_t ebit = s->op.hw ? R_FAULT_STATUS_PROG_ERR_MASK :
+                                           R_ERR_CODE_PROG_ERR_MASK;
+                ot_flash_set_error(s, ebit, address);
+            }
+        }
+
+        if (fifo_empty) {
+            break;
+        }
+    }
+
+    /*
+     * If we finished the entire program operation (i.e. no early exit as FIFO
+     * is empty), mark the operation as completed.
+     */
+    if (!s->op.remaining) {
+        ot_flash_op_complete(s);
+    }
+}
+
+static void ot_flash_op_erase_page(OtFlashState *s, unsigned address)
+{
+    OtFlashStorage *storage = &s->flash;
+    uint32_t *dest = s->op.info_part ? storage->info : storage->data;
+    unsigned page_size = BYTES_PER_PAGE;
+    unsigned page_address = address - (address % page_size);
+    unsigned word_address = page_address / sizeof(uint32_t);
+
+    g_assert((word_address + page_size) <
+             ((s->op.info_part ? storage->info_size : storage->data_size) *
+              storage->bank_count));
+    memset(&dest[word_address], 0xFF, page_size);
+    if (!s->op.info_part) {
+        /*
+         * for data, we must flush relevant TLB pages to ensure host reads
+         * for XIP execution of mutated code in flash are correct.
+         */
+        memory_region_set_dirty(&s->mmio.mem, (hwaddr)page_address, page_size);
+    }
+    trace_ot_flash_erase(s->ot_id, s->op.info_part, word_address, page_size);
+    if (ot_flash_is_backend_writable(s)) {
+        uintptr_t dest_offset = (uintptr_t)dest - (uintptr_t)storage->data;
+        if (ot_flash_write_backend(s, &dest[word_address],
+                                   (unsigned)(dest_offset + word_address),
+                                   page_size)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: cannot update flash backend\n", __func__,
+                          s->ot_id);
+            uint32_t ebit = s->op.hw ? R_FAULT_STATUS_PROG_ERR_MASK :
+                                       R_ERR_CODE_PROG_ERR_MASK;
+            ot_flash_set_error(s, ebit, page_address);
+            ot_flash_op_complete(s);
+            return;
+        }
+    }
+
+    ot_flash_op_complete(s);
+}
+
+static void ot_flash_op_erase_bank(OtFlashState *s, unsigned address)
+{
+    OtFlashStorage *storage = &s->flash;
+    unsigned bank_size =
+        s->op.info_part ? storage->info_size : storage->data_size;
+    unsigned bank = address / bank_size;
+
+    if (!ot_flash_can_erase_bank(s, bank)) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: cannot erase bank %u when bank-wide erase not enabled\n",
+            __func__, s->ot_id, bank);
+        uint32_t ebit =
+            s->op.hw ? R_FAULT_STATUS_MP_ERR_MASK : R_ERR_CODE_MP_ERR_MASK;
+        ot_flash_set_error(s, ebit, address);
+        ot_flash_op_complete(s);
+        return;
+    }
+
+    /*
+     * For bank erase only, if the data partition is selected, just the
+     * data partition is erased. If the info partition is selected, BOTH
+     * the data and info partitions are erased.
+     */
+    unsigned bank_address = address - (address % bank_size);
+    bank_address /= sizeof(uint32_t); /* convert to word address */
+    unsigned data_address, info_address = 0u;
+    if (!s->op.info_part) {
+        data_address = bank_address;
+        g_assert((data_address + bank_size) <=
+                 (storage->data_size * storage->bank_count));
+        memset(&storage->data[data_address], 0xFF, bank_size);
+        trace_ot_flash_erase(s->ot_id, s->op.info_part, data_address,
+                             bank_size);
+    } else {
+        info_address = bank_address;
+        g_assert((info_address + bank_size) <=
+                 (storage->info_size * storage->bank_count));
+        memset(&storage->info[info_address], 0xFF, bank_size);
+        trace_ot_flash_erase(s->ot_id, true, info_address, bank_size);
+
+        bank_size = storage->data_size;
+        data_address = bank_size * bank / sizeof(uint32_t);
+        g_assert((data_address + bank_size) <=
+                 (storage->data_size * storage->bank_count));
+        memset(&storage->data[data_address], 0xFF, bank_size);
+        trace_ot_flash_erase(s->ot_id, false, data_address, bank_size);
+    }
+    /*
+     * for data, we must flush relevant TLB pages to ensure host reads
+     * for XIP execution of mutated code in flash are correct.
+     */
+    hwaddr data_byte_address = (hwaddr)data_address * sizeof(uint32_t);
+    memory_region_set_dirty(&s->mmio.mem, data_byte_address, bank_size);
+
+    if (ot_flash_is_backend_writable(s)) {
+        int data_write_err =
+            ot_flash_write_backend(s, &storage->data[data_address],
+                                   (unsigned)(data_address),
+                                   storage->data_size);
+        int info_write_err = 0u;
+        if (s->op.info_part) {
+            uintptr_t offset =
+                (uintptr_t)storage->info - (uintptr_t)storage->data;
+            info_write_err =
+                ot_flash_write_backend(s, &storage->info[info_address],
+                                       (unsigned)(offset + info_address),
+                                       storage->info_size);
+        }
+
+        if (data_write_err || info_write_err) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: cannot update flash backend\n", __func__,
+                          s->ot_id);
+            uint32_t ebit = s->op.hw ? R_FAULT_STATUS_PROG_ERR_MASK :
+                                       R_ERR_CODE_PROG_ERR_MASK;
+            ot_flash_set_error(s, ebit, address * sizeof(uint32_t));
+            ot_flash_op_complete(s);
+            return;
+        }
+    }
+
+    ot_flash_op_complete(s);
+}
+
+static void ot_flash_op_erase(OtFlashState *s)
+{
+    unsigned address = s->op.info_part ? ot_flash_next_info_address(s) :
+                                         ot_flash_next_data_address(s);
+    if (s->op.failed) {
+        ot_flash_op_complete(s);
+        return;
+    }
+
+    /* Try to erase all bits in the page/bank back to 1. */
+    if (s->op.erase_sel == ERASE_SEL_PAGE) {
+        ot_flash_op_erase_page(s, address);
+    } else { /* ERASE_SEL_BANK */
+        ot_flash_op_erase_bank(s, address);
+    }
+}
+
+static void ot_flash_update_fifos_status(OtFlashState *s)
+{
+    uint32_t rd_full = (uint32_t)ot_fifo32_is_full(&s->rd_fifo);
+    uint32_t rd_empty = (uint32_t)ot_fifo32_is_empty(&s->rd_fifo);
+    uint32_t prog_full = (uint32_t)ot_fifo32_is_full(&s->prog_fifo);
+    uint32_t prog_empty = (uint32_t)ot_fifo32_is_empty(&s->prog_fifo);
+
+    s->regs[R_STATUS] = FIELD_DP32(s->regs[R_STATUS], STATUS, RD_FULL, rd_full);
+    s->regs[R_STATUS] =
+        FIELD_DP32(s->regs[R_STATUS], STATUS, RD_EMPTY, rd_empty);
+    s->regs[R_STATUS] =
+        FIELD_DP32(s->regs[R_STATUS], STATUS, PROG_FULL, prog_full);
+    s->regs[R_STATUS] =
+        FIELD_DP32(s->regs[R_STATUS], STATUS, PROG_EMPTY, prog_empty);
+
+    if (rd_full) {
+        s->regs[R_INTR_STATE] |= INTR_RD_FULL_MASK;
+    }
+    if (prog_empty) {
+        s->regs[R_INTR_STATE] |= INTR_PROG_EMPTY_MASK;
+    }
+    ot_flash_update_rd_watermark(s);
+    ot_flash_update_prog_watermark(s);
+    ot_flash_update_irqs(s);
+}
+
+static void ot_flash_op_execute(OtFlashState *s)
+{
+    switch (s->op.kind) {
+    case OP_READ:
+        trace_ot_flash_op_execute(s->ot_id, OP_NAME(s->op.kind), s->op.hw);
+        ot_flash_op_read(s);
+        break;
+    case OP_PROG:
+        trace_ot_flash_op_execute(s->ot_id, OP_NAME(s->op.kind), s->op.hw);
+        ot_flash_op_prog(s);
+        break;
+    case OP_ERASE:
+        trace_ot_flash_op_execute(s->ot_id, OP_NAME(s->op.kind), s->op.hw);
+        ot_flash_op_erase(s);
+        break;
+    default:
+        s->regs[R_CTRL_REGWEN] |= R_CTRL_REGWEN_EN_MASK;
+        xtrace_ot_flash_error(s->ot_id, "unsupported");
+        break;
+    }
+
+    /* Update fifo status reg & intrs if not in a HW operation */
+    if (!ot_flash_in_hw_operation(s)) {
+        ot_flash_update_fifos_status(s);
+    }
+}
+
+static void ot_flash_op_start(OtFlashState *s)
+{
+    trace_ot_flash_op_start(s->ot_id, OP_NAME(s->op.kind), s->op.hw);
+
+    s->regs[R_CTRL_REGWEN] &= ~R_CTRL_REGWEN_EN_MASK;
+    if (s->op.hw) {
+        /* hw op req will clear the prog fifo, whereas sw op req will not */
+        ot_flash_reset_prog_fifo(s);
+    }
+    ot_flash_op_execute(s);
+}
+
+static unsigned ot_flash_get_op_address_from_page(unsigned bank, unsigned page)
+{
+    return page * BYTES_PER_PAGE + bank * BYTES_PER_BANK;
+}
+
+static void ot_flash_read_keymgr_seed(OtFlashState *s, unsigned page,
+                                      OtFlashKeyMgrSecret *seed)
+{
+    ot_fifo32_reset(&s->hw_rd_fifo);
+
+    s->op.kind = OP_READ;
+    s->op.address = ot_flash_get_op_address_from_page(FLASH_SEED_BANK, page);
+    s->op.info_part = true;
+    s->op.info_sel = FLASH_SEED_INFO_PARTITION;
+    s->op.count = FLASH_SEED_WORDS;
+    /*
+     * init is triggered by SW, but the key reads during init are triggered by
+     * the flash controller HW
+     */
+    s->op.hw = true;
+    s->op.failed = false;
+    s->op.remaining = s->op.count;
+
+    ot_flash_op_start(s);
+
+    uint32_t words_read = ot_fifo32_num_used(&s->hw_rd_fifo);
+    g_assert(words_read == FLASH_SEED_WORDS);
+
+    uint32_t seed_words[FLASH_SEED_WORDS];
+    for (size_t ix = 0; ix < FLASH_SEED_WORDS; ix++) {
+        seed_words[ix] = ot_fifo32_pop(&s->hw_rd_fifo);
+    }
+    memcpy(seed->secret, seed_words, FLASH_SEED_BYTES);
+    seed->valid = !s->op.failed;
+
+    if (trace_event_get_state(TRACE_OT_FLASH_READ_KEYMGR_SEED)) {
+        const char *hexstr =
+            ot_flash_dump_bigint(s, seed->secret, FLASH_SEED_BYTES);
+        trace_ot_flash_read_keymgr_seed(s->ot_id, page, !s->op.failed, hexstr);
+    }
+
+    if (s->op.failed) {
+        ot_flash_set_error(s, R_FAULT_STATUS_SEED_ERR_MASK, s->op.address);
+    }
+}
+
+static void ot_flash_initialize(OtFlashState *s)
+{
+    bool initialized = (bool)FIELD_EX32(s->regs[R_STATUS], STATUS, INITIALIZED);
+    bool init_wip = (bool)FIELD_EX32(s->regs[R_STATUS], STATUS, INIT_WIP);
+    if (ot_flash_in_operation(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: cannot initialize while in op",
+                      __func__, s->ot_id);
+        return;
+    }
+    if (initialized) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: initialize is meaningless when already initialized",
+            __func__, s->ot_id);
+        return;
+    }
+    if (init_wip) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: initialize is meaningless when currently initializing",
+            __func__, s->ot_id);
+        return;
+    }
+
+    /* Start the INIT operation. */
+    s->op.kind = OP_INIT;
+    s->op.hw = false;
+    trace_ot_flash_op_start(s->ot_id, OP_NAME(s->op.kind), s->op.hw);
+    s->regs[R_STATUS] = FIELD_DP32(s->regs[R_STATUS], STATUS, INIT_WIP, 1u);
+    s->regs[R_PHY_STATUS] =
+        FIELD_DP32(s->regs[R_PHY_STATUS], PHY_STATUS, INIT_WIP, 1u);
+
+    /*
+     * TODO: this flash life cycle management logic is currently missing the
+     * ability to receive RMA requests from the lc_ctrl and wipe.
+     *
+     * TODO: implement reading of flash address and data keys from OTP
+     */
+
+    /*
+     * only read the flash seeds if `lc_seed_hw_rd_en` is received from the
+     * lc_ctrl to indicate "good otp/lc initialization".
+     */
+    bool seed_hw_rd_en =
+        s->lc_broadcast.current_level_bm & BIT(OT_FLASH_LC_SEED_HW_RD_EN);
+    if (seed_hw_rd_en) {
+        /* Read & latch seeds stored in flash on initialisation */
+        s->phase = LC_PHASE_SEED;
+        trace_ot_flash_change_lc_phase(s->ot_id, LC_PHASE_NAME(s->phase),
+                                       s->phase);
+
+        ot_flash_read_keymgr_seed(
+            s, FLASH_QUAL_INFO_PAGE_CREATOR,
+            &s->keymgr_seeds[FLASH_KEYMGR_SECRET_CREATOR_SEED]);
+        ot_flash_read_keymgr_seed(
+            s, FLASH_QUAL_INFO_PAGE_OWNER,
+            &s->keymgr_seeds[FLASH_KEYMGR_SECRET_OWNER_SEED]);
+    } else {
+        /* TODO: Lock up & wait for RMA entry to reseed and then wipe */
+        s->phase = LC_PHASE_NONE;
+        trace_ot_flash_change_lc_phase(s->ot_id, LC_PHASE_NAME(s->phase),
+                                       s->phase);
+        /* TODO: should this still complete the init operation? */
+    }
+
+    /* continue the init operation */
+    s->op.kind = OP_INIT;
+    s->op.hw = false;
+
+    /* Delay to emulate taking time to process the `INIT` op. */
+    timer_mod(s->op_delay,
+              qemu_clock_get_ns(OT_VIRTUAL_CLOCK) + OP_INIT_DURATION_NS);
+}
+
+static void ot_flash_update_exec(OtFlashState *s)
+{
+    OtVMapperClass *vm = OT_VMAPPER_GET_CLASS(s->vmapper);
+    bool ifetch = s->regs[R_EXEC] == EXEC_EN;
+
+    vm->disable_exec(s->vmapper, &s->mmio.mem, !ifetch);
+}
+
+static bool ot_flash_check_program_resolution(OtFlashState *s)
+{
+    unsigned start_address = s->op.address / sizeof(uint32_t);
+    unsigned end_address = start_address - 1u + s->op.count;
+    unsigned start_window = start_address / BUS_PGM_RES;
+    unsigned end_window = end_address / BUS_PGM_RES;
+    if (start_window != end_window) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: program resolution error for addr=%u, count=%u "
+                      "(start_window=%u, end_window=%u)\n",
+                      __func__, s->ot_id, s->op.address, s->op.count,
+                      start_window, end_window);
+        ot_flash_set_error(s, R_ERR_CODE_PROG_WIN_ERR_MASK, s->op.address);
+        ot_flash_op_complete(s);
+        return false;
+    }
+    return true;
+}
+
+static bool ot_flash_check_program_type(OtFlashState *s)
+{
+    uint32_t en_mask;
+    if (s->op.prog_sel == PROG_SEL_NORMAL) {
+        en_mask = R_PROG_TYPE_EN_NORMAL_MASK;
+    } else { /* PROG_SEL_REPAIR */
+        en_mask = R_PROG_TYPE_EN_REPAIR_MASK;
+    }
+    if (!(s->regs[R_PROG_TYPE_EN] & en_mask)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: program type not enabled: %s\n",
+                      __func__, s->ot_id, PROGRAM_NAME(s->op.prog_sel));
+        ot_flash_set_error(s, R_ERR_CODE_PROG_TYPE_ERR_MASK, s->op.address);
+        ot_flash_op_complete(s);
+        return false;
+    }
+    return true;
+}
+
+static void ot_flash_process_control_op(OtFlashState *s)
+{
+    uint32_t ctrl = s->regs[R_CONTROL];
+    bool start = (bool)FIELD_EX32(ctrl, CONTROL, START);
+    if (!start || ot_flash_in_operation(s)) {
+        return;
+    }
+
+    unsigned op = (unsigned)FIELD_EX32(ctrl, CONTROL, OP);
+    bool prog_sel = (bool)FIELD_EX32(ctrl, CONTROL, PROG_SEL);
+    bool erase_sel = (bool)FIELD_EX32(ctrl, CONTROL, ERASE_SEL);
+    bool part_sel = (bool)FIELD_EX32(ctrl, CONTROL, PARTITION_SEL);
+    unsigned info_sel = (unsigned)FIELD_EX32(ctrl, CONTROL, INFO_SEL);
+    unsigned num = (unsigned)FIELD_EX32(ctrl, CONTROL, NUM);
+
+    s->op.hw = false;
+
+    /*
+     * If the flash controller is disabled by software, then (a) the flash
+     * protocol controller completes existing software commands, (b) the flash
+     * physical controller completes existing stateful operations, and (c) the
+     * flash protocol controller MP errors back all controller initiated ops.
+     */
+    if (ot_flash_is_disabled(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: flash has been disabled\n",
+                      __func__, s->ot_id);
+        ot_flash_set_error(s, R_ERR_CODE_MP_ERR_MASK, 0u);
+        return;
+    }
+
+    switch (op) {
+    case CONTROL_OP_READ:
+        s->op.kind = OP_READ;
+        s->op.address = WORD_ALIGN_ADDR(s->regs[R_ADDR]);
+        s->op.info_part = part_sel;
+        s->op.info_sel = info_sel;
+        xtrace_ot_flash_info(s->ot_id, "Read from", s->op.address);
+        s->op.count = num + 1u;
+        break;
+    case CONTROL_OP_PROG:
+        s->op.kind = OP_PROG;
+        s->op.address = WORD_ALIGN_ADDR(s->regs[R_ADDR]);
+        s->op.info_part = part_sel;
+        s->op.info_sel = info_sel;
+        s->op.prog_sel = (bool)prog_sel;
+        s->op.count = num + 1u;
+        /*
+         * On encountering either a program resolution error or program type
+         * error, do not start the transaction.
+         */
+        if (!ot_flash_check_program_resolution(s) ||
+            !ot_flash_check_program_type(s)) {
+            break;
+        }
+        xtrace_ot_flash_info(s->ot_id, "Write to", s->op.address);
+        break;
+    case CONTROL_OP_ERASE:
+        s->op.kind = OP_ERASE;
+        s->op.address = WORD_ALIGN_ADDR(s->regs[R_ADDR]);
+        s->op.info_part = part_sel;
+        s->op.info_sel = info_sel;
+        s->op.erase_sel = (bool)erase_sel;
+        /* Erase ops neither go through FIFOs nor use/require a word count */
+        s->op.count = 0u;
+        xtrace_ot_flash_info(s->ot_id, "Erase at", s->op.address);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Operation %u (%s) is invalid\n",
+                      __func__, s->ot_id, op, CONTROL_OP_NAME(op));
+        ot_flash_set_error(s, R_ERR_CODE_OP_ERR_MASK, 0u);
+        ot_flash_op_complete(s);
+        return;
+    }
+    s->op.failed = false;
+    s->op.remaining = s->op.count;
+    ot_flash_op_start(s);
+}
+
+static void ot_flash_init_complete(void *opaque)
+{
+    OtFlashState *s = opaque;
+
+    s->regs[R_STATUS] = FIELD_DP32(s->regs[R_STATUS], STATUS, INIT_WIP, 0u);
+    s->regs[R_STATUS] = FIELD_DP32(s->regs[R_STATUS], STATUS, INITIALIZED, 1u);
+    s->regs[R_PHY_STATUS] =
+        FIELD_DP32(s->regs[R_PHY_STATUS], PHY_STATUS, INIT_WIP, 0u);
+
+    trace_ot_flash_op_complete(s->ot_id, OP_NAME(s->op.kind), s->op.hw, true);
+
+    s->op.kind = OP_NONE;
+}
+
+static uint64_t ot_flash_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtFlashState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_DIS:
+    case R_EXEC:
+    case R_INIT:
+    case R_CTRL_REGWEN:
+    case R_CONTROL:
+    case R_ADDR:
+    case R_PROG_TYPE_EN:
+    case R_ERASE_SUSPEND:
+    case R_REGION_CFG_REGWEN_0:
+    case R_REGION_CFG_REGWEN_1:
+    case R_REGION_CFG_REGWEN_2:
+    case R_REGION_CFG_REGWEN_3:
+    case R_REGION_CFG_REGWEN_4:
+    case R_REGION_CFG_REGWEN_5:
+    case R_REGION_CFG_REGWEN_6:
+    case R_REGION_CFG_REGWEN_7:
+    case R_MP_REGION_CFG_0:
+    case R_MP_REGION_CFG_1:
+    case R_MP_REGION_CFG_2:
+    case R_MP_REGION_CFG_3:
+    case R_MP_REGION_CFG_4:
+    case R_MP_REGION_CFG_5:
+    case R_MP_REGION_CFG_6:
+    case R_MP_REGION_CFG_7:
+    case R_MP_REGION_0:
+    case R_MP_REGION_1:
+    case R_MP_REGION_2:
+    case R_MP_REGION_3:
+    case R_MP_REGION_4:
+    case R_MP_REGION_5:
+    case R_MP_REGION_6:
+    case R_MP_REGION_7:
+    case R_DEFAULT_REGION:
+    case R_BANK0_INFO0_REGWEN_0:
+    case R_BANK0_INFO0_REGWEN_1:
+    case R_BANK0_INFO0_REGWEN_2:
+    case R_BANK0_INFO0_REGWEN_3:
+    case R_BANK0_INFO0_REGWEN_4:
+    case R_BANK0_INFO0_REGWEN_5:
+    case R_BANK0_INFO0_REGWEN_6:
+    case R_BANK0_INFO0_REGWEN_7:
+    case R_BANK0_INFO0_REGWEN_8:
+    case R_BANK0_INFO0_REGWEN_9:
+    case R_BANK0_INFO0_PAGE_CFG_0:
+    case R_BANK0_INFO0_PAGE_CFG_1:
+    case R_BANK0_INFO0_PAGE_CFG_2:
+    case R_BANK0_INFO0_PAGE_CFG_3:
+    case R_BANK0_INFO0_PAGE_CFG_4:
+    case R_BANK0_INFO0_PAGE_CFG_5:
+    case R_BANK0_INFO0_PAGE_CFG_6:
+    case R_BANK0_INFO0_PAGE_CFG_7:
+    case R_BANK0_INFO0_PAGE_CFG_8:
+    case R_BANK0_INFO0_PAGE_CFG_9:
+    case R_BANK0_INFO1_REGWEN:
+    case R_BANK0_INFO1_PAGE_CFG:
+    case R_BANK0_INFO2_REGWEN_0:
+    case R_BANK0_INFO2_REGWEN_1:
+    case R_BANK0_INFO2_PAGE_CFG_0:
+    case R_BANK0_INFO2_PAGE_CFG_1:
+    case R_BANK1_INFO0_REGWEN_0:
+    case R_BANK1_INFO0_REGWEN_1:
+    case R_BANK1_INFO0_REGWEN_2:
+    case R_BANK1_INFO0_REGWEN_3:
+    case R_BANK1_INFO0_REGWEN_4:
+    case R_BANK1_INFO0_REGWEN_5:
+    case R_BANK1_INFO0_REGWEN_6:
+    case R_BANK1_INFO0_REGWEN_7:
+    case R_BANK1_INFO0_REGWEN_8:
+    case R_BANK1_INFO0_REGWEN_9:
+    case R_BANK1_INFO0_PAGE_CFG_0:
+    case R_BANK1_INFO0_PAGE_CFG_1:
+    case R_BANK1_INFO0_PAGE_CFG_2:
+    case R_BANK1_INFO0_PAGE_CFG_3:
+    case R_BANK1_INFO0_PAGE_CFG_4:
+    case R_BANK1_INFO0_PAGE_CFG_5:
+    case R_BANK1_INFO0_PAGE_CFG_6:
+    case R_BANK1_INFO0_PAGE_CFG_7:
+    case R_BANK1_INFO0_PAGE_CFG_8:
+    case R_BANK1_INFO0_PAGE_CFG_9:
+    case R_BANK1_INFO1_REGWEN:
+    case R_BANK1_INFO1_PAGE_CFG:
+    case R_BANK1_INFO2_REGWEN_0:
+    case R_BANK1_INFO2_REGWEN_1:
+    case R_BANK1_INFO2_PAGE_CFG_0:
+    case R_BANK1_INFO2_PAGE_CFG_1:
+    case R_HW_INFO_CFG_OVERRIDE:
+    case R_BANK_CFG_REGWEN:
+    case R_MP_BANK_CFG_SHADOWED:
+    case R_OP_STATUS:
+    case R_DEBUG_STATE:
+    case R_ERR_CODE:
+    case R_STD_FAULT_STATUS:
+    case R_FAULT_STATUS:
+    case R_ERR_ADDR:
+    case R_ECC_SINGLE_ERR_CNT:
+    case R_ECC_SINGLE_ERR_ADDR_0:
+    case R_ECC_SINGLE_ERR_ADDR_1:
+    case R_PHY_ALERT_CFG:
+    case R_PHY_STATUS:
+    case R_SCRATCH:
+    case R_FIFO_LVL:
+    case R_FIFO_RST:
+    case R_STATUS:
+        val32 = s->regs[reg];
+        break;
+    case R_RD_FIFO:
+        if (!ot_fifo32_is_empty(&s->rd_fifo)) {
+            val32 = ot_fifo32_pop(&s->rd_fifo);
+            s->regs[R_STATUS] &= ~R_STATUS_RD_FULL_MASK;
+            s->regs[R_INTR_STATE] &= ~INTR_RD_FULL_MASK;
+            if (ot_fifo32_is_empty(&s->rd_fifo)) {
+                s->regs[R_STATUS] |= R_STATUS_RD_EMPTY_MASK;
+            }
+            ot_flash_update_rd_watermark(s);
+            ot_flash_update_irqs(s);
+            if (ot_flash_operation_ongoing(s)) {
+                ot_flash_op_execute(s);
+            }
+        } else {
+            /**
+             * @todo: technically, the hardware appears to stall the bus read
+             * from the read FIFO until there is valid data to read; this is
+             * fine in QEMU for most cases as we complete synchronously, except
+             * for initialisation, where we cannot trivially stall for
+             * completion to avoid blocking the main IO thread.
+             *
+             * For now, the initialization delay is set sufficiently small so
+             * as to make it unlikely that this case will be hit in OT testing;
+             * a better long term solution might be removing the initialisation
+             * delay entirely, or introducing some logic here to cancel the
+             * timer and complete init, though this would need to be careful
+             * with races and incomplete operations.
+             */
+            if (!ot_flash_is_initialized(s)) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: %s: Bus stalling on reads from uninit FIFO "
+                              "are not supported in QEMU\n",
+                              __func__, s->ot_id);
+            } else {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Read empty FIFO\n",
+                              __func__, s->ot_id);
+            }
+            val32 = 0u;
+        }
+        break;
+    case R_CURR_FIFO_LVL:
+        val32 =
+            SHARED_FIELD_DP32(0u, FIFO_LVL_RD, ot_fifo32_num_used(&s->rd_fifo));
+        val32 = SHARED_FIELD_DP32(val32, FIFO_LVL_PROG,
+                                  ot_fifo32_num_used(&s->prog_fifo));
+        break;
+    case R_ALERT_TEST:
+    case R_PROG_FIFO:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_flash_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                               pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_flash_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                unsigned size)
+{
+    OtFlashState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_flash_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE: {
+        uint32_t rw1c_mask = INTR_CORR_ERR_MASK | INTR_OP_DONE_MASK;
+        if (val32 & ~rw1c_mask) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Write to R/O field in register 0x%03x"
+                          " (%s)\n",
+                          __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        }
+        val32 &= rw1c_mask;
+        s->regs[reg] &= ~val32;
+        ot_flash_update_irqs(s);
+        break;
+    }
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_ENABLE] = val32;
+        ot_flash_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] |= val32;
+        ot_flash_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_MASK;
+        s->regs[reg] = val32;
+        ot_flash_update_alerts(s);
+        break;
+    case R_DIS:
+        val32 &= R_DIS_VAL_MASK;
+        s->regs[reg] = ot_multibitbool_w1s_write(s->regs[reg], val32, 4u);
+        if (ot_flash_is_disabled(s)) {
+            xtrace_ot_flash_error(s->ot_id, "flash controller disabled by SW");
+            memory_region_set_enabled(&s->mmio.mem, false);
+        }
+        break;
+    case R_INIT:
+        val32 &= R_INIT_VAL_MASK;
+        s->regs[reg] = val32;
+        if (val32) {
+            ot_flash_initialize(s);
+        }
+        break;
+    case R_EXEC:
+        s->regs[reg] = val32;
+        ot_flash_update_exec(s);
+        break;
+    case R_CONTROL:
+        if (!(s->regs[R_CTRL_REGWEN] & R_CTRL_REGWEN_EN_MASK)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: %s is not enabled, so %s is protected\n",
+                          __func__, s->ot_id, REG_NAME(R_CTRL_REGWEN),
+                          REG_NAME(reg));
+            break;
+        }
+
+        val32 &= CONTROL_MASK;
+        s->regs[reg] = val32;
+
+        /*
+         * SW protocol operations are not processed until the PHY controller is
+         * initialized, but the protocol controller is not required to be
+         * initialized (i.e. before the scrambling keys are read). In such a
+         * case we *can* interact with the flash - we just do not buffer
+         * outgoing reads, but they are still permitted.
+         *
+         * We emulate the PHY as always being initialized, so there is no need
+         * to check for initialization here.
+         *
+         * Note for future implementation of scrambling: there is a special
+         * case for scrambled pages: when reading from a scrambled page with
+         * the flash_ctrl uninitialized, default scrambling keys hardcoded in
+         * the RTL are used instead of the (not yet) loaded flash addr/data
+         * keys.
+         */
+        ot_flash_process_control_op(s);
+        break;
+    case R_ADDR:
+        val32 &= R_ADDR_START_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_PROG_TYPE_EN:
+        val32 &= R_PROG_TYPE_EN_NORMAL_MASK | R_PROG_TYPE_EN_REPAIR_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_ERASE_SUSPEND:
+        /*
+         * @todo We do not implement the erase suspend operation in QEMU as we
+         * do all erases synchronously, and so just immediately clear the erase
+         * suspend request. To implement this feature properly we would have to
+         * add delay to bank erases & check for erase suspends at each step.
+         */
+        s->regs[reg] = 0u;
+        break;
+    case R_REGION_CFG_REGWEN_0:
+    case R_REGION_CFG_REGWEN_1:
+    case R_REGION_CFG_REGWEN_2:
+    case R_REGION_CFG_REGWEN_3:
+    case R_REGION_CFG_REGWEN_4:
+    case R_REGION_CFG_REGWEN_5:
+    case R_REGION_CFG_REGWEN_6:
+    case R_REGION_CFG_REGWEN_7:
+    case R_BANK0_INFO0_REGWEN_0:
+    case R_BANK0_INFO0_REGWEN_1:
+    case R_BANK0_INFO0_REGWEN_2:
+    case R_BANK0_INFO0_REGWEN_3:
+    case R_BANK0_INFO0_REGWEN_4:
+    case R_BANK0_INFO0_REGWEN_5:
+    case R_BANK0_INFO0_REGWEN_6:
+    case R_BANK0_INFO0_REGWEN_7:
+    case R_BANK0_INFO0_REGWEN_8:
+    case R_BANK0_INFO0_REGWEN_9:
+    case R_BANK0_INFO1_REGWEN:
+    case R_BANK0_INFO2_REGWEN_0:
+    case R_BANK0_INFO2_REGWEN_1:
+    case R_BANK1_INFO0_REGWEN_0:
+    case R_BANK1_INFO0_REGWEN_1:
+    case R_BANK1_INFO0_REGWEN_2:
+    case R_BANK1_INFO0_REGWEN_3:
+    case R_BANK1_INFO0_REGWEN_4:
+    case R_BANK1_INFO0_REGWEN_5:
+    case R_BANK1_INFO0_REGWEN_6:
+    case R_BANK1_INFO0_REGWEN_7:
+    case R_BANK1_INFO0_REGWEN_8:
+    case R_BANK1_INFO0_REGWEN_9:
+    case R_BANK1_INFO2_REGWEN_0:
+    case R_BANK1_INFO2_REGWEN_1:
+    case R_BANK1_INFO1_REGWEN:
+    case R_BANK_CFG_REGWEN:
+        val32 &= BANK_REGWEN_MASK;
+        s->regs[reg] &= val32; /* rw0c */
+        break;
+    case R_HW_INFO_CFG_OVERRIDE:
+        val32 &= R_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK |
+                 R_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_MP_REGION_CFG_0:
+    case R_MP_REGION_CFG_1:
+    case R_MP_REGION_CFG_2:
+    case R_MP_REGION_CFG_3:
+    case R_MP_REGION_CFG_4:
+    case R_MP_REGION_CFG_5:
+    case R_MP_REGION_CFG_6:
+    case R_MP_REGION_CFG_7:
+        if (ot_flash_regs_is_wr_enabled(s, reg - R_MP_REGION_CFG_0 +
+                                               R_REGION_CFG_REGWEN_0)) {
+            val32 &= MP_REGION_CFG_MASK;
+            s->regs[reg] = val32;
+        }
+        break;
+    case R_MP_REGION_0:
+    case R_MP_REGION_1:
+    case R_MP_REGION_2:
+    case R_MP_REGION_3:
+    case R_MP_REGION_4:
+    case R_MP_REGION_5:
+    case R_MP_REGION_6:
+    case R_MP_REGION_7:
+        if (ot_flash_regs_is_wr_enabled(s, reg - R_MP_REGION_0 +
+                                               R_REGION_CFG_REGWEN_0)) {
+            val32 &= MP_REGION_MASK;
+            s->regs[reg] = val32;
+        }
+        break;
+    case R_DEFAULT_REGION:
+        val32 &= DEFAULT_REGION_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_BANK0_INFO0_PAGE_CFG_0:
+    case R_BANK0_INFO0_PAGE_CFG_1:
+    case R_BANK0_INFO0_PAGE_CFG_2:
+    case R_BANK0_INFO0_PAGE_CFG_3:
+    case R_BANK0_INFO0_PAGE_CFG_4:
+    case R_BANK0_INFO0_PAGE_CFG_5:
+    case R_BANK0_INFO0_PAGE_CFG_6:
+    case R_BANK0_INFO0_PAGE_CFG_7:
+    case R_BANK0_INFO0_PAGE_CFG_8:
+    case R_BANK0_INFO0_PAGE_CFG_9:
+        if (ot_flash_regs_is_wr_enabled(s, reg - R_BANK0_INFO0_PAGE_CFG_0 +
+                                               R_BANK0_INFO0_REGWEN_0)) {
+            val32 &= BANK_INFO_PAGE_CFG_MASK;
+            s->regs[reg] = val32;
+        }
+        break;
+    case R_BANK0_INFO1_PAGE_CFG:
+        if (ot_flash_regs_is_wr_enabled(s, R_BANK0_INFO1_REGWEN)) {
+            val32 &= BANK_INFO_PAGE_CFG_MASK;
+            s->regs[reg] = val32;
+        }
+        break;
+    case R_BANK0_INFO2_PAGE_CFG_0:
+    case R_BANK0_INFO2_PAGE_CFG_1:
+        if (ot_flash_regs_is_wr_enabled(s, reg - R_BANK0_INFO2_PAGE_CFG_0 +
+                                               R_BANK0_INFO2_REGWEN_0)) {
+            val32 &= BANK_INFO_PAGE_CFG_MASK;
+            s->regs[reg] = val32;
+        }
+        break;
+    case R_BANK1_INFO0_PAGE_CFG_0:
+    case R_BANK1_INFO0_PAGE_CFG_1:
+    case R_BANK1_INFO0_PAGE_CFG_2:
+    case R_BANK1_INFO0_PAGE_CFG_3:
+    case R_BANK1_INFO0_PAGE_CFG_4:
+    case R_BANK1_INFO0_PAGE_CFG_5:
+    case R_BANK1_INFO0_PAGE_CFG_6:
+    case R_BANK1_INFO0_PAGE_CFG_7:
+    case R_BANK1_INFO0_PAGE_CFG_8:
+    case R_BANK1_INFO0_PAGE_CFG_9:
+        if (ot_flash_regs_is_wr_enabled(s, reg - R_BANK1_INFO0_PAGE_CFG_0 +
+                                               R_BANK1_INFO0_REGWEN_0)) {
+            val32 &= BANK_INFO_PAGE_CFG_MASK;
+            s->regs[reg] = val32;
+        }
+        break;
+    case R_BANK1_INFO1_PAGE_CFG:
+        if (ot_flash_regs_is_wr_enabled(s, R_BANK1_INFO1_REGWEN)) {
+            val32 &= BANK_INFO_PAGE_CFG_MASK;
+            s->regs[reg] = val32;
+        }
+        break;
+    case R_BANK1_INFO2_PAGE_CFG_0:
+    case R_BANK1_INFO2_PAGE_CFG_1:
+        if (ot_flash_regs_is_wr_enabled(s, reg - R_BANK1_INFO2_PAGE_CFG_0 +
+                                               R_BANK1_INFO2_REGWEN_0)) {
+            val32 &= BANK_INFO_PAGE_CFG_MASK;
+            s->regs[reg] = val32;
+        }
+        break;
+    case R_MP_BANK_CFG_SHADOWED:
+        val32 &= (R_MP_BANK_CFG_SHADOWED_ERASE_EN_0_MASK |
+                  R_MP_BANK_CFG_SHADOWED_ERASE_EN_1_MASK);
+        s->regs[reg] = val32;
+        break;
+    case R_OP_STATUS:
+        val32 &= R_OP_STATUS_DONE_MASK | R_OP_STATUS_ERR_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_ERR_CODE:
+        val32 &= ERR_CODE_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        break;
+    case R_ECC_SINGLE_ERR_CNT:
+        val32 &=
+            (R_ECC_SINGLE_ERR_CNT_CNT_0_MASK | R_ECC_SINGLE_ERR_CNT_CNT_1_MASK);
+        s->regs[reg] = val32;
+        break;
+    case R_PHY_ALERT_CFG:
+        val32 &=
+            (R_PHY_ALERT_CFG_ALERT_ACK_MASK | R_PHY_ALERT_CFG_ALERT_TRIG_MASK);
+        s->regs[reg] = val32;
+        break;
+    case R_SCRATCH:
+        s->regs[reg] = val32;
+        break;
+    case R_FIFO_LVL:
+        val32 &= FIFO_LVL_PROG_MASK | FIFO_LVL_RD_MASK;
+        s->regs[reg] = val32;
+        ot_flash_update_rd_watermark(s);
+        ot_flash_update_prog_watermark(s);
+        break;
+    case R_FIFO_RST:
+        val32 &= R_FIFO_RST_EN_MASK;
+        s->regs[reg] = val32;
+        if (val32) {
+            ot_flash_reset_rd_fifo(s);
+            ot_flash_reset_prog_fifo(s);
+        }
+        break;
+    case R_PROG_FIFO:
+        if (s->op.kind != OP_PROG || s->op.hw) {
+            /*
+             * "This FIFO can only be programmed by software after a program
+             * operation has been initiated via the `CONTROL` register."
+             */
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: write prog fifo when not in a sw prog op\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        if (!ot_fifo32_is_full(&s->prog_fifo)) {
+            if (!ot_flash_fifo_in_reset(s)) {
+                ot_fifo32_push(&s->prog_fifo, val32);
+                s->regs[R_STATUS] &= ~R_STATUS_PROG_EMPTY_MASK;
+                s->regs[R_INTR_STATE] &= ~INTR_PROG_EMPTY_MASK;
+                ot_flash_update_prog_watermark(s);
+                ot_flash_update_irqs(s);
+            }
+            if (ot_fifo32_is_full(&s->prog_fifo)) {
+                s->regs[R_STATUS] |= R_STATUS_PROG_FULL_MASK;
+            }
+            if (ot_flash_operation_ongoing(s)) {
+                ot_flash_op_execute(s);
+            }
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Write full FIFO\n",
+                          __func__, s->ot_id);
+        }
+        break;
+    case R_FAULT_STATUS: {
+        uint32_t rw0c_mask = (R_FAULT_STATUS_PHY_RELBL_ERR_MASK |
+                              R_FAULT_STATUS_PHY_STORAGE_ERR_MASK);
+        if (val32 & ~rw0c_mask) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Write to R/O field in register 0x%03x"
+                          " (%s)\n",
+                          __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        }
+        val32 &= rw0c_mask;
+        val32 |= ~rw0c_mask;
+        s->regs[reg] &= val32;
+        break;
+    }
+    case R_CTRL_REGWEN:
+    case R_STATUS:
+    case R_DEBUG_STATE:
+    case R_RD_FIFO:
+    case R_STD_FAULT_STATUS:
+    case R_ERR_ADDR:
+    case R_ECC_SINGLE_ERR_ADDR_0:
+    case R_ECC_SINGLE_ERR_ADDR_1:
+    case R_PHY_STATUS:
+    case R_CURR_FIFO_LVL:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static uint64_t ot_flash_csrs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtFlashState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr csr = R32_OFF(addr);
+
+    switch (csr) {
+    case R_CSR0_REGWEN:
+    case R_CSR1:
+    case R_CSR2:
+    case R_CSR3:
+    case R_CSR4:
+    case R_CSR5:
+    case R_CSR6:
+    case R_CSR7:
+    case R_CSR8:
+    case R_CSR9:
+    case R_CSR10:
+    case R_CSR11:
+    case R_CSR12:
+    case R_CSR13:
+    case R_CSR14:
+    case R_CSR15:
+    case R_CSR16:
+    case R_CSR17:
+    case R_CSR18:
+    case R_CSR19:
+    case R_CSR20:
+        val32 = s->csrs[csr];
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_flash_io_read_out(s->ot_id, (uint32_t)addr, CSR_NAME(csr), val32,
+                               pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_flash_csrs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                unsigned size)
+{
+    OtFlashState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr csr = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_flash_io_write(s->ot_id, (uint32_t)addr, CSR_NAME(csr), val32, pc);
+
+    bool enable = s->csrs[R_CSR0_REGWEN] & R_CSR0_REGWEN_FIELD0_MASK;
+    switch (csr) {
+    case R_CSR0_REGWEN:
+        val32 &= R_CSR0_REGWEN_FIELD0_MASK;
+        break;
+    case R_CSR1:
+        val32 &= R_CSR1_FIELD0_MASK | R_CSR1_FIELD1_MASK;
+        break;
+    case R_CSR2:
+        val32 &= R_CSR2_FIELD0_MASK | R_CSR2_FIELD1_MASK | R_CSR2_FIELD2_MASK |
+                 R_CSR2_FIELD3_MASK | R_CSR2_FIELD4_MASK | R_CSR2_FIELD5_MASK |
+                 R_CSR2_FIELD6_MASK | R_CSR2_FIELD7_MASK;
+        break;
+    case R_CSR3:
+        val32 &= R_CSR3_FIELD0_MASK | R_CSR3_FIELD1_MASK | R_CSR3_FIELD2_MASK |
+                 R_CSR3_FIELD3_MASK | R_CSR3_FIELD4_MASK | R_CSR3_FIELD5_MASK |
+                 R_CSR3_FIELD6_MASK | R_CSR3_FIELD7_MASK | R_CSR3_FIELD8_MASK |
+                 R_CSR3_FIELD9_MASK;
+        break;
+    case R_CSR4:
+        val32 &= R_CSR4_FIELD0_MASK | R_CSR4_FIELD1_MASK | R_CSR4_FIELD2_MASK |
+                 R_CSR4_FIELD3_MASK;
+        break;
+    case R_CSR5:
+        val32 &= R_CSR5_FIELD0_MASK | R_CSR5_FIELD1_MASK | R_CSR5_FIELD2_MASK |
+                 R_CSR5_FIELD3_MASK | R_CSR5_FIELD4_MASK;
+        break;
+    case R_CSR6:
+        val32 &= R_CSR6_FIELD0_MASK | R_CSR6_FIELD1_MASK | R_CSR6_FIELD2_MASK |
+                 R_CSR6_FIELD3_MASK | R_CSR6_FIELD4_MASK | R_CSR6_FIELD5_MASK |
+                 R_CSR6_FIELD6_MASK | R_CSR6_FIELD7_MASK | R_CSR6_FIELD8_MASK;
+        break;
+    case R_CSR7:
+        val32 &= R_CSR7_FIELD0_MASK | R_CSR7_FIELD1_MASK;
+        break;
+    case R_CSR8:
+    case R_CSR9:
+    case R_CSR10:
+    case R_CSR11:
+        break;
+    case R_CSR12:
+        val32 &= R_CSR12_FIELD0_MASK;
+        break;
+    case R_CSR13:
+        val32 &= R_CSR13_FIELD0_MASK | R_CSR13_FIELD1_MASK;
+        break;
+    case R_CSR14:
+        val32 &= R_CSR14_FIELD0_MASK | R_CSR14_FIELD1_MASK;
+        break;
+    case R_CSR15:
+        val32 &= R_CSR15_FIELD0_MASK | R_CSR15_FIELD1_MASK;
+        break;
+    case R_CSR16:
+        val32 &= R_CSR16_FIELD0_MASK | R_CSR16_FIELD1_MASK;
+        break;
+    case R_CSR17:
+        val32 &= R_CSR17_FIELD0_MASK | R_CSR17_FIELD1_MASK;
+        break;
+    case R_CSR18:
+        val32 &= R_CSR18_FIELD0_MASK;
+        break;
+    case R_CSR19:
+        val32 &= R_CSR19_FIELD0_MASK;
+        break;
+    case R_CSR20:
+        val32 &=
+            R_CSR20_FIELD0_MASK | R_CSR20_FIELD1_MASK | R_CSR20_FIELD2_MASK;
+        break;
+    default:
+        enable = false;
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+
+    if (enable) {
+        s->csrs[csr] = val32;
+    }
+}
+
+static void ot_flash_lc_broadcast_recv(void *opaque, int n, int level)
+{
+    OtFlashState *s = opaque;
+    OtFlashLcBroadcast *bcast = &s->lc_broadcast;
+
+    g_assert((unsigned)n < OT_FLASH_LC_BROADCAST_COUNT);
+
+    uint16_t bit = 1u << (unsigned)n;
+    bcast->incoming_signal_bm |= bit;
+    /*
+     * As these signals are only used to change permissions, it is valid to
+     * override a signal value that has not been processed yet.
+     */
+    if (level) {
+        bcast->incoming_level_bm |= bit;
+    } else {
+        bcast->incoming_level_bm &= ~bit;
+    }
+
+    /* Use a short timer to decouple IRQ signaling from actual handling */
+    uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+    timer_mod(s->lc_broadcast.timer, (int64_t)(now + LC_BROADCAST_DELAY));
+}
+
+static void ot_flash_lc_broadcast(void *opaque)
+{
+    OtFlashState *s = opaque;
+    OtFlashLcBroadcast *bcast = &s->lc_broadcast;
+
+    /* handle all flagged signals */
+    while (bcast->incoming_signal_bm) {
+        /* pick the first seen signal and clear it */
+        unsigned signal = ctz16(bcast->incoming_signal_bm);
+        uint16_t signal_mask = 1u << signal;
+        bcast->incoming_signal_bm &= ~signal_mask;
+        bcast->current_level_bm &= ~signal_mask;
+        bcast->current_level_bm |= (bcast->incoming_level_bm & signal_mask);
+        bool level = (bool)(bcast->current_level_bm & signal_mask);
+
+        trace_ot_flash_lc_broadcast(s->ot_id, signal, level);
+
+        switch (signal) {
+        case OT_FLASH_LC_SEED_HW_RD_EN:
+        case OT_FLASH_LC_CREATOR_SEED_SW_RW_EN:
+        case OT_FLASH_LC_OWNER_SEED_SW_RW_EN:
+        case OT_FLASH_LC_ISO_PART_SW_RD_EN:
+        case OT_FLASH_LC_ISO_PART_SW_WR_EN:
+            /* nothing to do here, flag is latched in current_level */
+            break;
+        case OT_FLASH_LC_ESCALATE_EN:
+            /* flash disabling is detected from latch in current_level */
+            /* todo: also change the flash lcmgr lc_state? */
+            if (s->fatal_escalate) {
+                error_setg(&error_fatal, "%s: %s: Flash LC escalate", __func__,
+                           s->ot_id);
+            }
+            break;
+        case OT_FLASH_LC_NVM_DEBUG_EN:
+            qemu_log_mask(
+                LOG_UNIMP,
+                "%s: %s: lc_nvm_debug_en for JTAG connection is ignored\n",
+                __func__, s->ot_id);
+            break;
+        default:
+            error_setg(&error_fatal, "%s: %s: unexpected LC broadcast %d",
+                       __func__, s->ot_id, signal);
+            g_assert_not_reached();
+            break;
+        }
+    }
+}
+
+static void ot_flash_get_keymgr_secret(const OtFlashState *s,
+                                       OtFlashKeyMgrSecretType type,
+                                       OtFlashKeyMgrSecret *secret)
+{
+    trace_ot_flash_get_keymgr_secret(s->ot_id, FLASH_KEYMGR_SECRET_NAME(type),
+                                     type);
+
+    switch (type) {
+    case FLASH_KEYMGR_SECRET_CREATOR_SEED:
+    case FLASH_KEYMGR_SECRET_OWNER_SEED:
+        memcpy(secret, &s->keymgr_seeds[type], sizeof(OtFlashKeyMgrSecret));
+        bool invalid_seed =
+            (bool)(s->regs[R_FAULT_STATUS] & R_FAULT_STATUS_SEED_ERR_MASK);
+        secret->valid = !invalid_seed;
+        return;
+    default:
+        error_report("%s: %s: invalid flash keymgr secret type: %d", __func__,
+                     s->ot_id, type);
+        secret->valid = false;
+        memset(secret->secret, 0, OT_FLASH_KEYMGR_SECRET_BYTES);
+        return;
+    }
+}
+
+static void ot_flash_load(OtFlashState *s, Error **errp)
+{
+    OtFlashStorage *flash = &s->flash;
+    memset(flash, 0, sizeof(OtFlashStorage));
+
+    uintptr_t base;
+    unsigned flash_size;
+    unsigned data_size;
+    unsigned info_size;
+
+    memset(flash->info_parts, 0, sizeof(flash->info_parts));
+
+    if (s->blk) {
+        uint64_t perm = BLK_PERM_CONSISTENT_READ |
+                        (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
+        (void)blk_set_perm(s->blk, perm, perm, errp);
+
+        static_assert(sizeof(OtFlashBackendHeader) == 32u,
+                      "Invalid backend header size");
+
+        QEMU_AUTO_VFREE OtFlashBackendHeader *header =
+            blk_blockalign(s->blk, sizeof(OtFlashBackendHeader));
+
+        int rc;
+        /* NOLINTNEXTLINE(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        rc = blk_pread(s->blk, 0, sizeof(*header), header, 0);
+        if (rc < 0) {
+            error_setg(errp,
+                       "%s: %s: failed to read the flash header content: %d",
+                       __func__, s->ot_id, rc);
+            return;
+        }
+
+        if (memcmp(header->magic, "vFSH", sizeof(header->magic)) != 0) {
+            error_setg(errp, "%s: %s: Flash file is not a valid flash backend",
+                       __func__, s->ot_id);
+            return;
+        }
+        if (header->version != 1u) {
+            error_setg(errp, "%s: %s: Flash file version is not supported",
+                       __func__, s->ot_id);
+            return;
+        }
+
+        /*
+         * for now, only assert the flash file header matches local constants,
+         * which should match the default configuration. A real implementation
+         * should use these dynamic values, but this is fully out-of-scope for
+         * now.
+         */
+        if (header->bank != REG_NUM_BANKS || header->info != NUM_INFO_TYPES ||
+            header->page != REG_PAGES_PER_BANK ||
+            header->psize != BYTES_PER_PAGE || header->ipp[0u] != NUM_INFOS0 ||
+            header->ipp[1u] != NUM_INFOS1 || header->ipp[2u] != NUM_INFOS2 ||
+            header->ipp[3u] != 0u) {
+            error_setg(errp, "Flash file characteristics not supported");
+            return;
+        }
+
+        data_size = header->page * header->psize;
+        unsigned info_pages = 0;
+        unsigned pg_offset = 0;
+        for (unsigned ix = 0; ix < header->info; ix++) {
+            unsigned size = header->ipp[ix] * header->psize;
+            flash->info_parts[ix].size = size;
+            flash->info_parts[ix].offset = pg_offset;
+            pg_offset += size;
+            info_pages += header->ipp[ix];
+        }
+        flash->info_part_count = header->info;
+        info_size = info_pages * header->psize;
+        flash_size = header->bank * (data_size + info_size);
+
+        g_assert(pg_offset == info_size);
+
+        flash->storage = blk_blockalign(s->blk, flash_size);
+        base = (uintptr_t)flash->storage;
+        g_assert(!(base & (sizeof(uint64_t) - 1u)));
+
+        unsigned offset = offsetof(OtFlashBackendHeader, hlength) +
+                          sizeof(header->hlength) + header->hlength;
+
+        /* NOLINTNEXTLINE(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        rc = blk_pread(s->blk, (int64_t)offset, flash_size, flash->storage, 0);
+        if (rc < 0) {
+            error_setg(errp, "failed to read the initial flash content: %d",
+                       rc);
+            return;
+        }
+
+        flash->bank_count = header->bank;
+        flash->size = flash_size;
+
+        /* two banks, OTRE+OTB0 binaries/bank */
+        size_t debug_trailer_size =
+            (size_t)(flash->bank_count) * ELFNAME_SIZE * BIN_APP_COUNT;
+        uint8_t *elfnames = blk_blockalign(s->blk, debug_trailer_size);
+        /* NOLINTBEGIN(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        rc = blk_pread(s->blk, (int64_t)offset + flash_size,
+                       (int64_t)debug_trailer_size, elfnames, 0);
+        /* NOLINTEND(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        if (!rc) {
+            const char *elfname = (const char *)elfnames;
+            for (unsigned ix = 0; ix < BIN_APP_COUNT; ix++) {
+                size_t elflen = strnlen(elfname, ELFNAME_SIZE);
+                if (elflen > 0 && elflen < ELFNAME_SIZE) {
+                    if (!access(elfname, F_OK)) {
+                        if (load_elf_sym(elfname, 0, EM_RISCV, 1)) {
+                            xtrace_ot_flash_error(s->ot_id,
+                                                  "Cannot load ELF symbols");
+                        }
+                    }
+                }
+                elfname += ELFNAME_SIZE;
+            }
+        }
+
+        qemu_vfree(elfnames);
+    } else {
+        data_size = BYTES_PER_BANK;
+        info_size = BYTES_PER_PAGE * (NUM_INFOS0 + NUM_INFOS1 + NUM_INFOS2);
+        flash_size = REG_NUM_BANKS * (data_size + info_size);
+
+        flash->storage =
+            g_new0(uint32_t, DIV_ROUND_UP(flash_size, sizeof(uint32_t)));
+        base = (uintptr_t)flash->storage;
+
+        memset(flash->storage, 0xff, flash_size);
+
+        flash->info_parts[0u].size = NUM_INFOS0 * BYTES_PER_PAGE;
+        flash->info_parts[0u].offset = 0;
+        flash->info_parts[1u].size = NUM_INFOS1 * BYTES_PER_PAGE;
+        flash->info_parts[1u].offset =
+            flash->info_parts[0u].offset + flash->info_parts[0u].size;
+        flash->info_parts[2u].size = NUM_INFOS2 * BYTES_PER_PAGE;
+        flash->info_parts[2u].offset =
+            flash->info_parts[1u].offset + flash->info_parts[1u].size;
+        flash->info_part_count = NUM_INFO_TYPES;
+
+        flash->bank_count = REG_NUM_BANKS;
+    }
+
+    /*
+     * Raw backend structure:
+     * - HEADER
+     * - DATA_PART bank 0
+     * - DATA_PART bank 1
+     * - INFO_PARTS bank 0:
+     *   - INFO0 bank 0
+     *   - INFO1 bank 0
+     *   - INFO2 bank 0
+     * - INFO_PARTS bank 1:
+     *   - INFO0 bank 1
+     *   - INFO1 bank 1
+     *   - INFO2 bank 1
+     * - Debug info (ELF file names)
+     *
+     * @todo Add ECC section to backend for ECC/ICV support also
+     */
+    flash->data = (uint32_t *)(base);
+    flash->info =
+        (uint32_t *)(base + (uintptr_t)(flash->bank_count * data_size));
+    flash->data_size = data_size;
+    flash->info_size = info_size;
+}
+
+#if DATA_PART_USE_IO_OPS
+static uint64_t ot_flash_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtFlashState *s = opaque;
+    uint32_t val32;
+
+    if (ot_flash_is_disabled(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: flash has been disabled\n",
+                      __func__, s->ot_id);
+        return 0u;
+    }
+
+    if (addr < s->flash.bank_count * s->flash.data_size) {
+        val32 = s->flash.data[addr >> 2u];
+        unsigned offset = (unsigned)(addr & 0x3u);
+        val32 >>= offset << 3u;
+        uint32_t pc = ibex_get_current_pc();
+#if LOG_GPR_ON_FLASH_DATA_ACCESS
+#if LOG_GPR_ON_FLASH_DATA_ACCESS != UINT32_MAX
+        if (pc == (uint32_t)LOG_GPR_ON_FLASH_DATA_ACCESS)
+#endif
+            ibex_log_vcpu_registers(
+                RV_GPR_PC | RV_GPR_T0 | RV_GPR_T1 | RV_GPR_T2 | RV_GPR_A0 |
+                RV_GPR_A1 | RV_GPR_A2);
+#endif /* LOG_GPR_ON_FLASH_DATA_ACCESS */
+        trace_ot_flash_mem_read_out((uint32_t)addr, size, val32, pc);
+    } else {
+        uint32_t pc = ibex_get_current_pc();
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%06x, pc=0x%x\n",
+                      __func__, s->ot_id, (uint32_t)addr, pc);
+        val32 = 0;
+    }
+
+    return (uint64_t)val32;
+};
+#endif /* #if DATA_PART_USE_IO_OPS */
+
+static const Property ot_flash_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtFlashState, ot_id),
+    DEFINE_PROP_DRIVE("drive", OtFlashState, blk),
+    DEFINE_PROP_LINK("vmapper", OtFlashState, vmapper, TYPE_OT_VMAPPER,
+                     OtVMapperState *),
+    /* Optionally disable memory protection, as searching for valid memory
+    regions and checking their config can slow down regular operation. */
+    DEFINE_PROP_BOOL("no-mem-prot", OtFlashState, no_mem_prot, false),
+    DEFINE_PROP_BOOL("fatal_escalate", OtFlashState, fatal_escalate, false),
+};
+
+static const MemoryRegionOps ot_flash_regs_ops = {
+    .read = &ot_flash_regs_read,
+    .write = &ot_flash_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_flash_csrs_ops = {
+    .read = &ot_flash_csrs_read,
+    .write = &ot_flash_csrs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+#if DATA_PART_USE_IO_OPS
+static const MemoryRegionOps ot_flash_mem_ops = {
+    .read = &ot_flash_mem_read,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 1u,
+    .impl.max_access_size = 4u,
+};
+#else
+#if LOG_GPR_ON_FLASH_DATA_ACCESS
+#warning "Cannot use LOG_GPR_ON_FLASH_DATA_ACCESS w/o DATA_PART_USE_IO_OPS"
+#endif
+#endif /* DATA_PART_USE_IO_OPS */
+
+static void ot_flash_reset_enter(Object *obj, ResetType type)
+{
+    OtFlashClass *c = OT_FLASH_GET_CLASS(obj);
+    OtFlashState *s = OT_FLASH(obj);
+
+    trace_ot_flash_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->lc_broadcast.timer);
+
+    timer_del(s->op_delay);
+    s->op.kind = OP_NONE;
+
+    memset(s->regs, 0, REGS_SIZE);
+    s->regs[R_INTR_STATE] = 0x3u;
+    s->regs[R_DIS] = 0x9u;
+    s->regs[R_CTRL_REGWEN] = 0x1u;
+    s->regs[R_PROG_TYPE_EN] = 0x3u;
+    s->regs[R_REGION_CFG_REGWEN_0] = 0x1u;
+    s->regs[R_REGION_CFG_REGWEN_1] = 0x1u;
+    s->regs[R_REGION_CFG_REGWEN_2] = 0x1u;
+    s->regs[R_REGION_CFG_REGWEN_3] = 0x1u;
+    s->regs[R_REGION_CFG_REGWEN_4] = 0x1u;
+    s->regs[R_REGION_CFG_REGWEN_5] = 0x1u;
+    s->regs[R_REGION_CFG_REGWEN_6] = 0x1u;
+    s->regs[R_REGION_CFG_REGWEN_7] = 0x1u;
+    s->regs[R_MP_REGION_CFG_0] = 0x9999999u;
+    s->regs[R_MP_REGION_CFG_1] = 0x9999999u;
+    s->regs[R_MP_REGION_CFG_2] = 0x9999999u;
+    s->regs[R_MP_REGION_CFG_3] = 0x9999999u;
+    s->regs[R_MP_REGION_CFG_4] = 0x9999999u;
+    s->regs[R_MP_REGION_CFG_5] = 0x9999999u;
+    s->regs[R_MP_REGION_CFG_6] = 0x9999999u;
+    s->regs[R_MP_REGION_CFG_7] = 0x9999999u;
+    s->regs[R_DEFAULT_REGION] = 0x999999u;
+    s->regs[R_BANK0_INFO0_REGWEN_0] = 0x1u;
+    s->regs[R_BANK0_INFO0_REGWEN_1] = 0x1u;
+    s->regs[R_BANK0_INFO0_REGWEN_2] = 0x1u;
+    s->regs[R_BANK0_INFO0_REGWEN_3] = 0x1u;
+    s->regs[R_BANK0_INFO0_REGWEN_4] = 0x1u;
+    s->regs[R_BANK0_INFO0_REGWEN_5] = 0x1u;
+    s->regs[R_BANK0_INFO0_REGWEN_6] = 0x1u;
+    s->regs[R_BANK0_INFO0_REGWEN_7] = 0x1u;
+    s->regs[R_BANK0_INFO0_REGWEN_8] = 0x1u;
+    s->regs[R_BANK0_INFO0_REGWEN_9] = 0x1u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_0] = 0x9999999u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_1] = 0x9999999u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_2] = 0x9999999u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_3] = 0x9999999u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_4] = 0x9999999u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_5] = 0x9999999u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_6] = 0x9999999u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_7] = 0x9999999u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_8] = 0x9999999u;
+    s->regs[R_BANK0_INFO0_PAGE_CFG_9] = 0x9999999u;
+    s->regs[R_BANK0_INFO1_REGWEN] = 0x1u;
+    s->regs[R_BANK0_INFO1_PAGE_CFG] = 0x9999999u;
+    s->regs[R_BANK0_INFO2_REGWEN_0] = 0x1u;
+    s->regs[R_BANK0_INFO2_REGWEN_1] = 0x1u;
+    s->regs[R_BANK0_INFO2_PAGE_CFG_0] = 0x9999999u;
+    s->regs[R_BANK0_INFO2_PAGE_CFG_1] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_REGWEN_0] = 0x1u;
+    s->regs[R_BANK1_INFO0_REGWEN_1] = 0x1u;
+    s->regs[R_BANK1_INFO0_REGWEN_2] = 0x1u;
+    s->regs[R_BANK1_INFO0_REGWEN_3] = 0x1u;
+    s->regs[R_BANK1_INFO0_REGWEN_4] = 0x1u;
+    s->regs[R_BANK1_INFO0_REGWEN_5] = 0x1u;
+    s->regs[R_BANK1_INFO0_REGWEN_6] = 0x1u;
+    s->regs[R_BANK1_INFO0_REGWEN_7] = 0x1u;
+    s->regs[R_BANK1_INFO0_REGWEN_8] = 0x1u;
+    s->regs[R_BANK1_INFO0_REGWEN_9] = 0x1u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_0] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_1] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_2] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_3] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_4] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_5] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_6] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_7] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_8] = 0x9999999u;
+    s->regs[R_BANK1_INFO0_PAGE_CFG_9] = 0x9999999u;
+    s->regs[R_BANK1_INFO1_REGWEN] = 0x1u;
+    s->regs[R_BANK1_INFO1_PAGE_CFG] = 0x9999999u;
+    s->regs[R_BANK1_INFO2_REGWEN_0] = 0x1u;
+    s->regs[R_BANK1_INFO2_REGWEN_1] = 0x1u;
+    s->regs[R_BANK1_INFO2_PAGE_CFG_0] = 0x9999999u;
+    s->regs[R_BANK1_INFO2_PAGE_CFG_1] = 0x9999999u;
+    s->regs[R_HW_INFO_CFG_OVERRIDE] = 0x99u;
+    s->regs[R_BANK_CFG_REGWEN] = 0x1u;
+    s->regs[R_STATUS] = 0xau;
+    s->regs[R_PHY_STATUS] = 0x6u;
+    s->regs[R_FIFO_LVL] = 0xf0fu;
+
+    s->csrs[R_CSR0_REGWEN] = 0x1u;
+
+    /* restore flash memory region enablement if previously disabled */
+    memory_region_set_enabled(&s->mmio.mem, true);
+
+    s->latched_alerts = 0u;
+
+    s->lc_broadcast.incoming_signal_bm = 0u;
+    s->lc_broadcast.incoming_level_bm = 0u;
+    s->lc_broadcast.current_level_bm = 0u;
+
+    s->phase = LC_PHASE_NONE;
+
+    /* wipe internal secrets latched on initialisation */
+    for (unsigned ix = 0; ix < FLASH_KEYMGR_SECRET_COUNT; ix++) {
+        memset(s->keymgr_seeds[ix].secret, 0, OT_FLASH_KEYMGR_SECRET_BYTES);
+        s->keymgr_seeds[ix].valid = false;
+    }
+
+    ot_flash_update_irqs(s);
+    ot_flash_update_alerts(s);
+
+    ot_flash_reset_rd_fifo(s);
+    ot_flash_reset_prog_fifo(s);
+    ot_fifo32_reset(&s->hw_rd_fifo);
+}
+
+static void ot_flash_reset_exit(Object *obj, ResetType type)
+{
+    OtFlashClass *c = OT_FLASH_GET_CLASS(obj);
+    OtFlashState *s = OT_FLASH(obj);
+
+    trace_ot_flash_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    ot_flash_update_exec(s);
+}
+
+static void ot_flash_realize(DeviceState *dev, Error **errp)
+{
+    OtFlashState *s = OT_FLASH(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->vmapper);
+
+    ot_flash_load(s, &error_fatal);
+
+    uint64_t size = (uint64_t)s->flash.data_size * s->flash.bank_count;
+    MemoryRegion *mr = &s->mmio.mem;
+
+#if DATA_PART_USE_IO_OPS
+    memory_region_init_io(mr, OBJECT(dev), &ot_flash_mem_ops, s,
+                          TYPE_OT_FLASH ".mem", size);
+#else
+    /* there is no "memory_region_init_rom_ptr" - use ram_ptr variant and r/o */
+    memory_region_init_ram_ptr(mr, OBJECT(dev), TYPE_OT_FLASH ".mem", size,
+                               (void *)s->flash.data);
+    mr->readonly = true;
+#endif /* DATA_PART_USE_IO_OPS */
+
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), mr);
+}
+
+static void ot_flash_init(Object *obj)
+{
+    OtFlashState *s = OT_FLASH(obj);
+
+    memory_region_init_io(&s->mmio.regs, obj, &ot_flash_regs_ops, s,
+                          TYPE_OT_FLASH ".regs", REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio.regs);
+
+    memory_region_init_io(&s->mmio.csrs, obj, &ot_flash_csrs_ops, s,
+                          TYPE_OT_FLASH ".csrs", CSRS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio.csrs);
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+    s->csrs = g_new0(uint32_t, CSRS_COUNT);
+    ot_fifo32_create(&s->rd_fifo, OT_FLASH_READ_FIFO_SIZE);
+    ot_fifo32_create(&s->hw_rd_fifo, FLASH_SEED_WORDS);
+    ot_fifo32_create(&s->prog_fifo, OT_FLASH_PROG_FIFO_SIZE);
+
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_flash_lc_broadcast_recv,
+                            OT_LC_BROADCAST, OT_FLASH_LC_BROADCAST_COUNT);
+
+    s->lc_broadcast.timer =
+        timer_new_ns(OT_VIRTUAL_CLOCK, &ot_flash_lc_broadcast, s);
+    s->op_delay = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_flash_init_complete, s);
+
+    s->hexstr = g_new0(char, OT_FLASH_HEXSTR_SIZE);
+}
+
+static void ot_flash_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_flash_realize;
+    device_class_set_props(dc, ot_flash_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtFlashClass *fc = OT_FLASH_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_flash_reset_enter, NULL,
+                                       &ot_flash_reset_exit,
+                                       &fc->parent_phases);
+
+    fc->get_keymgr_secret = &ot_flash_get_keymgr_secret;
+}
+
+static const TypeInfo ot_flash_info = {
+    .name = TYPE_OT_FLASH,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtFlashState),
+    .instance_init = &ot_flash_init,
+    .class_size = sizeof(OtFlashClass),
+    .class_init = &ot_flash_class_init,
+};
+
+static void ot_flash_register_types(void)
+{
+    type_register_static(&ot_flash_info);
+}
+
+type_init(ot_flash_register_types);
diff --git a/hw/opentitan/ot_gpio_dj.c b/hw/opentitan/ot_gpio_dj.c
new file mode 100644
index 0000000000000..eb14e6c83dda4
--- /dev/null
+++ b/hw/opentitan/ot_gpio_dj.c
@@ -0,0 +1,954 @@
+/*
+ * QEMU OpenTitan Darjeeling GPIO device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Samuel Ortiz <sameo@rivosinc.com>
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "chardev/char-fe.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_gpio_dj.h"
+#include "hw/opentitan/ot_pinmux.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_gpio.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+#define PARAM_NUM_ALERTS 1u
+#define PARAM_NUM_IO     32u
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, FATAL_FAULT_ERR, 0u, 1u)
+REG32(DATA_IN, 0x10u)
+REG32(HW_STRAPS_DATA_IN_VALID, 0x14u)
+    FIELD(HW_STRAPS_DATA_IN_VALID, VALID, 0u, 1u)
+REG32(HW_STRAPS_DATA_IN, 0x18u)
+REG32(DIRECT_OUT, 0x1cu)
+REG32(MASKED_OUT_LOWER, 0x20u)
+    SHARED_FIELD(MASKED_VALUE, 0u, 16u)
+    SHARED_FIELD(MASKED_MASK, 16u, 16u)
+REG32(MASKED_OUT_UPPER, 0x24u)
+REG32(DIRECT_OE, 0x28u)
+REG32(MASKED_OE_LOWER, 0x2cu)
+REG32(MASKED_OE_UPPER, 0x30u)
+REG32(INTR_CTRL_EN_RISING, 0x34u)
+REG32(INTR_CTRL_EN_FALLING, 0x38u)
+REG32(INTR_CTRL_EN_LVLHIGH, 0x3cu)
+REG32(INTR_CTRL_EN_LVLLOW, 0x40u)
+REG32(CTRL_EN_INPUT_FILTER, 0x44u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_CTRL_EN_INPUT_FILTER)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define ALERT_TEST_MASK (R_ALERT_TEST_FATAL_FAULT_ERR_MASK)
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(DATA_IN),
+    REG_NAME_ENTRY(HW_STRAPS_DATA_IN_VALID),
+    REG_NAME_ENTRY(HW_STRAPS_DATA_IN),
+    REG_NAME_ENTRY(DIRECT_OUT),
+    REG_NAME_ENTRY(MASKED_OUT_LOWER),
+    REG_NAME_ENTRY(MASKED_OUT_UPPER),
+    REG_NAME_ENTRY(DIRECT_OE),
+    REG_NAME_ENTRY(MASKED_OE_LOWER),
+    REG_NAME_ENTRY(MASKED_OE_UPPER),
+    REG_NAME_ENTRY(INTR_CTRL_EN_RISING),
+    REG_NAME_ENTRY(INTR_CTRL_EN_FALLING),
+    REG_NAME_ENTRY(INTR_CTRL_EN_LVLHIGH),
+    REG_NAME_ENTRY(INTR_CTRL_EN_LVLLOW),
+    REG_NAME_ENTRY(CTRL_EN_INPUT_FILTER),
+};
+#undef REG_NAME_ENTRY
+
+typedef struct {
+    uint32_t hi_z;
+    uint32_t pull_v;
+    uint32_t out_en;
+    uint32_t out_v;
+    uint32_t in_m;
+} OtGpioDjBackendState;
+
+typedef enum {
+    IO_IDLE,
+    IO_RESET,
+    IO_READY,
+} OtGpioDjIOState;
+
+struct OtGpioDjState {
+    SysBusDevice parent_obj;
+
+    IbexIRQ *irqs;
+    IbexIRQ *gpos;
+    IbexIRQ alert;
+
+    MemoryRegion mmio;
+
+    uint32_t regs[REGS_COUNT];
+    uint32_t data_out; /* output data */
+    uint32_t data_oe; /* output enable */
+    uint32_t data_ii; /* input data from IRQ lines */
+    uint32_t data_ib; /* input data from backend */
+    uint32_t data_bi; /* ignore backend input */
+    uint32_t data_gi; /* ignore GPIO input */
+    uint32_t invert; /* invert signal */
+    uint32_t opendrain; /* open drain (1 -> hi-z) */
+    uint32_t pull_en; /* pull up/down enable */
+    uint32_t pull_sel; /* pull up or pull down */
+    uint32_t connected; /* connected to an external device or preset */
+
+    char ibuf[PARAM_NUM_IO]; /* backed input buffer */
+    unsigned ipos;
+    OtGpioDjIOState io_state;
+    OtGpioDjBackendState backend_state; /* cache */
+    bool log_en; /* trace enable */
+
+    char *ot_id;
+    char *log_id;
+    uint32_t reset_in; /* initial input levels */
+    uint32_t reset_out; /* initial output levels */
+    uint32_t reset_oe; /* initial output enable vs. hi-z levels */
+    uint32_t reset_ie; /* initial input enable (reset_in active GPIOs) */
+    uint32_t ibex_out; /* output w/ ibex_gpio (vs. tri-state) signalization */
+    CharFrontend chr; /* communication device */
+    guint watch_tag; /* tracker for comm device change */
+    bool wipe; /* whether to wipe the backend at reset */
+};
+
+struct OtGpioDjClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static void ot_gpio_dj_update_backend(OtGpioDjState *s, bool force);
+
+static void ot_gpio_dj_update_irqs(OtGpioDjState *s)
+{
+    uint32_t level = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+    if (s->log_en) {
+        trace_ot_gpio_irqs(s->ot_id, s->regs[R_INTR_STATE],
+                           s->regs[R_INTR_ENABLE], level);
+    }
+    for (unsigned ix = 0; ix < PARAM_NUM_IO; ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_gpio_dj_update_intr_level(OtGpioDjState *s)
+{
+    uint32_t intr_state = 0;
+
+    intr_state |= s->regs[R_INTR_CTRL_EN_LVLLOW] & ~s->regs[R_DATA_IN];
+    intr_state |= s->regs[R_INTR_CTRL_EN_LVLHIGH] & s->regs[R_DATA_IN];
+
+    s->regs[R_INTR_STATE] |= intr_state;
+}
+
+static void ot_gpio_dj_update_intr_edge(OtGpioDjState *s, uint32_t prev)
+{
+    uint32_t change = prev ^ s->regs[R_DATA_IN];
+    uint32_t rising = change & s->regs[R_DATA_IN];
+    uint32_t falling = change & ~s->regs[R_DATA_IN];
+
+    uint32_t intr_state = 0;
+
+    intr_state |= s->regs[R_INTR_CTRL_EN_RISING] & rising;
+    intr_state |= s->regs[R_INTR_CTRL_EN_FALLING] & falling;
+
+    s->regs[R_INTR_STATE] |= intr_state;
+}
+
+static void ot_gpio_dj_update_data_in(OtGpioDjState *s)
+{
+    uint32_t prev = s->regs[R_DATA_IN];
+
+    uint32_t ii_mask = s->connected & ~s->data_gi & ~s->data_oe;
+    uint32_t bi_mask = ~s->connected & ~s->data_bi & ~s->data_oe;
+    uint32_t pi_mask = s->data_gi & s->data_bi & ~s->data_oe;
+
+    uint32_t data_ii = s->data_ii & ii_mask;
+    uint32_t data_ib = s->data_ib & bi_mask;
+    uint32_t pull_in = s->pull_en & s->pull_sel & pi_mask;
+    uint32_t data_in = data_ii | data_ib | pull_in;
+
+    if (s->log_en) {
+        trace_ot_gpio_in_ignore(s->ot_id, s->connected, s->data_gi, s->data_bi,
+                                s->data_oe);
+        trace_ot_gpio_in_line(s->ot_id, s->data_ii, ii_mask, data_ii);
+        trace_ot_gpio_in_backend(s->ot_id, s->data_ib, bi_mask, data_ib);
+        trace_ot_gpio_in_pull(s->ot_id, s->pull_en, s->pull_sel, pi_mask,
+                              pull_in);
+    }
+
+    /* apply inversion if any */
+    data_in ^= s->invert;
+
+    /* inject back output pin values into input */
+    uint32_t data_mix = data_in | (s->data_out & s->data_oe);
+
+    s->regs[R_DATA_IN] = data_mix;
+
+    if (s->log_en) {
+        trace_ot_gpio_in_update(s->ot_id, s->invert, data_in, s->data_out,
+                                data_mix);
+    }
+
+    ot_gpio_dj_update_intr_level(s);
+    ot_gpio_dj_update_intr_edge(s, prev);
+    ot_gpio_dj_update_irqs(s);
+}
+
+static void ot_gpio_dj_update_data_out(OtGpioDjState *s)
+{
+    uint32_t outv = s->data_out;
+    /* assume invert is performed on device output data, not on pull up/down */
+    outv ^= s->invert; /* OV */
+
+    /*
+     *   OE  OD  OV  PE  PU  NA  Wk  IbexOut BinOut
+     *  |---|---|---|---|---|---|---|-------|------|
+     *    0   X   X   0   X   1   0     z    undef
+     *    0   X   X   1   0   1   1     l     0
+     *    0   X   X   1   1   1   1     h     1
+     *    1   X   0   X   X   0   0     L     0
+     *    1   0   1   X   X   0   0     H     1
+     *    1   1   1   0   X   1   0     z    undef
+     *    1   1   1   1   0   1   1     l     0
+     *    1   1   1   1   1   1   1     h     1
+     */
+
+    uint32_t not_active =
+        ~s->data_oe | (s->data_oe & s->opendrain & outv); /* NA */
+    uint32_t hi_z = ~s->pull_en & not_active;
+    uint32_t weak = s->pull_en & not_active; /* Wk */
+
+    if (s->log_en) {
+        trace_ot_gpio_out_update(s->ot_id, outv, weak, hi_z);
+    }
+    for (unsigned ix = 0; ix < PARAM_NUM_IO; ix++) {
+        unsigned bit = 1u << ix;
+        int level;
+        if (s->ibex_out & bit) {
+            /* Ibex GPIO output */
+            level =
+                hi_z & bit ?
+                    IBEX_GPIO_HIZ :
+                    (weak & bit ? IBEX_GPIO_FROM_WEAK_SIG(s->pull_sel & bit) :
+                                  IBEX_GPIO_FROM_ACTIVE_SIG(outv & bit));
+        } else {
+            /* binary output */
+            if (hi_z & bit) {
+                /* skip */
+                continue;
+            }
+            level = (int)(bool)((weak ? s->pull_sel : outv) & bit);
+        }
+        if (level != ibex_irq_get_level(&s->gpos[ix]) && s->log_en) {
+            if (s->ibex_out & bit) {
+                trace_ot_gpio_out_update_line_ibex(s->ot_id, ix,
+                                                   ibex_gpio_repr(level));
+            } else {
+                trace_ot_gpio_out_update_line_bool(s->ot_id, ix, level);
+            }
+        }
+        ibex_irq_set(&s->gpos[ix], level);
+    }
+}
+
+static void ot_gpio_dj_strap_en(void *opaque, int no, int level)
+{
+    OtGpioDjState *s = opaque;
+
+    g_assert(no == 0);
+
+    if (level) {
+        s->regs[R_HW_STRAPS_DATA_IN] = s->regs[R_DATA_IN];
+        s->regs[R_HW_STRAPS_DATA_IN_VALID] =
+            R_HW_STRAPS_DATA_IN_VALID_VALID_MASK;
+    }
+
+    if (s->log_en) {
+        trace_ot_gpio_strap_en(s->ot_id, no, (bool)level,
+                               s->regs[R_HW_STRAPS_DATA_IN]);
+    }
+}
+
+static void ot_gpio_dj_in_change(void *opaque, int no, int level)
+{
+    OtGpioDjState *s = opaque;
+
+    g_assert(no < PARAM_NUM_IO);
+
+    bool ibex_in = ibex_gpio_check(level);
+    bool hiz;
+    bool on;
+    bool weak;
+
+    if (ibex_in) {
+        hiz = ibex_gpio_is_hiz(level);
+        on = ibex_gpio_level(level);
+        weak = ibex_gpio_is_weak(level);
+    } else {
+        hiz = level < 0;
+        on = level > 0;
+        weak = false;
+    }
+    if (s->log_en) {
+        trace_ot_gpio_in_change(s->ot_id, no, hiz, on, weak);
+    }
+
+    uint32_t bit = 1u << no;
+
+    /*
+     * any time a signal is received from a remote device the pin is considered
+     * as connected and backend no longer may update its state.
+     */
+    s->connected |= bit;
+
+    if (!hiz) {
+        if (on) {
+            s->data_ii |= bit;
+        } else {
+            s->data_ii &= ~bit;
+        }
+        s->data_gi &= ~bit;
+    } else {
+        s->data_gi |= bit;
+    }
+
+    ot_gpio_dj_update_data_in(s);
+    ot_gpio_dj_update_backend(s, false);
+}
+
+static void ot_gpio_dj_pad_attr_change(void *opaque, int no, int level)
+{
+    OtGpioDjState *s = opaque;
+
+    g_assert(no < PARAM_NUM_IO);
+
+    uint32_t cfg = (uint32_t)level;
+    uint32_t bit = 1u << no;
+    char confstr[4u];
+
+    if (cfg & OT_PINMUX_PAD_ATTR_INVERT_MASK) {
+        s->invert |= bit;
+        confstr[0u] = '!';
+    } else {
+        s->invert &= ~bit;
+        confstr[0u] = '.';
+    }
+
+    if (cfg & (OT_PINMUX_PAD_ATTR_OD_EN_MASK |
+               OT_PINMUX_PAD_ATTR_VIRTUAL_OD_EN_MASK)) {
+        s->opendrain |= bit;
+        confstr[1u] = 'o';
+    } else {
+        s->opendrain &= ~bit;
+        confstr[1u] = '.';
+    }
+
+    if (cfg & OT_PINMUX_PAD_ATTR_PULL_SELECT_MASK) {
+        s->pull_sel |= bit;
+        confstr[2u] = 'h';
+    } else {
+        s->pull_sel &= ~bit;
+        confstr[2u] = 'l';
+    }
+
+    if (cfg & OT_PINMUX_PAD_ATTR_PULL_EN_MASK) {
+        s->pull_en |= bit;
+    } else {
+        s->pull_en &= ~bit;
+        confstr[2u] = '.';
+    }
+
+    confstr[3u] = '\0';
+
+    if (s->log_en) {
+        trace_ot_gpio_pad_attr_change(s->ot_id, no, cfg, confstr);
+    }
+
+    if (s->io_state == IO_READY) {
+        ot_gpio_dj_update_data_out(s);
+        ot_gpio_dj_update_backend(s, false);
+        ot_gpio_dj_update_data_in(s);
+    }
+}
+
+static uint64_t ot_gpio_dj_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtGpioDjState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_DATA_IN:
+    case R_DIRECT_OUT:
+    case R_DIRECT_OE:
+    case R_INTR_CTRL_EN_RISING:
+    case R_INTR_CTRL_EN_FALLING:
+    case R_INTR_CTRL_EN_LVLHIGH:
+    case R_INTR_CTRL_EN_LVLLOW:
+    case R_CTRL_EN_INPUT_FILTER:
+    case R_HW_STRAPS_DATA_IN:
+    case R_HW_STRAPS_DATA_IN_VALID:
+        val32 = s->regs[reg];
+        break;
+    case R_MASKED_OUT_LOWER:
+        val32 = s->data_out & MASKED_VALUE_MASK;
+        break;
+    case R_MASKED_OUT_UPPER:
+        val32 = (s->data_out >> MASKED_MASK_SHIFT) & MASKED_VALUE_MASK;
+        break;
+    case R_MASKED_OE_LOWER:
+        val32 = s->data_oe & MASKED_VALUE_MASK;
+        break;
+    case R_MASKED_OE_UPPER:
+        val32 = (s->data_oe >> MASKED_MASK_SHIFT) & MASKED_VALUE_MASK;
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0u;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    if (s->log_en) {
+        trace_ot_gpio_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg),
+                                  val32, pc);
+    }
+
+    return (uint64_t)val32;
+};
+
+static void ot_gpio_dj_write(void *opaque, hwaddr addr, uint64_t val64,
+                             unsigned size)
+{
+    OtGpioDjState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+    uint32_t mask;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_gpio_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_gpio_dj_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        s->regs[reg] = val32;
+        ot_gpio_dj_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        s->regs[R_INTR_STATE] |= val32;
+        ot_gpio_dj_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    case R_DIRECT_OUT:
+        s->regs[reg] = val32;
+        s->data_out = val32;
+        ot_gpio_dj_update_data_out(s);
+        ot_gpio_dj_update_backend(s, false);
+        ot_gpio_dj_update_data_in(s);
+        break;
+    case R_DIRECT_OE:
+        s->regs[reg] = val32;
+        s->data_oe = val32;
+        ot_gpio_dj_update_data_out(s);
+        ot_gpio_dj_update_backend(s, false);
+        ot_gpio_dj_update_data_in(s);
+        break;
+    case R_MASKED_OUT_LOWER:
+        s->regs[reg] = val32;
+        mask = val32 >> MASKED_MASK_SHIFT;
+        s->data_out &= ~mask;
+        s->data_out |= val32 & mask;
+        ot_gpio_dj_update_data_out(s);
+        ot_gpio_dj_update_backend(s, false);
+        ot_gpio_dj_update_data_in(s);
+        break;
+    case R_MASKED_OUT_UPPER:
+        s->regs[reg] = val32;
+        mask = val32 & MASKED_MASK_MASK;
+        s->data_out &= ~mask;
+        s->data_out |= (val32 << MASKED_MASK_SHIFT) & mask;
+        ot_gpio_dj_update_data_out(s);
+        ot_gpio_dj_update_backend(s, false);
+        ot_gpio_dj_update_data_in(s);
+        break;
+    case R_MASKED_OE_LOWER:
+        s->regs[reg] = val32;
+        mask = val32 >> MASKED_MASK_SHIFT;
+        s->data_oe &= ~mask;
+        s->data_oe |= val32 & mask;
+        ot_gpio_dj_update_data_out(s);
+        ot_gpio_dj_update_backend(s, false);
+        ot_gpio_dj_update_data_in(s);
+        break;
+    case R_MASKED_OE_UPPER:
+        s->regs[reg] = val32;
+        mask = val32 & MASKED_MASK_MASK;
+        s->data_oe &= ~mask;
+        s->data_oe |= (val32 << MASKED_MASK_SHIFT) & mask;
+        ot_gpio_dj_update_data_out(s);
+        ot_gpio_dj_update_backend(s, false);
+        ot_gpio_dj_update_data_in(s);
+        break;
+    case R_INTR_CTRL_EN_RISING:
+    case R_INTR_CTRL_EN_FALLING:
+        s->regs[reg] = val32;
+        break;
+    case R_INTR_CTRL_EN_LVLHIGH:
+    case R_INTR_CTRL_EN_LVLLOW:
+        s->regs[reg] = val32;
+        ot_gpio_dj_update_data_in(s);
+        break;
+    case R_CTRL_EN_INPUT_FILTER:
+        /* nothing can be done at QEMU level for sampling that fast */
+        s->regs[reg] = val32;
+        break;
+    case R_DATA_IN:
+    case R_HW_STRAPS_DATA_IN:
+    case R_HW_STRAPS_DATA_IN_VALID:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static int ot_gpio_dj_chr_can_receive(void *opaque)
+{
+    OtGpioDjState *s = opaque;
+
+    return (int)sizeof(s->ibuf) - (int)s->ipos;
+}
+
+static void ot_gpio_dj_chr_receive(void *opaque, const uint8_t *buf, int size)
+{
+    OtGpioDjState *s = opaque;
+
+    if (s->ipos + (unsigned)size > sizeof(s->ibuf)) {
+        error_report("%s: %s: Unexpected chardev receive\n", __func__,
+                     s->ot_id);
+        return;
+    }
+
+    memcpy(&s->ibuf[s->ipos], buf, (size_t)size);
+    s->ipos += (unsigned)size;
+
+    for (;;) {
+        const char *eol = memchr(s->ibuf, (int)'\n', s->ipos);
+        if (!eol) {
+            if (s->ipos > 10u) {
+                /* discard any garbage */
+                memset(s->ibuf, 0, sizeof(s->ibuf));
+                s->ipos = 0;
+            }
+            return;
+        }
+        unsigned eolpos = eol - s->ibuf;
+        if (eolpos < 10u) {
+            /* discard incomplete lines */
+            memmove(s->ibuf, eol + 1u, eolpos + 1u);
+            s->ipos = 0;
+            continue;
+        }
+        uint32_t data_in = 0;
+        char cmd = '\0';
+
+        /* NOLINTNEXTLINE */
+        int ret = sscanf(s->ibuf, "%c:%08x", &cmd, &data_in);
+        /* discard current command, even if invalid, up to first EOL */
+        const char *next = eol + 1u;
+        unsigned rem = (unsigned)(&s->ibuf[s->ipos] - next);
+        memmove(s->ibuf, next, rem);
+        s->ipos = rem;
+
+        if (ret == 2) {
+            if (s->log_en) {
+                trace_ot_gpio_backend_recv(s->ot_id, cmd, data_in);
+            }
+            if (cmd == 'M') {
+                s->data_bi = data_in;
+                ot_gpio_dj_update_data_in(s);
+            } else if (cmd == 'I') {
+                s->data_ib = data_in;
+                ot_gpio_dj_update_data_in(s);
+            } else if (cmd == 'R') {
+                ot_gpio_dj_update_backend(s, true);
+            } else {
+                qemu_log_mask(LOG_UNIMP, "%s: unsupported command %c\n",
+                              __func__, cmd);
+            }
+        }
+    }
+}
+
+static void ot_gpio_dj_init_backend(OtGpioDjState *s)
+{
+    if (!qemu_chr_fe_backend_connected(&s->chr)) {
+        return;
+    }
+
+    if (s->wipe) {
+        /* query backend for current input status */
+        char buf[16u];
+        int len = snprintf(buf, sizeof(buf), "C:%08x\r\n", 0);
+        qemu_chr_fe_write(&s->chr, (const uint8_t *)buf, len);
+    }
+}
+
+static void ot_gpio_dj_update_backend(OtGpioDjState *s, bool force)
+{
+    if (!qemu_chr_fe_backend_connected(&s->chr)) {
+        return;
+    }
+
+    /*
+     * use the MS DOS CR LF syntax because some people keep using
+     * Windows-style terminal.
+     */
+
+    uint32_t outv = s->data_out;
+    /* assume invert is performed on device output data, not on pull up/down */
+    outv ^= s->invert;
+
+    uint32_t out_en = s->data_oe;
+
+    /* if open drain is active and output is high, disable output enable */
+    out_en &= ~(s->opendrain & outv);
+
+    uint32_t active = s->pull_en | out_en;
+    outv &= out_en;
+
+    OtGpioDjBackendState bstate = { .hi_z = ~active,
+                                    .pull_v = s->pull_sel,
+                                    .out_en = out_en,
+                                    .out_v = outv,
+                                    .in_m = s->regs[R_DATA_IN] };
+
+    /*
+     * use the MS DOS CR LF syntax because some people keep using
+     * Windows-style terminal.
+     */
+
+    if (!memcmp(&bstate, &s->backend_state, sizeof(OtGpioDjBackendState)) &&
+        !force) {
+        /* do not emit new state if nothing has changed */
+        return;
+    }
+
+    char buf[64u];
+    size_t len = 0;
+
+    len += snprintf(&buf[len], sizeof(buf) - len, "Z:%08x\r\n", bstate.hi_z);
+    len += snprintf(&buf[len], sizeof(buf) - len, "P:%08x\r\n", bstate.pull_v);
+    len += snprintf(&buf[len], sizeof(buf) - len, "D:%08x\r\n", bstate.out_en);
+    len += snprintf(&buf[len], sizeof(buf) - len, "O:%08x\r\n", bstate.out_v);
+    len += snprintf(&buf[len], sizeof(buf) - len, "Y:%08x\r\n", bstate.in_m);
+
+    s->backend_state = bstate;
+
+    qemu_chr_fe_write(&s->chr, (const uint8_t *)buf, (int)len);
+
+    if (s->log_en) {
+        /* replace CRLF so that trace is kept on a single line */
+        buf[10] = buf[22] = buf[34] = buf[46] = ',';
+        buf[11] = buf[23] = buf[35] = buf[47] = ' ';
+        buf[58] = '\0';
+        trace_ot_gpio_backend_send(s->ot_id, buf);
+    }
+}
+
+static void ot_gpio_dj_chr_event_hander(void *opaque, QEMUChrEvent event)
+{
+    OtGpioDjState *s = opaque;
+
+    if (event == CHR_EVENT_OPENED) {
+        if (object_dynamic_cast(OBJECT(s->chr.chr), TYPE_CHARDEV_SERIAL)) {
+            ot_common_ignore_chr_status_lines(&s->chr);
+        }
+
+        if (!qemu_chr_fe_backend_connected(&s->chr)) {
+            return;
+        }
+
+        ot_gpio_dj_update_backend(s, true);
+
+        /* query backend for current input status */
+        char buf[16u];
+        int len = snprintf(buf, sizeof(buf), "Q:%08x\r\n", s->data_oe);
+        qemu_chr_fe_write(&s->chr, (const uint8_t *)buf, len);
+        buf[MIN((unsigned)len - 1, sizeof(buf) - 1u)] = '\0';
+        trace_ot_gpio_backend_send(s->ot_id, buf);
+    }
+}
+
+static gboolean
+ot_gpio_dj_chr_watch_cb(void *do_not_use, GIOCondition cond, void *opaque)
+{
+    OtGpioDjState *s = opaque;
+    (void)do_not_use;
+    (void)cond;
+
+    s->watch_tag = 0;
+
+    return FALSE;
+}
+
+static int ot_gpio_dj_chr_be_change(void *opaque)
+{
+    OtGpioDjState *s = opaque;
+
+    qemu_chr_fe_set_handlers(&s->chr, &ot_gpio_dj_chr_can_receive,
+                             &ot_gpio_dj_chr_receive,
+                             &ot_gpio_dj_chr_event_hander,
+                             &ot_gpio_dj_chr_be_change, s, NULL, true);
+
+    memset(s->ibuf, 0, sizeof(s->ibuf));
+    s->ipos = 0;
+
+    if (s->watch_tag > 0) {
+        g_source_remove(s->watch_tag);
+        /* NOLINTNEXTLINE(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+                                             &ot_gpio_dj_chr_watch_cb, s);
+    }
+
+    return 0;
+}
+
+static const MemoryRegionOps ot_gpio_dj_regs_ops = {
+    .read = &ot_gpio_dj_read,
+    .write = &ot_gpio_dj_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const Property ot_gpio_dj_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtGpioDjState, ot_id),
+    DEFINE_PROP_STRING("log_id", OtGpioDjState, log_id),
+    DEFINE_PROP_UINT32("in", OtGpioDjState, reset_in, 0u),
+    DEFINE_PROP_UINT32("out", OtGpioDjState, reset_out, 0u),
+    DEFINE_PROP_UINT32("ie", OtGpioDjState, reset_ie, 0u),
+    DEFINE_PROP_UINT32("oe", OtGpioDjState, reset_oe, 0u),
+    DEFINE_PROP_UINT32("ibex_out", OtGpioDjState, ibex_out, 0u),
+    DEFINE_PROP_BOOL("wipe", OtGpioDjState, wipe, false),
+    DEFINE_PROP_CHR("chardev", OtGpioDjState, chr),
+};
+
+static void ot_gpio_dj_reset_enter(Object *obj, ResetType type)
+{
+    OtGpioDjClass *c = OT_GPIO_DJ_GET_CLASS(obj);
+    OtGpioDjState *s = OT_GPIO_DJ(obj);
+
+    s->log_en = s->log_id ? !strcmp(s->ot_id, s->log_id) : true;
+
+    if (s->log_en) {
+        trace_ot_gpio_reset(s->ot_id, "> enter");
+    }
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    s->io_state = IO_RESET;
+
+    memset(s->regs, 0, sizeof(s->regs));
+    memset(&s->backend_state, 0, sizeof(s->backend_state));
+
+    /* reset_* fields are properties, never get reset */
+    s->connected = s->reset_oe | s->reset_ie;
+    s->data_ii = s->reset_in;
+    s->data_ib = 0;
+    s->data_out = s->reset_out;
+    s->data_oe = s->reset_oe;
+    s->data_bi = UINT32_MAX;
+    s->data_gi = ~s->connected;
+    s->pull_en = 0;
+    s->pull_sel = 0;
+    s->invert = 0;
+
+    s->regs[R_DATA_IN] = s->reset_in;
+    s->regs[R_DIRECT_OUT] = s->reset_out;
+    s->regs[R_DIRECT_OE] = s->reset_oe;
+
+    ot_gpio_dj_update_irqs(s);
+    ibex_irq_set(&s->alert, 0);
+
+    if (s->log_en) {
+        trace_ot_gpio_reset(s->ot_id, "< enter");
+    }
+}
+
+static void ot_gpio_dj_reset_exit(Object *obj, ResetType type)
+{
+    /*
+     * use of a Resettable full API enables performing I/O updates only once
+     * the pinmux configuration has been received (from its own reset stage)
+     */
+    OtGpioDjClass *c = OT_GPIO_DJ_GET_CLASS(obj);
+    OtGpioDjState *s = OT_GPIO_DJ(obj);
+
+    if (s->log_en) {
+        trace_ot_gpio_reset(s->ot_id, "> exit");
+    }
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    ot_gpio_dj_init_backend(s);
+    ot_gpio_dj_update_data_out(s);
+    ot_gpio_dj_update_backend(s, true);
+    ot_gpio_dj_update_data_in(s);
+
+    s->io_state = IO_READY;
+    /*
+     * do not reset the input backend buffer as external GPIO changes is fully
+     * async with OT reset. However, it should be reset when the backend changes
+     */
+    if (s->log_en) {
+        trace_ot_gpio_reset(s->ot_id, "< exit");
+    }
+}
+
+static void ot_gpio_dj_realize(DeviceState *dev, Error **errp)
+{
+    OtGpioDjState *s = OT_GPIO_DJ(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+
+    qemu_chr_fe_set_handlers(&s->chr, &ot_gpio_dj_chr_can_receive,
+                             &ot_gpio_dj_chr_receive,
+                             &ot_gpio_dj_chr_event_hander,
+                             &ot_gpio_dj_chr_be_change, s, NULL, true);
+}
+
+static void ot_gpio_dj_init(Object *obj)
+{
+    OtGpioDjState *s = OT_GPIO_DJ(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_gpio_dj_regs_ops, s,
+                          TYPE_OT_GPIO_DJ, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->irqs = g_new(IbexIRQ, PARAM_NUM_IO);
+    s->gpos = g_new(IbexIRQ, PARAM_NUM_IO);
+    for (unsigned ix = 0; ix < PARAM_NUM_IO; ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    ibex_qdev_init_irqs_default(obj, s->gpos, OT_GPIO_OUT, PARAM_NUM_IO, -1);
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_gpio_dj_strap_en, OT_GPIO_STRAP_EN,
+                            1);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_gpio_dj_in_change, OT_GPIO_IN,
+                            PARAM_NUM_IO);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_gpio_dj_pad_attr_change,
+                            OT_PINMUX_PAD, PARAM_NUM_IO);
+
+    s->io_state = IO_IDLE;
+}
+
+static void ot_gpio_dj_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_gpio_dj_realize;
+    device_class_set_props(dc, ot_gpio_dj_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(dc);
+    OtGpioDjClass *gc = OT_GPIO_DJ_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_gpio_dj_reset_enter, NULL,
+                                       &ot_gpio_dj_reset_exit,
+                                       &gc->parent_phases);
+}
+
+static const TypeInfo ot_gpio_dj_info = {
+    .name = TYPE_OT_GPIO_DJ,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtGpioDjState),
+    .instance_init = &ot_gpio_dj_init,
+    .class_size = sizeof(OtGpioDjClass),
+    .class_init = &ot_gpio_dj_class_init,
+};
+
+static void ot_gpio_dj_register_types(void)
+{
+    type_register_static(&ot_gpio_dj_info);
+}
+
+type_init(ot_gpio_dj_register_types);
diff --git a/hw/opentitan/ot_gpio_eg.c b/hw/opentitan/ot_gpio_eg.c
new file mode 100644
index 0000000000000..5fa553e055fa8
--- /dev/null
+++ b/hw/opentitan/ot_gpio_eg.c
@@ -0,0 +1,837 @@
+/*
+ * QEMU OpenTitan Earlgrey GPIO device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "chardev/char-fe.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_gpio_eg.h"
+#include "hw/opentitan/ot_pinmux.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+#define PARAM_NUM_ALERTS 1u
+#define PARAM_NUM_IO     32u
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, FATAL_FAULT_ERR, 0u, 1u)
+REG32(DATA_IN, 0x10u)
+REG32(DIRECT_OUT, 0x14u)
+REG32(MASKED_OUT_LOWER, 0x18u)
+    SHARED_FIELD(MASKED_VALUE, 0u, 16u)
+    SHARED_FIELD(MASKED_MASK, 16u, 16u)
+REG32(MASKED_OUT_UPPER, 0x1cu)
+REG32(DIRECT_OE, 0x20u)
+REG32(MASKED_OE_LOWER, 0x24u)
+REG32(MASKED_OE_UPPER, 0x28u)
+REG32(INTR_CTRL_EN_RISING, 0x2cu)
+REG32(INTR_CTRL_EN_FALLING, 0x30u)
+REG32(INTR_CTRL_EN_LVLHIGH, 0x34u)
+REG32(INTR_CTRL_EN_LVLLOW, 0x38u)
+REG32(CTRL_EN_INPUT_FILTER, 0x3cu)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_CTRL_EN_INPUT_FILTER)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define ALERT_TEST_MASK (R_ALERT_TEST_FATAL_FAULT_ERR_MASK)
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(DATA_IN),
+    REG_NAME_ENTRY(DIRECT_OUT),
+    REG_NAME_ENTRY(MASKED_OUT_LOWER),
+    REG_NAME_ENTRY(MASKED_OUT_UPPER),
+    REG_NAME_ENTRY(DIRECT_OE),
+    REG_NAME_ENTRY(MASKED_OE_LOWER),
+    REG_NAME_ENTRY(MASKED_OE_UPPER),
+    REG_NAME_ENTRY(INTR_CTRL_EN_RISING),
+    REG_NAME_ENTRY(INTR_CTRL_EN_FALLING),
+    REG_NAME_ENTRY(INTR_CTRL_EN_LVLHIGH),
+    REG_NAME_ENTRY(INTR_CTRL_EN_LVLLOW),
+    REG_NAME_ENTRY(CTRL_EN_INPUT_FILTER),
+};
+#undef REG_NAME_ENTRY
+
+typedef struct {
+    uint32_t hi_z;
+    uint32_t pull_v;
+    uint32_t out_en;
+    uint32_t out_v;
+    uint32_t in_m;
+} OtGpioEgBackendState;
+
+struct OtGpioEgState {
+    SysBusDevice parent_obj;
+
+    IbexIRQ *irqs;
+    IbexIRQ *gpos;
+    IbexIRQ alert;
+
+    MemoryRegion mmio;
+
+    uint32_t regs[REGS_COUNT];
+    uint32_t data_out; /* output data */
+    uint32_t data_oe; /* output enable */
+    uint32_t data_ii; /* input data from IRQ lines */
+    uint32_t data_ib; /* input data from backend */
+    uint32_t data_bi; /* ignore backend input */
+    uint32_t data_gi; /* ignore GPIO input */
+    uint32_t invert; /* invert signal */
+    uint32_t opendrain; /* open drain (1 -> hi-z) */
+    uint32_t pull_en; /* pull up/down enable */
+    uint32_t pull_sel; /* pull up or pull down */
+    uint32_t connected; /* connected to an external device */
+
+    char ibuf[PARAM_NUM_IO]; /* backed input buffer */
+    unsigned ipos;
+    OtGpioEgBackendState backend_state; /* cache */
+
+    char *ot_id;
+    uint32_t reset_in; /* initial input levels */
+    uint32_t reset_out; /* initial output levels */
+    uint32_t reset_oe; /* initial output enable vs. hi-z levels */
+    CharFrontend chr; /* communication device */
+    guint watch_tag; /* tracker for comm device change */
+    bool wipe; /* whether to wipe the backend at reset */
+};
+
+struct OtGpioEgClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static void ot_gpio_eg_update_backend(OtGpioEgState *s, bool force);
+
+static void ot_gpio_eg_update_irqs(OtGpioEgState *s)
+{
+    uint32_t level = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+    trace_ot_gpio_irqs(s->ot_id, s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE],
+                       level);
+    for (unsigned ix = 0; ix < PARAM_NUM_IO; ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_gpio_eg_update_intr_level(OtGpioEgState *s)
+{
+    uint32_t intr_state = 0;
+
+    intr_state |= s->regs[R_INTR_CTRL_EN_LVLLOW] & ~s->regs[R_DATA_IN];
+    intr_state |= s->regs[R_INTR_CTRL_EN_LVLHIGH] & s->regs[R_DATA_IN];
+
+    s->regs[R_INTR_STATE] |= intr_state;
+}
+
+static void ot_gpio_eg_update_intr_edge(OtGpioEgState *s, uint32_t prev)
+{
+    uint32_t change = prev ^ s->regs[R_DATA_IN];
+    uint32_t rising = change & s->regs[R_DATA_IN];
+    uint32_t falling = change & ~s->regs[R_DATA_IN];
+
+    uint32_t intr_state = 0;
+
+    intr_state |= s->regs[R_INTR_CTRL_EN_RISING] & rising;
+    intr_state |= s->regs[R_INTR_CTRL_EN_FALLING] & falling;
+
+    s->regs[R_INTR_STATE] |= intr_state;
+}
+
+static void ot_gpio_eg_update_data_in(OtGpioEgState *s)
+{
+    uint32_t prev = s->regs[R_DATA_IN];
+
+    uint32_t ii_mask = s->connected & ~s->data_gi & ~s->data_oe;
+    uint32_t bi_mask = ~s->connected & ~s->data_bi & ~s->data_oe;
+    uint32_t pi_mask = s->connected & s->data_gi & s->data_bi & ~s->data_oe;
+
+    uint32_t data_ii = s->data_ii & ii_mask;
+    uint32_t data_ib = s->data_ib & bi_mask;
+    uint32_t pull_in = s->pull_en & s->pull_sel & pi_mask;
+    uint32_t data_in = data_ii | data_ib | pull_in;
+
+    trace_ot_gpio_in_ignore(s->ot_id, s->connected, s->data_gi, s->data_bi,
+                            s->data_oe);
+    trace_ot_gpio_in_line(s->ot_id, s->data_ii, ii_mask, data_ii);
+    trace_ot_gpio_in_backend(s->ot_id, s->data_ib, bi_mask, data_ib);
+    trace_ot_gpio_in_pull(s->ot_id, s->pull_en, s->pull_sel, pi_mask, pull_in);
+
+    /* apply inversion if any */
+    data_in ^= s->invert;
+
+    /* inject back output pin values into input */
+    uint32_t data_mix = data_in | (s->data_out & s->data_oe);
+
+    s->regs[R_DATA_IN] = data_mix;
+
+    trace_ot_gpio_in_update(s->ot_id, s->invert, data_in, s->data_out,
+                            data_mix);
+
+    ot_gpio_eg_update_intr_level(s);
+    ot_gpio_eg_update_intr_edge(s, prev);
+    ot_gpio_eg_update_irqs(s);
+}
+
+static void ot_gpio_eg_update_data_out(OtGpioEgState *s)
+{
+    uint32_t outv = s->data_out;
+    /* assume invert is performed on device output data, not on pull up/down */
+    outv ^= s->invert;
+
+    uint32_t out_en = s->data_oe;
+
+    /* if open drain is active and output is high, disable output enable */
+    out_en &= ~(s->opendrain & outv);
+
+    /* keep non- opendrain high values */
+    outv &= out_en;
+
+    trace_ot_gpio_out_update(s->ot_id, outv, 0, 0);
+    for (unsigned ix = 0; ix < PARAM_NUM_IO; ix++) {
+        if ((out_en >> ix) & 1u) {
+            int level = (int)((outv >> ix) & 1u);
+            if (level != ibex_irq_get_level(&s->gpos[ix])) {
+                trace_ot_gpio_out_update_line_bool(s->ot_id, ix, level);
+            }
+            ibex_irq_set(&s->gpos[ix], level);
+        }
+    }
+}
+
+static void ot_gpio_eg_in_change(void *opaque, int no, int level)
+{
+    OtGpioEgState *s = opaque;
+
+    trace_ot_gpio_in_change(s->ot_id, no, level < 0, level > 0, 0);
+
+    g_assert(no < PARAM_NUM_IO);
+
+    bool ignore = level < 0;
+    bool on = (bool)level;
+    uint32_t bit = 1u << no;
+
+    /*
+     * any time a signal is received from a remote device the pin is considered
+     * as connected and backend no longer may update its state.
+     */
+    s->connected |= bit;
+
+    if (!ignore) {
+        if (on) {
+            s->data_ii |= bit;
+        } else {
+            s->data_ii &= ~bit;
+        }
+        s->data_gi &= ~bit;
+    } else {
+        s->data_gi |= bit;
+    }
+
+    ot_gpio_eg_update_data_in(s);
+    ot_gpio_eg_update_backend(s, false);
+}
+
+static void ot_gpio_eg_pad_attr_change(void *opaque, int no, int level)
+{
+    OtGpioEgState *s = opaque;
+
+    g_assert(no < PARAM_NUM_IO);
+
+    uint32_t cfg = (uint32_t)level;
+    uint32_t bit = 1u << no;
+    char confstr[4u];
+
+    if (cfg & OT_PINMUX_PAD_ATTR_INVERT_MASK) {
+        s->invert |= bit;
+        confstr[0u] = '!';
+    } else {
+        s->invert &= ~bit;
+        confstr[0u] = '.';
+    }
+
+    if (cfg & (OT_PINMUX_PAD_ATTR_OD_EN_MASK |
+               OT_PINMUX_PAD_ATTR_VIRTUAL_OD_EN_MASK)) {
+        s->opendrain |= bit;
+        confstr[1u] = 'o';
+    } else {
+        s->opendrain &= ~bit;
+        confstr[1u] = '.';
+    }
+
+    if (cfg & OT_PINMUX_PAD_ATTR_PULL_SELECT_MASK) {
+        s->pull_sel |= bit;
+        confstr[2u] = 'h';
+    } else {
+        s->pull_sel &= ~bit;
+        confstr[2u] = 'l';
+    }
+
+    if (cfg & OT_PINMUX_PAD_ATTR_PULL_EN_MASK) {
+        s->pull_en |= bit;
+    } else {
+        s->pull_en &= ~bit;
+        confstr[2u] = '.';
+    }
+    confstr[3u] = '\0';
+
+    trace_ot_gpio_pad_attr_change(s->ot_id, no, cfg, confstr);
+
+    ot_gpio_eg_update_data_in(s);
+    ot_gpio_eg_update_data_out(s);
+    ot_gpio_eg_update_backend(s, false);
+}
+
+static uint64_t ot_gpio_eg_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtGpioEgState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_DATA_IN:
+    case R_DIRECT_OUT:
+    case R_DIRECT_OE:
+    case R_INTR_CTRL_EN_RISING:
+    case R_INTR_CTRL_EN_FALLING:
+    case R_INTR_CTRL_EN_LVLHIGH:
+    case R_INTR_CTRL_EN_LVLLOW:
+    case R_CTRL_EN_INPUT_FILTER:
+        val32 = s->regs[reg];
+        break;
+    case R_MASKED_OUT_LOWER:
+        val32 = s->data_out & MASKED_VALUE_MASK;
+        break;
+    case R_MASKED_OUT_UPPER:
+        val32 = (s->data_out >> MASKED_MASK_SHIFT) & MASKED_VALUE_MASK;
+        break;
+    case R_MASKED_OE_LOWER:
+        val32 = s->data_oe & MASKED_VALUE_MASK;
+        break;
+    case R_MASKED_OE_UPPER:
+        val32 = (s->data_oe >> MASKED_MASK_SHIFT) & MASKED_VALUE_MASK;
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0u;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_gpio_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                              pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_gpio_eg_write(void *opaque, hwaddr addr, uint64_t val64,
+                             unsigned size)
+{
+    OtGpioEgState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+    uint32_t mask;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_gpio_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_gpio_eg_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        s->regs[reg] = val32;
+        ot_gpio_eg_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        s->regs[R_INTR_STATE] |= val32;
+        ot_gpio_eg_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    case R_DIRECT_OUT:
+        s->regs[reg] = val32;
+        s->data_out = val32;
+        ot_gpio_eg_update_data_out(s);
+        ot_gpio_eg_update_backend(s, false);
+        ot_gpio_eg_update_data_in(s);
+        break;
+    case R_DIRECT_OE:
+        s->regs[reg] = val32;
+        s->data_oe = val32;
+        ot_gpio_eg_update_data_out(s);
+        ot_gpio_eg_update_backend(s, false);
+        ot_gpio_eg_update_data_in(s);
+        break;
+    case R_MASKED_OUT_LOWER:
+        s->regs[reg] = val32;
+        mask = val32 >> MASKED_MASK_SHIFT;
+        s->data_out &= ~mask;
+        s->data_out |= val32 & mask;
+        ot_gpio_eg_update_data_out(s);
+        ot_gpio_eg_update_backend(s, false);
+        ot_gpio_eg_update_data_in(s);
+        break;
+    case R_MASKED_OUT_UPPER:
+        s->regs[reg] = val32;
+        mask = val32 & MASKED_MASK_MASK;
+        s->data_out &= ~mask;
+        s->data_out |= (val32 << MASKED_MASK_SHIFT) & mask;
+        ot_gpio_eg_update_data_out(s);
+        ot_gpio_eg_update_backend(s, false);
+        ot_gpio_eg_update_data_in(s);
+        break;
+    case R_MASKED_OE_LOWER:
+        s->regs[reg] = val32;
+        mask = val32 >> MASKED_MASK_SHIFT;
+        s->data_oe &= ~mask;
+        s->data_oe |= val32 & mask;
+        ot_gpio_eg_update_data_out(s);
+        ot_gpio_eg_update_backend(s, false);
+        ot_gpio_eg_update_data_in(s);
+        break;
+    case R_MASKED_OE_UPPER:
+        s->regs[reg] = val32;
+        mask = val32 & MASKED_MASK_MASK;
+        s->data_oe &= ~mask;
+        s->data_oe |= (val32 << MASKED_MASK_SHIFT) & mask;
+        ot_gpio_eg_update_data_out(s);
+        ot_gpio_eg_update_backend(s, false);
+        ot_gpio_eg_update_data_in(s);
+        break;
+    case R_INTR_CTRL_EN_RISING:
+    case R_INTR_CTRL_EN_FALLING:
+        s->regs[reg] = val32;
+        break;
+    case R_INTR_CTRL_EN_LVLHIGH:
+    case R_INTR_CTRL_EN_LVLLOW:
+        s->regs[reg] = val32;
+        ot_gpio_eg_update_data_in(s);
+        break;
+    case R_CTRL_EN_INPUT_FILTER:
+        /* nothing can be done at QEMU level for sampling that fast */
+        s->regs[reg] = val32;
+        break;
+    case R_DATA_IN:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static int ot_gpio_eg_chr_can_receive(void *opaque)
+{
+    OtGpioEgState *s = opaque;
+
+    return (int)sizeof(s->ibuf) - (int)s->ipos;
+}
+
+static void ot_gpio_eg_chr_receive(void *opaque, const uint8_t *buf, int size)
+{
+    OtGpioEgState *s = opaque;
+
+    if (s->ipos + (unsigned)size > sizeof(s->ibuf)) {
+        error_report("%s: %s: Unexpected chardev receive\n", __func__,
+                     s->ot_id);
+        return;
+    }
+
+    memcpy(&s->ibuf[s->ipos], buf, (size_t)size);
+    s->ipos += (unsigned)size;
+
+    for (;;) {
+        const char *eol = memchr(s->ibuf, (int)'\n', s->ipos);
+        if (!eol) {
+            if (s->ipos > 10u) {
+                /* discard any garbage */
+                memset(s->ibuf, 0, sizeof(s->ibuf));
+                s->ipos = 0;
+            }
+            return;
+        }
+        unsigned eolpos = eol - s->ibuf;
+        if (eolpos < 10u) {
+            /* discard incomplete lines */
+            memmove(s->ibuf, eol + 1u, eolpos + 1u);
+            s->ipos = 0;
+            continue;
+        }
+        uint32_t data_in = 0;
+        char cmd = '\0';
+
+        /* NOLINTNEXTLINE */
+        int ret = sscanf(s->ibuf, "%c:%08x", &cmd, &data_in);
+        /* discard current command, even if invalid, up to first EOL */
+        const char *next = eol + 1u;
+        unsigned rem = (unsigned)(&s->ibuf[s->ipos] - next);
+        memmove(s->ibuf, next, rem);
+        s->ipos = rem;
+
+        if (ret == 2) {
+            trace_ot_gpio_backend_recv(s->ot_id, cmd, data_in);
+            if (cmd == 'M') {
+                s->data_bi = data_in;
+                ot_gpio_eg_update_data_in(s);
+            } else if (cmd == 'I') {
+                s->data_ib = data_in;
+                ot_gpio_eg_update_data_in(s);
+            } else if (cmd == 'R') {
+                ot_gpio_eg_update_backend(s, true);
+            } else {
+                qemu_log_mask(LOG_UNIMP, "%s: unsupported command %c\n",
+                              __func__, cmd);
+            }
+        }
+    }
+}
+
+static void ot_gpio_eg_init_backend(OtGpioEgState *s)
+{
+    if (!qemu_chr_fe_backend_connected(&s->chr)) {
+        return;
+    }
+
+    if (s->wipe) {
+        /* query backend for current input status */
+        char buf[16u];
+        int len = snprintf(buf, sizeof(buf), "C:%08x\r\n", 0);
+        qemu_chr_fe_write(&s->chr, (const uint8_t *)buf, len);
+    }
+}
+
+static void ot_gpio_eg_update_backend(OtGpioEgState *s, bool force)
+{
+    if (!qemu_chr_fe_backend_connected(&s->chr)) {
+        return;
+    }
+
+    /*
+     * use the MS DOS CR LF syntax because some people keep using
+     * Windows-style terminal.
+     */
+
+    uint32_t outv = s->data_out;
+    /* assume invert is performed on device output data, not on pull up/down */
+    outv ^= s->invert;
+
+    uint32_t out_en = s->data_oe;
+
+    /* if open drain is active and output is high, disable output enable */
+    out_en &= ~(s->opendrain & outv);
+
+    uint32_t active = s->pull_en | out_en;
+    outv &= out_en;
+
+    OtGpioEgBackendState bstate = { .hi_z = ~active,
+                                    .pull_v = s->pull_sel,
+                                    .out_en = out_en,
+                                    .out_v = outv,
+                                    .in_m = s->regs[R_DATA_IN] };
+
+    /*
+     * use the MS DOS CR LF syntax because some people keep using
+     * Windows-style terminal.
+     */
+
+    if (!memcmp(&bstate, &s->backend_state, sizeof(OtGpioEgBackendState)) &&
+        !force) {
+        /* do not emit new state if nothing has changed */
+        return;
+    }
+
+    char buf[64u];
+    size_t len = 0;
+
+    len += snprintf(&buf[len], sizeof(buf) - len, "Z:%08x\r\n", bstate.hi_z);
+    len += snprintf(&buf[len], sizeof(buf) - len, "P:%08x\r\n", bstate.pull_v);
+    len += snprintf(&buf[len], sizeof(buf) - len, "D:%08x\r\n", bstate.out_en);
+    len += snprintf(&buf[len], sizeof(buf) - len, "O:%08x\r\n", bstate.out_v);
+    len += snprintf(&buf[len], sizeof(buf) - len, "Y:%08x\r\n", bstate.in_m);
+
+    s->backend_state = bstate;
+
+    qemu_chr_fe_write(&s->chr, (const uint8_t *)buf, (int)len);
+    /* replace CRLF so that trace is kept on a single line */
+    buf[10] = buf[22] = buf[34] = buf[46] = ',';
+    buf[11] = buf[23] = buf[35] = buf[47] = ' ';
+    buf[58] = '\0';
+    trace_ot_gpio_backend_send(s->ot_id, buf);
+}
+
+static void ot_gpio_eg_chr_event_hander(void *opaque, QEMUChrEvent event)
+{
+    OtGpioEgState *s = opaque;
+
+    if (event == CHR_EVENT_OPENED) {
+        if (object_dynamic_cast(OBJECT(s->chr.chr), TYPE_CHARDEV_SERIAL)) {
+            ot_common_ignore_chr_status_lines(&s->chr);
+        }
+
+        if (!qemu_chr_fe_backend_connected(&s->chr)) {
+            return;
+        }
+
+        ot_gpio_eg_update_backend(s, true);
+
+        /* query backend for current input status */
+        char buf[16u];
+        int len = snprintf(buf, sizeof(buf), "Q:%08x\r\n", s->data_oe);
+        qemu_chr_fe_write(&s->chr, (const uint8_t *)buf, len);
+        buf[MIN((unsigned)len - 1, sizeof(buf) - 1u)] = '\0';
+        trace_ot_gpio_backend_send(s->ot_id, buf);
+    }
+}
+
+static gboolean
+ot_gpio_eg_chr_watch_cb(void *do_not_use, GIOCondition cond, void *opaque)
+{
+    OtGpioEgState *s = opaque;
+    (void)do_not_use;
+    (void)cond;
+
+    s->watch_tag = 0;
+
+    return FALSE;
+}
+
+static int ot_gpio_eg_chr_be_change(void *opaque)
+{
+    OtGpioEgState *s = opaque;
+
+    qemu_chr_fe_set_handlers(&s->chr, &ot_gpio_eg_chr_can_receive,
+                             &ot_gpio_eg_chr_receive,
+                             &ot_gpio_eg_chr_event_hander,
+                             &ot_gpio_eg_chr_be_change, s, NULL, true);
+
+    memset(s->ibuf, 0, sizeof(s->ibuf));
+    s->ipos = 0;
+
+    if (s->watch_tag > 0) {
+        g_source_remove(s->watch_tag);
+        /* NOLINTNEXTLINE(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+                                             &ot_gpio_eg_chr_watch_cb, s);
+    }
+
+    return 0;
+}
+
+static const MemoryRegionOps ot_gpio_eg_regs_ops = {
+    .read = &ot_gpio_eg_read,
+    .write = &ot_gpio_eg_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const Property ot_gpio_eg_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtGpioEgState, ot_id),
+    DEFINE_PROP_UINT32("in", OtGpioEgState, reset_in, 0u),
+    DEFINE_PROP_UINT32("out", OtGpioEgState, reset_out, 0u),
+    DEFINE_PROP_UINT32("oe", OtGpioEgState, reset_oe, 0u),
+    DEFINE_PROP_BOOL("wipe", OtGpioEgState, wipe, false),
+    DEFINE_PROP_CHR("chardev", OtGpioEgState, chr),
+};
+
+static void ot_gpio_eg_reset_enter(Object *obj, ResetType type)
+{
+    OtGpioEgClass *c = OT_GPIO_EG_GET_CLASS(obj);
+    OtGpioEgState *s = OT_GPIO_EG(obj);
+
+    trace_ot_gpio_reset(s->ot_id, "> enter");
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->regs, 0, sizeof(s->regs));
+    memset(&s->backend_state, 0, sizeof(s->backend_state));
+
+    /* reset_* fields are properties, never get reset */
+    s->data_ii = s->reset_in;
+    s->data_out = s->reset_out;
+    s->data_oe = s->reset_oe;
+    /* all input disable until signal is received, or output is forced */
+    s->data_gi = ~s->reset_oe;
+    s->pull_en = 0;
+    s->pull_sel = 0;
+    s->invert = 0;
+    s->connected = 0;
+
+    s->regs[R_DATA_IN] = s->reset_in;
+    s->regs[R_DIRECT_OUT] = s->reset_out;
+    s->regs[R_DIRECT_OE] = s->reset_oe;
+
+    /*
+     * Sample the input lines (e.g. the chardev) which persist their state
+     * across reset. This is important for cases like straps which are held
+     * asserted across a reset.
+     */
+    ot_gpio_eg_update_data_in(s);
+
+    ibex_irq_set(&s->alert, 0);
+
+    trace_ot_gpio_reset(s->ot_id, "< enter");
+}
+
+static void ot_gpio_eg_reset_exit(Object *obj, ResetType type)
+{
+    /*
+     * use of a Resettable full API enables performing I/O updates only once
+     * the pinmux configuration has been received (from its own reset stage)
+     */
+    OtGpioEgClass *c = OT_GPIO_EG_GET_CLASS(obj);
+    OtGpioEgState *s = OT_GPIO_EG(obj);
+
+    trace_ot_gpio_reset(s->ot_id, "> exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    ot_gpio_eg_init_backend(s);
+    ot_gpio_eg_update_data_out(s);
+    ot_gpio_eg_update_backend(s, true);
+
+    /*
+     * do not reset the input backend buffer as external GPIO changes is fully
+     * async with OT reset. However, it should be reset when the backend changes
+     */
+    trace_ot_gpio_reset(s->ot_id, "< exit");
+}
+
+static void ot_gpio_eg_realize(DeviceState *dev, Error **errp)
+{
+    OtGpioEgState *s = OT_GPIO_EG(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+
+    qemu_chr_fe_set_handlers(&s->chr, &ot_gpio_eg_chr_can_receive,
+                             &ot_gpio_eg_chr_receive,
+                             &ot_gpio_eg_chr_event_hander,
+                             &ot_gpio_eg_chr_be_change, s, NULL, true);
+}
+
+static void ot_gpio_eg_init(Object *obj)
+{
+    OtGpioEgState *s = OT_GPIO_EG(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_gpio_eg_regs_ops, s,
+                          TYPE_OT_GPIO_EG, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->irqs = g_new(IbexIRQ, PARAM_NUM_IO);
+    s->gpos = g_new(IbexIRQ, PARAM_NUM_IO);
+    for (unsigned ix = 0; ix < PARAM_NUM_IO; ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    ibex_qdev_init_irqs_default(obj, s->gpos, OT_GPIO_OUT, PARAM_NUM_IO, -1);
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_gpio_eg_in_change, OT_GPIO_IN,
+                            PARAM_NUM_IO);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_gpio_eg_pad_attr_change,
+                            OT_PINMUX_PAD, PARAM_NUM_IO);
+
+    /* Backend state persists across reset so initialise it once now */
+    s->data_ib = 0u;
+    s->data_bi = UINT32_MAX;
+}
+
+static void ot_gpio_eg_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_gpio_eg_realize;
+    device_class_set_props(dc, ot_gpio_eg_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(dc);
+    OtGpioEgClass *gc = OT_GPIO_EG_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_gpio_eg_reset_enter, NULL,
+                                       &ot_gpio_eg_reset_exit,
+                                       &gc->parent_phases);
+}
+
+static const TypeInfo ot_gpio_eg_info = {
+    .name = TYPE_OT_GPIO_EG,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtGpioEgState),
+    .instance_init = &ot_gpio_eg_init,
+    .class_size = sizeof(OtGpioEgClass),
+    .class_init = &ot_gpio_eg_class_init,
+};
+
+static void ot_gpio_eg_register_types(void)
+{
+    type_register_static(&ot_gpio_eg_info);
+}
+
+type_init(ot_gpio_eg_register_types);
diff --git a/hw/opentitan/ot_hmac.c b/hw/opentitan/ot_hmac.c
new file mode 100644
index 0000000000000..bbe8152486af7
--- /dev/null
+++ b/hw/opentitan/ot_hmac.c
@@ -0,0 +1,1362 @@
+/*
+ * QEMU OpenTitan HMAC device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Copyright (c) 2024-2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "qemu/fifo8.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_clkmgr.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_hmac.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "tomcrypt.h"
+#include "trace.h"
+
+/* Input FIFO length is 64 bytes (16 x 32 bits) */
+#define OT_HMAC_FIFO_LENGTH 64u
+
+/* Maximum digest length is 64 bytes (512 bits) */
+#define OT_HMAC_MAX_DIGEST_LENGTH 64u
+
+/* Maximum key length is 128 bytes (1024 bits) */
+#define OT_HMAC_MAX_KEY_LENGTH 128u
+
+#define PARAM_NUM_IRQS 3u
+
+/* clang-format off */
+REG32(INTR_STATE, 0x00u)
+    SHARED_FIELD(INTR_HMAC_DONE, 0u, 1u)
+    SHARED_FIELD(INTR_FIFO_EMPTY, 1u, 1u)
+    SHARED_FIELD(INTR_HMAC_ERR, 2u, 1u)
+REG32(INTR_ENABLE, 0x04u)
+REG32(INTR_TEST, 0x08u)
+REG32(ALERT_TEST, 0x0cu)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(CFG, 0x10u)
+    FIELD(CFG, HMAC_EN, 0u, 1u)
+    FIELD(CFG, SHA_EN, 1u, 1u)
+    FIELD(CFG, ENDIAN_SWAP, 2u, 1u)
+    FIELD(CFG, DIGEST_SWAP, 3u, 1u)
+    FIELD(CFG, KEY_SWAP, 4u, 1u)
+    FIELD(CFG, DIGEST_SIZE, 5u, 4u)
+    FIELD(CFG, KEY_LENGTH, 9u, 6u)
+REG32(CMD, 0x14u)
+    FIELD(CMD, HASH_START, 0u, 1u)
+    FIELD(CMD, HASH_PROCESS, 1u, 1u)
+    FIELD(CMD, HASH_STOP, 2u, 1u)
+    FIELD(CMD, HASH_CONTINUE, 3u, 1u)
+REG32(STATUS, 0x18u)
+    FIELD(STATUS, HMAC_IDLE, 0u, 1u)
+    FIELD(STATUS, FIFO_EMPTY, 1u, 1u)
+    FIELD(STATUS, FIFO_FULL, 2u, 1u)
+    FIELD(STATUS, FIFO_DEPTH, 4u, 6u)
+REG32(ERR_CODE, 0x1cu)
+#define R_ERR_CODE_PUSH_MSG_WHEN_SHA_DISABLED   0x00000001u
+#define R_ERR_CODE_HASH_START_WHEN_SHA_DISABLED 0x00000002u
+#define R_ERR_CODE_UPDATE_SECRET_KEY_INPROCESS  0x00000003u
+#define R_ERR_CODE_HASH_START_WHEN_ACTIVE       0x00000004u
+#define R_ERR_CODE_PUSH_MSG_WHEN_DISALLOWED     0x00000005u
+#define R_ERR_CODE_INVALID_CONFIG               0x00000006u
+REG32(WIPE_SECRET, 0x20u)
+REG32(KEY_0, 0x24u)
+REG32(KEY_1, 0x28u)
+REG32(KEY_2, 0x2cu)
+REG32(KEY_3, 0x30u)
+REG32(KEY_4, 0x34u)
+REG32(KEY_5, 0x38u)
+REG32(KEY_6, 0x3cu)
+REG32(KEY_7, 0x40u)
+REG32(KEY_8, 0x44u)
+REG32(KEY_9, 0x48u)
+REG32(KEY_10, 0x4cu)
+REG32(KEY_11, 0x50u)
+REG32(KEY_12, 0x54u)
+REG32(KEY_13, 0x58u)
+REG32(KEY_14, 0x5cu)
+REG32(KEY_15, 0x60u)
+REG32(KEY_16, 0x64u)
+REG32(KEY_17, 0x68u)
+REG32(KEY_18, 0x6cu)
+REG32(KEY_19, 0x70u)
+REG32(KEY_20, 0x74u)
+REG32(KEY_21, 0x78u)
+REG32(KEY_22, 0x7cu)
+REG32(KEY_23, 0x80u)
+REG32(KEY_24, 0x84u)
+REG32(KEY_25, 0x88u)
+REG32(KEY_26, 0x8cu)
+REG32(KEY_27, 0x90u)
+REG32(KEY_28, 0x94u)
+REG32(KEY_29, 0x98u)
+REG32(KEY_30, 0x9cu)
+REG32(KEY_31, 0xa0u)
+REG32(DIGEST_0, 0xa4u)
+REG32(DIGEST_1, 0xa8u)
+REG32(DIGEST_2, 0xacu)
+REG32(DIGEST_3, 0xb0u)
+REG32(DIGEST_4, 0xb4u)
+REG32(DIGEST_5, 0xb8u)
+REG32(DIGEST_6, 0xbcu)
+REG32(DIGEST_7, 0xc0u)
+REG32(DIGEST_8, 0xc4u)
+REG32(DIGEST_9, 0xc8u)
+REG32(DIGEST_10, 0xccu)
+REG32(DIGEST_11, 0xd0u)
+REG32(DIGEST_12, 0xd4u)
+REG32(DIGEST_13, 0xd8u)
+REG32(DIGEST_14, 0xdcu)
+REG32(DIGEST_15, 0xe0u)
+REG32(MSG_LENGTH_LOWER, 0xe4u)
+REG32(MSG_LENGTH_UPPER, 0xe8u)
+/* clang-format on */
+
+#define INTR_MASK \
+    (INTR_HMAC_ERR_MASK | INTR_FIFO_EMPTY_MASK | INTR_HMAC_DONE_MASK)
+
+/* base offset for MMIO registers */
+#define OT_HMAC_REGS_BASE 0x00000000u
+/* base offset for MMIO FIFO */
+#define OT_HMAC_FIFO_BASE 0x00001000u
+/* length of MMIO FIFO */
+#define OT_HMAC_FIFO_SIZE 0x00001000u
+/* length of the whole device MMIO region */
+#define OT_HMAC_WHOLE_SIZE (OT_HMAC_FIFO_BASE + OT_HMAC_FIFO_SIZE)
+
+/* value representing 'SHA2_NONE' in the config digest size field */
+#define OT_HMAC_CFG_DIGEST_SHA2_NONE 0x8u
+/* value representing 'KEY_NONE' in the config key length field */
+#define OT_HMAC_CFG_KEY_LENGTH_NONE 0x20u
+
+#define OT_HMAC_CLOCK_ACTIVE "clock-active"
+#define OT_HMAC_CLOCK_INPUT  "clock-in"
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_MSG_LENGTH_UPPER)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CFG),
+    REG_NAME_ENTRY(CMD),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(ERR_CODE),
+    REG_NAME_ENTRY(WIPE_SECRET),
+    REG_NAME_ENTRY(KEY_0),
+    REG_NAME_ENTRY(KEY_1),
+    REG_NAME_ENTRY(KEY_2),
+    REG_NAME_ENTRY(KEY_3),
+    REG_NAME_ENTRY(KEY_4),
+    REG_NAME_ENTRY(KEY_5),
+    REG_NAME_ENTRY(KEY_6),
+    REG_NAME_ENTRY(KEY_7),
+    REG_NAME_ENTRY(KEY_8),
+    REG_NAME_ENTRY(KEY_9),
+    REG_NAME_ENTRY(KEY_10),
+    REG_NAME_ENTRY(KEY_11),
+    REG_NAME_ENTRY(KEY_12),
+    REG_NAME_ENTRY(KEY_13),
+    REG_NAME_ENTRY(KEY_14),
+    REG_NAME_ENTRY(KEY_15),
+    REG_NAME_ENTRY(KEY_16),
+    REG_NAME_ENTRY(KEY_17),
+    REG_NAME_ENTRY(KEY_18),
+    REG_NAME_ENTRY(KEY_19),
+    REG_NAME_ENTRY(KEY_20),
+    REG_NAME_ENTRY(KEY_21),
+    REG_NAME_ENTRY(KEY_22),
+    REG_NAME_ENTRY(KEY_23),
+    REG_NAME_ENTRY(KEY_24),
+    REG_NAME_ENTRY(KEY_25),
+    REG_NAME_ENTRY(KEY_26),
+    REG_NAME_ENTRY(KEY_27),
+    REG_NAME_ENTRY(KEY_28),
+    REG_NAME_ENTRY(KEY_29),
+    REG_NAME_ENTRY(KEY_30),
+    REG_NAME_ENTRY(KEY_31),
+    REG_NAME_ENTRY(DIGEST_0),
+    REG_NAME_ENTRY(DIGEST_1),
+    REG_NAME_ENTRY(DIGEST_2),
+    REG_NAME_ENTRY(DIGEST_3),
+    REG_NAME_ENTRY(DIGEST_4),
+    REG_NAME_ENTRY(DIGEST_5),
+    REG_NAME_ENTRY(DIGEST_6),
+    REG_NAME_ENTRY(DIGEST_7),
+    REG_NAME_ENTRY(DIGEST_8),
+    REG_NAME_ENTRY(DIGEST_9),
+    REG_NAME_ENTRY(DIGEST_10),
+    REG_NAME_ENTRY(DIGEST_11),
+    REG_NAME_ENTRY(DIGEST_12),
+    REG_NAME_ENTRY(DIGEST_13),
+    REG_NAME_ENTRY(DIGEST_14),
+    REG_NAME_ENTRY(DIGEST_15),
+    REG_NAME_ENTRY(MSG_LENGTH_LOWER),
+    REG_NAME_ENTRY(MSG_LENGTH_UPPER),
+};
+#undef REG_NAME_ENTRY
+
+typedef enum OtHMACDigestSize {
+    HMAC_SHA2_NONE,
+    HMAC_SHA2_256,
+    HMAC_SHA2_384,
+    HMAC_SHA2_512,
+} OtHMACDigestSize;
+
+typedef enum OtHMACKeyLength {
+    HMAC_KEY_NONE,
+    HMAC_KEY_128,
+    HMAC_KEY_256,
+    HMAC_KEY_384,
+    HMAC_KEY_512,
+    HMAC_KEY_1024,
+} OtHMACKeyLength;
+
+struct OtHMACRegisters {
+    uint32_t intr_state;
+    uint32_t intr_enable;
+    uint32_t alert_test;
+    uint32_t cfg;
+    uint32_t cmd;
+    uint32_t err_code;
+    uint32_t wipe_secret;
+    uint32_t key[OT_HMAC_MAX_KEY_LENGTH / sizeof(uint32_t)];
+    uint32_t digest[OT_HMAC_MAX_DIGEST_LENGTH / sizeof(uint32_t)];
+    uint64_t msg_length;
+};
+typedef struct OtHMACRegisters OtHMACRegisters;
+
+struct OtHMACContext {
+    hash_state state;
+    OtHMACDigestSize digest_size_started;
+};
+typedef struct OtHMACContext OtHMACContext;
+
+struct OtHMACState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    MemoryRegion regs_mmio;
+    MemoryRegion fifo_mmio;
+
+    IbexIRQ irqs[PARAM_NUM_IRQS];
+    IbexIRQ alert;
+    IbexIRQ clock_active;
+    unsigned pclk; /* Current input clock */
+    const char *clock_src_name; /* IRQ name once connected */
+
+    OtHMACRegisters *regs;
+    OtHMACContext *ctx;
+    Fifo8 input_fifo;
+
+    char *ot_id;
+    char *clock_name;
+    DeviceState *clock_src;
+};
+
+struct OtHMACClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static inline OtHMACDigestSize ot_hmac_get_digest_size(uint32_t cfg_reg)
+{
+    switch ((cfg_reg & R_CFG_DIGEST_SIZE_MASK) >> R_CFG_DIGEST_SIZE_SHIFT) {
+    case 0x1u:
+        return HMAC_SHA2_256;
+    case 0x2u:
+        return HMAC_SHA2_384;
+    case 0x4u:
+        return HMAC_SHA2_512;
+    case 0x8u:
+    default:
+        return HMAC_SHA2_NONE;
+    }
+}
+
+static size_t ot_hmac_get_digest_bytes(OtHMACDigestSize digest_size)
+{
+    switch (digest_size) {
+    case HMAC_SHA2_256:
+        return 32u;
+    case HMAC_SHA2_384:
+        return 48u;
+    case HMAC_SHA2_512:
+        return 64u;
+    case HMAC_SHA2_NONE:
+    default:
+        /*
+         * Should never happen: digest size was validated when calling start /
+         * continue to begin operation.
+         */
+        g_assert_not_reached();
+        return 0u;
+    }
+}
+
+static size_t ot_hmac_get_block_size_bytes(OtHMACState *s)
+{
+    switch (ot_hmac_get_digest_size(s->regs->cfg)) {
+    case HMAC_SHA2_256:
+        return 64u;
+    case HMAC_SHA2_384:
+    case HMAC_SHA2_512:
+        return 128u;
+    case HMAC_SHA2_NONE:
+    default:
+        /*
+         * Should never happen: digest size was validated when calling start /
+         * continue to begin operation.
+         */
+        g_assert_not_reached();
+        return 0u;
+    }
+}
+
+static inline OtHMACKeyLength ot_hmac_get_key_length(uint32_t cfg_reg)
+{
+    switch ((cfg_reg & R_CFG_KEY_LENGTH_MASK) >> R_CFG_KEY_LENGTH_SHIFT) {
+    case 0x01u:
+        return HMAC_KEY_128;
+    case 0x02u:
+        return HMAC_KEY_256;
+    case 0x04u:
+        return HMAC_KEY_384;
+    case 0x08u:
+        return HMAC_KEY_512;
+    case 0x10u:
+        return HMAC_KEY_1024;
+    case 0x20u:
+    default:
+        return HMAC_KEY_NONE;
+    }
+}
+
+static size_t ot_hmac_get_key_bytes(OtHMACState *s)
+{
+    switch (ot_hmac_get_key_length(s->regs->cfg)) {
+    case HMAC_KEY_128:
+        return 16u;
+    case HMAC_KEY_256:
+        return 32u;
+    case HMAC_KEY_384:
+        return 48u;
+    case HMAC_KEY_512:
+        return 64u;
+    case HMAC_KEY_1024:
+        return 128u;
+    case HMAC_KEY_NONE:
+    default:
+        /*
+         * Should never happen: key length was validated when calling start /
+         * continue to begin operation if HMAC was enabled, and HMAC cannot be
+         * enabled while the SHA engine is in operation.
+         */
+        g_assert_not_reached();
+        return 0u;
+    }
+}
+
+static inline bool ot_hmac_key_length_supported(OtHMACDigestSize digest_size,
+                                                OtHMACKeyLength key_length)
+{
+    return !(digest_size == HMAC_SHA2_256 && key_length == HMAC_KEY_1024);
+}
+
+static void ot_hmac_update_irqs(OtHMACState *s)
+{
+    uint32_t levels = s->regs->intr_state & s->regs->intr_enable;
+    trace_ot_hmac_irqs(s->ot_id, s->regs->intr_state, s->regs->intr_enable,
+                       levels);
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((levels >> ix) & 0x1u));
+    }
+}
+
+static void ot_hmac_update_alert(OtHMACState *s)
+{
+    bool level = s->regs->alert_test & R_ALERT_TEST_FATAL_FAULT_MASK;
+    ibex_irq_set(&s->alert, level);
+}
+
+static void ot_hmac_report_error(OtHMACState *s, uint32_t error)
+{
+    s->regs->err_code = error;
+    s->regs->intr_state |= INTR_HMAC_ERR_MASK;
+    ot_hmac_update_irqs(s);
+}
+
+static void ot_hmac_writeback_digest_state(OtHMACState *s)
+{
+    /* copy intermediary digest to mock HMAC's stop/continue behaviour. */
+    switch (s->ctx->digest_size_started) {
+    case HMAC_SHA2_256:
+        for (unsigned idx = 0; idx < 8u; idx++) {
+            STORE32H(s->ctx->state.sha256.state[idx], s->regs->digest + idx);
+        }
+        break;
+    case HMAC_SHA2_384:
+        /*
+         * Even though SHA384 only uses the first six uint64_t values of
+         * the SHA512 digest, we must store all for intermediary computation.
+         */
+    case HMAC_SHA2_512:
+        for (unsigned idx = 0; idx < 8u; idx++) {
+            STORE64H(s->ctx->state.sha512.state[idx],
+                     s->regs->digest + 2 * idx);
+        }
+        break;
+    case HMAC_SHA2_NONE:
+    default:
+        /*
+         * Should never happen: digest size was validated when calling start /
+         * continue to begin operation.
+         */
+        g_assert_not_reached();
+    }
+}
+
+static void ot_hmac_restore_context(OtHMACState *s)
+{
+    /*
+     * When restoring context, if HMAC is enabled we must add the block size to
+     * the message length to keep our cryptographic library consistent with the
+     * SW interface. This is because the extra block containing the key XORed
+     * with the inner pad is not included in the SW-visible message length.
+     */
+    unsigned msg_length = s->regs->msg_length;
+    if (s->regs->cfg & R_CFG_HMAC_EN_MASK) {
+        msg_length += ot_hmac_get_block_size_bytes(s) * 8u;
+    }
+
+    switch (s->ctx->digest_size_started) {
+    case HMAC_SHA2_256:
+        s->ctx->state.sha256.curlen = 0;
+        s->ctx->state.sha256.length = msg_length;
+        for (unsigned idx = 0; idx < 8u; idx++) {
+            LOAD32H(s->ctx->state.sha256.state[idx], s->regs->digest + idx);
+        }
+        break;
+    case HMAC_SHA2_384:
+        /*
+         * Even though SHA384 only uses the first six uint64_t values of
+         * the SHA512 digest, we must restore all for intermediary computation.
+         */
+    case HMAC_SHA2_512:
+        s->ctx->state.sha512.curlen = 0;
+        s->ctx->state.sha512.length = msg_length;
+        for (unsigned idx = 0; idx < 8u; idx++) {
+            LOAD64H(s->ctx->state.sha512.state[idx], s->regs->digest + 2 * idx);
+        }
+        break;
+    case HMAC_SHA2_NONE:
+    default:
+        /*
+         * Should never happen: digest size was validated when receiving the
+         * continue command to (re-)begin operation.
+         */
+        g_assert_not_reached();
+    }
+}
+
+static size_t ot_hmac_get_curlen(OtHMACState *s)
+{
+    switch (s->ctx->digest_size_started) {
+    case HMAC_SHA2_256:
+        return s->ctx->state.sha256.curlen;
+    case HMAC_SHA2_384:
+    case HMAC_SHA2_512:
+        return s->ctx->state.sha512.curlen;
+    case HMAC_SHA2_NONE:
+    default:
+        /*
+         * Should never happen: digest size was validated when calling start /
+         * continue to begin operation.
+         */
+        g_assert_not_reached();
+        return 0u;
+    }
+}
+
+static void ot_hmac_sha_init(OtHMACState *s, bool write_back)
+{
+    switch (s->ctx->digest_size_started) {
+    case HMAC_SHA2_256:
+        sha256_init(&s->ctx->state);
+        break;
+    case HMAC_SHA2_384:
+        sha384_init(&s->ctx->state);
+        break;
+    case HMAC_SHA2_512:
+        sha512_init(&s->ctx->state);
+        break;
+    case HMAC_SHA2_NONE:
+    default:
+        /*
+         * Should never happen: digest size was validated when calling start /
+         * continue to begin operation.
+         */
+        g_assert_not_reached();
+        return;
+    }
+    if (write_back) {
+        ot_hmac_writeback_digest_state(s);
+    }
+}
+
+static void ot_hmac_sha_process(OtHMACState *s, const uint8_t *in, size_t inlen,
+                                bool write_back)
+{
+    switch (s->ctx->digest_size_started) {
+    case HMAC_SHA2_256:
+        sha256_process(&s->ctx->state, in, inlen);
+        break;
+    /* NOLINTNEXTLINE */
+    case HMAC_SHA2_384:
+        sha384_process(&s->ctx->state, in, inlen);
+        break;
+    case HMAC_SHA2_512:
+        sha512_process(&s->ctx->state, in, inlen);
+        break;
+    case HMAC_SHA2_NONE:
+    default:
+        /*
+         * Should never happen: digest size was validated when calling start /
+         * continue to begin operation.
+         */
+        g_assert_not_reached();
+        return;
+    }
+    if (write_back) {
+        ot_hmac_writeback_digest_state(s);
+    }
+}
+
+static void ot_hmac_sha_done(OtHMACState *s)
+{
+    switch (s->ctx->digest_size_started) {
+    case HMAC_SHA2_256:
+        sha256_done(&s->ctx->state, (uint8_t *)s->regs->digest);
+        return;
+    case HMAC_SHA2_384:
+        sha384_done(&s->ctx->state, (uint8_t *)s->regs->digest);
+        return;
+    case HMAC_SHA2_512:
+        sha512_done(&s->ctx->state, (uint8_t *)s->regs->digest);
+        return;
+    case HMAC_SHA2_NONE:
+    default:
+        /*
+         * Should never happen: digest size was validated when calling start /
+         * continue to begin operation.
+         */
+        g_assert_not_reached();
+        return;
+    }
+}
+
+static void ot_hmac_compute_digest(OtHMACState *s)
+{
+    trace_ot_hmac_debug(s->ot_id, __func__);
+
+    /* HMAC mode, perform outer hash */
+    if (s->regs->cfg & R_CFG_HMAC_EN_MASK) {
+        ot_hmac_sha_done(s);
+
+        size_t key_length_b = ot_hmac_get_key_bytes(s);
+        size_t block_size_b = ot_hmac_get_block_size_bytes(s);
+        /* pad key to right with 0s when it is smaller than the block size. */
+        size_t pad_length_b = MAX(key_length_b, block_size_b);
+        size_t pad_length_w = pad_length_b / sizeof(uint64_t);
+        uint64_t opad[OT_HMAC_MAX_KEY_LENGTH / sizeof(uint64_t)];
+        memset(opad, 0, sizeof(opad));
+        memcpy(opad, s->regs->key, key_length_b);
+        for (size_t idx = 0; idx < pad_length_w; idx++) {
+            opad[idx] ^= 0x5c5c5c5c5c5c5c5cull;
+        }
+        ot_hmac_sha_init(s, false);
+        ot_hmac_sha_process(s, (const uint8_t *)opad, pad_length_b, false);
+        ot_hmac_sha_process(s, (const uint8_t *)s->regs->digest,
+                            ot_hmac_get_digest_bytes(
+                                s->ctx->digest_size_started),
+                            true);
+    }
+    ot_hmac_sha_done(s);
+}
+
+static void ot_hmac_process_fifo(OtHMACState *s)
+{
+    trace_ot_hmac_debug(s->ot_id, __func__);
+
+    bool stop = s->regs->cmd & R_CMD_HASH_STOP_MASK;
+
+    if (!fifo8_is_empty(&s->input_fifo) &&
+        (!stop || ot_hmac_get_curlen(s) != 0)) {
+        while (!fifo8_is_empty(&s->input_fifo) &&
+               (!stop || ot_hmac_get_curlen(s) != 0)) {
+            uint8_t value = fifo8_pop(&s->input_fifo);
+            ot_hmac_sha_process(s, &value, 1u, false);
+        }
+
+        /* write back updated digest state */
+        if (fifo8_is_empty(&s->input_fifo) || stop) {
+            ot_hmac_writeback_digest_state(s);
+        }
+
+        /* assert FIFO Empty IRQ */
+        if (fifo8_is_empty(&s->input_fifo)) {
+            s->regs->intr_state |= INTR_FIFO_EMPTY_MASK;
+        }
+    }
+
+    if (stop && ot_hmac_get_curlen(s) == 0) {
+        s->regs->intr_state |= INTR_HMAC_DONE_MASK;
+        s->regs->cmd = 0;
+    }
+
+    if (s->regs->cmd & R_CMD_HASH_PROCESS_MASK) {
+        ot_hmac_compute_digest(s);
+        s->regs->intr_state |= INTR_HMAC_DONE_MASK;
+        s->regs->cmd = 0;
+    }
+
+    ot_hmac_update_irqs(s);
+
+    ibex_irq_set(&s->clock_active,
+                 !fifo8_is_empty(&s->input_fifo) || (bool)s->regs->cmd);
+}
+
+static inline void ot_hmac_wipe_buffer(OtHMACState *s, uint32_t *buffer,
+                                       size_t size)
+{
+    for (unsigned index = 0; index < size; index++) {
+        buffer[index] = s->regs->wipe_secret;
+    }
+}
+
+static void ot_hmac_clock_input(void *opaque, int irq, int level)
+{
+    OtHMACState *s = opaque;
+
+    g_assert(irq == 0);
+
+    s->pclk = (unsigned)level;
+
+    /* TODO: disable HMAC execution when PCLK is 0 */
+}
+
+static uint64_t ot_hmac_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtHMACState *s = OT_HMAC(opaque);
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 = s->regs->intr_state;
+        break;
+    case R_INTR_ENABLE:
+        val32 = s->regs->intr_enable;
+        break;
+    case R_CFG:
+        val32 = s->regs->cfg;
+        break;
+    case R_CMD:
+        val32 = 0;
+        /* always read 0: CMD is r0w1c */
+        break;
+    case R_STATUS: {
+        uint32_t num_used = fifo8_num_used(&s->input_fifo);
+        if (num_used == 0) {
+            val32 = R_STATUS_FIFO_EMPTY_MASK;
+        } else {
+            val32 = ((num_used / 4u) << R_STATUS_FIFO_DEPTH_SHIFT) &
+                    R_STATUS_FIFO_DEPTH_MASK;
+            if (num_used == OT_HMAC_FIFO_LENGTH) {
+                val32 |= R_STATUS_FIFO_FULL_MASK;
+            }
+        }
+        if (!(s->regs->cmd)) {
+            val32 |= R_STATUS_HMAC_IDLE_MASK;
+        }
+    } break;
+    case R_ERR_CODE:
+        val32 = s->regs->err_code;
+        break;
+    case R_DIGEST_0:
+    case R_DIGEST_1:
+    case R_DIGEST_2:
+    case R_DIGEST_3:
+    case R_DIGEST_4:
+    case R_DIGEST_5:
+    case R_DIGEST_6:
+    case R_DIGEST_7:
+    case R_DIGEST_8:
+    case R_DIGEST_9:
+    case R_DIGEST_10:
+    case R_DIGEST_11:
+    case R_DIGEST_12:
+    case R_DIGEST_13:
+    case R_DIGEST_14:
+    case R_DIGEST_15:
+        /* make sure we've processed any input blocks before reading */
+        if (!fifo8_is_empty(&s->input_fifo) && ot_hmac_get_curlen(s) != 0) {
+            ot_hmac_process_fifo(s);
+        }
+        /*
+         * We use a SHA library that computes in native (little) endian-ness,
+         * but produces a big-endian digest upon termination. To ensure
+         * consistency between digests that are read/written, we make sure the
+         * value internally in s->regs is always big endian, to match the final
+         * digest. So, we only need to swap if the swap config is 0 (i.e. the
+         * digest should be output in little endian).
+         */
+        if (s->regs->cfg & R_CFG_DIGEST_SWAP_MASK) {
+            val32 = s->regs->digest[reg - R_DIGEST_0];
+        } else {
+            val32 = bswap32(s->regs->digest[reg - R_DIGEST_0]);
+        }
+        break;
+    case R_MSG_LENGTH_LOWER:
+        val32 = s->regs->msg_length;
+        break;
+    case R_MSG_LENGTH_UPPER:
+        val32 = s->regs->msg_length >> 32u;
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+    case R_WIPE_SECRET:
+    case R_KEY_0:
+    case R_KEY_1:
+    case R_KEY_2:
+    case R_KEY_3:
+    case R_KEY_4:
+    case R_KEY_5:
+    case R_KEY_6:
+    case R_KEY_7:
+    case R_KEY_8:
+    case R_KEY_9:
+    case R_KEY_10:
+    case R_KEY_11:
+    case R_KEY_12:
+    case R_KEY_13:
+    case R_KEY_14:
+    case R_KEY_15:
+    case R_KEY_16:
+    case R_KEY_17:
+    case R_KEY_18:
+    case R_KEY_19:
+    case R_KEY_20:
+    case R_KEY_21:
+    case R_KEY_22:
+    case R_KEY_23:
+    case R_KEY_24:
+    case R_KEY_25:
+    case R_KEY_26:
+    case R_KEY_27:
+    case R_KEY_28:
+    case R_KEY_29:
+    case R_KEY_30:
+    case R_KEY_31:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_hmac_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                              pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_hmac_regs_write(void *opaque, hwaddr addr, uint64_t value,
+                               unsigned size)
+{
+    OtHMACState *s = OT_HMAC(opaque);
+    (void)size;
+    uint32_t val32 = (uint32_t)value;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_hmac_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    OtHMACDigestSize digest_size;
+    OtHMACKeyLength key_length;
+
+    switch (reg) {
+    case R_INTR_STATE:
+        s->regs->intr_state &= ~(val32 & INTR_MASK);
+        ot_hmac_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        s->regs->intr_enable = val32 & INTR_MASK;
+        ot_hmac_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        s->regs->intr_state |= val32 & INTR_MASK;
+        ot_hmac_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        s->regs->alert_test |= val32 & R_ALERT_TEST_FATAL_FAULT_MASK;
+        ot_hmac_update_alert(s);
+        break;
+    case R_CFG:
+        /* ignore write if engine is not idle */
+        if (s->regs->cmd) {
+            break;
+        }
+
+        val32 &=
+            (R_CFG_HMAC_EN_MASK | R_CFG_SHA_EN_MASK | R_CFG_ENDIAN_SWAP_MASK |
+             R_CFG_DIGEST_SWAP_MASK | R_CFG_KEY_SWAP_MASK |
+             R_CFG_DIGEST_SIZE_MASK | R_CFG_KEY_LENGTH_MASK);
+
+        /* If the digest size is invalid, it gets mapped to SHA2_NONE. */
+        digest_size = ot_hmac_get_digest_size(val32);
+        if (digest_size == HMAC_SHA2_NONE) {
+            val32 &= ~R_CFG_DIGEST_SIZE_MASK;
+            val32 |= OT_HMAC_CFG_DIGEST_SHA2_NONE << R_CFG_DIGEST_SIZE_SHIFT;
+        }
+
+        /* If the key length is invalid, it gets mapped to KEY_NONE. */
+        key_length = ot_hmac_get_key_length(val32);
+        if (key_length == HMAC_KEY_NONE) {
+            val32 &= ~R_CFG_KEY_LENGTH_MASK;
+            val32 |= OT_HMAC_CFG_KEY_LENGTH_NONE << R_CFG_KEY_LENGTH_SHIFT;
+        }
+
+        s->regs->cfg = val32;
+
+        /* clear digest when SHA is disabled */
+        if (!(s->regs->cfg & R_CFG_SHA_EN_MASK)) {
+            ot_hmac_wipe_buffer(s, s->regs->digest,
+                                ARRAY_SIZE(s->regs->digest));
+        }
+        break;
+    case R_CMD:
+        if (val32 & (R_CMD_HASH_START_MASK | R_CMD_HASH_CONTINUE_MASK)) {
+            digest_size = ot_hmac_get_digest_size(s->regs->cfg);
+            if (digest_size == HMAC_SHA2_NONE) {
+                ot_hmac_report_error(s, R_ERR_CODE_INVALID_CONFIG);
+                break;
+            }
+
+            if (s->regs->cfg & R_CFG_HMAC_EN_MASK) {
+                key_length = ot_hmac_get_key_length(s->regs->cfg);
+                if (key_length == HMAC_KEY_NONE ||
+                    !ot_hmac_key_length_supported(digest_size, key_length)) {
+                    ot_hmac_report_error(s, R_ERR_CODE_INVALID_CONFIG);
+                    break;
+                }
+            }
+        }
+
+        if (val32 & R_CMD_HASH_START_MASK) {
+            if (!(s->regs->cfg & R_CFG_SHA_EN_MASK)) {
+                ot_hmac_report_error(s,
+                                     R_ERR_CODE_HASH_START_WHEN_SHA_DISABLED);
+                break;
+            }
+            if (s->regs->cmd) {
+                ot_hmac_report_error(s, R_ERR_CODE_HASH_START_WHEN_ACTIVE);
+                break;
+            }
+            s->regs->cmd = R_CMD_HASH_START_MASK;
+            s->regs->msg_length = 0;
+
+            ibex_irq_set(&s->clock_active, true);
+
+            /*
+             * Hold the previous digest size until the HMAC is started with the
+             * new digest size configured
+             */
+            s->ctx->digest_size_started = ot_hmac_get_digest_size(s->regs->cfg);
+
+            ot_hmac_sha_init(s, true);
+
+            /* HMAC mode, process input padding */
+            if (s->regs->cfg & R_CFG_HMAC_EN_MASK) {
+                size_t key_length_b = ot_hmac_get_key_bytes(s);
+                size_t block_size_b = ot_hmac_get_block_size_bytes(s);
+                /* pad key to right with 0s if smaller than the block size. */
+                size_t pad_length_b = MAX(key_length_b, block_size_b);
+                size_t pad_length_w = pad_length_b / sizeof(uint64_t);
+                uint64_t ipad[OT_HMAC_MAX_KEY_LENGTH / sizeof(uint64_t)];
+                memset(ipad, 0, sizeof(ipad));
+                memcpy(ipad, s->regs->key, key_length_b);
+                for (size_t idx = 0; idx < pad_length_w; idx++) {
+                    ipad[idx] ^= 0x3636363636363636ull;
+                }
+                ot_hmac_sha_process(s, (const uint8_t *)ipad, pad_length_b,
+                                    true);
+            }
+        }
+
+        if (val32 & R_CMD_HASH_PROCESS_MASK) {
+            if (!(s->regs->cmd &
+                  (R_CMD_HASH_START_MASK | R_CMD_HASH_CONTINUE_MASK))) {
+                qemu_log_mask(
+                    LOG_GUEST_ERROR,
+                    "%s: CMD.PROCESS requested but hash not started yet\n",
+                    __func__);
+                break;
+            }
+            if (s->regs->cmd & R_CMD_HASH_PROCESS_MASK) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: CMD.PROCESS requested but hash is currently "
+                              "processing\n",
+                              __func__);
+                break;
+            }
+            s->regs->cmd |= R_CMD_HASH_PROCESS_MASK;
+
+            /* trigger delayed processing of FIFO */
+            ibex_irq_set(&s->clock_active, true);
+            ot_hmac_process_fifo(s);
+        }
+
+        if (val32 & R_CMD_HASH_STOP_MASK) {
+            s->regs->cmd = R_CMD_HASH_STOP_MASK;
+
+            /*
+             * trigger delayed processing of FIFO until the next block is
+             * processed.
+             */
+            ibex_irq_set(&s->clock_active, true);
+            ot_hmac_process_fifo(s);
+        }
+
+        if (val32 & R_CMD_HASH_CONTINUE_MASK) {
+            if (!(s->regs->cfg & R_CFG_SHA_EN_MASK)) {
+                ot_hmac_report_error(s,
+                                     R_ERR_CODE_HASH_START_WHEN_SHA_DISABLED);
+                break;
+            }
+            if (s->regs->cmd) {
+                ot_hmac_report_error(s, R_ERR_CODE_HASH_START_WHEN_ACTIVE);
+                break;
+            }
+
+            s->regs->cmd = R_CMD_HASH_CONTINUE_MASK;
+
+            /*
+             * Hold the previous digest size until the HMAC is started with the
+             * new digest size configured
+             */
+            s->ctx->digest_size_started = ot_hmac_get_digest_size(s->regs->cfg);
+
+            ot_hmac_restore_context(s);
+
+            /* trigger delayed processing of FIFO */
+            ibex_irq_set(&s->clock_active, true);
+            ot_hmac_process_fifo(s);
+        }
+
+        break;
+    case R_WIPE_SECRET:
+        s->regs->wipe_secret = val32;
+        ot_hmac_wipe_buffer(s, s->regs->key, ARRAY_SIZE(s->regs->key));
+        ot_hmac_wipe_buffer(s, s->regs->digest, ARRAY_SIZE(s->regs->digest));
+        break;
+    case R_KEY_0:
+    case R_KEY_1:
+    case R_KEY_2:
+    case R_KEY_3:
+    case R_KEY_4:
+    case R_KEY_5:
+    case R_KEY_6:
+    case R_KEY_7:
+    case R_KEY_8:
+    case R_KEY_9:
+    case R_KEY_10:
+    case R_KEY_11:
+    case R_KEY_12:
+    case R_KEY_13:
+    case R_KEY_14:
+    case R_KEY_15:
+    case R_KEY_16:
+    case R_KEY_17:
+    case R_KEY_18:
+    case R_KEY_19:
+    case R_KEY_20:
+    case R_KEY_21:
+    case R_KEY_22:
+    case R_KEY_23:
+    case R_KEY_24:
+    case R_KEY_25:
+    case R_KEY_26:
+    case R_KEY_27:
+    case R_KEY_28:
+    case R_KEY_29:
+    case R_KEY_30:
+    case R_KEY_31:
+        /* ignore write and report error if engine is not idle */
+        if (s->regs->cmd) {
+            ot_hmac_report_error(s, R_ERR_CODE_UPDATE_SECRET_KEY_INPROCESS);
+            break;
+        }
+
+        /*
+         * We use a SHA library that operates in native (little) endian-ness,
+         * so we only need to swap if the swap config is 0 (i.e. the input key
+         * is big endian), to ensure the value in s->regs is little endian.
+         */
+        if (s->regs->cfg & R_CFG_KEY_SWAP_MASK) {
+            s->regs->key[reg - R_KEY_0] = val32;
+        } else {
+            s->regs->key[reg - R_KEY_0] = bswap32(val32);
+        }
+        break;
+    case R_STATUS:
+    case R_ERR_CODE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_DIGEST_0:
+    case R_DIGEST_1:
+    case R_DIGEST_2:
+    case R_DIGEST_3:
+    case R_DIGEST_4:
+    case R_DIGEST_5:
+    case R_DIGEST_6:
+    case R_DIGEST_7:
+    case R_DIGEST_8:
+    case R_DIGEST_9:
+    case R_DIGEST_10:
+    case R_DIGEST_11:
+    case R_DIGEST_12:
+    case R_DIGEST_13:
+    case R_DIGEST_14:
+    case R_DIGEST_15:
+        /* ignore write and report error if engine is not idle */
+        if (s->regs->cmd) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Cannot W register 0x%02x (%s) whilst non-idle\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
+            break;
+        } else if (s->regs->cfg & R_CFG_SHA_EN_MASK) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Cannot W register 0x%02x (%s) whilst SHA Engine "
+                          "is enabled\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
+        }
+
+        /*
+         * We use a SHA library that computes in native (little) endian-ness,
+         * but produces a big-endian digest upon termination. To ensure
+         * consistency between digests that are read/written, we make sure the
+         * value internally in s->regs is always big endian, to match the final
+         * digest. So, we only need to swap if the swap config is 0 (i.e. the
+         * input digest is little endian).
+         */
+        if (s->regs->cfg & R_CFG_DIGEST_SWAP_MASK) {
+            s->regs->digest[reg - R_DIGEST_0] = val32;
+        } else {
+            s->regs->digest[reg - R_DIGEST_0] = bswap32(val32);
+        }
+        break;
+    case R_MSG_LENGTH_LOWER:
+        /* ignore write and report error if engine is not idle */
+        if (s->regs->cmd) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Cannot W register 0x%02x (%s) whilst non-idle\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
+            break;
+        } else if (s->regs->cfg & R_CFG_SHA_EN_MASK) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Cannot W register 0x%02x (%s) whilst SHA Engine "
+                          "is enabled\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
+        }
+        s->regs->msg_length =
+            (s->regs->msg_length & (0xFFFFFFFFull << 32u)) | val32;
+        break;
+    case R_MSG_LENGTH_UPPER:
+        /* ignore write and report error if engine is not idle */
+        if (s->regs->cmd) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Cannot W register 0x%02x (%s) whilst non-idle\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
+            break;
+        } else if (s->regs->cfg & R_CFG_SHA_EN_MASK) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Cannot W register 0x%02x (%s) whilst SHA Engine "
+                          "is enabled\n",
+                          __func__, (uint32_t)addr, REG_NAME(reg));
+        }
+        s->regs->msg_length =
+            ((uint64_t)val32 << 32u) | (s->regs->msg_length & 0xFFFFFFFFull);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+}
+
+static uint64_t ot_hmac_fifo_read(void *opaque, hwaddr addr, unsigned size)
+{
+    (void)opaque;
+    (void)addr;
+    (void)size;
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: MSG_FIFO is write only\n", __func__);
+
+    return 0;
+}
+
+static void ot_hmac_fifo_write(void *opaque, hwaddr addr, uint64_t value,
+                               unsigned size)
+{
+    OtHMACState *s = OT_HMAC(opaque);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_hmac_fifo_write(s->ot_id, (uint32_t)addr, (uint32_t)value, size,
+                             pc);
+
+    if (!s->regs->cmd) {
+        ot_hmac_report_error(s, R_ERR_CODE_PUSH_MSG_WHEN_DISALLOWED);
+        return;
+    }
+
+    if (!(s->regs->cfg & R_CFG_SHA_EN_MASK)) {
+        ot_hmac_report_error(s, R_ERR_CODE_PUSH_MSG_WHEN_SHA_DISABLED);
+        return;
+    }
+
+    if (s->regs->cfg & R_CFG_ENDIAN_SWAP_MASK) {
+        if (size == 4u) {
+            value = bswap32((uint32_t)value);
+        } else if (size == 2u) {
+            value = bswap16((uint16_t)value);
+        }
+    }
+
+    ibex_irq_set(&s->clock_active, true);
+
+    for (unsigned i = 0; i < size; i++) {
+        uint8_t b = value;
+        g_assert(!fifo8_is_full(&s->input_fifo));
+        fifo8_push(&s->input_fifo, b);
+        value >>= 8u;
+    }
+
+    s->regs->msg_length += (uint64_t)size * 8u;
+
+    /*
+     * Note: real HW may stall the bus till some room is available in the input
+     * FIFO. In QEMU, we do not want to stall the I/O thread to emulate this
+     * feature. The workaround is to let the FIFO fill up with an arbitrary
+     * length, always smaller than the FIFO capacity, here half the size of the
+     * FIFO then process the whole FIFO content in one step. This let the FIFO
+     * depth register to update on each call as the real HW. However the FIFO
+     * can never be full, which is not supposed to occur on the real HW anyway
+     * since the HMAC is reportedly faster than the Ibex capability to fill in
+     * the FIFO. Could be different with DMA access though.
+     */
+    if (fifo8_num_used(&s->input_fifo) >= OT_HMAC_FIFO_LENGTH / 2u) {
+        ot_hmac_process_fifo(s);
+    }
+}
+
+static const Property ot_hmac_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtHMACState, ot_id),
+    DEFINE_PROP_STRING("clock-name", OtHMACState, clock_name),
+    DEFINE_PROP_LINK("clock-src", OtHMACState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+};
+
+static const MemoryRegionOps ot_hmac_regs_ops = {
+    .read = &ot_hmac_regs_read,
+    .write = &ot_hmac_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 4u,
+        .max_access_size = 4u,
+    },
+};
+
+static const MemoryRegionOps ot_hmac_fifo_ops = {
+    .read = &ot_hmac_fifo_read,
+    .write = &ot_hmac_fifo_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 1u,
+        .max_access_size = 4u,
+    },
+};
+
+static void ot_hmac_reset_enter(Object *obj, ResetType type)
+{
+    OtHMACClass *c = OT_HMAC_GET_CLASS(obj);
+    OtHMACState *s = OT_HMAC(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    ibex_irq_set(&s->clock_active, false);
+
+    memset(s->ctx, 0, sizeof(*(s->ctx)));
+    memset(s->regs, 0, sizeof(*(s->regs)));
+
+    ot_hmac_update_irqs(s);
+    ot_hmac_update_alert(s);
+
+    fifo8_reset(&s->input_fifo);
+
+    if (!s->clock_src_name) {
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_name =
+            ic->get_clock_source(ii, s->clock_name, DEVICE(s), &error_fatal);
+        qemu_irq in_irq =
+            qdev_get_gpio_in_named(DEVICE(s), OT_HMAC_CLOCK_INPUT, 0);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_name, 0, in_irq);
+
+        if (object_dynamic_cast(OBJECT(s->clock_src), TYPE_OT_CLKMGR)) {
+            char *hint_name =
+                g_strdup_printf(OT_CLOCK_HINT_PREFIX "%s", s->clock_name);
+            qemu_irq hint_irq =
+                qdev_get_gpio_in_named(s->clock_src, hint_name, 0);
+            g_assert(hint_irq);
+            qdev_connect_gpio_out_named(DEVICE(s), OT_HMAC_CLOCK_ACTIVE, 0,
+                                        hint_irq);
+            g_free(hint_name);
+        }
+    }
+}
+
+static void ot_hmac_reset_exit(Object *obj, ResetType type)
+{
+    OtHMACClass *c = OT_HMAC_GET_CLASS(obj);
+    OtHMACState *s = OT_HMAC(obj);
+    OtHMACRegisters *r = s->regs;
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    r->cfg = 0x4100u;
+}
+
+static void ot_hmac_realize(DeviceState *dev, Error **errp)
+{
+    (void)errp;
+
+    OtHMACState *s = OT_HMAC(dev);
+
+    g_assert(s->ot_id);
+    g_assert(s->clock_name);
+    g_assert(s->clock_src);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_hmac_clock_input,
+                            OT_HMAC_CLOCK_INPUT, 1);
+}
+
+static void ot_hmac_init(Object *obj)
+{
+    OtHMACState *s = OT_HMAC(obj);
+
+    s->regs = g_new0(OtHMACRegisters, 1u);
+    s->ctx = g_new(OtHMACContext, 1u);
+
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+    ibex_qdev_init_irq(obj, &s->clock_active, OT_HMAC_CLOCK_ACTIVE);
+
+    memory_region_init(&s->mmio, OBJECT(s), TYPE_OT_HMAC, OT_HMAC_WHOLE_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    memory_region_init_io(&s->regs_mmio, obj, &ot_hmac_regs_ops, s,
+                          TYPE_OT_HMAC ".regs", REGS_SIZE);
+    memory_region_add_subregion(&s->mmio, OT_HMAC_REGS_BASE, &s->regs_mmio);
+
+    memory_region_init_io(&s->fifo_mmio, obj, &ot_hmac_fifo_ops, s,
+                          TYPE_OT_HMAC ".fifo", OT_HMAC_FIFO_SIZE);
+    memory_region_add_subregion(&s->mmio, OT_HMAC_FIFO_BASE, &s->fifo_mmio);
+
+    /* FIFO sizes as per OT Spec */
+    fifo8_create(&s->input_fifo, OT_HMAC_FIFO_LENGTH);
+}
+
+static void ot_hmac_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_hmac_realize;
+    device_class_set_props(dc, ot_hmac_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtHMACClass *hc = OT_HMAC_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_hmac_reset_enter, NULL,
+                                       &ot_hmac_reset_exit, &hc->parent_phases);
+}
+
+static const TypeInfo ot_hmac_info = {
+    .name = TYPE_OT_HMAC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtHMACState),
+    .instance_init = &ot_hmac_init,
+    .class_size = sizeof(OtHMACClass),
+    .class_init = &ot_hmac_class_init,
+};
+
+static void ot_hmac_register_types(void)
+{
+    type_register_static(&ot_hmac_info);
+}
+
+type_init(ot_hmac_register_types);
diff --git a/hw/opentitan/ot_i2c.c b/hw/opentitan/ot_i2c.c
new file mode 100644
index 0000000000000..36dd02b36c5f7
--- /dev/null
+++ b/hw/opentitan/ot_i2c.c
@@ -0,0 +1,1438 @@
+/*
+ * QEMU OpenTitan I2C device
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Duncan Laurie <duncan@rivosinc.com>
+ *  Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/*
+ * The OpenTitan I2C Controller supports both host and target mode.
+ *
+ * The datasheet indicates that this controller should be able to support host
+ * and target mode enabled at the same time but notes it may not be validated
+ * in hardware.  The register, FIFO, and interrupt interfaces are separate so
+ * enabling host and target mode at the same time is supported in QEMU.
+ */
+
+/*
+ * Features not handled:
+ * - This controller does not support 10 bit addressing.
+ * - Anything that requires raw SCL/SDA:
+ *      bus recover/override
+ *      some interrupts will never be generated (except via INTR_TEST)
+ *      bus timing registers are ignored
+ * - Target mode only supports TARGET_ID.ADDRESS0 and TARGET_ID.MASK0
+ * - Loopback mode.  Need more details about how it works in HW.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/fifo8.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "qapi/error.h"
+#include "hw/i2c/i2c.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_fifo32.h"
+#include "hw/opentitan/ot_i2c.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+typedef enum {
+    FMT_THRESHOLD,
+    RX_THRESHOLD,
+    ACQ_THRESHOLD,
+    RX_OVERFLOW,
+    CONTROLLER_HALT,
+    SCL_INTERFERENCE,
+    SDA_INTERFERENCE,
+    STRETCH_TIMEOUT,
+    SDA_UNSTABLE,
+    CMD_COMPLETE,
+    TX_STRETCH,
+    TX_THRESHOLD,
+    ACQ_STRETCH,
+    UNEXP_STOP,
+    HOST_TIMEOUT,
+    OT_I2C_IRQ_NUM
+} OtI2CInterrupt;
+
+/* clang-format off */
+REG32(INTR_STATE, 0x00u)
+    SHARED_FIELD(INTR_FMT_THRESHOLD, FMT_THRESHOLD, 1u)
+    SHARED_FIELD(INTR_RX_THRESHOLD, RX_THRESHOLD, 1u)
+    SHARED_FIELD(INTR_ACQ_THRESHOLD, ACQ_THRESHOLD, 1u)
+    SHARED_FIELD(INTR_RX_OVERFLOW, RX_OVERFLOW, 1u)
+    SHARED_FIELD(INTR_CONTROLLER_HALT, CONTROLLER_HALT, 1u)
+    SHARED_FIELD(INTR_SCL_INTERFERENCE, SCL_INTERFERENCE, 1u)
+    SHARED_FIELD(INTR_SDA_INTERFERENCE, SDA_INTERFERENCE, 1u)
+    SHARED_FIELD(INTR_STRETCH_TIMEOUT, STRETCH_TIMEOUT, 1u)
+    SHARED_FIELD(INTR_SDA_UNSTABLE, SDA_UNSTABLE, 1u)
+    SHARED_FIELD(INTR_CMD_COMPLETE, CMD_COMPLETE, 1u)
+    SHARED_FIELD(INTR_TX_STRETCH, TX_STRETCH, 1u)
+    SHARED_FIELD(INTR_TX_THRESHOLD, TX_THRESHOLD, 1u)
+    SHARED_FIELD(INTR_ACQ_STRETCH, ACQ_STRETCH, 1u)
+    SHARED_FIELD(INTR_UNEXP_STOP, UNEXP_STOP, 1u)
+    SHARED_FIELD(INTR_HOST_TIMEOUT, HOST_TIMEOUT, 1u)
+REG32(INTR_ENABLE, 0x04u)
+REG32(INTR_TEST, 0x08u)
+REG32(ALERT_TEST, 0x0cu)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(CTRL, 0x10u)
+    FIELD(CTRL, ENABLEHOST, 0u, 1u)
+    FIELD(CTRL, ENABLETARGET, 1u, 1u)
+    FIELD(CTRL, LLPBK, 2u, 1u)
+    FIELD(CTRL, NACK_ADDR_AFTER_TIMEOUT, 3u, 1u)
+    FIELD(CTRL, ACK_CTRL_EN, 4u, 1u)
+    FIELD(CTRL, MULTI_CONTROLLER_MONITOR_EN, 5u, 1u)
+    FIELD(CTRL, TX_STRETCH_CTRL_EN, 6u, 1u)
+REG32(STATUS, 0x14u)
+    FIELD(STATUS, FMTFULL, 0u, 1u)
+    FIELD(STATUS, RXFULL, 1u, 1u)
+    FIELD(STATUS, FMTEMPTY, 2u, 1u)
+    FIELD(STATUS, HOSTIDLE, 3u, 1u)
+    FIELD(STATUS, TARGETIDLE, 4u, 1u)
+    FIELD(STATUS, RXEMPTY, 5u, 1u)
+    FIELD(STATUS, TXFULL, 6u, 1u)
+    FIELD(STATUS, ACQFULL, 7u, 1u)
+    FIELD(STATUS, TXEMPTY, 8u, 1u)
+    FIELD(STATUS, ACQEMPTY, 9u, 1u)
+    FIELD(STATUS, ACK_CTRL_STRETCH, 10u, 1u)
+REG32(RDATA, 0x18u)
+    FIELD(RDATA, RDATA, 0u, 8u)
+REG32(FDATA, 0x1cu)
+    FIELD(FDATA, FBYTE, 0u, 8u)
+    FIELD(FDATA, START, 8u, 1u)
+    FIELD(FDATA, STOP, 9u, 1u)
+    FIELD(FDATA, READB, 10u, 1u)
+    FIELD(FDATA, RCONT, 11u, 1u)
+    FIELD(FDATA, NAKOK, 12u, 1u)
+REG32(FIFO_CTRL, 0x20u)
+    FIELD(FIFO_CTRL, RXRST, 0u, 1u)
+    FIELD(FIFO_CTRL, FMTRST, 1u, 1u)
+    FIELD(FIFO_CTRL, ACQRST, 7u, 1u)
+    FIELD(FIFO_CTRL, TXRST, 8u, 1u)
+REG32(HOST_FIFO_CONFIG, 0x24u)
+    FIELD(HOST_FIFO_CONFIG, RX_THRESH, 0u, 12u)
+    FIELD(HOST_FIFO_CONFIG, FMT_THRESH, 16u, 12u)
+REG32(TARGET_FIFO_CONFIG, 0x28u)
+    FIELD(TARGET_FIFO_CONFIG, TX_THRESH, 0u, 12u)
+    FIELD(TARGET_FIFO_CONFIG, ACQ_THRESH, 16u, 12u)
+REG32(HOST_FIFO_STATUS, 0x2cu)
+    FIELD(HOST_FIFO_STATUS, FMTLVL, 0u, 12u)
+    FIELD(HOST_FIFO_STATUS, RXLVL, 16u, 12u)
+REG32(TARGET_FIFO_STATUS, 0x30u)
+    FIELD(TARGET_FIFO_STATUS, TXLVL, 0u, 12u)
+    FIELD(TARGET_FIFO_STATUS, ACQLVL, 16u, 12u)
+REG32(OVRD, 0x34u)
+    FIELD(OVRD, TXOVRDEN, 0u, 1u)
+    FIELD(OVRD, SCLVAL, 1u, 1u)
+    FIELD(OVRD, SDAVAL, 2u, 1u)
+REG32(VAL, 0x38u)
+    FIELD(VAL, SCL_RX, 0u, 16u)
+    FIELD(VAL, SDA_RX, 16u, 16u)
+REG32(TIMING0, 0x3cu)
+    FIELD(TIMING0, THIGH, 0u, 13u)
+    FIELD(TIMING0, TLOW, 16u, 13u)
+REG32(TIMING1, 0x40u)
+    FIELD(TIMING1, T_R, 0u, 10u)
+    FIELD(TIMING1, T_F, 16u, 9u)
+REG32(TIMING2, 0x44u)
+    FIELD(TIMING2, TSU_STA, 0u, 13u)
+    FIELD(TIMING2, THD_STA, 16u, 13u)
+REG32(TIMING3, 0x48u)
+    FIELD(TIMING3, TSU_DAT, 0u, 9u)
+    FIELD(TIMING3, THD_DAT, 16u, 13u)
+REG32(TIMING4, 0x4cu)
+    FIELD(TIMING4, TSU_STO, 0u, 13u)
+    FIELD(TIMING4, T_BUF, 16u, 13u)
+REG32(TIMEOUT_CTRL, 0x50u)
+    FIELD(TIMEOUT_CTRL, VAL, 0u, 30u)
+    FIELD(TIMEOUT_CTRL, MODE, 30u, 1u)
+    FIELD(TIMEOUT_CTRL, EN, 31u, 1u)
+REG32(TARGET_ID, 0x54u)
+    FIELD(TARGET_ID, ADDRESS0, 0u, 7u)
+    FIELD(TARGET_ID, MASK0, 7u, 7u)
+    FIELD(TARGET_ID, ADDRESS1, 14u, 7u)
+    FIELD(TARGET_ID, MASK1, 21u, 7u)
+REG32(ACQDATA, 0x58u)
+    FIELD(ACQDATA, ABYTE, 0u, 8u)
+    FIELD(ACQDATA, SIGNAL, 8u, 3u)
+REG32(TXDATA, 0x5cu)
+    FIELD(TXDATA, TXDATA, 0u, 8u)
+REG32(HOST_TIMEOUT_CTRL, 0x60u)
+    FIELD(HOST_TIMEOUT_CTRL, HOST_TIMEOUT_CTRL, 0u, 20u)
+REG32(TARGET_TIMEOUT_CTRL, 0x64u)
+    FIELD(TARGET_TIMEOUT_CTRL, VAL, 0u, 31u)
+    FIELD(TARGET_TIMEOUT_CTRL, EN, 31u, 1u)
+REG32(TARGET_NACK_COUNT, 0x68u)
+    FIELD(TARGET_NACK_COUNT, TARGET_NACK_COUNT, 0u, 8u)
+REG32(TARGET_ACK_CTRL, 0x6cu)
+    FIELD(TARGET_ACK_CTRL, NBYTES, 0u, 9u)
+    FIELD(TARGET_ACK_CTRL, NACK, 31u, 1u)
+REG32(ACQ_FIFO_NEXT_DATA, 0x70u)
+    FIELD(ACQ_FIFO_NEXT_DATA, ACQ_FIFO_NEXT_DATA, 0u, 8u)
+REG32(HOST_NACK_HANDLER_TIMEOUT, 0x74u)
+    FIELD(HOST_NACK_HANDLER_TIMEOUT, VAL, 0u, 31u)
+    FIELD(HOST_NACK_HANDLER_TIMEOUT, EN, 31u, 1u)
+REG32(CONTROLLER_EVENTS, 0x78u)
+    FIELD(CONTROLLER_EVENTS, NACK, 0u, 1u)
+    FIELD(CONTROLLER_EVENTS, UNHANDLED_NACK_TIMEOUT, 1u, 1u)
+    FIELD(CONTROLLER_EVENTS, BUS_TIMEOUT, 2u, 1u)
+    FIELD(CONTROLLER_EVENTS, ARBITRATION_LOST, 3u, 1u)
+REG32(TARGET_EVENTS, 0x7cu)
+    FIELD(TARGET_EVENTS, TX_PENDING, 0u, 1u)
+    FIELD(TARGET_EVENTS, BUS_TIMEOUT, 1u, 1u)
+    FIELD(TARGET_EVENTS, ARBITRATION_LOST, 2u, 1u)
+/* clang-format on */
+
+#define INTR_RW1C_MASK \
+    (INTR_RX_OVERFLOW_MASK | INTR_SCL_INTERFERENCE_MASK | \
+     INTR_SDA_INTERFERENCE_MASK | INTR_STRETCH_TIMEOUT_MASK | \
+     INTR_SDA_UNSTABLE_MASK | INTR_CMD_COMPLETE_MASK | INTR_UNEXP_STOP_MASK | \
+     INTR_HOST_TIMEOUT_MASK)
+
+#define INTR_MASK \
+    (INTR_RW1C_MASK | INTR_FMT_THRESHOLD_MASK | INTR_RX_THRESHOLD_MASK | \
+     INTR_ACQ_THRESHOLD_MASK | INTR_CONTROLLER_HALT_MASK | \
+     INTR_TX_STRETCH_MASK | INTR_TX_THRESHOLD_MASK | INTR_ACQ_STRETCH_MASK)
+
+#define CONTROLLER_EVENTS_RW1C_MASK \
+    (R_CONTROLLER_EVENTS_NACK_MASK | \
+     R_CONTROLLER_EVENTS_UNHANDLED_NACK_TIMEOUT_MASK | \
+     R_CONTROLLER_EVENTS_BUS_TIMEOUT_MASK | \
+     R_CONTROLLER_EVENTS_ARBITRATION_LOST_MASK)
+
+#define TARGET_EVENTS_RW1C_MASK \
+    (R_TARGET_EVENTS_TX_PENDING_MASK | R_TARGET_EVENTS_BUS_TIMEOUT_MASK | \
+     R_TARGET_EVENTS_ARBITRATION_LOST_MASK)
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_TARGET_EVENTS)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CTRL),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(RDATA),
+    REG_NAME_ENTRY(FDATA),
+    REG_NAME_ENTRY(FIFO_CTRL),
+    REG_NAME_ENTRY(HOST_FIFO_CONFIG),
+    REG_NAME_ENTRY(TARGET_FIFO_CONFIG),
+    REG_NAME_ENTRY(HOST_FIFO_STATUS),
+    REG_NAME_ENTRY(TARGET_FIFO_STATUS),
+    REG_NAME_ENTRY(OVRD),
+    REG_NAME_ENTRY(VAL),
+    REG_NAME_ENTRY(TIMING0),
+    REG_NAME_ENTRY(TIMING1),
+    REG_NAME_ENTRY(TIMING2),
+    REG_NAME_ENTRY(TIMING3),
+    REG_NAME_ENTRY(TIMING4),
+    REG_NAME_ENTRY(TIMEOUT_CTRL),
+    REG_NAME_ENTRY(TARGET_ID),
+    REG_NAME_ENTRY(ACQDATA),
+    REG_NAME_ENTRY(TXDATA),
+    REG_NAME_ENTRY(HOST_TIMEOUT_CTRL),
+    REG_NAME_ENTRY(TARGET_TIMEOUT_CTRL),
+    REG_NAME_ENTRY(TARGET_NACK_COUNT),
+    REG_NAME_ENTRY(TARGET_ACK_CTRL),
+    REG_NAME_ENTRY(ACQ_FIFO_NEXT_DATA),
+    REG_NAME_ENTRY(HOST_NACK_HANDLER_TIMEOUT),
+    REG_NAME_ENTRY(CONTROLLER_EVENTS),
+    REG_NAME_ENTRY(TARGET_EVENTS),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+#define IRQ_NAME_ENTRY(_irq_) [_irq_] = stringify(_irq_)
+static const char *IRQ_NAMES[OT_I2C_IRQ_NUM] = {
+    /* clang-format off */
+    IRQ_NAME_ENTRY(FMT_THRESHOLD),
+    IRQ_NAME_ENTRY(RX_THRESHOLD),
+    IRQ_NAME_ENTRY(ACQ_THRESHOLD),
+    IRQ_NAME_ENTRY(RX_OVERFLOW),
+    IRQ_NAME_ENTRY(CONTROLLER_HALT),
+    IRQ_NAME_ENTRY(SCL_INTERFERENCE),
+    IRQ_NAME_ENTRY(SDA_INTERFERENCE),
+    IRQ_NAME_ENTRY(STRETCH_TIMEOUT),
+    IRQ_NAME_ENTRY(SDA_UNSTABLE),
+    IRQ_NAME_ENTRY(CMD_COMPLETE),
+    IRQ_NAME_ENTRY(TX_STRETCH),
+    IRQ_NAME_ENTRY(TX_THRESHOLD),
+    IRQ_NAME_ENTRY(ACQ_STRETCH),
+    IRQ_NAME_ENTRY(UNEXP_STOP),
+    IRQ_NAME_ENTRY(HOST_TIMEOUT),
+    /* clang-format on */
+};
+#undef IRQ_NAME_ENTRY
+
+#define OT_I2C_FIFO_SIZE     64u
+#define OT_I2C_ACQ_FIFO_SIZE 268u
+
+typedef enum {
+    SIGNAL_NONE,
+    SIGNAL_START,
+    SIGNAL_STOP,
+    SIGNAL_RESTART,
+    SIGNAL_NACK,
+    SIGNAL_NACK_START,
+    SIGNAL_NACK_STOP
+} OtI2CSignal;
+
+struct OtI2CState {
+    SysBusDevice parent_obj;
+
+    I2CBus *bus;
+    I2CSlave *target;
+
+    MemoryRegion mmio;
+
+    uint32_t regs[REGS_COUNT];
+    IbexIRQ irqs[OT_I2C_IRQ_NUM];
+    IbexIRQ alert;
+
+    /*
+     * FMT: Scheduled operations for host mode.
+     * [7:0] = Data byte
+     * [12] = NAKOK
+     */
+    OtFifo32 host_tx_fifo;
+    uint32_t host_tx_threshold;
+
+    /* RX: Received bytes for host mode. */
+    Fifo8 host_rx_fifo;
+
+    /*
+     * ACQ: Received bytes + signals for target mode.
+     * [7:0] = Data byte
+     * [10:8] = Signal (OtI2CSignal)
+     */
+    OtFifo32 target_rx_fifo;
+
+    /* Whether I2C timings should be checked before comm. over the bus */
+    bool check_timings;
+
+    /* TX: Scheduled responses for target mode. */
+    Fifo8 target_tx_fifo;
+
+    /* Target mode first address mask */
+    uint8_t address_mask_0;
+
+    /* Address that was matched to us */
+    uint8_t matched_address;
+
+    uint32_t pclk; /* Current input clock */
+    const char *clock_src_name; /* IRQ name once connected */
+
+    char *ot_id;
+    char *clock_name;
+    DeviceState *clock_src;
+};
+
+struct OtI2CClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+struct OtI2CTarget {
+    I2CSlave i2c;
+};
+
+static uint8_t ot_i2c_address_abyte(uint8_t address, bool read)
+{
+    return (address << 1u) | (read ? 1u : 0);
+}
+
+static void ot_i2c_update_irqs(OtI2CState *s)
+{
+    uint32_t state_masked = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+
+    if (s->regs[R_INTR_STATE] || s->regs[R_INTR_ENABLE]) {
+        trace_ot_i2c_update_irqs(s->ot_id, s->regs[R_INTR_STATE],
+                                 s->regs[R_INTR_ENABLE], state_masked);
+    }
+
+    for (unsigned index = 0; index < ARRAY_SIZE(s->irqs); index++) {
+        bool level = (state_masked & (1U << index)) != 0;
+        ibex_irq_set(&s->irqs[index], level);
+    }
+}
+
+static void ot_i2c_irq_set_state(OtI2CState *s, OtI2CInterrupt irq, bool en)
+{
+    unsigned long *addr = (unsigned long *)&s->regs[R_INTR_STATE];
+
+    if (irq > ARRAY_SIZE(s->irqs)) {
+        return;
+    }
+    if (test_bit(irq, addr) == en) {
+        return;
+    }
+
+    trace_ot_i2c_irq(s->ot_id, IRQ_NAMES[irq], en);
+
+    if (en) {
+        set_bit(irq, addr);
+    } else {
+        clear_bit(irq, addr);
+    }
+
+    ot_i2c_update_irqs(s);
+}
+
+static bool ot_i2c_host_enabled(const OtI2CState *s)
+{
+    return (bool)ARRAY_FIELD_EX32(s->regs, CTRL, ENABLEHOST);
+}
+
+static bool ot_i2c_target_enabled(const OtI2CState *s)
+{
+    return (bool)ARRAY_FIELD_EX32(s->regs, CTRL, ENABLETARGET);
+}
+
+static uint32_t ot_i2c_get_fmt_threshold(const OtI2CState *s)
+{
+    return ARRAY_FIELD_EX32(s->regs, HOST_FIFO_CONFIG, FMT_THRESH);
+}
+
+static uint32_t ot_i2c_get_rx_threshold(const OtI2CState *s)
+{
+    return ARRAY_FIELD_EX32(s->regs, HOST_FIFO_CONFIG, RX_THRESH);
+}
+
+static uint32_t ot_i2c_get_acq_threshold(const OtI2CState *s)
+{
+    return ARRAY_FIELD_EX32(s->regs, TARGET_FIFO_CONFIG, ACQ_THRESH);
+}
+
+static uint32_t ot_i2c_get_tx_threshold(const OtI2CState *s)
+{
+    return ARRAY_FIELD_EX32(s->regs, TARGET_FIFO_CONFIG, TX_THRESH);
+}
+
+static bool ot_i2c_fmt_threshold_intr(OtI2CState *s)
+{
+    return ot_fifo32_num_used(&s->host_tx_fifo) < ot_i2c_get_fmt_threshold(s);
+}
+
+static bool ot_i2c_rx_threshold_intr(OtI2CState *s)
+{
+    return fifo8_num_used(&s->host_rx_fifo) > ot_i2c_get_rx_threshold(s);
+}
+
+static bool ot_i2c_acq_threshold_intr(OtI2CState *s)
+{
+    return ot_fifo32_num_used(&s->target_rx_fifo) > ot_i2c_get_acq_threshold(s);
+}
+
+static bool ot_i2c_tx_threshold_intr(OtI2CState *s)
+{
+    return fifo8_num_used(&s->target_tx_fifo) < ot_i2c_get_tx_threshold(s);
+}
+
+
+static void ot_i2c_host_reset_tx_fifo(OtI2CState *s)
+{
+    SHARED_ARRAY_FIELD_DP32(s->regs, R_INTR_STATE, INTR_FMT_THRESHOLD, 0);
+    ot_fifo32_reset(&s->host_tx_fifo);
+    s->host_tx_threshold = 0;
+}
+
+static void ot_i2c_host_reset_rx_fifo(OtI2CState *s)
+{
+    SHARED_ARRAY_FIELD_DP32(s->regs, R_INTR_STATE, INTR_RX_THRESHOLD, 0);
+    SHARED_ARRAY_FIELD_DP32(s->regs, R_INTR_STATE, INTR_RX_OVERFLOW, 0);
+    fifo8_reset(&s->host_rx_fifo);
+}
+
+static void ot_i2c_target_reset_tx_fifo(OtI2CState *s)
+{
+    SHARED_ARRAY_FIELD_DP32(s->regs, R_INTR_STATE, INTR_TX_THRESHOLD, 0);
+    fifo8_reset(&s->target_tx_fifo);
+}
+
+static void ot_i2c_target_reset_rx_fifo(OtI2CState *s)
+{
+    SHARED_ARRAY_FIELD_DP32(s->regs, R_INTR_STATE, INTR_ACQ_THRESHOLD, 0);
+    ot_fifo32_reset(&s->target_rx_fifo);
+}
+
+static uint8_t ot_i2c_host_read_rx_fifo(OtI2CState *s)
+{
+    if (!ot_i2c_host_enabled(s)) {
+        return 0;
+    }
+    if (fifo8_is_empty(&s->host_rx_fifo)) {
+        return 0;
+    }
+
+    return fifo8_pop(&s->host_rx_fifo);
+}
+
+static void ot_i2c_host_send(OtI2CState *s)
+{
+    trace_ot_i2c_host_send(s->ot_id, ot_fifo32_num_used(&s->host_tx_fifo),
+                           s->host_tx_threshold);
+
+    /* Send all the data in the TX FIFO to the target. */
+    while (!ot_fifo32_is_empty(&s->host_tx_fifo)) {
+        uint32_t val = ot_fifo32_pop(&s->host_tx_fifo);
+        uint8_t fbyte = (uint8_t)FIELD_EX32(val, FDATA, FBYTE);
+        bool nakok = (bool)FIELD_EX32(val, FDATA, NAKOK);
+        if (i2c_send(s->bus, fbyte) && !nakok) {
+            /*
+             * Error while sending byte and NAKOK unset,
+             * raise controller halt interrupt.
+             */
+            ARRAY_FIELD_DP32(s->regs, CONTROLLER_EVENTS, NACK, 1);
+            ot_i2c_irq_set_state(s, CONTROLLER_HALT, true);
+            break;
+        }
+    }
+
+    /*
+     * Threshold interrupt is raised when FIFO depth goes from above
+     * threshold to below. If we haven't reached the threshold, reset the
+     * cached threshold level.
+     */
+    if (s->host_tx_threshold &&
+        ot_fifo32_num_used(&s->host_tx_fifo) < s->host_tx_threshold) {
+        ot_i2c_irq_set_state(s, FMT_THRESHOLD, true);
+        s->host_tx_threshold = 0;
+    }
+}
+
+static uint32_t ot_i2c_target_read_rx_fifo(OtI2CState *s)
+{
+    if (!ot_i2c_target_enabled(s)) {
+        return 0;
+    }
+    if (ot_fifo32_is_empty(&s->target_rx_fifo)) {
+        return 0;
+    }
+
+    return ot_fifo32_pop(&s->target_rx_fifo);
+}
+
+static void ot_i2c_target_write_tx_fifo(OtI2CState *s, uint8_t val)
+{
+    if (!ot_i2c_target_enabled(s)) {
+        return;
+    }
+
+    /* Handle a full FIFO. */
+    if (fifo8_is_full(&s->target_tx_fifo)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Target TX FIFO overflow\n",
+                      __func__, s->ot_id);
+    } else {
+        /* Add this entry to the FIFO. */
+        fifo8_push(&s->target_tx_fifo, val);
+    }
+
+    ot_i2c_irq_set_state(s, TX_THRESHOLD, ot_i2c_tx_threshold_intr(s));
+}
+
+static bool ot_i2c_check_timings(OtI2CState *s)
+{
+    if (!s->pclk) {
+        return 0;
+    }
+
+    uint32_t thigh = FIELD_EX32(s->regs[R_TIMING0], TIMING0, THIGH);
+    uint32_t tlow = FIELD_EX32(s->regs[R_TIMING0], TIMING0, TLOW);
+    uint32_t tr = FIELD_EX32(s->regs[R_TIMING1], TIMING1, T_R);
+    uint32_t tf = FIELD_EX32(s->regs[R_TIMING1], TIMING1, T_F);
+    uint32_t tsusta = FIELD_EX32(s->regs[R_TIMING2], TIMING2, TSU_STA);
+    uint32_t thdsta = FIELD_EX32(s->regs[R_TIMING2], TIMING2, THD_STA);
+    uint32_t tsudat = FIELD_EX32(s->regs[R_TIMING3], TIMING3, TSU_DAT);
+    uint32_t thddat = FIELD_EX32(s->regs[R_TIMING3], TIMING3, THD_DAT);
+    uint32_t tsusto = FIELD_EX32(s->regs[R_TIMING4], TIMING4, TSU_STO);
+    uint32_t tbuf = FIELD_EX32(s->regs[R_TIMING4], TIMING4, T_BUF);
+
+    bool res = true;
+
+    /* Check I2C HW limits (I2C input clock cycles) */
+
+    if (thddat == 0u || (thdsta < thddat + 2u)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid THD settings\n",
+                      __func__, s->ot_id);
+        res = false;
+    }
+    if (tlow < 3u + tr) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid Tlow settings\n",
+                      __func__, s->ot_id);
+        res = false;
+    }
+    if (thigh < 4u) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid Thigh settings\n",
+                      __func__, s->ot_id);
+        res = false;
+    }
+
+    /* Convert clock cycles into nanoseconds based on input clock */
+
+    thigh = (uint32_t)((((uint64_t)thigh) * NANOSECONDS_PER_SECOND) / s->pclk);
+    tlow = (uint32_t)((((uint64_t)tlow) * NANOSECONDS_PER_SECOND) / s->pclk);
+
+    /* Check I2C limits (from I2C specification rev. 6, table 10) */
+
+    if (((thigh >= 4000u) && (tlow < 4700u)) ||
+        ((tlow >= 4700u) && (thigh < 4000u)) ||
+        ((thigh >= 600) && (tlow < 1300u)) ||
+        ((tlow >= 1300u) && (thigh < 600u)) ||
+        ((thigh < 260u) || (tlow < 500u))) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid Thigh/Tlow settings\n",
+                      __func__, s->ot_id);
+        res = false;
+        return res; /* subsequent checks would lead to more errors */
+    }
+
+    uint32_t tsusta_min;
+    uint32_t tsudat_min;
+    uint32_t tsusto_min;
+    uint32_t tbuf_min;
+    uint32_t tr_max;
+    uint32_t tf_max;
+    if (thigh >= 4000u) {
+        /* standard mode */
+        tsusta_min = 4700u;
+        tsudat_min = 250u;
+        tsusto_min = 4000u;
+        tbuf_min = 4700u;
+        tr_max = 1000u;
+        tf_max = 300u;
+    } else if (thigh > 600u) {
+        /* fast mode */
+        tsusta_min = 600u;
+        tsudat_min = 100u;
+        tsusto_min = 600u;
+        tbuf_min = 1300u;
+        tr_max = 300u;
+        tf_max = 300u;
+    } else {
+        /* fast mode plus */
+        tsusta_min = 260u;
+        tsudat_min = 50u;
+        tsusto_min = 260u;
+        tbuf_min = 500u;
+        tr_max = 120u;
+        tf_max = 1230u;
+    }
+
+    tsusta =
+        (uint32_t)((((uint64_t)tsusta) * NANOSECONDS_PER_SECOND) / s->pclk);
+    tsudat =
+        (uint32_t)((((uint64_t)tsudat) * NANOSECONDS_PER_SECOND) / s->pclk);
+    tsusto =
+        (uint32_t)((((uint64_t)tsusto) * NANOSECONDS_PER_SECOND) / s->pclk);
+    tbuf = (uint32_t)((((uint64_t)tbuf) * NANOSECONDS_PER_SECOND) / s->pclk);
+    tr = (uint32_t)((((uint64_t)tr) * NANOSECONDS_PER_SECOND) / s->pclk);
+    tf = (uint32_t)((((uint64_t)tf) * NANOSECONDS_PER_SECOND) / s->pclk);
+
+    if (tsusta < tsusta_min) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Tsu;sta too low\n", __func__,
+                      s->ot_id);
+        res = false;
+    }
+    if (tsudat < tsudat_min) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Tsu;dat too low\n", __func__,
+                      s->ot_id);
+        res = false;
+    }
+    if (tsusto < tsusto_min) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Tsu;sto too low\n", __func__,
+                      s->ot_id);
+        res = false;
+    }
+    if (tbuf < tbuf_min) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Tbuf too low\n", __func__,
+                      s->ot_id);
+        res = false;
+    }
+    if (tr > tr_max) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Tr too high\n", __func__,
+                      s->ot_id);
+        res = false;
+    }
+    if (tf > tf_max) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Tf too high\n", __func__,
+                      s->ot_id);
+        res = false;
+    }
+
+    return res;
+}
+
+static void ot_i2c_clock_input(void *opaque, int irq, int level)
+{
+    OtI2CState *s = opaque;
+
+    g_assert(irq == 0);
+
+    if (level && ((uint32_t)level != s->pclk)) {
+        s->check_timings = true;
+    }
+
+    s->pclk = (uint32_t)level;
+    /* TODO: disable I2C transfers when PCLK is 0 */
+}
+
+static uint64_t ot_i2c_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtI2CState *s = opaque;
+    uint32_t val32 = 0;
+    hwaddr reg = R32_OFF(addr);
+    (void)size;
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_CTRL:
+    case R_HOST_FIFO_CONFIG:
+    case R_TARGET_FIFO_CONFIG:
+    case R_TARGET_ID:
+    case R_TIMEOUT_CTRL:
+    case R_HOST_TIMEOUT_CTRL:
+    case R_CONTROLLER_EVENTS:
+    case R_TARGET_EVENTS:
+        val32 = s->regs[reg];
+        break;
+    case R_STATUS:
+        val32 = FIELD_DP32(val32, STATUS, HOSTIDLE, !i2c_bus_busy(s->bus));
+        val32 = FIELD_DP32(val32, STATUS, TARGETIDLE, !i2c_bus_busy(s->bus));
+
+        /* Report host TX FIFO status. */
+        if (ot_fifo32_is_empty(&s->host_tx_fifo)) {
+            val32 = FIELD_DP32(val32, STATUS, FMTEMPTY, 1u);
+        }
+        if (ot_fifo32_is_full(&s->host_tx_fifo)) {
+            val32 = FIELD_DP32(val32, STATUS, FMTFULL, 1u);
+        }
+
+        /* Report host RX FIFO status. */
+        if (fifo8_is_empty(&s->host_rx_fifo)) {
+            val32 = FIELD_DP32(val32, STATUS, RXEMPTY, 1u);
+        }
+        if (fifo8_is_full(&s->host_rx_fifo)) {
+            val32 = FIELD_DP32(val32, STATUS, RXFULL, 1u);
+        }
+
+        /* Report target TX FIFO status. */
+        if (fifo8_is_empty(&s->target_tx_fifo)) {
+            val32 = FIELD_DP32(val32, STATUS, TXEMPTY, 1u);
+        }
+        if (fifo8_is_full(&s->target_tx_fifo)) {
+            val32 = FIELD_DP32(val32, STATUS, TXFULL, 1u);
+        }
+
+        /* Report target TX FIFO status. */
+        if (ot_fifo32_is_empty(&s->target_rx_fifo)) {
+            val32 = FIELD_DP32(val32, STATUS, ACQEMPTY, 1u);
+        }
+        if (ot_fifo32_is_full(&s->target_rx_fifo)) {
+            val32 = FIELD_DP32(val32, STATUS, ACQFULL, 1u);
+        }
+        break;
+    case R_RDATA:
+        val32 = (uint32_t)ot_i2c_host_read_rx_fifo(s);
+        ot_i2c_irq_set_state(s, RX_THRESHOLD, ot_i2c_rx_threshold_intr(s));
+        break;
+    case R_ACQDATA:
+        val32 = (uint32_t)ot_i2c_target_read_rx_fifo(s);
+        /* Deassert level interrupt state if FIFO is no longer above the
+         * threshold. */
+        ot_i2c_irq_set_state(s, ACQ_THRESHOLD, ot_i2c_acq_threshold_intr(s));
+        break;
+    case R_HOST_FIFO_STATUS:
+        val32 = FIELD_DP32(val32, HOST_FIFO_STATUS, FMTLVL,
+                           ot_fifo32_num_used(&s->host_tx_fifo));
+        val32 = FIELD_DP32(val32, HOST_FIFO_STATUS, RXLVL,
+                           fifo8_num_used(&s->host_rx_fifo));
+        break;
+    case R_TARGET_FIFO_STATUS:
+        val32 = FIELD_DP32(val32, TARGET_FIFO_STATUS, TXLVL,
+                           fifo8_num_used(&s->target_tx_fifo));
+        val32 = FIELD_DP32(val32, TARGET_FIFO_STATUS, ACQLVL,
+                           ot_fifo32_num_used(&s->target_rx_fifo));
+        break;
+    case R_OVRD:
+    case R_VAL:
+    case R_TIMING0:
+    case R_TIMING1:
+    case R_TIMING2:
+    case R_TIMING3:
+    case R_TIMING4:
+        val32 = s->regs[reg];
+        break;
+    case R_TARGET_TIMEOUT_CTRL:
+    case R_TARGET_NACK_COUNT:
+    case R_TARGET_ACK_CTRL:
+    case R_ACQ_FIFO_NEXT_DATA:
+    case R_HOST_NACK_HANDLER_TIMEOUT:
+        qemu_log_mask(LOG_UNIMP, "%s: %s: register %s is not implemented\n",
+                      __func__, s->ot_id, REG_NAME(reg));
+        break;
+    case R_FIFO_CTRL:
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+    case R_FDATA:
+    case R_TXDATA:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint64_t pc = ibex_get_current_pc();
+    trace_ot_i2c_io_read(s->ot_id, (unsigned)addr, REG_NAME(reg),
+                         (uint64_t)val32, pc);
+
+    return (uint64_t)val32;
+}
+
+static unsigned ot_i2c_host_recv_fill_fifo(OtI2CState *s, unsigned chunk)
+{
+    unsigned index = 0;
+
+    trace_ot_i2c_host_recv(s->ot_id, fifo8_num_used(&s->host_rx_fifo), chunk);
+
+    /* Check if read is larger than room in the FIFO. */
+    if (fifo8_num_free(&s->host_rx_fifo) < chunk) {
+        chunk = fifo8_num_free(&s->host_rx_fifo);
+    }
+
+    /* Read expected number of bytes from target. */
+    for (index = 0; index < chunk; index++) {
+        fifo8_push(&s->host_rx_fifo, i2c_recv(s->bus));
+    }
+
+    /* Check if rx_threshold interrupt should be asserted. */
+    ot_i2c_irq_set_state(s, RX_THRESHOLD, ot_i2c_rx_threshold_intr(s));
+
+    /* Return number of bytes read. */
+    return index;
+}
+
+static void ot_i2c_write_fdata(OtI2CState *s, uint32_t fdata)
+{
+    uint8_t fbyte = FIELD_EX32(fdata, FDATA, FBYTE);
+    bool readb = FIELD_EX32(fdata, FDATA, READB);
+    bool start = FIELD_EX32(fdata, FDATA, START);
+    bool stop = FIELD_EX32(fdata, FDATA, STOP);
+    bool rcont = FIELD_EX32(fdata, FDATA, RCONT);
+    bool nakok = FIELD_EX32(fdata, FDATA, NAKOK);
+
+    if (!ot_i2c_host_enabled(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: I2C host not enabled, no write issued\n",
+                      __func__, s->ot_id);
+        return;
+    }
+
+    if (readb) {
+        /* Number of bytes to read is in FDATA.FBYTE, 0 means 256 bytes. */
+        unsigned bytes_to_read = fbyte ?: 256;
+        unsigned index;
+
+        if (nakok) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Invalid FDATA flags READB+NAKOK\n", __func__,
+                          s->ot_id);
+        }
+        if (rcont && stop) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Invalid FDATA flags READB+RCONT+STOP\n",
+                          __func__, s->ot_id);
+            return;
+        }
+
+        /* Read bytes from target device into host_rx_fifo. */
+        do {
+            if (fifo8_is_full(&s->host_rx_fifo)) {
+                /* End the transfer and exit. */
+                ot_i2c_irq_set_state(s, HOST_TIMEOUT, true);
+                i2c_end_transfer(s->bus);
+                return;
+            }
+            index = ot_i2c_host_recv_fill_fifo(s, bytes_to_read);
+            if (index == 0 || index >= bytes_to_read) {
+                break;
+            }
+            bytes_to_read -= index;
+        } while (bytes_to_read);
+
+        /* NACK the last byte read if indicated to allow reads >256 bytes. */
+        if (!rcont) {
+            i2c_nack(s->bus);
+        }
+    } else { /* !READB */
+        if (start) {
+            /* START or RESTART I2C transaction to requested address. */
+            i2c_start_transfer(s->bus, extract32(fbyte, 1, 7),
+                               extract32(fbyte, 0, 1));
+        } else {
+            /* Check for overflow. */
+            if (ot_fifo32_is_full(&s->host_tx_fifo)) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: TX FIFO overflow\n",
+                              __func__, s->ot_id);
+                return;
+            }
+
+            uint32_t val = 0;
+            val = FIELD_DP32(val, FDATA, FBYTE, fbyte);
+            val = FIELD_DP32(val, FDATA, NAKOK, nakok);
+            /* Add this byte to the TX FIFO. */
+            ot_fifo32_push(&s->host_tx_fifo, val);
+
+            /* Check if threshold has been reached. */
+            s->host_tx_threshold = ot_i2c_get_fmt_threshold(s);
+            if (ot_fifo32_num_used(&s->host_tx_fifo) < s->host_tx_threshold) {
+                ot_i2c_irq_set_state(s, FMT_THRESHOLD, true);
+            } else {
+                /* Reset the cached threshold level. */
+                s->host_tx_threshold = 0;
+            }
+
+            /* Try to send contents of TX FIFO to the target. */
+            ot_i2c_host_send(s);
+        }
+    }
+
+    if (stop) {
+        /* End the transaction. */
+        i2c_end_transfer(s->bus);
+
+        /* Signal command completion. */
+        ot_i2c_irq_set_state(s, CMD_COMPLETE, true);
+
+        /* Allow target mode to process data. */
+        i2c_schedule_pending_master(s->bus);
+    }
+}
+
+static void ot_i2c_write(void *opaque, hwaddr addr, uint64_t val64,
+                         unsigned size)
+{
+    OtI2CState *s = opaque;
+    uint32_t val32 = val64;
+    hwaddr reg = R32_OFF(addr);
+    uint64_t pc = ibex_get_current_pc();
+    uint8_t address, mask;
+    (void)size;
+
+    trace_ot_i2c_io_write(s->ot_id, (unsigned)addr, REG_NAME(reg), val64, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_RW1C_MASK;
+        s->regs[reg] &= ~val32;
+        ot_i2c_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[reg] = val32;
+        ot_i2c_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] |= val32;
+        ot_i2c_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        s->regs[reg] = val32;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    case R_TIMEOUT_CTRL:
+    case R_HOST_TIMEOUT_CTRL:
+        s->regs[reg] = val32;
+        break;
+    case R_TARGET_ID:
+        if (FIELD_EX32(val32, TARGET_ID, ADDRESS1)) {
+            qemu_log_mask(
+                LOG_UNIMP,
+                "%s: %s: Target mode second address is not supported.\n",
+                __func__, s->ot_id);
+        }
+        address = FIELD_EX32(val32, TARGET_ID, ADDRESS0);
+        mask = FIELD_EX32(val32, TARGET_ID, MASK0);
+
+        ARRAY_FIELD_DP32(s->regs, TARGET_ID, ADDRESS0, address);
+        ARRAY_FIELD_DP32(s->regs, TARGET_ID, MASK0, mask);
+        /* Update the address mask of this target on the bus. */
+        s->address_mask_0 = (uint8_t)mask;
+        if (address != 0u) {
+            /* Update the address of this target on the bus. */
+            i2c_slave_set_address(s->target, address);
+        }
+        break;
+    case R_CTRL:
+        if (FIELD_EX32(val32, CTRL, LLPBK)) {
+            qemu_log_mask(LOG_UNIMP, "%s: %s: Loopback mode not supported.\n",
+                          __func__, s->ot_id);
+        }
+        /*
+         * Allow both ENABLEHOST and ENABLETARGET to be set so the
+         * host can decide how to configure and use the controller.
+         */
+        val32 &= R_CTRL_LLPBK_MASK | R_CTRL_ENABLEHOST_MASK |
+                 R_CTRL_ENABLETARGET_MASK;
+        s->regs[reg] = val32;
+        if (s->regs[reg]) {
+            /* check timings once, each time one or more timings are updated */
+            if (s->check_timings) {
+                ot_i2c_check_timings(s);
+                s->check_timings = false;
+            }
+        }
+        break;
+    case R_FDATA:
+        ot_i2c_write_fdata(s, val32);
+        break;
+    case R_TXDATA:
+        ot_i2c_target_write_tx_fifo(s, FIELD_EX8(val32, TXDATA, TXDATA));
+        break;
+    case R_FIFO_CTRL:
+        if (FIELD_EX32(val32, FIFO_CTRL, RXRST)) {
+            ot_i2c_host_reset_rx_fifo(s);
+        }
+        if (FIELD_EX32(val32, FIFO_CTRL, TXRST)) {
+            ot_i2c_target_reset_tx_fifo(s);
+        }
+        if (FIELD_EX32(val32, FIFO_CTRL, FMTRST)) {
+            ot_i2c_host_reset_tx_fifo(s);
+        }
+        if (FIELD_EX32(val32, FIFO_CTRL, ACQRST)) {
+            ot_i2c_target_reset_rx_fifo(s);
+        }
+        break;
+    case R_HOST_FIFO_CONFIG:
+        ARRAY_FIELD_DP32(s->regs, HOST_FIFO_CONFIG, RX_THRESH,
+                         FIELD_EX32(val32, HOST_FIFO_CONFIG, RX_THRESH));
+        ARRAY_FIELD_DP32(s->regs, HOST_FIFO_CONFIG, FMT_THRESH,
+                         FIELD_EX32(val32, HOST_FIFO_CONFIG, FMT_THRESH));
+
+        ot_i2c_irq_set_state(s, RX_THRESHOLD, ot_i2c_rx_threshold_intr(s));
+        ot_i2c_irq_set_state(s, FMT_THRESHOLD, ot_i2c_fmt_threshold_intr(s));
+        break;
+    case R_TARGET_FIFO_CONFIG:
+        ARRAY_FIELD_DP32(s->regs, TARGET_FIFO_CONFIG, TX_THRESH,
+                         FIELD_EX32(val32, TARGET_FIFO_CONFIG, TX_THRESH));
+        ARRAY_FIELD_DP32(s->regs, TARGET_FIFO_CONFIG, ACQ_THRESH,
+                         FIELD_EX32(val32, TARGET_FIFO_CONFIG, ACQ_THRESH));
+
+        ot_i2c_irq_set_state(s, TX_THRESHOLD, ot_i2c_tx_threshold_intr(s));
+        ot_i2c_irq_set_state(s, ACQ_THRESHOLD, ot_i2c_acq_threshold_intr(s));
+        break;
+    case R_OVRD:
+        qemu_log_mask(LOG_UNIMP, "%s: %s: register %s is not implemented\n",
+                      __func__, s->ot_id, REG_NAME(reg));
+        val32 &= R_OVRD_TXOVRDEN_MASK | R_OVRD_SCLVAL_MASK | R_OVRD_SDAVAL_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_TIMING0:
+        val32 &= R_TIMING0_THIGH_MASK | R_TIMING0_TLOW_MASK;
+        s->regs[reg] = val32;
+        s->check_timings = true;
+        break;
+    case R_TIMING1:
+        val32 &= R_TIMING1_T_R_MASK | R_TIMING1_T_F_MASK;
+        s->regs[reg] = val32;
+        s->check_timings = true;
+        break;
+    case R_TIMING2:
+        val32 &= R_TIMING2_TSU_STA_MASK | R_TIMING2_THD_STA_MASK;
+        s->regs[reg] = val32;
+        s->check_timings = true;
+        break;
+    case R_TIMING3:
+        val32 &= R_TIMING3_TSU_DAT_MASK | R_TIMING3_THD_DAT_MASK;
+        s->regs[reg] = val32;
+        s->check_timings = true;
+        break;
+    case R_TIMING4:
+        val32 &= R_TIMING4_TSU_STO_MASK | R_TIMING4_T_BUF_MASK;
+        s->regs[reg] = val32;
+        s->check_timings = true;
+        break;
+    case R_CONTROLLER_EVENTS:
+        val32 &= CONTROLLER_EVENTS_RW1C_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_i2c_irq_set_state(s, CONTROLLER_HALT, s->regs[reg] != 0);
+        break;
+    case R_TARGET_EVENTS:
+        val32 &= TARGET_EVENTS_RW1C_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_i2c_irq_set_state(s, TX_STRETCH, s->regs[reg] != 0);
+        break;
+    case R_TARGET_NACK_COUNT:
+    case R_TARGET_ACK_CTRL:
+    case R_ACQ_FIFO_NEXT_DATA:
+    case R_HOST_NACK_HANDLER_TIMEOUT:
+        qemu_log_mask(LOG_UNIMP, "%s: %s: register %s is not implemented\n",
+                      __func__, s->ot_id, REG_NAME(reg));
+        break;
+    case R_STATUS:
+    case R_RDATA:
+    case R_HOST_FIFO_STATUS:
+    case R_TARGET_FIFO_STATUS:
+    case R_VAL:
+    case R_ACQDATA:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static void ot_i2c_target_set_acqdata(OtI2CState *s, uint32_t data,
+                                      OtI2CSignal signal)
+{
+    uint32_t val32 = 0;
+
+    if (ot_fifo32_is_full(&s->target_rx_fifo)) {
+        i2c_end_transfer(s->bus);
+        return;
+    }
+
+    /* Set the first byte to the target address + RW bit as 0. */
+    val32 = FIELD_DP32(val32, ACQDATA, ABYTE, data);
+    /* Indicate that this should send requested signal to the host. */
+    val32 = FIELD_DP32(val32, ACQDATA, SIGNAL, signal);
+    /* Add this entry to the target receive FIFO. */
+    ot_fifo32_push(&s->target_rx_fifo, val32);
+
+    /* See if adding this entry exceeded the threshold. */
+    ot_i2c_irq_set_state(s, ACQ_THRESHOLD, ot_i2c_acq_threshold_intr(s));
+
+    trace_ot_i2c_target_set_acqdata(s->ot_id,
+                                    ot_fifo32_num_used(&s->target_rx_fifo),
+                                    data, signal);
+}
+
+static int ot_i2c_target_event(I2CSlave *target, enum i2c_event event)
+{
+    BusState *abus = qdev_get_parent_bus(DEVICE(target));
+    OtI2CState *s = OT_I2C(abus->parent);
+    int ret = 0;
+
+    if (!ot_i2c_target_enabled(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: I2C target mode not enabled, no event issued\n",
+                      __func__, s->ot_id);
+        return -1;
+    }
+
+    switch (event) {
+    case I2C_START_SEND:
+    case I2C_START_SEND_ASYNC:
+        /* Set the first byte to the matched target address + RW bit as 0. */
+        ot_i2c_target_set_acqdata(s,
+                                  ot_i2c_address_abyte(s->matched_address,
+                                                       false),
+                                  SIGNAL_START);
+        if (event == I2C_START_SEND_ASYNC) {
+            i2c_ack(s->bus);
+        }
+        break;
+    case I2C_START_RECV:
+        ot_i2c_target_set_acqdata(s,
+                                  ot_i2c_address_abyte(s->matched_address,
+                                                       true),
+                                  SIGNAL_START);
+        if (ot_fifo32_num_used(&s->target_rx_fifo) > 1) {
+            /*
+             * Potentially an unhandled condition in the ACQ fifo. Datasheet
+             * says to stretch the clock in this situation so assert that
+             * interrupt and let the driver decide what to do.
+             */
+            ot_i2c_irq_set_state(s, TX_STRETCH, true);
+        }
+        i2c_ack(s->bus);
+        break;
+    case I2C_NACK:
+        g_assert_not_reached();
+        break;
+    case I2C_FINISH:
+        /* Signal STOP as the last entry in the fifo. */
+        ot_i2c_target_set_acqdata(s, 0, SIGNAL_STOP);
+
+        /* Assert command complete interrupt. */
+        ot_i2c_irq_set_state(s, CMD_COMPLETE, true);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: %s: I2C event %d unimplemented\n",
+                      __func__, s->ot_id, event);
+        ret = -1;
+    }
+
+    return ret;
+}
+
+static uint8_t ot_i2c_target_recv(I2CSlave *target)
+{
+    BusState *abus = qdev_get_parent_bus(DEVICE(target));
+    OtI2CState *s = OT_I2C(abus->parent);
+    uint8_t data;
+
+    if (!ot_i2c_target_enabled(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: I2C target mode not enabled, no event issued\n",
+                      __func__, s->ot_id);
+        return 0;
+    }
+
+    /* If the FIFO is empty then there is nothing to return. */
+    if (fifo8_is_empty(&s->target_tx_fifo)) {
+        return 0;
+    }
+
+    /* pop FIFO and check threshold. */
+    data = fifo8_pop(&s->target_tx_fifo);
+    ot_i2c_irq_set_state(s, TX_THRESHOLD, ot_i2c_tx_threshold_intr(s));
+
+    trace_ot_i2c_target_recv(s->ot_id, fifo8_num_used(&s->target_tx_fifo),
+                             data);
+    return data;
+}
+
+static int ot_i2c_target_send(I2CSlave *target, uint8_t data)
+{
+    BusState *abus = qdev_get_parent_bus(DEVICE(target));
+    OtI2CState *s = OT_I2C(abus->parent);
+    if (!ot_i2c_target_enabled(s)) {
+        return -1;
+    }
+
+    ot_i2c_target_set_acqdata(s, data, SIGNAL_NONE);
+    return 0;
+}
+
+static void ot_i2c_target_send_async(I2CSlave *target, uint8_t data)
+{
+    BusState *abus = qdev_get_parent_bus(DEVICE(target));
+    OtI2CState *s = OT_I2C(abus->parent);
+
+    if (ot_i2c_target_enabled(s)) {
+        /* Send data byte with no signal flags. */
+        ot_i2c_target_set_acqdata(s, data, SIGNAL_NONE);
+        i2c_ack(s->bus);
+    }
+}
+
+static bool ot_i2c_target_match_and_add(I2CSlave *candidate, uint8_t address,
+                                        bool broadcast,
+                                        I2CNodeList *current_devs)
+{
+    BusState *abus = qdev_get_parent_bus(DEVICE(candidate));
+    OtI2CState *s = OT_I2C(abus->parent);
+
+    /* Check address, subject to address masking. */
+    if (broadcast || (s->address_mask_0 &&
+                      (address & s->address_mask_0) == candidate->address)) {
+        /*
+         * Store the address that successfully matched to
+         * use the correct address for start condition
+         */
+        s->matched_address = address;
+
+        I2CNode *node = g_new0(struct I2CNode, 1u);
+        node->elt = candidate;
+        QLIST_INSERT_HEAD(current_devs, node, next);
+        return true;
+    }
+
+    /* Not found and not broadcast. */
+    return false;
+}
+
+static void ot_i2c_target_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
+    (void)data;
+
+    dc->desc = "OpenTitan I2C Target";
+    sc->match_and_add = &ot_i2c_target_match_and_add;
+    sc->event = &ot_i2c_target_event;
+    sc->send = &ot_i2c_target_send;
+    sc->send_async = &ot_i2c_target_send_async;
+    sc->recv = &ot_i2c_target_recv;
+}
+
+static const TypeInfo ot_i2c_target_info = {
+    .name = TYPE_OT_I2C_TARGET,
+    .parent = TYPE_I2C_SLAVE,
+    .instance_size = sizeof(OtI2CState),
+    .class_init = &ot_i2c_target_class_init,
+    .class_size = sizeof(I2CSlaveClass),
+};
+
+static const MemoryRegionOps ot_i2c_ops = {
+    .read = &ot_i2c_read,
+    .write = &ot_i2c_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const Property ot_i2c_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtI2CState, ot_id),
+    DEFINE_PROP_STRING("clock-name", OtI2CState, clock_name),
+    DEFINE_PROP_LINK("clock-src", OtI2CState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+};
+
+static void ot_i2c_reset_enter(Object *obj, ResetType type)
+{
+    OtI2CClass *c = OT_I2C_GET_CLASS(obj);
+    OtI2CState *s = OT_I2C(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    i2c_end_transfer(s->bus);
+
+    for (unsigned index = 0; index < ARRAY_SIZE(s->irqs); index++) {
+        ibex_irq_set(&s->irqs[index], 0);
+    }
+    ibex_irq_set(&s->alert, 0);
+
+    memset(s->regs, 0, sizeof(s->regs));
+
+    ot_i2c_host_reset_tx_fifo(s);
+    ot_i2c_host_reset_rx_fifo(s);
+    ot_i2c_target_reset_tx_fifo(s);
+    ot_i2c_target_reset_rx_fifo(s);
+
+    if (!s->clock_src_name) {
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_name =
+            ic->get_clock_source(ii, s->clock_name, DEVICE(s), &error_fatal);
+        qemu_irq in_irq = qdev_get_gpio_in_named(DEVICE(s), "clock-in", 0);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_name, 0, in_irq);
+    }
+
+    s->check_timings = true;
+    s->address_mask_0 = 0x0u;
+    s->matched_address = 0x0u;
+}
+
+static void ot_i2c_realize(DeviceState *dev, Error **errp)
+{
+    OtI2CState *s = OT_I2C(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->clock_name);
+    g_assert(s->clock_src);
+    OBJECT_CHECK(IbexClockSrcIf, s->clock_src, TYPE_IBEX_CLOCK_SRC_IF);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_i2c_clock_input, "clock-in", 1);
+
+    /* TODO: check if the following can be moved to ot_i2c_init */
+    char *bus_name = g_strdup_printf("ot-%s", s->ot_id);
+    s->bus = i2c_init_bus(dev, bus_name);
+    g_free(bus_name);
+    s->target = i2c_slave_create_simple(s->bus, TYPE_OT_I2C_TARGET, 0xff);
+}
+
+static void ot_i2c_init(Object *obj)
+{
+    OtI2CState *s = OT_I2C(obj);
+
+    for (unsigned index = 0; index < ARRAY_SIZE(s->irqs); index++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[index]);
+    }
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    memory_region_init_io(&s->mmio, obj, &ot_i2c_ops, s, TYPE_OT_I2C,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    ot_fifo32_create(&s->host_tx_fifo, OT_I2C_FIFO_SIZE);
+    fifo8_create(&s->host_rx_fifo, OT_I2C_FIFO_SIZE);
+    fifo8_create(&s->target_tx_fifo, OT_I2C_FIFO_SIZE);
+    ot_fifo32_create(&s->target_rx_fifo, OT_I2C_ACQ_FIFO_SIZE);
+}
+
+static void ot_i2c_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->desc = "OpenTitan I2C Host";
+    dc->realize = ot_i2c_realize;
+    device_class_set_props(dc, ot_i2c_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtI2CClass *ic = OT_I2C_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_i2c_reset_enter, NULL, NULL,
+                                       &ic->parent_phases);
+}
+
+static const TypeInfo ot_i2c_info = {
+    .name = TYPE_OT_I2C,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtI2CState),
+    .instance_init = &ot_i2c_init,
+    .class_size = sizeof(OtI2CClass),
+    .class_init = &ot_i2c_class_init,
+};
+
+static void ot_i2c_register_types(void)
+{
+    type_register_static(&ot_i2c_info);
+    type_register_static(&ot_i2c_target_info);
+}
+
+type_init(ot_i2c_register_types);
diff --git a/hw/opentitan/ot_i2c_host_proxy.c b/hw/opentitan/ot_i2c_host_proxy.c
new file mode 100644
index 0000000000000..8edac7b3fd4b4
--- /dev/null
+++ b/hw/opentitan/ot_i2c_host_proxy.c
@@ -0,0 +1,373 @@
+/*
+ * I2C Host Proxy Device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "qom/object.h"
+#include "chardev/char-fe.h"
+#include "hw/i2c/i2c.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_i2c_host_proxy.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "trace.h"
+
+typedef enum {
+    /* Initial state, wait for 'i' followed by version byte */
+    CMD_I2C_INIT,
+    /* Waiting for version byte */
+    CMD_I2C_VERSION,
+    /* bus idle state before transaction start */
+    CMD_I2C_BUS_IDLE,
+    /* Waiting for address + r/w byte */
+    CMD_I2C_START,
+    CMD_I2C_REPEATED_START,
+    /* read transaction - waiting to read byte */
+    CMD_I2C_READ,
+    /* write transaction - waiting to write byte */
+    CMD_I2C_WRITE,
+    /* write transaction - waiting for byte to write */
+    CMD_I2C_WRITE_PAYLOAD,
+    /* parse error state */
+    CMD_I2C_ERR,
+} CmdParserState;
+
+#define I2C_PROXY_PROTO_VERSION 0x01u
+
+#define I2C_PROXY_STALL_NS 100000u /* 100us */
+
+struct OtI2CHostProxyState {
+    I2CSlave parent_obj;
+    I2CBus *bus;
+
+    /* chardev i2c command parser state */
+    CmdParserState parser_state;
+
+    /* Saved target address of transaction for repeated start conditions */
+    uint8_t address;
+
+    /*
+     * Timer to stall chardev I/O to return control back to the vCPU, so
+     * that OT can process the I2C transaction
+     */
+    QEMUTimer *stall_timer;
+
+    /* device change tracker */
+    guint watch_tag;
+
+    CharFrontend chr;
+};
+
+struct OtI2CHostProxyClass {
+    I2CSlaveClass parent_class;
+};
+
+static void ot_i2c_host_proxy_put_byte(OtI2CHostProxyState *s, uint8_t data)
+{
+    qemu_chr_fe_write(&s->chr, &data, 1u);
+}
+
+static void ot_i2c_host_proxy_put_nack(OtI2CHostProxyState *s)
+{
+    ot_i2c_host_proxy_put_byte(s, (uint8_t)'!');
+}
+
+static void ot_i2c_host_proxy_put_ack(OtI2CHostProxyState *s)
+{
+    ot_i2c_host_proxy_put_byte(s, (uint8_t)'.');
+}
+
+/*
+ * Stall the chardev to slow down I2C transaction processing, so that QEMU can
+ * return control to the vCPU to process and prepare response data for OT I2C.
+ */
+static void ot_i2c_host_proxy_stall(OtI2CHostProxyState *s)
+{
+    uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+    timer_mod(s->stall_timer, (int64_t)(now + I2C_PROXY_STALL_NS));
+}
+
+static void
+ot_i2c_host_proxy_start_transfer(OtI2CHostProxyState *s, bool read_transfer)
+{
+    if (i2c_start_transfer(s->bus, s->address, read_transfer) != 0) {
+        ot_i2c_host_proxy_put_nack(s);
+    } else {
+        ot_i2c_host_proxy_put_ack(s);
+    }
+    ot_i2c_host_proxy_stall(s);
+}
+
+static void ot_i2c_host_proxy_do_read(OtI2CHostProxyState *s)
+{
+    ot_i2c_host_proxy_put_byte(s, i2c_recv(s->bus));
+    ot_i2c_host_proxy_stall(s);
+}
+
+static void ot_i2c_host_proxy_do_write(OtI2CHostProxyState *s, uint8_t data)
+{
+    if (i2c_send(s->bus, data) != 0) {
+        ot_i2c_host_proxy_put_nack(s);
+    } else {
+        ot_i2c_host_proxy_put_ack(s);
+    }
+    ot_i2c_host_proxy_stall(s);
+}
+
+static void ot_i2c_host_proxy_parse_error(OtI2CHostProxyState *s)
+{
+    s->parser_state = CMD_I2C_ERR;
+    ot_i2c_host_proxy_put_byte(s, (uint8_t)'x');
+}
+
+static void ot_i2c_host_proxy_command_byte(OtI2CHostProxyState *s, uint8_t byte)
+{
+    switch (s->parser_state) {
+    case CMD_I2C_INIT:
+        if (byte == 'i') {
+            s->parser_state = CMD_I2C_VERSION;
+            break;
+        }
+        s->parser_state = CMD_I2C_ERR;
+        break;
+    case CMD_I2C_VERSION:
+        if (byte == I2C_PROXY_PROTO_VERSION) {
+            ot_i2c_host_proxy_put_ack(s);
+            s->parser_state = CMD_I2C_BUS_IDLE;
+            break;
+        }
+        ot_i2c_host_proxy_put_nack(s);
+        s->parser_state = CMD_I2C_ERR;
+        break;
+    case CMD_I2C_BUS_IDLE:
+        if (byte == 'S') {
+            s->parser_state = CMD_I2C_START;
+            break;
+        }
+        s->parser_state = CMD_I2C_ERR;
+        break;
+    case CMD_I2C_START:
+    case CMD_I2C_REPEATED_START:
+        /*
+         * If a transaction is already in progress (repeated start), QEMU does
+         * not re-scan the bus to find devices even if the provided address
+         * is different, so we do not bother storing it here as the address
+         * that the transaction was started with will be used anyway.
+         */
+        if (s->parser_state == CMD_I2C_START) {
+            s->address = (byte >> 1u);
+        }
+        bool read_transfer = (byte & 1u) == 1u;
+        ot_i2c_host_proxy_start_transfer(s, read_transfer);
+        s->parser_state = read_transfer ? CMD_I2C_READ : CMD_I2C_WRITE;
+        break;
+    case CMD_I2C_READ:
+        if (byte == 'R') {
+            ot_i2c_host_proxy_do_read(s);
+            break;
+        }
+        if (byte == 'P') {
+            s->parser_state = CMD_I2C_INIT;
+            i2c_end_transfer(s->bus);
+            break;
+        }
+        if (byte == 'S') {
+            s->parser_state = CMD_I2C_REPEATED_START;
+            break;
+        }
+        s->parser_state = CMD_I2C_ERR;
+        i2c_end_transfer(s->bus);
+        ot_i2c_host_proxy_parse_error(s);
+        break;
+    case CMD_I2C_WRITE:
+        if (byte == 'W') {
+            s->parser_state = CMD_I2C_WRITE_PAYLOAD;
+            break;
+        }
+        if (byte == 'P') {
+            s->parser_state = CMD_I2C_INIT;
+            i2c_end_transfer(s->bus);
+            break;
+        }
+        if (byte == 'S') {
+            s->parser_state = CMD_I2C_REPEATED_START;
+            break;
+        }
+        s->parser_state = CMD_I2C_ERR;
+        i2c_end_transfer(s->bus);
+        ot_i2c_host_proxy_parse_error(s);
+        break;
+    case CMD_I2C_WRITE_PAYLOAD:
+        ot_i2c_host_proxy_do_write(s, byte);
+        s->parser_state = CMD_I2C_WRITE;
+        break;
+    case CMD_I2C_ERR:
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void ot_i2c_host_proxy_timer(void *opaque)
+{
+    (void)opaque;
+}
+
+static int ot_i2c_host_proxy_can_receive(void *opaque)
+{
+    OtI2CHostProxyState *s = OT_I2C_HOST_PROXY(opaque);
+    if (s->parser_state == CMD_I2C_ERR) {
+        return 0;
+    }
+    return timer_pending(s->stall_timer) ? 0 : 1;
+}
+
+static void ot_i2c_host_proxy_receive(void *opaque, const uint8_t *buf,
+                                      int size)
+{
+    OtI2CHostProxyState *s = OT_I2C_HOST_PROXY(opaque);
+    g_assert(size == 1);
+    ot_i2c_host_proxy_command_byte(s, *buf);
+}
+
+static void ot_i2c_host_proxy_event_handler(void *opaque, QEMUChrEvent event)
+{
+    OtI2CHostProxyState *s = OT_I2C_HOST_PROXY(opaque);
+
+    if (event == CHR_EVENT_CLOSED) {
+        switch (s->parser_state) {
+        case CMD_I2C_READ:
+        case CMD_I2C_WRITE:
+        case CMD_I2C_WRITE_PAYLOAD:
+            i2c_end_transfer(s->bus);
+            break;
+        default:
+            break;
+        }
+        s->parser_state = CMD_I2C_INIT;
+        timer_del(s->stall_timer);
+    }
+}
+
+static int ot_i2c_host_proxy_chr_watch_cb(void *do_not_use, GIOCondition cond,
+                                          void *opaque)
+{
+    OtI2CHostProxyState *s = OT_I2C_HOST_PROXY(opaque);
+    (void)do_not_use;
+    (void)cond;
+    s->watch_tag = 0;
+    return 0;
+}
+
+static int ot_i2c_host_proxy_be_change(void *opaque)
+{
+    OtI2CHostProxyState *s = OT_I2C_HOST_PROXY(opaque);
+
+    qemu_chr_fe_set_handlers(&s->chr, ot_i2c_host_proxy_can_receive,
+                             ot_i2c_host_proxy_receive,
+                             ot_i2c_host_proxy_event_handler,
+                             ot_i2c_host_proxy_be_change, s, NULL, true);
+
+    if (s->watch_tag > 0) {
+        g_source_remove(s->watch_tag);
+        s->watch_tag =
+            /* NOLINTNEXTLINE(clang-analyzer-optin.core.EnumCastOutOfRange) */
+            qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+                                  &ot_i2c_host_proxy_chr_watch_cb, s);
+    }
+
+    return 0;
+}
+
+static void ot_i2c_host_proxy_realize(DeviceState *dev, Error **errp)
+{
+    (void)errp;
+    OtI2CHostProxyState *state = OT_I2C_HOST_PROXY(dev);
+    BusState *bus = qdev_get_parent_bus(dev);
+    state->bus = I2C_BUS(bus);
+    qemu_chr_fe_set_handlers(&state->chr, ot_i2c_host_proxy_can_receive,
+                             ot_i2c_host_proxy_receive, NULL,
+                             ot_i2c_host_proxy_be_change, state, NULL, true);
+}
+
+static void ot_i2c_host_proxy_init(Object *obj)
+{
+    OtI2CHostProxyState *s = OT_I2C_HOST_PROXY(obj);
+    s->parser_state = CMD_I2C_INIT;
+    s->stall_timer =
+        timer_new_ns(OT_VIRTUAL_CLOCK, &ot_i2c_host_proxy_timer, (void *)s);
+}
+
+static const Property ot_i2c_host_proxy_properties[] = {
+    DEFINE_PROP_CHR("chardev", OtI2CHostProxyState, chr),
+};
+
+/*
+ * This device does not support being a target device, and does not respond to
+ * transactions. Overwrite the default `match_and_add` implementation to
+ * always not match any address, even for a broadcast.
+ */
+static bool ot_i2c_host_proxy_match_and_add(
+    I2CSlave *s, uint8_t address, bool broadcast, I2CNodeList *current_devs)
+{
+    (void)s;
+    (void)address;
+    (void)broadcast;
+    (void)current_devs;
+    return false;
+}
+
+static void ot_i2c_host_proxy_class_init(ObjectClass *klass, const void *data)
+{
+    (void)data;
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "I2C Host Proxy";
+    dc->realize = ot_i2c_host_proxy_realize;
+    device_class_set_props(dc, ot_i2c_host_proxy_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
+    sc->match_and_add = &ot_i2c_host_proxy_match_and_add;
+}
+
+static const TypeInfo ot_i2c_host_proxy = {
+    .name = TYPE_OT_I2C_HOST_PROXY,
+    .parent = TYPE_I2C_SLAVE,
+    .instance_size = sizeof(OtI2CHostProxyState),
+    .instance_init = ot_i2c_host_proxy_init,
+    .class_init = ot_i2c_host_proxy_class_init,
+    .class_size = sizeof(OtI2CHostProxyClass),
+};
+
+static void register_types(void)
+{
+    type_register_static(&ot_i2c_host_proxy);
+}
+
+type_init(register_types);
diff --git a/hw/opentitan/ot_ibex_wrapper.c b/hw/opentitan/ot_ibex_wrapper.c
new file mode 100644
index 0000000000000..0a23f5d52a5e1
--- /dev/null
+++ b/hw/opentitan/ot_ibex_wrapper.c
@@ -0,0 +1,1568 @@
+/*
+ * QEMU OpenTitan Ibex wrapper device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: there are two modes to handle address remapping:
+ *   - default mode: use an MMU-like implementation (via ot_vmapper) to remap
+ *     addresses. This mode enables to remap instruction accesses and data
+ *     accesses independently, as the real HW. However, due to QEMU limitations,
+ *     addresses and mapped region sizes should be aligned and multiple of 4096
+ *     bytes, i.e. a standard MMU page size. This is the recommended mode.
+ *   - legacy mode: This mode has no address nor size limitations, however it
+ *     cannot distinguish instruction accesses from data accesses, which means
+ *     that both kind of accesses must be defined for each active remapping slot
+ *     for the remapping to be enabled. Moreover it relies on MemoryRegion
+ *     aliasing and may not be as robust as the default mode. It is recommended
+ *     to use the default mode whenever possible. To enable this legacy mode,
+ *     set the "alias-mode" property to true.
+ */
+
+#include "qemu/osdep.h"
+#include <string.h>
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "chardev/char-fe.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_ibex_wrapper.h"
+#include "hw/opentitan/ot_vmapper.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+/* DEBUG: define to print the full memory view on remap */
+#undef PRINT_MTREE
+/* DEBUG: define to print the enumerated list of registers */
+#undef PRINT_REGNAMES
+
+#define NUM_SW_ALERTS 2u
+#define NUM_ALERTS    4u
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x0u)
+    SHARED_FIELD(ALERT_FATAL_SW, 0u, 1u)
+    SHARED_FIELD(ALERT_RECOV_SW, 1u, 1u)
+    SHARED_FIELD(ALERT_FATAL_HW, 2u, 1u)
+    SHARED_FIELD(ALERT_RECOV_HW, 3u, 1u)
+REG32(SW_RECOV_ERR, 0x4u)
+    FIELD(SW_RECOV_ERR, VAL, 0u, 4u)
+REG32(SW_FATAL_ERR, 0x8u)
+    FIELD(SW_FATAL_ERR, VAL, 0u, 4u)
+SHARED_FIELD(REGWEN_EN, 0u, 1u)
+SHARED_FIELD(ADDR_EN, 0u, 1u)
+SHARED_FIELD(NMI_ALERT_EN, 0u, 1u)
+SHARED_FIELD(NMI_WDOG_EN, 1u, 1u)
+SHARED_FIELD(ERR_STATUS_REG_INTG, 0u, 1u)
+SHARED_FIELD(ERR_STATUS_FATAL_INTG, 8u, 1u)
+SHARED_FIELD(ERR_STATUS_FATAL_CORE, 9u, 1u)
+SHARED_FIELD(ERR_STATUS_RECOV_CORE, 10u, 1u)
+SHARED_FIELD(RND_STATUS_RND_DATA_VALID, 0u, 1u)
+SHARED_FIELD(RND_STATUS_RND_DATA_FIPS, 1u, 1u)
+SHARED_FIELD(DV_SIM_STATUS_CODE, 0u, 16u)
+SHARED_FIELD(DV_SIM_STATUS_INFO, 16u, 16u)
+/* clang-format on */
+
+#define ALERT_MASK \
+    (ALERT_FATAL_SW_MASK | ALERT_RECOV_SW_MASK | ALERT_FATAL_HW_MASK | \
+     ALERT_RECOV_HW_MASK)
+
+#define ERR_STATUS_MASK \
+    (ERR_STATUS_REG_INTG_MASK | ERR_STATUS_FATAL_INTG_MASK | \
+     ERR_STATUS_FATAL_CORE_MASK | ERR_STATUS_RECOV_CORE_MASK)
+
+#define NMI_MASK (NMI_ALERT_EN_MASK | NMI_WDOG_EN_MASK)
+
+/* OpenTitan SW log severities. */
+typedef enum {
+    TEST_LOG_SEVERITY_INFO,
+    TEST_LOG_SEVERITY_WARN,
+    TEST_LOG_SEVERITY_ERROR,
+    TEST_LOG_SEVERITY_FATAL,
+} OtIbexTestLogLevel;
+
+/* OpenTitan SW log metadata used to format a log line. */
+typedef struct {
+    OtIbexTestLogLevel severity;
+    uint32_t file_name_ptr; /* const char * in RV32 */
+    uint32_t line;
+    uint32_t nargs;
+    uint32_t format_ptr; /* const char * in RV32 */
+} OtIbexTestLogFields;
+
+typedef enum {
+    TEST_LOG_STATE_IDLE,
+    TEST_LOG_STATE_ARG,
+    TEST_LOG_STATE_ERROR,
+} OtIbexTestLogState;
+
+/*
+ * These enumerated values are not HW values, however the two last values are
+ * documented by DV SW as:"This is a terminal state. Any code appearing after
+ * this value is set is unreachable."
+ *
+ * There are therefore handled as special HW-SW case that triggers explicit
+ * QEMU termination with a special exit code.
+ */
+typedef enum {
+    TEST_STATUS_IN_BOOT_ROM = 0xb090, /* 'bogo', BOotrom GO */
+    TEST_STATUS_IN_BOOT_ROM_HALT = 0xb057, /* 'bost', BOotrom STop */
+    TEST_STATUS_IN_TEST = 0x4354, /* 'test' */
+    TEST_STATUS_IN_WFI = 0x1d1e, /* 'idle' */
+    TEST_STATUS_PASSED = 0x900d, /* 'good' */
+    TEST_STATUS_FAILED = 0xbaad /* 'baad' */
+} OtIbexTestStatus;
+
+typedef enum {
+    ACCESS_INSN,
+    ACCESS_DATA,
+    ACCESS_COUNT,
+} OtIbexRemapAccess;
+
+enum {
+    DV_SIM_STATUS,
+    DV_SIM_LOG,
+    DV_SIM_WIN2,
+    DV_SIM_WIN3,
+    DV_SIM_WIN4,
+    DV_SIM_WIN5,
+    DV_SIM_WIN6,
+    DV_SIM_WIN7,
+    DV_SIM_COUNT,
+};
+
+typedef struct {
+    OtIbexTestLogState state;
+    AddressSpace *as;
+    OtIbexTestLogFields fields;
+    unsigned arg_count;
+    uintptr_t *args; /* arguments */
+    bool *strargs; /* whether slot should be freed or a not */
+    const char *fmtptr; /* current pointer in format string */
+    char *filename;
+    char *format;
+} OtIbexTestLogEngine;
+
+typedef uint32_t (*ot_ibex_wrapper_reg_read_fn)(OtIbexWrapperState *s,
+                                                unsigned reg);
+typedef void (*ot_ibex_wrapper_reg_write_fn)(OtIbexWrapperState *s,
+                                             unsigned reg, uint32_t value);
+
+typedef struct {
+    uint32_t regwen;
+    uint32_t addr_en;
+    uint32_t addr_matching;
+    uint32_t remap_addr;
+} OtIbexRemap;
+
+typedef struct {
+    uint32_t alert_test;
+    uint32_t sw_recov_err;
+    uint32_t sw_fatal_err;
+    /* physical location for remapper regs are moved to the end of struct */
+    uint32_t nmi_enable;
+    uint32_t nmi_state;
+    uint32_t err_status;
+    uint32_t rnd_data;
+    uint32_t rnd_status;
+    uint32_t fpga_info;
+    uint32_t _reserved[7u];
+    uint32_t dv_sim_win[DV_SIM_COUNT];
+    /* note: remap pointer introduce padding here */
+    OtIbexRemap *remap[ACCESS_COUNT]; /* num_regions */
+} OtIbexWrapperRegs;
+
+typedef struct {
+    ot_ibex_wrapper_reg_read_fn read;
+    ot_ibex_wrapper_reg_write_fn write;
+    uint32_t mask; /* the mask to apply to the written value */
+} OtIbexWrapperAccess;
+
+struct OtIbexWrapperState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    MemoryRegion *remappers;
+    MemoryRegion *sys_mem;
+    IbexIRQ alerts[NUM_ALERTS];
+
+    OtIbexTestLogEngine *log_engine;
+    OtIbexWrapperRegs regs; /* not ordered by register index */
+    OtIbexWrapperAccess *access_table; /* ordered by register index */
+    uint32_t **access_regs; /* ordered by register index */
+    char **reg_names; /* ordered by register index */
+    CPUState *cpu;
+    unsigned reg_count; /* total count of registers */
+    unsigned remap_reg_count; /* count of remapping registers */
+    uint8_t cpu_en_bm;
+    bool entropy_requested;
+    bool edn_connected;
+    bool esc_rx;
+
+    char *ot_id;
+    char *lc_ignore_ids;
+    OtEDNState *edn;
+    OtVMapperState *vmapper;
+    uint8_t num_regions;
+    uint8_t edn_ep;
+    uint8_t qemu_version;
+    bool lc_ignore;
+    bool alias_mode;
+    bool dv_sim_status_exit;
+    CharFrontend chr;
+};
+
+struct OtIbexWrapperClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+#define OT_IBEX_CPU_EN_MASK (((1u << OT_IBEX_CPU_EN_COUNT)) - 1u)
+
+static const char MISSING_LOG_STRING[] = "(?)";
+
+#define CASE_RANGE(_reg_, _cnt_) (_reg_)...((_reg_) + (_cnt_) - (1u))
+
+#define xtrace_ot_ibex_wrapper_info(_s_, _msg_) \
+    trace_ot_ibex_wrapper_info((_s_)->ot_id, __func__, __LINE__, _msg_)
+#define xtrace_ot_ibex_wrapper_error(_s_, _msg_) \
+    trace_ot_ibex_wrapper_error((_s_)->ot_id, __func__, __LINE__, _msg_)
+
+#define REG_NAME_LENGTH 24u /* > "DBUS_ADDR_MATCHING_31" */
+
+#define LAST_STATIC_REG     sw_fatal_err
+#define FIRST_REMAP_REG_POS ((LAST_STATIC_REG_POS) + 1u)
+#define LAST_STATIC_REG_POS R32_POS(LAST_STATIC_REG)
+#define R32_OFF(_r_)        ((_r_) / sizeof(uint32_t))
+#define R32_POS(_r_)        (offsetof(OtIbexWrapperRegs, _r_) / sizeof(uint32_t))
+#define R32_DYN_OFFSET(_s_, _r_) \
+    (R32_POS(_r_) <= LAST_STATIC_REG_POS ? 0 : s->remap_reg_count)
+#define R32_DYN_POS(_s_, _r_) (R32_POS(_r_) + R32_DYN_OFFSET(_s_, _r_))
+#define REG_NAME(_s_, _reg_) \
+    ((_reg_) < (_s_)->reg_count ? (_s_)->reg_names[(_reg_)] : "?")
+#define CREATE_NAME_REG_AT(_s_, _off_, _reg_) \
+    strncpy((_s_)->reg_names[_off_], stringify(_reg_), REG_NAME_LENGTH - 1)
+#define CREATE_NAME_REG(_s_, _reg_) CREATE_NAME_REG_AT(_s_, R_##_reg_, _reg_)
+#define CREATE_NAME_REG_IX_AT(_s_, _pfx_, _off_, _ix_, _reg_) \
+    do { \
+        int l = snprintf((_s_)->reg_names[(_off_)], REG_NAME_LENGTH, \
+                         "%s" stringify(_reg_) "_%u", (_pfx_), (_ix_)); \
+        g_assert((unsigned)l < REG_NAME_LENGTH); \
+    } while (0)
+
+/*
+ * Alert management
+ */
+
+static void ot_ibex_wrapper_update_alerts(OtIbexWrapperState *s)
+{
+    uint32_t level = s->regs.alert_test;
+
+    if (s->regs.sw_fatal_err != OT_MULTIBITBOOL4_FALSE) {
+        level |= ALERT_FATAL_SW_MASK;
+    }
+
+    for (unsigned ix = 0; ix < NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+/*
+ * Entropy management (RND)
+ */
+
+static void ot_ibex_wrapper_fill_entropy(void *opaque, uint32_t bits, bool fips)
+{
+    OtIbexWrapperState *s = opaque;
+
+    trace_ot_ibex_wrapper_fill_entropy(s->ot_id, bits, fips);
+
+    s->regs.rnd_data = bits;
+    s->regs.rnd_status = RND_STATUS_RND_DATA_VALID_MASK;
+    if (fips) {
+        s->regs.rnd_status |= RND_STATUS_RND_DATA_FIPS_MASK;
+    }
+
+    s->entropy_requested = false;
+}
+
+static bool ot_ibex_wrapper_has_edn(OtIbexWrapperState *s)
+{
+    return (s->edn != NULL) && (s->edn_ep != UINT8_MAX);
+}
+
+static void ot_ibex_wrapper_request_entropy(OtIbexWrapperState *s)
+{
+    if (!s->entropy_requested && ot_ibex_wrapper_has_edn(s)) {
+        if (unlikely(!s->edn_connected)) {
+            ot_edn_connect_endpoint(s->edn, s->edn_ep,
+                                    &ot_ibex_wrapper_fill_entropy, s);
+            s->edn_connected = true;
+        }
+        s->entropy_requested = true;
+        trace_ot_ibex_wrapper_request_entropy(s->ot_id, s->entropy_requested);
+        if (ot_edn_request_entropy(s->edn, s->edn_ep)) {
+            s->entropy_requested = false;
+            xtrace_ot_ibex_wrapper_error(s, "failed to request entropy");
+        }
+    }
+}
+
+/*
+ * Address translation management (legacy mode using memory region aliases)
+ */
+
+static void
+ot_ibex_wrapper_remapper_destroy(OtIbexWrapperState *s, unsigned slot)
+{
+    g_assert(slot < (unsigned)s->num_regions);
+    MemoryRegion *mr = &s->remappers[slot];
+    if (memory_region_is_mapped(mr)) {
+        trace_ot_ibex_wrapper_unmap(s->ot_id, slot);
+        memory_region_transaction_begin();
+        memory_region_set_enabled(mr, false);
+        /* QEMU memory model enables unparenting alias regions */
+        memory_region_del_subregion(s->sys_mem, mr);
+        memory_region_transaction_commit();
+    }
+}
+
+/* NOLINTNEXTLINE */
+static bool ot_ibex_wrapper_mr_map_offset(hwaddr *offset,
+                                          const MemoryRegion *root, hwaddr dst,
+                                          size_t size, const MemoryRegion *tmr)
+{
+    if (root == tmr) {
+        return true;
+    }
+
+    const MemoryRegion *mr;
+
+    QTAILQ_FOREACH(mr, &root->subregions, subregions_link) {
+        if (dst < mr->addr ||
+            (dst + size) > (mr->addr + int128_getlo(mr->size))) {
+            continue;
+        }
+
+        bool ret;
+
+        if (mr->alias) {
+            hwaddr alias_offset = mr->addr - mr->alias_offset;
+            dst -= alias_offset;
+
+            ret = ot_ibex_wrapper_mr_map_offset(offset, mr->alias, dst, size,
+                                                tmr);
+            if (ret) {
+                /*
+                 * the selected MR tree leads to the target region, so update
+                 * the alias offset with the local offset
+                 */
+                *offset += alias_offset;
+            }
+        } else {
+            ret = ot_ibex_wrapper_mr_map_offset(offset, mr, dst, size, tmr);
+            if (ret) {
+                *offset += mr->addr;
+            }
+        }
+
+        return ret;
+    }
+
+    return false;
+}
+
+static void ot_ibex_wrapper_remapper_create(
+    OtIbexWrapperState *s, unsigned slot, hwaddr dst, hwaddr src, size_t size)
+{
+    g_assert(slot < (unsigned)s->num_regions);
+    MemoryRegion *mr = &s->remappers[slot];
+    g_assert(!memory_region_is_mapped(mr));
+
+    int priority = (int)((unsigned)s->num_regions - slot);
+
+    MemoryRegion *mr_dst;
+
+    char *name = g_strdup_printf(TYPE_OT_IBEX_WRAPPER "-remap[%u]", slot);
+
+    memory_region_transaction_begin();
+    /*
+     * try to map onto the actual device if there's a single one, otherwise
+     * map on the whole address space.
+     */
+    MemoryRegionSection mrs;
+    mrs = memory_region_find(s->sys_mem, dst, (uint64_t)size);
+    size_t mrs_lsize = int128_getlo(mrs.size);
+    mr_dst = (mrs.mr && mrs_lsize >= size) ? mrs.mr : s->sys_mem;
+
+    /*
+     * adjust the offset if the memory region target for the mapping
+     * is itself mapped through memory region(s)
+     */
+    hwaddr offset = 0;
+    if (ot_ibex_wrapper_mr_map_offset(&offset, s->sys_mem, dst, size, mr_dst)) {
+        offset = dst - offset;
+    }
+
+    trace_ot_ibex_wrapper_map(s->ot_id, slot, src, dst, size, mr_dst->name,
+                              (uint32_t)offset);
+    memory_region_init_alias(mr, OBJECT(s), name, mr_dst, offset,
+                             (uint64_t)size);
+    memory_region_add_subregion_overlap(s->sys_mem, src, mr, priority);
+    memory_region_set_enabled(mr, true);
+    memory_region_transaction_commit();
+    g_free(name);
+
+#ifdef PRINT_MTREE
+    mtree_info(false, false, false, true);
+#endif
+}
+
+static void ot_ibex_wrapper_update_remap_mr(
+    OtIbexWrapperState *s, OtIbexRemapAccess access, unsigned slot)
+{
+    g_assert(slot < (unsigned)s->num_regions);
+    /*
+     * Warning:
+     * for now, QEMU is unable to distinguish instruction or data access.
+     * in this implementation, we chose to enable remap whenever either D or I
+     * remapping is selected, and both D & I configuration match; we disable
+     * translation when both D & I are remapping are disabled
+     */
+    (void)access;
+
+    bool en_remap_i = s->regs.remap[ACCESS_INSN][slot].addr_en;
+    bool en_remap_d = s->regs.remap[ACCESS_DATA][slot].addr_en;
+    if (!en_remap_i && !en_remap_d) {
+        /* disable */
+        ot_ibex_wrapper_remapper_destroy(s, slot);
+    } else {
+        uint32_t src_match_i = s->regs.remap[ACCESS_INSN][slot].addr_matching;
+        uint32_t src_match_d = s->regs.remap[ACCESS_DATA][slot].addr_matching;
+        if (src_match_i != src_match_d) {
+            /* I and D do not match, do nothing */
+            xtrace_ot_ibex_wrapper_info(s, "src remapping do not match");
+            return;
+        }
+        uint32_t remap_addr_i = s->regs.remap[ACCESS_INSN][slot].remap_addr;
+        uint32_t remap_addr_d = s->regs.remap[ACCESS_DATA][slot].remap_addr;
+        if (remap_addr_i != remap_addr_d) {
+            /* I and D do not match, do nothing */
+            xtrace_ot_ibex_wrapper_info(s, "dst remapping do not match");
+            return;
+        }
+        /* enable */
+        uint32_t map_size = (-src_match_i & (src_match_i + 1u)) << 1u;
+        uint32_t map_mask = ~(map_size - 1u);
+        uint32_t src_base = src_match_i & map_mask;
+        uint32_t dst_base = remap_addr_i & map_mask;
+
+        ot_ibex_wrapper_remapper_destroy(s, slot);
+        ot_ibex_wrapper_remapper_create(s, slot, (hwaddr)dst_base,
+                                        (hwaddr)src_base, (size_t)map_size);
+    }
+}
+
+static void ot_ibex_wrapper_update_remap_vmap(
+    OtIbexWrapperState *s, OtIbexRemapAccess access, unsigned slot)
+
+{
+    g_assert(slot < s->num_regions);
+    g_assert(s->vmapper);
+    g_assert(access < ACCESS_COUNT);
+
+    bool enable = s->regs.remap[access][slot].addr_en;
+    uint32_t match_addr = s->regs.remap[access][slot].addr_matching;
+    uint32_t remap_addr = s->regs.remap[access][slot].remap_addr;
+
+    uint32_t map_size = (-match_addr & (match_addr + 1u)) << 1u;
+    uint32_t map_mask = ~(map_size - 1u);
+    uint32_t src_base = match_addr & map_mask;
+    uint32_t dst_base = remap_addr & map_mask;
+
+    OtVMapperClass *vc = OT_VMAPPER_GET_CLASS(s->vmapper);
+
+    vc->translate(s->vmapper, access == ACCESS_INSN, slot, src_base, dst_base,
+                  enable ? map_size : 0);
+}
+
+/*
+ * DV logging management
+ */
+
+static bool
+ot_ibex_wrapper_log_load_string(OtIbexWrapperState *s, hwaddr addr, char **str)
+{
+    OtIbexTestLogEngine *eng = s->log_engine;
+
+    /*
+     * Logging needs to access strings that are stored in guest memory.
+     * This function adopts a "best effort" strategy: it may fails to retrieve
+     * a log string argument.
+     */
+    bool res = false;
+    MemoryRegionSection mrs;
+
+    /*
+     * Find the region where the string may reside, using a small size as the
+     * length of the string is not known, and memory_region_find would fail if
+     * look up is performed behing the end of the containing memory region
+     */
+    mrs = memory_region_find(eng->as->root, addr, 4u);
+    MemoryRegion *mr = mrs.mr;
+    if (!mr) {
+        xtrace_ot_ibex_wrapper_error(s, "cannot find mr section");
+        goto end;
+    }
+
+    if (!memory_region_is_ram(mr)) {
+        xtrace_ot_ibex_wrapper_error(s, "invalid mr section");
+        goto end;
+    }
+
+    uintptr_t src = (uintptr_t)memory_region_get_ram_ptr(mr);
+    if (!src) {
+        xtrace_ot_ibex_wrapper_error(s, "cannot get host mem");
+        goto end;
+    }
+    src += mrs.offset_within_region;
+
+    size_t size = int128_getlo(mrs.size) - mrs.offset_within_region;
+    size = MIN(size, 4096u);
+
+    const void *end = memchr((const void *)src, '\0', size);
+    if (!end) {
+        xtrace_ot_ibex_wrapper_error(s, "cannot compute strlen");
+        goto end;
+    }
+    size_t slen = (uintptr_t)end - (uintptr_t)src;
+
+    char *tstr = g_malloc(slen + 1);
+    memcpy(tstr, (const void *)src, slen);
+    tstr[slen] = '\0';
+
+    *str = tstr;
+    res = true;
+
+end:
+    if (mr) {
+        memory_region_unref(mr);
+    }
+    return res;
+}
+
+static bool ot_ibex_wrapper_log_load_fields(OtIbexWrapperState *s, hwaddr addr)
+{
+    OtIbexTestLogEngine *eng = s->log_engine;
+
+    MemoryRegionSection mrs;
+    mrs = memory_region_find(eng->as->root, addr, sizeof(eng->fields));
+
+    MemoryRegion *mr = mrs.mr;
+    bool res = false;
+
+    if (!mr) {
+        xtrace_ot_ibex_wrapper_error(s, "cannot find mr section");
+        goto end;
+    }
+
+    if (!memory_region_is_ram(mr)) {
+        xtrace_ot_ibex_wrapper_error(s, "invalid mr section");
+        goto end;
+    }
+
+    uintptr_t src = (uintptr_t)memory_region_get_ram_ptr(mr);
+    if (!src) {
+        xtrace_ot_ibex_wrapper_error(s, "cannot get host mem");
+        goto end;
+    }
+    src += mrs.offset_within_region;
+
+    memcpy(&eng->fields, (const void *)src, sizeof(eng->fields));
+
+    if (eng->fields.file_name_ptr) {
+        if (!ot_ibex_wrapper_log_load_string(s,
+                                             (uintptr_t)
+                                                 eng->fields.file_name_ptr,
+                                             &eng->filename)) {
+            xtrace_ot_ibex_wrapper_error(s, "cannot get filename");
+            goto end;
+        }
+    }
+
+    if (eng->fields.format_ptr) {
+        if (!ot_ibex_wrapper_log_load_string(s,
+                                             (uintptr_t)eng->fields.format_ptr,
+                                             &eng->format)) {
+            xtrace_ot_ibex_wrapper_error(s, "cannot get format string");
+            goto end;
+        }
+    }
+
+    eng->arg_count = 0;
+    eng->fmtptr = eng->format;
+    if (eng->fields.nargs) {
+        eng->args = g_new0(uintptr_t, eng->fields.nargs);
+        eng->strargs = g_new0(bool, eng->fields.nargs);
+    } else {
+        eng->args = NULL;
+        eng->strargs = NULL;
+    }
+
+    res = true;
+
+end:
+    if (mr) {
+        memory_region_unref(mr);
+    }
+    return res;
+}
+
+static bool ot_ibex_wrapper_log_load_arg(OtIbexWrapperState *s, uint32_t value)
+{
+    OtIbexTestLogEngine *eng = s->log_engine;
+
+    if (!eng->fmtptr) {
+        xtrace_ot_ibex_wrapper_error(s, "invalid fmtptr");
+        return false;
+    }
+
+    bool cont;
+    do {
+        cont = false;
+        eng->fmtptr = strchr(eng->fmtptr, '%');
+        if (!eng->fmtptr) {
+            xtrace_ot_ibex_wrapper_error(s, "cannot find formatter");
+            return false;
+        }
+        eng->fmtptr++;
+        switch (*eng->fmtptr) {
+        case '%':
+            eng->fmtptr++;
+            cont = true;
+            continue;
+        case '\0':
+            xtrace_ot_ibex_wrapper_error(s, "cannot find formatter");
+            return false;
+        case 's':
+            if (!ot_ibex_wrapper_log_load_string(s, (hwaddr)value,
+                                                 (char **)&eng
+                                                     ->args[eng->arg_count])) {
+                xtrace_ot_ibex_wrapper_error(s, "cannot load string arg");
+                /* use a default string, best effort strategy */
+                eng->args[eng->arg_count] = (uintptr_t)&MISSING_LOG_STRING[0];
+            } else {
+                /* string has been dynamically allocated, and should be freed */
+                eng->strargs[eng->arg_count] = true;
+            }
+            break;
+        default:
+            eng->args[eng->arg_count] = (uintptr_t)value;
+            break;
+        }
+    } while (cont);
+
+    eng->arg_count++;
+
+    return true;
+}
+
+static void ot_ibex_wrapper_log_cleanup(OtIbexWrapperState *s)
+{
+    OtIbexTestLogEngine *eng = s->log_engine;
+
+    if (eng->strargs && eng->args) {
+        for (unsigned ix = 0; ix < eng->fields.nargs; ix++) {
+            if (eng->strargs[ix]) {
+                if (eng->args[ix]) {
+                    g_free((void *)eng->args[ix]);
+                }
+            }
+        }
+    }
+    g_free(eng->format);
+    g_free(eng->filename);
+    g_free(eng->strargs);
+    g_free(eng->args);
+    eng->format = NULL;
+    eng->filename = NULL;
+    eng->fmtptr = NULL;
+    eng->strargs = NULL;
+    eng->args = NULL;
+}
+
+static void ot_ibex_wrapper_log_emit(OtIbexWrapperState *s)
+{
+    OtIbexTestLogEngine *eng = s->log_engine;
+
+    const char *level;
+    switch (eng->fields.severity) {
+    case TEST_LOG_SEVERITY_INFO:
+        level = "INFO";
+        break;
+    case TEST_LOG_SEVERITY_WARN:
+        level = "WARN ";
+        break;
+    case TEST_LOG_SEVERITY_ERROR:
+        level = "ERROR ";
+        break;
+    case TEST_LOG_SEVERITY_FATAL:
+        level = "FATAL ";
+        break;
+    default:
+        level = "DEBUG ";
+        break;
+    }
+
+    /* discard the path of the stored file to reduce log message length */
+    const char *basename = eng->filename ? strrchr(eng->filename, '/') : NULL;
+    basename = basename ? basename + 1u : eng->filename;
+
+    char *logfmt = g_strdup_printf("%s %s:%d %s\n", level, basename,
+                                   eng->fields.line, eng->format);
+
+/* hack ahead: use the uintptr_t array as a va_list */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wincompatible-pointer-types"
+    char *logmsg = g_strdup_vprintf(logfmt, (char *)eng->args);
+#pragma GCC diagnostic pop
+
+    if (!qemu_chr_fe_backend_connected(&s->chr)) {
+        qemu_log_mask(LOG_STRACE, "%s", logmsg);
+    } else {
+        qemu_chr_fe_write(&s->chr, (const uint8_t *)logmsg,
+                          (int)strlen(logmsg));
+    }
+
+    g_free(logmsg);
+    g_free(logfmt);
+
+    ot_ibex_wrapper_log_cleanup(s);
+}
+
+static void ot_ibex_wrapper_status_report(OtIbexWrapperState *s, uint32_t value)
+{
+    const char *msg;
+    switch (value) {
+    case TEST_STATUS_IN_BOOT_ROM:
+        msg = "IN_BOOT_ROM";
+        break;
+    case TEST_STATUS_IN_BOOT_ROM_HALT:
+        msg = "IN_BOOT_ROM_HALT";
+        break;
+    case TEST_STATUS_IN_TEST:
+        msg = "IN_TEST";
+        break;
+    case TEST_STATUS_IN_WFI:
+        msg = "IN_BOOT_WFI";
+        break;
+    case TEST_STATUS_PASSED:
+        msg = "PASSED";
+        break;
+    case TEST_STATUS_FAILED:
+        msg = "FAILED";
+        break;
+    default:
+        msg = "UNKNOWN";
+        break;
+    }
+
+    if (!qemu_chr_fe_backend_connected(&s->chr)) {
+        qemu_log_mask(LOG_STRACE, "%s\n", msg);
+    } else {
+        qemu_chr_fe_write(&s->chr, (const uint8_t *)msg, (int)strlen(msg));
+        uint8_t eol[] = { '\n' };
+        qemu_chr_fe_write(&s->chr, eol, (int)sizeof(eol));
+    }
+}
+
+static void ot_ibex_wrapper_log_handle(OtIbexWrapperState *s, uint32_t value)
+{
+    /*
+     * Note about logging:
+     *
+     * For OT DV logging to work, the "fields" should not be placed in the
+     * default linker-discarded sections such as ".logs.fields"
+     * i.e. __attribute__((section(".logs.fields"))) should be removed from
+     * the "LOG()"" macro.
+     */
+    OtIbexTestLogEngine *eng = s->log_engine;
+
+    switch (eng->state) {
+    case TEST_LOG_STATE_IDLE:
+        if (!ot_ibex_wrapper_log_load_fields(s, (hwaddr)value)) {
+            eng->state = TEST_LOG_STATE_ERROR;
+            ot_ibex_wrapper_log_cleanup(s);
+            break;
+        }
+        if (eng->fields.nargs) {
+            eng->state = TEST_LOG_STATE_ARG;
+        } else {
+            ot_ibex_wrapper_log_emit(s);
+            eng->state = TEST_LOG_STATE_IDLE;
+        }
+        break;
+    case TEST_LOG_STATE_ARG:
+        if (!ot_ibex_wrapper_log_load_arg(s, value)) {
+            ot_ibex_wrapper_log_cleanup(s);
+            eng->state = TEST_LOG_STATE_ERROR;
+        }
+        if (eng->arg_count == eng->fields.nargs) {
+            ot_ibex_wrapper_log_emit(s);
+            eng->state = TEST_LOG_STATE_IDLE;
+        }
+        break;
+    case TEST_LOG_STATE_ERROR:
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "Can no longer handle DV log, in error");
+        break;
+    }
+}
+
+/*
+ * vCPU management
+ */
+
+static void ot_ibex_wrapper_update_exec(OtIbexWrapperState *s)
+{
+    /*
+     * "Fetch is only enabled when local fetch enable, lifecycle CPU enable and
+     *  power manager CPU enable are all enabled."
+     */
+    bool enable =
+        ((s->cpu_en_bm & OT_IBEX_CPU_EN_MASK) == OT_IBEX_CPU_EN_MASK) &&
+        !s->esc_rx;
+
+    CPUState *cs = s->cpu;
+    g_assert(cs);
+    trace_ot_ibex_wrapper_update_exec(s->ot_id ?: "", s->cpu_en_bm, s->esc_rx,
+                                      cs->halted, cs->disabled, enable);
+
+    if (enable) {
+        cs->halted = 0;
+        cs->disabled = false;
+        cpu_resume(cs);
+    } else {
+        cs->disabled = true;
+        cpu_pause(cs);
+    }
+}
+
+static void ot_ibex_wrapper_cpu_enable_recv(void *opaque, int n, int level)
+{
+    OtIbexWrapperState *s = opaque;
+
+    g_assert((unsigned)n < OT_IBEX_CPU_EN_COUNT);
+
+    bool override = s->lc_ignore && (n == OT_IBEX_LC_CTRL_CPU_EN) && !level;
+    if (override) {
+        level = 1;
+    }
+
+    if (level) {
+        s->cpu_en_bm |= 1u << (unsigned)n;
+    } else {
+        s->cpu_en_bm &= ~(1u << (unsigned)n);
+    }
+
+    /*
+     * "Fetch is only enabled when local fetch enable, lifecycle CPU enable and
+     *  power manager CPU enable are all enabled."
+     */
+    trace_ot_ibex_wrapper_cpu_enable(s->ot_id ?: "",
+                                     n == OT_IBEX_LC_CTRL_CPU_EN ?
+                                         (override ? "LC-override" : "LC") :
+                                         "PWR",
+                                     (bool)level);
+
+    ot_ibex_wrapper_update_exec(s);
+}
+
+static void ot_ibex_wrapper_escalate_rx(void *opaque, int n, int level)
+{
+    OtIbexWrapperState *s = opaque;
+
+    g_assert(n == 0);
+
+    trace_ot_ibex_wrapper_escalate_rx(s->ot_id ?: "", (bool)level);
+
+    s->esc_rx = (bool)level;
+
+    ot_ibex_wrapper_update_exec(s);
+}
+
+/*
+ * I/O
+ */
+
+static uint32_t ot_ibex_wrapper_read_zero(OtIbexWrapperState *s, unsigned reg)
+{
+    (void)s;
+    (void)reg;
+
+    return 0u;
+}
+
+static uint32_t ot_ibex_wrapper_read_reg(OtIbexWrapperState *s, unsigned reg)
+{
+    g_assert(reg < s->reg_count);
+
+    return *s->access_regs[reg];
+}
+
+static uint32_t
+ot_ibex_wrapper_read_rnd_data(OtIbexWrapperState *s, unsigned reg)
+{
+    (void)reg;
+
+    if (!ot_ibex_wrapper_has_edn(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: No EDN connection\n", __func__);
+        return 0;
+    }
+
+    uint32_t value = s->regs.rnd_data;
+    if (!(s->regs.rnd_status & RND_STATUS_RND_DATA_VALID_MASK)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Read invalid entropy data 0x%08x\n",
+                      __func__, value);
+    }
+    s->regs.rnd_data = 0;
+    s->regs.rnd_status = 0;
+
+    ot_ibex_wrapper_request_entropy(s);
+
+    return value;
+}
+
+static uint32_t
+ot_ibex_wrapper_read_rnd_status(OtIbexWrapperState *s, unsigned reg)
+{
+    (void)reg;
+
+    if (!ot_ibex_wrapper_has_edn(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: No EDN connection\n", __func__);
+        return 0;
+    }
+
+    if (!(s->regs.rnd_status & RND_STATUS_RND_DATA_VALID_MASK)) {
+        ot_ibex_wrapper_request_entropy(s);
+    }
+
+    return s->regs.rnd_status;
+}
+
+static void ot_ibex_wrapper_write_reg(OtIbexWrapperState *s, unsigned reg,
+                                      uint32_t value)
+{
+    *s->access_regs[reg] = value;
+}
+
+static void ot_ibex_wrapper_write_ro(OtIbexWrapperState *s, unsigned reg,
+                                     uint32_t value)
+{
+    (void)value;
+
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s is a R/O register\n", __func__,
+                  s->ot_id, REG_NAME(s, reg));
+}
+
+static void ot_ibex_wrapper_write_alert_test(OtIbexWrapperState *s,
+                                             unsigned reg, uint32_t value)
+{
+    (void)reg;
+
+    s->regs.alert_test = value;
+    ot_ibex_wrapper_update_alerts(s);
+    s->regs.alert_test = 0u;
+    ot_ibex_wrapper_update_alerts(s);
+}
+
+static void ot_ibex_wrapper_write_sw_recov_err(OtIbexWrapperState *s,
+                                               unsigned reg, uint32_t value)
+{
+    (void)reg;
+
+    s->regs.sw_recov_err = value;
+    ot_ibex_wrapper_update_alerts(s);
+    s->regs.sw_recov_err = OT_MULTIBITBOOL4_FALSE;
+    ot_ibex_wrapper_update_alerts(s);
+}
+
+static void ot_ibex_wrapper_write_sw_fatal_err(OtIbexWrapperState *s,
+                                               unsigned reg, uint32_t value)
+{
+    (void)reg;
+
+    /* QEMU extenson */
+    if ((value >> 16u) == 0xC0DEu) {
+        /* guest should now use DV_SIM_STATUS register */
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: QEMU exit on SW_FATAL_ERR is deprecated",
+                      __func__, s->ot_id);
+        /* discard MSB magic */
+        value &= UINT16_MAX;
+        /* discard multibool4false mark */
+        value >>= 4u;
+        /* std exit code should be in [0..127] range */
+        if (value > 127u) {
+            value = 127u;
+        }
+        qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_GUEST_SHUTDOWN,
+                                               (int)value);
+    }
+
+    /* real HW */
+    value &= R_SW_FATAL_ERR_VAL_MASK;
+    s->regs.sw_fatal_err =
+        ot_multibitbool_w1s_write(s->regs.sw_fatal_err, value, 4u);
+    ot_ibex_wrapper_update_alerts(s);
+}
+
+static void ot_ibex_wrapper_write_regwen(OtIbexWrapperState *s, unsigned reg,
+                                         uint32_t value)
+{
+    g_assert(reg >= FIRST_REMAP_REG_POS);
+    reg -= FIRST_REMAP_REG_POS;
+    unsigned access = reg / (R32_OFF(sizeof(OtIbexRemap)) * s->num_regions);
+    unsigned group = reg % (R32_OFF(sizeof(OtIbexRemap)) * s->num_regions);
+    unsigned region = group % s->num_regions;
+    g_assert(access < ACCESS_COUNT);
+    g_assert(region < s->num_regions);
+
+    s->regs.remap[access][region].regwen &= value; /* RW0C */
+}
+
+static void
+ot_ibex_wrapper_write_remap(OtIbexWrapperState *s, unsigned reg, uint32_t value)
+{
+    g_assert(reg >= FIRST_REMAP_REG_POS);
+    reg -= FIRST_REMAP_REG_POS;
+    unsigned access = reg / (R32_OFF(sizeof(OtIbexRemap)) * s->num_regions);
+    unsigned group = reg % (R32_OFF(sizeof(OtIbexRemap)) * s->num_regions);
+    unsigned offset = group / s->num_regions;
+    unsigned region = group % s->num_regions;
+    g_assert(access < ACCESS_COUNT);
+
+    if (offset != offsetof(OtIbexRemap, regwen) &&
+        !s->regs.remap[access][region].regwen) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ REGWEN\n",
+                      __func__, s->ot_id, REG_NAME(s, reg));
+        return;
+    }
+
+    switch (offset) {
+    case R32_OFF(offsetof(OtIbexRemap, addr_en)):
+        s->regs.remap[access][region].addr_en = value;
+        break;
+    case R32_OFF(offsetof(OtIbexRemap, addr_matching)):
+        s->regs.remap[access][region].addr_matching = value;
+        break;
+    case R32_OFF(offsetof(OtIbexRemap, remap_addr)):
+        s->regs.remap[access][region].remap_addr = value;
+        break;
+    case R32_OFF(offsetof(OtIbexRemap, regwen)):
+    default:
+        g_assert_not_reached();
+        return;
+    }
+
+    if (s->alias_mode) {
+        ot_ibex_wrapper_update_remap_mr(s, (OtIbexRemapAccess)access, region);
+
+    } else {
+        ot_ibex_wrapper_update_remap_vmap(s, (OtIbexRemapAccess)access, region);
+    }
+}
+
+static void ot_ibex_wrapper_write_nmi_enable(OtIbexWrapperState *s,
+                                             unsigned reg, uint32_t value)
+{
+    (void)reg;
+
+    s->regs.nmi_enable |= value; /* RW1S */
+}
+
+static void ot_ibex_wrapper_write_nmi_state(OtIbexWrapperState *s, unsigned reg,
+                                            uint32_t value)
+{
+    (void)reg;
+
+    qemu_log_mask(LOG_UNIMP, "%s: %s: %s is not supported\n", __func__,
+                  s->ot_id, REG_NAME(s, reg));
+
+    s->regs.nmi_state &= ~value; /* RW1C */
+}
+
+static void ot_ibex_wrapper_write_err_status(OtIbexWrapperState *s,
+                                             unsigned reg, uint32_t value)
+{
+    qemu_log_mask(LOG_UNIMP, "%s: %s: %s is not supported\n", __func__,
+                  s->ot_id, REG_NAME(s, reg));
+
+    s->regs.err_status &= ~value; /* RW1C */
+}
+
+static void ot_ibex_wrapper_write_dv_sim_status(OtIbexWrapperState *s,
+                                                unsigned reg, uint32_t value)
+{
+    (void)reg;
+
+    ot_ibex_wrapper_status_report(s, value);
+
+    if (s->dv_sim_status_exit) {
+        switch (value & DV_SIM_STATUS_CODE_MASK) {
+        case TEST_STATUS_PASSED:
+            trace_ot_ibex_wrapper_exit(s->ot_id, "DV SIM success, exiting", 0);
+            qemu_system_shutdown_request_with_code(
+                SHUTDOWN_CAUSE_GUEST_SHUTDOWN, 0);
+            break;
+        case TEST_STATUS_FAILED: {
+            uint32_t info = SHARED_FIELD_EX32(value, DV_SIM_STATUS_INFO);
+            int ret;
+            if (info == 0) {
+                /* no extra info */
+                ret = 1;
+            } else {
+                ret = (int)(info & 0x7fu);
+            }
+            trace_ot_ibex_wrapper_exit(s->ot_id, "DV SIM failure, exiting",
+                                       ret);
+            qemu_system_shutdown_request_with_code(
+                SHUTDOWN_CAUSE_GUEST_SHUTDOWN, ret);
+            break;
+        }
+        default:
+            break;
+        }
+    } else {
+        trace_ot_ibex_wrapper_exit(s->ot_id,
+                                   "dv-sim-status-exit disabled, not exiting",
+                                   0);
+    }
+
+    s->regs.dv_sim_win[DV_SIM_STATUS] = value;
+}
+
+static void ot_ibex_wrapper_write_dv_sim_log(OtIbexWrapperState *s,
+                                             unsigned reg, uint32_t value)
+{
+    g_assert(reg < s->reg_count);
+    reg -= R32_DYN_POS(s, dv_sim_win[0]);
+    g_assert(reg < ARRAY_SIZE(((OtIbexWrapperRegs *)0)->dv_sim_win));
+    /* NOLINTNEXTLINE */
+    switch (reg) {
+    case 0u:
+        ot_ibex_wrapper_log_handle(s, value);
+        break;
+    default:
+        s->regs.dv_sim_win[reg] = value;
+        break;
+    }
+}
+
+static uint64_t
+ot_ibex_wrapper_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtIbexWrapperState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    if (reg >= s->reg_count) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid register 0x%03x\n",
+                      __func__, s->ot_id, (uint32_t)addr);
+        return 0;
+    }
+
+    g_assert(s->access_table[reg].read);
+    val32 = (*s->access_table[reg].read)(s, reg);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_ibex_wrapper_io_read_out(s->ot_id, (uint32_t)addr,
+                                      REG_NAME(s, reg), val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_ibex_wrapper_regs_write(void *opaque, hwaddr addr,
+                                       uint64_t val64, unsigned size)
+{
+    OtIbexWrapperState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_ibex_wrapper_io_write(s->ot_id, (uint32_t)addr, REG_NAME(s, reg),
+                                   val32, pc);
+
+    if (reg >= s->reg_count) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid register 0x%03x\n",
+                      __func__, s->ot_id, (uint32_t)addr);
+        return;
+    }
+
+    val32 &= s->access_table[reg].mask;
+
+    g_assert(s->access_table[reg].write);
+    (*s->access_table[reg].write)(s, reg, val32);
+};
+
+static void ot_ibex_wrapper_fill_tables(OtIbexWrapperState *s)
+{
+    uint32_t *regs;
+
+    CREATE_NAME_REG(s, ALERT_TEST);
+    CREATE_NAME_REG(s, SW_RECOV_ERR);
+    CREATE_NAME_REG(s, SW_FATAL_ERR);
+
+    regs = &s->regs.alert_test;
+    unsigned rix;
+    for (rix = 0; rix <= LAST_STATIC_REG_POS; rix++) {
+        /* NOLINTNEXTLINE */
+        s->access_regs[rix] = &regs[rix];
+    }
+
+    for (unsigned aix = 0; aix < ACCESS_COUNT; aix++) {
+        char prefix[6] = " BUS_";
+        prefix[0] = aix ? 'D' : 'I';
+        for (unsigned mix = 0; mix < s->num_regions; mix++) {
+            CREATE_NAME_REG_IX_AT(s, prefix, rix, mix, REGWEN);
+            s->access_regs[rix++] = &s->regs.remap[aix][mix].regwen;
+        }
+        for (unsigned mix = 0; mix < s->num_regions; mix++) {
+            CREATE_NAME_REG_IX_AT(s, prefix, rix, mix, ADDR_EN);
+            s->access_regs[rix++] = &s->regs.remap[aix][mix].addr_en;
+        }
+        for (unsigned mix = 0; mix < s->num_regions; mix++) {
+            CREATE_NAME_REG_IX_AT(s, prefix, rix, mix, ADDR_MATCHING);
+            s->access_regs[rix++] = &s->regs.remap[aix][mix].addr_matching;
+        }
+        for (unsigned mix = 0; mix < s->num_regions; mix++) {
+            CREATE_NAME_REG_IX_AT(s, prefix, rix, mix, REMAP_ADDR);
+            s->access_regs[rix++] = &s->regs.remap[aix][mix].remap_addr;
+        }
+    }
+    g_assert(rix == R32_DYN_POS(s, nmi_enable));
+
+    CREATE_NAME_REG_AT(s, R32_DYN_POS(s, nmi_enable), NMI_ENABLE);
+    CREATE_NAME_REG_AT(s, R32_DYN_POS(s, nmi_state), NMI_STATE);
+    CREATE_NAME_REG_AT(s, R32_DYN_POS(s, err_status), ERR_STATUS);
+    CREATE_NAME_REG_AT(s, R32_DYN_POS(s, rnd_data), RND_DATA);
+    CREATE_NAME_REG_AT(s, R32_DYN_POS(s, rnd_status), RND_STATUS);
+    CREATE_NAME_REG_AT(s, R32_DYN_POS(s, fpga_info), FPGA_INFO);
+    CREATE_NAME_REG_AT(s,
+                       s->remap_reg_count + R32_POS(dv_sim_win[DV_SIM_STATUS]),
+                       DV_SIM_STATUS);
+    CREATE_NAME_REG_AT(s, s->remap_reg_count + R32_POS(dv_sim_win[DV_SIM_LOG]),
+                       DV_SIM_LOG);
+
+    for (unsigned wix = DV_SIM_WIN2; wix <= DV_SIM_WIN7; wix++) {
+        CREATE_NAME_REG_IX_AT(s, "", R32_DYN_POS(s, dv_sim_win[wix]), wix,
+                              DV_SIM_WIN);
+    }
+
+    regs = &s->regs.nmi_enable;
+    while (rix < R32_DYN_POS(s, dv_sim_win[DV_SIM_COUNT])) {
+        s->access_regs[rix++] = regs++;
+    }
+
+    /* assign readers */
+    for (rix = 0; rix < s->reg_count; rix++) {
+        s->access_table[rix].read = &ot_ibex_wrapper_read_reg;
+    }
+
+    s->access_table[R32_DYN_POS(s, rnd_data)].read =
+        &ot_ibex_wrapper_read_rnd_data;
+    s->access_table[R32_DYN_POS(s, rnd_status)].read =
+        &ot_ibex_wrapper_read_rnd_status;
+    s->access_table[R32_DYN_POS(s, dv_sim_win[0u])].read =
+        &ot_ibex_wrapper_read_zero;
+
+    /* assign writers */
+    for (rix = 0; rix < s->reg_count; rix++) {
+        s->access_table[rix].write = &ot_ibex_wrapper_write_reg;
+        s->access_table[rix].mask = UINT32_MAX;
+    }
+
+    s->access_table[R32_DYN_POS(s, alert_test)].write =
+        &ot_ibex_wrapper_write_alert_test;
+    s->access_table[R32_DYN_POS(s, sw_recov_err)].write =
+        &ot_ibex_wrapper_write_sw_recov_err;
+    s->access_table[R32_DYN_POS(s, sw_fatal_err)].write =
+        &ot_ibex_wrapper_write_sw_fatal_err;
+    s->access_table[R32_DYN_POS(s, err_status)].write =
+        &ot_ibex_wrapper_write_err_status;
+    s->access_table[R32_DYN_POS(s, nmi_enable)].write =
+        &ot_ibex_wrapper_write_nmi_enable;
+    s->access_table[R32_DYN_POS(s, nmi_state)].write =
+        &ot_ibex_wrapper_write_nmi_state;
+    s->access_table[R32_DYN_POS(s, rnd_data)].write = &ot_ibex_wrapper_write_ro;
+    s->access_table[R32_DYN_POS(s, rnd_status)].write =
+        &ot_ibex_wrapper_write_ro;
+    s->access_table[R32_DYN_POS(s, fpga_info)].write =
+        &ot_ibex_wrapper_write_ro;
+    s->access_table[R32_DYN_POS(s, dv_sim_win[DV_SIM_STATUS])].write =
+        &ot_ibex_wrapper_write_dv_sim_status;
+    s->access_table[R32_DYN_POS(s, dv_sim_win[DV_SIM_LOG])].write =
+        &ot_ibex_wrapper_write_dv_sim_log;
+
+    s->access_table[R32_DYN_POS(s, alert_test)].mask = ALERT_MASK;
+    s->access_table[R32_DYN_POS(s, sw_recov_err)].mask =
+        R_SW_RECOV_ERR_VAL_MASK;
+    /* this register is extended in QEMU, HW mask is applied in HW handler */
+    s->access_table[R32_DYN_POS(s, sw_fatal_err)].mask = UINT32_MAX;
+    s->access_table[R32_DYN_POS(s, nmi_enable)].mask = NMI_MASK;
+    s->access_table[R32_DYN_POS(s, nmi_state)].mask = NMI_MASK;
+    s->access_table[R32_DYN_POS(s, err_status)].mask = ERR_STATUS_MASK;
+
+    unsigned base = FIRST_REMAP_REG_POS;
+    for (unsigned aix = 0; aix < ACCESS_COUNT; aix++) {
+        for (unsigned mix = 0; mix < s->num_regions; mix++) {
+            s->access_table[base + mix].write = &ot_ibex_wrapper_write_regwen;
+            s->access_table[base + mix].mask = REGWEN_EN_MASK;
+        }
+        base += s->num_regions;
+        for (unsigned mix = 0; mix < s->num_regions; mix++) {
+            s->access_table[base + mix].write = &ot_ibex_wrapper_write_remap;
+            s->access_table[base + mix].mask = UINT32_MAX;
+        }
+        base += s->num_regions;
+        for (unsigned mix = 0; mix < s->num_regions; mix++) {
+            s->access_table[base + mix].write = &ot_ibex_wrapper_write_remap;
+            s->access_table[base + mix].mask = UINT32_MAX;
+        }
+        base += s->num_regions;
+        for (unsigned mix = 0; mix < s->num_regions; mix++) {
+            s->access_table[base + mix].write = &ot_ibex_wrapper_write_remap;
+            s->access_table[base + mix].mask = UINT32_MAX;
+        }
+        base += s->num_regions;
+    }
+
+
+#ifdef PRINT_REGNAMES
+    for (unsigned ix = 0; ix < s->reg_count; ix++) {
+        qemu_log("%s: %s: REG[%2u] = %s\n", __func__, s->ot_id, ix,
+                 REG_NAME(s, ix));
+    }
+#endif
+}
+
+/* all properties are optional */
+static const Property ot_ibex_wrapper_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtIbexWrapperState, ot_id),
+    DEFINE_PROP_LINK("edn", OtIbexWrapperState, edn, TYPE_OT_EDN, OtEDNState *),
+    DEFINE_PROP_LINK("vmapper", OtIbexWrapperState, vmapper, TYPE_OT_VMAPPER,
+                     OtVMapperState *),
+    DEFINE_PROP_UINT8("num-regions", OtIbexWrapperState, num_regions, 0),
+    DEFINE_PROP_UINT8("edn-ep", OtIbexWrapperState, edn_ep, UINT8_MAX),
+    DEFINE_PROP_BOOL("lc-ignore", OtIbexWrapperState, lc_ignore, false),
+    DEFINE_PROP_BOOL("alias-mode", OtIbexWrapperState, alias_mode, false),
+    DEFINE_PROP_BOOL("dv-sim-status-exit", OtIbexWrapperState,
+                     dv_sim_status_exit, true),
+    DEFINE_PROP_UINT8("qemu_version", OtIbexWrapperState, qemu_version, 0),
+    DEFINE_PROP_STRING("lc-ignore-ids", OtIbexWrapperState, lc_ignore_ids),
+    DEFINE_PROP_CHR("logdev", OtIbexWrapperState, chr),
+};
+
+static const MemoryRegionOps ot_ibex_wrapper_regs_ops = {
+    .read = &ot_ibex_wrapper_regs_read,
+    .write = &ot_ibex_wrapper_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_ibex_wrapper_reset_enter(Object *obj, ResetType type)
+{
+    OtIbexWrapperClass *c = OT_IBEX_WRAPPER_GET_CLASS(obj);
+    OtIbexWrapperState *s = OT_IBEX_WRAPPER(obj);
+
+    trace_ot_ibex_wrapper_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    if (s->lc_ignore_ids) {
+        char *ign = g_strdup(s->lc_ignore_ids);
+        char *token = strtok(ign, ",");
+        while (token) {
+            if (!strcmp(token, s->ot_id)) {
+                s->lc_ignore = true;
+            }
+            token = strtok(NULL, ",");
+        }
+        g_free(ign);
+    }
+
+    if (!s->cpu) {
+        CPUState *cpu = ot_common_get_local_cpu(DEVICE(s));
+        if (!cpu) {
+            error_setg(&error_fatal, "Could not find the associated vCPU");
+            g_assert_not_reached();
+        }
+        s->cpu = cpu;
+    }
+
+    for (unsigned slot = 0; slot < (unsigned)s->num_regions; slot++) {
+        ot_ibex_wrapper_remapper_destroy(s, slot);
+    }
+
+    static_assert(offsetof(OtIbexWrapperRegs, remap) ==
+                      sizeof(OtIbexWrapperRegs) -
+                          sizeof(((OtIbexWrapperRegs *)0)->remap),
+                  "Offset of remap field is incorrect");
+    memset(&s->regs, 0, offsetof(OtIbexWrapperRegs, remap));
+    s->regs.sw_recov_err = OT_MULTIBITBOOL4_FALSE;
+    s->regs.sw_fatal_err = OT_MULTIBITBOOL4_FALSE;
+    for (unsigned aix = 0; aix < ACCESS_COUNT; aix++) {
+        for (unsigned rix = 0; rix < (unsigned)s->num_regions; rix++) {
+            s->regs.remap[aix][rix].regwen = 0x1u;
+        }
+    }
+
+    /* 'QMU_' in LE, _ is the QEMU version stored in the MSB */
+    s->regs.fpga_info = 0x00554d51u + (((uint32_t)s->qemu_version) << 24u);
+    s->entropy_requested = false;
+    s->cpu_en_bm = s->lc_ignore ? (1u << OT_IBEX_LC_CTRL_CPU_EN) : 0;
+
+    memset(s->log_engine, 0, sizeof(*s->log_engine));
+}
+
+static void ot_ibex_wrapper_reset_exit(Object *obj, ResetType type)
+{
+    OtIbexWrapperClass *c = OT_IBEX_WRAPPER_GET_CLASS(obj);
+    OtIbexWrapperState *s = OT_IBEX_WRAPPER(obj);
+
+    trace_ot_ibex_wrapper_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    s->log_engine->as = ot_common_get_local_address_space(DEVICE(s));
+
+    /* "Upon reset the data will be invalid with a new EDN request pending." */
+    ot_ibex_wrapper_request_entropy(s);
+}
+
+static void ot_ibex_wrapper_realize(DeviceState *dev, Error **errp)
+{
+    OtIbexWrapperState *s = OT_IBEX_WRAPPER(dev);
+    (void)errp;
+
+    s->sys_mem = ot_common_get_local_address_space(dev)->root;
+    g_assert(s->sys_mem);
+    g_assert(s->ot_id);
+    g_assert(s->num_regions);
+    /* if EDN mode is enabled, EDN endpoint must be set */
+    g_assert(!s->edn || s->edn_ep != UINT8_MAX);
+    /* if legacy alias_mode is disabled, vmapper must be set */
+    g_assert(!s->alias_mode || s->vmapper);
+
+    s->remap_reg_count =
+        s->num_regions * ACCESS_COUNT * sizeof(OtIbexRemap) / sizeof(uint32_t);
+    s->reg_count = offsetof(OtIbexWrapperRegs, dv_sim_win) / sizeof(uint32_t) +
+                   DV_SIM_COUNT + s->remap_reg_count;
+
+    memory_region_init_io(&s->mmio, OBJECT(dev), &ot_ibex_wrapper_regs_ops, s,
+                          TYPE_OT_IBEX_WRAPPER,
+                          s->reg_count * sizeof(uint32_t));
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->remappers = g_new0(MemoryRegion, s->num_regions);
+    s->access_table = g_new0(OtIbexWrapperAccess, s->reg_count);
+    s->access_regs = g_new0(uint32_t *, s->reg_count);
+    s->reg_names = g_new0(char *, s->reg_count);
+    for (unsigned ix = 0; ix < ACCESS_COUNT; ix++) {
+        s->regs.remap[ix] = g_new0(OtIbexRemap, s->num_regions);
+    }
+    char *name_buf = g_new0(char, (size_t)(REG_NAME_LENGTH * s->reg_count));
+    for (unsigned ix = 0; ix < s->reg_count;
+         ix++, name_buf += REG_NAME_LENGTH) {
+        s->reg_names[ix] = name_buf;
+    }
+
+    ot_ibex_wrapper_fill_tables(s);
+}
+
+static void ot_ibex_wrapper_init(Object *obj)
+{
+    OtIbexWrapperState *s = OT_IBEX_WRAPPER(obj);
+
+    for (unsigned ix = 0; ix < NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_ibex_wrapper_cpu_enable_recv,
+                            OT_IBEX_WRAPPER_CPU_EN, OT_IBEX_CPU_EN_COUNT);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_ibex_wrapper_escalate_rx,
+                            OT_ALERT_ESCALATE, 1);
+
+    s->log_engine = g_new0(OtIbexTestLogEngine, 1u);
+}
+
+static void ot_ibex_wrapper_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_ibex_wrapper_realize;
+    device_class_set_props(dc, ot_ibex_wrapper_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtIbexWrapperClass *ic = OT_IBEX_WRAPPER_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_ibex_wrapper_reset_enter, NULL,
+                                       &ot_ibex_wrapper_reset_exit,
+                                       &ic->parent_phases);
+}
+
+static const TypeInfo ot_ibex_wrapper_info = {
+    .name = TYPE_OT_IBEX_WRAPPER,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtIbexWrapperState),
+    .instance_init = &ot_ibex_wrapper_init,
+    .class_size = sizeof(OtIbexWrapperClass),
+    .class_init = &ot_ibex_wrapper_class_init,
+};
+
+static void ot_ibex_wrapper_register_types(void)
+{
+    type_register_static(&ot_ibex_wrapper_info);
+}
+
+type_init(ot_ibex_wrapper_register_types);
diff --git a/hw/opentitan/ot_key_sink.c b/hw/opentitan/ot_key_sink.c
new file mode 100644
index 0000000000000..b26f76e708cd9
--- /dev/null
+++ b/hw/opentitan/ot_key_sink.c
@@ -0,0 +1,42 @@
+/*
+ * QEMU OpenTitan Key Sink interface
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/opentitan/ot_key_sink.h"
+
+static const TypeInfo ot_key_sink_info = {
+    .name = TYPE_OT_KEY_SINK_IF,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(OtKeySinkIfClass),
+};
+
+static void ot_key_sink_register_types(void)
+{
+    type_register_static(&ot_key_sink_info);
+}
+
+type_init(ot_key_sink_register_types);
diff --git a/hw/opentitan/ot_keymgr.c b/hw/opentitan/ot_keymgr.c
new file mode 100644
index 0000000000000..554d5cbb55ccb
--- /dev/null
+++ b/hw/opentitan/ot_keymgr.c
@@ -0,0 +1,2558 @@
+/*
+ * QEMU OpenTitan Key Manager device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Known limitations:
+ *  - Entropy reseeding is not currently supported; the value in the shadowed
+ *    `RESEED_INTERVAL_THRESHOLD` register is ignored.
+ *  - Currently the keymgr is designed without KMAC masking. If KMAC masking
+ *    is enabled, a small amount of logic (KMAC data / key integrity checks)
+ *    needs to be updated to use both key shares correctly.
+ *  - Some faults may not be modelled completely accurately (i.e., untested).
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_aes.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_flash.h"
+#include "hw/opentitan/ot_key_sink.h"
+#include "hw/opentitan/ot_keymgr.h"
+#include "hw/opentitan/ot_kmac.h"
+#include "hw/opentitan/ot_lc_ctrl.h"
+#include "hw/opentitan/ot_otbn.h"
+#include "hw/opentitan/ot_otp_if.h"
+#include "hw/opentitan/ot_prng.h"
+#include "hw/opentitan/ot_rom_ctrl.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+/* properties from keymgr.hjson */
+#define NUM_SALT_REG       8u
+#define NUM_SW_BINDING_REG 8u
+#define NUM_OUTPUT_REG     8u
+
+/* properties from keymgr_pkg.sv */
+#define NUM_CDIS                  2u
+#define NUM_KEY_SHARES            2u
+#define KEYMGR_KEY_WIDTH          256u
+#define KEYMGR_KEY_BYTES          ((KEYMGR_KEY_WIDTH) / 8u)
+#define KEYMGR_SW_BINDING_WIDTH   ((NUM_SW_BINDING_REG) * 32u)
+#define KEYMGR_SALT_WIDTH         ((NUM_SALT_REG) * 32u)
+#define KEYMGR_KEY_VERSION_WIDTH  32u
+#define KEYMGR_HEALTH_STATE_WIDTH 128u
+#define KEYMGR_DEV_ID_WIDTH       256u
+#define KEYMGR_LFSR_WIDTH         64u
+
+#define KEYMGR_SALT_BYTES       ((NUM_SALT_REG) * sizeof(uint32_t))
+#define KEYMGR_SW_BINDING_BYTES ((NUM_SW_BINDING_REG) * sizeof(uint32_t))
+
+/* the largest Advance input data used across all keymgr stages */
+#define KEYMGR_ADV_DATA_BYTES \
+    ((KEYMGR_SW_BINDING_WIDTH + (2 * (KEYMGR_KEY_WIDTH)) + \
+      KEYMGR_DEV_ID_WIDTH + KEYMGR_HEALTH_STATE_WIDTH) / \
+     8u)
+
+#define KEYMGR_ID_DATA_BYTES (KEYMGR_KEY_BYTES)
+
+#define KEYMGR_GEN_DATA_BYTES \
+    ((KEYMGR_KEY_VERSION_WIDTH + KEYMGR_SALT_WIDTH + KEYMGR_KEY_WIDTH * 2u) / \
+     8u)
+
+#define KEYMGR_KDF_BUFFER_WIDTH 1600u
+#define KEYMGR_KDF_BUFFER_BYTES ((KEYMGR_KDF_BUFFER_WIDTH) / 8u)
+#define KEYMGR_SEED_BYTES       (KEYMGR_KEY_BYTES)
+#define _MAX(_a_, _b_)          ((_a_) > (_b_) ? (_a_) : (_b_))
+#define KEYMGR_KEY_SIZE_MAX     _MAX(KEYMGR_KEY_BYTES, OT_OTBN_KEY_SIZE)
+
+/*
+ * The EDN provides words of entropy at a time, so the keymgr needs
+ * to send multiple entropy requests to reseeds its internal LFSR.
+ */
+#define KEYMGR_RESEED_COUNT (KEYMGR_LFSR_WIDTH / (8u * sizeof(uint32_t)))
+
+static_assert(KEYMGR_ADV_DATA_BYTES <= KEYMGR_KDF_BUFFER_BYTES,
+              "KeyMgr ADV data does not fit in KDF buffer");
+static_assert(KEYMGR_ID_DATA_BYTES <= KEYMGR_KDF_BUFFER_BYTES,
+              "KeyMgr ID data does not fit in KDF buffer");
+static_assert(KEYMGR_GEN_DATA_BYTES <= KEYMGR_KDF_BUFFER_BYTES,
+              "KeyMgr GEN data does not fit in KDF buffer");
+static_assert((KEYMGR_KDF_BUFFER_BYTES % OT_KMAC_APP_MSG_BYTES) == 0u,
+              "KeyMgr KDF buffer not a multiple of KMAC message size");
+/* NOLINTBEGIN(misc-redundant-expression) */
+static_assert(KEYMGR_KEY_BYTES == OT_OTP_KEYMGR_SECRET_SIZE,
+              "KeyMgr key size does not match OTP KeyMgr secret size");
+static_assert(KEYMGR_KEY_BYTES == OT_KMAC_KEY_SIZE,
+              "KeyMgr key size does not match KMAC key size");
+/* NOLINTEND(misc-redundant-expression) */
+static_assert(KEYMGR_KEY_SIZE_MAX <= OT_KMAC_APP_DIGEST_BYTES,
+              "KeyMgr key size does not match KMAC digest size");
+
+#define KEYMGR_ENTROPY_WIDTH  (KEYMGR_LFSR_WIDTH / 2u)
+#define KEYMGR_ENTROPY_ROUNDS (KEYMGR_KEY_WIDTH / KEYMGR_ENTROPY_WIDTH)
+
+#define KEYMGR_LFSR_SEED_BYTES ((KEYMGR_LFSR_WIDTH) / 8u)
+
+static_assert(KEYMGR_LFSR_SEED_BYTES <= KEYMGR_SEED_BYTES,
+              "Keymgr LFSR seed is larger than generic KeyMgr seed size");
+
+/* Use a timer with a small delay instead of a BH for reliability */
+#define FSM_TICK_DELAY 200u /* 200 ns */
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(INTR_OP_DONE, 0u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, RECOV_OPERATION_ERR, 0u, 1u)
+    FIELD(ALERT_TEST, FATAL_FAULT_ERR, 1u, 1u)
+REG32(CFG_REGWEN, 0x10u)
+    FIELD(CFG_REGWEN, EN, 0u, 1u)
+REG32(START, 0x14u)
+    FIELD(START, EN, 0u, 1u)
+REG32(CONTROL_SHADOWED, 0x18u)
+    FIELD(CONTROL_SHADOWED, OPERATION, 4u, 3u)
+    FIELD(CONTROL_SHADOWED, CDI_SEL, 7u, 1u)
+    FIELD(CONTROL_SHADOWED, DEST_SEL, 12u, 2u)
+REG32(SIDELOAD_CLEAR, 0x1cu)
+    FIELD(SIDELOAD_CLEAR, VAL, 0u, 3u)
+REG32(RESEED_INTERVAL_REGWEN, 0x20u)
+    FIELD(RESEED_INTERVAL_REGWEN, EN, 0u, 1u)
+REG32(RESEED_INTERVAL_SHADOWED, 0x24u)
+    FIELD(RESEED_INTERVAL_SHADOWED, VAL, 0u, 16u)
+REG32(SW_BINDING_REGWEN, 0x28u)
+    FIELD(SW_BINDING_REGWEN, EN, 0u, 1u)
+REG32(SEALING_SW_BINDING_0, 0x2cu)
+REG32(SEALING_SW_BINDING_1, 0x30u)
+REG32(SEALING_SW_BINDING_2, 0x34u)
+REG32(SEALING_SW_BINDING_3, 0x38u)
+REG32(SEALING_SW_BINDING_4, 0x3cu)
+REG32(SEALING_SW_BINDING_5, 0x40u)
+REG32(SEALING_SW_BINDING_6, 0x44u)
+REG32(SEALING_SW_BINDING_7, 0x48u)
+REG32(ATTEST_SW_BINDING_0, 0x4cu)
+REG32(ATTEST_SW_BINDING_1, 0x50u)
+REG32(ATTEST_SW_BINDING_2, 0x54u)
+REG32(ATTEST_SW_BINDING_3, 0x58u)
+REG32(ATTEST_SW_BINDING_4, 0x5cu)
+REG32(ATTEST_SW_BINDING_5, 0x60u)
+REG32(ATTEST_SW_BINDING_6, 0x64u)
+REG32(ATTEST_SW_BINDING_7, 0x68u)
+REG32(SALT_0, 0x6cu)
+REG32(SALT_1, 0x70u)
+REG32(SALT_2, 0x74u)
+REG32(SALT_3, 0x78u)
+REG32(SALT_4, 0x7cu)
+REG32(SALT_5, 0x80u)
+REG32(SALT_6, 0x84u)
+REG32(SALT_7, 0x88u)
+REG32(KEY_VERSION, 0x8cu)
+REG32(MAX_CREATOR_KEY_VER_REGWEN, 0x90u)
+    FIELD(MAX_CREATOR_KEY_VER_REGWEN, EN, 0u, 1u)
+REG32(MAX_CREATOR_KEY_VER_SHADOWED, 0x94u)
+REG32(MAX_OWNER_INT_KEY_VER_REGWEN, 0x98u)
+    FIELD(MAX_OWNER_INT_KEY_VER_REGWEN, EN, 0u, 1u)
+REG32(MAX_OWNER_INT_KEY_VER_SHADOWED, 0x9cu)
+REG32(MAX_OWNER_KEY_VER_REGWEN, 0xa0u)
+    FIELD(MAX_OWNER_KEY_VER_REGWEN, EN, 0u, 1u)
+REG32(MAX_OWNER_KEY_VER_SHADOWED, 0xa4u)
+REG32(SW_SHARE0_OUTPUT_0, 0xa8u)
+REG32(SW_SHARE0_OUTPUT_1, 0xacu)
+REG32(SW_SHARE0_OUTPUT_2, 0xb0u)
+REG32(SW_SHARE0_OUTPUT_3, 0xb4u)
+REG32(SW_SHARE0_OUTPUT_4, 0xb8u)
+REG32(SW_SHARE0_OUTPUT_5, 0xbcu)
+REG32(SW_SHARE0_OUTPUT_6, 0xc0u)
+REG32(SW_SHARE0_OUTPUT_7, 0xc4u)
+REG32(SW_SHARE1_OUTPUT_0, 0xc8u)
+REG32(SW_SHARE1_OUTPUT_1, 0xccu)
+REG32(SW_SHARE1_OUTPUT_2, 0xd0u)
+REG32(SW_SHARE1_OUTPUT_3, 0xd4u)
+REG32(SW_SHARE1_OUTPUT_4, 0xd8u)
+REG32(SW_SHARE1_OUTPUT_5, 0xdcu)
+REG32(SW_SHARE1_OUTPUT_6, 0xe0u)
+REG32(SW_SHARE1_OUTPUT_7, 0xe4u)
+REG32(WORKING_STATE, 0xe8u)
+    FIELD(WORKING_STATE, STATE, 0u, 3u)
+REG32(OP_STATUS, 0xecu)
+    FIELD(OP_STATUS, STATUS, 0u, 2u)
+REG32(ERR_CODE, 0xf0u)
+    FIELD(ERR_CODE, INVALID_OP, 0u, 1u)
+    FIELD(ERR_CODE, INVALID_KMAC_INPUT, 1u, 1u)
+    FIELD(ERR_CODE, INVALID_SHADOW_UPDATE, 2u, 1u)
+REG32(FAULT_STATUS, 0xf4u)
+    FIELD(FAULT_STATUS, CMD, 0u, 1u)
+    FIELD(FAULT_STATUS, KMAC_FSM, 1u, 1u)
+    FIELD(FAULT_STATUS, KMAC_DONE, 2u, 1u)
+    FIELD(FAULT_STATUS, KMAC_OP, 3u, 1u)
+    FIELD(FAULT_STATUS, KMAC_OUT, 4u, 1u)
+    FIELD(FAULT_STATUS, REGFILE_INTG, 5u, 1u)
+    FIELD(FAULT_STATUS, SHADOW, 6u, 1u)
+    FIELD(FAULT_STATUS, CTRL_FSM_INTG, 7u, 1u)
+    FIELD(FAULT_STATUS, CTRL_FSM_CHK, 8u, 1u)
+    FIELD(FAULT_STATUS, CTRL_FSM_CNT, 9u, 1u)
+    FIELD(FAULT_STATUS, RESEED_CNT, 10u, 1u)
+    FIELD(FAULT_STATUS, SIDE_CTRL_FSM, 11u, 1u)
+    FIELD(FAULT_STATUS, SIDE_CTRL_SEL, 12u, 1u)
+    FIELD(FAULT_STATUS, KEY_ECC, 13u, 1u)
+REG32(DEBUG, 0xf8u)
+    FIELD(DEBUG, INVALID_CREATOR_SEED, 0u, 1u)
+    FIELD(DEBUG, INVALID_OWNER_SEED, 1u, 1u)
+    FIELD(DEBUG, INVALID_DEV_ID, 2u, 1u)
+    FIELD(DEBUG, INVALID_HEALTH_STATE, 3u, 1u)
+    FIELD(DEBUG, INVALID_KEY_VERSION, 4u, 1u)
+    FIELD(DEBUG, INVALID_KEY, 5u, 1u)
+    FIELD(DEBUG, INVALID_DIGEST, 6u, 1u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_DEBUG)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+
+#define INTR_MASK (INTR_OP_DONE_MASK)
+#define ALERT_MASK \
+    (R_ALERT_TEST_RECOV_OPERATION_ERR_MASK | R_ALERT_TEST_FATAL_FAULT_ERR_MASK)
+
+#define R_CONTROL_SHADOWED_MASK \
+    (R_CONTROL_SHADOWED_OPERATION_MASK | R_CONTROL_SHADOWED_CDI_SEL_MASK | \
+     R_CONTROL_SHADOWED_DEST_SEL_MASK)
+
+#define ERR_CODE_MASK \
+    (R_ERR_CODE_INVALID_OP_MASK | R_ERR_CODE_INVALID_KMAC_INPUT_MASK | \
+     R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK)
+
+#define FAULT_STATUS_MASK \
+    (R_FAULT_STATUS_CMD_MASK | R_FAULT_STATUS_KMAC_FSM_MASK | \
+     R_FAULT_STATUS_KMAC_DONE_MASK | R_FAULT_STATUS_KMAC_OP_MASK | \
+     R_FAULT_STATUS_KMAC_OUT_MASK | R_FAULT_STATUS_REGFILE_INTG_MASK | \
+     R_FAULT_STATUS_SHADOW_MASK | R_FAULT_STATUS_CTRL_FSM_INTG_MASK | \
+     R_FAULT_STATUS_CTRL_FSM_CHK_MASK | R_FAULT_STATUS_CTRL_FSM_CNT_MASK | \
+     R_FAULT_STATUS_RESEED_CNT_MASK | R_FAULT_STATUS_SIDE_CTRL_FSM_MASK | \
+     R_FAULT_STATUS_SIDE_CTRL_SEL_MASK | R_FAULT_STATUS_KEY_ECC_MASK)
+
+#define DEBUG_MASK \
+    (R_DEBUG_INVALID_CREATOR_SEED_MASK | R_DEBUG_INVALID_OWNER_SEED_MASK | \
+     R_DEBUG_INVALID_DEV_ID_MASK | R_DEBUG_INVALID_HEALTH_STATE_MASK | \
+     R_DEBUG_INVALID_KEY_VERSION_MASK | R_DEBUG_INVALID_KEY_MASK | \
+     R_DEBUG_INVALID_DIGEST_MASK)
+
+typedef enum {
+    KEYMGR_KEY_SINK_AES,
+    KEYMGR_KEY_SINK_KMAC,
+    KEYMGR_KEY_SINK_OTBN,
+    KEYMGR_KEY_SINK_COUNT
+} OtKeyMgrKeySink;
+
+static_assert(KEYMGR_KEY_SINK_COUNT < 32,
+              "Sideload clear bitmasking logic needs < 32 key sinks");
+
+#define KEY_SINK_OFFSET 1
+
+typedef enum {
+    KEYMGR_STAGE_CREATOR,
+    KEYMGR_STAGE_OWNER_INT,
+    KEYMGR_STAGE_OWNER,
+    KEYMGR_STAGE_DISABLE,
+} OtKeyMgrStage;
+
+/* values for CONTROL_SHADOWED.OPERATION */
+typedef enum {
+    KEYMGR_OP_ADVANCE = 0,
+    KEYMGR_OP_GENERATE_ID = 1,
+    KEYMGR_OP_GENERATE_SW_OUTPUT = 2,
+    KEYMGR_OP_GENERATE_HW_OUTPUT = 3,
+    KEYMGR_OP_DISABLE = 4,
+} OtKeyMgrOperation;
+
+/* values for CONTROL_SHADOWED.DEST_SEL */
+typedef enum {
+    KEYMGR_DEST_SEL_VALUE_NONE = 0,
+    KEYMGR_DEST_SEL_VALUE_AES = KEYMGR_KEY_SINK_AES + KEY_SINK_OFFSET,
+    KEYMGR_DEST_SEL_VALUE_KMAC = KEYMGR_KEY_SINK_KMAC + KEY_SINK_OFFSET,
+    KEYMGR_DEST_SEL_VALUE_OTBN = KEYMGR_KEY_SINK_OTBN + KEY_SINK_OFFSET,
+} OtKeyMgrDestSel;
+
+/* values for CONTROL_SHADOWED.CDI_SEL */
+typedef enum {
+    KEYMGR_CDI_SEALING = 0,
+    KEYMGR_CDI_ATTESTATION = 1,
+} OtKeyMgrCdi;
+
+/* values for SIDELOAD_CLEAR.VAL */
+typedef enum {
+    KEYMGR_SIDELOAD_CLEAR_NONE = 0,
+    KEYMGR_SIDELOAD_CLEAR_AES = KEYMGR_KEY_SINK_AES + KEY_SINK_OFFSET,
+    KEYMGR_SIDELOAD_CLEAR_KMAC = KEYMGR_KEY_SINK_KMAC + KEY_SINK_OFFSET,
+    KEYMGR_SIDELOAD_CLEAR_OTBN = KEYMGR_KEY_SINK_OTBN + KEY_SINK_OFFSET,
+} OtKeyMgrSideloadClear;
+
+/* values for WORKING_STATE.STATE */
+typedef enum {
+    KEYMGR_WORKING_STATE_RESET = 0,
+    KEYMGR_WORKING_STATE_INIT = 1,
+    KEYMGR_WORKING_STATE_CREATOR_ROOT_KEY = 2,
+    KEYMGR_WORKING_STATE_OWNER_INTERMEDIATE_KEY = 3,
+    KEYMGR_WORKING_STATE_OWNER_KEY = 4,
+    KEYMGR_WORKING_STATE_DISABLED = 5,
+    KEYMGR_WORKING_STATE_INVALID = 6,
+} OtKeyMgrWorkingState;
+
+/* value for OP_STATUS.STATUS */
+typedef enum {
+    KEYMGR_OP_STATUS_IDLE = 0,
+    KEYMGR_OP_STATUS_WIP = 1,
+    KEYMGR_OP_STATUS_DONE_SUCCESS = 2,
+    KEYMGR_OP_STATUS_DONE_ERROR = 3,
+} OtKeyMgrOpStatus;
+
+enum {
+    /* clang-format off */
+    ALERT_RECOVERABLE,
+    ALERT_FATAL,
+    ALERT_COUNT
+    /* clang-format on */
+};
+
+enum {
+    KEYMGR_SEED_LFSR,
+    KEYMGR_SEED_REV,
+    KEYMGR_SEED_CREATOR_IDENTITY,
+    KEYMGR_SEED_OWNER_INT_IDENTITY,
+    KEYMGR_SEED_OWNER_IDENTITY,
+    KEYMGR_SEED_SW_OUT,
+    KEYMGR_SEED_HW_OUT,
+    KEYMGR_SEED_AES,
+    KEYMGR_SEED_KMAC,
+    KEYMGR_SEED_OTBN,
+    KEYMGR_SEED_CDI,
+    KEYMGR_SEED_NONE,
+    KEYMGR_SEED_COUNT,
+};
+
+typedef enum {
+    KEYMGR_ST_RESET,
+    KEYMGR_ST_ENTROPY_RESEED,
+    KEYMGR_ST_RANDOM,
+    KEYMGR_ST_ROOT_KEY,
+    KEYMGR_ST_INIT,
+    KEYMGR_ST_CREATOR_ROOT_KEY,
+    KEYMGR_ST_OWNER_INT_KEY,
+    KEYMGR_ST_OWNER_KEY,
+    KEYMGR_ST_DISABLED,
+    KEYMGR_ST_WIPE,
+    KEYMGR_ST_INVALID,
+} OtKeyMgrFSMState;
+
+typedef struct {
+    OtEDNState *device;
+    uint8_t ep;
+    bool connected;
+    bool scheduled;
+} OtKeyMgrEDN;
+
+typedef struct {
+    OtPrngState *state;
+    bool reseed_req;
+    bool reseed_ack;
+    uint8_t reseed_cnt;
+} OtKeyMgrPrng;
+
+typedef struct {
+    uint8_t share0[KEYMGR_KEY_BYTES];
+    uint8_t share1[KEYMGR_KEY_BYTES];
+    bool valid;
+} OtKeyMgrKey;
+
+typedef struct {
+    bool op_req;
+    bool op_ack;
+    bool valid_inputs;
+    OtKeyMgrStage stage;
+    OtKeyMgrCdi adv_cdi_cnt;
+} OtKeyMgrOpState;
+
+typedef struct {
+    uint8_t *data;
+    unsigned offset; /* current read offset (in bytes ) */
+    unsigned length; /* current length (in bytes) */
+} OtKeyMgrKdfBuffer;
+
+typedef struct OtKeyMgrState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ irq;
+    IbexIRQ alerts[ALERT_COUNT];
+    QEMUTimer *fsm_tick_timer;
+    OtKeyMgrKdfBuffer kdf_buf;
+
+    uint32_t regs[REGS_COUNT];
+    OtShadowReg control;
+    OtShadowReg reseed_interval;
+    OtShadowReg max_creator_key_ver;
+    OtShadowReg max_owner_int_key_ver;
+    OtShadowReg max_owner_key_ver;
+    uint8_t *salt;
+    uint8_t *sealing_sw_binding;
+    uint8_t *attest_sw_binding;
+
+    bool enabled;
+    OtKeyMgrFSMState state;
+    OtKeyMgrPrng prng;
+    OtKeyMgrOpState op_state;
+    uint8_t *seeds[KEYMGR_SEED_COUNT];
+
+    /* key states */
+    OtKeyMgrKey *key_states;
+    OtKeyMgrKey *saved_kmac_key; /* store KMAC key & restore when completing */
+
+    /* SW output keys */
+    OtKeyMgrKey *sw_out_key;
+
+    char *hexstr;
+
+    /* properties */
+    char *ot_id;
+    OtKeyMgrEDN edn;
+    OtKMACState *kmac;
+    uint8_t kmac_app;
+    OtFlashState *flash_ctrl;
+    OtLcCtrlState *lc_ctrl;
+    DeviceState *otp_ctrl;
+    OtRomCtrlState *rom_ctrl;
+    DeviceState *key_sinks[KEYMGR_KEY_SINK_COUNT];
+    char *seed_xstrs[KEYMGR_SEED_COUNT];
+    bool use_default_entropy_seed; /* flag to seed PRNG with default seed */
+    bool disable_flash_seed_check; /* disable all-0/1 check for flash seeds */
+} OtKeyMgrState;
+
+struct OtKeyMgrClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static const size_t OT_KEY_MGR_KEY_SINK_SIZES[KEYMGR_KEY_SINK_COUNT] = {
+    [KEYMGR_KEY_SINK_AES] = OT_AES_KEY_SIZE,
+    [KEYMGR_KEY_SINK_KMAC] = OT_KMAC_KEY_SIZE,
+    [KEYMGR_KEY_SINK_OTBN] = OT_OTBN_KEY_SIZE,
+};
+
+/* see kmac_pkg::AppCfg in `kmac_pkg.sv` */
+static const OtKMACAppCfg KMAC_APP_CFG = OT_KMAC_CONFIG(KMAC, 256u, "KMAC", "");
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CFG_REGWEN),
+    REG_NAME_ENTRY(START),
+    REG_NAME_ENTRY(CONTROL_SHADOWED),
+    REG_NAME_ENTRY(SIDELOAD_CLEAR),
+    REG_NAME_ENTRY(RESEED_INTERVAL_REGWEN),
+    REG_NAME_ENTRY(RESEED_INTERVAL_SHADOWED),
+    REG_NAME_ENTRY(SW_BINDING_REGWEN),
+    REG_NAME_ENTRY(SEALING_SW_BINDING_0),
+    REG_NAME_ENTRY(SEALING_SW_BINDING_1),
+    REG_NAME_ENTRY(SEALING_SW_BINDING_2),
+    REG_NAME_ENTRY(SEALING_SW_BINDING_3),
+    REG_NAME_ENTRY(SEALING_SW_BINDING_4),
+    REG_NAME_ENTRY(SEALING_SW_BINDING_5),
+    REG_NAME_ENTRY(SEALING_SW_BINDING_6),
+    REG_NAME_ENTRY(SEALING_SW_BINDING_7),
+    REG_NAME_ENTRY(ATTEST_SW_BINDING_0),
+    REG_NAME_ENTRY(ATTEST_SW_BINDING_1),
+    REG_NAME_ENTRY(ATTEST_SW_BINDING_2),
+    REG_NAME_ENTRY(ATTEST_SW_BINDING_3),
+    REG_NAME_ENTRY(ATTEST_SW_BINDING_4),
+    REG_NAME_ENTRY(ATTEST_SW_BINDING_5),
+    REG_NAME_ENTRY(ATTEST_SW_BINDING_6),
+    REG_NAME_ENTRY(ATTEST_SW_BINDING_7),
+    REG_NAME_ENTRY(SALT_0),
+    REG_NAME_ENTRY(SALT_1),
+    REG_NAME_ENTRY(SALT_2),
+    REG_NAME_ENTRY(SALT_3),
+    REG_NAME_ENTRY(SALT_4),
+    REG_NAME_ENTRY(SALT_5),
+    REG_NAME_ENTRY(SALT_6),
+    REG_NAME_ENTRY(SALT_7),
+    REG_NAME_ENTRY(KEY_VERSION),
+    REG_NAME_ENTRY(MAX_CREATOR_KEY_VER_REGWEN),
+    REG_NAME_ENTRY(MAX_CREATOR_KEY_VER_SHADOWED),
+    REG_NAME_ENTRY(MAX_OWNER_INT_KEY_VER_REGWEN),
+    REG_NAME_ENTRY(MAX_OWNER_INT_KEY_VER_SHADOWED),
+    REG_NAME_ENTRY(MAX_OWNER_KEY_VER_REGWEN),
+    REG_NAME_ENTRY(MAX_OWNER_KEY_VER_SHADOWED),
+    REG_NAME_ENTRY(SW_SHARE0_OUTPUT_0),
+    REG_NAME_ENTRY(SW_SHARE0_OUTPUT_1),
+    REG_NAME_ENTRY(SW_SHARE0_OUTPUT_2),
+    REG_NAME_ENTRY(SW_SHARE0_OUTPUT_3),
+    REG_NAME_ENTRY(SW_SHARE0_OUTPUT_4),
+    REG_NAME_ENTRY(SW_SHARE0_OUTPUT_5),
+    REG_NAME_ENTRY(SW_SHARE0_OUTPUT_6),
+    REG_NAME_ENTRY(SW_SHARE0_OUTPUT_7),
+    REG_NAME_ENTRY(SW_SHARE1_OUTPUT_0),
+    REG_NAME_ENTRY(SW_SHARE1_OUTPUT_1),
+    REG_NAME_ENTRY(SW_SHARE1_OUTPUT_2),
+    REG_NAME_ENTRY(SW_SHARE1_OUTPUT_3),
+    REG_NAME_ENTRY(SW_SHARE1_OUTPUT_4),
+    REG_NAME_ENTRY(SW_SHARE1_OUTPUT_5),
+    REG_NAME_ENTRY(SW_SHARE1_OUTPUT_6),
+    REG_NAME_ENTRY(SW_SHARE1_OUTPUT_7),
+    REG_NAME_ENTRY(WORKING_STATE),
+    REG_NAME_ENTRY(OP_STATUS),
+    REG_NAME_ENTRY(ERR_CODE),
+    REG_NAME_ENTRY(FAULT_STATUS),
+    REG_NAME_ENTRY(DEBUG),
+};
+#undef REG_NAME_ENTRY
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define STAGE_ENTRY(_st_) [KEYMGR_STAGE_##_st_] = stringify(_st_)
+static const char *STAGE_NAMES[] = {
+    STAGE_ENTRY(CREATOR),
+    STAGE_ENTRY(OWNER_INT),
+    STAGE_ENTRY(OWNER),
+    STAGE_ENTRY(DISABLE),
+};
+#undef STAGE_ENTRY
+#define STAGE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(STAGE_NAMES) ? STAGE_NAMES[(_st_)] : "?")
+
+#define CDI_ENTRY(_cd_) [KEYMGR_CDI_##_cd_] = stringify(_cd_)
+static const char *CDI_NAMES[] = {
+    CDI_ENTRY(SEALING),
+    CDI_ENTRY(ATTESTATION),
+};
+#undef CDI_ENTRY
+#define CDI_NAME(_cd_) \
+    (((unsigned)(_cd_)) < ARRAY_SIZE(CDI_NAMES) ? CDI_NAMES[(_cd_)] : "?")
+
+#define OP_ENTRY(_op_) [KEYMGR_OP_##_op_] = stringify(_op_)
+static const char *OP_NAMES[] = {
+    OP_ENTRY(ADVANCE),
+    OP_ENTRY(GENERATE_ID),
+    OP_ENTRY(GENERATE_SW_OUTPUT),
+    OP_ENTRY(GENERATE_HW_OUTPUT),
+    OP_ENTRY(DISABLE),
+};
+#undef OP_ENTRY
+#define OP_NAME(_op_) \
+    (((unsigned)(_op_)) < ARRAY_SIZE(OP_NAMES) ? OP_NAMES[(_op_)] : "?")
+
+#define KEY_SINK_ENTRY(_st_) [KEYMGR_KEY_SINK_##_st_] = stringify(_st_)
+static const char *KEY_SINK_NAMES[] = {
+    KEY_SINK_ENTRY(AES),
+    KEY_SINK_ENTRY(KMAC),
+    KEY_SINK_ENTRY(OTBN),
+};
+#undef KEY_SINK_ENTRY
+#define KEY_SINK_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(KEY_SINK_NAMES) ? \
+         KEY_SINK_NAMES[(_st_)] : \
+         "?")
+
+#define SIDELOAD_CLEAR_ENTRY(_st_) \
+    [KEYMGR_SIDELOAD_CLEAR_##_st_] = stringify(_st_)
+static const char *SIDELOAD_CLEAR_NAMES[] = {
+    SIDELOAD_CLEAR_ENTRY(NONE),
+    SIDELOAD_CLEAR_ENTRY(AES),
+    SIDELOAD_CLEAR_ENTRY(KMAC),
+    SIDELOAD_CLEAR_ENTRY(OTBN),
+};
+#undef SIDELOAD_CLEAR_ENTRY
+#define SIDELOAD_CLEAR_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(SIDELOAD_CLEAR_NAMES) ? \
+         SIDELOAD_CLEAR_NAMES[(_st_)] : \
+         "?")
+
+#define WORKING_STATE_ENTRY(_st_) \
+    [KEYMGR_WORKING_STATE_##_st_] = stringify(_st_)
+static const char *WORKING_STATE_NAMES[] = {
+    WORKING_STATE_ENTRY(RESET),
+    WORKING_STATE_ENTRY(INIT),
+    WORKING_STATE_ENTRY(CREATOR_ROOT_KEY),
+    WORKING_STATE_ENTRY(OWNER_INTERMEDIATE_KEY),
+    WORKING_STATE_ENTRY(OWNER_KEY),
+    WORKING_STATE_ENTRY(DISABLED),
+    WORKING_STATE_ENTRY(INVALID),
+};
+#undef WORKING_STATE_ENTRY
+#define WORKING_STATE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(WORKING_STATE_NAMES) ? \
+         WORKING_STATE_NAMES[(_st_)] : \
+         "?")
+
+#define OP_STATUS_ENTRY(_st_) [KEYMGR_OP_STATUS_##_st_] = stringify(_st_)
+static const char *OP_STATUS_NAMES[] = {
+    OP_STATUS_ENTRY(IDLE),
+    OP_STATUS_ENTRY(WIP),
+    OP_STATUS_ENTRY(DONE_SUCCESS),
+    OP_STATUS_ENTRY(DONE_ERROR),
+};
+#undef OP_STATUS_ENTRY
+#define OP_STATUS_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(OP_STATUS_NAMES) ? \
+         OP_STATUS_NAMES[(_st_)] : \
+         "?")
+
+#define FST_ENTRY(_st_) [KEYMGR_ST_##_st_] = stringify(_st_)
+static const char *FST_NAMES[] = {
+    /* clang-format off */
+    FST_ENTRY(RESET),
+    FST_ENTRY(ENTROPY_RESEED),
+    FST_ENTRY(RANDOM),
+    FST_ENTRY(ROOT_KEY),
+    FST_ENTRY(INIT),
+    FST_ENTRY(CREATOR_ROOT_KEY),
+    FST_ENTRY(OWNER_INT_KEY),
+    FST_ENTRY(OWNER_KEY),
+    FST_ENTRY(DISABLED),
+    FST_ENTRY(WIPE),
+    FST_ENTRY(INVALID),
+    /* clang-format on */
+};
+#undef FST_ENTRY
+#define FST_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(FST_NAMES) ? FST_NAMES[(_st_)] : "?")
+
+#define OT_KEYMGR_HEXSTR_SIZE 256u
+
+#define ot_keymgr_dump_bigint(_s_, _b_, _l_) \
+    ot_common_lhexdump(_b_, _l_, true, (_s_)->hexstr, OT_KEYMGR_HEXSTR_SIZE)
+
+static void ot_keymgr_dump_kdf_buf(const OtKeyMgrState *s, const char *op)
+{
+    if (trace_event_get_state(TRACE_OT_KEYMGR_DUMP_KDF_BUF)) {
+        size_t msgs = (s->kdf_buf.length + OT_KMAC_APP_MSG_BYTES - 1u) /
+                      OT_KMAC_APP_MSG_BYTES;
+        for (size_t ix = 0u; ix < msgs; ix++) {
+            trace_ot_keymgr_dump_kdf_buf(
+                s->ot_id, op, ix,
+                ot_keymgr_dump_bigint(s,
+                                      &s->kdf_buf
+                                           .data[ix * OT_KMAC_APP_MSG_BYTES],
+                                      OT_KMAC_APP_MSG_BYTES));
+        }
+    }
+}
+
+static void ot_keymgr_update_irq(OtKeyMgrState *s)
+{
+    bool level = (bool)(s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE]);
+    trace_ot_keymgr_irq(s->ot_id, s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE],
+                        level);
+    ibex_irq_set(&s->irq, (int)level);
+}
+
+static void ot_keymgr_update_alerts(OtKeyMgrState *s)
+{
+    uint32_t levels = s->regs[R_ALERT_TEST];
+
+    bool recov_operation = s->regs[R_ERR_CODE] & ERR_CODE_MASK;
+    if (recov_operation) {
+        levels |= 1u << ALERT_RECOVERABLE;
+    }
+
+    bool fatal_fault = s->regs[R_FAULT_STATUS] & FAULT_STATUS_MASK;
+    if (fatal_fault) {
+        levels |= 1u << ALERT_FATAL;
+    }
+
+    for (unsigned ix = 0u; ix < ALERT_COUNT; ix++) {
+        int level = (int)((levels >> ix) & 0x1u);
+        if (level != ibex_irq_get_level(&s->alerts[ix])) {
+            trace_ot_keymgr_update_alert(s->ot_id,
+                                         ibex_irq_get_level(&s->alerts[ix]),
+                                         level);
+        }
+        ibex_irq_set(&s->alerts[ix], level);
+    }
+
+    if (!s->regs[R_ALERT_TEST] && !recov_operation) {
+        return;
+    }
+    /* ALERT_TEST and recoverable error alerts are transient */
+    s->regs[R_ALERT_TEST] = 0u;
+    s->regs[R_FAULT_STATUS] &= ~FAULT_STATUS_MASK;
+    levels = fatal_fault ? (1u << ALERT_FATAL) : 0u;
+
+    for (unsigned ix = 0u; ix < ALERT_COUNT; ix++) {
+        int level = (int)((levels >> ix) & 0x1u);
+        if (level != ibex_irq_get_level(&s->alerts[ix])) {
+            trace_ot_keymgr_update_alert(s->ot_id,
+                                         ibex_irq_get_level(&s->alerts[ix]),
+                                         level);
+        }
+        ibex_irq_set(&s->alerts[ix], level);
+    }
+}
+
+#define ot_keymgr_change_working_state(_s_, _working_state_) \
+    ot_keymgr_xchange_working_state(_s_, _working_state_, __LINE__)
+
+static OtKeyMgrWorkingState ot_keymgr_get_working_state(const OtKeyMgrState *s)
+{
+    uint32_t working_state =
+        FIELD_EX32(s->regs[R_WORKING_STATE], WORKING_STATE, STATE);
+
+    if (working_state <= KEYMGR_WORKING_STATE_INVALID) {
+        return working_state;
+    }
+    return KEYMGR_WORKING_STATE_INVALID;
+}
+
+static void ot_keymgr_xchange_working_state(
+    OtKeyMgrState *s, OtKeyMgrWorkingState working_state, int line)
+{
+    OtKeyMgrWorkingState prev_working_state = ot_keymgr_get_working_state(s);
+
+    if (prev_working_state != working_state) {
+        trace_ot_keymgr_change_working_state(s->ot_id, line,
+                                             WORKING_STATE_NAME(
+                                                 prev_working_state),
+                                             prev_working_state,
+                                             WORKING_STATE_NAME(working_state),
+                                             working_state);
+        s->regs[R_WORKING_STATE] = working_state;
+    }
+}
+
+static OtKeyMgrOpStatus ot_keymgr_get_op_status(const OtKeyMgrState *s)
+{
+    uint32_t op_status = FIELD_EX32(s->regs[R_OP_STATUS], OP_STATUS, STATUS);
+
+    if (op_status <= KEYMGR_OP_STATUS_DONE_ERROR) {
+        return op_status;
+    }
+    g_assert_not_reached();
+}
+
+#define ot_keymgr_change_op_status(_s_, _op_status_) \
+    ot_keymgr_xchange_op_status(_s_, _op_status_, __LINE__)
+
+static void ot_keymgr_xchange_op_status(OtKeyMgrState *s,
+                                        OtKeyMgrOpStatus op_status, int line)
+{
+    OtKeyMgrOpStatus prev_status = ot_keymgr_get_op_status(s);
+    if (prev_status != op_status) {
+        trace_ot_keymgr_change_op_status(s->ot_id, line,
+                                         OP_STATUS_NAME(prev_status),
+                                         prev_status, OP_STATUS_NAME(op_status),
+                                         op_status);
+        s->regs[R_OP_STATUS] =
+            FIELD_DP32(s->regs[R_OP_STATUS], OP_STATUS, STATUS, op_status);
+    }
+}
+
+#define ot_keymgr_schedule_fsm(_s_) \
+    ot_keymgr_xschedule_fsm(_s_, __func__, __LINE__)
+
+static void ot_keymgr_xschedule_fsm(OtKeyMgrState *s, const char *func,
+                                    int line)
+{
+    trace_ot_keymgr_schedule_fsm(s->ot_id, func, line);
+    if (!timer_pending(s->fsm_tick_timer)) {
+        uint64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+        timer_mod(s->fsm_tick_timer, (int64_t)(now + FSM_TICK_DELAY));
+    }
+}
+
+static void ot_keymgr_request_entropy(OtKeyMgrState *s);
+
+static void ot_keymgr_push_entropy(void *opaque, uint32_t bits, bool fips)
+{
+    (void)fips;
+    OtKeyMgrState *s = opaque;
+    OtKeyMgrEDN *edn = &s->edn;
+    OtKeyMgrPrng *prng = &s->prng;
+
+    if (!edn->scheduled) {
+        trace_ot_keymgr_error(s->ot_id, "Unexpected entropy");
+        return;
+    }
+    edn->scheduled = false;
+
+    ot_prng_reseed(prng->state, bits);
+    prng->reseed_cnt++;
+
+    bool reschedule = prng->reseed_cnt < KEYMGR_RESEED_COUNT;
+
+    trace_ot_keymgr_entropy(s->ot_id, prng->reseed_cnt, reschedule);
+
+    if (reschedule) {
+        /* we need more entropy */
+        ot_keymgr_request_entropy(s);
+    } else if (prng->reseed_req) {
+        prng->reseed_ack = true;
+        prng->reseed_cnt = 0u;
+        ot_keymgr_schedule_fsm(s);
+    }
+}
+
+static void ot_keymgr_request_entropy(OtKeyMgrState *s)
+{
+    OtKeyMgrEDN *edn = &s->edn;
+
+    if (!edn->connected) {
+        ot_edn_connect_endpoint(edn->device, edn->ep, &ot_keymgr_push_entropy,
+                                s);
+        edn->connected = true;
+    }
+
+    if (!edn->scheduled && s->prng.reseed_req) {
+        edn->scheduled = true;
+        if (ot_edn_request_entropy(edn->device, edn->ep)) {
+            error_setg(&error_fatal, "%s: %s: keymgr failed to request entropy",
+                       __func__, s->ot_id);
+        }
+    }
+}
+
+/* Returns true if 'data' is not all zeros or all ones */
+static bool ot_keymgr_valid_data_check(const uint8_t *data, size_t len)
+{
+    size_t popcount = 0u;
+    for (unsigned ix = 0u; ix < len; ix++) {
+        popcount += __builtin_popcount(data[ix]);
+    }
+    return (popcount && popcount != (len * BITS_PER_BYTE));
+}
+
+static void ot_keymgr_push_key(
+    OtKeyMgrState *s, OtKeyMgrKeySink key_sink, const uint8_t *key_share0,
+    const uint8_t *key_share1, bool valid, bool sideload_key)
+{
+    g_assert((unsigned)key_sink < KEYMGR_KEY_SINK_COUNT);
+
+    size_t key_size = OT_KEY_MGR_KEY_SINK_SIZES[key_sink];
+    DeviceState *sink = s->key_sinks[key_sink];
+
+    g_assert(sink);
+
+    g_assert(key_share0);
+    g_assert(key_share1);
+
+    /*
+     * Save the latest KMAC sideloading key, as it needs to be restored after
+     * any keymgr operations that load the KMAC KDF key to offload KDF.
+     */
+    if (sideload_key && key_sink == KEYMGR_KEY_SINK_KMAC) {
+        memcpy(s->saved_kmac_key->share0, key_share0, key_size);
+        memcpy(s->saved_kmac_key->share1, key_share1, key_size);
+        s->saved_kmac_key->valid = valid;
+    }
+
+    if (trace_event_get_state(TRACE_OT_KEYMGR_PUSH_KEY)) {
+        if (!key_share0 || !key_share1) {
+            trace_ot_keymgr_push_key(s->ot_id, KEY_SINK_NAME(key_sink),
+                                     sideload_key, valid, "");
+        } else {
+            /* compute the unmasked key for tracing */
+            uint8_t key_value[KEYMGR_KEY_SIZE_MAX];
+            for (unsigned ix = 0u; ix < key_size; ix++) {
+                key_value[ix] = key_share0[ix] ^ key_share1[ix];
+            }
+
+            trace_ot_keymgr_push_key(s->ot_id, KEY_SINK_NAME(key_sink),
+                                     sideload_key, valid,
+                                     ot_keymgr_dump_bigint(s, key_value,
+                                                           key_size));
+        }
+    }
+
+    OtKeySinkIfClass *kc = OT_KEY_SINK_IF_GET_CLASS(sink);
+    OtKeySinkIf *ki = OT_KEY_SINK_IF(sink);
+
+    g_assert(kc->push_key);
+
+    kc->push_key(ki, key_share0, key_share1, key_size, valid);
+}
+
+static void ot_keymgr_push_kdf_key(OtKeyMgrState *s, const uint8_t *key_share0,
+                                   const uint8_t *key_share1, bool valid)
+{
+    trace_ot_keymgr_push_kdf_key(s->ot_id, valid);
+
+    /*
+     * @todo: when KMAC masking is introduced, this should check both key
+     * shares and not just key share 0 for validity.
+     */
+    if (!ot_keymgr_valid_data_check(key_share0, OT_KMAC_KEY_SIZE)) {
+        s->regs[R_DEBUG] |= R_DEBUG_INVALID_KEY_MASK;
+        s->op_state.valid_inputs = false;
+    }
+
+    ot_keymgr_push_key(s, KEYMGR_KEY_SINK_KMAC, key_share0, key_share1, valid,
+                       false);
+}
+
+static void ot_keymgr_wipe_keys(OtKeyMgrState *s, bool key_states,
+                                bool sw_outputs, uint32_t key_sink_bm)
+{
+    trace_ot_keymgr_wipe_keys(s->ot_id, key_states, sw_outputs, key_sink_bm);
+
+    uint8_t sideload_share0[KEYMGR_KEY_SIZE_MAX];
+    uint8_t sideload_share1[KEYMGR_KEY_SIZE_MAX];
+
+    /* all keys (CDIs, shares etc.) are wiped with the same entropy */
+    for (unsigned ix = 0; ix < KEYMGR_KEY_SIZE_MAX; ix += sizeof(uint32_t)) {
+        /* @todo: use reseed_cnt and reseed if > RESEED_INTERVAL_SHADOWED */
+        uint32_t randval = ot_prng_random_u32(s->prng.state);
+
+        if (key_states && ix < KEYMGR_KEY_BYTES) {
+            for (unsigned cdi = 0u; cdi < NUM_CDIS; cdi++) {
+                stl_le_p(&s->key_states[cdi].share0[ix], randval);
+                stl_le_p(&s->key_states[cdi].share1[ix], randval);
+            }
+        }
+
+        if (sw_outputs && ix < KEYMGR_KEY_BYTES) {
+            stl_le_p(&s->sw_out_key->share0[ix], randval);
+            stl_le_p(&s->sw_out_key->share1[ix], randval);
+        }
+
+        if (key_sink_bm) {
+            stl_le_p(&sideload_share0[ix], randval);
+            stl_le_p(&sideload_share1[ix], randval);
+        }
+    }
+
+    for (unsigned ix = 0; key_sink_bm && ix < KEYMGR_KEY_SINK_COUNT; ix++) {
+        uint32_t key_sink_mask = (1u << ix);
+        if (key_sink_bm & key_sink_mask) {
+            key_sink_bm &= ~key_sink_mask;
+            ot_keymgr_push_key(s, (OtKeyMgrKeySink)ix, sideload_share0,
+                               sideload_share1, false, true);
+        }
+    }
+}
+
+static void ot_keymgr_wipe_all_keys(OtKeyMgrState *s)
+{
+    uint32_t all_keys_bm = (1u << KEYMGR_KEY_SINK_COUNT) - 1u;
+    ot_keymgr_wipe_keys(s, true, true, all_keys_bm);
+}
+
+static void ot_keymgr_sideload_clear(OtKeyMgrState *s)
+{
+    int sideload_clear =
+        (int)FIELD_EX32(s->regs[R_SIDELOAD_CLEAR], SIDELOAD_CLEAR, VAL);
+
+    trace_ot_keymgr_sideload_clear(s->ot_id,
+                                   SIDELOAD_CLEAR_NAME(sideload_clear),
+                                   sideload_clear);
+
+    uint32_t sideload_clear_bm;
+    switch (sideload_clear) {
+    case KEYMGR_SIDELOAD_CLEAR_NONE:
+        return;
+    case KEYMGR_SIDELOAD_CLEAR_AES:
+    case KEYMGR_SIDELOAD_CLEAR_OTBN:
+    case KEYMGR_SIDELOAD_CLEAR_KMAC:
+        sideload_clear_bm = 1u << (sideload_clear - KEY_SINK_OFFSET);
+        break;
+    default:
+        /* continuously clear ALL slots if a non-enumerated value is written */
+        sideload_clear_bm = (1u << KEYMGR_KEY_SINK_COUNT) - 1u;
+        break;
+    }
+
+    ot_keymgr_wipe_keys(s, false, false, sideload_clear_bm);
+}
+
+static void ot_keymgr_reset_kdf_buffer(OtKeyMgrState *s)
+{
+    memset(s->kdf_buf.data, 0u, KEYMGR_KDF_BUFFER_BYTES);
+    s->kdf_buf.offset = 0u;
+    s->kdf_buf.length = 0u;
+}
+
+static void ot_keymgr_kdf_push_bytes(OtKeyMgrState *s, const uint8_t *data,
+                                     size_t len)
+{
+    g_assert(s->kdf_buf.length + len <= KEYMGR_KDF_BUFFER_BYTES);
+
+    memcpy(&s->kdf_buf.data[s->kdf_buf.length], data, len);
+    s->kdf_buf.length += len;
+}
+
+static void G_GNUC_PRINTF(4, 5)
+    ot_keymgr_dump_kdf_material(const OtKeyMgrState *s, const uint8_t *buf,
+                                size_t len, const char *fmt, ...)
+{
+    if (trace_event_get_state(TRACE_OT_KEYMGR_DUMP_KDF_MATERIAL)) {
+        va_list args;
+        va_start(args, fmt);
+        char *what = g_strdup_vprintf(fmt, args);
+        va_end(args);
+        const char *hexstr = ot_keymgr_dump_bigint(s, buf, len);
+        trace_ot_keymgr_dump_kdf_material(s->ot_id, what, hexstr);
+        g_free(what);
+    }
+}
+
+static size_t ot_keymgr_kdf_append_rev_seed(OtKeyMgrState *s)
+{
+    ot_keymgr_kdf_push_bytes(s, s->seeds[KEYMGR_SEED_REV], KEYMGR_SEED_BYTES);
+    ot_keymgr_dump_kdf_material(s, s->seeds[KEYMGR_SEED_REV], KEYMGR_SEED_BYTES,
+                                "REV_SEED");
+    return KEYMGR_SEED_BYTES;
+}
+
+static size_t ot_keymgr_kdf_append_rom_digest(OtKeyMgrState *s)
+{
+    uint8_t rom_digest[OT_ROM_DIGEST_BYTES] = { 0u };
+
+    OtRomCtrlClass *rcc = OT_ROM_CTRL_GET_CLASS(s->rom_ctrl);
+    rcc->get_rom_digest(s->rom_ctrl, rom_digest);
+
+    ot_keymgr_kdf_push_bytes(s, rom_digest, OT_ROM_DIGEST_BYTES);
+    if (!ot_keymgr_valid_data_check(rom_digest, OT_ROM_DIGEST_BYTES)) {
+        s->regs[R_DEBUG] |= R_DEBUG_INVALID_DIGEST_MASK;
+        s->op_state.valid_inputs = false;
+    }
+
+    ot_keymgr_dump_kdf_material(s, rom_digest, OT_ROM_DIGEST_BYTES,
+                                "ROM_DIGEST");
+    return OT_ROM_DIGEST_BYTES;
+}
+
+static size_t ot_keymgr_kdf_append_km_div(OtKeyMgrState *s)
+{
+    OtLcCtrlKeyMgrDiv km_div = { 0u };
+
+    OtLcCtrlClass *lc = OT_LC_CTRL_GET_CLASS(s->lc_ctrl);
+    lc->get_keymgr_div(s->lc_ctrl, &km_div);
+
+    ot_keymgr_kdf_push_bytes(s, km_div.data, OT_LC_KEYMGR_DIV_BYTES);
+    if (!ot_keymgr_valid_data_check(km_div.data, OT_LC_KEYMGR_DIV_BYTES)) {
+        s->regs[R_DEBUG] |= R_DEBUG_INVALID_HEALTH_STATE_MASK;
+        s->op_state.valid_inputs = false;
+    }
+
+    ot_keymgr_dump_kdf_material(s, km_div.data, OT_LC_KEYMGR_DIV_BYTES,
+                                "KM_DIV");
+    return OT_LC_KEYMGR_DIV_BYTES;
+}
+
+static size_t ot_keymgr_kdf_append_dev_id(OtKeyMgrState *s)
+{
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+    const OtOTPHWCfg *hw_cfg = oc->get_hw_cfg(oi);
+
+    ot_keymgr_kdf_push_bytes(s, hw_cfg->device_id,
+                             OT_OTP_HWCFG_DEVICE_ID_BYTES);
+    if (!ot_keymgr_valid_data_check(hw_cfg->device_id,
+                                    OT_OTP_HWCFG_DEVICE_ID_BYTES)) {
+        s->regs[R_DEBUG] |= R_DEBUG_INVALID_DEV_ID_MASK;
+        s->op_state.valid_inputs = false;
+    }
+
+    ot_keymgr_dump_kdf_material(s, hw_cfg->device_id,
+                                OT_OTP_HWCFG_DEVICE_ID_BYTES, "DEVICE_ID");
+    return OT_OTP_HWCFG_DEVICE_ID_BYTES;
+}
+
+static size_t
+ot_keymgr_kdf_append_flash_seed(OtKeyMgrState *s, OtFlashKeyMgrSecretType type,
+                                const char *seed_name, uint32_t debug_mask)
+{
+    OtFlashKeyMgrSecret seed = { 0u };
+
+    OtFlashClass *fc = OT_FLASH_GET_CLASS(s->flash_ctrl);
+    fc->get_keymgr_secret(s->flash_ctrl, type, &seed);
+
+    ot_keymgr_kdf_push_bytes(s, seed.secret, OT_FLASH_KEYMGR_SECRET_BYTES);
+    bool data_valid =
+        ot_keymgr_valid_data_check(seed.secret, OT_FLASH_KEYMGR_SECRET_BYTES);
+
+    /*
+     * Unprovisioned flash will not contain valid secrets, and will return all
+     * 1s (failing the validity check) if scrambling/ECCs are disabled. Using
+     * the `disable-flash-seed-check` property allows you to optionally bypass
+     * these errors for unprovisioned environments where flash info page
+     * splicing is not available.
+     */
+    if (!data_valid && s->disable_flash_seed_check) {
+        trace_ot_keymgr_bypass_failure(s->ot_id, seed_name);
+        data_valid = true;
+    }
+    if (!seed.valid || !data_valid) {
+        s->regs[R_DEBUG] |= debug_mask;
+        s->op_state.valid_inputs = false;
+    }
+
+    ot_keymgr_dump_kdf_material(s, seed.secret, OT_FLASH_KEYMGR_SECRET_BYTES,
+                                "%s", seed_name);
+    return OT_FLASH_KEYMGR_SECRET_BYTES;
+}
+
+static size_t ot_keymgr_kdf_append_sw_binding(OtKeyMgrState *s, OtKeyMgrCdi cdi)
+{
+    uint8_t *sw_binding = (cdi == KEYMGR_CDI_SEALING) ? s->sealing_sw_binding :
+                                                        s->attest_sw_binding;
+
+    ot_keymgr_kdf_push_bytes(s, sw_binding, KEYMGR_SW_BINDING_BYTES);
+
+    ot_keymgr_dump_kdf_material(s, sw_binding, KEYMGR_SW_BINDING_BYTES,
+                                "%s_SW_BINDING", CDI_NAME(cdi));
+    return KEYMGR_SW_BINDING_BYTES;
+}
+
+static size_t ot_keymgr_kdf_append_key_seed(
+    OtKeyMgrState *s, const uint8_t *seed, const char *name)
+{
+    ot_keymgr_kdf_push_bytes(s, seed, KEYMGR_SEED_BYTES);
+    ot_keymgr_dump_kdf_material(s, seed, KEYMGR_SEED_BYTES, "%s", name);
+
+    return KEYMGR_SEED_BYTES;
+}
+
+static size_t ot_keymgr_kdf_append_output_seed(OtKeyMgrState *s, bool sw)
+{
+    int seed_idx = sw ? KEYMGR_SEED_SW_OUT : KEYMGR_SEED_HW_OUT;
+    const char *seed_name = sw ? "SW_OUT_KEY_SEED" : "HW_OUT_KEY_SEED";
+    return ot_keymgr_kdf_append_key_seed(s, s->seeds[seed_idx], seed_name);
+}
+
+static size_t
+ot_keymgr_kdf_append_destination_seed(OtKeyMgrState *s, OtKeyMgrDestSel dest)
+{
+    uint8_t *dest_seed;
+    switch (dest) {
+    case KEYMGR_DEST_SEL_VALUE_AES:
+        dest_seed = s->seeds[KEYMGR_SEED_AES];
+        break;
+    case KEYMGR_DEST_SEL_VALUE_KMAC:
+        dest_seed = s->seeds[KEYMGR_SEED_KMAC];
+        break;
+    case KEYMGR_DEST_SEL_VALUE_OTBN:
+        dest_seed = s->seeds[KEYMGR_SEED_OTBN];
+        break;
+    case KEYMGR_DEST_SEL_VALUE_NONE:
+    default:
+        dest_seed = s->seeds[KEYMGR_SEED_NONE];
+        break;
+    }
+    return ot_keymgr_kdf_append_key_seed(s, dest_seed, "DEST_SEED");
+}
+
+static size_t ot_keymgr_kdf_append_salt(OtKeyMgrState *s)
+{
+    ot_keymgr_kdf_push_bytes(s, s->salt, KEYMGR_SALT_BYTES);
+    ot_keymgr_dump_kdf_material(s, s->salt, KEYMGR_SALT_BYTES, "SALT");
+
+    return KEYMGR_SALT_BYTES;
+}
+
+static size_t ot_keymgr_kdf_append_key_version(OtKeyMgrState *s)
+{
+    uint8_t buf[sizeof(uint32_t)];
+    stl_le_p(buf, s->regs[R_KEY_VERSION]);
+    ot_keymgr_kdf_push_bytes(s, buf, sizeof(uint32_t));
+    ot_keymgr_dump_kdf_material(s, buf, sizeof(uint32_t), "KEY_VERSION");
+
+    return sizeof(uint32_t);
+}
+
+static void ot_keymgr_get_root_key(OtKeyMgrState *s, OtOTPKeyMgrSecret *share0,
+                                   OtOTPKeyMgrSecret *share1)
+{
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+    oc->get_keymgr_secret(oi, OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE0,
+                          share0);
+    oc->get_keymgr_secret(oi, OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE1,
+                          share1);
+
+    if (trace_event_get_state(TRACE_OT_KEYMGR_DUMP_CREATOR_ROOT_KEY)) {
+        trace_ot_keymgr_dump_creator_root_key(
+            s->ot_id, 0, share0->valid,
+            ot_keymgr_dump_bigint(s, share0->secret,
+                                  OT_OTP_KEYMGR_SECRET_SIZE));
+        trace_ot_keymgr_dump_creator_root_key(
+            s->ot_id, 1, share1->valid,
+            ot_keymgr_dump_bigint(s, share1->secret,
+                                  OT_OTP_KEYMGR_SECRET_SIZE));
+    }
+}
+
+#define ot_keymgr_change_main_fsm_state(_s_, _op_status_) \
+    ot_keymgr_xchange_main_fsm_state(_s_, _op_status_, __LINE__)
+
+static void ot_keymgr_xchange_main_fsm_state(OtKeyMgrState *s,
+                                             OtKeyMgrFSMState state, int line)
+{
+    if (s->state != state) {
+        trace_ot_keymgr_change_main_fsm_state(s->ot_id, line,
+                                              FST_NAME(s->state), s->state,
+                                              FST_NAME(state), state);
+        s->state = state;
+    }
+}
+
+static void ot_keymgr_send_kmac_req(OtKeyMgrState *s)
+{
+    g_assert(s->kdf_buf.length);
+    g_assert(s->kdf_buf.offset < s->kdf_buf.length);
+
+    unsigned msg_len = s->kdf_buf.length - s->kdf_buf.offset;
+    if (msg_len > OT_KMAC_APP_MSG_BYTES) {
+        msg_len = OT_KMAC_APP_MSG_BYTES;
+    }
+
+    unsigned next_offset = s->kdf_buf.offset + msg_len;
+
+    OtKMACAppReq req = {
+        .last = next_offset == s->kdf_buf.length,
+        .msg_len = msg_len,
+    };
+    memcpy(req.msg_data, &s->kdf_buf.data[s->kdf_buf.offset], msg_len);
+
+    trace_ot_keymgr_kmac_req(s->ot_id, s->kdf_buf.length, s->kdf_buf.offset,
+                             req.msg_len, req.last);
+
+    s->kdf_buf.offset = next_offset;
+
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    kc->app_request(s->kmac, s->kmac_app, &req);
+}
+
+static void ot_keymgr_operation_disable(OtKeyMgrState *s)
+{
+    ot_keymgr_wipe_all_keys(s);
+    ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_DISABLED);
+    s->op_state.op_ack = true;
+    ot_keymgr_schedule_fsm(s);
+}
+
+static void ot_keymgr_operation_advance(OtKeyMgrState *s, OtKeyMgrStage stage,
+                                        OtKeyMgrCdi cdi)
+{
+    trace_ot_keymgr_advance(s->ot_id, STAGE_NAME(stage), (int)stage,
+                            CDI_NAME(cdi), (int)cdi);
+
+    ot_keymgr_reset_kdf_buffer(s);
+
+    size_t expected_kdf_len = 0u;
+
+    switch (stage) {
+    case KEYMGR_STAGE_CREATOR:
+        /* Revision Seed (which is a netlist constant) */
+        expected_kdf_len += ot_keymgr_kdf_append_rev_seed(s);
+
+        /* Rom Digest (from rom_ctrl) */
+        expected_kdf_len += ot_keymgr_kdf_append_rom_digest(s);
+
+        /* KeyManager Diversification (from lc_ctrl) */
+        expected_kdf_len += ot_keymgr_kdf_append_km_div(s);
+
+        /* Device ID (from OTP) */
+        expected_kdf_len += ot_keymgr_kdf_append_dev_id(s);
+        break;
+    case KEYMGR_STAGE_OWNER_INT:
+        /* Creator Seed (from flash) */
+        expected_kdf_len +=
+            ot_keymgr_kdf_append_flash_seed(s, FLASH_KEYMGR_SECRET_CREATOR_SEED,
+                                            "CREATOR_SEED",
+                                            R_DEBUG_INVALID_CREATOR_SEED_MASK);
+        break;
+    case KEYMGR_STAGE_OWNER:
+        /* Owner Seed (from flash) */
+        expected_kdf_len +=
+            ot_keymgr_kdf_append_flash_seed(s, FLASH_KEYMGR_SECRET_OWNER_SEED,
+                                            "OWNER_SEED",
+                                            R_DEBUG_INVALID_OWNER_SEED_MASK);
+        break;
+    case KEYMGR_STAGE_DISABLE:
+        /* you can "advance" from the OwnerRootKey to the `Disabled` state */
+        ot_keymgr_operation_disable(s);
+        return;
+    default:
+        g_assert_not_reached();
+    }
+
+    /* Software Binding (software-provided via {x_SW_BINDING_y registers) */
+    expected_kdf_len += ot_keymgr_kdf_append_sw_binding(s, cdi);
+
+    /* check that we have pushed all expected KDF data */
+    g_assert(s->kdf_buf.length == expected_kdf_len);
+
+    g_assert(s->kdf_buf.length <= KEYMGR_ADV_DATA_BYTES);
+    s->kdf_buf.length = KEYMGR_ADV_DATA_BYTES;
+
+    /* send the current key state to KMAC as the KDF key */
+    g_assert(cdi < NUM_CDIS);
+    OtKeyMgrKey *key_state = &s->key_states[cdi];
+    ot_keymgr_push_kdf_key(s, key_state->share0, key_state->share1,
+                           key_state->valid);
+
+    /* transmit the contents of the KDF buffer to KMAC for computation */
+    ot_keymgr_dump_kdf_buf(s, "adv");
+    ot_keymgr_send_kmac_req(s);
+}
+
+static void
+ot_keymgr_operation_gen_output(OtKeyMgrState *s, OtKeyMgrStage stage, bool sw)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    OtKeyMgrCdi cdi = (OtKeyMgrCdi)FIELD_EX32(ctrl, CONTROL_SHADOWED, CDI_SEL);
+    OtKeyMgrDestSel dest =
+        (OtKeyMgrDestSel)FIELD_EX32(ctrl, CONTROL_SHADOWED, DEST_SEL);
+
+    trace_ot_keymgr_gen_output(s->ot_id, STAGE_NAME(stage), (int)stage,
+                               CDI_NAME(cdi), (int)cdi, (sw ? "sw" : "hw"));
+
+    ot_keymgr_reset_kdf_buffer(s);
+    size_t expected_kdf_len = 0u;
+
+    /* Output Key Seed (SW/HW key) */
+    expected_kdf_len += ot_keymgr_kdf_append_output_seed(s, sw);
+
+    /* Destination Seed (netlist constant i.e. seed)*/
+    expected_kdf_len += ot_keymgr_kdf_append_destination_seed(s, dest);
+
+    /* Salt (from SW, input via the `SALT_x` registers) */
+    expected_kdf_len += ot_keymgr_kdf_append_salt(s);
+
+    /* Key Version (from SW, input via the `KEY_VERSION` register) */
+    expected_kdf_len += ot_keymgr_kdf_append_key_version(s);
+
+    g_assert(s->kdf_buf.length == expected_kdf_len);
+    g_assert(s->kdf_buf.length == KEYMGR_GEN_DATA_BYTES);
+
+    uint32_t max_key_version;
+    switch (stage) {
+    case KEYMGR_STAGE_CREATOR:
+        max_key_version = ot_shadow_reg_peek(&s->max_creator_key_ver);
+        break;
+    case KEYMGR_STAGE_OWNER_INT:
+        max_key_version = ot_shadow_reg_peek(&s->max_owner_int_key_ver);
+        break;
+    case KEYMGR_STAGE_OWNER:
+        max_key_version = ot_shadow_reg_peek(&s->max_owner_key_ver);
+        break;
+    case KEYMGR_STAGE_DISABLE:
+    default:
+        max_key_version = 0;
+    }
+    bool valid_key_version = s->regs[R_KEY_VERSION] <= max_key_version;
+
+    if (!valid_key_version) {
+        /*
+         * Report the error in DEBUG now, but only in ERR_CODE when the KMAC
+         * response has been received.
+         */
+        s->regs[R_DEBUG] |= R_DEBUG_INVALID_KEY_VERSION_MASK;
+        s->op_state.valid_inputs = false;
+    }
+
+    /* send the current key state to KMAC as the KDF key */
+    g_assert(cdi < NUM_CDIS);
+    OtKeyMgrKey *key_state = &s->key_states[cdi];
+    ot_keymgr_push_kdf_key(s, key_state->share0, key_state->share1,
+                           key_state->valid);
+
+    /* transmit the contents of the KDF buffer to KMAC for computation */
+    ot_keymgr_dump_kdf_buf(s, "gen");
+    ot_keymgr_send_kmac_req(s);
+}
+
+static void ot_keymgr_operation_gen_id(OtKeyMgrState *s, OtKeyMgrStage stage)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    OtKeyMgrCdi cdi = (OtKeyMgrCdi)FIELD_EX32(ctrl, CONTROL_SHADOWED, CDI_SEL);
+
+    trace_ot_keymgr_gen_output(s->ot_id, STAGE_NAME(stage), (int)stage,
+                               CDI_NAME(cdi), (int)cdi, "id");
+
+    ot_keymgr_reset_kdf_buffer(s);
+    size_t expected_kdf_len = 0u;
+
+    /* Identity seed (netlist constant i.e. seed)*/
+    const uint8_t *id_seed;
+    switch (stage) {
+    case KEYMGR_STAGE_CREATOR:
+        id_seed = s->seeds[KEYMGR_SEED_CREATOR_IDENTITY];
+        break;
+    case KEYMGR_STAGE_OWNER_INT:
+        id_seed = s->seeds[KEYMGR_SEED_OWNER_INT_IDENTITY];
+        break;
+    case KEYMGR_STAGE_OWNER:
+        id_seed = s->seeds[KEYMGR_SEED_OWNER_IDENTITY];
+        break;
+    case KEYMGR_STAGE_DISABLE:
+    default:
+        g_assert_not_reached();
+    }
+    expected_kdf_len +=
+        ot_keymgr_kdf_append_key_seed(s, id_seed, "IDENTITY_SEED");
+
+    g_assert(s->kdf_buf.length == expected_kdf_len);
+    g_assert(s->kdf_buf.length == KEYMGR_ID_DATA_BYTES);
+
+    /* send the current key state to KMAC as the KDF key */
+    g_assert(cdi < NUM_CDIS);
+    OtKeyMgrKey *key_state = &s->key_states[cdi];
+    ot_keymgr_push_kdf_key(s, key_state->share0, key_state->share1,
+                           key_state->valid);
+
+    /* transmit the contents of the KDF buffer to KMAC for computation */
+    ot_keymgr_dump_kdf_buf(s, "gen_id");
+    ot_keymgr_send_kmac_req(s);
+}
+
+static void ot_keymgr_start_operation(OtKeyMgrState *s)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    int op = (int)FIELD_EX32(ctrl, CONTROL_SHADOWED, OPERATION);
+
+    trace_ot_keymgr_operation(s->ot_id, STAGE_NAME(s->op_state.stage),
+                              OP_NAME(op), op);
+
+    switch (op) {
+    case KEYMGR_OP_ADVANCE:
+        s->op_state.adv_cdi_cnt = (OtKeyMgrCdi)0;
+        ot_keymgr_operation_advance(s, s->op_state.stage,
+                                    s->op_state.adv_cdi_cnt);
+        break;
+    case KEYMGR_OP_GENERATE_ID:
+        ot_keymgr_operation_gen_id(s, s->op_state.stage);
+        break;
+    case KEYMGR_OP_GENERATE_SW_OUTPUT:
+        ot_keymgr_operation_gen_output(s, s->op_state.stage, true);
+        break;
+    case KEYMGR_OP_GENERATE_HW_OUTPUT:
+        ot_keymgr_operation_gen_output(s, s->op_state.stage, false);
+        break;
+    case KEYMGR_OP_DISABLE:
+        ot_keymgr_operation_disable(s);
+        break;
+    default:
+        /* should only be called with a valid operation */
+        g_assert_not_reached();
+    }
+}
+
+static void ot_keymgr_restore_kmac_key(OtKeyMgrState *s)
+{
+    trace_ot_keymgr_restore_kmac_key(s->ot_id);
+
+    /* restore saved KMAC sideload key now that offloaded KDF KMAC is done */
+    ot_keymgr_push_key(s, KEYMGR_KEY_SINK_KMAC, s->saved_kmac_key->share0,
+                       s->saved_kmac_key->share1, s->saved_kmac_key->valid,
+                       true);
+}
+
+static bool
+ot_keymgr_handle_kmac_resp_advance(OtKeyMgrState *s, const OtKMACAppRsp *rsp)
+{
+    unsigned cdi = s->op_state.adv_cdi_cnt;
+
+    g_assert(cdi < NUM_CDIS);
+
+    OtKeyMgrKey *key_state = &s->key_states[cdi];
+    key_state->valid = true;
+    memcpy(key_state->share0, rsp->digest_share0, OT_KMAC_KEY_SIZE);
+    memcpy(key_state->share1, rsp->digest_share1, OT_KMAC_KEY_SIZE);
+
+    /* SW can lock the `SW_BINDING` regs, and HW unlocks after an advance */
+    s->regs[R_SW_BINDING_REGWEN] |= R_SW_BINDING_REGWEN_EN_MASK;
+
+    unsigned next_cdi = cdi + 1;
+    if (next_cdi < NUM_CDIS) {
+        /* when advancing, we must advance all CDIs before completing */
+        s->op_state.adv_cdi_cnt = next_cdi;
+        ot_keymgr_operation_advance(s, s->op_state.stage, next_cdi);
+        return false;
+    }
+
+    /* all CDIs have been advanced, so complete the advance operation */
+    s->op_state.adv_cdi_cnt = 0u;
+
+    /* SW can lock the `SW_BINDING` regs, and HW unlocks after an advance */
+    s->regs[R_SW_BINDING_REGWEN] |= R_SW_BINDING_REGWEN_EN_MASK;
+
+    switch (s->op_state.stage) {
+    case KEYMGR_STAGE_CREATOR:
+        ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_CREATOR_ROOT_KEY);
+        break;
+    case KEYMGR_STAGE_OWNER_INT:
+        ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_OWNER_INT_KEY);
+        break;
+    case KEYMGR_STAGE_OWNER:
+        ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_OWNER_KEY);
+        break;
+    case KEYMGR_STAGE_DISABLE:
+    default:
+        /* should not be advancing to the `disable` state */
+        g_assert_not_reached();
+    }
+
+    return true;
+}
+
+static bool ot_keymgr_handle_kmac_resp_gen_output_hw(OtKeyMgrState *s,
+                                                     const OtKMACAppRsp *rsp)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    OtKeyMgrDestSel dest =
+        (OtKeyMgrDestSel)FIELD_EX32(ctrl, CONTROL_SHADOWED, DEST_SEL);
+
+    switch (dest) {
+    case KEYMGR_DEST_SEL_VALUE_AES:
+    case KEYMGR_DEST_SEL_VALUE_KMAC:
+    case KEYMGR_DEST_SEL_VALUE_OTBN: {
+        OtKeyMgrKeySink key_sink = (OtKeyMgrKeySink)(dest - KEY_SINK_OFFSET);
+        bool key_valid = s->op_state.valid_inputs;
+        ot_keymgr_push_key(s, key_sink, rsp->digest_share0, rsp->digest_share1,
+                           key_valid, true);
+        break;
+    }
+    case KEYMGR_DEST_SEL_VALUE_NONE:
+        break; /* no-op, just ack */
+    default:
+        g_assert_not_reached();
+    }
+
+    return true;
+}
+
+static bool ot_keymgr_handle_kmac_resp_gen_output_sw(OtKeyMgrState *s,
+                                                     const OtKMACAppRsp *rsp)
+{
+    memcpy(s->sw_out_key->share0, rsp->digest_share0, KEYMGR_KEY_BYTES);
+    memcpy(s->sw_out_key->share1, rsp->digest_share1, KEYMGR_KEY_BYTES);
+    s->sw_out_key->valid = s->op_state.valid_inputs;
+
+    return true;
+}
+
+static void
+ot_keymgr_handle_kmac_response(void *opaque, const OtKMACAppRsp *rsp)
+{
+    OtKeyMgrState *s = OT_KEYMGR(opaque);
+
+    if (trace_event_get_state(TRACE_OT_KEYMGR_KMAC_RSP)) {
+        /* if tracing, trace the unmasked KMAC response key */
+        if (rsp->done) {
+            uint8_t key[OT_KMAC_APP_DIGEST_BYTES];
+            for (unsigned ix = 0u; ix < OT_KMAC_APP_DIGEST_BYTES; ix++) {
+                key[ix] = rsp->digest_share0[ix] ^ rsp->digest_share1[ix];
+            }
+            trace_ot_keymgr_kmac_rsp(
+                s->ot_id, true,
+                ot_keymgr_dump_bigint(s, key, OT_KMAC_APP_DIGEST_BYTES));
+        } else {
+            trace_ot_keymgr_kmac_rsp(s->ot_id, false, "");
+        }
+    }
+
+    if (!s->op_state.op_req) {
+        /* KMAC response when we weren't expecting one */
+        s->regs[R_FAULT_STATUS] |= R_FAULT_STATUS_KMAC_DONE_MASK;
+        ot_keymgr_update_alerts(s);
+        ot_keymgr_schedule_fsm(s);
+        return;
+    }
+
+    if (!rsp->done) {
+        /* not the last response from KMAC, send more data */
+        ot_keymgr_send_kmac_req(s);
+        return;
+    }
+
+    if (s->kdf_buf.offset != s->kdf_buf.length) {
+        /* KMAC interface reports done but we did not send the whole KDF buf */
+        s->regs[R_FAULT_STATUS] |= R_FAULT_STATUS_KMAC_DONE_MASK;
+        ot_keymgr_update_alerts(s);
+        ot_keymgr_schedule_fsm(s);
+        return;
+    }
+
+    /* @todo: check share1 as well when KMAC masking is supported */
+    bool share0_valid = ot_keymgr_valid_data_check(rsp->digest_share0,
+                                                   OT_KMAC_APP_DIGEST_BYTES);
+    if (!share0_valid) {
+        /* KMAC returned all 0s or all 1s*/;
+        s->regs[R_FAULT_STATUS] |= R_FAULT_STATUS_KMAC_OUT_MASK;
+        ot_keymgr_update_alerts(s);
+        ot_keymgr_schedule_fsm(s);
+        return;
+    }
+
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    bool op_complete;
+
+    int op = (int)FIELD_EX32(ctrl, CONTROL_SHADOWED, OPERATION);
+    switch (op) {
+    case KEYMGR_OP_ADVANCE:
+        op_complete = ot_keymgr_handle_kmac_resp_advance(s, rsp);
+        break;
+    case KEYMGR_OP_GENERATE_ID:
+        /* the identity output is also placed into the SW share registers */
+    case KEYMGR_OP_GENERATE_SW_OUTPUT:
+        op_complete = ot_keymgr_handle_kmac_resp_gen_output_sw(s, rsp);
+        break;
+    case KEYMGR_OP_GENERATE_HW_OUTPUT:
+        op_complete = ot_keymgr_handle_kmac_resp_gen_output_hw(s, rsp);
+        break;
+    case KEYMGR_OP_DISABLE:
+        /* disabling should not require the KMAC */
+    default:
+        g_assert_not_reached();
+    }
+
+    if (op_complete) {
+        /* reload the sideloaded key into the KMAC key sink */
+        ot_keymgr_restore_kmac_key(s);
+
+        /* complete the operation, and reschedule the FSM */
+        s->op_state.op_ack = true;
+        if (!s->op_state.valid_inputs) {
+            /* now that the operation completed, report any errors */
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_KMAC_INPUT_MASK;
+        }
+        ot_keymgr_schedule_fsm(s);
+    }
+}
+
+static void ot_keymgr_fsm_key_stage(OtKeyMgrState *s, bool supports_generation,
+                                    OtKeyMgrStage advance,
+                                    OtKeyMgrStage generate)
+{
+    bool op_start = s->regs[R_START] & R_START_EN_MASK;
+    bool invalid_state = s->regs[R_FAULT_STATUS] & FAULT_STATUS_MASK;
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+
+    /* check for op errors before enablement & state validity */
+    uint32_t op = FIELD_EX32(ctrl, CONTROL_SHADOWED, OPERATION);
+    bool invalid_op = false;
+    switch (op) {
+    case KEYMGR_OP_GENERATE_ID:
+    case KEYMGR_OP_GENERATE_HW_OUTPUT:
+    case KEYMGR_OP_GENERATE_SW_OUTPUT:
+        if (op_start && !supports_generation) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+            invalid_op = true;
+        }
+        break;
+    default:
+        break;
+    }
+
+    /* wipe if disabled or in an invalid state */
+    if (!s->enabled || invalid_state) {
+        ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_WIPE);
+        return;
+    }
+
+    if (!op_start || s->op_state.op_req || invalid_op) {
+        return; /* no state change if op_start is not set */
+    }
+
+    switch (op) {
+    case KEYMGR_OP_DISABLE:
+        s->op_state.stage = KEYMGR_STAGE_DISABLE;
+        break;
+    case KEYMGR_OP_ADVANCE:
+        s->op_state.stage = advance;
+        break;
+    default:
+        s->op_state.stage = generate;
+    }
+    s->op_state.op_req = true;
+    s->op_state.valid_inputs = true;
+    ot_keymgr_start_operation(s);
+}
+
+/* Tick the main FSM. Returns whether there was any state change this tick. */
+static bool ot_keymgr_main_fsm_tick(OtKeyMgrState *s)
+{
+    /* store current state so we can determine (& return) any state change */
+    OtKeyMgrFSMState state = s->state;
+    bool op_start = s->regs[R_START] & R_START_EN_MASK;
+    bool invalid_state = s->regs[R_FAULT_STATUS] & FAULT_STATUS_MASK;
+    bool init = false;
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+
+    trace_ot_keymgr_main_fsm_tick(s->ot_id, FST_NAME(s->state), s->state);
+
+    switch (s->state) {
+    case KEYMGR_ST_RESET:
+        ot_keymgr_change_working_state(s, KEYMGR_WORKING_STATE_RESET);
+        bool op_advance =
+            FIELD_EX32(ctrl, CONTROL_SHADOWED, OPERATION) == KEYMGR_OP_ADVANCE;
+        bool advance_sel = op_start && op_advance && s->enabled;
+        if (op_start && !advance_sel) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+        }
+
+        if (invalid_state) {
+            ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_WIPE);
+        } else if (advance_sel) {
+            ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_ENTROPY_RESEED);
+        }
+        break;
+    case KEYMGR_ST_ENTROPY_RESEED:
+        ot_keymgr_change_working_state(s, KEYMGR_WORKING_STATE_RESET);
+        /*
+         * The Earlgrey 1.0.0 keymgr does not immediately transition to
+         * ST_INVALID if disabled by the lc_ctrl whilst reseeding entropy.
+         */
+        if (!s->prng.reseed_req) {
+            s->prng.reseed_ack = false;
+            s->prng.reseed_req = true;
+            ot_keymgr_request_entropy(s);
+        } else if (s->prng.reseed_ack) {
+            ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_RANDOM);
+        }
+        break;
+    case KEYMGR_ST_RANDOM:
+        ot_keymgr_change_working_state(s, KEYMGR_WORKING_STATE_RESET);
+        /*
+         * The Earlgrey 1.0.0 keymgr does not immediately transition to
+         * ST_INVALID if disabled by the lc_ctrl whilst reseeding entropy.
+         *
+         * @todo: normally, this state would initialise the key state with
+         * some random entropy for masking of key shares, but we leave these
+         * uninitialised while there is no KMAC masking.
+         */
+        ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_ROOT_KEY);
+        break;
+    case KEYMGR_ST_ROOT_KEY:
+        ot_keymgr_change_working_state(s, KEYMGR_WORKING_STATE_INIT);
+        /* If the keymgr is disabled or the root key is invalid, we must wipe */
+        if (!s->enabled) {
+            ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_WIPE);
+            break;
+        }
+        init = true;
+
+        /* Retrieve Creator Root Key from OTP */
+        OtOTPKeyMgrSecret secret_share0 = { 0u };
+        OtOTPKeyMgrSecret secret_share1 = { 0u };
+        ot_keymgr_get_root_key(s, &secret_share0, &secret_share1);
+
+        if (secret_share0.valid && secret_share1.valid) {
+            memset(s->key_states, 0u, NUM_CDIS * sizeof(OtKeyMgrKey));
+            for (unsigned cdi = 0u; cdi < NUM_CDIS; cdi++) {
+                memcpy(s->key_states[cdi].share0, secret_share0.secret,
+                       OT_OTP_KEYMGR_SECRET_SIZE);
+                memcpy(s->key_states[cdi].share1, secret_share1.secret,
+                       OT_OTP_KEYMGR_SECRET_SIZE);
+                s->key_states[cdi].valid = true;
+            }
+            ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_INIT);
+        } else {
+            ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_WIPE);
+        }
+        break;
+    case KEYMGR_ST_INIT:
+        ot_keymgr_change_working_state(s, KEYMGR_WORKING_STATE_INIT);
+        ot_keymgr_fsm_key_stage(s, false, KEYMGR_STAGE_CREATOR,
+                                KEYMGR_STAGE_DISABLE);
+        break;
+    case KEYMGR_ST_CREATOR_ROOT_KEY:
+        ot_keymgr_change_working_state(s,
+                                       KEYMGR_WORKING_STATE_CREATOR_ROOT_KEY);
+        ot_keymgr_fsm_key_stage(s, true, KEYMGR_STAGE_OWNER_INT,
+                                KEYMGR_STAGE_CREATOR);
+        break;
+    case KEYMGR_ST_OWNER_INT_KEY:
+        ot_keymgr_change_working_state(
+            s, KEYMGR_WORKING_STATE_OWNER_INTERMEDIATE_KEY);
+        ot_keymgr_fsm_key_stage(s, true, KEYMGR_STAGE_OWNER,
+                                KEYMGR_STAGE_OWNER_INT);
+        break;
+    case KEYMGR_ST_OWNER_KEY:
+        ot_keymgr_change_working_state(s, KEYMGR_WORKING_STATE_OWNER_KEY);
+        ot_keymgr_fsm_key_stage(s, true, KEYMGR_STAGE_DISABLE,
+                                KEYMGR_STAGE_OWNER);
+        break;
+    case KEYMGR_ST_DISABLED:
+        ot_keymgr_change_working_state(s, KEYMGR_WORKING_STATE_DISABLED);
+        if (!s->enabled || invalid_state) {
+            ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_WIPE);
+        }
+        break;
+    case KEYMGR_ST_WIPE:
+        /* whilst wiping, keymgr retains the previous working state */
+        ot_keymgr_wipe_all_keys(s);
+        /* see OT keymgr_ctrl.sv RTL: maintain & complete ongoing ops */
+        if (op_start) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+        } else {
+            ot_keymgr_change_main_fsm_state(s, KEYMGR_ST_INVALID);
+        }
+        break;
+    case KEYMGR_ST_INVALID:
+        ot_keymgr_change_working_state(s, KEYMGR_WORKING_STATE_INVALID);
+        if (op_start) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+        }
+        break;
+    default:
+        break;
+    }
+
+    /* update the last requested operation status */
+    bool invalid_op = (bool)(s->regs[R_ERR_CODE] & R_ERR_CODE_INVALID_OP_MASK);
+    bool op_done =
+        s->op_state.op_req ? s->op_state.op_ack : (init || invalid_op);
+    if (op_done) {
+        s->op_state.op_req = false;
+        s->op_state.op_ack = false;
+        s->regs[R_START] &= ~R_START_EN_MASK;
+        if (s->regs[R_ERR_CODE] || s->regs[R_FAULT_STATUS]) {
+            ot_keymgr_update_alerts(s);
+            ot_keymgr_change_op_status(s, KEYMGR_OP_STATUS_DONE_ERROR);
+        } else {
+            ot_keymgr_change_op_status(s, KEYMGR_OP_STATUS_DONE_SUCCESS);
+        }
+        s->regs[R_INTR_STATE] |= INTR_OP_DONE_MASK;
+        ot_keymgr_update_irq(s);
+    } else if (op_start) {
+        ot_keymgr_change_op_status(s, KEYMGR_OP_STATUS_WIP);
+    }
+
+    /* lock CFG_REGWEN when an operation is ongoing */
+    if (s->enabled && op_start) {
+        if (op_done) {
+            s->regs[R_CFG_REGWEN] |= R_CFG_REGWEN_EN_MASK;
+        } else {
+            s->regs[R_CFG_REGWEN] &= ~R_CFG_REGWEN_EN_MASK;
+        }
+    }
+
+    return state != s->state;
+}
+
+static void ot_keymgr_fsm_tick(void *opaque)
+{
+    OtKeyMgrState *s = opaque;
+
+    bool fsm_state_changed = ot_keymgr_main_fsm_tick(s);
+    if (fsm_state_changed) {
+        /* FSM state changed, so schedule an FSM update once more */
+        ot_keymgr_schedule_fsm(s);
+    } else {
+        /* no FSM state change, so go idle and wait for some external event */
+        trace_ot_keymgr_go_idle(s->ot_id);
+    }
+}
+
+static void ot_keymgr_lc_signal(void *opaque, int irq, int level)
+{
+    OtKeyMgrState *s = opaque;
+    bool enable_keymgr = (bool)level;
+
+    g_assert(irq == 0);
+
+    trace_ot_keymgr_lc_signal(s->ot_id, level);
+
+    bool enablement_changed = enable_keymgr ^ s->enabled;
+    if (!enablement_changed) {
+        return;
+    }
+
+    s->enabled = enable_keymgr;
+
+    if (s->enabled) {
+        s->regs[R_CFG_REGWEN] |= R_CFG_REGWEN_EN_MASK;
+    } else {
+        s->regs[R_CFG_REGWEN] &= ~R_CFG_REGWEN_EN_MASK;
+    }
+
+    ot_keymgr_schedule_fsm(s);
+}
+
+#define ot_keymgr_check_reg_write(_s_, _reg_, _regwen_) \
+    ot_keymgr_check_reg_write_func(__func__, _s_, _reg_, _regwen_)
+
+static inline bool ot_keymgr_check_reg_write_func(
+    const char *func, OtKeyMgrState *s, hwaddr reg, hwaddr regwen)
+{
+    if (s->regs[regwen]) {
+        return true;
+    }
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Write to %s protected with %s\n",
+                  func, s->ot_id, REG_NAME(reg), REG_NAME(regwen));
+    return false;
+}
+
+static uint64_t ot_keymgr_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtKeyMgrState *s = opaque;
+    (void)size;
+
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_CFG_REGWEN:
+    case R_START:
+    case R_SIDELOAD_CLEAR:
+    case R_RESEED_INTERVAL_REGWEN:
+    case R_SW_BINDING_REGWEN:
+    case R_KEY_VERSION:
+    case R_MAX_CREATOR_KEY_VER_REGWEN:
+    case R_MAX_OWNER_INT_KEY_VER_REGWEN:
+    case R_MAX_OWNER_KEY_VER_REGWEN:
+    case R_WORKING_STATE:
+    case R_OP_STATUS:
+    case R_ERR_CODE:
+    case R_FAULT_STATUS:
+    case R_DEBUG:
+        val32 = s->regs[reg];
+        break;
+    case R_CONTROL_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->control);
+        break;
+    case R_RESEED_INTERVAL_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->reseed_interval);
+        break;
+    case R_MAX_CREATOR_KEY_VER_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->max_creator_key_ver);
+        break;
+    case R_MAX_OWNER_INT_KEY_VER_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->max_owner_int_key_ver);
+        break;
+    case R_MAX_OWNER_KEY_VER_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->max_owner_key_ver);
+        break;
+    case R_SEALING_SW_BINDING_0:
+    case R_SEALING_SW_BINDING_1:
+    case R_SEALING_SW_BINDING_2:
+    case R_SEALING_SW_BINDING_3:
+    case R_SEALING_SW_BINDING_4:
+    case R_SEALING_SW_BINDING_5:
+    case R_SEALING_SW_BINDING_6:
+    case R_SEALING_SW_BINDING_7: {
+        unsigned offset = (reg - R_SEALING_SW_BINDING_0) * sizeof(uint32_t);
+        val32 = ldl_le_p(&s->sealing_sw_binding[offset]);
+        break;
+    }
+    case R_ATTEST_SW_BINDING_0:
+    case R_ATTEST_SW_BINDING_1:
+    case R_ATTEST_SW_BINDING_2:
+    case R_ATTEST_SW_BINDING_3:
+    case R_ATTEST_SW_BINDING_4:
+    case R_ATTEST_SW_BINDING_5:
+    case R_ATTEST_SW_BINDING_6:
+    case R_ATTEST_SW_BINDING_7: {
+        unsigned offset = (reg - R_ATTEST_SW_BINDING_0) * sizeof(uint32_t);
+        val32 = ldl_le_p(&s->attest_sw_binding[offset]);
+        break;
+    }
+    case R_SALT_0:
+    case R_SALT_1:
+    case R_SALT_2:
+    case R_SALT_3:
+    case R_SALT_4:
+    case R_SALT_5:
+    case R_SALT_6:
+    case R_SALT_7: {
+        unsigned offset = (reg - R_SALT_0) * sizeof(uint32_t);
+        val32 = ldl_le_p(&s->salt[offset]);
+        break;
+    }
+    case R_SW_SHARE0_OUTPUT_0:
+    case R_SW_SHARE0_OUTPUT_1:
+    case R_SW_SHARE0_OUTPUT_2:
+    case R_SW_SHARE0_OUTPUT_3:
+    case R_SW_SHARE0_OUTPUT_4:
+    case R_SW_SHARE0_OUTPUT_5:
+    case R_SW_SHARE0_OUTPUT_6:
+    case R_SW_SHARE0_OUTPUT_7: {
+        unsigned offset = (reg - R_SW_SHARE0_OUTPUT_0) * sizeof(uint32_t);
+        void *ptr = &s->sw_out_key->share0[offset];
+        val32 = ldl_le_p(ptr);
+        stl_le_p(ptr, 0u); /* RC */
+        break;
+    }
+    case R_SW_SHARE1_OUTPUT_0:
+    case R_SW_SHARE1_OUTPUT_1:
+    case R_SW_SHARE1_OUTPUT_2:
+    case R_SW_SHARE1_OUTPUT_3:
+    case R_SW_SHARE1_OUTPUT_4:
+    case R_SW_SHARE1_OUTPUT_5:
+    case R_SW_SHARE1_OUTPUT_6:
+    case R_SW_SHARE1_OUTPUT_7: {
+        unsigned offset = (reg - R_SW_SHARE1_OUTPUT_0) * sizeof(uint32_t);
+        void *ptr = &s->sw_out_key->share1[offset];
+        val32 = ldl_le_p(ptr);
+        stl_le_p(ptr, 0u); /* RC */
+        break;
+    }
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0u;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0u;
+        break;
+    }
+
+    uint64_t pc = ibex_get_current_pc();
+    trace_ot_keymgr_io_read_out(s->ot_id, (unsigned)addr, REG_NAME(reg),
+                                (uint64_t)val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_keymgr_write(void *opaque, hwaddr addr, uint64_t val64,
+                            unsigned size)
+{
+    OtKeyMgrState *s = opaque;
+    (void)size;
+
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint64_t pc = ibex_get_current_pc();
+    trace_ot_keymgr_io_write(s->ot_id, (unsigned)addr, REG_NAME(reg), val64,
+                             pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_keymgr_update_irq(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[reg] = val32;
+        ot_keymgr_update_irq(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] |= val32;
+        ot_keymgr_update_irq(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_MASK;
+        s->regs[reg] |= val32;
+        ot_keymgr_update_alerts(s);
+        break;
+    case R_START:
+        if (!ot_keymgr_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        val32 &= R_START_EN_MASK;
+        s->regs[reg] = val32;
+        ot_keymgr_fsm_tick(s);
+        break;
+    case R_CONTROL_SHADOWED:
+        if (!ot_keymgr_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        val32 &= R_CONTROL_SHADOWED_MASK;
+        switch (ot_shadow_reg_write(&s->control, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK;
+            ot_keymgr_update_alerts(s);
+        }
+        break;
+    case R_SIDELOAD_CLEAR:
+        if (!ot_keymgr_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        val32 &= R_SIDELOAD_CLEAR_VAL_MASK;
+        s->regs[reg] = val32;
+        ot_keymgr_sideload_clear(s);
+        break;
+    case R_RESEED_INTERVAL_REGWEN:
+        val32 &= R_RESEED_INTERVAL_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_RESEED_INTERVAL_SHADOWED:
+        if (!ot_keymgr_check_reg_write(s, reg, R_RESEED_INTERVAL_REGWEN)) {
+            break;
+        }
+        val32 &= R_RESEED_INTERVAL_SHADOWED_VAL_MASK;
+        switch (ot_shadow_reg_write(&s->reseed_interval, val32)) {
+        case OT_SHADOW_REG_STAGED:
+            /* @todo: implement entropy reseeding & better entropy modelling */
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: Entropy reseeding not implemented.\n",
+                          __func__, s->ot_id);
+            break;
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK;
+            ot_keymgr_update_alerts(s);
+        }
+        break;
+    case R_SW_BINDING_REGWEN:
+        val32 &= R_SW_BINDING_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_SEALING_SW_BINDING_0:
+    case R_SEALING_SW_BINDING_1:
+    case R_SEALING_SW_BINDING_2:
+    case R_SEALING_SW_BINDING_3:
+    case R_SEALING_SW_BINDING_4:
+    case R_SEALING_SW_BINDING_5:
+    case R_SEALING_SW_BINDING_6:
+    case R_SEALING_SW_BINDING_7: {
+        if (!ot_keymgr_check_reg_write(s, reg, R_SW_BINDING_REGWEN)) {
+            break;
+        }
+        unsigned offset = (reg - R_SEALING_SW_BINDING_0) * sizeof(uint32_t);
+        stl_le_p(&s->sealing_sw_binding[offset], val32);
+        break;
+    }
+    case R_ATTEST_SW_BINDING_0:
+    case R_ATTEST_SW_BINDING_1:
+    case R_ATTEST_SW_BINDING_2:
+    case R_ATTEST_SW_BINDING_3:
+    case R_ATTEST_SW_BINDING_4:
+    case R_ATTEST_SW_BINDING_5:
+    case R_ATTEST_SW_BINDING_6:
+    case R_ATTEST_SW_BINDING_7: {
+        if (!ot_keymgr_check_reg_write(s, reg, R_SW_BINDING_REGWEN)) {
+            break;
+        }
+        unsigned offset = (reg - R_ATTEST_SW_BINDING_0) * sizeof(uint32_t);
+        stl_le_p(&s->attest_sw_binding[offset], val32);
+        break;
+    }
+    case R_SALT_0:
+    case R_SALT_1:
+    case R_SALT_2:
+    case R_SALT_3:
+    case R_SALT_4:
+    case R_SALT_5:
+    case R_SALT_6:
+    case R_SALT_7: {
+        if (!ot_keymgr_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        unsigned offset = (reg - R_SALT_0) * sizeof(uint32_t);
+        stl_le_p(&s->salt[offset], val32);
+        break;
+    }
+    case R_KEY_VERSION:
+        if (!ot_keymgr_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        s->regs[reg] = val32;
+        break;
+    case R_MAX_CREATOR_KEY_VER_REGWEN:
+        val32 &= R_MAX_CREATOR_KEY_VER_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_MAX_CREATOR_KEY_VER_SHADOWED:
+        if (!ot_keymgr_check_reg_write(s, reg, R_MAX_CREATOR_KEY_VER_REGWEN)) {
+            break;
+        }
+        switch (ot_shadow_reg_write(&s->max_creator_key_ver, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK;
+            ot_keymgr_update_alerts(s);
+        }
+        break;
+    case R_MAX_OWNER_INT_KEY_VER_REGWEN:
+        val32 &= R_MAX_OWNER_INT_KEY_VER_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_MAX_OWNER_INT_KEY_VER_SHADOWED:
+        if (!ot_keymgr_check_reg_write(s, reg,
+                                       R_MAX_OWNER_INT_KEY_VER_REGWEN)) {
+            break;
+        }
+        switch (ot_shadow_reg_write(&s->max_owner_int_key_ver, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK;
+            ot_keymgr_update_alerts(s);
+        }
+        break;
+    case R_MAX_OWNER_KEY_VER_REGWEN:
+        val32 &= R_MAX_OWNER_KEY_VER_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_MAX_OWNER_KEY_VER_SHADOWED:
+        if (!ot_keymgr_check_reg_write(s, reg, R_MAX_OWNER_KEY_VER_REGWEN)) {
+            break;
+        }
+        switch (ot_shadow_reg_write(&s->max_owner_key_ver, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK;
+            ot_keymgr_update_alerts(s);
+        }
+        break;
+    case R_OP_STATUS: {
+        val32 &= R_OP_STATUS_STATUS_MASK;
+        ot_keymgr_change_op_status(s, s->regs[reg] & ~val32); /* RW1C */
+        /* SW write may clear `WIP` here which may be immediately set again */
+        ot_keymgr_fsm_tick(s);
+        break;
+    }
+    case R_ERR_CODE:
+        val32 &= ERR_CODE_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_keymgr_update_alerts(s);
+        break;
+    case R_DEBUG:
+        val32 &= DEBUG_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CFG_REGWEN:
+    case R_WORKING_STATE:
+    case R_SW_SHARE0_OUTPUT_0:
+    case R_SW_SHARE0_OUTPUT_1:
+    case R_SW_SHARE0_OUTPUT_2:
+    case R_SW_SHARE0_OUTPUT_3:
+    case R_SW_SHARE0_OUTPUT_4:
+    case R_SW_SHARE0_OUTPUT_5:
+    case R_SW_SHARE0_OUTPUT_6:
+    case R_SW_SHARE0_OUTPUT_7:
+    case R_SW_SHARE1_OUTPUT_0:
+    case R_SW_SHARE1_OUTPUT_1:
+    case R_SW_SHARE1_OUTPUT_2:
+    case R_SW_SHARE1_OUTPUT_3:
+    case R_SW_SHARE1_OUTPUT_4:
+    case R_SW_SHARE1_OUTPUT_5:
+    case R_SW_SHARE1_OUTPUT_6:
+    case R_SW_SHARE1_OUTPUT_7:
+    case R_FAULT_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x02%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static void ot_keymgr_configure_constants(OtKeyMgrState *s)
+{
+    for (unsigned ix = 0u; ix < KEYMGR_SEED_COUNT; ix++) {
+        if (!s->seed_xstrs[ix]) {
+            trace_ot_keymgr_seed_missing(s->ot_id, ix);
+            continue;
+        }
+
+        size_t len = strlen(s->seed_xstrs[ix]);
+        size_t seed_len_bytes = KEYMGR_SEED_BYTES;
+        /* the LFSR seed constant is smaller than other seed constants */
+        if (ix == KEYMGR_SEED_LFSR) {
+            seed_len_bytes = KEYMGR_LFSR_SEED_BYTES;
+        }
+        if (len != (seed_len_bytes * 2u)) {
+            error_setg(&error_fatal, "%s: %s invalid seed #%u length", __func__,
+                       s->ot_id, ix);
+            continue;
+        }
+
+        if (ot_common_parse_hexa_str(s->seeds[ix], s->seed_xstrs[ix],
+                                     seed_len_bytes, true, true)) {
+            error_setg(&error_fatal, "%s: %s unable to parse seed #%u",
+                       __func__, s->ot_id, ix);
+            continue;
+        }
+    }
+}
+
+static const Property ot_keymgr_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtKeyMgrState, ot_id),
+    DEFINE_PROP_LINK("edn", OtKeyMgrState, edn.device, TYPE_OT_EDN,
+                     OtEDNState *),
+    DEFINE_PROP_UINT8("edn-ep", OtKeyMgrState, edn.ep, UINT8_MAX),
+    DEFINE_PROP_LINK("flash_ctrl", OtKeyMgrState, flash_ctrl, TYPE_OT_FLASH,
+                     OtFlashState *),
+    DEFINE_PROP_LINK("kmac", OtKeyMgrState, kmac, TYPE_OT_KMAC, OtKMACState *),
+    DEFINE_PROP_UINT8("kmac-app", OtKeyMgrState, kmac_app, UINT8_MAX),
+    DEFINE_PROP_LINK("lc-ctrl", OtKeyMgrState, lc_ctrl, TYPE_OT_LC_CTRL,
+                     OtLcCtrlState *),
+    DEFINE_PROP_LINK("otp-ctrl", OtKeyMgrState, otp_ctrl, TYPE_OT_OTP_IF,
+                     DeviceState *),
+    DEFINE_PROP_LINK("rom_ctrl", OtKeyMgrState, rom_ctrl, TYPE_OT_ROM_CTRL,
+                     OtRomCtrlState *),
+    DEFINE_PROP_LINK("aes", OtKeyMgrState, key_sinks[KEYMGR_KEY_SINK_AES],
+                     TYPE_OT_KEY_SINK_IF, DeviceState *),
+    DEFINE_PROP_LINK("otbn", OtKeyMgrState, key_sinks[KEYMGR_KEY_SINK_OTBN],
+                     TYPE_OT_KEY_SINK_IF, DeviceState *),
+    DEFINE_PROP_STRING("lfsr_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_LFSR]),
+    DEFINE_PROP_STRING("revision_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_REV]),
+    DEFINE_PROP_STRING("creator_identity_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_CREATOR_IDENTITY]),
+    DEFINE_PROP_STRING("owner_int_identity_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_OWNER_INT_IDENTITY]),
+    DEFINE_PROP_STRING("owner_identity_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_OWNER_IDENTITY]),
+    DEFINE_PROP_STRING("soft_output_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_SW_OUT]),
+    DEFINE_PROP_STRING("hard_output_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_HW_OUT]),
+    DEFINE_PROP_STRING("aes_seed", OtKeyMgrState, seed_xstrs[KEYMGR_SEED_AES]),
+    DEFINE_PROP_STRING("kmac_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_KMAC]),
+    DEFINE_PROP_STRING("otbn_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_OTBN]),
+    DEFINE_PROP_STRING("cdi_seed", OtKeyMgrState, seed_xstrs[KEYMGR_SEED_CDI]),
+    DEFINE_PROP_STRING("none_seed", OtKeyMgrState,
+                       seed_xstrs[KEYMGR_SEED_NONE]),
+    DEFINE_PROP_BOOL("use-default-entropy-seed", OtKeyMgrState,
+                     use_default_entropy_seed, false),
+    DEFINE_PROP_BOOL("disable-flash-seed-check", OtKeyMgrState,
+                     disable_flash_seed_check, false),
+};
+
+static const MemoryRegionOps ot_keymgr_regs_ops = {
+    .read = &ot_keymgr_read,
+    .write = &ot_keymgr_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_keymgr_reset_enter(Object *obj, ResetType type)
+{
+    OtKeyMgrClass *c = OT_KEYMGR_GET_CLASS(obj);
+    OtKeyMgrState *s = OT_KEYMGR(obj);
+
+    trace_ot_keymgr_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->fsm_tick_timer);
+
+    g_assert(s->edn.device);
+    g_assert(s->edn.ep != UINT8_MAX);
+    g_assert(s->flash_ctrl);
+    g_assert(s->kmac);
+    g_assert(s->kmac_app != UINT8_MAX);
+    g_assert(s->lc_ctrl);
+    g_assert(s->otp_ctrl);
+    g_assert(s->rom_ctrl);
+
+    (void)OBJECT_CHECK(OtOTPIf, s->otp_ctrl, TYPE_OT_OTP_IF);
+
+    /* reset registers */
+    memset(s->regs, 0u, sizeof(s->regs));
+    s->regs[R_CFG_REGWEN] = 0x1u;
+    ot_shadow_reg_init(&s->control, 0x10u);
+    s->regs[R_RESEED_INTERVAL_REGWEN] = 0x1u;
+    ot_shadow_reg_init(&s->reseed_interval, 0x100u);
+    s->regs[R_SW_BINDING_REGWEN] = 0x1u;
+    s->regs[R_MAX_CREATOR_KEY_VER_REGWEN] = 0x1u;
+    ot_shadow_reg_init(&s->max_creator_key_ver, 0x0u);
+    s->regs[R_MAX_OWNER_INT_KEY_VER_REGWEN] = 0x1u;
+    ot_shadow_reg_init(&s->max_owner_int_key_ver, 0x1u);
+    s->regs[R_MAX_OWNER_KEY_VER_REGWEN] = 0x1u;
+    ot_shadow_reg_init(&s->max_owner_key_ver, 0x0u);
+    memset(s->salt, 0u, KEYMGR_SALT_BYTES);
+    memset(s->sealing_sw_binding, 0u, KEYMGR_SW_BINDING_BYTES);
+    memset(s->attest_sw_binding, 0u, KEYMGR_SW_BINDING_BYTES);
+
+    /* reset internal state */
+    s->enabled = false;
+    s->state = KEYMGR_ST_RESET;
+    s->prng.reseed_req = false;
+    s->prng.reseed_ack = false;
+    s->prng.reseed_cnt = 0u;
+    if (s->use_default_entropy_seed) {
+        const uint8_t *default_prng_seed = s->seeds[KEYMGR_SEED_LFSR];
+        for (unsigned ix = 0; ix < KEYMGR_SEED_BYTES; ix += sizeof(uint32_t)) {
+            uint32_t seed = ldl_le_p(&default_prng_seed[ix]);
+            ot_prng_reseed(s->prng.state, seed);
+        }
+    }
+    s->op_state.op_req = false;
+    s->op_state.op_ack = false;
+    s->op_state.valid_inputs = true;
+    s->op_state.stage = KEYMGR_STAGE_DISABLE;
+    s->op_state.adv_cdi_cnt = 0u;
+    ot_keymgr_reset_kdf_buffer(s);
+
+    /* reset output keys */
+    memset(s->sw_out_key, 0u, sizeof(OtKeyMgrKey));
+
+    /* update IRQ and alert states */
+    ot_keymgr_update_irq(s);
+    ot_keymgr_update_alerts(s);
+
+    /* connect to KMAC */
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    kc->connect_app(s->kmac, s->kmac_app, &KMAC_APP_CFG,
+                    ot_keymgr_handle_kmac_response, s);
+}
+
+static void ot_keymgr_reset_exit(Object *obj, ResetType type)
+{
+    OtKeyMgrClass *c = OT_KEYMGR_GET_CLASS(obj);
+    OtKeyMgrState *s = OT_KEYMGR(obj);
+
+    trace_ot_keymgr_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    /* invalidate internal key state & sideloaded keys when exiting reset */
+    uint32_t all_keys_bm = (1u << KEYMGR_KEY_SINK_COUNT) - 1u;
+    ot_keymgr_wipe_keys(s, true, false, all_keys_bm);
+}
+
+static void ot_keymgr_realize(DeviceState *dev, Error **errp)
+{
+    OtKeyMgrState *s = OT_KEYMGR(dev);
+
+    (void)errp; /* unused */
+
+    if (!s->ot_id) {
+        s->ot_id =
+            g_strdup(object_get_canonical_path_component(OBJECT(s)->parent));
+    }
+
+    for (unsigned ix = 0u; ix < KEYMGR_KEY_SINK_COUNT; ix++) {
+        if (s->key_sinks[ix]) {
+            OBJECT_CHECK(OtKeySinkIf, s->key_sinks[ix], TYPE_OT_KEY_SINK_IF);
+        }
+    }
+
+    ot_keymgr_configure_constants(s);
+
+    /*
+     * Define KMAC separately in `s->kmac` instead of directly as a key sink,
+     * as we also need to offload KDF operations to it.
+     */
+    s->key_sinks[KEYMGR_KEY_SINK_KMAC] = DEVICE(s->kmac);
+}
+
+static void ot_keymgr_init(Object *obj)
+{
+    OtKeyMgrState *s = OT_KEYMGR(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_keymgr_regs_ops, s, TYPE_OT_KEYMGR,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    ibex_sysbus_init_irq(obj, &s->irq);
+    for (unsigned ix = 0u; ix < ALERT_COUNT; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+    qdev_init_gpio_in_named(DEVICE(s), ot_keymgr_lc_signal, OT_KEYMGR_ENABLE,
+                            1);
+
+    s->prng.state = ot_prng_allocate();
+
+    s->kdf_buf.data = g_new0(uint8_t, KEYMGR_KDF_BUFFER_BYTES);
+    s->salt = g_new0(uint8_t, KEYMGR_SALT_BYTES);
+    s->sealing_sw_binding = g_new0(uint8_t, KEYMGR_SW_BINDING_BYTES);
+    s->attest_sw_binding = g_new0(uint8_t, KEYMGR_SW_BINDING_BYTES);
+    for (unsigned ix = 0u; ix < ARRAY_SIZE(s->seeds); ix++) {
+        s->seeds[ix] = g_new0(uint8_t, KEYMGR_SEED_BYTES);
+    }
+    s->key_states = g_new0(OtKeyMgrKey, NUM_CDIS);
+    s->saved_kmac_key = g_new0(OtKeyMgrKey, 1u);
+    s->sw_out_key = g_new0(OtKeyMgrKey, 1u);
+
+    s->fsm_tick_timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_keymgr_fsm_tick, s);
+
+    s->hexstr = g_new0(char, OT_KEYMGR_HEXSTR_SIZE);
+}
+
+static void ot_keymgr_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    (void)data; /* unused */
+
+    dc->realize = &ot_keymgr_realize;
+    device_class_set_props(dc, ot_keymgr_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtKeyMgrClass *kmc = OT_KEYMGR_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_keymgr_reset_enter, NULL,
+                                       &ot_keymgr_reset_exit,
+                                       &kmc->parent_phases);
+}
+
+static const TypeInfo ot_keymgr_info = {
+    .name = TYPE_OT_KEYMGR,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtKeyMgrState),
+    .instance_init = &ot_keymgr_init,
+    .class_size = sizeof(OtKeyMgrClass),
+    .class_init = &ot_keymgr_class_init,
+};
+
+static void ot_keymgr_register_types(void)
+{
+    type_register_static(&ot_keymgr_info);
+}
+
+type_init(ot_keymgr_register_types)
diff --git a/hw/opentitan/ot_keymgr_dpe.c b/hw/opentitan/ot_keymgr_dpe.c
new file mode 100644
index 0000000000000..212162bcffd13
--- /dev/null
+++ b/hw/opentitan/ot_keymgr_dpe.c
@@ -0,0 +1,2214 @@
+/*
+ * QEMU OpenTitan Key Manager DPE device
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Samuel Ortiz <sameo@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_aes.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_key_sink.h"
+#include "hw/opentitan/ot_keymgr_dpe.h"
+#include "hw/opentitan/ot_kmac.h"
+#include "hw/opentitan/ot_lc_ctrl.h"
+#include "hw/opentitan/ot_otbn.h"
+#include "hw/opentitan/ot_otp_if.h"
+#include "hw/opentitan/ot_prng.h"
+#include "hw/opentitan/ot_rom_ctrl.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+#define NUM_SALT_REG          8u
+#define NUM_SW_BINDING_REG    8u
+#define NUM_ROM_DIGEST_INPUTS 2u
+#define NUM_BOOT_STAGES       4u
+#define NUM_SLOTS             4u
+
+#define KEYMGR_DPE_KEY_WIDTH          256u
+#define KEYMGR_DPE_SW_BINDING_WIDTH   ((NUM_SW_BINDING_REG) * 32u)
+#define KEYMGR_DPE_SALT_WITDH         ((NUM_SALT_REG) * 32u)
+#define KEYMGR_DPE_HEALTH_STATE_WIDTH 128u
+#define KEYMGR_DPE_DEV_ID_WIDTH       256u
+
+#define KEYMGR_DPE_ADV_DATA_BYTES \
+    ((KEYMGR_DPE_SW_BINDING_WIDTH + KEYMGR_DPE_KEY_WIDTH + \
+      (1u + (NUM_ROM_DIGEST_INPUTS)) * KEYMGR_DPE_KEY_WIDTH + \
+      KEYMGR_DPE_DEV_ID_WIDTH + KEYMGR_DPE_HEALTH_STATE_WIDTH) / \
+     8u)
+
+/* key version + salt + key ID + constant */
+#define KEYMGR_DPE_GEN_DATA_BYTES \
+    ((32u + KEYMGR_DPE_SALT_WITDH + KEYMGR_DPE_KEY_WIDTH * 2u) / 8u)
+
+#define KEYMGR_DPE_SEED_BYTES       (KEYMGR_DPE_KEY_WIDTH / 8u)
+#define KEYMGR_DPE_KDF_BUFFER_BYTES (1984u / 8u)
+#define KEYMGR_DPE_KEY_SIZE         (256u / 8u)
+#define _MAX(_a_, _b_)              ((_a_) > (_b_) ? (_a_) : (_b_))
+#define KEYMGR_DPE_KEY_SIZE_MAX     _MAX(KEYMGR_DPE_KEY_SIZE, OT_OTBN_KEY_SIZE)
+
+static_assert(KEYMGR_DPE_ADV_DATA_BYTES <= KEYMGR_DPE_KDF_BUFFER_BYTES,
+              "KeyMgr ADV data does not fit in KDF buffer");
+static_assert(KEYMGR_DPE_GEN_DATA_BYTES <= KEYMGR_DPE_KDF_BUFFER_BYTES,
+              "KeyMgr GEN data does not fit in KDF buffer");
+static_assert((KEYMGR_DPE_KDF_BUFFER_BYTES % OT_KMAC_APP_MSG_BYTES) == 0u,
+              "KeyMgr KDF buffer not a multiple of KMAC message size");
+static_assert(KEYMGR_DPE_KEY_SIZE_MAX <= OT_KMAC_APP_DIGEST_BYTES,
+              "KeyMgr key size does not match KMAC digest size");
+/* NOLINTNEXTLINE(misc-redundant-expression) */
+static_assert(OT_OTBN_KEY_SIZE <= OT_KMAC_APP_DIGEST_BYTES,
+              "KeyMgr OTBN key size does not match KMAC digest size");
+static_assert(KEYMGR_DPE_KEY_SIZE == OT_OTP_KEYMGR_SECRET_SIZE,
+              "KeyMgr key size does not match OTP KeyMgr secret size");
+/* NOLINTBEGIN(misc-redundant-expression) */
+static_assert(KEYMGR_DPE_KEY_SIZE == OT_AES_KEY_SIZE, "invalid key size");
+static_assert(KEYMGR_DPE_KEY_SIZE == OT_KMAC_KEY_SIZE, "invalid key size");
+/* NOLINTEND(misc-redundant-expression) */
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(INTR_OP_DONE, 0u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, RECOV_OPERATION, 0u, 1u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 1u, 1u)
+REG32(CFG_REGWEN, 0x10u)
+    FIELD(CFG_REGWEN, EN, 0u, 1u)
+REG32(START, 0x14u)
+    FIELD(START, EN, 0u, 1u)
+REG32(CONTROL_SHADOWED, 0x18u)
+    FIELD(CONTROL_SHADOWED, OPERATION, 4u, 3u)
+    FIELD(CONTROL_SHADOWED, DEST_SEL, 12u, 2u)
+    FIELD(CONTROL_SHADOWED, SLOT_SRC_SEL, 14u, 2u)
+    FIELD(CONTROL_SHADOWED, SLOT_DST_SEL, 18u, 2u)
+REG32(SIDELOAD_CLEAR, 0x1cu)
+    FIELD(SIDELOAD_CLEAR, VAL, 0u, 3u)
+REG32(RESEED_INTERVAL_REGWEN, 0x20u)
+    FIELD(RESEED_INTERVAL_REGWEN, EN, 0u, 1u)
+REG32(RESEED_INTERVAL_SHADOWED, 0x24u)
+    FIELD(RESEED_INTERVAL_SHADOWED, VAL, 0u, 16u)
+REG32(SLOT_POLICY_REGWEN, 0x28u)
+    FIELD(SLOT_POLICY_REGWEN, EN, 0u, 1u)
+REG32(SLOT_POLICY, 0x2cu)
+    FIELD(SLOT_POLICY, ALLOW_CHILD, 0u, 1u)
+    FIELD(SLOT_POLICY, EXPORTABLE, 1u, 1u)
+    FIELD(SLOT_POLICY, RETAIN_PARENT, 2u, 1u)
+REG32(SW_BINDING_REGWEN, 0x30u)
+    FIELD(SW_BINDING_REGWEN, EN, 0u, 1u)
+REG32(SW_BINDING_0, 0x34u)
+REG32(SW_BINDING_1, 0x38u)
+REG32(SW_BINDING_2, 0x3cu)
+REG32(SW_BINDING_3, 0x40u)
+REG32(SW_BINDING_4, 0x44u)
+REG32(SW_BINDING_5, 0x48u)
+REG32(SW_BINDING_6, 0x4cu)
+REG32(SW_BINDING_7, 0x50u)
+REG32(SALT_0, 0x54u)
+REG32(SALT_1, 0x58u)
+REG32(SALT_2, 0x5cu)
+REG32(SALT_3, 0x60u)
+REG32(SALT_4, 0x64u)
+REG32(SALT_5, 0x68u)
+REG32(SALT_6, 0x6cu)
+REG32(SALT_7, 0x70u)
+REG32(KEY_VERSION, 0x74u)
+REG32(MAX_KEY_VER_REGWEN, 0x78u)
+    FIELD(MAX_KEY_VER_REGWEN, EN, 0u, 1u)
+REG32(MAX_KEY_VER_SHADOWED, 0x7cu)
+REG32(SW_SHARE0_OUTPUT_0, 0x80u)
+REG32(SW_SHARE0_OUTPUT_1, 0x84u)
+REG32(SW_SHARE0_OUTPUT_2, 0x88u)
+REG32(SW_SHARE0_OUTPUT_3, 0x8cu)
+REG32(SW_SHARE0_OUTPUT_4, 0x90u)
+REG32(SW_SHARE0_OUTPUT_5, 0x94u)
+REG32(SW_SHARE0_OUTPUT_6, 0x98u)
+REG32(SW_SHARE0_OUTPUT_7, 0x9cu)
+REG32(SW_SHARE1_OUTPUT_0, 0xa0u)
+REG32(SW_SHARE1_OUTPUT_1, 0xa4u)
+REG32(SW_SHARE1_OUTPUT_2, 0xa8u)
+REG32(SW_SHARE1_OUTPUT_3, 0xacu)
+REG32(SW_SHARE1_OUTPUT_4, 0xb0u)
+REG32(SW_SHARE1_OUTPUT_5, 0xb4u)
+REG32(SW_SHARE1_OUTPUT_6, 0xb8u)
+REG32(SW_SHARE1_OUTPUT_7, 0xbcu)
+REG32(WORKING_STATE, 0xc0u)
+    FIELD(WORKING_STATE, VAL, 0u, 2u)
+REG32(OP_STATUS, 0xc4u)
+    FIELD(OP_STATUS, VAL, 0u, 2u)
+REG32(ERR_CODE, 0xc8u)
+    FIELD(ERR_CODE, INVALID_OP, 0u, 1u)
+    FIELD(ERR_CODE, INVALID_KMAC_INPUT, 1u, 1u)
+    FIELD(ERR_CODE, INVALID_SHADOW_UPDATE, 2u, 1u)
+REG32(FAULT_STATUS, 0xccu)
+    FIELD(FAULT_STATUS, CMD, 0u, 1u)
+    FIELD(FAULT_STATUS, KMAC_FSM, 1u, 1u)
+    FIELD(FAULT_STATUS, KMAC_DONE, 2u, 1u)
+    FIELD(FAULT_STATUS, KMAC_OP, 3u, 1u)
+    FIELD(FAULT_STATUS, KMAC_OUT, 4u, 1u)
+    FIELD(FAULT_STATUS, REGFILE_INTG, 5u, 1u)
+    FIELD(FAULT_STATUS, SHADOW, 6u, 1u)
+    FIELD(FAULT_STATUS, CTRL_FSM_INTG, 7u, 1u)
+    FIELD(FAULT_STATUS, CTRL_FSM_CHK, 8u, 1u)
+    FIELD(FAULT_STATUS, CTRL_FSM_CNT, 9u, 1u)
+    FIELD(FAULT_STATUS, RESEED_CNT, 10u, 1u)
+    FIELD(FAULT_STATUS, SIDE_CTRL_FSM, 11u, 1u)
+    FIELD(FAULT_STATUS, SIDE_CTRL_SEL, 12u, 1u)
+    FIELD(FAULT_STATUS, KEY_ECC, 13u, 1u)
+REG32(DEBUG, 0xd0u)
+    FIELD(DEBUG, INVALID_CREATOR_SEED, 0u, 1u)
+    FIELD(DEBUG, INVALID_OWNER_SEED, 1u, 1u)
+    FIELD(DEBUG, INVALID_DEV_ID, 2u, 1u)
+    FIELD(DEBUG, INVALID_HEALTH_STATE, 3u, 1u)
+    FIELD(DEBUG, INVALID_KEY_VERSION, 4u, 1u)
+    FIELD(DEBUG, INVALID_KEY, 5u, 1u)
+    FIELD(DEBUG, INVALID_DIGEST, 6u, 1u)
+    FIELD(DEBUG, INVALID_ROOT_KEY, 7u, 1u)
+    FIELD(DEBUG, INACTIVE_LC_EN, 8u, 1u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_DEBUG)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+
+#define INTR_MASK (INTR_OP_DONE_MASK)
+#define ALERT_MASK \
+    (R_ALERT_TEST_RECOV_OPERATION_MASK | R_ALERT_TEST_FATAL_FAULT_MASK)
+
+#define R_CONTROL_SHADOWED_MASK \
+    (R_CONTROL_SHADOWED_OPERATION_MASK | R_CONTROL_SHADOWED_DEST_SEL_MASK | \
+     R_CONTROL_SHADOWED_SLOT_SRC_SEL_MASK | \
+     R_CONTROL_SHADOWED_SLOT_DST_SEL_MASK)
+
+#define ERR_CODE_MASK \
+    (R_ERR_CODE_INVALID_OP_MASK | R_ERR_CODE_INVALID_KMAC_INPUT_MASK | \
+     R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK)
+
+#define FAULT_STATUS_MASK \
+    (R_FAULT_STATUS_CMD_MASK | R_FAULT_STATUS_KMAC_FSM_MASK | \
+     R_FAULT_STATUS_KMAC_DONE_MASK | R_FAULT_STATUS_KMAC_OP_MASK | \
+     R_FAULT_STATUS_KMAC_OUT_MASK | R_FAULT_STATUS_REGFILE_INTG_MASK | \
+     R_FAULT_STATUS_SHADOW_MASK | R_FAULT_STATUS_CTRL_FSM_INTG_MASK | \
+     R_FAULT_STATUS_CTRL_FSM_CHK_MASK | R_FAULT_STATUS_CTRL_FSM_CNT_MASK | \
+     R_FAULT_STATUS_RESEED_CNT_MASK | R_FAULT_STATUS_SIDE_CTRL_FSM_MASK | \
+     R_FAULT_STATUS_SIDE_CTRL_SEL_MASK | R_FAULT_STATUS_KEY_ECC_MASK)
+
+#define DEBUG_MASK \
+    (R_DEBUG_INVALID_CREATOR_SEED_MASK | R_DEBUG_INVALID_OWNER_SEED_MASK | \
+     R_DEBUG_INVALID_DEV_ID_MASK | R_DEBUG_INVALID_HEALTH_STATE_MASK | \
+     R_DEBUG_INVALID_KEY_VERSION_MASK | R_DEBUG_INVALID_KEY_MASK | \
+     R_DEBUG_INVALID_DIGEST_MASK | R_DEBUG_INVALID_ROOT_KEY_MASK | \
+     R_DEBUG_INACTIVE_LC_EN_MASK)
+
+#define KEYMGR_DPE_LFSR_WIDTH    64u
+#define KEYMGR_DPE_ENTROPY_WIDTH (KEYMGR_DPE_LFSR_WIDTH / 2u)
+#define KEYMGR_DPE_ENTROPY_ROUNDS \
+    (KEYMGR_DPE_KEY_WIDTH / KEYMGR_DPE_ENTROPY_WIDTH)
+
+#define KEYMGR_DPE_RESEED_COUNT \
+    (KEYMGR_DPE_LFSR_WIDTH / (8u * sizeof(uint32_t)))
+
+typedef enum {
+    KEYMGR_DPE_KEY_SINK_AES,
+    KEYMGR_DPE_KEY_SINK_KMAC,
+    KEYMGR_DPE_KEY_SINK_OTBN,
+    KEYMGR_DPE_KEY_SINK_COUNT
+} OtKeyMgrDpeKeySink;
+
+#define KEY_SINK_OFFSET 1
+
+/* values for CONTROL_SHADOWED.OPERATION */
+typedef enum {
+    KEYMGR_DPE_OP_ADVANCE = 0,
+    KEYMGR_DPE_OP_ERASE_SLOT = 1,
+    KEYMGR_DPE_OP_GENERATE_SW_OUTPUT = 2,
+    KEYMGR_DPE_OP_GENERATE_HW_OUTPUT = 3,
+    KEYMGR_DPE_OP_DISABLE = 4,
+} OtKeyMgrDpeOperation;
+
+/* values for CONTROL_SHADOWED.DEST_SEL */
+typedef enum {
+    KEYMGR_DPE_DEST_SEL_VALUE_NONE = 0,
+    KEYMGR_DPE_DEST_SEL_VALUE_AES = KEYMGR_DPE_KEY_SINK_AES + KEY_SINK_OFFSET,
+    KEYMGR_DPE_DEST_SEL_VALUE_KMAC = KEYMGR_DPE_KEY_SINK_KMAC + KEY_SINK_OFFSET,
+    KEYMGR_DPE_DEST_SEL_VALUE_OTBN = KEYMGR_DPE_KEY_SINK_OTBN + KEY_SINK_OFFSET,
+} OtKeyMgrDpeDestSel;
+
+/* values for SIDELOAD_CLEAR.VAL */
+typedef enum {
+    KEYMGR_DPE_SIDELOAD_CLEAR_NONE = 0,
+    KEYMGR_DPE_SIDELOAD_CLEAR_AES = KEYMGR_DPE_KEY_SINK_AES + KEY_SINK_OFFSET,
+    KEYMGR_DPE_SIDELOAD_CLEAR_KMAC = KEYMGR_DPE_KEY_SINK_KMAC + KEY_SINK_OFFSET,
+    KEYMGR_DPE_SIDELOAD_CLEAR_OTBN = KEYMGR_DPE_KEY_SINK_OTBN + KEY_SINK_OFFSET,
+} OtKeyMgrDpeSideloadClear;
+
+/* values for WORKING_STATE.STATE */
+typedef enum {
+    KEYMGR_DPE_WORKING_STATE_RESET = 0,
+    KEYMGR_DPE_WORKING_STATE_AVAILABLE = 1,
+    KEYMGR_DPE_WORKING_STATE_DISABLED = 2,
+    KEYMGR_DPE_WORKING_STATE_INVALID = 3,
+} OtKeyMgrDpeWorkingState;
+
+/* value for OP_STATUS.STATUS */
+typedef enum {
+    KEYMGR_DPE_OP_STATUS_IDLE = 0,
+    KEYMGR_DPE_OP_STATUS_WIP = 1,
+    KEYMGR_DPE_OP_STATUS_DONE_SUCCESS = 2,
+    KEYMGR_DPE_OP_STATUS_DONE_ERROR = 3,
+} OtKeyMgrDpeOpStatus;
+
+enum {
+    /* clang-format off */
+    ALERT_RECOVERABLE,
+    ALERT_FATAL,
+    ALERT_COUNT
+    /* clang-format on */
+};
+
+enum {
+    KEYMGR_DPE_SEED_LFSR,
+    KEYMGR_DPE_SEED_REV,
+    KEYMGR_DPE_SEED_SW_OUT,
+    KEYMGR_DPE_SEED_HW_OUT,
+    KEYMGR_DPE_SEED_AES,
+    KEYMGR_DPE_SEED_KMAC,
+    KEYMGR_DPE_SEED_OTBN,
+    KEYMGR_DPE_SEED_NONE,
+    KEYMGR_DPE_SEED_COUNT,
+};
+
+typedef enum {
+    KEYMGR_DPE_ST_RESET,
+    KEYMGR_DPE_ST_ENTROPY_RESEED,
+    KEYMGR_DPE_ST_RANDOM,
+    KEYMGR_DPE_ST_ROOTKEY,
+    KEYMGR_DPE_ST_AVAILABLE,
+    KEYMGR_DPE_ST_WIPE,
+    KEYMGR_DPE_ST_DISABLING,
+    KEYMGR_DPE_ST_DISABLED,
+    KEYMGR_DPE_ST_INVALID,
+} OtKeyMgrDpeFSMState;
+
+typedef struct {
+    OtEDNState *device;
+    uint8_t ep;
+    bool connected;
+    bool scheduled;
+} OtKeyMgrDpeEDN;
+
+typedef struct {
+    OtPrngState *state;
+    bool reseed_req;
+    bool reseed_ack;
+    uint8_t reseed_cnt;
+} OtKeyMgrDpePrng;
+
+typedef struct {
+    bool allow_child;
+    bool exportable;
+    bool retain_parent;
+} OtKeyMgrDpeSlotPolicy;
+
+typedef struct {
+    uint8_t share0[KEYMGR_DPE_KEY_SIZE];
+    uint8_t share1[KEYMGR_DPE_KEY_SIZE];
+    bool valid;
+} OtKeyMgrDpeKey;
+
+typedef struct {
+    OtKeyMgrDpeKey key; /* always 256 bit keys */
+    uint32_t max_key_version;
+    uint8_t boot_stage;
+    OtKeyMgrDpeSlotPolicy policy;
+    bool valid;
+} OtKeyMgrDpeSlot;
+
+typedef struct {
+    uint8_t share0[OT_OTBN_KEY_SIZE];
+    uint8_t share1[OT_OTBN_KEY_SIZE];
+    bool valid;
+} OtKeyMgrDpeOtbnKey;
+
+typedef struct {
+    bool op_req;
+    bool op_ack;
+} OtKeyMgrDpeOpState;
+
+typedef struct {
+    uint8_t *data;
+    unsigned offset; /* current read offset (in bytes) */
+    unsigned length; /* current length (in bytes) */
+} OtKeyMgrDpeKdfBuffer;
+
+typedef struct OtKeyMgrDpeState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ irq;
+    IbexIRQ alerts[ALERT_COUNT];
+    QEMUBH *fsm_tick_bh;
+    OtKeyMgrDpeKdfBuffer kdf_buf;
+
+    uint32_t regs[REGS_COUNT];
+    OtShadowReg control;
+    OtShadowReg reseed_interval;
+    OtShadowReg max_key_ver;
+    uint8_t *salt;
+    uint8_t *sw_binding;
+
+    bool enabled;
+    OtKeyMgrDpeFSMState state;
+    OtKeyMgrDpePrng prng;
+    OtKeyMgrDpeOpState op_state;
+    uint8_t *seeds[KEYMGR_DPE_SEED_COUNT];
+
+    /* key slots */
+    OtKeyMgrDpeSlot *key_slots;
+
+    /* SW output keys */
+    OtKeyMgrDpeKey *sw_out_key;
+
+    char *hexstr;
+
+    /* properties */
+    char *ot_id;
+    OtKeyMgrDpeEDN edn;
+    OtKMACState *kmac;
+    uint8_t kmac_app;
+    OtLcCtrlState *lc_ctrl;
+    DeviceState *otp_ctrl;
+    OtRomCtrlState *rom_ctrl[NUM_ROM_DIGEST_INPUTS];
+    DeviceState *key_sinks[KEYMGR_DPE_KEY_SINK_COUNT];
+    char *seed_xstrs[KEYMGR_DPE_SEED_COUNT];
+} OtKeyMgrDpeState;
+
+struct OtKeyMgrDpeClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static const OtKeyMgrDpeSlotPolicy DEFAULT_UDS_POLICY = {
+    .allow_child = true,
+    .exportable = false,
+    .retain_parent = false,
+};
+
+static const size_t OT_KEY_MGR_DPE_KEY_SINK_SIZES[KEYMGR_DPE_KEY_SINK_COUNT] = {
+    [KEYMGR_DPE_KEY_SINK_AES] = OT_AES_KEY_SIZE,
+    [KEYMGR_DPE_KEY_SINK_KMAC] = OT_KMAC_KEY_SIZE,
+    [KEYMGR_DPE_KEY_SINK_OTBN] = OT_OTBN_KEY_SIZE,
+};
+
+static const OtKMACAppCfg KMAC_APP_CFG = OT_KMAC_CONFIG(KMAC, 256u, "KMAC", "");
+
+#define REG_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_ENTRY(INTR_STATE),
+    REG_ENTRY(INTR_ENABLE),
+    REG_ENTRY(INTR_TEST),
+    REG_ENTRY(ALERT_TEST),
+    REG_ENTRY(CFG_REGWEN),
+    REG_ENTRY(START),
+    REG_ENTRY(CONTROL_SHADOWED),
+    REG_ENTRY(SIDELOAD_CLEAR),
+    REG_ENTRY(RESEED_INTERVAL_REGWEN),
+    REG_ENTRY(RESEED_INTERVAL_SHADOWED),
+    REG_ENTRY(SLOT_POLICY_REGWEN),
+    REG_ENTRY(SLOT_POLICY),
+    REG_ENTRY(SW_BINDING_REGWEN),
+    REG_ENTRY(SW_BINDING_0),
+    REG_ENTRY(SW_BINDING_1),
+    REG_ENTRY(SW_BINDING_2),
+    REG_ENTRY(SW_BINDING_3),
+    REG_ENTRY(SW_BINDING_4),
+    REG_ENTRY(SW_BINDING_5),
+    REG_ENTRY(SW_BINDING_6),
+    REG_ENTRY(SW_BINDING_7),
+    REG_ENTRY(SALT_0),
+    REG_ENTRY(SALT_1),
+    REG_ENTRY(SALT_2),
+    REG_ENTRY(SALT_3),
+    REG_ENTRY(SALT_4),
+    REG_ENTRY(SALT_5),
+    REG_ENTRY(SALT_6),
+    REG_ENTRY(SALT_7),
+    REG_ENTRY(KEY_VERSION),
+    REG_ENTRY(MAX_KEY_VER_REGWEN),
+    REG_ENTRY(MAX_KEY_VER_SHADOWED),
+    REG_ENTRY(SW_SHARE0_OUTPUT_0),
+    REG_ENTRY(SW_SHARE0_OUTPUT_1),
+    REG_ENTRY(SW_SHARE0_OUTPUT_2),
+    REG_ENTRY(SW_SHARE0_OUTPUT_3),
+    REG_ENTRY(SW_SHARE0_OUTPUT_4),
+    REG_ENTRY(SW_SHARE0_OUTPUT_5),
+    REG_ENTRY(SW_SHARE0_OUTPUT_6),
+    REG_ENTRY(SW_SHARE0_OUTPUT_7),
+    REG_ENTRY(SW_SHARE1_OUTPUT_0),
+    REG_ENTRY(SW_SHARE1_OUTPUT_1),
+    REG_ENTRY(SW_SHARE1_OUTPUT_2),
+    REG_ENTRY(SW_SHARE1_OUTPUT_3),
+    REG_ENTRY(SW_SHARE1_OUTPUT_4),
+    REG_ENTRY(SW_SHARE1_OUTPUT_5),
+    REG_ENTRY(SW_SHARE1_OUTPUT_6),
+    REG_ENTRY(SW_SHARE1_OUTPUT_7),
+    REG_ENTRY(WORKING_STATE),
+    REG_ENTRY(OP_STATUS),
+    REG_ENTRY(ERR_CODE),
+    REG_ENTRY(FAULT_STATUS),
+    REG_ENTRY(DEBUG),
+};
+#undef REG_ENTRY
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define OP_ENTRY(_op_) [KEYMGR_DPE_OP_##_op_] = stringify(_op_)
+static const char *OP_NAMES[] = {
+    OP_ENTRY(ADVANCE),
+    OP_ENTRY(ERASE_SLOT),
+    OP_ENTRY(GENERATE_SW_OUTPUT),
+    OP_ENTRY(GENERATE_HW_OUTPUT),
+    OP_ENTRY(DISABLE),
+};
+#undef OP_ENTRY
+#define OP_NAME(_op_) \
+    (((unsigned)(_op_)) < ARRAY_SIZE(OP_NAMES) ? OP_NAMES[(_op_)] : "?")
+
+#define KEY_SINK_ENTRY(_st_) [KEYMGR_DPE_KEY_SINK_##_st_] = stringify(_st_)
+static const char *KEY_SINK_NAMES[] = {
+    KEY_SINK_ENTRY(AES),
+    KEY_SINK_ENTRY(KMAC),
+    KEY_SINK_ENTRY(OTBN),
+};
+#undef KEY_SINK_ENTRY
+#define KEY_SINK_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(KEY_SINK_NAMES) ? \
+         KEY_SINK_NAMES[(_st_)] : \
+         "?")
+
+#define SIDELOAD_CLEAR_ENTRY(_st_) \
+    [KEYMGR_DPE_SIDELOAD_CLEAR_##_st_] = stringify(_st_)
+static const char *SIDELOAD_CLEAR_NAMES[] = {
+    SIDELOAD_CLEAR_ENTRY(NONE),
+    SIDELOAD_CLEAR_ENTRY(AES),
+    SIDELOAD_CLEAR_ENTRY(KMAC),
+    SIDELOAD_CLEAR_ENTRY(OTBN),
+};
+#undef SIDELOAD_CLEAR_ENTRY
+#define SIDELOAD_CLEAR_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(SIDELOAD_CLEAR_NAMES) ? \
+         SIDELOAD_CLEAR_NAMES[(_st_)] : \
+         "?")
+
+#define WORKING_STATE_ENTRY(_st_) \
+    [KEYMGR_DPE_WORKING_STATE_##_st_] = stringify(_st_)
+static const char *WORKING_STATE_NAMES[] = {
+    WORKING_STATE_ENTRY(RESET),
+    WORKING_STATE_ENTRY(AVAILABLE),
+    WORKING_STATE_ENTRY(DISABLED),
+    WORKING_STATE_ENTRY(INVALID),
+};
+#undef WORKING_STATE_ENTRY
+#define WORKING_STATE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(WORKING_STATE_NAMES) ? \
+         WORKING_STATE_NAMES[(_st_)] : \
+         "?")
+
+#define OP_STATUS_ENTRY(_st_) [KEYMGR_DPE_OP_STATUS_##_st_] = stringify(_st_)
+static const char *OP_STATUS_NAMES[] = {
+    OP_STATUS_ENTRY(IDLE),
+    OP_STATUS_ENTRY(WIP),
+    OP_STATUS_ENTRY(DONE_SUCCESS),
+    OP_STATUS_ENTRY(DONE_ERROR),
+};
+#undef OP_STATUS_ENTRY
+#define OP_STATUS_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(OP_STATUS_NAMES) ? \
+         OP_STATUS_NAMES[(_st_)] : \
+         "?")
+
+#define FST_ENTRY(_st_) [KEYMGR_DPE_ST_##_st_] = stringify(_st_)
+static const char *FST_NAMES[] = {
+    /* clang-format off */
+    FST_ENTRY(RESET),
+    FST_ENTRY(ENTROPY_RESEED),
+    FST_ENTRY(RANDOM),
+    FST_ENTRY(ROOTKEY),
+    FST_ENTRY(AVAILABLE),
+    FST_ENTRY(WIPE),
+    FST_ENTRY(DISABLING),
+    FST_ENTRY(DISABLED),
+    FST_ENTRY(INVALID),
+    /* clang-format on */
+};
+#undef FST_ENTRY
+#define FST_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(FST_NAMES) ? FST_NAMES[(_st_)] : "?")
+
+#define SEED_ENTRY(_sd_) [KEYMGR_DPE_SEED_##_sd_] = stringify(_sd_)
+static const char *SEED_NAMES[] = {
+    /* clang-format off */
+    SEED_ENTRY(LFSR),
+    SEED_ENTRY(REV),
+    SEED_ENTRY(SW_OUT),
+    SEED_ENTRY(HW_OUT),
+    SEED_ENTRY(AES),
+    SEED_ENTRY(KMAC),
+    SEED_ENTRY(OTBN),
+    SEED_ENTRY(NONE),
+    SEED_ENTRY(COUNT),
+    /* clang-format on */
+};
+#undef SEED_ENTRY
+#define SEED_NAME(_sd_) \
+    (((unsigned)(_sd_)) < ARRAY_SIZE(SEED_NAMES) ? SEED_NAMES[(_sd_)] : "?")
+
+#define OT_KEYMGR_DPE_HEXSTR_SIZE 256u
+
+#define ot_keymgr_dpe_dump_bigint(_s_, _b_, _l_) \
+    ot_common_lhexdump(_b_, _l_, true, (_s_)->hexstr, OT_KEYMGR_DPE_HEXSTR_SIZE)
+
+static void ot_keymgr_dpe_dump_kdf_buf(OtKeyMgrDpeState *s, const char *op)
+{
+    if (trace_event_get_state(TRACE_OT_KEYMGR_DPE_DUMP_KDF_BUF)) {
+        size_t msgs = (s->kdf_buf.length + OT_KMAC_APP_MSG_BYTES - 1u) /
+                      OT_KMAC_APP_MSG_BYTES;
+        for (size_t ix = 0u; ix < msgs; ix++) {
+            trace_ot_keymgr_dpe_dump_kdf_buf(
+                s->ot_id, op, ix,
+                ot_keymgr_dpe_dump_bigint(
+                    s, &s->kdf_buf.data[ix * OT_KMAC_APP_MSG_BYTES],
+                    OT_KMAC_APP_MSG_BYTES));
+        }
+    }
+}
+
+#define ot_keymgr_dpe_schedule_fsm(_s_) \
+    ot_keymgr_dpe_xschedule_fsm(_s_, __func__, __LINE__)
+
+static void
+ot_keymgr_dpe_xschedule_fsm(OtKeyMgrDpeState *s, const char *func, int line)
+{
+    trace_ot_keymgr_dpe_schedule_fsm(s->ot_id, func, line);
+    qemu_bh_schedule(s->fsm_tick_bh);
+}
+
+static void ot_keymgr_dpe_update_irq(OtKeyMgrDpeState *s)
+{
+    bool level = (bool)(s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE]);
+    trace_ot_keymgr_dpe_irq(s->ot_id, s->regs[R_INTR_STATE],
+                            s->regs[R_INTR_ENABLE], level);
+    ibex_irq_set(&s->irq, (int)level);
+}
+
+static void ot_keymgr_dpe_update_alert(OtKeyMgrDpeState *s)
+{
+    uint32_t level = s->regs[R_ALERT_TEST];
+
+    if (s->regs[R_FAULT_STATUS] & FAULT_STATUS_MASK) {
+        level |= 1u << ALERT_FATAL;
+    }
+    if (s->regs[R_ERR_CODE] & ERR_CODE_MASK) {
+        level |= 1u << ALERT_RECOVERABLE;
+    }
+
+    for (unsigned ix = 0u; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static OtKeyMgrDpeWorkingState
+ot_keymgr_dpe_get_working_state(const OtKeyMgrDpeState *s)
+{
+    switch (FIELD_EX32(s->regs[R_WORKING_STATE], WORKING_STATE, VAL)) {
+    case KEYMGR_DPE_WORKING_STATE_RESET:
+        return KEYMGR_DPE_WORKING_STATE_RESET;
+    case KEYMGR_DPE_WORKING_STATE_AVAILABLE:
+        return KEYMGR_DPE_WORKING_STATE_AVAILABLE;
+    case KEYMGR_DPE_WORKING_STATE_DISABLED:
+        return KEYMGR_DPE_WORKING_STATE_DISABLED;
+    default:
+        return KEYMGR_DPE_WORKING_STATE_INVALID;
+    }
+}
+
+#define ot_keymgr_dpe_change_working_state(_s_, _working_state_) \
+    ot_keymgr_dpe_xchange_working_state(_s_, _working_state_, __LINE__)
+
+static void ot_keymgr_dpe_xchange_working_state(
+    OtKeyMgrDpeState *s, OtKeyMgrDpeWorkingState working_state, int line)
+{
+    OtKeyMgrDpeWorkingState prev_state = ot_keymgr_dpe_get_working_state(s);
+
+    if (prev_state != working_state) {
+        trace_ot_keymgr_dpe_change_working_state(s->ot_id, line,
+                                                 WORKING_STATE_NAME(prev_state),
+                                                 prev_state,
+                                                 WORKING_STATE_NAME(
+                                                     working_state),
+                                                 working_state);
+        s->regs[R_WORKING_STATE] = working_state;
+    }
+}
+
+static OtKeyMgrDpeOpStatus
+ot_keymgr_dpe_get_op_status(const OtKeyMgrDpeState *s)
+{
+    switch (FIELD_EX32(s->regs[R_OP_STATUS], OP_STATUS, VAL)) {
+    case KEYMGR_DPE_OP_STATUS_IDLE:
+        return KEYMGR_DPE_OP_STATUS_IDLE;
+    case KEYMGR_DPE_OP_STATUS_WIP:
+        return KEYMGR_DPE_OP_STATUS_WIP;
+    case KEYMGR_DPE_OP_STATUS_DONE_SUCCESS:
+        return KEYMGR_DPE_OP_STATUS_DONE_SUCCESS;
+    case KEYMGR_DPE_OP_STATUS_DONE_ERROR:
+        return KEYMGR_DPE_OP_STATUS_DONE_ERROR;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+#define ot_keymgr_dpe_change_op_status(_s_, _op_status_) \
+    ot_keymgr_dpe_xchange_op_status(_s_, _op_status_, __LINE__)
+
+static void ot_keymgr_dpe_xchange_op_status(
+    OtKeyMgrDpeState *s, OtKeyMgrDpeOpStatus op_status, int line)
+{
+    OtKeyMgrDpeOpStatus prev_op_status = ot_keymgr_dpe_get_op_status(s);
+    if (prev_op_status != op_status) {
+        trace_ot_keymgr_dpe_change_op_status(s->ot_id, line,
+                                             OP_STATUS_NAME(prev_op_status),
+                                             prev_op_status,
+                                             OP_STATUS_NAME(op_status),
+                                             op_status);
+        s->regs[R_OP_STATUS] =
+            FIELD_DP32(s->regs[R_OP_STATUS], OP_STATUS, VAL, op_status);
+    }
+}
+
+static void ot_keymgr_dpe_request_entropy(OtKeyMgrDpeState *s);
+
+static void ot_keymgr_dpe_push_entropy(void *opaque, uint32_t bits, bool fips)
+{
+    (void)fips;
+    OtKeyMgrDpeState *s = opaque;
+    OtKeyMgrDpeEDN *edn = &s->edn;
+    OtKeyMgrDpePrng *prng = &s->prng;
+
+    if (!edn->scheduled) {
+        trace_ot_keymgr_dpe_error(s->ot_id, "Unexpected entropy");
+        return;
+    }
+    edn->scheduled = false;
+
+    ot_prng_reseed(prng->state, bits);
+    prng->reseed_cnt++;
+
+    bool resched = prng->reseed_cnt < KEYMGR_DPE_RESEED_COUNT;
+
+    trace_ot_keymgr_dpe_entropy(s->ot_id, prng->reseed_cnt, resched);
+
+    if (resched) {
+        /* We need more entropy */
+        ot_keymgr_dpe_request_entropy(s);
+    } else if (prng->reseed_req) {
+        prng->reseed_ack = true;
+        prng->reseed_cnt = 0u;
+        ot_keymgr_dpe_schedule_fsm(s);
+    }
+}
+
+static void ot_keymgr_dpe_request_entropy(OtKeyMgrDpeState *s)
+{
+    OtKeyMgrDpeEDN *edn = &s->edn;
+
+    if (!edn->connected) {
+        ot_edn_connect_endpoint(edn->device, edn->ep,
+                                &ot_keymgr_dpe_push_entropy, s);
+        edn->connected = true;
+    }
+
+    if (!edn->scheduled) {
+        edn->scheduled = s->prng.reseed_req;
+        if (!edn->scheduled) {
+            return;
+        }
+        if (ot_edn_request_entropy(edn->device, edn->ep)) {
+            error_setg(&error_fatal,
+                       "%s: %s: keymgr_dpe failed to request entropy", __func__,
+                       s->ot_id);
+        }
+    }
+}
+
+static void ot_keymgr_dpe_push_key(
+    OtKeyMgrDpeState *s, OtKeyMgrDpeKeySink key_sink, const uint8_t *key_share0,
+    const uint8_t *key_share1, bool valid)
+{
+    g_assert((unsigned)key_sink < KEYMGR_DPE_KEY_SINK_COUNT);
+
+    size_t key_size = OT_KEY_MGR_DPE_KEY_SINK_SIZES[key_sink];
+
+    DeviceState *sink = s->key_sinks[key_sink];
+    if (!sink) {
+        return;
+    }
+
+    if (trace_event_get_state(TRACE_OT_KEYMGR_DPE_PUSH_KEY)) {
+        if (!key_share0 || !key_share1) {
+            trace_ot_keymgr_dpe_push_key(s->ot_id, KEY_SINK_NAME(key_sink),
+                                         valid, "");
+        } else {
+            /* Compute the unmasked key for tracing. */
+            uint8_t key_value[KEYMGR_DPE_KEY_SIZE_MAX];
+            for (unsigned ix = 0u; ix < key_size; ix++) {
+                key_value[ix] = key_share0[ix] ^ key_share1[ix];
+            }
+
+            trace_ot_keymgr_dpe_push_key(s->ot_id, KEY_SINK_NAME(key_sink),
+                                         valid,
+                                         ot_keymgr_dpe_dump_bigint(s, key_value,
+                                                                   key_size));
+        }
+    }
+
+    OtKeySinkIfClass *kc = OT_KEY_SINK_IF_GET_CLASS(sink);
+    OtKeySinkIf *ki = OT_KEY_SINK_IF(sink);
+
+    g_assert(kc->push_key);
+
+    kc->push_key(ki, key_share0, key_share1, key_size, valid);
+}
+
+static void ot_keymgr_dpe_kmac_push_key(OtKeyMgrDpeState *s)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    uint8_t slot_src_sel =
+        (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, SLOT_SRC_SEL);
+    OtKeyMgrDpeSlot *src_slot = &s->key_slots[slot_src_sel];
+
+    ot_keymgr_dpe_push_key(s, KEYMGR_DPE_KEY_SINK_KMAC, src_slot->key.share0,
+                           src_slot->key.share1, src_slot->valid);
+}
+
+static void ot_keymgr_dpe_send_kmac_req(OtKeyMgrDpeState *s)
+{
+    g_assert(s->kdf_buf.length);
+    g_assert(s->kdf_buf.offset < s->kdf_buf.length);
+
+    unsigned msg_len = s->kdf_buf.length - s->kdf_buf.offset;
+    if (msg_len > OT_KMAC_APP_MSG_BYTES) {
+        msg_len = OT_KMAC_APP_MSG_BYTES;
+    }
+
+    unsigned next_offset = s->kdf_buf.offset + msg_len;
+
+    OtKMACAppReq req = {
+        .last = next_offset == s->kdf_buf.length,
+        .msg_len = msg_len,
+    };
+    memcpy(req.msg_data, &s->kdf_buf.data[s->kdf_buf.offset], msg_len);
+
+    trace_ot_keymgr_dpe_kmac_req(s->ot_id, s->kdf_buf.length, s->kdf_buf.offset,
+                                 req.msg_len, req.last);
+
+    s->kdf_buf.offset = next_offset;
+
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    kc->app_request(s->kmac, s->kmac_app, &req);
+}
+
+static bool ot_keymgr_dpe_handle_kmac_resp_advance(
+    OtKeyMgrDpeState *s, uint8_t slot_src_sel, uint8_t slot_dst_sel,
+    const OtKMACAppRsp *rsp)
+{
+    uint32_t max_key_version = ot_shadow_reg_peek(&s->max_key_ver);
+    uint32_t slot_policy = s->regs[R_SLOT_POLICY];
+    OtKeyMgrDpeSlot *src_slot = &s->key_slots[slot_src_sel];
+    OtKeyMgrDpeSlot *dst_slot = &s->key_slots[slot_dst_sel];
+
+    dst_slot->valid = true;
+    memcpy(dst_slot->key.share0, rsp->digest_share0, OT_KMAC_KEY_SIZE);
+    memcpy(dst_slot->key.share1, rsp->digest_share1, OT_KMAC_KEY_SIZE);
+    dst_slot->max_key_version = max_key_version;
+    dst_slot->boot_stage = src_slot->boot_stage + 1u;
+    dst_slot->policy.allow_child =
+        (bool)(slot_policy & R_SLOT_POLICY_ALLOW_CHILD_MASK);
+    dst_slot->policy.exportable =
+        (bool)(slot_policy & R_SLOT_POLICY_EXPORTABLE_MASK);
+    dst_slot->policy.retain_parent =
+        (bool)(slot_policy & R_SLOT_POLICY_RETAIN_PARENT_MASK);
+
+    /*
+     * Unlock `SW_BINDING`, `SLOT_POLICY` and `MAX_KEY_VERSION` registers
+     * after succesful advance
+     */
+    s->regs[R_SW_BINDING_REGWEN] |= R_SW_BINDING_REGWEN_EN_MASK;
+    s->regs[R_SLOT_POLICY_REGWEN] |= R_SLOT_POLICY_REGWEN_EN_MASK;
+    s->regs[R_MAX_KEY_VER_REGWEN] |= R_MAX_KEY_VER_REGWEN_EN_MASK;
+
+    return true;
+}
+
+static bool ot_keymgr_dpe_handle_kmac_resp_gen_hw_out(
+    OtKeyMgrDpeState *s, uint8_t dest_sel, const OtKMACAppRsp *rsp)
+{
+    switch (dest_sel) {
+    case KEYMGR_DPE_DEST_SEL_VALUE_AES:
+    case KEYMGR_DPE_DEST_SEL_VALUE_KMAC:
+    case KEYMGR_DPE_DEST_SEL_VALUE_OTBN: {
+        OtKeyMgrDpeKeySink key_sink = dest_sel - KEY_SINK_OFFSET;
+        ot_keymgr_dpe_push_key(s, key_sink, rsp->digest_share0,
+                               rsp->digest_share1, true);
+        return dest_sel != KEYMGR_DPE_DEST_SEL_VALUE_KMAC;
+    }
+    case KEYMGR_DPE_DEST_SEL_VALUE_NONE:
+        /* no output, just ack the operation */
+        return true;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static bool ot_keymgr_dpe_handle_kmac_resp_gen_sw_out(OtKeyMgrDpeState *s,
+                                                      const OtKMACAppRsp *rsp)
+{
+    memcpy(s->sw_out_key->share0, rsp->digest_share0, OT_KMAC_KEY_SIZE);
+    memcpy(s->sw_out_key->share1, rsp->digest_share1, OT_KMAC_KEY_SIZE);
+    s->sw_out_key->valid = true;
+    return true;
+}
+
+static void
+ot_keymgr_dpe_handle_kmac_response(void *opaque, const OtKMACAppRsp *rsp)
+{
+    OtKeyMgrDpeState *s = OT_KEYMGR_DPE(opaque);
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    bool reset_kmac_key = true;
+
+    if (trace_event_get_state(TRACE_OT_KEYMGR_DPE_KMAC_RSP)) {
+        if (rsp->done) {
+            uint8_t key[OT_KMAC_APP_DIGEST_BYTES];
+            for (unsigned ix = 0u; ix < OT_KMAC_APP_DIGEST_BYTES; ix++) {
+                key[ix] = rsp->digest_share0[ix] ^ rsp->digest_share1[ix];
+            }
+            trace_ot_keymgr_dpe_kmac_rsp(
+                s->ot_id, true,
+                ot_keymgr_dpe_dump_bigint(s, key, OT_KMAC_APP_DIGEST_BYTES));
+        } else {
+            trace_ot_keymgr_dpe_kmac_rsp(s->ot_id, false, "");
+        }
+    }
+
+    if (!rsp->done) {
+        /* not last response from KMAC, send more data */
+        ot_keymgr_dpe_send_kmac_req(s);
+        return;
+    }
+
+    g_assert(s->kdf_buf.offset == s->kdf_buf.length);
+
+    switch (FIELD_EX32(ctrl, CONTROL_SHADOWED, OPERATION)) {
+    case KEYMGR_DPE_OP_ADVANCE: {
+        uint8_t slot_src_sel =
+            (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, SLOT_SRC_SEL);
+        uint8_t slot_dst_sel =
+            (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, SLOT_DST_SEL);
+        reset_kmac_key =
+            ot_keymgr_dpe_handle_kmac_resp_advance(s, slot_src_sel,
+                                                   slot_dst_sel, rsp);
+        break;
+    }
+    case KEYMGR_DPE_OP_GENERATE_HW_OUTPUT: {
+        uint8_t dest_sel =
+            (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, DEST_SEL);
+        reset_kmac_key =
+            ot_keymgr_dpe_handle_kmac_resp_gen_hw_out(s, dest_sel, rsp);
+        break;
+    }
+    case KEYMGR_DPE_OP_GENERATE_SW_OUTPUT:
+        reset_kmac_key = ot_keymgr_dpe_handle_kmac_resp_gen_sw_out(s, rsp);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    /* reset KMAC key if required */
+    if (reset_kmac_key) {
+        /* TODO: maybe push last sideloaded KMAC key instead? */
+        trace_ot_keymgr_dpe_reset_kmac_key(s->ot_id);
+        ot_keymgr_dpe_push_key(s, KEYMGR_DPE_KEY_SINK_KMAC, NULL, NULL, false);
+    }
+
+    /* operation complete */
+    s->op_state.op_ack = true;
+    ot_keymgr_dpe_schedule_fsm(s);
+}
+
+/* check that 'data' is not all zeros or all ones */
+static bool ot_keymgr_dpe_valid_data_check(const uint8_t *data, size_t len)
+{
+    size_t popcount = 0u;
+    for (unsigned ix = 0u; ix < len; ix++) {
+        popcount += __builtin_popcount(data[ix]);
+    }
+    return (popcount && popcount != (len * BITS_PER_BYTE));
+}
+
+static void ot_keymgr_dpe_reset_kdf_buffer(OtKeyMgrDpeState *s)
+{
+    memset(s->kdf_buf.data, 0u, KEYMGR_DPE_KDF_BUFFER_BYTES);
+    s->kdf_buf.offset = 0u;
+    s->kdf_buf.length = 0u;
+}
+
+static void ot_keymgr_dpe_kdf_push_bytes(OtKeyMgrDpeState *s,
+                                         const uint8_t *data, size_t len)
+{
+    g_assert(s->kdf_buf.length + len <= KEYMGR_DPE_KDF_BUFFER_BYTES);
+
+    memcpy(&s->kdf_buf.data[s->kdf_buf.length], data, len);
+    s->kdf_buf.length += len;
+}
+
+static void G_GNUC_PRINTF(4, 5)
+    ot_keymgr_dpe_dump_kdf_material(const OtKeyMgrDpeState *s,
+                                    const uint8_t *buf, size_t len,
+                                    const char *fmt, ...)
+{
+    if (trace_event_get_state(TRACE_OT_KEYMGR_DPE_DUMP_KDF_MATERIAL)) {
+        va_list args;
+        va_start(args, fmt);
+        char *what = g_strdup_vprintf(fmt, args);
+        va_end(args);
+        const char *hexstr = ot_keymgr_dpe_dump_bigint(s, buf, len);
+        trace_ot_keymgr_dpe_dump_kdf_material(s->ot_id, what, hexstr);
+        g_free(what);
+    }
+}
+
+static void ot_keymgr_dpe_kdf_push_key_version(OtKeyMgrDpeState *s)
+{
+    uint8_t buf[sizeof(uint32_t)];
+    stl_le_p(buf, s->regs[R_KEY_VERSION]);
+    ot_keymgr_dpe_kdf_push_bytes(s, buf, sizeof(uint32_t));
+
+    ot_keymgr_dpe_dump_kdf_material(s, buf, sizeof(uint32_t), "KEY_VERSION");
+}
+
+static size_t
+ot_keymgr_dpe_kdf_append_creator_seed(OtKeyMgrDpeState *s, bool *dvalid)
+{
+    OtOTPKeyMgrSecret secret = { 0u };
+
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+    oc->get_keymgr_secret(oi, OT_OTP_KEYMGR_SECRET_CREATOR_SEED, &secret);
+
+    ot_keymgr_dpe_kdf_push_bytes(s, secret.secret, OT_OTP_KEYMGR_SECRET_SIZE);
+    *dvalid &= ot_keymgr_dpe_valid_data_check(secret.secret,
+                                              OT_OTP_KEYMGR_SECRET_SIZE);
+
+    ot_keymgr_dpe_dump_kdf_material(s, secret.secret, OT_OTP_KEYMGR_SECRET_SIZE,
+                                    "CREATOR_SEED");
+    return OT_OTP_KEYMGR_SECRET_SIZE;
+}
+
+static size_t ot_keymgr_dpe_kdf_append_rom_digest(
+    OtKeyMgrDpeState *s, unsigned rom_idx, bool *dvalid)
+{
+    uint8_t rom_digest[OT_ROM_DIGEST_BYTES] = { 0u };
+
+    OtRomCtrlClass *rcc = OT_ROM_CTRL_GET_CLASS(s->rom_ctrl[rom_idx]);
+    rcc->get_rom_digest(s->rom_ctrl[rom_idx], rom_digest);
+
+    ot_keymgr_dpe_kdf_push_bytes(s, rom_digest, OT_ROM_DIGEST_BYTES);
+    *dvalid &= ot_keymgr_dpe_valid_data_check(rom_digest, OT_ROM_DIGEST_BYTES);
+
+    ot_keymgr_dpe_dump_kdf_material(s, rom_digest, OT_ROM_DIGEST_BYTES,
+                                    "ROM%u_DIGEST", rom_idx);
+
+    return OT_ROM_DIGEST_BYTES;
+}
+
+static size_t ot_keymgr_dpe_kdf_append_km_div(OtKeyMgrDpeState *s, bool *dvalid)
+{
+    OtLcCtrlKeyMgrDiv km_div = { 0u };
+
+    OtLcCtrlClass *lc = OT_LC_CTRL_GET_CLASS(s->lc_ctrl);
+    lc->get_keymgr_div(s->lc_ctrl, &km_div);
+
+    ot_keymgr_dpe_kdf_push_bytes(s, km_div.data, OT_LC_KEYMGR_DIV_BYTES);
+    *dvalid &=
+        ot_keymgr_dpe_valid_data_check(km_div.data, OT_LC_KEYMGR_DIV_BYTES);
+
+    ot_keymgr_dpe_dump_kdf_material(s, km_div.data, OT_LC_KEYMGR_DIV_BYTES,
+                                    "KM_DIV");
+    return OT_LC_KEYMGR_DIV_BYTES;
+}
+
+static size_t ot_keymgr_dpe_kdf_append_dev_id(OtKeyMgrDpeState *s, bool *dvalid)
+{
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+    const OtOTPHWCfg *hw_cfg = oc->get_hw_cfg(oi);
+
+    ot_keymgr_dpe_kdf_push_bytes(s, hw_cfg->device_id,
+                                 OT_OTP_HWCFG_DEVICE_ID_BYTES);
+    *dvalid &= ot_keymgr_dpe_valid_data_check(hw_cfg->device_id,
+                                              OT_OTP_HWCFG_DEVICE_ID_BYTES);
+
+    ot_keymgr_dpe_dump_kdf_material(s, hw_cfg->device_id,
+                                    OT_OTP_HWCFG_DEVICE_ID_BYTES, "DEVICE_ID");
+    return OT_OTP_HWCFG_DEVICE_ID_BYTES;
+}
+
+static size_t ot_keymgr_dpe_kdf_append_rev_seed(OtKeyMgrDpeState *s)
+{
+    ot_keymgr_dpe_kdf_push_bytes(s, s->seeds[KEYMGR_DPE_SEED_REV],
+                                 KEYMGR_DPE_SEED_BYTES);
+
+    ot_keymgr_dpe_dump_kdf_material(s, s->seeds[KEYMGR_DPE_SEED_REV],
+                                    KEYMGR_DPE_SEED_BYTES, "REV_SEED");
+
+    return KEYMGR_DPE_SEED_BYTES;
+}
+
+static size_t
+ot_keymgr_dpe_kdf_append_owner_seed(OtKeyMgrDpeState *s, bool *dvalid)
+{
+    OtOTPKeyMgrSecret secret = { 0u };
+
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+    oc->get_keymgr_secret(oi, OT_OTP_KEYMGR_SECRET_OWNER_SEED, &secret);
+
+    ot_keymgr_dpe_kdf_push_bytes(s, secret.secret, OT_OTP_KEYMGR_SECRET_SIZE);
+    *dvalid &= ot_keymgr_dpe_valid_data_check(secret.secret,
+                                              OT_OTP_KEYMGR_SECRET_SIZE);
+
+    ot_keymgr_dpe_dump_kdf_material(s, secret.secret, OT_OTP_KEYMGR_SECRET_SIZE,
+                                    "OWNER_SEED");
+    return OT_OTP_KEYMGR_SECRET_SIZE;
+}
+
+static void ot_keymgr_dpe_operation_advance(OtKeyMgrDpeState *s)
+{
+    bool dvalid = true;
+
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    uint8_t slot_dst_sel =
+        (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, SLOT_DST_SEL);
+    uint8_t slot_src_sel =
+        (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, SLOT_SRC_SEL);
+    OtKeyMgrDpeSlot *src_slot = &s->key_slots[slot_src_sel];
+    OtKeyMgrDpeSlot *dst_slot = &s->key_slots[slot_dst_sel];
+
+    bool invalid_allow_child = !src_slot->policy.allow_child;
+    bool invalid_max_boot_stage =
+        src_slot->boot_stage >= (NUM_BOOT_STAGES - 1u);
+    bool invalid_src_slot = !src_slot->valid;
+    bool invalid_retain_parent =
+        src_slot->policy.retain_parent ?
+            (slot_src_sel == slot_dst_sel || dst_slot->valid) :
+            (slot_src_sel != slot_dst_sel);
+
+    /* TODO trigger error */
+    (void)(invalid_allow_child || invalid_max_boot_stage || invalid_src_slot ||
+           invalid_retain_parent);
+
+    ot_keymgr_dpe_reset_kdf_buffer(s);
+
+    size_t expected_kdf_len = 0u;
+
+    switch (src_slot->boot_stage) {
+    /* Creator */
+    case 0u: {
+        /* Creator Seed (OTP) */
+        expected_kdf_len += ot_keymgr_dpe_kdf_append_creator_seed(s, &dvalid);
+
+        /* ROM digests (ROM_CTRL) */
+        for (unsigned ix = 0u; ix < NUM_ROM_DIGEST_INPUTS; ix++) {
+            expected_kdf_len +=
+                ot_keymgr_dpe_kdf_append_rom_digest(s, ix, &dvalid);
+        }
+
+        /* KeyManager diversification (LC_CTRL) */
+        expected_kdf_len += ot_keymgr_dpe_kdf_append_km_div(s, &dvalid);
+
+        /* Device ID (OTP) */
+        expected_kdf_len += ot_keymgr_dpe_kdf_append_dev_id(s, &dvalid);
+
+        /* Revision Seed (netlist constant) */
+        expected_kdf_len += ot_keymgr_dpe_kdf_append_rev_seed(s);
+
+        break;
+    }
+    /* OwnerInt */
+    case 1u: {
+        /* Owner Seed (OTP) */
+        expected_kdf_len += ot_keymgr_dpe_kdf_append_owner_seed(s, &dvalid);
+
+        break;
+    }
+    default:
+        break;
+    }
+
+    /* Software Binding (software-provided via SW_BINDING_x registers) */
+    ot_keymgr_dpe_kdf_push_bytes(s, s->sw_binding,
+                                 NUM_SW_BINDING_REG * sizeof(uint32_t));
+    expected_kdf_len += NUM_SW_BINDING_REG * sizeof(uint32_t);
+    ot_keymgr_dpe_dump_kdf_material(s, s->sw_binding,
+                                    NUM_SW_BINDING_REG * sizeof(uint32_t),
+                                    "SW_BINDING");
+
+    /* check that we have pushed all expected KDF data*/
+    g_assert(s->kdf_buf.length == expected_kdf_len);
+
+    /*
+     * @todo store `dvalid` somewhere and, if the data is invalid, replace the
+     * kmac response with decoy data (random permutation of entropy share 1).
+     */
+    if (!dvalid) {
+        s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_KMAC_INPUT_MASK;
+    }
+
+    g_assert(s->kdf_buf.length <= KEYMGR_DPE_ADV_DATA_BYTES);
+    s->kdf_buf.length = KEYMGR_DPE_ADV_DATA_BYTES;
+
+    ot_keymgr_dpe_kmac_push_key(s);
+
+    ot_keymgr_dpe_dump_kdf_buf(s, "adv");
+    ot_keymgr_dpe_send_kmac_req(s);
+}
+
+static void ot_keymgr_dpe_operation_erase_slot(OtKeyMgrDpeState *s)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    uint8_t slot_dst_sel =
+        (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, SLOT_DST_SEL);
+    OtKeyMgrDpeSlot *dst_slot = &s->key_slots[slot_dst_sel];
+
+    bool invalid_erase = !dst_slot->valid;
+
+    /* TODO trigger error */
+    (void)invalid_erase;
+
+    memset(dst_slot, 0u, sizeof(OtKeyMgrDpeSlot));
+
+    s->op_state.op_ack = true;
+    ot_keymgr_dpe_schedule_fsm(s);
+}
+
+static void ot_keymgr_dpe_operation_gen_output(OtKeyMgrDpeState *s, bool sw)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    uint8_t dest_sel = (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, DEST_SEL);
+    uint8_t slot_src_sel =
+        (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, SLOT_SRC_SEL);
+    OtKeyMgrDpeSlot *src_slot = &s->key_slots[slot_src_sel];
+
+    ot_keymgr_dpe_reset_kdf_buffer(s);
+
+    if (src_slot->valid) {
+        /* Output Key Seed (SW/HW key) */
+        uint8_t *output_key = sw ? s->seeds[KEYMGR_DPE_SEED_SW_OUT] :
+                                   s->seeds[KEYMGR_DPE_SEED_HW_OUT];
+        ot_keymgr_dpe_kdf_push_bytes(s, output_key, KEYMGR_DPE_SEED_BYTES);
+        ot_keymgr_dpe_dump_kdf_material(s, output_key, KEYMGR_DPE_SEED_BYTES,
+                                        "OUT_KEY_SEED");
+
+        /* Destination Seed (AES/KMAC/OTBN/other) */
+        uint8_t *dest_seed;
+        switch (dest_sel) {
+        case KEYMGR_DPE_DEST_SEL_VALUE_AES:
+            dest_seed = s->seeds[KEYMGR_DPE_SEED_AES];
+            break;
+        case KEYMGR_DPE_DEST_SEL_VALUE_KMAC:
+            dest_seed = s->seeds[KEYMGR_DPE_SEED_KMAC];
+            break;
+        case KEYMGR_DPE_DEST_SEL_VALUE_OTBN:
+            dest_seed = s->seeds[KEYMGR_DPE_SEED_OTBN];
+            break;
+        case KEYMGR_DPE_DEST_SEL_VALUE_NONE:
+        default:
+            dest_seed = s->seeds[KEYMGR_DPE_SEED_NONE];
+            break;
+        }
+        ot_keymgr_dpe_kdf_push_bytes(s, dest_seed, KEYMGR_DPE_SEED_BYTES);
+        ot_keymgr_dpe_dump_kdf_material(s, dest_seed, KEYMGR_DPE_SEED_BYTES,
+                                        "DEST_SEED");
+
+        /* Salt (software-provided via SALT_x registers) */
+        ot_keymgr_dpe_kdf_push_bytes(s, s->salt,
+                                     NUM_SALT_REG * sizeof(uint32_t));
+        ot_keymgr_dpe_dump_kdf_material(s, s->salt,
+                                        NUM_SALT_REG * sizeof(uint32_t),
+                                        "SALT");
+
+        /* Key Version (software-provided via KEY_VERSION register) */
+        ot_keymgr_dpe_kdf_push_key_version(s);
+    } else {
+        /* active key slot is not valid, push random data */
+        unsigned count = KEYMGR_DPE_GEN_DATA_BYTES / sizeof(uint32_t);
+        while (count--) {
+            uint32_t data = ot_prng_random_u32(s->prng.state);
+            ot_keymgr_dpe_kdf_push_bytes(s, (uint8_t *)&data, sizeof(data));
+        }
+    }
+
+    bool key_version_valid =
+        s->regs[R_KEY_VERSION] <= src_slot->max_key_version;
+
+    /* TODO trigger error */
+    (void)key_version_valid;
+
+    g_assert(s->kdf_buf.length == KEYMGR_DPE_GEN_DATA_BYTES);
+
+    ot_keymgr_dpe_kmac_push_key(s);
+
+    ot_keymgr_dpe_dump_kdf_buf(s, "gen");
+    ot_keymgr_dpe_send_kmac_req(s);
+}
+
+static void ot_keymgr_dpe_operation_sw_output(OtKeyMgrDpeState *s)
+{
+    ot_keymgr_dpe_operation_gen_output(s, true);
+}
+
+static void ot_keymgr_dpe_operation_hw_output(OtKeyMgrDpeState *s)
+{
+    ot_keymgr_dpe_operation_gen_output(s, false);
+}
+
+static void ot_keymgr_dpe_operation_disable(OtKeyMgrDpeState *s)
+{
+    /* TODO implement */
+    s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+    s->op_state.op_ack = true;
+    ot_keymgr_dpe_schedule_fsm(s);
+}
+
+static void ot_keymgr_dpe_start_operation(OtKeyMgrDpeState *s)
+{
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    int op = (int)FIELD_EX32(ctrl, CONTROL_SHADOWED, OPERATION);
+
+    trace_ot_keymgr_dpe_operation(s->ot_id, OP_NAME(op), op);
+
+    switch (op) {
+    case KEYMGR_DPE_OP_ADVANCE:
+        ot_keymgr_dpe_operation_advance(s);
+        break;
+    case KEYMGR_DPE_OP_ERASE_SLOT:
+        ot_keymgr_dpe_operation_erase_slot(s);
+        break;
+    case KEYMGR_DPE_OP_GENERATE_SW_OUTPUT:
+        ot_keymgr_dpe_operation_sw_output(s);
+        break;
+    case KEYMGR_DPE_OP_GENERATE_HW_OUTPUT:
+        ot_keymgr_dpe_operation_hw_output(s);
+        break;
+    case KEYMGR_DPE_OP_DISABLE:
+        ot_keymgr_dpe_operation_disable(s);
+        break;
+    default:
+        s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+        s->op_state.op_ack = true;
+        ot_keymgr_dpe_schedule_fsm(s);
+        break;
+    }
+}
+
+static void ot_keymgr_dpe_sideload_clear(OtKeyMgrDpeState *s)
+{
+    uint32_t sl_clear =
+        FIELD_EX32(s->regs[R_SIDELOAD_CLEAR], SIDELOAD_CLEAR, VAL);
+
+    trace_ot_keymgr_dpe_sideload_clear(s->ot_id, SIDELOAD_CLEAR_NAME(sl_clear),
+                                       sl_clear);
+
+    uint32_t bm;
+    switch ((int)sl_clear) {
+    case KEYMGR_DPE_SIDELOAD_CLEAR_NONE:
+        /* nothing to clear, exit */
+        return;
+    case KEYMGR_DPE_SIDELOAD_CLEAR_AES:
+    case KEYMGR_DPE_SIDELOAD_CLEAR_OTBN:
+    case KEYMGR_DPE_SIDELOAD_CLEAR_KMAC:
+        bm = 1u << (sl_clear - KEY_SINK_OFFSET);
+        break;
+    default:
+        /*
+         * "If the value programmed is not one of the enumerated values below,
+         * ALL sideload key slots are continuously cleared."
+         */
+        bm = (1u << KEYMGR_DPE_KEY_SINK_COUNT) - 1u;
+        break;
+    }
+
+    uint8_t share0[KEYMGR_DPE_KEY_SIZE_MAX];
+    uint8_t share1[KEYMGR_DPE_KEY_SIZE_MAX];
+
+    for (unsigned kix = 0; bm && kix < KEYMGR_DPE_KEY_SINK_COUNT; kix++) {
+        if (bm & (1u << kix)) {
+            bm &= ~(1u << kix);
+
+            DeviceState *sink = s->key_sinks[kix];
+            if (!sink) {
+                continue;
+            }
+
+            OtKeySinkIfClass *kc = OT_KEY_SINK_IF_GET_CLASS(sink);
+            OtKeySinkIf *ki = OT_KEY_SINK_IF(sink);
+
+            g_assert(kc->push_key);
+
+            size_t key_size = OT_KEY_MGR_DPE_KEY_SINK_SIZES[kix];
+
+            /* TODO this needs to use random data */
+            memset(share0, 0, key_size);
+            memset(share1, 0, key_size);
+
+            kc->push_key(ki, share0, share1, key_size, false);
+        }
+    }
+}
+
+static void ot_keymgr_dpe_lc_signal(void *opaque, int irq, int level)
+{
+    OtKeyMgrDpeState *s = opaque;
+    bool enable_keymgr = (bool)level;
+
+    g_assert(irq == 0);
+
+    trace_ot_keymgr_dpe_lc_signal(s->ot_id, level);
+
+    bool changed = enable_keymgr ^ s->enabled;
+    if (!changed) {
+        /* no change, exit */
+        return;
+    }
+
+    s->enabled = enable_keymgr;
+
+    if (s->enabled) {
+        s->regs[R_DEBUG] &= ~R_DEBUG_INACTIVE_LC_EN_MASK;
+        s->regs[R_CFG_REGWEN] |= R_CFG_REGWEN_EN_MASK;
+    } else {
+        s->regs[R_DEBUG] |= R_DEBUG_INACTIVE_LC_EN_MASK;
+        s->regs[R_CFG_REGWEN] &= ~R_CFG_REGWEN_EN_MASK;
+    }
+
+    ot_keymgr_dpe_schedule_fsm(s);
+}
+
+#define ot_keymgr_dpe_change_main_fsm_state(_s_, _op_status_) \
+    ot_keymgr_dpe_xchange_main_fsm_state(_s_, _op_status_, __LINE__)
+
+static void ot_keymgr_dpe_xchange_main_fsm_state(
+    OtKeyMgrDpeState *s, OtKeyMgrDpeFSMState state, int line)
+{
+    if (s->state != state) {
+        trace_ot_keymgr_dpe_change_main_fsm_state(s->ot_id, line,
+                                                  FST_NAME(s->state), s->state,
+                                                  FST_NAME(state), state);
+        s->state = state;
+    }
+}
+
+static void ot_keymgr_dpe_get_root_key(
+    OtKeyMgrDpeState *s, OtOTPKeyMgrSecret *share0, OtOTPKeyMgrSecret *share1)
+{
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+    oc->get_keymgr_secret(oi, OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE0,
+                          share0);
+    oc->get_keymgr_secret(oi, OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE1,
+                          share1);
+
+    if (trace_event_get_state(TRACE_OT_KEYMGR_DPE_DUMP_CREATOR_ROOT_KEY)) {
+        trace_ot_keymgr_dpe_dump_creator_root_key(
+            s->ot_id, 0, share0->valid,
+            ot_keymgr_dpe_dump_bigint(s, share0->secret,
+                                      OT_OTP_KEYMGR_SECRET_SIZE));
+        trace_ot_keymgr_dpe_dump_creator_root_key(
+            s->ot_id, 1, share1->valid,
+            ot_keymgr_dpe_dump_bigint(s, share1->secret,
+                                      OT_OTP_KEYMGR_SECRET_SIZE));
+    }
+}
+
+static bool ot_keymgr_dpe_main_fsm_tick(OtKeyMgrDpeState *s)
+{
+    OtKeyMgrDpeFSMState state = s->state;
+    bool op_start = s->regs[R_START] & R_START_EN_MASK;
+    bool invalid_state = s->regs[R_FAULT_STATUS] & FAULT_STATUS_MASK;
+    bool init = false;
+    uint32_t ctrl = ot_shadow_reg_peek(&s->control);
+    uint8_t slot_dst_sel =
+        (uint8_t)FIELD_EX32(ctrl, CONTROL_SHADOWED, SLOT_DST_SEL);
+    OtKeyMgrDpeSlot *dst_slot = &s->key_slots[slot_dst_sel];
+
+    trace_ot_keymgr_dpe_main_fsm_tick(s->ot_id, FST_NAME(s->state), s->state);
+
+    switch (s->state) {
+    case KEYMGR_DPE_ST_RESET:
+        ot_keymgr_dpe_change_working_state(s, KEYMGR_DPE_WORKING_STATE_RESET);
+        if (invalid_state) {
+            ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_INVALID);
+        }
+        if (!op_start) {
+            break;
+        }
+        bool op_advance = FIELD_EX32(ctrl, CONTROL_SHADOWED, OPERATION) ==
+                          KEYMGR_DPE_OP_ADVANCE;
+        if (!s->enabled || !op_advance) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+        } else if (!invalid_state) {
+            ot_keymgr_dpe_change_main_fsm_state(s,
+                                                KEYMGR_DPE_ST_ENTROPY_RESEED);
+        }
+        break;
+    case KEYMGR_DPE_ST_ENTROPY_RESEED:
+        ot_keymgr_dpe_change_working_state(s, KEYMGR_DPE_WORKING_STATE_RESET);
+        if (!s->enabled) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+            ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_INVALID);
+        } else if (!s->prng.reseed_req) {
+            s->prng.reseed_ack = false;
+            s->prng.reseed_req = true;
+            ot_keymgr_dpe_request_entropy(s);
+        } else if (s->prng.reseed_ack) {
+            s->prng.reseed_req = true;
+            ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_RANDOM);
+        }
+        break;
+    case KEYMGR_DPE_ST_RANDOM:
+        ot_keymgr_dpe_change_working_state(s, KEYMGR_DPE_WORKING_STATE_RESET);
+        if (!s->enabled) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+            ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_INVALID);
+        } else {
+            /* current RTL only initializes slot 'slot_dst_sel' with 0s */
+            memset(dst_slot, 0u, sizeof(OtKeyMgrDpeSlot));
+            ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_ROOTKEY);
+        }
+        break;
+    case KEYMGR_DPE_ST_ROOTKEY:
+        ot_keymgr_dpe_change_working_state(s, KEYMGR_DPE_WORKING_STATE_RESET);
+        if (!s->enabled) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+        }
+        if (!s->enabled || invalid_state) {
+            ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_INVALID);
+        } else {
+            init = true;
+
+            /* retrieve Creator Root Key from OTP */
+            OtOTPKeyMgrSecret secret_share0 = { 0u };
+            OtOTPKeyMgrSecret secret_share1 = { 0u };
+            ot_keymgr_dpe_get_root_key(s, &secret_share0, &secret_share1);
+
+            if (secret_share0.valid && secret_share1.valid) {
+                memset(dst_slot, 0u, sizeof(OtKeyMgrDpeSlot));
+                dst_slot->valid = true;
+                dst_slot->boot_stage = 0u;
+                memcpy(dst_slot->key.share0, secret_share0.secret,
+                       OT_OTP_KEYMGR_SECRET_SIZE);
+                memcpy(dst_slot->key.share1, secret_share1.secret,
+                       OT_OTP_KEYMGR_SECRET_SIZE);
+                dst_slot->max_key_version = ot_shadow_reg_peek(&s->max_key_ver);
+                dst_slot->policy = DEFAULT_UDS_POLICY;
+
+                ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_AVAILABLE);
+            } else {
+                s->regs[R_DEBUG] |= R_DEBUG_INVALID_ROOT_KEY_MASK;
+
+                ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_INVALID);
+            }
+        }
+        break;
+    case KEYMGR_DPE_ST_AVAILABLE:
+        ot_keymgr_dpe_change_working_state(s,
+                                           KEYMGR_DPE_WORKING_STATE_AVAILABLE);
+        if (invalid_state) {
+            ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_WIPE);
+        }
+        if (!op_start) {
+            /* no state change if op_start is not set */
+            break;
+        }
+        if (!s->enabled) {
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_OP_MASK;
+            /*
+             * Given that the root key was latched by an earlier FSM state, we
+             * need to take care of clearing the sensitive root key.
+             */
+            ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_WIPE);
+        } else if (!invalid_state && !s->op_state.op_req) {
+            s->op_state.op_req = true;
+            ot_keymgr_dpe_start_operation(s);
+        }
+        break;
+    case KEYMGR_DPE_ST_WIPE:
+        ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_DISABLING);
+        break;
+    case KEYMGR_DPE_ST_DISABLING:
+        /* TODO wipe before going to disabled state */
+        ot_keymgr_dpe_change_main_fsm_state(s, KEYMGR_DPE_ST_DISABLED);
+        break;
+    case KEYMGR_DPE_ST_DISABLED:
+        ot_keymgr_dpe_change_working_state(s,
+                                           KEYMGR_DPE_WORKING_STATE_DISABLED);
+        break;
+    case KEYMGR_DPE_ST_INVALID:
+    default:
+        ot_keymgr_dpe_change_working_state(s, KEYMGR_DPE_WORKING_STATE_INVALID);
+        break;
+    }
+
+    /* last requested operation status */
+    bool invalid_op = (bool)(s->regs[R_ERR_CODE] & R_ERR_CODE_INVALID_OP_MASK);
+    bool op_done =
+        s->op_state.op_req ? s->op_state.op_ack : (init || invalid_op);
+    if (op_done) {
+        s->op_state.op_req = false;
+        s->op_state.op_ack = false;
+        s->regs[R_START] &= ~R_START_EN_MASK;
+        if (s->regs[R_ERR_CODE] | s->regs[R_FAULT_STATUS]) {
+            ot_keymgr_dpe_update_alert(s);
+            ot_keymgr_dpe_change_op_status(s, KEYMGR_DPE_OP_STATUS_DONE_ERROR);
+        } else {
+            ot_keymgr_dpe_change_op_status(s,
+                                           KEYMGR_DPE_OP_STATUS_DONE_SUCCESS);
+        }
+    } else if (op_start) {
+        ot_keymgr_dpe_change_op_status(s, KEYMGR_DPE_OP_STATUS_WIP);
+    } else {
+        ot_keymgr_dpe_change_op_status(s, KEYMGR_DPE_OP_STATUS_IDLE);
+    }
+
+    /* lock CFG_REGWEN when an operation is ongoing */
+    if (s->enabled && op_start) {
+        if (op_done) {
+            s->regs[R_CFG_REGWEN] |= R_CFG_REGWEN_EN_MASK;
+        } else {
+            s->regs[R_CFG_REGWEN] &= ~R_CFG_REGWEN_EN_MASK;
+        }
+    }
+
+    return state != s->state;
+}
+
+static void ot_keymgr_dpe_fsm_tick(void *opaque)
+{
+    OtKeyMgrDpeState *s = opaque;
+
+    if (ot_keymgr_dpe_main_fsm_tick(s)) {
+        /* schedule FSM update once more if its state has changed */
+        ot_keymgr_dpe_schedule_fsm(s);
+    } else {
+        /* otherwise, go idle and wait for an external event */
+        trace_ot_keymgr_dpe_go_idle(s->ot_id);
+    }
+}
+
+#define ot_keymgr_dpe_check_reg_write(_s_, _reg_, _regwen_) \
+    ot_keymgr_dpe_check_reg_write_func(__func__, _s_, _reg_, _regwen_)
+
+static inline bool ot_keymgr_dpe_check_reg_write_func(
+    const char *func, OtKeyMgrDpeState *s, hwaddr reg, hwaddr regwen)
+{
+    if (!s->regs[regwen]) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to %s protected with %s\n",
+                      func, REG_NAME(reg), REG_NAME(regwen));
+        return false;
+    }
+
+    return true;
+}
+
+static uint64_t ot_keymgr_dpe_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtKeyMgrDpeState *s = opaque;
+    (void)size;
+
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_CFG_REGWEN:
+    case R_START:
+    case R_SIDELOAD_CLEAR:
+    case R_RESEED_INTERVAL_REGWEN:
+    case R_SLOT_POLICY_REGWEN:
+    case R_SLOT_POLICY:
+    case R_SW_BINDING_REGWEN:
+    case R_KEY_VERSION:
+    case R_MAX_KEY_VER_REGWEN:
+    case R_WORKING_STATE:
+    case R_OP_STATUS:
+    case R_ERR_CODE:
+    case R_FAULT_STATUS:
+    case R_DEBUG:
+        val32 = s->regs[reg];
+        break;
+    case R_CONTROL_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->control);
+        break;
+    case R_RESEED_INTERVAL_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->reseed_interval);
+        break;
+    case R_MAX_KEY_VER_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->max_key_ver);
+        break;
+    case R_SW_BINDING_0:
+    case R_SW_BINDING_1:
+    case R_SW_BINDING_2:
+    case R_SW_BINDING_3:
+    case R_SW_BINDING_4:
+    case R_SW_BINDING_5:
+    case R_SW_BINDING_6:
+    case R_SW_BINDING_7: {
+        unsigned offset = (reg - R_SW_BINDING_0) * sizeof(uint32_t);
+        val32 = ldl_le_p(&s->sw_binding[offset]);
+        break;
+    }
+    case R_SALT_0:
+    case R_SALT_1:
+    case R_SALT_2:
+    case R_SALT_3:
+    case R_SALT_4:
+    case R_SALT_5:
+    case R_SALT_6:
+    case R_SALT_7: {
+        unsigned offset = (reg - R_SALT_0) * sizeof(uint32_t);
+        val32 = ldl_le_p(&s->salt[offset]);
+        break;
+    }
+    case R_SW_SHARE0_OUTPUT_0:
+    case R_SW_SHARE0_OUTPUT_1:
+    case R_SW_SHARE0_OUTPUT_2:
+    case R_SW_SHARE0_OUTPUT_3:
+    case R_SW_SHARE0_OUTPUT_4:
+    case R_SW_SHARE0_OUTPUT_5:
+    case R_SW_SHARE0_OUTPUT_6:
+    case R_SW_SHARE0_OUTPUT_7: {
+        /* TODO should this depend on the current state? */
+        unsigned offset = (reg - R_SW_SHARE0_OUTPUT_0) * sizeof(uint32_t);
+        void *ptr = &s->sw_out_key->share0[offset];
+        val32 = ldl_le_p(ptr);
+        stl_le_p(ptr, 0u); /* RC */
+        break;
+    }
+    case R_SW_SHARE1_OUTPUT_0:
+    case R_SW_SHARE1_OUTPUT_1:
+    case R_SW_SHARE1_OUTPUT_2:
+    case R_SW_SHARE1_OUTPUT_3:
+    case R_SW_SHARE1_OUTPUT_4:
+    case R_SW_SHARE1_OUTPUT_5:
+    case R_SW_SHARE1_OUTPUT_6:
+    case R_SW_SHARE1_OUTPUT_7: {
+        /* TODO should this depend on the current state? */
+        unsigned offset = (reg - R_SW_SHARE1_OUTPUT_0) * sizeof(uint32_t);
+        void *ptr = &s->sw_out_key->share1[offset];
+        val32 = ldl_le_p(ptr);
+        stl_le_p(ptr, 0u); /* RC */
+        break;
+    }
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0u;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0u;
+        break;
+    }
+
+    uint64_t pc = ibex_get_current_pc();
+    trace_ot_keymgr_dpe_io_read_out(s->ot_id, (unsigned)addr, REG_NAME(reg),
+                                    (uint64_t)val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_keymgr_dpe_write(void *opaque, hwaddr addr, uint64_t val64,
+                                unsigned size)
+{
+    OtKeyMgrDpeState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint64_t pc = ibex_get_current_pc();
+    trace_ot_keymgr_dpe_io_write(s->ot_id, (unsigned)addr, REG_NAME(reg), val64,
+                                 pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_keymgr_dpe_update_irq(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[reg] = val32;
+        ot_keymgr_dpe_update_irq(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] |= val32;
+        ot_keymgr_dpe_update_irq(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_MASK;
+        s->regs[R_ALERT_TEST] |= val32;
+        ot_keymgr_dpe_update_alert(s);
+        break;
+    case R_START:
+        if (!ot_keymgr_dpe_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        val32 &= R_START_EN_MASK;
+        s->regs[reg] = val32;
+        ot_keymgr_dpe_fsm_tick(s);
+        break;
+    case R_CONTROL_SHADOWED:
+        if (!ot_keymgr_dpe_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        val32 &= R_CONTROL_SHADOWED_MASK;
+        switch (ot_shadow_reg_write(&s->control, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK;
+            ot_keymgr_dpe_update_alert(s);
+        }
+        break;
+    case R_SIDELOAD_CLEAR:
+        if (!ot_keymgr_dpe_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        val32 &= R_SIDELOAD_CLEAR_VAL_MASK;
+        s->regs[reg] = val32;
+        ot_keymgr_dpe_sideload_clear(s);
+        break;
+    case R_RESEED_INTERVAL_REGWEN:
+        val32 &= R_RESEED_INTERVAL_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_RESEED_INTERVAL_SHADOWED:
+        if (!ot_keymgr_dpe_check_reg_write(s, reg, R_RESEED_INTERVAL_REGWEN)) {
+            break;
+        }
+        val32 &= R_RESEED_INTERVAL_SHADOWED_VAL_MASK;
+        switch (ot_shadow_reg_write(&s->reseed_interval, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK;
+            ot_keymgr_dpe_update_alert(s);
+        }
+        break;
+    case R_SLOT_POLICY_REGWEN:
+        val32 &= R_SLOT_POLICY_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_SLOT_POLICY:
+        if (!ot_keymgr_dpe_check_reg_write(s, reg, R_SLOT_POLICY_REGWEN)) {
+            break;
+        }
+        s->regs[reg] = val32;
+        break;
+    case R_SW_BINDING_REGWEN:
+        val32 &= R_SW_BINDING_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_SW_BINDING_0:
+    case R_SW_BINDING_1:
+    case R_SW_BINDING_2:
+    case R_SW_BINDING_3:
+    case R_SW_BINDING_4:
+    case R_SW_BINDING_5:
+    case R_SW_BINDING_6:
+    case R_SW_BINDING_7: {
+        if (!ot_keymgr_dpe_check_reg_write(s, reg, R_SW_BINDING_REGWEN)) {
+            break;
+        }
+        unsigned offset = (reg - R_SW_BINDING_0) * sizeof(uint32_t);
+        stl_le_p(&s->sw_binding[offset], val32);
+        break;
+    }
+    case R_SALT_0:
+    case R_SALT_1:
+    case R_SALT_2:
+    case R_SALT_3:
+    case R_SALT_4:
+    case R_SALT_5:
+    case R_SALT_6:
+    case R_SALT_7: {
+        if (!ot_keymgr_dpe_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        unsigned offset = (reg - R_SALT_0) * sizeof(uint32_t);
+        stl_le_p(&s->salt[offset], val32);
+        break;
+    }
+    case R_KEY_VERSION:
+        if (!ot_keymgr_dpe_check_reg_write(s, reg, R_CFG_REGWEN)) {
+            break;
+        }
+        /* TODO */
+        s->regs[reg] = val32;
+        break;
+    case R_MAX_KEY_VER_REGWEN:
+        val32 &= R_MAX_KEY_VER_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_MAX_KEY_VER_SHADOWED:
+        if (!ot_keymgr_dpe_check_reg_write(s, reg, R_MAX_KEY_VER_REGWEN)) {
+            break;
+        }
+        switch (ot_shadow_reg_write(&s->max_key_ver, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_ERR_CODE] |= R_ERR_CODE_INVALID_SHADOW_UPDATE_MASK;
+            ot_keymgr_dpe_update_alert(s);
+        }
+        break;
+    case R_OP_STATUS:
+        val32 &= R_OP_STATUS_VAL_MASK;
+        ot_keymgr_dpe_change_op_status(s, s->regs[reg] & ~val32); /* RW1C */
+        /* SW write may clear `WIP` here which may be immediately set again */
+        ot_keymgr_dpe_fsm_tick(s);
+        break;
+    case R_ERR_CODE:
+        val32 &= ERR_CODE_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_keymgr_dpe_update_alert(s);
+        break;
+    case R_DEBUG:
+        val32 &= DEBUG_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CFG_REGWEN:
+    case R_WORKING_STATE:
+    case R_SW_SHARE0_OUTPUT_0:
+    case R_SW_SHARE0_OUTPUT_1:
+    case R_SW_SHARE0_OUTPUT_2:
+    case R_SW_SHARE0_OUTPUT_3:
+    case R_SW_SHARE0_OUTPUT_4:
+    case R_SW_SHARE0_OUTPUT_5:
+    case R_SW_SHARE0_OUTPUT_6:
+    case R_SW_SHARE0_OUTPUT_7:
+    case R_SW_SHARE1_OUTPUT_0:
+    case R_SW_SHARE1_OUTPUT_1:
+    case R_SW_SHARE1_OUTPUT_2:
+    case R_SW_SHARE1_OUTPUT_3:
+    case R_SW_SHARE1_OUTPUT_4:
+    case R_SW_SHARE1_OUTPUT_5:
+    case R_SW_SHARE1_OUTPUT_6:
+    case R_SW_SHARE1_OUTPUT_7:
+    case R_FAULT_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x02%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static void ot_keymgr_dpe_configure_constants(OtKeyMgrDpeState *s)
+{
+    for (unsigned ix = 0u; ix < KEYMGR_DPE_SEED_COUNT; ix++) {
+        if (!s->seed_xstrs[ix]) {
+            trace_ot_keymgr_dpe_seed_missing(s->ot_id, ix);
+            continue;
+        }
+
+        size_t len = strlen(s->seed_xstrs[ix]);
+        size_t seed_len_bytes = KEYMGR_DPE_SEED_BYTES;
+        if (ix == KEYMGR_DPE_SEED_LFSR) {
+            seed_len_bytes = 8u;
+        }
+        if (len != (seed_len_bytes * 2u)) {
+            error_setg(&error_fatal, "%s: %s invalid seed %s length: %zu\n",
+                       __func__, s->ot_id, SEED_NAME(ix), len);
+            continue;
+        }
+
+        if (ot_common_parse_hexa_str(s->seeds[ix], s->seed_xstrs[ix],
+                                     seed_len_bytes, true, true)) {
+            error_setg(&error_fatal, "%s: %s unable to parse seed %s\n",
+                       __func__, s->ot_id, SEED_NAME(ix));
+            continue;
+        }
+    }
+}
+
+static const Property ot_keymgr_dpe_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtKeyMgrDpeState, ot_id),
+    DEFINE_PROP_LINK("edn", OtKeyMgrDpeState, edn.device, TYPE_OT_EDN,
+                     OtEDNState *),
+    DEFINE_PROP_UINT8("edn-ep", OtKeyMgrDpeState, edn.ep, UINT8_MAX),
+    DEFINE_PROP_LINK("kmac", OtKeyMgrDpeState, kmac, TYPE_OT_KMAC,
+                     OtKMACState *),
+    DEFINE_PROP_UINT8("kmac-app", OtKeyMgrDpeState, kmac_app, UINT8_MAX),
+    DEFINE_PROP_LINK("lc-ctrl", OtKeyMgrDpeState, lc_ctrl, TYPE_OT_LC_CTRL,
+                     OtLcCtrlState *),
+    DEFINE_PROP_LINK("otp-ctrl", OtKeyMgrDpeState, otp_ctrl, TYPE_OT_OTP_IF,
+                     DeviceState *),
+    DEFINE_PROP_LINK("rom0", OtKeyMgrDpeState, rom_ctrl[0], TYPE_OT_ROM_CTRL,
+                     OtRomCtrlState *),
+    DEFINE_PROP_LINK("rom1", OtKeyMgrDpeState, rom_ctrl[1], TYPE_OT_ROM_CTRL,
+                     OtRomCtrlState *),
+    DEFINE_PROP_LINK("aes", OtKeyMgrDpeState,
+                     key_sinks[KEYMGR_DPE_KEY_SINK_AES], TYPE_OT_KEY_SINK_IF,
+                     DeviceState *),
+    DEFINE_PROP_LINK("otbn", OtKeyMgrDpeState,
+                     key_sinks[KEYMGR_DPE_KEY_SINK_OTBN], TYPE_OT_KEY_SINK_IF,
+                     DeviceState *),
+    DEFINE_PROP_STRING("aes_seed", OtKeyMgrDpeState,
+                       seed_xstrs[KEYMGR_DPE_SEED_AES]),
+    DEFINE_PROP_STRING("hard_output_seed", OtKeyMgrDpeState,
+                       seed_xstrs[KEYMGR_DPE_SEED_HW_OUT]),
+    DEFINE_PROP_STRING("kmac_seed", OtKeyMgrDpeState,
+                       seed_xstrs[KEYMGR_DPE_SEED_KMAC]),
+    DEFINE_PROP_STRING("lfsr_seed", OtKeyMgrDpeState,
+                       seed_xstrs[KEYMGR_DPE_SEED_LFSR]),
+    DEFINE_PROP_STRING("none_seed", OtKeyMgrDpeState,
+                       seed_xstrs[KEYMGR_DPE_SEED_NONE]),
+    DEFINE_PROP_STRING("otbn_seed", OtKeyMgrDpeState,
+                       seed_xstrs[KEYMGR_DPE_SEED_OTBN]),
+    DEFINE_PROP_STRING("revision_seed", OtKeyMgrDpeState,
+                       seed_xstrs[KEYMGR_DPE_SEED_REV]),
+    DEFINE_PROP_STRING("soft_output_seed", OtKeyMgrDpeState,
+                       seed_xstrs[KEYMGR_DPE_SEED_SW_OUT]),
+};
+
+static const MemoryRegionOps ot_keymgr_dpe_regs_ops = {
+    .read = &ot_keymgr_dpe_read,
+    .write = &ot_keymgr_dpe_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_keymgr_dpe_reset_enter(Object *obj, ResetType type)
+{
+    OtKeyMgrDpeClass *c = OT_KEYMGR_DPE_GET_CLASS(obj);
+    OtKeyMgrDpeState *s = OT_KEYMGR_DPE(obj);
+
+    trace_ot_keymgr_dpe_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    qemu_bh_cancel(s->fsm_tick_bh);
+
+    g_assert(s->edn.device);
+    g_assert(s->edn.ep != UINT8_MAX);
+    g_assert(s->kmac);
+    g_assert(s->kmac_app != UINT8_MAX);
+    g_assert(s->lc_ctrl);
+    g_assert(s->otp_ctrl);
+    g_assert(s->rom_ctrl[0]);
+    g_assert(s->rom_ctrl[1]);
+
+    (void)OBJECT_CHECK(OtOTPIf, s->otp_ctrl, TYPE_OT_OTP_IF);
+
+    s->key_sinks[KEYMGR_DPE_KEY_SINK_KMAC] = DEVICE(s->kmac);
+
+    /* reset registers */
+    memset(s->regs, 0u, sizeof(s->regs));
+    s->regs[R_CFG_REGWEN] = 0x1u;
+    ot_shadow_reg_init(&s->control, 10u);
+    s->regs[R_RESEED_INTERVAL_REGWEN] = 0x1u;
+    ot_shadow_reg_init(&s->reseed_interval, 0x100u);
+    s->regs[R_SLOT_POLICY_REGWEN] = 0x1u;
+    s->regs[R_SW_BINDING_REGWEN] = 0x1u;
+    memset(s->sw_binding, 0u, NUM_SW_BINDING_REG * sizeof(uint32_t));
+    memset(s->salt, 0u, NUM_SALT_REG * sizeof(uint32_t));
+    s->regs[R_MAX_KEY_VER_REGWEN] = 0x1u;
+    ot_shadow_reg_init(&s->max_key_ver, 0u);
+
+    /* reset internal state */
+    s->enabled = false;
+    s->state = KEYMGR_DPE_ST_RESET;
+    s->prng.reseed_req = false;
+    s->prng.reseed_ack = false;
+    s->prng.reseed_cnt = 0u;
+    s->op_state.op_req = false;
+    s->op_state.op_ack = false;
+    ot_keymgr_dpe_reset_kdf_buffer(s);
+
+    /* reset slots */
+    memset(s->key_slots, 0u, NUM_SLOTS * sizeof(OtKeyMgrDpeSlot));
+
+    /* reset output keys */
+    memset(s->sw_out_key, 0u, sizeof(OtKeyMgrDpeKey));
+
+    /* update IRQ and alert states */
+    ot_keymgr_dpe_update_irq(s);
+    ot_keymgr_dpe_update_alert(s);
+
+    /* connect to KMAC */
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    kc->connect_app(s->kmac, s->kmac_app, &KMAC_APP_CFG,
+                    ot_keymgr_dpe_handle_kmac_response, s);
+}
+
+static void ot_keymgr_dpe_reset_exit(Object *obj, ResetType type)
+{
+    OtKeyMgrDpeClass *c = OT_KEYMGR_DPE_GET_CLASS(obj);
+    OtKeyMgrDpeState *s = OT_KEYMGR_DPE(obj);
+
+    trace_ot_keymgr_dpe_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    for (unsigned ix = 0u; ix < KEYMGR_DPE_KEY_SINK_COUNT; ix++) {
+        OtKeyMgrDpeKeySink key_sink = (OtKeyMgrDpeKeySink)ix;
+        ot_keymgr_dpe_push_key(s, key_sink, NULL, NULL, false);
+    }
+}
+
+static void ot_keymgr_dpe_realize(DeviceState *dev, Error **errp)
+{
+    OtKeyMgrDpeState *s = OT_KEYMGR_DPE(dev);
+
+    (void)errp; /* unused */
+
+    if (!s->ot_id) {
+        s->ot_id =
+            g_strdup(object_get_canonical_path_component(OBJECT(s)->parent));
+    }
+
+    for (unsigned ix = 0u; ix < KEYMGR_DPE_KEY_SINK_COUNT; ix++) {
+        if (s->key_sinks[ix]) {
+            OBJECT_CHECK(OtKeySinkIf, s->key_sinks[ix], TYPE_OT_KEY_SINK_IF);
+        }
+    }
+
+    ot_keymgr_dpe_configure_constants(s);
+}
+
+static void ot_keymgr_dpe_init(Object *obj)
+{
+    OtKeyMgrDpeState *s = OT_KEYMGR_DPE(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_keymgr_dpe_regs_ops, s,
+                          TYPE_OT_KEYMGR_DPE, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    ibex_sysbus_init_irq(obj, &s->irq);
+    for (unsigned ix = 0u; ix < ALERT_COUNT; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+    qdev_init_gpio_in_named(DEVICE(s), ot_keymgr_dpe_lc_signal,
+                            OT_KEYMGR_DPE_ENABLE, 1);
+
+    s->prng.state = ot_prng_allocate();
+
+    s->kdf_buf.data = g_new0(uint8_t, KEYMGR_DPE_KDF_BUFFER_BYTES);
+    s->salt = g_new0(uint8_t, NUM_SALT_REG * sizeof(uint32_t));
+    s->sw_binding = g_new0(uint8_t, NUM_SW_BINDING_REG * sizeof(uint32_t));
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->seeds); ix++) {
+        s->seeds[ix] = g_new0(uint8_t, KEYMGR_DPE_SEED_BYTES);
+    }
+    s->key_slots = g_new0(OtKeyMgrDpeSlot, NUM_SLOTS);
+    s->sw_out_key = g_new0(OtKeyMgrDpeKey, 1u);
+
+    s->fsm_tick_bh = qemu_bh_new(&ot_keymgr_dpe_fsm_tick, s);
+
+    s->hexstr = g_new0(char, OT_KEYMGR_DPE_HEXSTR_SIZE);
+}
+
+static void ot_keymgr_dpe_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    (void)data; /* unused */
+
+    dc->realize = &ot_keymgr_dpe_realize;
+    device_class_set_props(dc, ot_keymgr_dpe_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtKeyMgrDpeClass *kmc = OT_KEYMGR_DPE_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_keymgr_dpe_reset_enter, NULL,
+                                       &ot_keymgr_dpe_reset_exit,
+                                       &kmc->parent_phases);
+}
+
+static const TypeInfo ot_keymgr_dpe_info = {
+    .name = TYPE_OT_KEYMGR_DPE,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtKeyMgrDpeState),
+    .instance_init = &ot_keymgr_dpe_init,
+    .class_size = sizeof(OtKeyMgrDpeClass),
+    .class_init = &ot_keymgr_dpe_class_init,
+};
+
+static void ot_keymgr_dpe_register_types(void)
+{
+    type_register_static(&ot_keymgr_dpe_info);
+}
+
+type_init(ot_keymgr_dpe_register_types)
diff --git a/hw/opentitan/ot_kmac.c b/hw/opentitan/ot_kmac.c
new file mode 100644
index 0000000000000..c072698b030c3
--- /dev/null
+++ b/hw/opentitan/ot_kmac.c
@@ -0,0 +1,1991 @@
+/*
+ * QEMU OpenTitan KMAC device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * For details check the documentation here:
+ *    https://opentitan.org/book/hw/ip/kmac
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: This implementation is missing some features:
+ *   - Masking (current implementation does not consume entropy)
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/fifo8.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/timer.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_clkmgr.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_key_sink.h"
+#include "hw/opentitan/ot_kmac.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "tomcrypt.h"
+#include "trace.h"
+
+#define KMAC_PARAM_NUM_ALERTS 2u
+
+/* clang-format off */
+REG32(INTR_STATE, 0x00u)
+    SHARED_FIELD(INTR_KMAC_DONE, 0u, 1u)
+    SHARED_FIELD(INTR_FIFO_EMPTY, 1u, 1u)
+    SHARED_FIELD(INTR_KMAC_ERR, 2u, 1u)
+REG32(INTR_ENABLE, 0x04u)
+REG32(INTR_TEST, 0x08u)
+REG32(ALERT_TEST, 0x0cu)
+    FIELD(ALERT_TEST, RECOV_OPERATION, 0u, 1u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 1u, 1u)
+REG32(CFG_REGWEN, 0x10u)
+    FIELD(CFG_REGWEN, EN, 0u, 1u)
+REG32(CFG_SHADOWED, 0x14u)
+    FIELD(CFG_SHADOWED, KMAC_EN, 0u, 1u)
+    FIELD(CFG_SHADOWED, KSTRENGTH, 1u, 3u)
+    FIELD(CFG_SHADOWED, MODE, 4u, 2u)
+    FIELD(CFG_SHADOWED, MSG_ENDIANNESS, 8u, 1u)
+    FIELD(CFG_SHADOWED, STATE_ENDIANNESS, 9u, 1u)
+    FIELD(CFG_SHADOWED, SIDELOAD, 12u, 1u)
+    FIELD(CFG_SHADOWED, ENTROPY_MODE, 16u, 2u)
+    FIELD(CFG_SHADOWED, ENTROPY_FAST_PROCESS, 19u, 1u)
+    FIELD(CFG_SHADOWED, MSG_MASK, 20u, 1u)
+    FIELD(CFG_SHADOWED, ENTROPY_READY, 24u, 1u)
+    FIELD(CFG_SHADOWED, EN_UNSUPPORTED_MODESTRENGTH, 26u, 1u)
+REG32(CMD, 0x18u)
+    FIELD(CMD, CMD, 0u, 6u)
+    FIELD(CMD, ENTROPY_REQ, 8u, 1u)
+    FIELD(CMD, HASH_CNT_CLR, 9u, 1u)
+    FIELD(CMD, ERR_PROCESSED, 10u, 1u)
+REG32(STATUS, 0x1cu)
+    FIELD(STATUS, SHA3_IDLE, 0u, 1u)
+    FIELD(STATUS, SHA3_ABSORB, 1u, 1u)
+    FIELD(STATUS, SHA3_SQUEEZE, 2u, 1u)
+    FIELD(STATUS, FIFO_DEPTH, 8u, 5u)
+    FIELD(STATUS, FIFO_EMPTY, 14u, 1u)
+    FIELD(STATUS, FIFO_FULL, 15u, 1u)
+    FIELD(STATUS, ALERT_FATAL_FAULT, 16u, 1u)
+    FIELD(STATUS, ALERT_RECOV_CTRL_UPDATE_ERR, 17u, 1u)
+REG32(ENTROPY_PERIOD, 0x20u)
+    FIELD(ENTROPY_PERIOD, PRESCALER, 0u, 10u)
+    FIELD(ENTROPY_PERIOD, WAIT_TIMER, 16u, 16u)
+REG32(ENTROPY_REFRESH_HASH_CNT, 0x24u)
+    FIELD(ENTROPY_REFRESH_HASH_CNT, HASH_CNT, 0u, 10u)
+REG32(ENTROPY_REFRESH_THRESHOLD_SHADOWED, 0x28u)
+    FIELD(ENTROPY_REFRESH_THRESHOLD_SHADOWED, THRESHOLD, 0u, 10u)
+REG32(ENTROPY_SEED, 0x2cu)
+REG32(KEY_SHARE0_0, 0x30u)
+REG32(KEY_SHARE0_1, 0x34u)
+REG32(KEY_SHARE0_2, 0x38u)
+REG32(KEY_SHARE0_3, 0x3cu)
+REG32(KEY_SHARE0_4, 0x40u)
+REG32(KEY_SHARE0_5, 0x44u)
+REG32(KEY_SHARE0_6, 0x48u)
+REG32(KEY_SHARE0_7, 0x4cu)
+REG32(KEY_SHARE0_8, 0x50u)
+REG32(KEY_SHARE0_9, 0x54u)
+REG32(KEY_SHARE0_10, 0x58u)
+REG32(KEY_SHARE0_11, 0x5cu)
+REG32(KEY_SHARE0_12, 0x60u)
+REG32(KEY_SHARE0_13, 0x64u)
+REG32(KEY_SHARE0_14, 0x68u)
+REG32(KEY_SHARE0_15, 0x6cu)
+REG32(KEY_SHARE1_0, 0x70u)
+REG32(KEY_SHARE1_1, 0x74u)
+REG32(KEY_SHARE1_2, 0x78u)
+REG32(KEY_SHARE1_3, 0x7cu)
+REG32(KEY_SHARE1_4, 0x80u)
+REG32(KEY_SHARE1_5, 0x84u)
+REG32(KEY_SHARE1_6, 0x88u)
+REG32(KEY_SHARE1_7, 0x8cu)
+REG32(KEY_SHARE1_8, 0x90u)
+REG32(KEY_SHARE1_9, 0x94u)
+REG32(KEY_SHARE1_10, 0x98u)
+REG32(KEY_SHARE1_11, 0x9cu)
+REG32(KEY_SHARE1_12, 0xa0u)
+REG32(KEY_SHARE1_13, 0xa4u)
+REG32(KEY_SHARE1_14, 0xa8u)
+REG32(KEY_SHARE1_15, 0xacu)
+REG32(KEY_LEN, 0xb0u)
+    FIELD(KEY_LEN, LEN, 0u, 3u)
+REG32(PREFIX_0, 0xb4u)
+REG32(PREFIX_1, 0xb8u)
+REG32(PREFIX_2, 0xbcu)
+REG32(PREFIX_3, 0xc0u)
+REG32(PREFIX_4, 0xc4u)
+REG32(PREFIX_5, 0xc8u)
+REG32(PREFIX_6, 0xccu)
+REG32(PREFIX_7, 0xd0u)
+REG32(PREFIX_8, 0xd4u)
+REG32(PREFIX_9, 0xd8u)
+REG32(PREFIX_10, 0xdcu)
+REG32(ERR_CODE, 0xe0u)
+    FIELD(ERR_CODE, INFO, 0u, 24u)
+    FIELD(ERR_CODE, CODE, 24u, 8u)
+/* clang-format on */
+
+#define INTR_MASK \
+    (INTR_KMAC_ERR_MASK | INTR_FIFO_EMPTY_MASK | INTR_KMAC_DONE_MASK)
+#define ALERT_MASK \
+    (R_ALERT_TEST_FATAL_FAULT_MASK | R_ALERT_TEST_RECOV_OPERATION_MASK)
+#define CFG_MASK \
+    (R_CFG_SHADOWED_KMAC_EN_MASK | R_CFG_SHADOWED_KSTRENGTH_MASK | \
+     R_CFG_SHADOWED_MODE_MASK | R_CFG_SHADOWED_MSG_ENDIANNESS_MASK | \
+     R_CFG_SHADOWED_STATE_ENDIANNESS_MASK | R_CFG_SHADOWED_SIDELOAD_MASK | \
+     R_CFG_SHADOWED_ENTROPY_MODE_MASK | \
+     R_CFG_SHADOWED_ENTROPY_FAST_PROCESS_MASK | R_CFG_SHADOWED_MSG_MASK_MASK | \
+     R_CFG_SHADOWED_ENTROPY_READY_MASK | \
+     R_CFG_SHADOWED_EN_UNSUPPORTED_MODESTRENGTH_MASK)
+
+enum {
+    OT_KMAC_CMD_NONE = 0,
+    OT_KMAC_CMD_START = 0x1d,
+    OT_KMAC_CMD_PROCESS = 0x2e,
+    OT_KMAC_CMD_MANUAL_RUN = 0x31,
+    OT_KMAC_CMD_DONE = 0x16,
+};
+
+#define CMD_NAME_ENTRY(_st_) [OT_KMAC_CMD_##_st_] = stringify(_st_)
+static const char *CMD_NAMES[] = {
+    CMD_NAME_ENTRY(NONE),       CMD_NAME_ENTRY(START), CMD_NAME_ENTRY(PROCESS),
+    CMD_NAME_ENTRY(MANUAL_RUN), CMD_NAME_ENTRY(DONE),
+};
+#undef CMD_NAME_ENTRY
+#define CMD_NAME(_st_) \
+    ((_st_) >= 0 && (_st_) < ARRAY_SIZE(CMD_NAMES) ? CMD_NAMES[(_st_)] : "?")
+
+enum {
+    OT_KMAC_ERR_NONE = 0,
+    OT_KMAC_ERR_KEY_NOT_VALID = 0x01,
+    OT_KMAC_ERR_SW_PUSHED_MSG_FIFO = 0x02,
+    OT_KMAC_ERR_SW_ISSUED_CMD_IN_APP_ACTIVE = 0x03,
+    OT_KMAC_ERR_WAIT_TIMER_EXPIRED = 0x04,
+    OT_KMAC_ERR_INCORRECT_ENTROPY_MODE = 0x05,
+    OT_KMAC_ERR_UNEXPECTED_MODE_STRENGTH = 0x06,
+    OT_KMAC_ERR_INCORRECT_FUNCTION_NAME = 0x07,
+    OT_KMAC_ERR_SW_CMD_SEQUENCE = 0x08,
+    OT_KMAC_ERR_SW_HASHING_WITHOUT_ENTROPY_READY = 0x09,
+    OT_KMAC_ERR_SHADOW_REG_UPDATE = 0xc0,
+    OT_KMAC_ERR_FATAL_ERROR = 0xc1,
+    OT_KMAC_ERR_PACKER_INTEGRITY = 0xc2,
+    OT_KMAC_ERR_MSG_FIFO_INTEGRITY = 0xc3,
+};
+
+#define ERR_NAME_ENTRY(_st_) [OT_KMAC_ERR_##_st_] = stringify(_st_)
+static const char *ERR_NAMES[] = {
+    ERR_NAME_ENTRY(NONE),
+    ERR_NAME_ENTRY(KEY_NOT_VALID),
+    ERR_NAME_ENTRY(SW_PUSHED_MSG_FIFO),
+    ERR_NAME_ENTRY(SW_ISSUED_CMD_IN_APP_ACTIVE),
+    ERR_NAME_ENTRY(WAIT_TIMER_EXPIRED),
+    ERR_NAME_ENTRY(INCORRECT_ENTROPY_MODE),
+    ERR_NAME_ENTRY(UNEXPECTED_MODE_STRENGTH),
+    ERR_NAME_ENTRY(INCORRECT_FUNCTION_NAME),
+    ERR_NAME_ENTRY(SW_CMD_SEQUENCE),
+    ERR_NAME_ENTRY(SW_HASHING_WITHOUT_ENTROPY_READY),
+    ERR_NAME_ENTRY(SHADOW_REG_UPDATE),
+    ERR_NAME_ENTRY(FATAL_ERROR),
+    ERR_NAME_ENTRY(PACKER_INTEGRITY),
+    ERR_NAME_ENTRY(MSG_FIFO_INTEGRITY),
+};
+#undef ERR_NAME_ENTRY
+#define ERR_NAME(_st_) \
+    ((_st_) >= 0 && (_st_) < ARRAY_SIZE(ERR_NAMES) ? ERR_NAMES[(_st_)] : "?")
+
+/* base offset for MMIO registers */
+#define OT_KMAC_REGS_BASE 0x00000000u
+/* base offset for MMIO STATE */
+#define OT_KMAC_STATE_BASE 0x00000400u
+/* length of MMIO STATE */
+#define OT_KMAC_STATE_SIZE 0x00000200u
+/* base offset for MMIO MSG_FIFO */
+#define OT_KMAC_MSG_FIFO_BASE 0x00000800u
+/* length of MMIO FIFO */
+#define OT_KMAC_MSG_FIFO_SIZE 0x00000800u
+/* length of the whole device MMIO region */
+#define OT_KMAC_WHOLE_SIZE (OT_KMAC_MSG_FIFO_BASE + OT_KMAC_MSG_FIFO_SIZE)
+
+#define OT_KMAC_CLOCK_ACTIVE "clock-active"
+#define OT_KMAC_CLOCK_INPUT  "clock-in"
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_ERR_CODE)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CFG_REGWEN),
+    REG_NAME_ENTRY(CFG_SHADOWED),
+    REG_NAME_ENTRY(CMD),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(ENTROPY_PERIOD),
+    REG_NAME_ENTRY(ENTROPY_REFRESH_HASH_CNT),
+    REG_NAME_ENTRY(ENTROPY_REFRESH_THRESHOLD_SHADOWED),
+    REG_NAME_ENTRY(ENTROPY_SEED),
+    REG_NAME_ENTRY(KEY_SHARE0_0),
+    REG_NAME_ENTRY(KEY_SHARE0_1),
+    REG_NAME_ENTRY(KEY_SHARE0_2),
+    REG_NAME_ENTRY(KEY_SHARE0_3),
+    REG_NAME_ENTRY(KEY_SHARE0_4),
+    REG_NAME_ENTRY(KEY_SHARE0_5),
+    REG_NAME_ENTRY(KEY_SHARE0_6),
+    REG_NAME_ENTRY(KEY_SHARE0_7),
+    REG_NAME_ENTRY(KEY_SHARE0_8),
+    REG_NAME_ENTRY(KEY_SHARE0_9),
+    REG_NAME_ENTRY(KEY_SHARE0_10),
+    REG_NAME_ENTRY(KEY_SHARE0_11),
+    REG_NAME_ENTRY(KEY_SHARE0_12),
+    REG_NAME_ENTRY(KEY_SHARE0_13),
+    REG_NAME_ENTRY(KEY_SHARE0_14),
+    REG_NAME_ENTRY(KEY_SHARE0_15),
+    REG_NAME_ENTRY(KEY_SHARE1_0),
+    REG_NAME_ENTRY(KEY_SHARE1_1),
+    REG_NAME_ENTRY(KEY_SHARE1_2),
+    REG_NAME_ENTRY(KEY_SHARE1_3),
+    REG_NAME_ENTRY(KEY_SHARE1_4),
+    REG_NAME_ENTRY(KEY_SHARE1_5),
+    REG_NAME_ENTRY(KEY_SHARE1_6),
+    REG_NAME_ENTRY(KEY_SHARE1_7),
+    REG_NAME_ENTRY(KEY_SHARE1_8),
+    REG_NAME_ENTRY(KEY_SHARE1_9),
+    REG_NAME_ENTRY(KEY_SHARE1_10),
+    REG_NAME_ENTRY(KEY_SHARE1_11),
+    REG_NAME_ENTRY(KEY_SHARE1_12),
+    REG_NAME_ENTRY(KEY_SHARE1_13),
+    REG_NAME_ENTRY(KEY_SHARE1_14),
+    REG_NAME_ENTRY(KEY_SHARE1_15),
+    REG_NAME_ENTRY(KEY_LEN),
+    REG_NAME_ENTRY(PREFIX_0),
+    REG_NAME_ENTRY(PREFIX_1),
+    REG_NAME_ENTRY(PREFIX_2),
+    REG_NAME_ENTRY(PREFIX_3),
+    REG_NAME_ENTRY(PREFIX_4),
+    REG_NAME_ENTRY(PREFIX_5),
+    REG_NAME_ENTRY(PREFIX_6),
+    REG_NAME_ENTRY(PREFIX_7),
+    REG_NAME_ENTRY(PREFIX_8),
+    REG_NAME_ENTRY(PREFIX_9),
+    REG_NAME_ENTRY(PREFIX_10),
+    REG_NAME_ENTRY(ERR_CODE),
+};
+#undef REG_NAME_ENTRY
+
+#define OT_KMAC_KEY_HEXSTR_SIZE (OT_KMAC_KEY_SIZE * 2u + 2u)
+
+/* Input FIFO length is 80 bytes (10 x 64 bits) */
+#define FIFO_LENGTH 80u
+
+/* Delay FIFO ingestion and compute by 100ns */
+#define BH_TRIGGER_DELAY_NS 100u
+
+/* Max size of the KECCAK state */
+#define KECCAK_STATE_BITS  1600u
+#define KECCAK_STATE_BYTES (KECCAK_STATE_BITS / 8u)
+
+/*
+ * Size of the state window for each share. Each window contains
+ * KECCAK_STATE_BYTES of state followed by zeros.
+ */
+#define KECCAK_STATE_SHARE_BYTES 256u
+
+/* Number of KEY_* registers */
+#define NUM_KEY_REGS 16u
+
+/* Number of PREFIX_* registers */
+#define NUM_PREFIX_REGS 11u
+
+/* function prefix for KMAC operations (first 6 bytes of PREFIX_*) */
+#define KMAC_PREFIX_0      0x4d4b2001u
+#define KMAC_PREFIX_0_MASK 0xffffffffu
+#define KMAC_PREFIX_1      0x00004341u
+#define KMAC_PREFIX_1_MASK 0x0000ffffu
+
+enum {
+    ALERT_RECOVERABLE = 0,
+    ALERT_FATAL = 1,
+};
+
+/*
+ * FSM states, values hard-coded to st_logical_e values from RTL for direct use
+ * in error reporting
+ */
+typedef enum {
+    /* idle */
+    KMAC_ST_IDLE = 0,
+    /* MSG_FEED: receive the message bitstream */
+    KMAC_ST_MSG_FEED = 1,
+    /* PROCESSING: computes the keccak rounds */
+    KMAC_ST_PROCESSING = 2,
+    /* ABSORBED: digest is available */
+    KMAC_ST_ABSORBED = 3,
+    /* SQUEEZING: compute more keccak rounds */
+    KMAC_ST_SQUEEZING = 4,
+    /* illegal state reached and hang */
+    KMAC_ST_TERMINAL_ERROR = 5,
+} OtKMACFsmState;
+
+#define STATE_NAME_ENTRY(_st_) [KMAC_ST_##_st_] = stringify(_st_)
+static const char *STATE_NAMES[] = {
+    STATE_NAME_ENTRY(IDLE),       STATE_NAME_ENTRY(MSG_FEED),
+    STATE_NAME_ENTRY(PROCESSING), STATE_NAME_ENTRY(ABSORBED),
+    STATE_NAME_ENTRY(SQUEEZING),  STATE_NAME_ENTRY(TERMINAL_ERROR),
+};
+#undef STATE_NAME_ENTRY
+#define STATE_NAME(_st_) \
+    ((_st_) >= 0 && (_st_) < ARRAY_SIZE(STATE_NAMES) ? STATE_NAMES[(_st_)] : \
+                                                       "?")
+typedef struct {
+    unsigned index; /* app index */
+    OtKMACAppCfg cfg; /* configuration */
+    OtKMACAppReq req; /* pending request */
+    OtKmacResponse fn; /* response callback */
+    void *opaque; /* opaque parameter to response callback */
+    bool connected; /* app is connected to KMAC */
+    bool req_pending; /* true if pending request */
+} OtKMACApp;
+
+typedef struct {
+    uint8_t share0[OT_KMAC_KEY_SIZE];
+    uint8_t share1[OT_KMAC_KEY_SIZE];
+    bool valid;
+} OtKMACKey;
+
+struct OtKMACState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    MemoryRegion regs_mmio;
+    MemoryRegion state_mmio;
+    MemoryRegion msgfifo_mmio;
+    IbexIRQ irqs[3u];
+    IbexIRQ alerts[KMAC_PARAM_NUM_ALERTS];
+    IbexIRQ clock_active;
+
+    uint32_t *regs;
+    OtShadowReg cfg;
+    OtShadowReg entropy_refresh_threshold;
+
+    OtKMACFsmState state; /* Main FSM state */
+    bool invalid_state_read;
+    bool error_awaiting_sw; /* error awaiting SW acknowledgement */
+    hash_state ltc_state; /* TomCrypt hash state */
+    uint8_t keccak_state[KECCAK_STATE_BYTES];
+
+    OtKMACAppCfg sw_cfg;
+    OtKMACAppCfg *current_cfg;
+    unsigned pclk; /* Current input clock */
+    const char *clock_src_name; /* IRQ name once connected */
+
+    OtKMACApp *apps;
+    OtKMACApp *current_app;
+    OtKMACKey *sl_key;
+    char *hexstr;
+    uint32_t pending_apps;
+
+    Fifo8 input_fifo;
+    QEMUTimer *bh_timer; /* timer to delay bh when triggered from vCPU */
+    QEMUBH *bh;
+
+    char *ot_id;
+    char *clock_name;
+    DeviceState *clock_src;
+    OtEDNState *edn;
+    uint8_t edn_ep;
+    uint8_t num_app;
+};
+
+static void
+ot_kmac_change_fsm_state_line(OtKMACState *s, OtKMACFsmState state, int line)
+{
+    if (s->state == state) {
+        return;
+    }
+
+    if (s->current_app) {
+        trace_ot_kmac_change_state_app(s->ot_id, s->current_app->index, line,
+                                       STATE_NAME(s->state), s->state,
+                                       STATE_NAME(state), state);
+    } else {
+        trace_ot_kmac_change_state_sw(s->ot_id, line, STATE_NAME(s->state),
+                                      s->state, STATE_NAME(state), state);
+    }
+
+    ibex_irq_set(&s->clock_active, (bool)(state != KMAC_ST_IDLE));
+
+    s->state = state;
+}
+
+#define ot_kmac_change_fsm_state(_s_, _st_) \
+    ot_kmac_change_fsm_state_line(_s_, _st_, __LINE__)
+
+static void ot_kmac_trigger_deferred_bh(OtKMACState *s)
+{
+    timer_del(s->bh_timer);
+    timer_mod(s->bh_timer,
+              qemu_clock_get_ns(OT_VIRTUAL_CLOCK) + BH_TRIGGER_DELAY_NS);
+}
+
+static void ot_kmac_bh_timer_handler(void *opaque)
+{
+    OtKMACState *s = opaque;
+    qemu_bh_schedule(s->bh);
+}
+
+static void ot_kmac_cancel_bh(OtKMACState *s)
+{
+    timer_del(s->bh_timer);
+    qemu_bh_cancel(s->bh);
+}
+
+static void ot_kmac_update_irq(OtKMACState *s)
+{
+    uint32_t level = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->irqs); ix++) {
+        ibex_irq_set(&s->irqs[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_kmac_update_alert(OtKMACState *s)
+{
+    uint32_t level = s->regs[R_ALERT_TEST];
+
+    if (s->regs[R_STATUS] & R_STATUS_ALERT_FATAL_FAULT_MASK) {
+        level |= 1u << ALERT_FATAL;
+    }
+    if (s->regs[R_STATUS] & R_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK) {
+        level |= 1u << ALERT_RECOVERABLE;
+    }
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_kmac_report_error(OtKMACState *s, int code, uint32_t info)
+{
+    trace_ot_kmac_report_error(s->ot_id, code, ERR_NAME(code), info);
+
+    uint32_t error = 0;
+    error = FIELD_DP32(error, ERR_CODE, CODE, code);
+    error = FIELD_DP32(error, ERR_CODE, INFO, info);
+
+    s->error_awaiting_sw = true;
+    s->regs[R_ERR_CODE] = error;
+    s->regs[R_INTR_STATE] |= INTR_KMAC_ERR_MASK;
+    ot_kmac_update_irq(s);
+}
+
+static void ot_kmac_get_sw_config(OtKMACState *s)
+{
+    uint32_t cfg = ot_shadow_reg_peek(&s->cfg);
+
+    switch (FIELD_EX32(cfg, CFG_SHADOWED, MODE)) {
+    case 0:
+        s->sw_cfg.mode = OT_KMAC_MODE_SHA3;
+        break;
+    case 2u:
+        s->sw_cfg.mode = OT_KMAC_MODE_SHAKE;
+        break;
+    case 3u:
+        if (FIELD_EX32(cfg, CFG_SHADOWED, KMAC_EN) != 0) {
+            s->sw_cfg.mode = OT_KMAC_MODE_KMAC;
+        } else {
+            s->sw_cfg.mode = OT_KMAC_MODE_CSHAKE;
+        }
+        break;
+    default:
+        /* invalid modes are checked when processing START command */
+        s->sw_cfg.mode = OT_KMAC_MODE_NONE;
+        break;
+    }
+
+    switch (FIELD_EX32(cfg, CFG_SHADOWED, KSTRENGTH)) {
+    case 0:
+        s->sw_cfg.strength = 128u;
+        break;
+    case 1u:
+        s->sw_cfg.strength = 224u;
+        break;
+    case 2u:
+        s->sw_cfg.strength = 256u;
+        break;
+    case 3u:
+        s->sw_cfg.strength = 384u;
+        break;
+    case 4u:
+        s->sw_cfg.strength = 512u;
+        break;
+    default:
+        /* invalid key strength are checked when processing START command */
+        s->sw_cfg.strength = 0;
+        break;
+    }
+}
+
+static inline size_t ot_kmac_get_key_length(const OtKMACState *s)
+{
+    uint32_t key_len = FIELD_EX32(s->regs[R_KEY_LEN], KEY_LEN, LEN);
+    switch (key_len) {
+    case 0:
+        return 16u;
+    case 1u:
+        return 24u;
+    case 2u:
+        return 32u;
+    case 3u:
+        return 48u;
+    case 4u:
+        return 64u;
+    default:
+        /* invalid key length values are traced at register write */
+        return 0;
+    }
+}
+
+static void ot_kmac_push_key(OtKeySinkIf *ifd, const uint8_t *share0,
+                             const uint8_t *share1, size_t key_len, bool valid)
+{
+    g_assert(!key_len || key_len == OT_KMAC_KEY_SIZE);
+
+    OtKMACState *s = OT_KMAC(ifd);
+    OtKMACKey *key = s->sl_key;
+
+    if (key_len && share0) {
+        memcpy(key->share0, share0, key_len);
+    } else {
+        memset(key->share0, 0, OT_KMAC_KEY_SIZE);
+    }
+    if (key_len && share1) {
+        memcpy(key->share1, share1, key_len);
+    } else {
+        memset(key->share1, 0, OT_KMAC_KEY_SIZE);
+    }
+    key->valid = valid;
+
+    if (trace_event_get_state(TRACE_OT_KMAC_PUSH_KEY)) {
+        uint8_t key_value[OT_KMAC_KEY_SIZE];
+        for (unsigned ix = 0u; ix < OT_KMAC_KEY_SIZE; ix++) {
+            key_value[ix] = key->share0[ix] ^ key->share1[ix];
+        }
+
+        trace_ot_kmac_push_key(s->ot_id, valid,
+                               ot_common_lhexdump(key_value, OT_KMAC_KEY_SIZE,
+                                                  true, s->hexstr,
+                                                  OT_KMAC_KEY_HEXSTR_SIZE));
+    }
+}
+
+static void ot_kmac_get_key(OtKMACState *s, uint8_t *key, size_t *keylen)
+{
+    uint32_t cfg = ot_shadow_reg_peek(&s->cfg);
+    bool sideload = FIELD_EX32(cfg, CFG_SHADOWED, SIDELOAD) != 0;
+
+    /* force sideload for app interface */
+    if (s->current_app) {
+        sideload = true;
+    }
+
+    if (sideload) {
+        *keylen = OT_KMAC_KEY_SIZE;
+        const OtKMACKey *sl_key = s->sl_key;
+        for (size_t ix = 0; ix < OT_KMAC_KEY_SIZE; ix++) {
+            key[ix] = sl_key->share0[ix] ^ sl_key->share1[ix];
+        }
+
+        if (!sl_key->valid) {
+            /* HW defaults to info = app_id = 0 when in a SW operation. */
+            uint32_t err_info = s->current_app ? s->current_app->index : 0;
+            ot_kmac_report_error(s, OT_KMAC_ERR_KEY_NOT_VALID, err_info);
+        }
+        return;
+    }
+
+    *keylen = ot_kmac_get_key_length(s);
+    for (size_t ix = 0; ix < *keylen; ix++) {
+        uint8_t reg = ix / sizeof(uint32_t);
+        uint8_t byteoffset = ix & (sizeof(uint32_t) - 1u);
+
+        uint8_t share0 = (uint8_t)(s->regs[R_KEY_SHARE0_0 + reg] >>
+                                   (byteoffset * BITS_PER_BYTE));
+        uint8_t share1 = (uint8_t)(s->regs[R_KEY_SHARE1_0 + reg] >>
+                                   (byteoffset * BITS_PER_BYTE));
+        key[ix] = share0 ^ share1;
+    }
+}
+
+static inline size_t ot_kmac_get_keccak_rate_bytes(size_t kstrength)
+{
+    /*
+     * Rate is calculated with:
+     * rate = (1600 - 2*x) where x is the security strength (i.e. half the
+     * capacity).
+     */
+    return (KECCAK_STATE_BITS - 2u * kstrength) / 8u;
+}
+
+static void ot_kmac_reset_state(OtKMACState *s)
+{
+    memset(s->keccak_state, 0, sizeof(s->keccak_state));
+    memset(&s->ltc_state, 0, sizeof(s->ltc_state));
+    s->current_cfg = NULL;
+}
+
+static void ot_kmac_start_pending_app(OtKMACState *s);
+
+static void ot_kmac_return_to_idle(OtKMACState *s)
+{
+    /* flush state */
+    ot_kmac_change_fsm_state(s, KMAC_ST_IDLE);
+    ot_kmac_reset_state(s);
+    ot_kmac_cancel_bh(s);
+    /* now is a good time to check for pending app requests */
+    ot_kmac_start_pending_app(s);
+}
+
+static void ot_kmac_complete_app_req(OtKMACState *s)
+{
+    trace_ot_kmac_app_finished(s->ot_id, s->current_app->index);
+    s->current_app = NULL;
+    ot_kmac_return_to_idle(s);
+}
+
+/* BH handler for processing FIFO and compute */
+static void ot_kmac_process(void *opaque)
+{
+    OtKMACState *s = opaque;
+    OtKMACAppCfg *cfg = s->current_cfg;
+    OtKMACAppRsp rsp;
+
+    g_assert(cfg);
+
+    if (s->current_app) {
+        /* App mode, FIFO should be empty */
+        g_assert(fifo8_is_empty(&s->input_fifo));
+
+        if (s->current_app->req_pending) {
+            sha3_process(&s->ltc_state, s->current_app->req.msg_data,
+                         s->current_app->req.msg_len);
+            s->current_app->req_pending = false;
+            if (s->current_app->req.last) {
+                /* append right-encoded output width if KMAC */
+                if (cfg->mode == OT_KMAC_MODE_KMAC) {
+                    uint8_t enc_out_len[3];
+                    uint32_t output_length = OT_KMAC_APP_DIGEST_BYTES * 8u;
+                    enc_out_len[0] = (output_length >> 8u) & 0xffu;
+                    enc_out_len[1] = output_length & 0xffu;
+                    enc_out_len[2] = 2u;
+                    sha3_process(&s->ltc_state, enc_out_len,
+                                 sizeof(enc_out_len));
+                }
+                /* go to PROCESSING state, response will be sent there */
+                ot_kmac_change_fsm_state(s, KMAC_ST_PROCESSING);
+            } else {
+                /* send empty response as acknowledge */
+                if (s->current_app->fn) {
+                    memset(&rsp, 0, sizeof(rsp));
+                    s->current_app->fn(s->current_app->opaque, &rsp);
+                }
+            }
+        }
+    } else {
+        /* SW mode, process FIFO data */
+        if (!fifo8_is_empty(&s->input_fifo)) {
+            while (!fifo8_is_empty(&s->input_fifo)) {
+                uint8_t value = fifo8_pop(&s->input_fifo);
+                sha3_process(&s->ltc_state, &value, 1);
+            }
+
+            /* assert FIFO Empty interrupt */
+            s->regs[R_INTR_STATE] |= INTR_FIFO_EMPTY_MASK;
+        }
+    }
+
+    switch (s->state) {
+    case KMAC_ST_PROCESSING:
+    case KMAC_ST_SQUEEZING:
+        switch (cfg->mode) {
+        case OT_KMAC_MODE_SHA3:
+            sha3_done(&s->ltc_state, &s->keccak_state[0]);
+            break;
+        case OT_KMAC_MODE_SHAKE:
+            sha3_shake_done(&s->ltc_state, &s->keccak_state[0],
+                            ot_kmac_get_keccak_rate_bytes(cfg->strength));
+            break;
+        /* NOLINTNEXTLINE(bugprone-branch-clone) */
+        case OT_KMAC_MODE_CSHAKE:
+        case OT_KMAC_MODE_KMAC:
+            sha3_cshake_done(&s->ltc_state, &s->keccak_state[0],
+                             ot_kmac_get_keccak_rate_bytes(cfg->strength));
+            break;
+        default:
+            /*
+             * should never happen: mode was validated when going from state
+             * IDLE to START
+             */
+            g_assert_not_reached();
+        }
+
+        /*
+         * "If key is sideloaded and KMAC is SW initiated, hide the capacity
+         * from SW by zeroing", i.e. if not doing a SW-initiated sideloaded
+         * operation, the entire Keccak state (including the meaningless
+         * capacity bytes) should be loaded.
+         */
+        uint32_t reg_cfg = ot_shadow_reg_peek(&s->cfg);
+        bool sideload = FIELD_EX32(reg_cfg, CFG_SHADOWED, SIDELOAD) != 0;
+        if (!sideload || s->current_app) {
+            static_assert(sizeof(s->ltc_state.sha3.sb) == KECCAK_STATE_BYTES,
+                          "LibTomCrypt's Keccak state is an unexpected size");
+            /* manually extract entire Keccak state, including capacity */
+            memcpy(&s->keccak_state[0], s->ltc_state.sha3.sb,
+                   KECCAK_STATE_BYTES);
+        }
+
+        if (s->current_app) {
+            /* App mode, send response and go back to IDLE state */
+            if (s->current_app->fn) {
+                rsp.done = true;
+                memcpy(&rsp.digest_share0[0], &s->keccak_state[0],
+                       sizeof(rsp.digest_share0));
+                memset(&rsp.digest_share1[0], 0, sizeof(rsp.digest_share1));
+                s->current_app->fn(s->current_app->opaque, &rsp);
+            }
+            if (!s->error_awaiting_sw) {
+                ot_kmac_complete_app_req(s);
+            }
+        } else {
+            /* SW mode, go to ABSORBED state */
+            ot_kmac_change_fsm_state(s, KMAC_ST_ABSORBED);
+
+            /* assert KMAC Done interrupt */
+            s->regs[R_INTR_STATE] |= INTR_KMAC_DONE_MASK;
+        }
+
+        break;
+    default:
+        /* nothing to do for other states */
+        break;
+    }
+
+    ot_kmac_update_irq(s);
+}
+
+static inline bool ot_kmac_config_enabled(const OtKMACState *s)
+{
+    /* configuration is enabled only in idle mode */
+    return s->state == KMAC_ST_IDLE;
+}
+
+static inline bool ot_kmac_check_reg_write(const OtKMACState *s, hwaddr reg)
+{
+    if (!ot_kmac_config_enabled(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: write to %s ignored while busy\n", __func__,
+                      s->ot_id, REG_NAME(reg));
+        return false;
+    }
+
+    return true;
+}
+
+static bool ot_kmac_check_mode_and_strength(const OtKMACAppCfg *cfg)
+{
+    switch (cfg->mode) {
+    case OT_KMAC_MODE_SHA3:
+        switch (cfg->strength) {
+        case 224u:
+        case 256u:
+        case 384u:
+        case 512u:
+            return true;
+        default:
+            /* unsupported strength for SHA3 */
+            return false;
+        }
+        break;
+    case OT_KMAC_MODE_SHAKE:
+    case OT_KMAC_MODE_CSHAKE:
+    case OT_KMAC_MODE_KMAC:
+        switch (cfg->strength) {
+        case 128u:
+        case 256u:
+            return true;
+        default:
+            /* unsupported strength for SHAKE/cSHAKE/KMAC */
+            return false;
+        }
+        break;
+    default:
+        /* unsupported mode */
+        return false;
+    }
+}
+
+static inline uint8_t
+ot_kmac_get_prefix_byte(const OtKMACState *s, size_t offset)
+{
+    size_t reg = offset / sizeof(uint32_t);
+    size_t byteoffset = offset - reg * sizeof(uint32_t);
+
+    if (reg >= NUM_PREFIX_REGS) {
+        /*
+         * Just return 0, bounds checking should have been done by the caller
+         * anyway.
+         */
+        return 0;
+    }
+
+    return (uint8_t)(s->regs[R_PREFIX_0 + reg] >> (byteoffset * 8u));
+}
+
+static size_t ot_kmac_left_decode(const OtKMACState *s, size_t offset,
+                                  size_t *value)
+{
+    size_t len;
+    size_t val = 0;
+
+    /* first byte is the length in bytes of encoded value */
+    len = (size_t)ot_kmac_get_prefix_byte(s, offset);
+    if (len < 1u || len > 4u) {
+        return 0;
+    }
+
+    /* compute value */
+    for (size_t ix = 1u; ix < len + 1u; ix++) {
+        val = (val << 8u) | ot_kmac_get_prefix_byte(s, offset + ix);
+    }
+
+    *value = val;
+    return 1u + len;
+}
+
+static bool ot_kmac_decode_sw_prefix(OtKMACState *s)
+{
+    size_t offset = 0;
+    size_t used;
+    OtKMACPrefix *prefix = &s->sw_cfg.prefix;
+
+    used = ot_kmac_left_decode(s, offset, &prefix->funcname_len);
+    prefix->funcname_len /= 8u;
+    offset += used;
+
+    if (prefix->funcname_len > OT_KMAC_PREFIX_FUNCNAME_LEN) {
+        goto error;
+    }
+    for (size_t ix = 0; ix < prefix->funcname_len; ix++) {
+        prefix->funcname[ix] = ot_kmac_get_prefix_byte(s, offset + ix);
+    }
+    offset += prefix->funcname_len;
+
+    used = ot_kmac_left_decode(s, offset, &prefix->customstr_len);
+    prefix->customstr_len /= 8u;
+    offset += used;
+
+    if (prefix->customstr_len > OT_KMAC_PREFIX_CUSTOMSTR_LEN) {
+        goto error;
+    }
+    for (size_t ix = 0; ix < prefix->customstr_len; ix++) {
+        prefix->customstr[ix] = ot_kmac_get_prefix_byte(s, offset + ix);
+    }
+    offset += prefix->funcname_len;
+
+    if (offset <= NUM_PREFIX_REGS * sizeof(uint32_t)) {
+        return true;
+    }
+
+error:
+    memset(prefix, 0, sizeof(OtKMACPrefix));
+    return false;
+}
+
+static bool ot_kmac_check_kmac_sw_prefix(const OtKMACState *s)
+{
+    /*
+     * check that the encoded prefix in PREFIX_x registers starts with a "KMAC"
+     * function name.
+     */
+    return ((s->regs[R_PREFIX_0] & KMAC_PREFIX_0_MASK) == KMAC_PREFIX_0) &&
+           ((s->regs[R_PREFIX_1] & KMAC_PREFIX_1_MASK) == KMAC_PREFIX_1);
+}
+
+static void ot_kmac_process_start(OtKMACState *s)
+{
+    OtKMACAppCfg *cfg = s->current_cfg;
+
+    g_assert(cfg);
+
+    switch (cfg->mode) {
+    case OT_KMAC_MODE_SHA3:
+        switch (cfg->strength) {
+        case 224u:
+            sha3_224_init(&s->ltc_state);
+            break;
+        case 256u:
+            sha3_256_init(&s->ltc_state);
+            break;
+        case 384u:
+            sha3_384_init(&s->ltc_state);
+            break;
+        case 512u:
+            sha3_512_init(&s->ltc_state);
+            break;
+        default:
+            /* should never happen: strength was already validated earlier */
+            g_assert_not_reached();
+        }
+        break;
+    case OT_KMAC_MODE_SHAKE:
+        switch (cfg->strength) {
+        case 128u:
+        case 256u:
+            sha3_shake_init(&s->ltc_state, (int)cfg->strength);
+            break;
+        default:
+            /* should never happen: strength was already validated earlier */
+            g_assert_not_reached();
+        }
+        break;
+    case OT_KMAC_MODE_CSHAKE:
+    case OT_KMAC_MODE_KMAC:
+        switch (cfg->strength) {
+        case 128u:
+        case 256u: {
+            sha3_cshake_init(&s->ltc_state, (int)cfg->strength,
+                             cfg->prefix.funcname, cfg->prefix.funcname_len,
+                             cfg->prefix.customstr, cfg->prefix.customstr_len);
+            /* if KMAC mode is enabled, process key */
+            if (cfg->mode == OT_KMAC_MODE_KMAC) {
+                uint8_t key[NUM_KEY_REGS * sizeof(uint32_t)];
+                size_t keylen = 0;
+                static_assert(OT_KMAC_KEY_SIZE <= ARRAY_SIZE(key),
+                              "key buffer too small to hold sideloaded key");
+                ot_kmac_get_key(s, key, &keylen);
+                sha3_process_kmac_key(&s->ltc_state, key, keylen);
+            }
+            break;
+        }
+        default:
+            /* should never happen: strength was already validated earlier */
+            g_assert_not_reached();
+        }
+        break;
+    default:
+        /* should never happen: mode was already validated earlier */
+        g_assert_not_reached();
+    }
+}
+
+static void ot_kmac_sw_err_processed(OtKMACState *s, int cmd)
+{
+    s->error_awaiting_sw = false;
+
+    if (s->current_app) {
+        /*
+         * If we have already received the entire app request data and sent a
+         * response, now we just need SW acknowledgement to complete.
+         *
+         * If we haven't got all the data, we should wait for it all before
+         * sending a response (but we store SW acknowledgement).
+         */
+        if (s->state == KMAC_ST_PROCESSING || s->state == KMAC_ST_SQUEEZING) {
+            ot_kmac_complete_app_req(s);
+        }
+    } else {
+        /* for SW: ignore further msg feed, absorb, report done & go to idle */
+        switch (s->state) {
+        case KMAC_ST_IDLE:
+        case KMAC_ST_MSG_FEED:
+            ot_kmac_change_fsm_state(s, KMAC_ST_PROCESSING);
+            /* fallthrough */
+        case KMAC_ST_PROCESSING:
+        case KMAC_ST_SQUEEZING:
+            ot_kmac_process((void *)s);
+            /* fallthrough */
+        case KMAC_ST_ABSORBED:
+            ot_kmac_return_to_idle(s);
+            break;
+        case KMAC_ST_TERMINAL_ERROR:
+            break;
+        default:
+            g_assert_not_reached();
+        }
+    }
+
+    /* Clear the status / alert */
+    s->regs[R_STATUS] &= ~R_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK;
+    ot_kmac_update_alert(s);
+
+    /* Clear the error */
+    s->regs[R_ERR_CODE] = 0u;
+
+    /* SW shoud not send a command along with the err_processed bit */
+    if (cmd != OT_KMAC_CMD_NONE) {
+        if (s->current_app) {
+            ot_kmac_report_error(s, OT_KMAC_ERR_SW_ISSUED_CMD_IN_APP_ACTIVE,
+                                 cmd);
+        } else {
+            /* see error encoding in (hw/ip/kmac/rtl/kmac_pkg.sv) */
+            uint32_t info = (1 << 11u);
+            info |= (uint32_t)s->state << 8u;
+            info |= cmd;
+            ot_kmac_report_error(s, OT_KMAC_ERR_SW_CMD_SEQUENCE, info);
+        }
+    }
+}
+
+
+static void ot_kmac_process_sw_command(OtKMACState *s, uint32_t cmd_reg)
+{
+    bool err_processed = (cmd_reg & R_CMD_ERR_PROCESSED_MASK) != 0;
+    int cmd = (int)FIELD_EX32(cmd_reg, CMD, CMD);
+    if (s->error_awaiting_sw) {
+        if (err_processed) {
+            ot_kmac_sw_err_processed(s, cmd);
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Control write without err_processed whilst "
+                          "KMAC is handling an error\n",
+                          __func__, s->ot_id);
+        }
+        return;
+    }
+
+    uint32_t cfg = ot_shadow_reg_peek(&s->cfg);
+    bool err_swsequence = false;
+    bool err_modestrength = false;
+    bool err_prefix = false;
+    bool err_entropy_ready = false;
+
+    /* check if an app is active */
+    if (s->current_app) {
+        ot_kmac_report_error(s, OT_KMAC_ERR_SW_ISSUED_CMD_IN_APP_ACTIVE, cmd);
+        return;
+    }
+
+    trace_ot_kmac_process_sw_command(s->ot_id, cmd, CMD_NAME(cmd));
+
+    switch (s->state) {
+    case KMAC_ST_IDLE:
+        if (cmd == OT_KMAC_CMD_NONE) {
+            /* nothing to do */
+        } else if (cmd == OT_KMAC_CMD_START) {
+            /* retrieve configuration from CFG_SHADOWED register */
+            ot_kmac_get_sw_config(s);
+
+            if (!ot_kmac_check_mode_and_strength(&s->sw_cfg)) {
+                err_modestrength = true;
+                break;
+            }
+            /* if KMAC mode, check prefix & entropy ready */
+            if (s->sw_cfg.mode == OT_KMAC_MODE_KMAC) {
+                if (!ot_kmac_check_kmac_sw_prefix(s)) {
+                    err_prefix = true;
+                    break;
+                }
+                if (false /* TODO: check entropy ready */) {
+                    err_entropy_ready = true;
+                    break;
+                }
+            }
+            /* if cSHAKE or KMAC modes, decode prefix from PREFIX_x registers */
+            if (s->sw_cfg.mode == OT_KMAC_MODE_CSHAKE ||
+                s->sw_cfg.mode == OT_KMAC_MODE_KMAC) {
+                if (!ot_kmac_decode_sw_prefix(s)) {
+                    qemu_log_mask(LOG_GUEST_ERROR,
+                                  "%s: %s: could not decode cSHAKE prefix, "
+                                  "digest result will be wrong!\n",
+                                  __func__, s->ot_id);
+                    memset(&s->sw_cfg.prefix, 0, sizeof(s->sw_cfg.prefix));
+                }
+            }
+
+            s->current_cfg = &s->sw_cfg;
+            ot_kmac_process_start(s);
+            ot_kmac_change_fsm_state(s, KMAC_ST_MSG_FEED);
+        } else {
+            err_swsequence = true;
+        }
+        break;
+    case KMAC_ST_MSG_FEED:
+        if (cmd == OT_KMAC_CMD_NONE) {
+            /* nothing to do */
+        } else if (cmd == OT_KMAC_CMD_PROCESS) {
+            ot_kmac_change_fsm_state(s, KMAC_ST_PROCESSING);
+            ot_kmac_trigger_deferred_bh(s);
+        } else {
+            err_swsequence = true;
+        }
+        break;
+    case KMAC_ST_PROCESSING:
+    case KMAC_ST_SQUEEZING:
+        /* computing stages during which no command can be issued */
+        if (cmd != OT_KMAC_CMD_NONE) {
+            err_swsequence = true;
+        }
+        break;
+    case KMAC_ST_ABSORBED:
+        if (cmd == OT_KMAC_CMD_NONE) {
+            /* nothing to do */
+        } else if (cmd == OT_KMAC_CMD_MANUAL_RUN) {
+            ot_kmac_change_fsm_state(s, KMAC_ST_SQUEEZING);
+            ot_kmac_trigger_deferred_bh(s);
+        } else if (cmd == OT_KMAC_CMD_DONE) {
+            ot_kmac_return_to_idle(s);
+        } else {
+            err_swsequence = true;
+        }
+        break;
+    case KMAC_ST_TERMINAL_ERROR:
+    default:
+        ot_kmac_change_fsm_state(s, KMAC_ST_TERMINAL_ERROR);
+        ot_kmac_reset_state(s);
+        ot_kmac_cancel_bh(s);
+        s->regs[R_STATUS] |= R_STATUS_ALERT_FATAL_FAULT_MASK;
+        ot_kmac_update_alert(s);
+        break;
+    }
+
+    /* report errors */
+    if (err_swsequence | err_modestrength | err_prefix | err_entropy_ready) {
+        uint8_t code;
+        uint32_t info = 0;
+        /*
+         * error encoding is not documented, reference is OpenTitan RTL
+         * (hw/ip/kmac/rtl/kmac_pkg.sv)
+         */
+        info |= err_swsequence ? 1 << 11u : 0;
+        info |= err_modestrength ? 1 << 10u : 0;
+        info |= err_prefix ? 1 << 9u : 0;
+        if (err_swsequence) {
+            info |= (uint32_t)s->state << 8u;
+            info |= cmd;
+            code = OT_KMAC_ERR_SW_CMD_SEQUENCE;
+        } else if (err_modestrength) {
+            info |= FIELD_EX32(cfg, CFG_SHADOWED, MODE) << 4u;
+            info |= FIELD_EX32(cfg, CFG_SHADOWED, KSTRENGTH);
+            code = OT_KMAC_ERR_UNEXPECTED_MODE_STRENGTH;
+        } else if (err_prefix) {
+            code = OT_KMAC_ERR_INCORRECT_FUNCTION_NAME;
+        } else if (err_entropy_ready) {
+            info |= err_entropy_ready ? 1 << 12u : 0;
+            info |= FIELD_EX32(cfg, CFG_SHADOWED, KMAC_EN) ? 1 << 1u : 0;
+            code = OT_KMAC_ERR_SW_HASHING_WITHOUT_ENTROPY_READY;
+        } else {
+            g_assert_not_reached();
+        }
+        ot_kmac_report_error(s, code, info);
+    } else if (!s->error_awaiting_sw) {
+        s->regs[R_ERR_CODE] = 0;
+    }
+}
+
+static void ot_kmac_clock_input(void *opaque, int irq, int level)
+{
+    OtKMACState *s = opaque;
+
+    g_assert(irq == 0);
+
+    s->pclk = (unsigned)level;
+
+    /* TODO: disable KMAC execution when PCLK is 0 */
+}
+
+static uint64_t ot_kmac_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtKMACState *s = OT_KMAC(opaque);
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_CFG_REGWEN:
+        val32 = ot_kmac_config_enabled(s) ? R_CFG_REGWEN_EN_MASK : 0;
+        break;
+    case R_CFG_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->cfg);
+        break;
+    case R_STATUS:
+        val32 = 0u;
+        switch (s->state) {
+        case KMAC_ST_IDLE:
+            val32 |= R_STATUS_SHA3_IDLE_MASK;
+            break;
+        case KMAC_ST_MSG_FEED:
+            val32 |= R_STATUS_SHA3_ABSORB_MASK;
+            break;
+        case KMAC_ST_ABSORBED:
+            val32 |= R_STATUS_SHA3_SQUEEZE_MASK;
+            break;
+        default:
+            break;
+        }
+        uint32_t num_used = fifo8_num_used(&s->input_fifo);
+        if (num_used == 0) {
+            val32 |= R_STATUS_FIFO_EMPTY_MASK;
+        } else {
+            val32 |= ((num_used / 4u) << R_STATUS_FIFO_DEPTH_SHIFT) &
+                     R_STATUS_FIFO_DEPTH_MASK;
+            if (num_used == FIFO_LENGTH) {
+                val32 |= R_STATUS_FIFO_FULL_MASK;
+            }
+        }
+        break;
+    case R_ENTROPY_REFRESH_THRESHOLD_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->entropy_refresh_threshold);
+        break;
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_ENTROPY_PERIOD:
+    case R_ENTROPY_REFRESH_HASH_CNT:
+    case R_PREFIX_0:
+    case R_PREFIX_1:
+    case R_PREFIX_2:
+    case R_PREFIX_3:
+    case R_PREFIX_4:
+    case R_PREFIX_5:
+    case R_PREFIX_6:
+    case R_PREFIX_7:
+    case R_PREFIX_8:
+    case R_PREFIX_9:
+    case R_PREFIX_10:
+    case R_ERR_CODE:
+        val32 = s->regs[reg];
+        break;
+    case R_CMD:
+        /* always read 0: CMD is r0w1c */
+        val32 = 0;
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+    case R_ENTROPY_SEED:
+    case R_KEY_SHARE0_0:
+    case R_KEY_SHARE0_1:
+    case R_KEY_SHARE0_2:
+    case R_KEY_SHARE0_3:
+    case R_KEY_SHARE0_4:
+    case R_KEY_SHARE0_5:
+    case R_KEY_SHARE0_6:
+    case R_KEY_SHARE0_7:
+    case R_KEY_SHARE0_8:
+    case R_KEY_SHARE0_9:
+    case R_KEY_SHARE0_10:
+    case R_KEY_SHARE0_11:
+    case R_KEY_SHARE0_12:
+    case R_KEY_SHARE0_13:
+    case R_KEY_SHARE0_14:
+    case R_KEY_SHARE0_15:
+    case R_KEY_SHARE1_0:
+    case R_KEY_SHARE1_1:
+    case R_KEY_SHARE1_2:
+    case R_KEY_SHARE1_3:
+    case R_KEY_SHARE1_4:
+    case R_KEY_SHARE1_5:
+    case R_KEY_SHARE1_6:
+    case R_KEY_SHARE1_7:
+    case R_KEY_SHARE1_8:
+    case R_KEY_SHARE1_9:
+    case R_KEY_SHARE1_10:
+    case R_KEY_SHARE1_11:
+    case R_KEY_SHARE1_12:
+    case R_KEY_SHARE1_13:
+    case R_KEY_SHARE1_14:
+    case R_KEY_SHARE1_15:
+    case R_KEY_LEN:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_kmac_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                              pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_kmac_regs_write(void *opaque, hwaddr addr, uint64_t value,
+                               unsigned size)
+{
+    OtKMACState *s = OT_KMAC(opaque);
+    (void)size;
+    uint32_t val32 = (uint32_t)value;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_kmac_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        s->regs[R_INTR_STATE] &= ~(val32 & INTR_MASK);
+        ot_kmac_update_irq(s);
+        break;
+    case R_INTR_ENABLE:
+        s->regs[R_INTR_ENABLE] = val32 & INTR_MASK;
+        ot_kmac_update_irq(s);
+        break;
+    case R_INTR_TEST:
+        s->regs[R_INTR_STATE] |= val32 & INTR_MASK;
+        ot_kmac_update_irq(s);
+        break;
+    case R_ALERT_TEST:
+        s->regs[R_ALERT_TEST] |= val32 & ALERT_MASK;
+        ot_kmac_update_alert(s);
+        break;
+    case R_CFG_SHADOWED:
+        if (!ot_kmac_check_reg_write(s, reg)) {
+            break;
+        }
+
+        /* check for unimplemented config bits */
+        if (val32 & R_CFG_SHADOWED_ENTROPY_MODE_MASK) {
+            qemu_log_mask(
+                LOG_UNIMP,
+                "%s: %s: CFG_SHADOWED.ENTROPY_MODE is not supported\n",
+                __func__, s->ot_id);
+        }
+        if (val32 & R_CFG_SHADOWED_ENTROPY_FAST_PROCESS_MASK) {
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: CFG_SHADOWED.ENTROPY_FAST_PROCESS is not "
+                          "supported\n",
+                          __func__, s->ot_id);
+        }
+        if (val32 & R_CFG_SHADOWED_MSG_MASK_MASK) {
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: CFG_SHADOWED.MSG_MASK is not supported\n",
+                          __func__, s->ot_id);
+        }
+        if (val32 & R_CFG_SHADOWED_ENTROPY_READY_MASK) {
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: CFG_SHADOWED.ENTROPY_READY is not "
+                          "supported\n",
+                          __func__, s->ot_id);
+        }
+        if (val32 & R_CFG_SHADOWED_EN_UNSUPPORTED_MODESTRENGTH_MASK) {
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: CFG_SHADOWED.EN_UNSUPPORTED_MODESTRENGTH is "
+                          "not supported\n",
+                          __func__, s->ot_id);
+        }
+
+        val32 &= CFG_MASK;
+        switch (ot_shadow_reg_write(&s->cfg, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_STATUS] |= R_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK;
+            ot_kmac_update_alert(s);
+            break;
+        }
+        break;
+    case R_CMD: {
+        ot_kmac_process_sw_command(s, val32);
+
+        if (val32 & R_CMD_ENTROPY_REQ_MASK) {
+            /* TODO: implement entropy */
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: CMD.ENTROPY_REQ is not supported\n",
+                          __func__, s->ot_id);
+        }
+
+        if (val32 & R_CMD_HASH_CNT_CLR_MASK) {
+            /* TODO: implement entropy */
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: CMD.HASH_CNT_CLR is not supported\n",
+                          __func__, s->ot_id);
+        }
+        break;
+    }
+    case R_ENTROPY_PERIOD:
+        if (!ot_kmac_check_reg_write(s, reg)) {
+            break;
+        }
+
+        val32 &= (R_ENTROPY_PERIOD_PRESCALER_MASK |
+                  R_ENTROPY_PERIOD_WAIT_TIMER_MASK);
+        s->regs[reg] = val32;
+        break;
+    case R_ENTROPY_REFRESH_THRESHOLD_SHADOWED:
+        if (!ot_kmac_check_reg_write(s, reg)) {
+            break;
+        }
+
+        val32 &= R_ENTROPY_REFRESH_THRESHOLD_SHADOWED_THRESHOLD_MASK;
+        switch (ot_shadow_reg_write(&s->entropy_refresh_threshold, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            break;
+        case OT_SHADOW_REG_ERROR:
+        default:
+            s->regs[R_STATUS] |= R_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_MASK;
+            ot_kmac_update_alert(s);
+            break;
+        }
+        break;
+    case R_ENTROPY_SEED:
+        /* TODO: implement entropy */
+        qemu_log_mask(LOG_UNIMP, "%s: %s: R_ENTROPY_SEED_* is not supported\n",
+                      __func__, s->ot_id);
+        break;
+    case R_KEY_LEN:
+        if (!ot_kmac_check_reg_write(s, reg)) {
+            break;
+        }
+        val32 &= R_KEY_LEN_LEN_MASK;
+        s->regs[reg] = val32;
+        if (!ot_kmac_get_key_length(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: :%s invalid KEY_LEN=%d, using key length 0\n",
+                          __func__, s->ot_id, val32);
+        }
+        break;
+    case R_KEY_SHARE0_0:
+    case R_KEY_SHARE0_1:
+    case R_KEY_SHARE0_2:
+    case R_KEY_SHARE0_3:
+    case R_KEY_SHARE0_4:
+    case R_KEY_SHARE0_5:
+    case R_KEY_SHARE0_6:
+    case R_KEY_SHARE0_7:
+    case R_KEY_SHARE0_8:
+    case R_KEY_SHARE0_9:
+    case R_KEY_SHARE0_10:
+    case R_KEY_SHARE0_11:
+    case R_KEY_SHARE0_12:
+    case R_KEY_SHARE0_13:
+    case R_KEY_SHARE0_14:
+    case R_KEY_SHARE0_15:
+    case R_KEY_SHARE1_0:
+    case R_KEY_SHARE1_1:
+    case R_KEY_SHARE1_2:
+    case R_KEY_SHARE1_3:
+    case R_KEY_SHARE1_4:
+    case R_KEY_SHARE1_5:
+    case R_KEY_SHARE1_6:
+    case R_KEY_SHARE1_7:
+    case R_KEY_SHARE1_8:
+    case R_KEY_SHARE1_9:
+    case R_KEY_SHARE1_10:
+    case R_KEY_SHARE1_11:
+    case R_KEY_SHARE1_12:
+    case R_KEY_SHARE1_13:
+    case R_KEY_SHARE1_14:
+    case R_KEY_SHARE1_15:
+    case R_PREFIX_0:
+    case R_PREFIX_1:
+    case R_PREFIX_2:
+    case R_PREFIX_3:
+    case R_PREFIX_4:
+    case R_PREFIX_5:
+    case R_PREFIX_6:
+    case R_PREFIX_7:
+    case R_PREFIX_8:
+    case R_PREFIX_9:
+    case R_PREFIX_10:
+        if (!ot_kmac_check_reg_write(s, reg)) {
+            break;
+        }
+        s->regs[reg] = val32;
+        break;
+    case R_CFG_REGWEN:
+    case R_STATUS:
+    case R_ENTROPY_REFRESH_HASH_CNT:
+    case R_ERR_CODE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static uint64_t ot_kmac_state_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtKMACState *s = OT_KMAC(opaque);
+    uint32_t val32;
+
+    if (s->state != KMAC_ST_ABSORBED) {
+        /*
+         * State is valid only after all absorbing process is completed.
+         * Otherwise it will be zero to prevent information leakage.
+         */
+        if (!s->invalid_state_read) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: STATE read while in invalid FSM state\n",
+                          __func__, s->ot_id);
+            s->invalid_state_read = true;
+        }
+        val32 = 0;
+    } else {
+        uint32_t cfg = ot_shadow_reg_peek(&s->cfg);
+        bool byteswap = FIELD_EX32(cfg, CFG_SHADOWED, STATE_ENDIANNESS) != 0;
+        hwaddr offset = addr;
+        int share = 0;
+
+        /* reset invalid state marker */
+        s->invalid_state_read = false;
+
+        /* compute share index */
+        while (offset > KECCAK_STATE_SHARE_BYTES) {
+            offset -= KECCAK_STATE_SHARE_BYTES;
+            share++;
+        }
+
+        switch (share) {
+        case 0:
+            if (addr + size <= KECCAK_STATE_BYTES) {
+                val32 = 0;
+                for (unsigned ix = 0; ix < size; ix++) {
+                    size_t byte_offset = byteswap ? ix : size - 1 - ix;
+                    val32 =
+                        (val32 << 8u) + s->keccak_state[offset + byte_offset];
+                }
+            } else {
+                val32 = 0;
+            }
+            break;
+        case 1:
+            /*
+             * TODO: implement masking. Current version returns unmasked state
+             * in first share and zeros in second one.
+             */
+            val32 = 0;
+            break;
+        default:
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n",
+                          __func__, s->ot_id, (uint32_t)addr);
+            val32 = 0;
+            break;
+        }
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_kmac_state_read_out(s->ot_id, (uint32_t)addr, val32, pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_kmac_state_write(void *opaque, hwaddr addr, uint64_t value,
+                                unsigned size)
+{
+    OtKMACState *s = OT_KMAC(opaque);
+    (void)addr;
+    (void)value;
+    (void)size;
+    /* on real hardware, writes to STATE are ignored */
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: STATE is read only\n", __func__,
+                  s->ot_id);
+}
+
+static uint64_t ot_kmac_msgfifo_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtKMACState *s = OT_KMAC(opaque);
+    (void)addr;
+    (void)size;
+    /* on real hardware, writes to FIFO will block. Let's just return 0. */
+    qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: MSG_FIFO is write only\n", __func__,
+                  s->ot_id);
+    return 0;
+}
+
+static void ot_kmac_msgfifo_write(void *opaque, hwaddr addr, uint64_t value,
+                                  unsigned size)
+{
+    OtKMACState *s = OT_KMAC(opaque);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_kmac_msgfifo_write(s->ot_id, (uint32_t)addr, (uint32_t)value, size,
+                                pc);
+
+    /* trigger error if an app is running or not in MSG_FEED state */
+    if (s->current_app || s->state != KMAC_ST_MSG_FEED) {
+        /* info field mux_sel=1 (SW) or 2 (App) */
+        ot_kmac_report_error(s, OT_KMAC_ERR_SW_PUSHED_MSG_FIFO,
+                             s->current_app ? 2 : 1);
+        return;
+    }
+
+    uint32_t cfg = ot_shadow_reg_peek(&s->cfg);
+    bool byteswap = FIELD_EX32(cfg, CFG_SHADOWED, MSG_ENDIANNESS) != 0;
+
+    if (fifo8_num_free(&s->input_fifo) < size) {
+        /*
+         * Not enough room in FIFO. Real hardware would fill the FIFO and stall
+         * but it cannot be done in QEMU so instead we artificially process data
+         * now to empty the FIFO.
+         */
+        ot_kmac_process(s);
+    }
+
+    for (unsigned ix = 0; ix < size; ix++) {
+        size_t byteoffset = byteswap ? (size - 1u - ix) : ix;
+        uint8_t b = (uint8_t)(value >> (byteoffset * 8u));
+        fifo8_push(&s->input_fifo, b);
+    }
+
+    /* trigger delayed processing of FIFO */
+    ot_kmac_trigger_deferred_bh(s);
+}
+
+static bool ot_kmac_compare_app_cfg(const OtKMACAppCfg *cfg1,
+                                    const OtKMACAppCfg *cfg2)
+{
+    return cfg1->mode == cfg2->mode && cfg1->strength == cfg2->strength &&
+           cfg1->prefix.funcname_len == cfg2->prefix.funcname_len &&
+           cfg1->prefix.customstr_len == cfg2->prefix.customstr_len &&
+           memcmp(cfg1->prefix.funcname, cfg2->prefix.funcname,
+                  cfg1->prefix.funcname_len) == 0 &&
+           memcmp(cfg1->prefix.customstr, cfg2->prefix.customstr,
+                  cfg1->prefix.customstr_len) == 0;
+}
+
+static void ot_kmac_connect_app(OtKMACState *s, unsigned app_idx,
+                                const OtKMACAppCfg *cfg, OtKmacResponse fn,
+                                void *opaque)
+{
+    g_assert(app_idx < s->num_app);
+
+    OtKMACApp *app = &s->apps[app_idx];
+
+    if (app->connected) {
+        if (ot_kmac_compare_app_cfg(&app->cfg, cfg) && fn == app->fn &&
+            opaque == app->opaque) {
+            /*
+             * silently ignore duplicate connection from the same component with
+             * the same parameters.
+             */
+            return;
+        }
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: ignoring connection to already used app index %u\n",
+            __func__, s->ot_id, app_idx);
+        return;
+    }
+
+    app->index = app_idx;
+    app->cfg = *cfg;
+    if (!ot_kmac_check_mode_and_strength(&app->cfg)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Invalid mode/strength for app index %u\n",
+                      __func__, s->ot_id, app_idx);
+        /* force dummy values, digest will be wrong */
+        app->cfg.mode = OT_KMAC_MODE_CSHAKE;
+        app->cfg.strength = 128u;
+    }
+    if (app->cfg.mode == OT_KMAC_MODE_KMAC) {
+        if (memcmp(app->cfg.prefix.funcname, "KMAC", 4u) != 0 ||
+            app->cfg.prefix.funcname_len != 4u) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: invalid config for app index %u: "
+                          "invalid prefix for KMAC\n",
+                          __func__, s->ot_id, app_idx);
+        }
+    }
+    app->fn = fn;
+    app->opaque = opaque;
+    app->connected = true;
+}
+
+static void ot_kmac_start_pending_app(OtKMACState *s)
+{
+    if (s->state == KMAC_ST_IDLE && s->pending_apps) {
+        /* select pending app */
+        uint8_t app_idx = ctz32(s->pending_apps);
+        g_assert(app_idx < s->num_app);
+        s->current_app = &s->apps[app_idx];
+        s->pending_apps &= ~(1u << app_idx);
+
+        /* process start */
+        trace_ot_kmac_app_start(s->ot_id, app_idx);
+        s->current_cfg = &s->current_app->cfg;
+        ot_kmac_process_start(s);
+        ot_kmac_change_fsm_state(s, KMAC_ST_MSG_FEED);
+
+        /* trigger deferred compute */
+        qemu_bh_schedule(s->bh);
+    }
+}
+
+static void ot_kmac_app_request(OtKMACState *s, unsigned app_idx,
+                                const OtKMACAppReq *req)
+{
+    g_assert(app_idx < s->num_app);
+    g_assert(req);
+    g_assert(req->msg_len <= OT_KMAC_APP_MSG_BYTES);
+
+    if (trace_event_get_state(TRACE_OT_KMAC_APP_REQUEST)) {
+        trace_ot_kmac_app_request(s->ot_id, app_idx, req->last, req->msg_len,
+                                  ot_common_lhexdump(req->msg_data,
+                                                     req->msg_len, false,
+                                                     s->hexstr,
+                                                     OT_KMAC_KEY_HEXSTR_SIZE));
+    }
+
+    OtKMACApp *app = &s->apps[app_idx];
+
+    if (app->req_pending) {
+        error_setg(&error_fatal,
+                   "%s: %s: dropping request to already busy app index %u",
+                   __func__, s->ot_id, app_idx);
+    }
+
+    /* save request */
+    app->req = *req;
+    app->req_pending = true;
+
+    /* check if app already started */
+    if (s->current_app == app &&
+        (s->state == KMAC_ST_IDLE || s->state == KMAC_ST_MSG_FEED)) {
+        /* yes, receiving more data, trigger deferred compute */
+        qemu_bh_schedule(s->bh);
+    } else {
+        /* no, mark as pending and try to start */
+        s->pending_apps |= (1u << app_idx);
+        ot_kmac_start_pending_app(s);
+    }
+}
+
+static const Property ot_kmac_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtKMACState, ot_id),
+    DEFINE_PROP_STRING("clock-name", OtKMACState, clock_name),
+    DEFINE_PROP_LINK("clock-src", OtKMACState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+    DEFINE_PROP_LINK("edn", OtKMACState, edn, TYPE_OT_EDN, OtEDNState *),
+    DEFINE_PROP_UINT8("edn-ep", OtKMACState, edn_ep, UINT8_MAX),
+    DEFINE_PROP_UINT8("num-app", OtKMACState, num_app, 0),
+};
+
+static const MemoryRegionOps ot_kmac_regs_ops = {
+    .read = &ot_kmac_regs_read,
+    .write = &ot_kmac_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 4u,
+        .max_access_size = 4u,
+    },
+};
+
+static const MemoryRegionOps ot_kmac_state_ops = {
+    .read = &ot_kmac_state_read,
+    .write = &ot_kmac_state_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 1u,
+        .max_access_size = 4u,
+    },
+};
+
+static const MemoryRegionOps ot_kmac_msgfifo_ops = {
+    .read = &ot_kmac_msgfifo_read,
+    .write = &ot_kmac_msgfifo_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 1u,
+        .max_access_size = 4u,
+    },
+};
+
+static void ot_kmac_reset_enter(Object *obj, ResetType type)
+{
+    OtKMACClass *c = OT_KMAC_GET_CLASS(obj);
+    OtKMACState *s = OT_KMAC(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    ot_kmac_cancel_bh(s);
+
+    ot_kmac_change_fsm_state(s, KMAC_ST_IDLE);
+    ot_kmac_reset_state(s);
+    memset(&s->sw_cfg, 0, sizeof(OtKMACAppCfg));
+    s->current_app = NULL;
+    s->pending_apps = 0;
+    s->invalid_state_read = false;
+    s->error_awaiting_sw = false;
+    memset(s->regs, 0, sizeof(*(s->regs)));
+    s->regs[R_STATUS] = 0x4001u;
+    ot_shadow_reg_init(&s->cfg, 0u);
+    ot_shadow_reg_init(&s->entropy_refresh_threshold, 0u);
+
+    ot_kmac_update_irq(s);
+    ot_kmac_update_alert(s);
+
+    fifo8_reset(&s->input_fifo);
+
+    memset(s->sl_key, 0, sizeof(OtKMACKey));
+
+    if (!s->clock_src_name) {
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_name =
+            ic->get_clock_source(ii, s->clock_name, DEVICE(s), &error_fatal);
+        qemu_irq in_irq =
+            qdev_get_gpio_in_named(DEVICE(s), OT_KMAC_CLOCK_INPUT, 0);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_name, 0, in_irq);
+
+        if (object_dynamic_cast(OBJECT(s->clock_src), TYPE_OT_CLKMGR)) {
+            char *hint_name =
+                g_strdup_printf(OT_CLOCK_HINT_PREFIX "%s", s->clock_name);
+            qemu_irq hint_irq =
+                qdev_get_gpio_in_named(s->clock_src, hint_name, 0);
+            g_assert(hint_irq);
+            qdev_connect_gpio_out_named(DEVICE(s), OT_KMAC_CLOCK_ACTIVE, 0,
+                                        hint_irq);
+            g_free(hint_name);
+        }
+    }
+}
+
+static void ot_kmac_realize(DeviceState *dev, Error **errp)
+{
+    OtKMACState *s = OT_KMAC(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->clock_name);
+    g_assert(s->clock_src);
+
+    /* make sure num-app property is set */
+    g_assert(s->num_app > 0);
+
+    /* make sure we don't overflow pending_apps bitmask */
+    g_assert(s->num_app <= 32);
+
+    s->apps = g_new0(OtKMACApp, s->num_app);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_kmac_clock_input,
+                            OT_KMAC_CLOCK_INPUT, 1);
+}
+
+static void ot_kmac_init(Object *obj)
+{
+    OtKMACState *s = OT_KMAC(obj);
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->irqs); ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    ibex_qdev_init_irq(obj, &s->clock_active, OT_KMAC_CLOCK_ACTIVE);
+
+    memory_region_init(&s->mmio, OBJECT(s), TYPE_OT_KMAC, OT_KMAC_WHOLE_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    memory_region_init_io(&s->regs_mmio, obj, &ot_kmac_regs_ops, s,
+                          TYPE_OT_KMAC ".regs", REGS_SIZE);
+    memory_region_add_subregion(&s->mmio, OT_KMAC_REGS_BASE, &s->regs_mmio);
+
+    memory_region_init_io(&s->state_mmio, obj, &ot_kmac_state_ops, s,
+                          TYPE_OT_KMAC ".state", OT_KMAC_STATE_SIZE);
+    memory_region_add_subregion(&s->mmio, OT_KMAC_STATE_BASE, &s->state_mmio);
+
+    memory_region_init_io(&s->msgfifo_mmio, obj, &ot_kmac_msgfifo_ops, s,
+                          TYPE_OT_KMAC ".msgfifo", OT_KMAC_MSG_FIFO_SIZE);
+    memory_region_add_subregion(&s->mmio, OT_KMAC_MSG_FIFO_BASE,
+                                &s->msgfifo_mmio);
+
+    /* setup deferred processing */
+    s->bh_timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_kmac_bh_timer_handler, s);
+    s->bh = qemu_bh_new(&ot_kmac_process, s);
+
+    /* FIFO sizes as per OT Spec */
+    fifo8_create(&s->input_fifo, FIFO_LENGTH);
+
+    s->sl_key = g_new0(OtKMACKey, 1u);
+
+    s->hexstr = g_new0(char, OT_KMAC_KEY_HEXSTR_SIZE);
+}
+
+static void ot_kmac_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_kmac_realize;
+    device_class_set_props(dc, ot_kmac_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtKMACClass *kc = OT_KMAC_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_kmac_reset_enter, NULL, NULL,
+                                       &kc->parent_phases);
+
+    kc->connect_app = &ot_kmac_connect_app;
+    kc->app_request = &ot_kmac_app_request;
+
+    OtKeySinkIfClass *sc = OT_KEY_SINK_IF_CLASS(klass);
+    sc->push_key = &ot_kmac_push_key;
+}
+
+static const TypeInfo ot_kmac_info = {
+    .name = TYPE_OT_KMAC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtKMACState),
+    .instance_init = &ot_kmac_init,
+    .class_size = sizeof(OtKMACClass),
+    .class_init = &ot_kmac_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_OT_KEY_SINK_IF },
+            {},
+        },
+};
+
+static void ot_kmac_register_types(void)
+{
+    type_register_static(&ot_kmac_info);
+}
+
+type_init(ot_kmac_register_types);
diff --git a/hw/opentitan/ot_lc_ctrl.c b/hw/opentitan/ot_lc_ctrl.c
new file mode 100644
index 0000000000000..71ddd0f8d27d1
--- /dev/null
+++ b/hw/opentitan/ot_lc_ctrl.c
@@ -0,0 +1,2436 @@
+/*
+ * QEMU OpenTitan Life Cycle controller device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Based on OpenTitan 0fc384d8a6
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_kmac.h"
+#include "hw/opentitan/ot_lc_ctrl.h"
+#include "hw/opentitan/ot_otp_if.h"
+#include "hw/opentitan/ot_pwrmgr.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "tomcrypt.h"
+#include "trace.h"
+#include "trace/trace-hw_opentitan.h"
+
+#undef OT_LC_CTRL_DEBUG
+
+#define NUM_ALERTS               3u
+#define PRODUCT_ID_WIDTH         16u
+#define SILICON_CREATOR_ID_WIDTH 16u
+#define REVISION_ID_WIDTH        8u
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x00u)
+    SHARED_FIELD(ALERT_FATAL_PROG_ERROR, 0u, 1u)
+    SHARED_FIELD(ALERT_FATAL_STATE_ERROR, 1u, 1u)
+    SHARED_FIELD(ALERT_FATAL_BUS_INTEG_ERROR, 2u, 1u)
+REG32(STATUS, 0x04u)
+    FIELD(STATUS, INITIALIZED, 0u, 1u)
+    FIELD(STATUS, READY, 1u, 1u)
+    FIELD(STATUS, EXT_CLOCK_SWITCHED, 2u, 1u)
+    FIELD(STATUS, TRANSITION_SUCCESSFUL, 3u, 1u)
+    FIELD(STATUS, TRANSITION_COUNT_ERROR, 4u, 1u)
+    FIELD(STATUS, TRANSITION_ERROR, 5u, 1u)
+    FIELD(STATUS, TOKEN_ERROR, 6u, 1u)
+    FIELD(STATUS, FLASH_RMA_ERROR, 7u, 1u)
+    FIELD(STATUS, OTP_ERROR, 8u, 1u)
+    FIELD(STATUS, STATE_ERROR, 9u, 1u)
+    FIELD(STATUS, BUS_INTEG_ERROR, 10u, 1u)
+    FIELD(STATUS, OTP_PARTITION_ERROR, 11u, 1u)
+REG32(CLAIM_TRANSITION_IF_REGWEN, 0x08u)
+    FIELD(CLAIM_TRANSITION_IF_REGWEN, EN, 0u, 1u)
+REG32(CLAIM_TRANSITION_IF, 0x0cu)
+    FIELD(CLAIM_TRANSITION_IF, MUTEX, 0u, 8u)
+REG32(TRANSITION_REGWEN, 0x10u)
+    FIELD(TRANSITION_REGWEN, EN, 0u, 1u)
+REG32(TRANSITION_CMD, 0x14u)
+    FIELD(TRANSITION_CMD, START, 0u, 1u)
+REG32(TRANSITION_CTRL, 0x18u)
+    FIELD(TRANSITION_CTRL, EXT_CLOCK_EN, 0u, 1u)
+    FIELD(TRANSITION_CTRL, VOLATILE_RAW_UNLOCK, 1u, 1u)
+REG32(TRANSITION_TOKEN_0, 0x1cu)
+REG32(TRANSITION_TOKEN_1, 0x20u)
+REG32(TRANSITION_TOKEN_2, 0x24u)
+REG32(TRANSITION_TOKEN_3, 0x28u)
+REG32(TRANSITION_TARGET, 0x2cu)
+    FIELD(TRANSITION_TARGET, STATE, 0u, 30u)
+REG32(OTP_VENDOR_TEST_CTRL, 0x30u)
+REG32(OTP_VENDOR_TEST_STATUS, 0x34u)
+REG32(LC_STATE, 0x38u)
+    FIELD(LC_STATE, STATE, 0u, 30u)
+REG32(LC_TRANSITION_CNT, 0x3cu)
+    FIELD(LC_TRANSITION_CNT, CNT, 0u, 5u)
+REG32(LC_ID_STATE, 0x40u)
+REG32(HW_REVISION0, 0x44u)
+    FIELD(HW_REVISION0, PRODUCT_ID, 0u, PRODUCT_ID_WIDTH)
+    FIELD(HW_REVISION0, SILICON_CREATOR_ID, PRODUCT_ID_WIDTH,
+          SILICON_CREATOR_ID_WIDTH)
+REG32(HW_REVISION1, 0x48u)
+    FIELD(HW_REVISION1, REVISION_ID, 0u, REVISION_ID_WIDTH)
+    FIELD(HW_REVISION1, RESERVED,
+          REVISION_ID_WIDTH, (32u - REVISION_ID_WIDTH))
+REG32(DEVICE_ID_0, 0x4cu)
+REG32(DEVICE_ID_1, 0x50u)
+REG32(DEVICE_ID_2, 0x54u)
+REG32(DEVICE_ID_3, 0x58u)
+REG32(DEVICE_ID_4, 0x5cu)
+REG32(DEVICE_ID_5, 0x60u)
+REG32(DEVICE_ID_6, 0x64u)
+REG32(DEVICE_ID_7, 0x68u)
+REG32(MANUF_STATE_0, 0x6cu)
+REG32(MANUF_STATE_1, 0x70u)
+REG32(MANUF_STATE_2, 0x74u)
+REG32(MANUF_STATE_3, 0x78u)
+REG32(MANUF_STATE_4, 0x7cu)
+REG32(MANUF_STATE_5, 0x80u)
+REG32(MANUF_STATE_6, 0x84u)
+REG32(MANUF_STATE_7, 0x88u)
+/* clang-format on */
+
+#define ALERT_TEST_WMASK \
+    (ALERT_FATAL_PROG_ERROR_MASK | ALERT_FATAL_STATE_ERROR_MASK | \
+     ALERT_FATAL_BUS_INTEG_ERROR_MASK)
+#define TRANSITION_CTRL_WMASK \
+    (TRANSITION_CTRL_EXT_CLOCK_EN_MASK | \
+     TRANSITION_CTRL_VOLATILE_RAW_UNLOCK_MASK)
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_MANUF_STATE_7)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define R_FIRST_EXCLUSIVE_REG (R_TRANSITION_TOKEN_0)
+#define R_LAST_EXCLUSIVE_REG  (R_TRANSITION_TARGET)
+#define EXCLUSIVE_REGS_COUNT  (R_LAST_EXCLUSIVE_REG - R_FIRST_EXCLUSIVE_REG + 1u)
+#define XREGS_OFFSET(_r_)     ((_r_) - R_FIRST_EXCLUSIVE_REG)
+
+#define LC_TRANSITION_COUNT_MAX 24u
+#define LC_TOKEN_WIDTH          16u /* 128 bits */
+#define LC_TOKEN_DWORDS         (LC_TOKEN_WIDTH / sizeof(uint64_t))
+
+#define LC_DEV_ID_WIDTH      OT_REG_SPAN(DEVICE_ID, 7)
+#define LC_MANUF_STATE_WIDTH OT_REG_SPAN(MANUF_STATE, 7)
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(CLAIM_TRANSITION_IF_REGWEN),
+    REG_NAME_ENTRY(CLAIM_TRANSITION_IF),
+    REG_NAME_ENTRY(TRANSITION_REGWEN),
+    REG_NAME_ENTRY(TRANSITION_CMD),
+    REG_NAME_ENTRY(TRANSITION_CTRL),
+    REG_NAME_ENTRY(TRANSITION_TOKEN_0),
+    REG_NAME_ENTRY(TRANSITION_TOKEN_1),
+    REG_NAME_ENTRY(TRANSITION_TOKEN_2),
+    REG_NAME_ENTRY(TRANSITION_TOKEN_3),
+    REG_NAME_ENTRY(TRANSITION_TARGET),
+    REG_NAME_ENTRY(OTP_VENDOR_TEST_CTRL),
+    REG_NAME_ENTRY(OTP_VENDOR_TEST_STATUS),
+    REG_NAME_ENTRY(LC_STATE),
+    REG_NAME_ENTRY(LC_TRANSITION_CNT),
+    REG_NAME_ENTRY(LC_ID_STATE),
+    REG_NAME_ENTRY(HW_REVISION0),
+    REG_NAME_ENTRY(HW_REVISION1),
+    REG_NAME_ENTRY(DEVICE_ID_0),
+    REG_NAME_ENTRY(DEVICE_ID_1),
+    REG_NAME_ENTRY(DEVICE_ID_2),
+    REG_NAME_ENTRY(DEVICE_ID_3),
+    REG_NAME_ENTRY(DEVICE_ID_4),
+    REG_NAME_ENTRY(DEVICE_ID_5),
+    REG_NAME_ENTRY(DEVICE_ID_6),
+    REG_NAME_ENTRY(DEVICE_ID_7),
+    REG_NAME_ENTRY(MANUF_STATE_0),
+    REG_NAME_ENTRY(MANUF_STATE_1),
+    REG_NAME_ENTRY(MANUF_STATE_2),
+    REG_NAME_ENTRY(MANUF_STATE_3),
+    REG_NAME_ENTRY(MANUF_STATE_4),
+    REG_NAME_ENTRY(MANUF_STATE_5),
+    REG_NAME_ENTRY(MANUF_STATE_6),
+    REG_NAME_ENTRY(MANUF_STATE_7),
+};
+#undef REG_NAME_ENTRY
+
+#define NUM_LC_STATE            (LC_STATE_VALID_COUNT)
+#define NUM_LC_TRANSITION_COUNT 25u
+#define NUM_OWNERSHIP           9u
+#define NUM_SOC_DBG             3u
+
+#define LC_TRANSITION_COUNT_WORDS 24u
+#define LC_STATE_WORDS            20u
+#define OWNERSHIP_WORDS           8u
+#define SOC_DBG_WORDS             2u
+
+#define LC_TRANSITION_COUNT_BYTES \
+    ((LC_TRANSITION_COUNT_WORDS) / sizeof(uint16_t))
+#define LC_STATE_BYTES ((LC_STATE_WORDS) / sizeof(uint16_t))
+#define OWNERSHIP_SIZE ((OWNERSHIP_WORDS) / sizeof(uint16_t))
+#define SOC_DBG_SIZE   ((SOC_DBG_WORDS) / sizeof(uint16_t))
+
+#define LC_STATE_BIT_WIDTH 5u
+#define LC_ENCODE_STATE(_x_) \
+    (((_x_) << (LC_STATE_BIT_WIDTH * 0)) | \
+     ((_x_) << (LC_STATE_BIT_WIDTH * 1u)) | \
+     ((_x_) << (LC_STATE_BIT_WIDTH * 2u)) | \
+     ((_x_) << (LC_STATE_BIT_WIDTH * 3u)) | \
+     ((_x_) << (LC_STATE_BIT_WIDTH * 4u)) | \
+     ((_x_) << (LC_STATE_BIT_WIDTH * 5u)))
+#define LC_STATE_BITS(_elc_) ((_elc_) & ((1u << LC_STATE_BIT_WIDTH) - 1u))
+
+#define LC_ID_STATE_BLANK        0
+#define LC_ID_STATE_PERSONALIZED 0x55555555u
+#define LC_ID_STATE_INVALID      0xaaaaaaaau
+
+/* Share lifecycle state definitions */
+typedef enum {
+    LC_STATE_RAW,
+    LC_STATE_TESTUNLOCKED0,
+    LC_STATE_TESTLOCKED0,
+    LC_STATE_TESTUNLOCKED1,
+    LC_STATE_TESTLOCKED1,
+    LC_STATE_TESTUNLOCKED2,
+    LC_STATE_TESTLOCKED2,
+    LC_STATE_TESTUNLOCKED3,
+    LC_STATE_TESTLOCKED3,
+    LC_STATE_TESTUNLOCKED4,
+    LC_STATE_TESTLOCKED4,
+    LC_STATE_TESTUNLOCKED5,
+    LC_STATE_TESTLOCKED5,
+    LC_STATE_TESTUNLOCKED6,
+    LC_STATE_TESTLOCKED6,
+    LC_STATE_TESTUNLOCKED7,
+    LC_STATE_DEV,
+    LC_STATE_PROD,
+    LC_STATE_PRODEND,
+    LC_STATE_RMA,
+    LC_STATE_SCRAP,
+    LC_STATE_VALID_COUNT,
+    LC_STATE_POST_TRANSITION = LC_STATE_VALID_COUNT,
+    LC_STATE_ESCALATE,
+    LC_STATE_INVALID,
+    LC_STATE_TOTAL_COUNT
+} OtLcState;
+
+typedef enum {
+    LC_ENC_STATE_RAW = LC_ENCODE_STATE(LC_STATE_RAW),
+    LC_ENC_STATE_TESTUNLOCKED0 = LC_ENCODE_STATE(LC_STATE_TESTUNLOCKED0),
+    LC_ENC_STATE_TESTLOCKED0 = LC_ENCODE_STATE(LC_STATE_TESTLOCKED0),
+    LC_ENC_STATE_TESTUNLOCKED1 = LC_ENCODE_STATE(LC_STATE_TESTUNLOCKED1),
+    LC_ENC_STATE_TESTLOCKED1 = LC_ENCODE_STATE(LC_STATE_TESTLOCKED1),
+    LC_ENC_STATE_TESTUNLOCKED2 = LC_ENCODE_STATE(LC_STATE_TESTUNLOCKED2),
+    LC_ENC_STATE_TESTLOCKED2 = LC_ENCODE_STATE(LC_STATE_TESTLOCKED2),
+    LC_ENC_STATE_TESTUNLOCKED3 = LC_ENCODE_STATE(LC_STATE_TESTUNLOCKED3),
+    LC_ENC_STATE_TESTLOCKED3 = LC_ENCODE_STATE(LC_STATE_TESTLOCKED3),
+    LC_ENC_STATE_TESTUNLOCKED4 = LC_ENCODE_STATE(LC_STATE_TESTUNLOCKED4),
+    LC_ENC_STATE_TESTLOCKED4 = LC_ENCODE_STATE(LC_STATE_TESTLOCKED4),
+    LC_ENC_STATE_TESTUNLOCKED5 = LC_ENCODE_STATE(LC_STATE_TESTUNLOCKED5),
+    LC_ENC_STATE_TESTLOCKED5 = LC_ENCODE_STATE(LC_STATE_TESTLOCKED5),
+    LC_ENC_STATE_TESTUNLOCKED6 = LC_ENCODE_STATE(LC_STATE_TESTUNLOCKED6),
+    LC_ENC_STATE_TESTLOCKED6 = LC_ENCODE_STATE(LC_STATE_TESTLOCKED6),
+    LC_ENC_STATE_TESTUNLOCKED7 = LC_ENCODE_STATE(LC_STATE_TESTUNLOCKED7),
+    LC_ENC_STATE_DEV = LC_ENCODE_STATE(LC_STATE_DEV),
+    LC_ENC_STATE_PROD = LC_ENCODE_STATE(LC_STATE_PROD),
+    LC_ENC_STATE_PRODEND = LC_ENCODE_STATE(LC_STATE_PRODEND),
+    LC_ENC_STATE_RMA = LC_ENCODE_STATE(LC_STATE_RMA),
+    LC_ENC_STATE_SCRAP = LC_ENCODE_STATE(LC_STATE_SCRAP),
+    LC_ENC_STATE_POST_TRANSITION = LC_ENCODE_STATE(LC_STATE_POST_TRANSITION),
+    LC_ENC_STATE_ESCALATE = LC_ENCODE_STATE(LC_STATE_ESCALATE),
+    LC_ENC_STATE_INVALID = LC_ENCODE_STATE(LC_STATE_INVALID),
+} OtLcEncodedState;
+
+typedef uint16_t OtLcCtrlStateValue[LC_STATE_WORDS];
+typedef uint16_t OtLcCtrlTransitionCountValue[LC_TRANSITION_COUNT_WORDS];
+typedef uint16_t OtLcCtrlOwnershipValue[OWNERSHIP_WORDS];
+typedef uint16_t OtLcCtrlSocDbgValue[SOC_DBG_WORDS];
+
+typedef enum {
+    LC_IF_NONE,
+    LC_IF_SW, /* CPU requester */
+    LC_IF_DMI, /* DMI requester */
+} OtLcCtrlIf;
+
+#define EXCLUSIVE_SLOTS_COUNT 2u
+#define LC_XSLOT(_ifreq_)     (((unsigned)(_ifreq_)) - 1u)
+
+typedef enum {
+    ST_RESET,
+    ST_IDLE,
+    ST_CLK_MUX,
+    ST_CNT_INCR,
+    ST_CNT_PROG,
+    ST_TRANS_CHECK,
+    ST_TOKEN_HASH,
+    ST_FLASH_RMA,
+    ST_TOKEN_CHECK0,
+    ST_TOKEN_CHECK1,
+    ST_TRANS_PROG,
+    ST_POST_TRANS,
+    ST_SCRAP,
+    ST_ESCALATE,
+    ST_INVALID,
+} OtLcCtrlFsmState;
+
+typedef enum {
+    ST_KMAC_IDLE,
+    ST_KMAC_FIRST,
+    ST_KMAC_SECOND,
+    ST_KMAC_WAIT,
+} OtLcCtrlFsmKmacState;
+
+typedef enum {
+    LC_TK_INVALID, /* SBZ */
+    LC_TK_ZERO,
+    LC_TK_RAW_UNLOCK,
+    LC_TK_TEST_UNLOCK,
+    LC_TK_TEST_EXIT,
+    LC_TK_RMA,
+    LC_TK_COUNT,
+} OtLcCtrlToken;
+
+/* Life cycle state group diversification value for keymgr */
+typedef enum {
+    LC_DIV_INVALID,
+    LC_DIV_TEST_UNLOCKED,
+    LC_DIV_DEV,
+    LC_DIV_PROD,
+    LC_DIV_RMA,
+    LC_DIV_COUNT,
+} OtLcCtrlKeyMgrDivType;
+
+/* Ownership states */
+typedef enum {
+    OWNERSHIP_ST_RAW,
+    OWNERSHIP_ST_LOCKED0,
+    OWNERSHIP_ST_RELEASED0,
+    OWNERSHIP_ST_LOCKED1,
+    OWNERSHIP_ST_RELEASED1,
+    OWNERSHIP_ST_LOCKED2,
+    OWNERSHIP_ST_RELEASED2,
+    OWNERSHIP_ST_LOCKED_3,
+    OWNERSHIP_ST_SCRAPPED,
+    OWNERSHIP_ST_COUNT,
+} OtLcCtrlOwnershipState;
+
+typedef enum {
+    LC_CTRL_TRANS_LC_STATE,
+    LC_CTRL_TRANS_LC_TCOUNT,
+    LC_CTRL_TRANS_OWNERSHIP,
+    LC_CTRL_TRANS_SOC_DBG,
+    LC_CTRL_TRANS_COUNT
+} OtLcCtrlTransition;
+
+enum OtLcCtrlTState {
+    LC_CTRL_TSTATE_FIRST, /* initial value */
+    LC_CTRL_TSTATE_LAST, /* terminal value */
+    LC_CTRL_TSTATE_COUNT,
+};
+
+typedef struct {
+    /* string of hexadecimal encoded bytes */
+    char *state[LC_CTRL_TSTATE_COUNT];
+} OtLcCtrlTransitionConfig;
+
+struct OtLcCtrlState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    MemoryRegion dmi_mmio;
+    QEMUBH *pwc_lc_bh;
+    QEMUBH *escalate_bh;
+    IbexIRQ alerts[NUM_ALERTS];
+    IbexIRQ broadcasts[OT_LC_BROADCAST_COUNT];
+    IbexIRQ pwc_lc_rsp;
+    IbexIRQ soc_dbg_tx;
+
+    uint32_t *regs; /* slots in xregs are not used in regs */
+    uint32_t xregs[EXCLUSIVE_SLOTS_COUNT][EXCLUSIVE_REGS_COUNT];
+    OtLcState lc_state;
+    uint32_t lc_tcount;
+    OtLcCtrlKeyMgrDivType km_div_type;
+    OtOTPTokenValue hash_token;
+    OtLcCtrlIf owner;
+    OtLcCtrlFsmState state;
+    OtLcCtrlFsmKmacState kmac_state;
+    OtLcCtrlStateValue *lc_states;
+    OtLcCtrlTransitionCountValue *lc_transitions;
+    OtLcCtrlOwnershipValue *ownerships;
+    OtLcCtrlSocDbgValue *soc_dbgs;
+    OtOTPTokenValue *hashed_tokens;
+    uint8_t km_divs[LC_DIV_COUNT][OT_LC_KEYMGR_DIV_BYTES];
+
+    uint32_t hashed_token_bm;
+    struct {
+        uint32_t value;
+        unsigned count;
+    } status_cache; /* special debug cache for status register */
+    bool ext_clock_en; /* request for external clock */
+    bool volatile_unlocked; /* set on successful volatile unlock */
+    bool force_raw; /* survivability mode */
+    uint8_t volatile_raw_unlock_bm; /* xslot-indexed bitmap */
+    uint8_t state_invalid_error_bm; /* error bitmap */
+    char *hexstr;
+
+    /* properties */
+    char *ot_id;
+    DeviceState *otp_ctrl;
+    OtKMACState *kmac;
+    char *raw_unlock_token_xstr;
+    char *km_div_xstrs[LC_DIV_COUNT];
+    OtLcCtrlTransitionConfig trans_cfg[LC_CTRL_TRANS_COUNT];
+    uint16_t silicon_creator_id;
+    uint16_t product_id;
+    uint8_t revision_id;
+    uint8_t kmac_app;
+    bool volatile_raw_unlock;
+    bool decode_soc_dbg; /* whether to handle SoCDbg state */
+};
+
+/* try to cope with the many ways to encode a transition matrix */
+typedef enum {
+    LC_TR_MODE_HISTORICAL, /* what prevailed in EarlGrey */
+    LC_TR_MODE_FIRST_FULL, /* first non-ZRO transition contains full first st */
+    LC_TR_MODE_FULL_CHANGE, /* no identifical words in transititions */
+} OtLcCtrlTransitionMode;
+
+typedef struct {
+    unsigned word_count; /* sequence size (count of 16-bit words) */
+    unsigned step_count; /* how many different steps/stages, incl. raw/blank */
+    OtLcCtrlTransitionMode mode; /* how transition matrix is "encoded" */
+    const char *name; /* helper name */
+} OtLcCtrlTransitionDesc;
+
+static_assert(sizeof(OtOTPTokenValue) == LC_TOKEN_WIDTH,
+              "Unexpected LC Token width");
+static_assert(OT_OTP_HWCFG_DEVICE_ID_BYTES == LC_DEV_ID_WIDTH,
+              "Unexpected LC Device ID width");
+static_assert(OT_OTP_HWCFG_MANUF_STATE_BYTES == LC_MANUF_STATE_WIDTH,
+              "Unexpected LC Manufacturing State width");
+
+#define KECCAK_STATE_BITS  1600u
+#define KECCAK_STATE_BYTES (KECCAK_STATE_BITS / 8u)
+
+static const OtKMACAppCfg OT_LC_CTRL_KMAC_CONFIG =
+    OT_KMAC_CONFIG(CSHAKE, 128u, "", "LC_CTRL");
+
+/* transition matrix */
+static const OtLcCtrlToken
+    LC_TRANS_TOKEN_MATRIX[LC_STATE_VALID_COUNT][LC_STATE_VALID_COUNT];
+
+/* NOLINTNEXTLINE*/
+#include "ot_lc_ctrl_matrix.c"
+
+#define LC_NAME_ENTRY(_st_) [_st_] = stringify(_st_)
+
+/* clang-format off */
+static const char *LC_FSM_STATE_NAMES[] = {
+    LC_NAME_ENTRY(ST_RESET),
+    LC_NAME_ENTRY(ST_IDLE),
+    LC_NAME_ENTRY(ST_CLK_MUX),
+    LC_NAME_ENTRY(ST_CNT_INCR),
+    LC_NAME_ENTRY(ST_CNT_PROG),
+    LC_NAME_ENTRY(ST_TRANS_CHECK),
+    LC_NAME_ENTRY(ST_TOKEN_HASH),
+    LC_NAME_ENTRY(ST_FLASH_RMA),
+    LC_NAME_ENTRY(ST_TOKEN_CHECK0),
+    LC_NAME_ENTRY(ST_TOKEN_CHECK1),
+    LC_NAME_ENTRY(ST_TRANS_PROG),
+    LC_NAME_ENTRY(ST_POST_TRANS),
+    LC_NAME_ENTRY(ST_SCRAP),
+    LC_NAME_ENTRY(ST_ESCALATE),
+    LC_NAME_ENTRY(ST_INVALID),
+};
+
+static const char *LC_TOKEN_NAMES[] = {
+    LC_NAME_ENTRY(LC_TK_INVALID),
+    LC_NAME_ENTRY(LC_TK_ZERO),
+    LC_NAME_ENTRY(LC_TK_RAW_UNLOCK),
+    LC_NAME_ENTRY(LC_TK_TEST_UNLOCK),
+    LC_NAME_ENTRY(LC_TK_TEST_EXIT),
+    LC_NAME_ENTRY(LC_TK_RMA),
+};
+
+static const char *LC_STATE_NAMES[] = {
+    LC_NAME_ENTRY(LC_STATE_RAW),
+    LC_NAME_ENTRY(LC_STATE_TESTUNLOCKED0),
+    LC_NAME_ENTRY(LC_STATE_TESTLOCKED0),
+    LC_NAME_ENTRY(LC_STATE_TESTUNLOCKED1),
+    LC_NAME_ENTRY(LC_STATE_TESTLOCKED1),
+    LC_NAME_ENTRY(LC_STATE_TESTUNLOCKED2),
+    LC_NAME_ENTRY(LC_STATE_TESTLOCKED2),
+    LC_NAME_ENTRY(LC_STATE_TESTUNLOCKED3),
+    LC_NAME_ENTRY(LC_STATE_TESTLOCKED3),
+    LC_NAME_ENTRY(LC_STATE_TESTUNLOCKED4),
+    LC_NAME_ENTRY(LC_STATE_TESTLOCKED4),
+    LC_NAME_ENTRY(LC_STATE_TESTUNLOCKED5),
+    LC_NAME_ENTRY(LC_STATE_TESTLOCKED5),
+    LC_NAME_ENTRY(LC_STATE_TESTUNLOCKED6),
+    LC_NAME_ENTRY(LC_STATE_TESTLOCKED6),
+    LC_NAME_ENTRY(LC_STATE_TESTUNLOCKED7),
+    LC_NAME_ENTRY(LC_STATE_DEV),
+    LC_NAME_ENTRY(LC_STATE_PROD),
+    LC_NAME_ENTRY(LC_STATE_PRODEND),
+    LC_NAME_ENTRY(LC_STATE_RMA),
+    LC_NAME_ENTRY(LC_STATE_SCRAP),
+    LC_NAME_ENTRY(LC_STATE_POST_TRANSITION),
+    LC_NAME_ENTRY(LC_STATE_ESCALATE),
+    LC_NAME_ENTRY(LC_STATE_INVALID),
+};
+
+static const char *LC_BROADCAST_NAMES[] = {
+    LC_NAME_ENTRY(OT_LC_RAW_TEST_RMA),
+    LC_NAME_ENTRY(OT_LC_DFT_EN),
+    LC_NAME_ENTRY(OT_LC_NVM_DEBUG_EN),
+    LC_NAME_ENTRY(OT_LC_HW_DEBUG_EN),
+    LC_NAME_ENTRY(OT_LC_CPU_EN),
+    LC_NAME_ENTRY(OT_LC_KEYMGR_EN),
+    LC_NAME_ENTRY(OT_LC_ESCALATE_EN),
+    LC_NAME_ENTRY(OT_LC_CHECK_BYP_EN),
+    LC_NAME_ENTRY(OT_LC_CREATOR_SEED_SW_RW_EN),
+    LC_NAME_ENTRY(OT_LC_OWNER_SEED_SW_RW_EN),
+    LC_NAME_ENTRY(OT_LC_ISO_PART_SW_RD_EN),
+    LC_NAME_ENTRY(OT_LC_ISO_PART_SW_WR_EN),
+    LC_NAME_ENTRY(OT_LC_SEED_HW_RD_EN),
+};
+
+static const char *TSTATE_NAMES[LC_CTRL_TSTATE_COUNT] = {
+    [LC_CTRL_TSTATE_FIRST] = "first",
+    [LC_CTRL_TSTATE_LAST] = "last",
+};
+
+static const OtLcCtrlTransitionDesc TRANSITION_DESC[LC_CTRL_TRANS_COUNT] = {
+    [LC_CTRL_TRANS_LC_STATE] = {
+        .word_count = LC_STATE_WORDS,
+        .step_count = NUM_LC_STATE,
+        .mode = LC_TR_MODE_HISTORICAL,
+        .name = "lc_state",
+    },
+    [LC_CTRL_TRANS_LC_TCOUNT] = {
+        .word_count = LC_TRANSITION_COUNT_WORDS,
+        .step_count = NUM_LC_TRANSITION_COUNT,
+        .mode = LC_TR_MODE_HISTORICAL,
+        .name = "lc_tcount",
+    },
+    [LC_CTRL_TRANS_OWNERSHIP] = {
+        .word_count = OWNERSHIP_WORDS,
+        .step_count = NUM_OWNERSHIP,
+        .mode = LC_TR_MODE_FIRST_FULL,
+        .name = "ownership",
+    },
+    [LC_CTRL_TRANS_SOC_DBG] = {
+        .word_count = SOC_DBG_WORDS,
+        .step_count = NUM_SOC_DBG,
+        .mode = LC_TR_MODE_FULL_CHANGE,
+        .name = "soc_dbg",
+    },
+};
+
+/* clang-format on */
+
+#undef LC_NAME_ENTRY
+
+#define LC_FSM_STATE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(LC_FSM_STATE_NAMES) ? \
+         LC_FSM_STATE_NAMES[(_st_)] : \
+         "?")
+
+#define LC_FSM_CHANGE_STATE(_s_, _st_) \
+    do { \
+        if (ot_lc_ctrl_change_state_line(_s_, _st_, __LINE__)) { \
+            ot_lc_ctrl_update_broadcast(_s_); \
+        } \
+    } while (0)
+
+#define LC_TOKEN_NAME(_tk_) \
+    (((unsigned)(_tk_)) < ARRAY_SIZE(LC_TOKEN_NAMES) ? \
+         LC_TOKEN_NAMES[(_tk_)] : \
+         "?")
+
+#define LC_STATE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(LC_STATE_NAMES) ? \
+         LC_STATE_NAMES[(_st_)] : \
+         "?")
+
+#define LC_BCAST_BIT(_sig_) (1u << (OT_LC_##_sig_))
+
+#define LC_BCAST_NAME(_bit_) \
+    (((unsigned)(_bit_)) < ARRAY_SIZE(LC_BROADCAST_NAMES) ? \
+         LC_BROADCAST_NAMES[(_bit_)] : \
+         "?")
+
+#define TSTATE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(TSTATE_NAMES) ? TSTATE_NAMES[(_st_)] : "?")
+
+#define LC_STATE_A (1u << 6u)
+#define LC_STATE_B (1u << 7u)
+
+#define ZRO 0
+#undef A
+#undef B
+#define A(_n_) ((LC_STATE_A) | (_n_))
+#define B(_n_) ((LC_STATE_B) | (_n_))
+
+/* clang-format off */
+static const uint8_t
+LC_STATES_TPL[NUM_LC_STATE][LC_STATE_WORDS] = {
+    [LC_STATE_RAW] = {
+        ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,
+        ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,   ZRO,
+    },
+    [LC_STATE_TESTUNLOCKED0] = {
+        B(0),  A(1),  A(2),  A(3),  A(4),  A(5),  A(6),  A(7),  A(8),  A(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTLOCKED0] = {
+        B(0),  B(1),  A(2),  A(3),  A(4),  A(5),  A(6),  A(7),  A(8),  A(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTUNLOCKED1] = {
+        B(0),  B(1),  B(2),  A(3),  A(4),  A(5),  A(6),  A(7),  A(8),  A(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTLOCKED1] = {
+        B(0),  B(1),  B(2),  B(3),  A(4),  A(5),  A(6),  A(7),  A(8),  A(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTUNLOCKED2] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  A(5),  A(6),  A(7),  A(8),  A(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTLOCKED2] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  A(6),  A(7),  A(8),  A(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTUNLOCKED3] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  A(7),  A(8),  A(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTLOCKED3] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  A(8),  A(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTUNLOCKED4] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  A(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTLOCKED4] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        A(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTUNLOCKED5] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), A(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTLOCKED5] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), B(11), A(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTUNLOCKED6] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), B(11), B(12), A(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTLOCKED6] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), B(11), B(12), B(13), A(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_TESTUNLOCKED7] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), B(11), B(12), B(13), B(14), A(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_DEV] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), B(11), B(12), B(13), B(14), B(15), A(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_PROD] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), B(11), B(12), B(13), B(14), A(15), B(16), A(17), A(18), A(19),
+    },
+    [LC_STATE_PRODEND] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), B(11), B(12), B(13), B(14), A(15), A(16), B(17), A(18), A(19),
+    },
+    [LC_STATE_RMA] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), B(11), B(12), B(13), B(14), B(15), B(16), A(17), B(18), B(19),
+    },
+    [LC_STATE_SCRAP] = {
+        B(0),  B(1),  B(2),  B(3),  B(4),  B(5),  B(6),  B(7),  B(8),  B(9),
+        B(10), B(11), B(12), B(13), B(14), B(15), B(16), B(17), B(18), B(19),
+    },
+};
+/* clang-format on */
+
+#define LC_STATE_A_WORD(_x_)    ((bool)((_x_) & LC_STATE_A))
+#define LC_STATE_B_WORD(_x_)    ((bool)((_x_) & LC_STATE_B))
+#define LC_STATE_ZERO_WORD(_x_) ((_x_) == 0u)
+#define LC_STATE_WORD(_x_)      ((_x_) & ~(LC_STATE_A | LC_STATE_B))
+#undef ZRO
+#undef A
+#undef B
+
+#ifdef OT_LC_CTRL_DEBUG
+#define OT_LC_CTRL_HEXSTR_SIZE 256u
+#define TRACE_LC_CTRL(msg, ...) \
+    qemu_log("%s: %s: " msg "\n", __func__, s->ot_id, ##__VA_ARGS__);
+#define ot_lc_ctrl_hexdump(_s_, _b_, _l_) \
+    ot_common_lhexdump((const uint8_t *)_b_, _l_, false, (_s_)->hexstr, \
+                       OT_LC_CTRL_HEXSTR_SIZE)
+#else
+#define TRACE_LC_CTRL(msg, ...)
+#define ot_lc_ctrl_hexdump(_s_, _b_, _l_)
+#endif
+
+static void ot_lc_ctrl_resume_transition(OtLcCtrlState *s);
+
+static bool
+ot_lc_ctrl_change_state_line(OtLcCtrlState *s, OtLcCtrlFsmState state, int line)
+{
+    trace_ot_lc_ctrl_change_state(s->ot_id, line, LC_FSM_STATE_NAME(s->state),
+                                  s->state, LC_FSM_STATE_NAME(state), state);
+
+    bool change = s->state != state;
+
+    s->state = state;
+
+    return change || state == ST_IDLE;
+}
+
+static void ot_lc_ctrl_update_alerts(OtLcCtrlState *s)
+{
+    uint32_t level = s->regs[R_ALERT_TEST];
+
+    for (unsigned ix = 0; ix < NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_lc_ctrl_update_broadcast(OtLcCtrlState *s)
+{
+    uint32_t sigbm = 0;
+    OtLcCtrlKeyMgrDivType div_type = LC_DIV_INVALID;
+
+    switch (s->state) {
+    case ST_RESET:
+        break;
+    case ST_IDLE:
+    case ST_CLK_MUX:
+    case ST_CNT_INCR:
+    case ST_CNT_PROG:
+    case ST_TRANS_CHECK:
+    case ST_TOKEN_HASH:
+    case ST_FLASH_RMA:
+    case ST_TOKEN_CHECK0:
+    case ST_TOKEN_CHECK1:
+    case ST_TRANS_PROG:
+        switch (s->lc_state) {
+        case LC_STATE_RAW:
+        case LC_STATE_TESTLOCKED0:
+        case LC_STATE_TESTLOCKED1:
+        case LC_STATE_TESTLOCKED2:
+        case LC_STATE_TESTLOCKED3:
+        case LC_STATE_TESTLOCKED4:
+        case LC_STATE_TESTLOCKED5:
+        case LC_STATE_TESTLOCKED6:
+            sigbm = LC_BCAST_BIT(RAW_TEST_RMA);
+            break;
+        case LC_STATE_TESTUNLOCKED0:
+        case LC_STATE_TESTUNLOCKED1:
+        case LC_STATE_TESTUNLOCKED2:
+        case LC_STATE_TESTUNLOCKED3:
+        case LC_STATE_TESTUNLOCKED4:
+        case LC_STATE_TESTUNLOCKED5:
+        case LC_STATE_TESTUNLOCKED6:
+            sigbm = LC_BCAST_BIT(RAW_TEST_RMA) | LC_BCAST_BIT(DFT_EN) |
+                    LC_BCAST_BIT(NVM_DEBUG_EN) | LC_BCAST_BIT(HW_DEBUG_EN) |
+                    LC_BCAST_BIT(CPU_EN) | LC_BCAST_BIT(ISO_PART_SW_WR_EN);
+            div_type = LC_DIV_TEST_UNLOCKED;
+            break;
+        case LC_STATE_TESTUNLOCKED7:
+            sigbm = LC_BCAST_BIT(RAW_TEST_RMA) | LC_BCAST_BIT(DFT_EN) |
+                    LC_BCAST_BIT(HW_DEBUG_EN) | LC_BCAST_BIT(CPU_EN) |
+                    LC_BCAST_BIT(ISO_PART_SW_WR_EN);
+            div_type = LC_DIV_TEST_UNLOCKED;
+            break;
+        case LC_STATE_PROD:
+        case LC_STATE_PRODEND:
+            sigbm = LC_BCAST_BIT(CPU_EN) | LC_BCAST_BIT(KEYMGR_EN) |
+                    LC_BCAST_BIT(OWNER_SEED_SW_RW_EN) |
+                    LC_BCAST_BIT(ISO_PART_SW_WR_EN) |
+                    LC_BCAST_BIT(ISO_PART_SW_RD_EN);
+            /*
+             * "Only allow provisioning if the device has not yet been
+             * personalized."
+             */
+            if (s->regs[R_LC_ID_STATE] == LC_ID_STATE_BLANK) {
+                sigbm |= LC_BCAST_BIT(CREATOR_SEED_SW_RW_EN);
+            }
+            /*
+             * "Only allow hardware to consume the seeds once personalized."
+             */
+            if (s->regs[R_LC_ID_STATE] == LC_ID_STATE_PERSONALIZED) {
+                sigbm |= LC_BCAST_BIT(SEED_HW_RD_EN);
+            }
+            div_type = LC_DIV_PROD;
+            break;
+        case LC_STATE_DEV:
+            sigbm =
+                LC_BCAST_BIT(HW_DEBUG_EN) | LC_BCAST_BIT(CPU_EN) |
+                LC_BCAST_BIT(KEYMGR_EN) | LC_BCAST_BIT(OWNER_SEED_SW_RW_EN) |
+                LC_BCAST_BIT(ISO_PART_SW_WR_EN);
+            if (s->regs[R_LC_ID_STATE] == LC_ID_STATE_BLANK) {
+                sigbm |= LC_BCAST_BIT(CREATOR_SEED_SW_RW_EN);
+            }
+            if (s->regs[R_LC_ID_STATE] == LC_ID_STATE_PERSONALIZED) {
+                sigbm |= LC_BCAST_BIT(SEED_HW_RD_EN);
+            }
+            div_type = LC_DIV_DEV;
+            break;
+        case LC_STATE_RMA:
+            /* note: RMA signal not available on EG 1.0.0 */
+            sigbm = LC_BCAST_BIT(RAW_TEST_RMA) | LC_BCAST_BIT(DFT_EN) |
+                    LC_BCAST_BIT(NVM_DEBUG_EN) | LC_BCAST_BIT(HW_DEBUG_EN) |
+                    LC_BCAST_BIT(CPU_EN) | LC_BCAST_BIT(KEYMGR_EN) |
+                    LC_BCAST_BIT(CHECK_BYP_EN) |
+                    LC_BCAST_BIT(CREATOR_SEED_SW_RW_EN) |
+                    LC_BCAST_BIT(OWNER_SEED_SW_RW_EN) |
+                    LC_BCAST_BIT(ISO_PART_SW_RD_EN) |
+                    LC_BCAST_BIT(ISO_PART_SW_WR_EN) |
+                    LC_BCAST_BIT(SEED_HW_RD_EN) | LC_BCAST_BIT(RMA);
+            div_type = LC_DIV_RMA;
+            break;
+        case LC_STATE_SCRAP:
+        default:
+            trace_ot_lc_ctrl_escalate(s->ot_id, LC_FSM_STATE_NAME(s->state),
+                                      LC_STATE_NAME(s->lc_state));
+            sigbm = LC_BCAST_BIT(ESCALATE_EN);
+            break;
+        }
+        break;
+    case ST_POST_TRANS:
+        break;
+    case ST_SCRAP:
+    case ST_ESCALATE:
+    case ST_INVALID:
+    default:
+        trace_ot_lc_ctrl_escalate(s->ot_id, LC_FSM_STATE_NAME(s->state),
+                                  LC_STATE_NAME(s->lc_state));
+        sigbm = LC_BCAST_BIT(ESCALATE_EN);
+        break;
+    }
+
+    s->km_div_type = div_type;
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->broadcasts); ix++) {
+        bool level = (bool)(sigbm & (1u << ix));
+        bool curlvl = (bool)ibex_irq_get_level(&s->broadcasts[ix]);
+        if (level != curlvl) {
+            trace_ot_lc_ctrl_update_broadcast(s->ot_id,
+                                              LC_FSM_STATE_NAME(s->state),
+                                              LC_BCAST_NAME(ix), curlvl, level);
+        }
+        ibex_irq_set(&s->broadcasts[ix], (int)level);
+    }
+}
+
+static bool ot_lc_ctrl_match_token(const OtLcCtrlState *s, OtLcCtrlToken tok)
+{
+    g_assert(((unsigned)tok) < LC_TK_COUNT);
+
+    bool match = ((bool)(s->hashed_token_bm & (1u << tok))) &&
+                 (s->hash_token.lo == s->hashed_tokens[tok].lo) &&
+                 (s->hash_token.hi == s->hashed_tokens[tok].hi);
+
+    if (!match) {
+        trace_ot_lc_ctrl_mismatch_token(s->ot_id,
+                                        s->hashed_token_bm & (1u << tok) ?
+                                            "hashed" :
+                                            "zero",
+                                        LC_TOKEN_NAME(tok), tok,
+                                        s->hash_token.hi, s->hash_token.lo,
+                                        s->hashed_tokens[tok].hi,
+                                        s->hashed_tokens[tok].lo);
+    }
+
+    return match;
+}
+
+static bool
+ot_lc_ctrl_is_hw_mutex_owner(const OtLcCtrlState *s, OtLcCtrlIf owner)
+{
+    return s->owner == owner;
+}
+
+static bool ot_lc_ctrl_lock_hw_mutex(OtLcCtrlState *s, OtLcCtrlIf owner)
+{
+    if (s->owner != LC_IF_NONE) {
+        return ot_lc_ctrl_is_hw_mutex_owner(s, owner);
+    }
+
+    s->owner = owner;
+
+    return true;
+}
+
+static void ot_lc_ctrl_release_hw_mutex(OtLcCtrlState *s)
+{
+    s->owner = LC_IF_NONE;
+}
+
+static bool
+ot_lc_ctrl_is_transition_en(const OtLcCtrlState *s, OtLcCtrlIf owner)
+{
+    return ot_lc_ctrl_is_hw_mutex_owner(s, owner) && s->state == ST_IDLE;
+}
+
+static bool ot_lc_ctrl_is_known_state(uint32_t state)
+{
+    switch (state) {
+    case LC_ENC_STATE_RAW:
+    case LC_ENC_STATE_TESTUNLOCKED0:
+    case LC_ENC_STATE_TESTLOCKED0:
+    case LC_ENC_STATE_TESTUNLOCKED1:
+    case LC_ENC_STATE_TESTLOCKED1:
+    case LC_ENC_STATE_TESTUNLOCKED2:
+    case LC_ENC_STATE_TESTLOCKED2:
+    case LC_ENC_STATE_TESTUNLOCKED3:
+    case LC_ENC_STATE_TESTLOCKED3:
+    case LC_ENC_STATE_TESTUNLOCKED4:
+    case LC_ENC_STATE_TESTLOCKED4:
+    case LC_ENC_STATE_TESTUNLOCKED5:
+    case LC_ENC_STATE_TESTLOCKED5:
+    case LC_ENC_STATE_TESTUNLOCKED6:
+    case LC_ENC_STATE_TESTLOCKED6:
+    case LC_ENC_STATE_TESTUNLOCKED7:
+    case LC_ENC_STATE_DEV:
+    case LC_ENC_STATE_PROD:
+    case LC_ENC_STATE_PRODEND:
+    case LC_ENC_STATE_RMA:
+    case LC_ENC_STATE_SCRAP:
+        return true;
+    default:
+        return false;
+    }
+}
+
+static bool ot_lc_ctrl_is_vendor_test_state(uint32_t state)
+{
+    switch (state) {
+    case LC_ENC_STATE_RAW:
+    case LC_ENC_STATE_TESTUNLOCKED0:
+    case LC_ENC_STATE_TESTLOCKED0:
+    case LC_ENC_STATE_TESTUNLOCKED1:
+    case LC_ENC_STATE_TESTLOCKED1:
+    case LC_ENC_STATE_TESTUNLOCKED2:
+    case LC_ENC_STATE_TESTLOCKED2:
+    case LC_ENC_STATE_TESTUNLOCKED3:
+    case LC_ENC_STATE_TESTLOCKED3:
+    case LC_ENC_STATE_TESTUNLOCKED4:
+    case LC_ENC_STATE_TESTLOCKED4:
+    case LC_ENC_STATE_TESTUNLOCKED5:
+    case LC_ENC_STATE_TESTLOCKED5:
+    case LC_ENC_STATE_TESTUNLOCKED6:
+    case LC_ENC_STATE_TESTLOCKED6:
+    case LC_ENC_STATE_TESTUNLOCKED7:
+    case LC_ENC_STATE_RMA:
+        return true;
+    default:
+        return false;
+    }
+}
+
+static OtLcState ot_lc_ctrl_convert_code_to_state(uint32_t enc_state)
+{
+    OtLcState state;
+
+    switch (enc_state) {
+    case LC_ENC_STATE_RAW:
+        state = LC_STATE_RAW;
+        break;
+    case LC_ENC_STATE_TESTUNLOCKED0:
+        state = LC_STATE_TESTUNLOCKED0;
+        break;
+    case LC_ENC_STATE_TESTLOCKED0:
+        state = LC_STATE_TESTLOCKED0;
+        break;
+    case LC_ENC_STATE_TESTUNLOCKED1:
+        state = LC_STATE_TESTUNLOCKED1;
+        break;
+    case LC_ENC_STATE_TESTLOCKED1:
+        state = LC_STATE_TESTLOCKED1;
+        break;
+    case LC_ENC_STATE_TESTUNLOCKED2:
+        state = LC_STATE_TESTUNLOCKED2;
+        break;
+    case LC_ENC_STATE_TESTLOCKED2:
+        state = LC_STATE_TESTLOCKED2;
+        break;
+    case LC_ENC_STATE_TESTUNLOCKED3:
+        state = LC_STATE_TESTUNLOCKED3;
+        break;
+    case LC_ENC_STATE_TESTLOCKED3:
+        state = LC_STATE_TESTLOCKED3;
+        break;
+    case LC_ENC_STATE_TESTUNLOCKED4:
+        state = LC_STATE_TESTUNLOCKED4;
+        break;
+    case LC_ENC_STATE_TESTLOCKED4:
+        state = LC_STATE_TESTLOCKED4;
+        break;
+    case LC_ENC_STATE_TESTUNLOCKED5:
+        state = LC_STATE_TESTUNLOCKED5;
+        break;
+    case LC_ENC_STATE_TESTLOCKED5:
+        state = LC_STATE_TESTLOCKED5;
+        break;
+    case LC_ENC_STATE_TESTUNLOCKED6:
+        state = LC_STATE_TESTUNLOCKED6;
+        break;
+    case LC_ENC_STATE_TESTLOCKED6:
+        state = LC_STATE_TESTLOCKED6;
+        break;
+    case LC_ENC_STATE_TESTUNLOCKED7:
+        state = LC_STATE_TESTUNLOCKED7;
+        break;
+    case LC_ENC_STATE_DEV:
+        state = LC_STATE_DEV;
+        break;
+    case LC_ENC_STATE_PROD:
+        state = LC_STATE_PROD;
+        break;
+    case LC_ENC_STATE_PRODEND:
+        state = LC_STATE_PRODEND;
+        break;
+    case LC_ENC_STATE_RMA:
+        state = LC_STATE_RMA;
+        break;
+    case LC_ENC_STATE_SCRAP:
+        state = LC_STATE_SCRAP;
+        break;
+    default:
+        /* code validity should have been verified first */
+        g_assert_not_reached();
+    }
+
+    return state;
+}
+
+static OtLcState ot_lc_ctrl_safe_convert_code_to_state(uint32_t enc_state)
+{
+    if (!ot_lc_ctrl_is_known_state(enc_state)) {
+        return LC_STATE_INVALID;
+    }
+
+    return ot_lc_ctrl_convert_code_to_state(enc_state);
+}
+
+static uint32_t ot_lc_ctrl_get_target_state(const OtLcCtrlState *s)
+{
+    unsigned sreq = LC_XSLOT(s->owner);
+
+    return s->xregs[sreq][R_TRANSITION_TARGET - R_FIRST_EXCLUSIVE_REG];
+}
+
+static void ot_lc_ctrl_load_hashed_token(OtLcCtrlState *s)
+{
+    g_assert(LC_XSLOT(s->owner) < EXCLUSIVE_SLOTS_COUNT);
+
+    const uint32_t *xregs = s->xregs[LC_XSLOT(s->owner)];
+
+    s->hash_token.lo =
+        (uint64_t)xregs[XREGS_OFFSET(R_TRANSITION_TOKEN_0)] |
+        (((uint64_t)xregs[XREGS_OFFSET(R_TRANSITION_TOKEN_1)]) << 32u);
+    s->hash_token.hi =
+        (uint64_t)xregs[XREGS_OFFSET(R_TRANSITION_TOKEN_2)] |
+        (((uint64_t)xregs[XREGS_OFFSET(R_TRANSITION_TOKEN_3)]) << 32u);
+}
+
+static void ot_lc_ctrl_kmac_request(OtLcCtrlState *s)
+{
+    g_assert(LC_XSLOT(s->owner) < EXCLUSIVE_SLOTS_COUNT);
+
+    const uint32_t *xregs = s->xregs[LC_XSLOT(s->owner)];
+    const uint32_t *token =
+        &xregs[(s->kmac_state == ST_KMAC_SECOND ?
+                    XREGS_OFFSET(R_TRANSITION_TOKEN_2) :
+                    XREGS_OFFSET(R_TRANSITION_TOKEN_0))];
+
+    OtKMACAppReq req = {
+        .msg_len = 8u,
+        .last = s->kmac_state == ST_KMAC_SECOND,
+    };
+    stl_le_p(&req.msg_data[0], token[0]);
+    stl_le_p(&req.msg_data[sizeof(uint32_t)], token[1]);
+
+    TRACE_LC_CTRL("KMAC input: %s",
+                  ot_lc_ctrl_hexdump(s, &req.msg_data[0], 8u));
+
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    kc->app_request(s->kmac, s->kmac_app, &req);
+}
+
+static void ot_lc_ctrl_kmac_handle_resp(void *opaque, const OtKMACAppRsp *rsp)
+{
+    OtLcCtrlState *s = opaque;
+
+    if (s->kmac_state == ST_KMAC_FIRST) {
+        g_assert(!rsp->done);
+        s->kmac_state = ST_KMAC_SECOND;
+        ot_lc_ctrl_kmac_request(s);
+        s->kmac_state = ST_KMAC_WAIT;
+        return;
+    }
+
+    g_assert(rsp->done);
+    g_assert(s->kmac_state == ST_KMAC_WAIT);
+
+    uint64_t dig0;
+    uint64_t dig1;
+    dig0 = ldq_le_p(&rsp->digest_share0[0]);
+    dig1 = ldq_le_p(&rsp->digest_share1[0]);
+    s->hash_token.lo = dig0 ^ dig1;
+    dig0 = ldq_le_p(&rsp->digest_share0[sizeof(uint64_t)]);
+    dig1 = ldq_le_p(&rsp->digest_share1[sizeof(uint64_t)]);
+    s->hash_token.hi = dig0 ^ dig1;
+
+    TRACE_LC_CTRL("MKAC output: %s",
+                  ot_lc_ctrl_hexdump(s, &s->hash_token.lo, 16u));
+
+    ot_lc_ctrl_resume_transition(s);
+}
+
+static uint32_t ot_lc_ctrl_load_lc_info(OtLcCtrlState *s)
+{
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+    OtLcCtrlStateValue lc_state;
+    OtLcCtrlTransitionCountValue lc_tcount;
+    uint8_t lc_valid;
+    uint8_t secret_valid;
+    const OtOTPTokens *tokens = NULL;
+    oc->get_lc_info(oi, lc_tcount, lc_state, &lc_valid, &secret_valid, &tokens);
+
+    if (s->force_raw) {
+        trace_ot_lc_ctrl_load_lc_info_force_raw(s->ot_id);
+        memcpy(lc_state, s->lc_states[0], sizeof(OtLcCtrlStateValue));
+        memcpy(lc_tcount, s->lc_transitions[0],
+               sizeof(OtLcCtrlTransitionCountValue));
+        lc_valid = true;
+    }
+
+    switch (secret_valid) {
+    case OT_MULTIBITBOOL_LC4_FALSE:
+        /* blank */
+        s->regs[R_LC_ID_STATE] = LC_ID_STATE_BLANK;
+        break;
+    case OT_MULTIBITBOOL_LC4_TRUE:
+        /* personalized */
+        s->regs[R_LC_ID_STATE] = LC_ID_STATE_PERSONALIZED;
+        break;
+    default:
+        /* invalid */
+        s->regs[R_LC_ID_STATE] = LC_ID_STATE_INVALID;
+        break;
+    }
+
+    uint32_t enc_lcstate = LC_ENCODE_STATE(LC_STATE_INVALID);
+    s->lc_tcount = NUM_LC_TRANSITION_COUNT;
+
+    for (unsigned ix = 0; ix < NUM_LC_TRANSITION_COUNT; ix++) {
+        if (!memcmp(lc_tcount, s->lc_transitions[ix],
+                    sizeof(OtLcCtrlTransitionCountValue))) {
+            s->lc_tcount = ix;
+            break;
+        }
+    }
+
+    for (unsigned ix = 0; ix < LC_STATE_VALID_COUNT; ix++) {
+        if (!memcmp(lc_state, s->lc_states[ix], sizeof(OtLcCtrlStateValue))) {
+            enc_lcstate = LC_ENCODE_STATE(ix);
+            break;
+        }
+    }
+
+    trace_ot_lc_ctrl_initial_lifecycle(s->ot_id, s->lc_tcount, enc_lcstate,
+                                       LC_STATE_BITS(enc_lcstate));
+
+    g_assert(tokens);
+
+    uint32_t valid_bm = tokens->valid_bm;
+    for (unsigned otix = 0; otix < OT_OTP_TOKEN_COUNT; otix++) {
+        /* beware: LC controller and OTP controller do not use same indices */
+        unsigned ltix = otix + LC_TK_TEST_UNLOCK - OT_OTP_TOKEN_TEST_UNLOCK;
+        /* 'valid' is OT terminology, should be considered as 'defined' */
+        bool valid = (bool)(valid_bm & (1u << otix));
+        if (valid) {
+            s->hashed_tokens[ltix] = tokens->values[otix];
+            s->hashed_token_bm |= 1u << ltix;
+        } else {
+            s->hashed_tokens[ltix] = (OtOTPTokenValue){ 0, 0 };
+            s->hashed_token_bm &= ~(1u << ltix);
+        }
+        trace_ot_lc_ctrl_load_otp_token(s->ot_id, LC_TOKEN_NAME(ltix), ltix,
+                                        valid ? "" : "in",
+                                        s->hashed_tokens[ltix].hi,
+                                        s->hashed_tokens[ltix].lo);
+    }
+
+    return lc_valid == OT_MULTIBITBOOL_LC4_TRUE ? enc_lcstate : UINT32_MAX;
+}
+
+static void ot_lc_ctrl_load_otp_hw_cfg(OtLcCtrlState *s)
+{
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+    const OtOTPHWCfg *hw_cfg = oc->get_hw_cfg(oi);
+
+    static_assert(sizeof(hw_cfg->device_id) == LC_DEV_ID_WIDTH,
+                  "HW_CFG Device ID size does not match size in registers");
+    memcpy(&s->regs[R_DEVICE_ID_0], &hw_cfg->device_id[0], LC_DEV_ID_WIDTH);
+
+    static_assert(sizeof(hw_cfg->manuf_state) == LC_MANUF_STATE_WIDTH,
+                  "HW_CFG Manuf State size does not match size in registers");
+    memcpy(&s->regs[R_MANUF_STATE_0], &hw_cfg->manuf_state[0],
+           LC_MANUF_STATE_WIDTH);
+
+    if (!s->decode_soc_dbg) {
+        return;
+    }
+
+    /* default to lowest capabilities */
+    int soc_dbg_ix = OT_LC_SOC_DBG_STATE_COUNT - 1u;
+
+    TRACE_LC_CTRL("soc_dbg_state: %s",
+                  ot_lc_ctrl_hexdump(s, hw_cfg->soc_dbg_state,
+                                     sizeof(OtLcCtrlSocDbgValue)));
+
+    for (unsigned six = 0; six < OT_LC_SOC_DBG_STATE_COUNT; six++) {
+        bool match = !memcmp(hw_cfg->soc_dbg_state, s->soc_dbgs[six],
+                             sizeof(OtLcCtrlSocDbgValue));
+        TRACE_LC_CTRL("soc_dbg ref[%u]: %s, match: %u", six,
+                      ot_lc_ctrl_hexdump(s, s->soc_dbgs[six],
+                                         sizeof(OtLcCtrlSocDbgValue)),
+                      match);
+        if (match) {
+            soc_dbg_ix = (int)six;
+            break;
+        }
+    }
+
+    ibex_irq_set(&s->soc_dbg_tx, soc_dbg_ix);
+}
+
+static void ot_lc_ctrl_handle_otp_ack(void *opaque, bool ack)
+{
+    OtLcCtrlState *s = opaque;
+
+    switch (s->state) {
+    case ST_IDLE:
+        trace_ot_lc_ctrl_info(s->ot_id, "Ignore OTP completion in IDLE");
+        break;
+    case ST_CNT_PROG:
+        LC_FSM_CHANGE_STATE(s, ST_TRANS_CHECK);
+        /*
+         * Notes:
+         *  - FLASH RMA is not implemented (not available on Darjeeling)
+         *  - Perform a unique Token Check (vs. 3 successive ones on real HW)
+         */
+        trace_ot_lc_ctrl_info(s->ot_id, "Request KMAC hashing");
+        g_assert(s->kmac_state == ST_KMAC_IDLE);
+        s->kmac_state = ST_KMAC_FIRST;
+        LC_FSM_CHANGE_STATE(s, ST_TOKEN_HASH);
+        ot_lc_ctrl_kmac_request(s);
+        break;
+    case ST_TRANS_PROG:
+        if (ack) {
+            trace_ot_lc_ctrl_info(s->ot_id, "Succesful transition update");
+            s->regs[R_STATUS] |= R_STATUS_TRANSITION_SUCCESSFUL_MASK;
+        } else {
+            trace_ot_lc_ctrl_info(s->ot_id, "Failed to program transition");
+            s->regs[R_STATUS] |= R_STATUS_OTP_ERROR_MASK;
+        }
+        LC_FSM_CHANGE_STATE(s, ST_POST_TRANS);
+        s->lc_state = LC_STATE_POST_TRANSITION;
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+}
+
+static void ot_lc_ctrl_program_otp(OtLcCtrlState *s, unsigned lc_tcount,
+                                   OtLcState lc_state)
+{
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+
+    if (!oc->program_req) {
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: %s: OTP implementation does not support programming",
+                      __func__, s->ot_id);
+        s->regs[R_STATUS] |= R_STATUS_OTP_ERROR_MASK;
+        LC_FSM_CHANGE_STATE(s, ST_POST_TRANS);
+        s->lc_state = LC_STATE_POST_TRANSITION;
+        return;
+    }
+
+    unsigned stix = MIN((unsigned)lc_state, NUM_LC_STATE);
+    unsigned tcix = MIN(lc_tcount, NUM_LC_TRANSITION_COUNT);
+    const uint16_t *transition_val = s->lc_transitions[tcix];
+    const uint16_t *state_val = s->lc_states[stix];
+
+    if (!oc->program_req(oi, transition_val, state_val,
+                         &ot_lc_ctrl_handle_otp_ack, s)) {
+        trace_ot_lc_ctrl_error(s->ot_id, "OTP program request rejected");
+        s->regs[R_STATUS] |= R_STATUS_STATE_ERROR_MASK;
+        LC_FSM_CHANGE_STATE(s, ST_POST_TRANS);
+        s->lc_state = LC_STATE_POST_TRANSITION;
+        return;
+    }
+}
+
+static void ot_lc_ctrl_start_transition(OtLcCtrlState *s)
+{
+    g_assert(s->state == ST_IDLE);
+
+    s->regs[R_STATUS] &= ~R_STATUS_READY_MASK;
+
+    bool tvolatile =
+        (bool)(s->volatile_raw_unlock_bm & LC_XSLOT(1u << s->owner));
+
+    uint32_t target_code = ot_lc_ctrl_get_target_state(s);
+    OtLcState target = ot_lc_ctrl_safe_convert_code_to_state(target_code);
+
+    trace_ot_lc_ctrl_start_transition(s->ot_id,
+                                      s->owner == LC_IF_SW ? "SW" : "DMI",
+                                      !tvolatile ? "OTP" :
+                                      s->volatile_raw_unlock ?
+                                                   "unlocked volatile" :
+                                                   "locked volatile",
+                                      LC_STATE_NAME(s->lc_state), s->lc_state,
+                                      LC_STATE_NAME(target), target,
+                                      s->lc_tcount);
+
+    if (s->volatile_raw_unlock && tvolatile) {
+        if (s->lc_state == LC_STATE_RAW || target == LC_STATE_TESTUNLOCKED0) {
+            ot_lc_ctrl_load_hashed_token(s);
+            if (ot_lc_ctrl_match_token(s, LC_TK_RAW_UNLOCK)) {
+                s->lc_state = LC_STATE_TESTUNLOCKED0;
+                if (s->lc_tcount == 0) {
+                    s->lc_tcount = 1u;
+                }
+                /* TODO DFT start override (see RTL) */
+
+                /* TODO change FSM behavior once this is selected */
+                s->volatile_unlocked = true;
+                s->regs[R_STATUS] |= R_STATUS_TRANSITION_SUCCESSFUL_MASK;
+                trace_ot_lc_ctrl_info(s->ot_id, "Successful volatile unlock");
+                s->regs[R_STATUS] |= R_STATUS_READY_MASK;
+                LC_FSM_CHANGE_STATE(s, ST_IDLE);
+            } else {
+                trace_ot_lc_ctrl_error(s->ot_id,
+                                       "Invalid volatile unlock token");
+                s->regs[R_STATUS] |= R_STATUS_TOKEN_ERROR_MASK;
+                LC_FSM_CHANGE_STATE(s, ST_POST_TRANS);
+                s->lc_state = LC_STATE_POST_TRANSITION;
+            }
+        } else {
+            trace_ot_lc_ctrl_error(s->ot_id,
+                                   "Invalid state(s) for volatile unlock");
+            s->regs[R_STATUS] |= R_STATUS_TRANSITION_ERROR_MASK;
+            LC_FSM_CHANGE_STATE(s, ST_POST_TRANS);
+            s->lc_state = LC_STATE_POST_TRANSITION;
+        }
+        return;
+    }
+
+    LC_FSM_CHANGE_STATE(s, ST_CLK_MUX);
+    switch (s->lc_state) {
+    case LC_STATE_RAW:
+    case LC_STATE_TESTUNLOCKED0:
+    case LC_STATE_TESTLOCKED0:
+    case LC_STATE_TESTUNLOCKED1:
+    case LC_STATE_TESTLOCKED1:
+    case LC_STATE_TESTUNLOCKED2:
+    case LC_STATE_TESTLOCKED2:
+    case LC_STATE_TESTUNLOCKED3:
+    case LC_STATE_TESTLOCKED3:
+    case LC_STATE_TESTUNLOCKED4:
+    case LC_STATE_TESTLOCKED4:
+    case LC_STATE_TESTUNLOCKED5:
+    case LC_STATE_TESTLOCKED5:
+    case LC_STATE_TESTUNLOCKED6:
+    case LC_STATE_TESTLOCKED6:
+    case LC_STATE_TESTUNLOCKED7:
+    case LC_STATE_RMA:
+        if (s->ext_clock_en) {
+            trace_ot_lc_ctrl_info(s->ot_id, "using external clock");
+            s->regs[R_STATUS] |= R_STATUS_EXT_CLOCK_SWITCHED_MASK;
+        } else {
+            trace_ot_lc_ctrl_info(s->ot_id, "using default clock");
+        }
+        break;
+    default:
+        break;
+    }
+
+    LC_FSM_CHANGE_STATE(s, ST_CNT_INCR);
+    if (s->lc_tcount >= LC_TRANSITION_COUNT_MAX) {
+        trace_ot_lc_ctrl_error(s->ot_id, "Max transition count reached");
+        s->regs[R_STATUS] |= R_STATUS_TRANSITION_COUNT_ERROR_MASK;
+        LC_FSM_CHANGE_STATE(s, ST_POST_TRANS);
+        s->lc_state = LC_STATE_POST_TRANSITION;
+        return;
+    }
+
+    if (target != LC_STATE_SCRAP) {
+        s->lc_tcount += 1;
+    } else {
+        s->lc_tcount = LC_TRANSITION_COUNT_MAX;
+    }
+
+    LC_FSM_CHANGE_STATE(s, ST_CNT_PROG);
+
+    ot_lc_ctrl_program_otp(s, s->lc_tcount, s->lc_state);
+}
+
+static void ot_lc_ctrl_resume_transition(OtLcCtrlState *s)
+{
+    g_assert(s->state == ST_TOKEN_HASH);
+
+    /*
+     * Notes:
+     *  - FLASH RMA is not implemented (not available on Darjeeling)
+     *  - Perform a unique Token Chaeck (vs. 3 successive ones on real HW)
+     */
+    LC_FSM_CHANGE_STATE(s, ST_TOKEN_CHECK0);
+
+    uint32_t target_code = ot_lc_ctrl_get_target_state(s);
+    OtLcState target_state = ot_lc_ctrl_safe_convert_code_to_state(target_code);
+
+    OtLcCtrlToken token;
+
+    if ((s->lc_state < LC_STATE_VALID_COUNT) &&
+        (target_state < LC_STATE_VALID_COUNT)) {
+        token = LC_TRANS_TOKEN_MATRIX[s->lc_state][target_state];
+    } else {
+        token = LC_TK_INVALID;
+    }
+
+    trace_ot_lc_ctrl_transit_request(s->ot_id,
+                                     s->owner == LC_IF_SW ? "SW" : "DMI",
+                                     LC_STATE_NAME(s->lc_state), s->lc_state,
+                                     LC_STATE_NAME(target_state), target_state,
+                                     LC_TOKEN_NAME(token), token);
+
+    if (token == LC_TK_INVALID) {
+        trace_ot_lc_ctrl_error(s->ot_id, "Invalid transition");
+        s->regs[R_STATUS] |= R_STATUS_TRANSITION_ERROR_MASK;
+        LC_FSM_CHANGE_STATE(s, ST_POST_TRANS);
+        s->lc_state = LC_STATE_POST_TRANSITION;
+    } else if (!ot_lc_ctrl_match_token(s, token)) {
+        trace_ot_lc_ctrl_error(s->ot_id, "Invalid OTP token");
+        s->regs[R_STATUS] |= R_STATUS_TOKEN_ERROR_MASK;
+        LC_FSM_CHANGE_STATE(s, ST_POST_TRANS);
+        s->lc_state = LC_STATE_POST_TRANSITION;
+    } else {
+        trace_ot_lc_ctrl_info(s->ot_id, "Valid token");
+
+        LC_FSM_CHANGE_STATE(s, ST_TRANS_PROG);
+
+        ot_lc_ctrl_program_otp(s, s->lc_tcount, target_state);
+    }
+}
+
+static inline size_t ot_lc_ctrl_get_keccak_rate_bytes(size_t kstrength)
+{
+    /*
+     * Rate is calculated with:
+     * rate = (1600 - 2*x) where x is the security strength (i.e. half the
+     * capacity).
+     */
+    return (KECCAK_STATE_BITS - 2u * kstrength) / 8u;
+}
+
+static void ot_lc_ctrl_compute_predefined_tokens(OtLcCtrlState *s)
+{
+    if (!s->raw_unlock_token_xstr) {
+        trace_ot_lc_ctrl_token_missing(s->ot_id, "raw_unlock_token");
+        return;
+    }
+
+    uint8_t all_zero_token[sizeof(OtOTPTokenValue)];
+    uint8_t raw_unlock_token[sizeof(OtOTPTokenValue)];
+
+    size_t len = strlen(s->raw_unlock_token_xstr);
+    if (len != sizeof(OtOTPTokenValue) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid raw_unlock_token length\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(raw_unlock_token, s->raw_unlock_token_xstr,
+                                 sizeof(OtOTPTokenValue), true, false)) {
+        error_setg(&error_fatal, "%s: %s unable to parse raw_unlock_token\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    memset(all_zero_token, 0, sizeof(all_zero_token));
+
+    const uint8_t *srcs[] = {
+        [LC_TK_INVALID] = NULL,
+        [LC_TK_ZERO] = all_zero_token,
+        [LC_TK_RAW_UNLOCK] = raw_unlock_token,
+    };
+    hash_state ltc_state;
+    uint8_t keccak_state[KECCAK_STATE_BYTES];
+
+    for (OtLcCtrlToken tk = LC_TK_RAW_UNLOCK; tk > LC_TK_INVALID; tk--) {
+        sha3_cshake_init(&ltc_state, (int)OT_LC_CTRL_KMAC_CONFIG.strength,
+                         OT_LC_CTRL_KMAC_CONFIG.prefix.funcname,
+                         OT_LC_CTRL_KMAC_CONFIG.prefix.funcname_len,
+                         OT_LC_CTRL_KMAC_CONFIG.prefix.customstr,
+                         OT_LC_CTRL_KMAC_CONFIG.prefix.customstr_len);
+        sha3_process(&ltc_state, srcs[tk], sizeof(OtOTPTokenValue));
+        sha3_cshake_done(&ltc_state, keccak_state,
+                         ot_lc_ctrl_get_keccak_rate_bytes(
+                             OT_LC_CTRL_KMAC_CONFIG.strength));
+        s->hashed_tokens[tk].lo = ldq_le_p(&keccak_state[0u]);
+        s->hashed_tokens[tk].hi = ldq_le_p(&keccak_state[sizeof(uint64_t)]);
+        s->hashed_token_bm |= 1u << tk;
+    }
+}
+
+static void ot_lc_ctrl_initialize(OtLcCtrlState *s)
+{
+    s->regs[R_HW_REVISION0] =
+        (((uint32_t)s->silicon_creator_id) << 16u) | ((uint32_t)s->product_id);
+    s->regs[R_HW_REVISION1] = (uint32_t)s->revision_id;
+
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    kc->connect_app(s->kmac, s->kmac_app, &OT_LC_CTRL_KMAC_CONFIG,
+                    &ot_lc_ctrl_kmac_handle_resp, s);
+
+    uint32_t enc_state = ot_lc_ctrl_load_lc_info(s);
+    if (enc_state == UINT32_MAX) {
+        trace_ot_lc_ctrl_error(s->ot_id, "LC invalid state");
+        s->state_invalid_error_bm |= 1u << 0u;
+    } else {
+        s->regs[R_STATUS] |= R_STATUS_INITIALIZED_MASK;
+    }
+
+    if (!ot_lc_ctrl_is_known_state(enc_state)) {
+        if (enc_state != UINT32_MAX) {
+            trace_ot_lc_ctrl_error(s->ot_id, "LC unknown state");
+        }
+        s->state_invalid_error_bm |= 1u << 1u;
+    } else {
+        s->lc_state = ot_lc_ctrl_convert_code_to_state(enc_state);
+    }
+
+    if (s->lc_tcount > LC_TRANSITION_COUNT_MAX) {
+        trace_ot_lc_ctrl_error(s->ot_id, "LC max transition count reached");
+        s->state_invalid_error_bm |= 1u << 2u;
+    }
+
+    if (s->regs[R_LC_ID_STATE] == LC_ID_STATE_INVALID) {
+        trace_ot_lc_ctrl_error(s->ot_id, "LC corrupted secret valid info");
+        s->state_invalid_error_bm |= 1u << 3u;
+    }
+
+    if (s->lc_state != LC_STATE_RAW && s->lc_tcount == 0) {
+        trace_ot_lc_ctrl_error(s->ot_id,
+                               "LC state non-RAW with zero transition count");
+        s->state_invalid_error_bm |= 1u << 4u;
+    }
+
+    if (s->regs[R_LC_ID_STATE] == LC_ID_STATE_PERSONALIZED) {
+        switch (s->lc_state) {
+        case LC_STATE_DEV:
+        case LC_STATE_PROD:
+        case LC_STATE_PRODEND:
+        case LC_STATE_RMA:
+        case LC_STATE_SCRAP:
+            break;
+        default:
+            trace_ot_lc_ctrl_error(s->ot_id,
+                                   "Personalized ID state w/ no secrets");
+            s->state_invalid_error_bm |= 1u << 5u;
+        }
+    }
+
+    if (!s->state_invalid_error_bm) {
+        ot_lc_ctrl_load_otp_hw_cfg(s);
+
+        s->regs[R_STATUS] |= R_STATUS_READY_MASK;
+
+        LC_FSM_CHANGE_STATE(s, ST_IDLE);
+
+        if (s->lc_state == LC_STATE_SCRAP) {
+            LC_FSM_CHANGE_STATE(s, ST_SCRAP);
+        }
+    } else {
+        LC_FSM_CHANGE_STATE(s, ST_INVALID);
+    }
+
+    trace_ot_lc_ctrl_initialize(s->ot_id, LC_STATE_NAME(s->lc_state),
+                                s->lc_state, s->lc_tcount,
+                                LC_FSM_STATE_NAME(s->state), s->state);
+}
+
+static void ot_lc_ctrl_pwr_lc_req(void *opaque, int n, int level)
+{
+    OtLcCtrlState *s = opaque;
+
+    g_assert(n == 0);
+
+    if (level) {
+        trace_ot_lc_ctrl_pwr_lc_req(s->ot_id, "signaled");
+        qemu_bh_schedule(s->pwc_lc_bh);
+    }
+}
+
+static void ot_lc_ctrl_escalate_rx(void *opaque, int n, int level)
+{
+    OtLcCtrlState *s = opaque;
+
+    g_assert((unsigned)n < 2u);
+
+    trace_ot_lc_ctrl_escalate_rx(s->ot_id, (unsigned)n, (bool)level);
+
+    if (level) {
+        qemu_bh_schedule(s->escalate_bh);
+    }
+}
+
+static void ot_lc_ctrl_a0_force_raw(void *opaque, int n, int level)
+{
+    OtLcCtrlState *s = opaque;
+
+    g_assert(n == 0);
+
+    trace_ot_lc_ctrl_force_raw(s->ot_id, (bool)level);
+
+    if (level) {
+        qemu_bh_schedule(s->escalate_bh);
+    }
+}
+
+static void ot_lc_ctrl_escalate_bh(void *opaque)
+{
+    OtLcCtrlState *s = opaque;
+
+    LC_FSM_CHANGE_STATE(s, ST_ESCALATE);
+
+    ot_lc_ctrl_update_broadcast(s);
+}
+
+static void ot_lc_ctrl_pwr_lc_bh(void *opaque)
+{
+    OtLcCtrlState *s = opaque;
+
+    trace_ot_lc_ctrl_pwr_lc_req(s->ot_id, "initialize");
+
+    ot_lc_ctrl_initialize(s);
+
+    ot_lc_ctrl_update_broadcast(s);
+
+    trace_ot_lc_ctrl_pwr_lc_req(s->ot_id, "done");
+
+    ibex_irq_set(&s->pwc_lc_rsp, 1);
+    ibex_irq_set(&s->pwc_lc_rsp, 0);
+}
+
+/* NOLINTBEGIN */
+static_assert(R_FIRST_EXCLUSIVE_REG == R_TRANSITION_TOKEN_0,
+              "Incoherent exclusive reg definition");
+static_assert(R_LAST_EXCLUSIVE_REG == R_TRANSITION_TARGET,
+              "Incoherent exclusive reg definition");
+/* NOLINTEND */
+
+static uint32_t ot_lc_ctrl_regs_read(OtLcCtrlState *s, hwaddr addr,
+                                     OtLcCtrlIf ifreq)
+{
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_LC_TRANSITION_CNT:
+        /* TODO: >= 24 -> state == SCRAP */
+
+        /* Error: should be 31 */
+        val32 = s->lc_tcount;
+        break;
+    case R_LC_STATE:
+        val32 = LC_ENCODE_STATE(s->lc_state);
+        break;
+    case R_OTP_VENDOR_TEST_STATUS:
+        val32 = ot_lc_ctrl_is_hw_mutex_owner(s, ifreq) &&
+                        ot_lc_ctrl_is_vendor_test_state(s->lc_state) ?
+                    s->regs[reg] :
+                    0u;
+        break;
+    case R_OTP_VENDOR_TEST_CTRL:
+        val32 = ot_lc_ctrl_is_hw_mutex_owner(s, ifreq) ? s->regs[reg] : 0u;
+        break;
+    case R_CLAIM_TRANSITION_IF:
+        val32 = ot_lc_ctrl_is_hw_mutex_owner(s, ifreq) ?
+                    OT_MULTIBITBOOL8_TRUE :
+                    OT_MULTIBITBOOL8_FALSE;
+        break;
+    case R_TRANSITION_CTRL:
+        val32 = 0;
+        if (ot_lc_ctrl_is_transition_en(s, ifreq)) {
+            if (s->ext_clock_en) {
+                val32 |= R_TRANSITION_CTRL_EXT_CLOCK_EN_MASK;
+            }
+            if (s->volatile_raw_unlock_bm & (1u << LC_XSLOT(ifreq))) {
+                val32 |= R_TRANSITION_CTRL_VOLATILE_RAW_UNLOCK_MASK;
+            }
+        }
+        break;
+    case R_TRANSITION_REGWEN:
+        val32 = ot_lc_ctrl_is_transition_en(s, ifreq) ?
+                    R_TRANSITION_REGWEN_EN_MASK :
+                    0;
+        break;
+    case R_TRANSITION_TOKEN_0:
+    case R_TRANSITION_TOKEN_1:
+    case R_TRANSITION_TOKEN_2:
+    case R_TRANSITION_TOKEN_3:
+    case R_TRANSITION_TARGET:
+        g_assert(LC_XSLOT(ifreq) < EXCLUSIVE_SLOTS_COUNT);
+        val32 = s->xregs[LC_XSLOT(ifreq)][reg - R_FIRST_EXCLUSIVE_REG];
+        break;
+    case R_STATUS:
+    case R_TRANSITION_CMD:
+    case R_CLAIM_TRANSITION_IF_REGWEN:
+    case R_LC_ID_STATE:
+    case R_HW_REVISION0:
+    case R_HW_REVISION1:
+    case R_DEVICE_ID_0:
+    case R_DEVICE_ID_1:
+    case R_DEVICE_ID_2:
+    case R_DEVICE_ID_3:
+    case R_DEVICE_ID_4:
+    case R_DEVICE_ID_5:
+    case R_DEVICE_ID_6:
+    case R_DEVICE_ID_7:
+    case R_MANUF_STATE_0:
+    case R_MANUF_STATE_1:
+    case R_MANUF_STATE_2:
+    case R_MANUF_STATE_3:
+    case R_MANUF_STATE_4:
+    case R_MANUF_STATE_5:
+    case R_MANUF_STATE_6:
+    case R_MANUF_STATE_7:
+        val32 = s->regs[reg];
+        break;
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    if (reg != R_STATUS) {
+        trace_ot_lc_ctrl_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg),
+                                     val32, pc);
+        s->status_cache.count = 0;
+    } else {
+        /*
+         * special trace for STATUS register: as LC_CTRL does not support an
+         * INTR channel, the SW needs to poll -a lot- the status register to
+         * check once an update operation is completed. To avoid flooding the
+         * trace log with many subsequent call traces to STATUS read out, track
+         * how many times the last STATUS read out has been repeated
+         */
+        if (s->status_cache.value == val32 && s->status_cache.count) {
+            s->status_cache.count += 1;
+        } else {
+            if (s->status_cache.count) {
+                trace_ot_lc_ctrl_io_read_out_repeat(s->ot_id, (uint32_t)addr,
+                                                    REG_NAME(reg),
+                                                    s->status_cache.count,
+                                                    s->status_cache.value);
+            }
+            s->status_cache.value = val32;
+            s->status_cache.count = 1;
+            trace_ot_lc_ctrl_io_read_out(s->ot_id, (uint32_t)addr,
+                                         REG_NAME(reg), val32, pc);
+        }
+    }
+
+    return val32;
+};
+
+static void ot_lc_ctrl_regs_write(OtLcCtrlState *s, hwaddr addr, uint32_t val32,
+                                  OtLcCtrlIf ifreq)
+{
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_lc_ctrl_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                              pc);
+
+    switch (reg) {
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_WMASK;
+        s->regs[R_ALERT_TEST] = val32;
+        ot_lc_ctrl_update_alerts(s);
+        break;
+    case R_CLAIM_TRANSITION_IF_REGWEN:
+        val32 &= R_CLAIM_TRANSITION_IF_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* rw0c */
+        break;
+    case R_CLAIM_TRANSITION_IF:
+        if (!(s->regs[R_CLAIM_TRANSITION_IF_REGWEN] &
+              R_CLAIM_TRANSITION_IF_REGWEN_EN_MASK)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: CLAIM_TRANSITION_IF disabled\n", __func__,
+                          s->ot_id);
+            break;
+        }
+        val32 &= R_CLAIM_TRANSITION_IF_MUTEX_MASK;
+        if (val32 == OT_MULTIBITBOOL8_TRUE) {
+            ot_lc_ctrl_lock_hw_mutex(s, ifreq);
+        } else {
+            ot_lc_ctrl_release_hw_mutex(s);
+        }
+        break;
+    case R_TRANSITION_CMD:
+        val32 &= R_TRANSITION_CMD_START_MASK;
+        if (val32) {
+            if (!ot_lc_ctrl_is_transition_en(s, ifreq)) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: LC IF not available\n",
+                              __func__, s->ot_id);
+                break;
+            }
+            ot_lc_ctrl_start_transition(s);
+        }
+        break;
+    case R_TRANSITION_CTRL:
+        if (!ot_lc_ctrl_is_transition_en(s, ifreq)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: LC IF not available\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        if (val32 & R_TRANSITION_CTRL_EXT_CLOCK_EN_MASK) {
+            s->ext_clock_en = true; /* rw1s */
+        }
+        if (s->volatile_raw_unlock) {
+            if (val32 & R_TRANSITION_CTRL_VOLATILE_RAW_UNLOCK_MASK) {
+                s->volatile_raw_unlock_bm |= 1u << LC_XSLOT(ifreq);
+            } else {
+                s->volatile_raw_unlock_bm &= ~(1u << LC_XSLOT(ifreq));
+            }
+        }
+        break;
+    case R_TRANSITION_TOKEN_0:
+    case R_TRANSITION_TOKEN_1:
+    case R_TRANSITION_TOKEN_2:
+    case R_TRANSITION_TOKEN_3:
+        if (!ot_lc_ctrl_is_transition_en(s, ifreq)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: LC IF not available\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        g_assert(LC_XSLOT(ifreq) < EXCLUSIVE_SLOTS_COUNT);
+        s->xregs[LC_XSLOT(ifreq)][reg - R_FIRST_EXCLUSIVE_REG] = val32;
+        break;
+    case R_TRANSITION_TARGET:
+        if (!ot_lc_ctrl_is_transition_en(s, ifreq)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: LC IF not available\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        val32 &= R_TRANSITION_TARGET_STATE_MASK;
+        if (ot_lc_ctrl_is_known_state(val32)) {
+            g_assert(LC_XSLOT(ifreq) < EXCLUSIVE_SLOTS_COUNT);
+            s->xregs[LC_XSLOT(ifreq)][reg - R_FIRST_EXCLUSIVE_REG] = val32;
+        }
+        break;
+    case R_OTP_VENDOR_TEST_CTRL:
+        if (!ot_lc_ctrl_is_transition_en(s, ifreq)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: LC IF not available\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        s->regs[reg] = val32;
+        break;
+    case R_STATUS:
+    case R_TRANSITION_REGWEN:
+    case R_OTP_VENDOR_TEST_STATUS:
+    case R_LC_STATE:
+    case R_LC_TRANSITION_CNT:
+    case R_LC_ID_STATE:
+    case R_HW_REVISION0:
+    case R_HW_REVISION1:
+    case R_DEVICE_ID_0:
+    case R_DEVICE_ID_1:
+    case R_DEVICE_ID_2:
+    case R_DEVICE_ID_3:
+    case R_DEVICE_ID_4:
+    case R_DEVICE_ID_5:
+    case R_DEVICE_ID_6:
+    case R_DEVICE_ID_7:
+    case R_MANUF_STATE_0:
+    case R_MANUF_STATE_1:
+    case R_MANUF_STATE_2:
+    case R_MANUF_STATE_3:
+    case R_MANUF_STATE_4:
+    case R_MANUF_STATE_5:
+    case R_MANUF_STATE_6:
+    case R_MANUF_STATE_7:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static uint64_t
+ot_lc_ctrl_sw_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtLcCtrlState *s = opaque;
+    (void)size;
+
+    return (uint32_t)ot_lc_ctrl_regs_read(s, addr, LC_IF_SW);
+}
+
+static void ot_lc_ctrl_sw_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                     unsigned size)
+{
+    OtLcCtrlState *s = opaque;
+    (void)size;
+
+    ot_lc_ctrl_regs_write(s, addr, (uint32_t)val64, LC_IF_SW);
+}
+
+static uint64_t
+ot_lc_ctrl_dmi_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtLcCtrlState *s = opaque;
+    (void)size;
+
+    return (uint32_t)ot_lc_ctrl_regs_read(s, addr, LC_IF_DMI);
+}
+
+static void ot_lc_ctrl_dmi_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                      unsigned size)
+{
+    OtLcCtrlState *s = opaque;
+    (void)size;
+
+    ot_lc_ctrl_regs_write(s, addr, (uint32_t)val64, LC_IF_DMI);
+}
+
+static void ot_lc_ctrl_load_transitions(OtLcCtrlState *s,
+                                        OtLcCtrlTransition trans,
+                                        uint16_t **first, uint16_t **last)
+{
+    g_assert(trans >= 0 && trans < LC_CTRL_TRANS_COUNT);
+
+    const OtLcCtrlTransitionDesc *tdesc = &TRANSITION_DESC[trans];
+    size_t len;
+
+    Error *err = NULL;
+    uint16_t *state[LC_CTRL_TSTATE_COUNT] = { NULL, NULL };
+
+    for (unsigned ix = 0; ix < LC_CTRL_TSTATE_COUNT; ix++) {
+        state[ix] = g_new0(uint16_t, tdesc->word_count);
+
+        if (!s->trans_cfg[trans].state[ix]) {
+            trace_ot_lc_ctrl_transition_missing(s->ot_id, tdesc->name,
+                                                TSTATE_NAME(ix));
+            /* non-fatal, state has been cleared out */
+            continue;
+        }
+
+        len = strlen(s->trans_cfg[trans].state[ix]);
+        /* each byte is encoding with two ASCII nibbles */
+        if (len != tdesc->word_count * sizeof(uint16_t) * 2u) {
+            qemu_log("%s: %s: %s %s %zu %zu\n", __func__, s->ot_id, tdesc->name,
+                     TSTATE_NAME(ix), len,
+                     tdesc->word_count * sizeof(uint16_t));
+            error_setg(&err, "%s: %s invalid %s %s length\n", __func__,
+                       s->ot_id, tdesc->name, TSTATE_NAME(ix));
+            break;
+        }
+
+        if (ot_common_parse_hexa_str((uint8_t *)state[ix],
+                                     s->trans_cfg[trans].state[ix],
+                                     tdesc->word_count * sizeof(uint16_t),
+                                     false, true)) {
+            error_setg(&err, "%s: %s unable to parse %s %s\n", __func__,
+                       s->ot_id, tdesc->name, TSTATE_NAME(ix));
+            break;
+        }
+    }
+
+    if (!err) {
+        /*
+         * if the configuration is missing, it is not a fatal error. Use an
+         * blank sequence, so that emulation works as if the config was not
+         * valid
+         */
+        g_assert(state[LC_CTRL_TSTATE_FIRST] && state[LC_CTRL_TSTATE_LAST]);
+        *first = state[LC_CTRL_TSTATE_FIRST];
+        *last = state[LC_CTRL_TSTATE_LAST];
+        return;
+    }
+
+    for (unsigned ix = 0; ix < LC_CTRL_TSTATE_COUNT; ix++) {
+        g_free(state[ix]);
+    }
+
+    /* equivalent to error_fatal usage */
+    error_report_err(err);
+    exit(1);
+}
+
+static void ot_lc_ctrl_configure_lc_states(OtLcCtrlState *s)
+{
+    uint16_t *first;
+    uint16_t *last;
+
+    ot_lc_ctrl_load_transitions(s, LC_CTRL_TRANS_LC_STATE, &first, &last);
+
+    for (unsigned lcix = 0; lcix < NUM_LC_STATE; lcix++) {
+        uint16_t *lcval = &s->lc_states[lcix][0];
+        const uint8_t *tpl = LC_STATES_TPL[lcix];
+        for (unsigned pos = 0; pos < LC_STATE_WORDS; pos++) {
+            unsigned slot = LC_STATE_WORD(tpl[pos]);
+            g_assert(slot < LC_STATE_WORDS);
+            if (LC_STATE_A_WORD(tpl[pos])) {
+                lcval[pos] = first[slot];
+            } else if (LC_STATE_B_WORD(tpl[pos])) {
+                lcval[pos] = last[slot];
+            } else if (LC_STATE_ZERO_WORD(tpl[pos])) {
+                lcval[pos] = 0u;
+            } else {
+                g_assert_not_reached();
+            }
+        }
+    }
+
+    g_free(last);
+    g_free(first);
+}
+
+static void ot_lc_ctrl_configure_transitions(
+    OtLcCtrlState *s, OtLcCtrlTransition trans, uint16_t *table)
+{
+    const OtLcCtrlTransitionDesc *tdesc = &TRANSITION_DESC[trans];
+
+    uint16_t *first;
+    uint16_t *last;
+    ot_lc_ctrl_load_transitions(s, trans, &first, &last);
+
+    uint16_t *lcval = table;
+    memset(lcval, 0, tdesc->word_count * sizeof(uint16_t)); /* RAW stage */
+    lcval += tdesc->word_count;
+
+    if (tdesc->mode != LC_TR_MODE_HISTORICAL) {
+        memcpy(lcval, first, tdesc->word_count * sizeof(uint16_t));
+        lcval += tdesc->word_count;
+    }
+
+    if (tdesc->mode != LC_TR_MODE_FULL_CHANGE) {
+        unsigned step_count = tdesc->step_count -
+                              (tdesc->mode == LC_TR_MODE_FIRST_FULL ? 1u : 0u);
+        for (unsigned tix = 1u; tix < step_count; tix++) {
+            memcpy(&lcval[0], &last[0], tix * sizeof(uint16_t));
+            memcpy(&lcval[tix], &first[tix],
+                   (tdesc->word_count - tix) * sizeof(uint16_t));
+            lcval += tdesc->word_count;
+        }
+    } else {
+        g_assert(tdesc->step_count == 3u);
+        memcpy(lcval, last, tdesc->word_count * sizeof(uint16_t));
+    }
+
+#ifdef OT_LC_CTRL_DEBUG
+    /* dump the generated transition tables */
+    lcval = table;
+    for (unsigned tix = 0; tix < tdesc->step_count; tix++) {
+        qemu_log("%s: %s: %s[%2u]", __func__, s->ot_id, tdesc->name, tix);
+        for (unsigned wix = 0; wix < tdesc->word_count; wix++) {
+            qemu_log(" %04hx", *lcval++);
+        };
+        qemu_log("\n");
+    }
+#endif
+
+    g_free(last);
+    g_free(first);
+}
+
+static void ot_lc_ctrl_configure_km_div(OtLcCtrlState *s)
+{
+    for (unsigned ix = 0; ix < LC_DIV_COUNT; ix++) {
+        if (!s->km_div_xstrs[ix]) {
+            trace_ot_lc_ctrl_km_div_missing(s->ot_id, ix);
+            continue;
+        }
+
+        size_t len = strlen(s->km_div_xstrs[ix]);
+        if (len != OT_LC_KEYMGR_DIV_BYTES * 2u) {
+            error_setg(&error_fatal, "%s: %s invalid km_div #%u length\n",
+                       __func__, s->ot_id, ix);
+            continue;
+        }
+
+        if (ot_common_parse_hexa_str(s->km_divs[ix], s->km_div_xstrs[ix],
+                                     OT_LC_KEYMGR_DIV_BYTES, true, true)) {
+            error_setg(&error_fatal, "%s: %s unable to parse km_div #%u\n",
+                       __func__, s->ot_id, ix);
+            continue;
+        }
+    }
+}
+
+static void ot_lc_ctrl_get_keymgr_div(const OtLcCtrlState *s,
+                                      OtLcCtrlKeyMgrDiv *div)
+{
+    g_assert(div);
+
+    memcpy(&div->data[0], s->km_divs[s->km_div_type], OT_LC_KEYMGR_DIV_BYTES);
+}
+
+static uint32_t
+ot_lc_ctrl_get_soc_dbg_state(const OtLcCtrlState *s, unsigned state)
+{
+    g_assert(s->decode_soc_dbg);
+
+    /*
+     * SoC debug controller is signalled with the OT_LC_CTRL_SOC_DBG interrupt
+     * line, with the decoded SoC debug state (OtSoCDbgState). In C code, this
+     * is defined as an enumeration. Valid constant values are initialized with
+     * the "soc_dbg_first" and "soc_dbg_last" properties and generated in
+     * #ot_lc_ctrl_configure_transitions. The encoded OTP values are loaded in
+     * #ot_lc_ctrl_load_otp_hw_cfg and decoded, if valid, into a OtSoCDbgState
+     * enumerated value. This feature is not deeply related to LC controller
+     * which only handles the Top-dependent SoC debug state value matrix and
+     * forward them to the Soc Debug Controller.
+     * However, the Soc Debug Controller now needs to expose the actual OTP
+     * encoded values onbly for debug purposes.
+     * This function converts back a OtSoCDbgState value into its actual
+     * top-specific encoding.
+     */
+    uint32_t code;
+
+    if (state < OT_LC_SOC_DBG_STATE_COUNT) {
+        code = (uint32_t)s->soc_dbgs[state][0u] |
+               ((uint32_t)s->soc_dbgs[state][1u]) << 16u;
+    } else {
+        error_report("%s: %s: unsupported Soc Dbg state %u", __func__, s->ot_id,
+                     state);
+        code = UINT32_MAX;
+    }
+
+    return code;
+}
+
+
+static const Property ot_lc_ctrl_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtLcCtrlState, ot_id),
+    DEFINE_PROP_LINK("otp-ctrl", OtLcCtrlState, otp_ctrl, TYPE_OT_OTP_IF,
+                     DeviceState *),
+    DEFINE_PROP_LINK("kmac", OtLcCtrlState, kmac, TYPE_OT_KMAC, OtKMACState *),
+    DEFINE_PROP_STRING("raw_unlock_token", OtLcCtrlState,
+                       raw_unlock_token_xstr),
+    DEFINE_PROP_STRING("invalid", OtLcCtrlState, km_div_xstrs[LC_DIV_INVALID]),
+    DEFINE_PROP_STRING("test_unlocked", OtLcCtrlState,
+                       km_div_xstrs[LC_DIV_TEST_UNLOCKED]),
+    DEFINE_PROP_STRING("dev", OtLcCtrlState, km_div_xstrs[LC_DIV_DEV]),
+    DEFINE_PROP_STRING("production", OtLcCtrlState, km_div_xstrs[LC_DIV_PROD]),
+    DEFINE_PROP_STRING("rma", OtLcCtrlState, km_div_xstrs[LC_DIV_RMA]),
+    DEFINE_PROP_STRING("lc_state_first", OtLcCtrlState,
+                       trans_cfg[LC_CTRL_TRANS_LC_STATE]
+                           .state[LC_CTRL_TSTATE_FIRST]),
+    DEFINE_PROP_STRING("lc_state_last", OtLcCtrlState,
+                       trans_cfg[LC_CTRL_TRANS_LC_STATE]
+                           .state[LC_CTRL_TSTATE_LAST]),
+    DEFINE_PROP_STRING("lc_trscnt_first", OtLcCtrlState,
+                       trans_cfg[LC_CTRL_TRANS_LC_TCOUNT]
+                           .state[LC_CTRL_TSTATE_FIRST]),
+    DEFINE_PROP_STRING("lc_trscnt_last", OtLcCtrlState,
+                       trans_cfg[LC_CTRL_TRANS_LC_TCOUNT]
+                           .state[LC_CTRL_TSTATE_LAST]),
+    DEFINE_PROP_STRING("ownership_first", OtLcCtrlState,
+                       trans_cfg[LC_CTRL_TRANS_OWNERSHIP]
+                           .state[LC_CTRL_TSTATE_FIRST]),
+    DEFINE_PROP_STRING("ownership_last", OtLcCtrlState,
+                       trans_cfg[LC_CTRL_TRANS_OWNERSHIP]
+                           .state[LC_CTRL_TSTATE_LAST]),
+    DEFINE_PROP_STRING("soc_dbg_first", OtLcCtrlState,
+                       trans_cfg[LC_CTRL_TRANS_SOC_DBG]
+                           .state[LC_CTRL_TSTATE_FIRST]),
+    DEFINE_PROP_STRING("soc_dbg_last", OtLcCtrlState,
+                       trans_cfg[LC_CTRL_TRANS_SOC_DBG]
+                           .state[LC_CTRL_TSTATE_LAST]),
+    DEFINE_PROP_UINT16("silicon_creator_id", OtLcCtrlState, silicon_creator_id,
+                       0),
+    DEFINE_PROP_UINT16("product_id", OtLcCtrlState, product_id, 0),
+    DEFINE_PROP_UINT8("revision_id", OtLcCtrlState, revision_id, 0),
+    DEFINE_PROP_BOOL("volatile_raw_unlock", OtLcCtrlState, volatile_raw_unlock,
+                     true),
+    DEFINE_PROP_BOOL("decode_soc_dbg", OtLcCtrlState, decode_soc_dbg, false),
+    DEFINE_PROP_UINT8("kmac-app", OtLcCtrlState, kmac_app, UINT8_MAX),
+};
+
+static const MemoryRegionOps ot_lc_ctrl_sw_regs_ops = {
+    .read = &ot_lc_ctrl_sw_regs_read,
+    .write = &ot_lc_ctrl_sw_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_lc_ctrl_dmi_regs_ops = {
+    .read = &ot_lc_ctrl_dmi_regs_read,
+    .write = &ot_lc_ctrl_dmi_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_lc_ctrl_reset_enter(Object *obj, ResetType type)
+{
+    OtLcCtrlClass *c = OT_LC_CTRL_GET_CLASS(obj);
+    OtLcCtrlState *s = OT_LC_CTRL(obj);
+
+    trace_ot_lc_ctrl_reset(s->ot_id);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    qemu_bh_cancel(s->escalate_bh);
+    qemu_bh_cancel(s->pwc_lc_bh);
+
+    memset(s->regs, 0, REGS_SIZE);
+    memset(s->xregs, 0, sizeof(s->xregs));
+
+    s->owner = LC_IF_NONE;
+    LC_FSM_CHANGE_STATE(s, ST_RESET);
+    s->kmac_state = ST_KMAC_IDLE;
+    s->regs[R_CLAIM_TRANSITION_IF] = OT_MULTIBITBOOL8_FALSE;
+    s->regs[R_CLAIM_TRANSITION_IF_REGWEN] = 1u;
+    s->ext_clock_en = false;
+    s->volatile_unlocked = false;
+    s->force_raw = false;
+    s->volatile_raw_unlock_bm = 0;
+    s->state_invalid_error_bm = 0;
+
+    memset(&s->status_cache, 0, sizeof(s->status_cache));
+
+    ot_lc_ctrl_update_alerts(s);
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->broadcasts); ix++) {
+        ibex_irq_set(&s->broadcasts[ix], 0);
+    }
+
+    ibex_irq_set(&s->pwc_lc_rsp, 0);
+
+    s->lc_state = LC_STATE_INVALID;
+    s->lc_tcount = LC_TRANSITION_COUNT_MAX + 1u;
+    s->km_div_type = LC_DIV_INVALID;
+
+    /*
+     * do not broadcast the current states, wait for initialization to happen,
+     * triggered by the Power Manager
+     */
+}
+
+static void ot_lc_ctrl_realize(DeviceState *dev, Error **errp)
+{
+    OtLcCtrlState *s = OT_LC_CTRL(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->otp_ctrl);
+    g_assert(s->kmac);
+    g_assert(s->kmac_app != UINT8_MAX);
+
+    (void)OBJECT_CHECK(OtOTPIf, s->otp_ctrl, TYPE_OT_OTP_IF);
+
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    g_assert(kc->connect_app);
+    g_assert(kc->app_request);
+
+    /*
+     * "ID of the silicon creator. Assigned by the OpenTitan project.
+     * 0x0000: invalid value
+     * 0x0001 - 0x3FFF: reserved for use in the open-source OpenTitan project
+     * 0x4000 - 0x7FFF: reserved for real integrations of OpenTitan
+     * 0x8000 - 0xFFFF: reserved for future use"
+     */
+    if (s->silicon_creator_id == 0 || s->silicon_creator_id > 0x8000) {
+        error_setg(&error_fatal, "Invalid silicon_creator_id: 0x%04x",
+                   s->silicon_creator_id);
+    }
+
+    /*
+     * "Used to identify a class of devices. Assigned by the Silicon Creator
+     * 0x0000: invalid value
+     * 0x0001 - 0x3FFF: reserved for discrete chip products
+     * 0x4000 - 0x7FFF: reserved for integrated IP products
+     * 0x8000 - 0xFFFF: reserved for future use"
+     */
+    if (s->product_id == 0 || s->product_id > 0x8000) {
+        error_setg(&error_fatal, "Invalid product_id: 0x%04x", s->product_id);
+    }
+
+    /*
+     * "Product revision ID. Assigned by the Silicon Creator
+     * Zero is an invalid value."
+     */
+    if (s->revision_id == 0) {
+        error_setg(&error_fatal, "Invalid revision_id: 0x%02x", s->revision_id);
+    }
+
+    ot_lc_ctrl_configure_lc_states(s);
+    ot_lc_ctrl_configure_transitions(s, LC_CTRL_TRANS_LC_TCOUNT,
+                                     (uint16_t *)s->lc_transitions);
+    ot_lc_ctrl_configure_transitions(s, LC_CTRL_TRANS_OWNERSHIP,
+                                     (uint16_t *)s->ownerships);
+    if (s->decode_soc_dbg) {
+        ot_lc_ctrl_configure_transitions(s, LC_CTRL_TRANS_SOC_DBG,
+                                         (uint16_t *)s->soc_dbgs);
+    }
+    ot_lc_ctrl_configure_km_div(s);
+    ot_lc_ctrl_compute_predefined_tokens(s);
+}
+
+static void ot_lc_ctrl_init(Object *obj)
+{
+    OtLcCtrlState *s = OT_LC_CTRL(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_lc_ctrl_sw_regs_ops, s,
+                          TYPE_OT_LC_CTRL, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    memory_region_init_io(&s->dmi_mmio, obj, &ot_lc_ctrl_dmi_regs_ops, s,
+                          TYPE_OT_LC_CTRL, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->dmi_mmio);
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+    s->lc_states = g_new0(OtLcCtrlStateValue, NUM_LC_STATE);
+    s->lc_transitions =
+        g_new0(OtLcCtrlTransitionCountValue, NUM_LC_TRANSITION_COUNT);
+    s->ownerships = g_new0(OtLcCtrlOwnershipValue, NUM_OWNERSHIP);
+    s->soc_dbgs = g_new0(OtLcCtrlSocDbgValue, NUM_SOC_DBG);
+    s->hashed_tokens = g_new0(OtOTPTokenValue, LC_TK_COUNT);
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->broadcasts); ix++) {
+        ibex_qdev_init_irq(obj, &s->broadcasts[ix], OT_LC_BROADCAST);
+    }
+
+    ibex_qdev_init_irq(obj, &s->pwc_lc_rsp, OT_PWRMGR_LC_RSP);
+    ibex_qdev_init_irq_default(obj, &s->soc_dbg_tx, OT_LC_SOC_DBG,
+                               /* initialize with an invalid level */
+                               OT_LC_SOC_DBG_STATE_COUNT);
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_lc_ctrl_pwr_lc_req,
+                            OT_PWRMGR_LC_REQ, 1);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_lc_ctrl_escalate_rx,
+                            OT_ALERT_ESCALATE, 2);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_lc_ctrl_a0_force_raw,
+                            OT_LC_A0_FORCE_RAW, 1);
+
+    s->pwc_lc_bh = qemu_bh_new(&ot_lc_ctrl_pwr_lc_bh, s);
+    s->escalate_bh = qemu_bh_new(&ot_lc_ctrl_escalate_bh, s);
+
+#ifdef OT_LC_CTRL_DEBUG
+    s->hexstr = g_new0(char, OT_LC_CTRL_HEXSTR_SIZE);
+#endif
+}
+
+static void ot_lc_ctrl_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_lc_ctrl_realize;
+    device_class_set_props(dc, ot_lc_ctrl_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtLcCtrlClass *lc = OT_LC_CTRL_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_lc_ctrl_reset_enter, NULL, NULL,
+                                       &lc->parent_phases);
+
+    lc->get_keymgr_div = &ot_lc_ctrl_get_keymgr_div;
+    lc->get_soc_dbg_state = &ot_lc_ctrl_get_soc_dbg_state;
+}
+
+static const TypeInfo ot_lc_ctrl_info = {
+    .name = TYPE_OT_LC_CTRL,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtLcCtrlState),
+    .instance_init = &ot_lc_ctrl_init,
+    .class_size = sizeof(OtLcCtrlClass),
+    .class_init = &ot_lc_ctrl_class_init,
+};
+
+static void ot_lc_ctrl_register_types(void)
+{
+    type_register_static(&ot_lc_ctrl_info);
+}
+
+type_init(ot_lc_ctrl_register_types);
diff --git a/hw/opentitan/ot_lc_ctrl_matrix.c b/hw/opentitan/ot_lc_ctrl_matrix.c
new file mode 100644
index 0000000000000..7392d5dfb38ae
--- /dev/null
+++ b/hw/opentitan/ot_lc_ctrl_matrix.c
@@ -0,0 +1,220 @@
+/*
+ * QEMU OpenTitan Life Cycle controller transition matrix.
+ *
+ * Slots that are not explictly filled evaluate to LC_TK_INVALID.
+ *
+ * Copyright (c) 2024 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* this prevents linters from checking this file without its parent file */
+#ifdef HW_OPENTITAN_OT_LC_CTRL_H
+
+/* clang-format off */
+
+static const OtLcCtrlToken
+LC_TRANS_TOKEN_MATRIX[LC_STATE_VALID_COUNT][LC_STATE_VALID_COUNT] = {
+    [LC_STATE_RAW] = {
+        [LC_STATE_TESTUNLOCKED0] = LC_TK_RAW_UNLOCK,
+        [LC_STATE_TESTUNLOCKED1] = LC_TK_RAW_UNLOCK,
+        [LC_STATE_TESTUNLOCKED2] = LC_TK_RAW_UNLOCK,
+        [LC_STATE_TESTUNLOCKED3] = LC_TK_RAW_UNLOCK,
+        [LC_STATE_TESTUNLOCKED4] = LC_TK_RAW_UNLOCK,
+        [LC_STATE_TESTUNLOCKED5] = LC_TK_RAW_UNLOCK,
+        [LC_STATE_TESTUNLOCKED6] = LC_TK_RAW_UNLOCK,
+        [LC_STATE_TESTUNLOCKED7] = LC_TK_RAW_UNLOCK,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTUNLOCKED0] = {
+        [LC_STATE_TESTLOCKED0] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED1] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED2] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED3] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED4] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED5] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED6] = LC_TK_ZERO,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_RMA] = LC_TK_ZERO,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTLOCKED0] = {
+        [LC_STATE_TESTUNLOCKED1] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED2] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED3] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED4] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED5] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED6] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED7] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTUNLOCKED1] = {
+        [LC_STATE_TESTLOCKED1] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED2] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED3] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED4] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED5] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED6] = LC_TK_ZERO,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_RMA] = LC_TK_ZERO,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTLOCKED1] = {
+        [LC_STATE_TESTUNLOCKED2] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED3] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED4] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED5] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED6] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED7] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTUNLOCKED2] = {
+        [LC_STATE_TESTLOCKED2] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED3] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED4] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED5] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED6] = LC_TK_ZERO,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_RMA] = LC_TK_ZERO,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTLOCKED2] = {
+        [LC_STATE_TESTUNLOCKED3] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED4] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED5] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED6] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED7] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTUNLOCKED3] = {
+        [LC_STATE_TESTLOCKED3] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED4] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED5] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED6] = LC_TK_ZERO,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_RMA] = LC_TK_ZERO,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTLOCKED3] = {
+        [LC_STATE_TESTUNLOCKED4] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED5] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED6] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED7] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTUNLOCKED4] = {
+        [LC_STATE_TESTLOCKED4] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED5] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED6] = LC_TK_ZERO,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_RMA] = LC_TK_ZERO,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTLOCKED4] = {
+        [LC_STATE_TESTUNLOCKED5] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED6] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED7] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTUNLOCKED5] = {
+        [LC_STATE_TESTLOCKED5] = LC_TK_ZERO,
+        [LC_STATE_TESTLOCKED6] = LC_TK_ZERO,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_RMA] = LC_TK_ZERO,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTLOCKED5] = {
+        [LC_STATE_TESTUNLOCKED6] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_TESTUNLOCKED7] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTUNLOCKED6] = {
+        [LC_STATE_TESTLOCKED6] = LC_TK_ZERO,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_RMA] = LC_TK_ZERO,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTLOCKED6] = {
+        [LC_STATE_TESTUNLOCKED7] = LC_TK_TEST_UNLOCK,
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_TESTUNLOCKED7] = {
+        [LC_STATE_DEV] = LC_TK_TEST_EXIT,
+        [LC_STATE_PROD] = LC_TK_TEST_EXIT,
+        [LC_STATE_PRODEND] = LC_TK_TEST_EXIT,
+        [LC_STATE_RMA] = LC_TK_ZERO,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_DEV] = {
+        [LC_STATE_RMA] = LC_TK_RMA,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_PROD] = {
+        [LC_STATE_RMA] = LC_TK_RMA,
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_PRODEND] = {
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+    [LC_STATE_RMA] = {
+        [LC_STATE_SCRAP] = LC_TK_ZERO,
+    },
+};
+
+/* clang-format off */
+
+#endif /* #ifdef HW_OPENTITAN_OT_LC_CTRL_H */
diff --git a/hw/opentitan/ot_mbx.c b/hw/opentitan/ot_mbx.c
new file mode 100644
index 0000000000000..0c7fcdeac92c0
--- /dev/null
+++ b/hw/opentitan/ot_mbx.c
@@ -0,0 +1,851 @@
+/*
+ * QEMU OpenTitan Data Object Exchange Mailbox
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMIT_ADDRED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note that system-side interrupts are not managed by the DOE Mailbox.
+ * Registers dedicated to system-side interrupt management are only storage
+ * space that the guest software (called the host side to get more confusing,
+ * not related to the VM host) should read and act accordingly, using other
+ * devices to signal the requester that a response is ready to be read.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_address_space.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_mbx.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "system/memory.h"
+#include "trace.h"
+
+
+/* ------------------------------------------------------------------------ */
+/* Register definitions */
+/* ------------------------------------------------------------------------ */
+
+#define PARAM_NUM_ALERTS 2u
+#define PARAM_NUM_IRQS   3u
+
+/* clang-format off */
+
+/* Internal interface, as seen from the OT responder */
+REG32(HOST_INTR_STATE, 0x00u)
+    SHARED_FIELD(INTR_MBX_READY, 0u, 1u)
+    SHARED_FIELD(INTR_MBX_ABORT, 1u, 1u)
+    SHARED_FIELD(INTR_MBX_ERROR, 2u, 1u)
+REG32(HOST_INTR_ENABLE, 0x04u)
+REG32(HOST_INTR_TEST, 0x08u)
+REG32(HOST_ALERT_TEST, 0x0cu)
+    FIELD(HOST_ALERT_TEST, FATAL_FAULT, 0u, 1u)
+    FIELD(HOST_ALERT_TEST, RECOV_FAULT, 1u, 1u)
+REG32(HOST_CONTROL, 0x10u)
+    FIELD(HOST_CONTROL, ABORT, 0u, 1u)
+    FIELD(HOST_CONTROL, ERROR, 1u, 1u)
+REG32(HOST_STATUS, 0x14u)
+    FIELD(HOST_STATUS, BUSY, 0u, 1u)
+    FIELD(HOST_STATUS, SYS_INTR_STATE, 1u, 1u)
+    FIELD(HOST_STATUS, SYS_INTR_ENABLE, 2u, 1u)
+REG32(HOST_ADDRESS_RANGE_REGWEN, 0x18u)
+    FIELD(HOST_ADDRESS_RANGE_REGWEN, EN, 0u, 4u)
+REG32(HOST_ADDRESS_RANGE_VALID, 0x1cu)
+    FIELD(HOST_ADDRESS_RANGE_VALID, VALID, 0u, 1u)
+REG32(HOST_IN_BASE_ADDR, 0x20u)
+REG32(HOST_IN_LIMIT_ADDR, 0x24u)
+REG32(HOST_IN_WRITE_PTR, 0x28u)
+REG32(HOST_OUT_BASE_ADDR, 0x2cu)
+REG32(HOST_OUT_LIMIT_ADDR, 0x30u)
+REG32(HOST_OUT_READ_PTR, 0x34u)
+REG32(HOST_OUT_OBJECT_SIZE, 0x38u)
+    FIELD(HOST_OUT_OBJECT_SIZE, SIZE, 0u, 10u)
+REG32(HOST_INTR_MSG_ADDR, 0x3cu)
+REG32(HOST_INTR_MSG_DATA, 0x40u)
+
+/*
+ * External Mailbox interface, as seen from a requester. Note that in case of
+ * a PCIe requester, the first two registers (SYS_INTR_*) are not visible as
+ * they are overlaid on the sys side by the PCIe wrapper with DOE EXT CAP and
+ * CAP registers
+ */
+REG32(DEPRECATED_MSG_ADDR, 0x00u)
+REG32(DEPRECATED_MSG_DATA, 0x04u)
+REG32(SYS_CONTROL, 0x08u)
+    FIELD(SYS_CONTROL, ABORT, 0u, 1u)
+    FIELD(SYS_CONTROL, SYS_INT_EN, 1u, 1u)
+    FIELD(SYS_CONTROL, GO, 31u, 1u)
+REG32(SYS_STATUS, 0x0cu)
+    FIELD(SYS_STATUS, BUSY, 0u, 1u)
+    FIELD(SYS_STATUS, INT, 1u, 1u)
+    FIELD(SYS_STATUS, ERROR, 2u, 1u)
+    FIELD(SYS_STATUS, READY, 31u, 1u)
+REG32(SYS_WRITE_DATA, 0x10u)
+REG32(SYS_READ_DATA, 0x14u)
+REG32(SYS_INTR_MSG_ADDR, 0x18u)
+REG32(SYS_INTR_MSG_DATA, 0x1cu)
+
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_HOST_LAST_REG (R_HOST_INTR_MSG_DATA)
+#define REGS_HOST_COUNT (R_HOST_LAST_REG + 1u)
+#define REGS_HOST_SIZE  (REGS_HOST_COUNT * sizeof(uint32_t))
+
+#define R_SYS_LAST_REG (R_SYS_INTR_MSG_DATA)
+#define REGS_SYS_COUNT (R_SYS_LAST_REG + 1u)
+#define REGS_SYS_SIZE  (REGS_SYS_COUNT * sizeof(uint32_t))
+
+#define R_SYSLOCAL_FIRST_REG (R_SYS_INTR_MSG_ADDR)
+#define R_SYSLOCAL_LAST_REG  (R_SYS_INTR_MSG_DATA)
+#define REGS_SYSLOCAL_COUNT  (R_SYSLOCAL_LAST_REG - R_SYSLOCAL_FIRST_REG + 1u)
+#define REGS_SYSLOCAL_SIZE   (REGS_SYSLOCAL_COUNT * sizeof(uint32_t))
+
+#define HOST_INTR_MASK \
+    (INTR_MBX_READY_MASK | INTR_MBX_ABORT_MASK | INTR_MBX_ERROR_MASK)
+#define HOST_ALERT_TEST_MASK \
+    (R_HOST_ALERT_TEST_FATAL_FAULT_MASK | R_HOST_ALERT_TEST_RECOV_FAULT_MASK)
+#define HOST_CONTROL_MASK \
+    (R_HOST_CONTROL_ABORT_MASK | R_HOST_CONTROL_ABORT_MASK)
+
+static_assert(OT_MBX_HOST_REGS_COUNT == REGS_HOST_COUNT, "Invalid HOST regs");
+static_assert(OT_MBX_SYS_REGS_COUNT == REGS_SYS_COUNT, "Invalid SYS regs");
+
+#define REG_NAME(_kind_, _reg_) \
+    ((((_reg_) < REGS_##_kind_##_COUNT) && REG_##_kind_##_NAMES[_reg_]) ? \
+         REG_##_kind_##_NAMES[_reg_] : \
+         "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+
+#define xtrace_ot_mbx_status(_s_) \
+    trace_ot_mbx_status((_s_)->ot_id, __LINE__, ot_mbx_is_on_abort(_s_), \
+                        ot_mbx_is_on_error(_s_), ot_mbx_is_busy(_s_))
+
+/* clang-format off */
+static const char *REG_HOST_NAMES[REGS_HOST_COUNT] = {
+    REG_NAME_ENTRY(HOST_INTR_STATE),
+    REG_NAME_ENTRY(HOST_INTR_ENABLE),
+    REG_NAME_ENTRY(HOST_INTR_TEST),
+    REG_NAME_ENTRY(HOST_ALERT_TEST),
+    REG_NAME_ENTRY(HOST_CONTROL),
+    REG_NAME_ENTRY(HOST_STATUS),
+    REG_NAME_ENTRY(HOST_ADDRESS_RANGE_REGWEN),
+    REG_NAME_ENTRY(HOST_ADDRESS_RANGE_VALID),
+    REG_NAME_ENTRY(HOST_IN_BASE_ADDR),
+    REG_NAME_ENTRY(HOST_IN_LIMIT_ADDR),
+    REG_NAME_ENTRY(HOST_IN_WRITE_PTR),
+    REG_NAME_ENTRY(HOST_OUT_BASE_ADDR),
+    REG_NAME_ENTRY(HOST_OUT_LIMIT_ADDR),
+    REG_NAME_ENTRY(HOST_OUT_READ_PTR),
+    REG_NAME_ENTRY(HOST_OUT_OBJECT_SIZE),
+    REG_NAME_ENTRY(HOST_INTR_MSG_ADDR),
+    REG_NAME_ENTRY(HOST_INTR_MSG_DATA),
+};
+
+static const char *REG_SYS_NAMES[REGS_SYS_COUNT] = {
+    REG_NAME_ENTRY(DEPRECATED_MSG_ADDR),
+    REG_NAME_ENTRY(DEPRECATED_MSG_DATA),
+    REG_NAME_ENTRY(SYS_CONTROL),
+    REG_NAME_ENTRY(SYS_STATUS),
+    REG_NAME_ENTRY(SYS_WRITE_DATA),
+    REG_NAME_ENTRY(SYS_READ_DATA),
+    REG_NAME_ENTRY(SYS_INTR_MSG_ADDR),
+    REG_NAME_ENTRY(SYS_INTR_MSG_DATA),
+};
+/* clang-format on */
+
+#undef REG_NAME_ENTRY
+
+enum {
+    ALERT_RECOVERABLE,
+    ALERT_FATAL,
+};
+
+typedef struct {
+    MemoryRegion mmio;
+    IbexIRQ irqs[PARAM_NUM_IRQS];
+    IbexIRQ alerts[PARAM_NUM_ALERTS];
+    uint32_t regs[REGS_HOST_COUNT];
+} OtMbxHost;
+
+typedef struct {
+    MemoryRegion mmio;
+    uint32_t regs[REGS_SYSLOCAL_COUNT];
+    AddressSpace *ram_as;
+} OtMbxSys;
+
+struct OtMbxState {
+    SysBusDevice parent_obj;
+
+    OtMbxHost host;
+    OtMbxSys sys;
+
+    char *ot_id;
+    char *ram_as_name;
+};
+
+struct OtMbxClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static void ot_mbx_host_update_irqs(OtMbxState *s)
+{
+    OtMbxHost *host = &s->host;
+    uint32_t *hregs = host->regs;
+
+    uint32_t levels = hregs[R_HOST_INTR_STATE] & hregs[R_HOST_INTR_ENABLE];
+
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        int level = (int)(bool)(levels & (1u << ix));
+        if (level != ibex_irq_get_level(&host->irqs[ix])) {
+            trace_ot_mbx_host_update_irq(s->ot_id,
+                                         ibex_irq_get_level(&host->irqs[ix]),
+                                         level);
+        }
+        ibex_irq_set(&host->irqs[ix], level);
+    }
+}
+
+static bool ot_mbx_is_enabled(const OtMbxState *s)
+{
+    return s->host.regs[R_HOST_ADDRESS_RANGE_VALID];
+}
+
+static bool ot_mbx_is_busy(const OtMbxState *s)
+{
+    return (bool)(s->host.regs[R_HOST_STATUS] & R_HOST_STATUS_BUSY_MASK);
+}
+
+static bool ot_mbx_is_on_error(const OtMbxState *s)
+{
+    return (bool)(s->host.regs[R_HOST_CONTROL] & R_HOST_CONTROL_ERROR_MASK);
+}
+
+static bool ot_mbx_is_on_abort(const OtMbxState *s)
+{
+    return (bool)(s->host.regs[R_HOST_CONTROL] & R_HOST_CONTROL_ABORT_MASK);
+}
+
+static bool ot_mbx_is_sys_interrupt(const OtMbxState *s)
+{
+    return (bool)(s->host.regs[R_HOST_STATUS] &
+                  R_HOST_STATUS_SYS_INTR_STATE_MASK);
+}
+
+static void ot_mbx_set_error(OtMbxState *s)
+{
+    uint32_t *hregs = s->host.regs;
+
+    /* should busy be set? */
+    hregs[R_HOST_CONTROL] |= R_HOST_CONTROL_ERROR_MASK;
+
+    if (hregs[R_HOST_STATUS] & R_HOST_STATUS_SYS_INTR_ENABLE_MASK) {
+        hregs[R_HOST_STATUS] |= R_HOST_STATUS_SYS_INTR_STATE_MASK;
+    }
+
+    /*
+     * Note: you should not use this interrupt, as it might create
+     * hard-to-manage signalling since IRQ might be raise at unexpected time
+     * in mailbox management. You've been warned.
+     *
+     * On error, wait for GO bit to be set, then handle any HW error at this
+     * point. If the SYS side detects the error bit before it sets the GO flag
+     * it can immediately trigger an abort.
+     */
+    hregs[R_HOST_INTR_STATE] |= INTR_MBX_ERROR_MASK;
+    ot_mbx_host_update_irqs(s);
+}
+
+static void ot_mbx_clear_busy(OtMbxState *s)
+{
+    uint32_t *hregs = s->host.regs;
+
+    hregs[R_HOST_STATUS] &= ~R_HOST_STATUS_BUSY_MASK;
+    hregs[R_HOST_IN_WRITE_PTR] = hregs[R_HOST_IN_BASE_ADDR];
+    hregs[R_HOST_OUT_READ_PTR] = hregs[R_HOST_OUT_BASE_ADDR];
+
+    trace_ot_mbx_busy(s->ot_id, "clear");
+}
+
+static uint64_t ot_mbx_host_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtMbxState *s = opaque;
+    (void)size;
+    OtMbxHost *host = &s->host;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_HOST_INTR_STATE:
+    case R_HOST_INTR_ENABLE:
+    case R_HOST_CONTROL:
+    case R_HOST_STATUS:
+    case R_HOST_ADDRESS_RANGE_REGWEN:
+    case R_HOST_ADDRESS_RANGE_VALID:
+    case R_HOST_IN_BASE_ADDR:
+    case R_HOST_IN_LIMIT_ADDR:
+    case R_HOST_IN_WRITE_PTR:
+    case R_HOST_OUT_BASE_ADDR:
+    case R_HOST_OUT_LIMIT_ADDR:
+    case R_HOST_OUT_READ_PTR:
+    case R_HOST_OUT_OBJECT_SIZE:
+    case R_HOST_INTR_MSG_ADDR:
+    case R_HOST_INTR_MSG_DATA:
+        val32 = host->regs[reg];
+        break;
+    case R_HOST_INTR_TEST:
+    case R_HOST_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(HOST, reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_mbx_host_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(HOST, reg),
+                                  val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_mbx_host_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                   unsigned size)
+{
+    OtMbxState *s = opaque;
+    (void)size;
+    OtMbxHost *host = &s->host;
+    uint32_t *hregs = host->regs;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_mbx_host_io_write(s->ot_id, (uint32_t)addr, REG_NAME(HOST, reg),
+                               val32, pc);
+    switch (reg) {
+    case R_HOST_INTR_STATE:
+        val32 &= HOST_INTR_MASK;
+        hregs[reg] &= ~val32; /* RW1C */
+        ot_mbx_host_update_irqs(s);
+        break;
+    case R_HOST_INTR_ENABLE:
+        val32 &= HOST_INTR_MASK;
+        hregs[reg] = val32;
+        ot_mbx_host_update_irqs(s);
+        break;
+    case R_HOST_INTR_TEST:
+        val32 &= HOST_INTR_MASK;
+        hregs[R_HOST_INTR_STATE] |= val32;
+        ot_mbx_host_update_irqs(s);
+        break;
+    case R_HOST_ALERT_TEST:
+        val32 &= HOST_ALERT_TEST_MASK;
+        for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+            ibex_irq_set(&host->alerts[ix], (int)((val32 >> ix) & 0x1u));
+        }
+        break;
+    case R_HOST_CONTROL:
+        if (val32 & R_HOST_CONTROL_ABORT_MASK) {
+            /* clear busy once abort is cleared */
+            trace_ot_mbx_change_state(s->ot_id, "clear busy");
+            ot_mbx_clear_busy(s);
+            hregs[reg] &= ~R_HOST_CONTROL_ABORT_MASK; /* RW1C */
+        }
+        if (val32 & R_HOST_CONTROL_ERROR_MASK) { /* RW1S */
+            ot_mbx_set_error(s);
+        };
+        xtrace_ot_mbx_status(s);
+        break;
+    case R_HOST_STATUS:
+    case R_HOST_IN_WRITE_PTR:
+    case R_HOST_OUT_READ_PTR:
+    case R_HOST_INTR_MSG_ADDR:
+    case R_HOST_INTR_MSG_DATA:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(HOST, reg));
+        break;
+    case R_HOST_ADDRESS_RANGE_REGWEN:
+        val32 &= R_HOST_ADDRESS_RANGE_REGWEN_EN_MASK;
+        hregs[reg] = ot_multibitbool_w0c_write(hregs[reg], val32, 4u);
+        break;
+    case R_HOST_ADDRESS_RANGE_VALID: {
+        val32 &= R_HOST_ADDRESS_RANGE_VALID_VALID_MASK;
+        bool validate = !hregs[reg] && (bool)val32;
+        hregs[reg] = val32;
+        if (validate) {
+            trace_ot_mbx_change_state(s->ot_id, "validate");
+            ot_mbx_clear_busy(s);
+            xtrace_ot_mbx_status(s);
+        } else {
+            trace_ot_mbx_change_state(s->ot_id, "invalidate");
+            hregs[R_HOST_STATUS] |= R_HOST_STATUS_BUSY_MASK;
+            xtrace_ot_mbx_status(s);
+        }
+    } break;
+    case R_HOST_IN_BASE_ADDR:
+    case R_HOST_IN_LIMIT_ADDR:
+    case R_HOST_OUT_BASE_ADDR:
+    case R_HOST_OUT_LIMIT_ADDR:
+        if (hregs[R_HOST_ADDRESS_RANGE_REGWEN] == OT_MULTIBITBOOL4_TRUE) {
+            val32 &= ~0b11u; /*b1..b0 always 0 */
+            hregs[reg] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s regwen protected 0x%02x\n",
+                          __func__, s->ot_id, (uint32_t)addr);
+        }
+        break;
+    case R_HOST_OUT_OBJECT_SIZE:
+        val32 &= R_HOST_OUT_OBJECT_SIZE_SIZE_MASK;
+        if (ot_mbx_is_on_error(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s cannot update objsize: on error\n", __func__,
+                          s->ot_id);
+            break;
+        }
+        if (ot_mbx_is_on_abort(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s cannot update objsize: aborted\n", __func__,
+                          s->ot_id);
+            break;
+        }
+        hregs[reg] = val32;
+        trace_ot_mbx_change_state(s->ot_id, "response available");
+        if (val32) {
+            hregs[R_HOST_OUT_READ_PTR] = hregs[R_HOST_OUT_BASE_ADDR];
+
+            if (hregs[R_HOST_STATUS] & R_HOST_STATUS_SYS_INTR_ENABLE_MASK) {
+                hregs[R_HOST_STATUS] |= R_HOST_STATUS_SYS_INTR_STATE_MASK;
+            }
+        }
+        xtrace_ot_mbx_status(s);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static void ot_mbx_sys_abort(OtMbxState *s)
+{
+    uint32_t *hregs = s->host.regs;
+
+    trace_ot_mbx_change_state(s->ot_id, "abort");
+
+    hregs[R_HOST_CONTROL] |= R_HOST_CONTROL_ABORT_MASK;
+
+    /*
+     * "DOE instance shall clear this bit [SYS_READY] in response to a DOE Abort
+     * handling, if not already clear" -> SYS_READY is OBJECT_SIZE != 0
+     */
+    hregs[R_HOST_OUT_OBJECT_SIZE] = 0;
+
+    /*
+     * "This bit [BUSY] must be set by the DOE instance while processing an
+     * abort command. Cleared when abort handling is complete"
+     */
+    hregs[R_HOST_STATUS] |= R_HOST_STATUS_BUSY_MASK;
+    trace_ot_mbx_busy(s->ot_id, "set on abort");
+
+    /*
+     * "Bit [ERROR] is cleared by writing a 1’b1 to the DOE abort bit in the DOE
+     * Control Register. DOE Abort is the only mechanism to clear this status
+     * bit"
+     */
+    hregs[R_HOST_CONTROL] &= ~R_HOST_CONTROL_ERROR_MASK;
+
+    hregs[R_HOST_INTR_STATE] |= INTR_MBX_ABORT_MASK;
+}
+
+static void ot_mbx_sys_go(OtMbxState *s)
+{
+    uint32_t *hregs = s->host.regs;
+
+    trace_ot_mbx_change_state(s->ot_id, "go");
+
+    if (!ot_mbx_is_on_abort(s)) {
+        /*
+         * accept GO even if an error has been flagged so the HOST side can
+         * handle it and trigger an interrupt from FW
+         */
+        hregs[R_HOST_STATUS] |= R_HOST_STATUS_BUSY_MASK;
+        trace_ot_mbx_busy(s->ot_id, "set on go");
+        /* wild guess as doc is not available */
+        hregs[R_HOST_INTR_STATE] |= INTR_MBX_READY_MASK;
+        xtrace_ot_mbx_status(s);
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s cannot GO: abort on going\n",
+                      __func__, s->ot_id);
+    }
+}
+
+static MemTxResult ot_mbx_sys_regs_read_with_attrs(
+    void *opaque, hwaddr addr, uint64_t *val64, unsigned size, MemTxAttrs attrs)
+{
+    OtMbxState *s = opaque;
+    (void)size;
+    OtMbxHost *host = &s->host;
+    OtMbxSys *sys = &s->sys;
+    uint32_t *hregs = host->regs;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_DEPRECATED_MSG_ADDR:
+    case R_DEPRECATED_MSG_DATA:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s deprecated reg %s 0x%02x\n",
+                      __func__, s->ot_id, REG_NAME(SYS, reg), (uint32_t)addr);
+        val32 = 0;
+        break;
+    case R_SYS_CONTROL:
+        val32 = hregs[R_HOST_STATUS] & R_HOST_STATUS_SYS_INTR_ENABLE_MASK ?
+                    R_SYS_CONTROL_SYS_INT_EN_MASK :
+                    0u;
+        break;
+    case R_SYS_STATUS:
+        val32 = FIELD_DP32(0, SYS_STATUS, BUSY, (uint32_t)ot_mbx_is_busy(s));
+        val32 = FIELD_DP32(val32, SYS_STATUS, INT,
+                           (uint32_t)ot_mbx_is_sys_interrupt(s));
+        val32 = FIELD_DP32(val32, SYS_STATUS, ERROR,
+                           (uint32_t)ot_mbx_is_on_error(s));
+        val32 = FIELD_DP32(val32, SYS_STATUS, READY,
+                           (uint32_t)(hregs[R_HOST_OUT_OBJECT_SIZE] != 0));
+        break;
+    case R_SYS_READ_DATA:
+        if (!ot_mbx_is_enabled(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s mailbox is not enabled\n",
+                          __func__, s->ot_id);
+            val32 = 0;
+            break;
+        }
+        if (ot_mbx_is_on_error(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s mailbox is on error\n",
+                          __func__, s->ot_id);
+            val32 = 0;
+            break;
+        }
+        if (hregs[R_HOST_OUT_OBJECT_SIZE] == 0) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s read underflow\n", __func__,
+                          s->ot_id);
+            val32 = 0u;
+        }
+        hwaddr raddr = (hwaddr)hregs[R_HOST_OUT_READ_PTR];
+        MemTxResult mres;
+        mres = address_space_rw(sys->ram_as, raddr, attrs, &val32,
+                                sizeof(val32), false);
+        if (mres != MEMTX_OK) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Cannot read @ 0x%x: %u\n",
+                          __func__, s->ot_id, (uint32_t)raddr, mres);
+            ibex_irq_set(&s->host.alerts[ALERT_RECOVERABLE], 1);
+            val32 = 0u;
+        }
+        break;
+    case R_SYS_WRITE_DATA:
+        /* "Reads of this register must return all 0’s." */
+        val32 = 0;
+        break;
+    case R_SYS_INTR_MSG_ADDR:
+        val32 = host->regs[R_HOST_INTR_MSG_ADDR];
+        break;
+    case R_SYS_INTR_MSG_DATA:
+        val32 = host->regs[R_HOST_INTR_MSG_DATA];
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    trace_ot_mbx_sys_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(SYS, reg),
+                                 val32);
+
+    *val64 = (uint64_t)val32;
+
+    /* never returns an error */
+    return MEMTX_OK;
+};
+
+static MemTxResult ot_mbx_sys_regs_write_with_attrs(
+    void *opaque, hwaddr addr, uint64_t val64, unsigned size, MemTxAttrs attrs)
+{
+    OtMbxState *s = opaque;
+    (void)size;
+    OtMbxHost *host = &s->host;
+    OtMbxSys *sys = &s->sys;
+    uint32_t *hregs = host->regs;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    trace_ot_mbx_sys_io_write(s->ot_id, (uint32_t)addr, REG_NAME(SYS, reg),
+                              val32);
+
+    switch (reg) {
+    case R_DEPRECATED_MSG_ADDR:
+    case R_DEPRECATED_MSG_DATA:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s deprecated reg %s 0x%02x\n",
+                      __func__, s->ot_id, REG_NAME(SYS, reg), (uint32_t)addr);
+        break;
+    case R_SYS_CONTROL:
+        if (ot_mbx_is_enabled(s)) {
+            if (val32 & R_SYS_CONTROL_ABORT_MASK) {
+                ot_mbx_sys_abort(s);
+            } else if (val32 & R_SYS_CONTROL_GO_MASK) {
+                ot_mbx_sys_go(s);
+            }
+            if (val32 & R_SYS_CONTROL_SYS_INT_EN_MASK) {
+                hregs[R_HOST_STATUS] |= R_HOST_STATUS_SYS_INTR_ENABLE_MASK;
+            } else {
+                hregs[R_HOST_STATUS] &= ~R_HOST_STATUS_SYS_INTR_ENABLE_MASK;
+            }
+            ot_mbx_host_update_irqs(s);
+        } else {
+            if (val32) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: %s mailbox is not enabled\n", __func__,
+                              s->ot_id);
+            }
+        }
+        xtrace_ot_mbx_status(s);
+        break;
+    case R_SYS_STATUS:
+        if (val32 & R_SYS_STATUS_INT_MASK) { /* RW1C bit */
+            hregs[R_HOST_STATUS] &= ~R_HOST_STATUS_SYS_INTR_STATE_MASK;
+        }
+        break;
+    case R_SYS_WRITE_DATA:
+        if (!ot_mbx_is_enabled(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s mailbox is not enabled\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        if (ot_mbx_is_on_error(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s mailbox is on error\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        if (ot_mbx_is_busy(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s mailbox is busy\n", __func__,
+                          s->ot_id);
+            break;
+        }
+        if (hregs[R_HOST_IN_WRITE_PTR] >= hregs[R_HOST_IN_LIMIT_ADDR]) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s write overflow\n", __func__,
+                          s->ot_id);
+            ot_mbx_set_error(s);
+            xtrace_ot_mbx_status(s);
+        }
+        hwaddr waddr = (hwaddr)hregs[R_HOST_IN_WRITE_PTR];
+        MemTxResult mres;
+        mres = address_space_rw(sys->ram_as, waddr, attrs, &val32,
+                                sizeof(val32), true);
+        if (mres != MEMTX_OK) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Cannot write @ 0x%x: %u\n",
+                          __func__, s->ot_id, (uint32_t)waddr, mres);
+            ot_mbx_set_error(s);
+            xtrace_ot_mbx_status(s);
+            ibex_irq_set(&s->host.alerts[ALERT_RECOVERABLE], 1);
+            break;
+        }
+        hregs[R_HOST_IN_WRITE_PTR] += sizeof(uint32_t);
+        break;
+    case R_SYS_READ_DATA:
+        if (!ot_mbx_is_enabled(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s mailbox is not enabled\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        if (ot_mbx_is_on_error(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s mailbox is on error\n",
+                          __func__, s->ot_id);
+            break;
+        }
+        if (hregs[R_HOST_OUT_OBJECT_SIZE]) {
+            hregs[R_HOST_OUT_READ_PTR] += sizeof(uint32_t);
+            hregs[R_HOST_OUT_OBJECT_SIZE] -= 1u;
+        }
+        if (hregs[R_HOST_OUT_OBJECT_SIZE] == 0) {
+            /* reset the read pointer*/
+            hregs[R_HOST_OUT_READ_PTR] = hregs[R_HOST_OUT_BASE_ADDR];
+            /* clear busy once the full response has been read */
+            ot_mbx_clear_busy(s);
+            xtrace_ot_mbx_status(s);
+        }
+        break;
+    case R_SYS_INTR_MSG_ADDR:
+        host->regs[R_HOST_INTR_MSG_ADDR] = val32;
+        break;
+    case R_SYS_INTR_MSG_DATA:
+        host->regs[R_HOST_INTR_MSG_DATA] = val32;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+
+    /* never returns an error */
+    return MEMTX_OK;
+}
+
+static const Property ot_mbx_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtMbxState, ot_id),
+    DEFINE_PROP_STRING("ram_as_name", OtMbxState, ram_as_name),
+};
+
+static const MemoryRegionOps ot_mbx_host_regs_ops = {
+    .read = &ot_mbx_host_regs_read,
+    .write = &ot_mbx_host_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_mbx_sys_regs_ops = {
+    .read_with_attrs = &ot_mbx_sys_regs_read_with_attrs,
+    .write_with_attrs = &ot_mbx_sys_regs_write_with_attrs,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_mbx_reset_enter(Object *obj, ResetType type)
+{
+    OtMbxClass *c = OT_MBX_GET_CLASS(obj);
+    OtMbxState *s = OT_MBX(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    OtMbxHost *host = &s->host;
+    OtMbxSys *sys = &s->sys;
+
+    memset(host->regs, 0, sizeof(host->regs));
+    memset(sys->regs, 0, sizeof(sys->regs));
+    host->regs[R_HOST_ADDRESS_RANGE_REGWEN] = OT_MULTIBITBOOL4_TRUE;
+    host->regs[R_HOST_STATUS] = R_SYS_STATUS_BUSY_MASK;
+
+    ot_mbx_host_update_irqs(s);
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_irq_set(&s->host.alerts[ix], 0);
+    }
+
+    xtrace_ot_mbx_status(s);
+}
+
+static void ot_mbx_reset_exit(Object *obj, ResetType type)
+{
+    OtMbxClass *c = OT_MBX_GET_CLASS(obj);
+    OtMbxState *s = OT_MBX(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    OtMbxSys *sys = &s->sys;
+
+    if (!sys->ram_as) {
+        Object *soc = obj->parent;
+        Object *as =
+            object_property_get_link(soc, s->ram_as_name, &error_fatal);
+        OtAddressSpaceState *oas =
+            OBJECT_CHECK(OtAddressSpaceState, as, TYPE_OT_ADDRESS_SPACE);
+        sys->ram_as = ot_address_space_get(oas);
+        g_assert(sys->ram_as);
+    }
+}
+
+static void ot_mbx_realize(DeviceState *dev, Error **errp)
+{
+    OtMbxState *s = OT_MBX(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->ram_as_name);
+}
+
+static void ot_mbx_init(Object *obj)
+{
+    OtMbxState *s = OT_MBX(obj);
+
+    memory_region_init_io(&s->host.mmio, obj, &ot_mbx_host_regs_ops, s,
+                          TYPE_OT_MBX "-host", REGS_HOST_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->host.mmio);
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_sysbus_init_irq(obj, &s->host.irqs[ix]);
+    }
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->host.alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    memory_region_init_io(&s->sys.mmio, obj, &ot_mbx_sys_regs_ops, s,
+                          TYPE_OT_MBX "-sys", REGS_SYS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->sys.mmio);
+}
+
+static void ot_mbx_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_mbx_realize;
+    device_class_set_props(dc, ot_mbx_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtMbxClass *mc = OT_MBX_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_mbx_reset_enter, NULL,
+                                       &ot_mbx_reset_exit, &mc->parent_phases);
+}
+
+static const TypeInfo ot_mbx_info = {
+    .name = TYPE_OT_MBX,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtMbxState),
+    .instance_init = &ot_mbx_init,
+    .class_size = sizeof(OtMbxClass),
+    .class_init = &ot_mbx_class_init,
+};
+
+static void ot_mbx_register_types(void)
+{
+    type_register_static(&ot_mbx_info);
+}
+
+type_init(ot_mbx_register_types);
diff --git a/hw/opentitan/ot_noise_src.c b/hw/opentitan/ot_noise_src.c
new file mode 100644
index 0000000000000..6564a3a560719
--- /dev/null
+++ b/hw/opentitan/ot_noise_src.c
@@ -0,0 +1,42 @@
+/*
+ * QEMU OpenTitan Noise Source interface
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/opentitan/ot_noise_src.h"
+
+static const TypeInfo ot_noise_src_info = {
+    .name = TYPE_OT_NOISE_SRC_IF,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(OtNoiseSrcIfClass),
+};
+
+static void ot_noise_src_register_types(void)
+{
+    type_register_static(&ot_noise_src_info);
+}
+
+type_init(ot_noise_src_register_types);
diff --git a/hw/opentitan/ot_otbn.c b/hw/opentitan/ot_otbn.c
new file mode 100644
index 0000000000000..51d86512741bb
--- /dev/null
+++ b/hw/opentitan/ot_otbn.c
@@ -0,0 +1,905 @@
+/*
+ * QEMU OpenTitan Big Number device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * OTBN emulation backend is a derivative work of the Rust RISC-V simulator,
+ * and is released under the Apache2 license. See README.md file in the
+ * hw/opentitan/otbn/otbn directory.
+ */
+
+#include "qemu/osdep.h"
+#include <zlib.h> /* for CRC-32 */
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_clkmgr.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_fifo32.h"
+#include "hw/opentitan/ot_key_sink.h"
+#include "hw/opentitan/ot_otbn.h"
+#include "hw/opentitan/otbn/otbnproxy.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+#undef OT_OTBN_DEBUG
+
+/* clang-format off */
+REG32(INTR_STATE, 0x00u)
+    SHARED_FIELD(INTR_DONE, 0u, 1u)
+REG32(INTR_ENABLE, 0x04u)
+REG32(INTR_TEST, 0x08u)
+REG32(ALERT_TEST, 0x0cu)
+    FIELD(ALERT_TEST, FATAL, 0u, 1u)
+    FIELD(ALERT_TEST, RECOVERY, 1u, 1u)
+REG32(CMD, 0x10u)
+    FIELD(CMD, CMD, 0u, 8u)
+REG32(CTRL, 0x14u)
+    FIELD(CTRL, SW_ERRS_FATAL, 0u, 1u)
+REG32(STATUS, 0x18u)
+    FIELD(STATUS, STATUS, 0u, 8u)
+REG32(ERR_BITS, 0x1cu)
+    FIELD(ERR_BITS, BAD_DATA_ADDR, 0u, 1u)
+    FIELD(ERR_BITS, BAD_INSN_ADDR, 1u, 1u)
+    FIELD(ERR_BITS, CALL_STACK, 2u, 1u)
+    FIELD(ERR_BITS, ILLEGAL_INSN, 3u, 1u)
+    FIELD(ERR_BITS, LOOP, 4u, 1u)
+    FIELD(ERR_BITS, KEY_INVALID, 5u, 1u)
+    FIELD(ERR_BITS, RND_REP_CHK_FAIL, 6u, 1u)
+    FIELD(ERR_BITS, RND_FIPS_CHK_FAIL, 7u, 1u)
+    FIELD(ERR_BITS, IMEM_INTG_VIOLATION, 16u, 1u)
+    FIELD(ERR_BITS, DMEM_INTG_VIOLATION, 17u, 1u)
+    FIELD(ERR_BITS, REG_INTG_VIOLATION, 18u, 1u)
+    FIELD(ERR_BITS, BUS_INTG_VIOLATION, 19u, 1u)
+    FIELD(ERR_BITS, BAD_INTERNAL_STATE, 20u, 1u)
+    FIELD(ERR_BITS, ILLEGAL_BUS_ACCESS, 21u, 1u)
+    FIELD(ERR_BITS, LIFECYCLE_ESCALATION, 22u, 1u)
+    FIELD(ERR_BITS, FATAL_SOFTWARE, 23u, 1u)
+REG32(FATAL_ALERT_CAUSE, 0x20u)
+    FIELD(FATAL_ALERT_CAUSE, IMEM_INTG_VIOLATION, 0u, 1u)
+    FIELD(FATAL_ALERT_CAUSE, DMEM_INTG_VIOLATION, 1u, 1u)
+    FIELD(FATAL_ALERT_CAUSE, REG_INTG_VIOLATION, 2u, 1u)
+    FIELD(FATAL_ALERT_CAUSE, BUS_INTG_VIOLATION, 3u, 1u)
+    FIELD(FATAL_ALERT_CAUSE, BAD_INTERNAL_STATE, 4u, 1u)
+    FIELD(FATAL_ALERT_CAUSE, ILLEGAL_BUS_ACCESS, 5u, 1u)
+    FIELD(FATAL_ALERT_CAUSE, LIFECYCLE_ESCALATION, 6u, 1u)
+    FIELD(FATAL_ALERT_CAUSE, FATAL_SOFTWARE, 7u, 1u)
+REG32(INSN_CNT, 0x24u)
+REG32(LOAD_CHECKSUM, 0x28u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define OT_OTBN_REGS_BASE 0x0u
+#define OT_OTBN_IMEM_BASE 0x4000u
+#define OT_OTBN_DMEM_BASE 0x8000u
+
+#define OT_OTBN_CLOCK_ACTIVE "clock-active"
+#define OT_OTBN_CLOCK_INPUT  "clock-in"
+
+#define R_LAST_REG (R_LOAD_CHECKSUM)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CMD),
+    REG_NAME_ENTRY(CTRL),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(ERR_BITS),
+    REG_NAME_ENTRY(FATAL_ALERT_CAUSE),
+    REG_NAME_ENTRY(INSN_CNT),
+    REG_NAME_ENTRY(LOAD_CHECKSUM),
+};
+
+typedef struct {
+    OtFifo32 packer; /* 32-bit to 256-bit packer */
+    OtOTBNState *otbn; /* parent */
+    OtEDNState *device; /* EDN instance property */
+    QEMUBH *proxy_entropy_req_bh;
+    uint8_t ep; /* EDN client endpoint property */
+    bool connected; /* EDN has been connected */
+    bool no_fips; /* Non FIPS-compliant data */
+    bool entropy_requested; /* EDN request on-going */
+} OtOTBNRandom;
+
+enum {
+    ALERT_FATAL,
+    ALERT_RECOVERABLE,
+    ALERT_COUNT,
+};
+
+struct OtOTBNState {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion mmio;
+    MemoryRegion regs;
+    MemoryRegion imem;
+    MemoryRegion dmem;
+
+    IbexIRQ irq_done;
+    IbexIRQ alerts[ALERT_COUNT];
+    IbexIRQ clock_active;
+
+    QEMUBH *proxy_completion_bh;
+    QEMUTimer *proxy_defer;
+    OTBNProxy proxy;
+    unsigned pclk; /* Current input clock */
+    const char *clock_src_name; /* IRQ name once connected */
+    char *hexstr;
+
+    uint32_t intr_state;
+    uint32_t intr_enable;
+    uint32_t intr_test;
+    uint32_t alert_test;
+    uint32_t errbits;
+    uint32_t load_checksum;
+
+    enum OtOTBNCommand last_cmd;
+
+    char *ot_id;
+    char *clock_name;
+    DeviceState *clock_src;
+    char *log_file;
+    OtOTBNRandom rnds[OT_OTBN_RND_COUNT];
+    bool log_asm;
+};
+
+struct OtOTBNClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+#ifdef OT_OTBN_DEBUG
+#define OT_OTBN_HEXSTR_SIZE  (OT_OTBN_KEY_SIZE * 2u + 2u)
+#define TRACE_OTBN(msg, ...) qemu_log("%s: " msg "\n", __func__, ##__VA_ARGS__);
+#define ot_otbn_hexdump(_s_, _b_, _l_) \
+    ot_common_lhexdump((const uint8_t *)_b_, _l_, false, (_s_)->hexstr, \
+                       OT_OTBN_HEXSTR_SIZE)
+#else
+#define TRACE_OTBN(msg, ...)
+#define ot_otbn_hexdump(_s_, _b_, _l_)
+#endif
+
+static void ot_otbn_request_entropy(OtOTBNRandom *rnd);
+
+static bool ot_otbn_is_idle(OtOTBNState *s)
+{
+    return ot_otbn_proxy_get_status(s->proxy) == OT_OTBN_STATUS_IDLE;
+}
+
+static bool ot_otbn_is_locked(OtOTBNState *s)
+{
+    return ot_otbn_proxy_get_status(s->proxy) == OT_OTBN_STATUS_LOCKED;
+}
+
+static void ot_otbn_update_irq(OtOTBNState *s)
+{
+    bool level = s->intr_state & s->intr_enable & INTR_DONE_MASK;
+    trace_ot_otbn_irq(s->ot_id, s->intr_state, s->intr_enable, level);
+    ibex_irq_set(&s->irq_done, level);
+}
+
+static void ot_otbn_update_alert(OtOTBNState *s)
+{
+    uint32_t levels = s->alert_test;
+
+    uint16_t recov_err_bits = (uint16_t)s->errbits;
+    if (recov_err_bits) {
+        levels |= 1u << ALERT_RECOVERABLE;
+    }
+
+    uint16_t fatal_err_bits = (uint16_t)(s->errbits >> 16u);
+    if (fatal_err_bits) {
+        levels |= 1u << ALERT_FATAL;
+    }
+
+    for (unsigned ix = 0u; ix < ALERT_COUNT; ix++) {
+        int level = (int)((levels >> ix) & 0x1u);
+        if (level != ibex_irq_get_level(&s->alerts[ix])) {
+            trace_ot_otbn_update_alert(s->ot_id,
+                                       ibex_irq_get_level(&s->alerts[ix]),
+                                       level);
+        }
+        ibex_irq_set(&s->alerts[ix], level);
+    }
+
+    if (!s->alert_test && !recov_err_bits) {
+        return;
+    }
+    /* ALERT_TEST and recoverable error alerts are transient */
+    s->alert_test = 0u;
+    s->errbits &= ~UINT16_MAX;
+    levels = fatal_err_bits ? (1u << ALERT_FATAL) : 0u;
+
+    for (unsigned ix = 0u; ix < ALERT_COUNT; ix++) {
+        int level = (int)((levels >> ix) & 0x1u);
+        if (level != ibex_irq_get_level(&s->alerts[ix])) {
+            trace_ot_otbn_update_alert(s->ot_id,
+                                       ibex_irq_get_level(&s->alerts[ix]),
+                                       level);
+        }
+        ibex_irq_set(&s->alerts[ix], level);
+    }
+}
+
+static void ot_otbn_post_execute(void *opaque)
+{
+    OtOTBNState *s = OT_OTBN(opaque);
+
+    s->errbits = ot_otbn_proxy_get_err_bits(s->proxy);
+    uint32_t insncount = ot_otbn_proxy_get_instruction_count(s->proxy);
+    trace_ot_otbn_post_execute(s->ot_id, s->errbits, insncount);
+    s->intr_state |= INTR_DONE_MASK;
+    ot_otbn_proxy_acknowledge_execution(s->proxy);
+    ot_otbn_update_alert(s);
+    ot_otbn_update_irq(s);
+    ibex_irq_set(&s->clock_active, false);
+}
+
+static void ot_otbn_signal_on_completion(void *opaque)
+{
+    OtOTBNState *s = OT_OTBN(opaque);
+
+    qemu_bh_schedule(s->proxy_completion_bh);
+}
+
+static void ot_otbn_trigger_entropy_req(void *opaque)
+{
+    OtOTBNRandom *r = (OtOTBNRandom *)opaque;
+
+    /* sanity check */
+    unsigned slot = (unsigned)(uintptr_t)(r - &r->otbn->rnds[0]);
+    trace_ot_otbn_proxy_entropy_request(r->otbn->ot_id, slot);
+
+    switch (slot) {
+    case OT_OTBN_URND:
+    case OT_OTBN_RND:
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+
+    qemu_bh_schedule(r->proxy_entropy_req_bh);
+}
+
+static void ot_otbn_proxy_completion_bh(void *opaque)
+{
+    OtOTBNState *s = opaque;
+
+    enum OtOTBNCommand last_cmd = s->last_cmd;
+    s->last_cmd = OT_OTBN_CMD_NONE;
+
+    trace_ot_otbn_proxy_completion_bh(s->ot_id, last_cmd);
+
+    switch (last_cmd) {
+    case OT_OTBN_CMD_EXECUTE:
+    case OT_OTBN_CMD_SEC_WIPE_DMEM:
+    case OT_OTBN_CMD_SEC_WIDE_IMEM:
+        if (s->proxy_defer) {
+            /*
+             * timer is used to simulate a delayed processing, which maybe
+             * useful to pass some test suites such as OT smoketest wait 100
+             * microsecs so that the virtual hart can be scheduled and may poll
+             * the status register before the actual completion is signalled
+             * from the OTBN working thread.
+             */
+            timer_del(s->proxy_defer);
+            timer_mod(s->proxy_defer,
+                      qemu_clock_get_us(OT_VIRTUAL_CLOCK) + 100u);
+        } else {
+            ot_otbn_post_execute(s);
+        }
+        break;
+    case OT_OTBN_CMD_NONE:
+    default:
+        break;
+    }
+}
+
+static void ot_otbn_fill_entropy(void *opaque, uint32_t bits, bool fips)
+{
+    OtOTBNRandom *rnd = opaque;
+    OtOTBNState *s = rnd->otbn;
+
+    if (!rnd->entropy_requested) {
+        /* entropy not expected, may occur on reset */
+        trace_ot_otbn_error(s->ot_id, "received unexpected entropy");
+        return;
+    }
+
+    if (ot_fifo32_is_full(&rnd->packer)) {
+        /* too many entropy bits, internal error */
+        trace_ot_otbn_error(s->ot_id, "received too many entropy");
+        return;
+    }
+
+    ot_fifo32_push(&rnd->packer, bits);
+    rnd->no_fips |= !fips;
+    rnd->entropy_requested = false;
+
+    if (!ot_fifo32_is_full(&rnd->packer)) {
+        /* need more entropy to fill in the packer */
+        ot_otbn_request_entropy(rnd);
+        return;
+    }
+
+    /* packer is ready to inject data into the OTBN */
+    uint32_t num = 0;
+    const uint32_t *buf;
+    buf = ot_fifo32_pop_buf(&rnd->packer, OT_OTBN_RANDOM_WORD_COUNT, &num);
+    const uint8_t *buf8 = (const uint8_t *)buf;
+    g_assert(num == OT_OTBN_RANDOM_WORD_COUNT);
+    num *= sizeof(uint32_t);
+    g_assert(s != NULL);
+    unsigned rnd_ix = (unsigned)(rnd - &s->rnds[0]);
+    bool res;
+    switch (rnd_ix) {
+    case OT_OTBN_URND:
+        trace_ot_otbn_proxy_push_entropy(s->ot_id, "urnd", !rnd->no_fips);
+        res = ot_otbn_proxy_push_entropy(s->proxy, rnd_ix, buf8, num,
+                                         !rnd->no_fips);
+        break;
+    case OT_OTBN_RND:
+        trace_ot_otbn_proxy_push_entropy(s->ot_id, "rnd", !rnd->no_fips);
+        res = ot_otbn_proxy_push_entropy(s->proxy, rnd_ix, buf8, num,
+                                         !rnd->no_fips);
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+    ot_fifo32_reset(&rnd->packer);
+    rnd->no_fips = false;
+    if (!res) {
+        trace_ot_otbn_error(s->ot_id, "cannot push entropy");
+    }
+}
+
+static void ot_otbn_request_entropy(OtOTBNRandom *rnd)
+{
+    if (!rnd->connected) {
+        ot_edn_connect_endpoint(rnd->device, rnd->ep, &ot_otbn_fill_entropy,
+                                rnd);
+        rnd->connected = true;
+    }
+
+    if (rnd->entropy_requested) {
+        /* another request is already ongoing */
+        return;
+    }
+
+    OtOTBNState *s = rnd->otbn;
+
+    rnd->entropy_requested = true;
+    trace_ot_otbn_request_entropy(s->ot_id, rnd->ep);
+    if (ot_edn_request_entropy(rnd->device, rnd->ep)) {
+        trace_ot_otbn_error(s->ot_id, "failed to request entropy");
+        rnd->entropy_requested = false;
+    }
+}
+
+static void ot_otbn_proxy_entropy_req_bh(void *opaque)
+{
+    /* BH triggered from the proxy */
+    ot_otbn_request_entropy((OtOTBNRandom *)opaque);
+}
+
+static void ot_otbn_handle_command(OtOTBNState *s, unsigned command)
+{
+    /* "Writes are ignored if OTBN is not idle" */
+    if (!ot_otbn_is_idle(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: cannot execute cmd %02X from a not IDLE state\n",
+                      __func__, s->ot_id, command);
+        return;
+    }
+
+    if (s->last_cmd != OT_OTBN_CMD_NONE) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: previous command %02X did not complete\n",
+                      __func__, s->ot_id, s->last_cmd);
+        return;
+    }
+
+    ibex_irq_set(&s->clock_active, true);
+
+    switch (command) {
+    case (unsigned)OT_OTBN_CMD_EXECUTE:
+        s->last_cmd = command;
+        ot_otbn_proxy_execute(s->proxy, false);
+        break;
+    case (unsigned)OT_OTBN_CMD_SEC_WIPE_DMEM:
+        s->last_cmd = command;
+        ot_otbn_proxy_wipe_memory(s->proxy, false);
+        break;
+    case (unsigned)OT_OTBN_CMD_SEC_WIDE_IMEM:
+        s->last_cmd = command;
+        ot_otbn_proxy_wipe_memory(s->proxy, true);
+        break;
+    default:
+        ibex_irq_set(&s->clock_active, false);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Invalid command %02X\n",
+                      __func__, s->ot_id, s->last_cmd);
+        break;
+    }
+}
+
+static void ot_otbn_clock_input(void *opaque, int irq, int level)
+{
+    OtOTBNState *s = opaque;
+
+    g_assert(irq == 0);
+
+    s->pclk = (unsigned)level;
+
+    /* TODO: disable OTBN execution when PCLK is 0 */
+}
+
+static void ot_otbn_push_key(OtKeySinkIf *ifd, const uint8_t *share0,
+                             const uint8_t *share1, size_t key_len, bool valid)
+{
+    g_assert(!key_len || key_len == OT_OTBN_KEY_SIZE);
+
+    OtOTBNState *s = OT_OTBN(ifd);
+    static const uint8_t empty_share[OT_OTBN_KEY_SIZE] = { 0 };
+
+    if (!key_len || !share0) {
+        key_len = sizeof(empty_share);
+        share0 = empty_share;
+    }
+    if (!key_len || !share1) {
+        key_len = sizeof(empty_share);
+        share1 = empty_share;
+    }
+
+    TRACE_OTBN("%s: share0 %s, valid: %u", s->ot_id,
+               ot_otbn_hexdump(s, share0, OT_OTBN_KEY_SIZE), valid);
+
+    bool res = ot_otbn_proxy_push_key(s->proxy, share0, share1, key_len, valid);
+    if (!res) {
+        trace_ot_otbn_error(s->ot_id, "Cannot push sideload key");
+    }
+}
+
+static uint64_t ot_otbn_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtOTBNState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    uint32_t pc = ibex_get_current_pc();
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 = s->intr_state;
+        break;
+    case R_INTR_ENABLE:
+        val32 = s->intr_enable;
+        break;
+    case R_CTRL:
+        val32 = (uint32_t)ot_otbn_proxy_get_ctrl(s->proxy);
+        break;
+    case R_STATUS:
+        val32 = ot_otbn_proxy_get_status(s->proxy);
+        break;
+    case R_ERR_BITS:
+        val32 = ot_otbn_proxy_get_err_bits(s->proxy);
+        break;
+    case R_FATAL_ALERT_CAUSE:
+        val32 = s->errbits >> 16u;
+        break;
+    case R_INSN_CNT:
+        val32 = ot_otbn_proxy_get_instruction_count(s->proxy);
+        break;
+    case R_LOAD_CHECKSUM:
+        val32 = s->load_checksum;
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+    case R_CMD:
+        val32 = 0;
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s is write only\n", __func__,
+                      s->ot_id, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    trace_ot_otbn_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                              pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_otbn_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                               unsigned size)
+{
+    OtOTBNState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_otbn_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    if (ot_otbn_is_locked(s)) {
+        trace_ot_otbn_deny(s->ot_id, pc, "write denied: locked");
+        return;
+    }
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_DONE_MASK;
+        s->intr_state &= ~val32; /* RW1C */
+        ot_otbn_update_irq(s);
+        break;
+    case R_INTR_ENABLE:
+        s->intr_enable = val32 & INTR_DONE_MASK;
+        ot_otbn_update_irq(s);
+        break;
+    case R_INTR_TEST:
+        if (val32 & INTR_DONE_MASK) {
+            s->intr_state |= val32 & INTR_DONE_MASK;
+            ot_otbn_update_irq(s);
+        }
+        break;
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_MASK | R_ALERT_TEST_RECOVERY_MASK;
+        s->alert_test |= val32;
+        ot_otbn_update_alert(s);
+        break;
+    case R_CMD:
+        val32 &= R_CMD_CMD_MASK;
+        ot_otbn_handle_command(s, (unsigned)val32);
+        break;
+    case R_CTRL:
+        val32 &= R_CTRL_SW_ERRS_FATAL_MASK;
+        ot_otbn_proxy_set_ctrl(s->proxy, (bool)val32);
+        ot_otbn_update_alert(s);
+        break;
+    case R_ERR_BITS:
+        ot_otbn_proxy_set_err_bits(s->proxy, val32);
+        break;
+    case R_INSN_CNT:
+        ot_otbn_proxy_set_instruction_count(s->proxy, val32);
+        break;
+    case R_LOAD_CHECKSUM:
+        s->load_checksum = val32;
+        break;
+    case R_STATUS:
+    case R_FATAL_ALERT_CAUSE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s is read only\n", __func__,
+                      s->ot_id, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static void ot_otbn_update_checksum(OtOTBNState *s, bool doi, uint32_t addr,
+                                    uint32_t value)
+{
+    uint8_t buf[6];
+
+    stw_le_p(&buf[4], addr >> 2U);
+    buf[5] |= doi ? 0x80u : 0x00u;
+    stl_le_p(&buf[0], value);
+
+    s->load_checksum = crc32(s->load_checksum, buf, sizeof(buf));
+}
+
+static uint32_t ot_otbn_mem_read(OtOTBNState *s, bool doi, hwaddr addr)
+{
+    uint32_t value = ot_otbn_proxy_read_memory(s->proxy, doi, addr);
+    trace_ot_otbn_mem_read(s->ot_id, doi ? 'I' : 'D', (uint32_t)addr, value);
+    return value;
+}
+
+static void ot_otbn_mem_write(OtOTBNState *s, bool doi, hwaddr addr,
+                              uint32_t value)
+{
+    bool written = ot_otbn_proxy_write_memory(s->proxy, doi, addr, value);
+    trace_ot_otbn_mem_write(s->ot_id, doi ? 'I' : 'D', (uint32_t)addr, value,
+                            written ? "" : " FAILED");
+    if (written) {
+        ot_otbn_update_checksum(s, doi, addr, value);
+    }
+}
+
+static inline uint64_t
+ot_otbn_imem_read(void *opaque, hwaddr addr, unsigned size)
+{
+    (void)size;
+
+    return (uint64_t)ot_otbn_mem_read((OtOTBNState *)opaque, true, addr);
+}
+
+static inline void ot_otbn_imem_write(void *opaque, hwaddr addr, uint64_t val64,
+                                      unsigned size)
+{
+    (void)size;
+
+    return ot_otbn_mem_write((OtOTBNState *)opaque, true, addr,
+                             (uint32_t)val64);
+}
+
+static inline uint64_t
+ot_otbn_dmem_read(void *opaque, hwaddr addr, unsigned size)
+{
+    (void)size;
+
+    return (uint64_t)ot_otbn_mem_read((OtOTBNState *)opaque, false, addr);
+}
+
+static inline void ot_otbn_dmem_write(void *opaque, hwaddr addr, uint64_t val64,
+                                      unsigned size)
+{
+    (void)size;
+
+    return ot_otbn_mem_write((OtOTBNState *)opaque, false, addr,
+                             (uint32_t)val64);
+}
+
+static const Property ot_otbn_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtOTBNState, ot_id),
+    DEFINE_PROP_STRING("clock-name", OtOTBNState, clock_name),
+    DEFINE_PROP_LINK("clock-src", OtOTBNState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+    DEFINE_PROP_LINK("edn-u", OtOTBNState, rnds[OT_OTBN_URND].device,
+                     TYPE_OT_EDN, OtEDNState *),
+    DEFINE_PROP_LINK("edn-r", OtOTBNState, rnds[OT_OTBN_RND].device,
+                     TYPE_OT_EDN, OtEDNState *),
+    DEFINE_PROP_UINT8("edn-u-ep", OtOTBNState, rnds[OT_OTBN_URND].ep,
+                      UINT8_MAX),
+    DEFINE_PROP_UINT8("edn-r-ep", OtOTBNState, rnds[OT_OTBN_RND].ep, UINT8_MAX),
+    DEFINE_PROP_STRING("logfile", OtOTBNState, log_file),
+    DEFINE_PROP_BOOL("logasm", OtOTBNState, log_asm, false),
+};
+
+static const MemoryRegionOps ot_otbn_regs_ops = {
+    .read = &ot_otbn_regs_read,
+    .write = &ot_otbn_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_otbn_imem_ops = {
+    .read = &ot_otbn_imem_read,
+    .write = &ot_otbn_imem_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_otbn_dmem_ops = {
+    .read = &ot_otbn_dmem_read,
+    .write = &ot_otbn_dmem_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_otbn_reset_enter(Object *obj, ResetType type)
+{
+    OtOTBNClass *c = OT_OTBN_GET_CLASS(obj);
+    OtOTBNState *s = OT_OTBN(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->proxy_defer);
+
+    s->intr_state = 0;
+    s->intr_enable = 0;
+    s->intr_test = 0;
+    s->alert_test = 0;
+    s->errbits = 0;
+    s->load_checksum = 0;
+
+    s->last_cmd = OT_OTBN_CMD_NONE;
+    ibex_irq_set(&s->irq_done, 0);
+    for (unsigned ix = 0; ix < ALERT_COUNT; ix++) {
+        ibex_irq_set(&s->alerts[ix], 0);
+    }
+
+    for (unsigned rix = 0; rix < (unsigned)OT_OTBN_RND_COUNT; rix++) {
+        OtOTBNRandom *rnd = &s->rnds[rix];
+        rnd->otbn = s;
+        rnd->no_fips = false;
+        rnd->entropy_requested = false;
+        ot_fifo32_reset(&rnd->packer);
+    }
+
+    if (!s->clock_src_name) {
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_name =
+            ic->get_clock_source(ii, s->clock_name, DEVICE(s), &error_fatal);
+        qemu_irq in_irq =
+            qdev_get_gpio_in_named(DEVICE(s), OT_OTBN_CLOCK_INPUT, 0);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_name, 0, in_irq);
+
+        if (object_dynamic_cast(OBJECT(s->clock_src), TYPE_OT_CLKMGR)) {
+            char *hint_name =
+                g_strdup_printf(OT_CLOCK_HINT_PREFIX "%s", s->clock_name);
+            qemu_irq hint_irq =
+                qdev_get_gpio_in_named(s->clock_src, hint_name, 0);
+            g_assert(hint_irq);
+            qdev_connect_gpio_out_named(DEVICE(s), OT_OTBN_CLOCK_ACTIVE, 0,
+                                        hint_irq);
+            g_free(hint_name);
+        }
+    }
+}
+
+static void ot_otbn_reset_exit(Object *obj, ResetType type)
+{
+    OtOTBNClass *c = OT_OTBN_GET_CLASS(obj);
+    OtOTBNState *s = OT_OTBN(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    if (!s->log_file) {
+        s->log_asm = false;
+    }
+
+    ot_otbn_proxy_start(s->proxy, false, s->log_file, s->log_asm);
+}
+
+static void ot_otbn_realize(DeviceState *dev, Error **errp)
+{
+    (void)errp;
+
+    OtOTBNState *s = OT_OTBN(dev);
+    g_assert(s->ot_id);
+    g_assert(s->clock_name);
+    g_assert(s->clock_src);
+
+    g_assert(s->rnds[OT_OTBN_URND].device);
+    g_assert(s->rnds[OT_OTBN_RND].device);
+    g_assert(s->rnds[OT_OTBN_URND].ep != UINT8_MAX);
+    g_assert(s->rnds[OT_OTBN_RND].ep != UINT8_MAX);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_otbn_clock_input,
+                            OT_OTBN_CLOCK_INPUT, 1);
+}
+
+static void ot_otbn_init(Object *obj)
+{
+    OtOTBNState *s = OT_OTBN(obj);
+
+    memory_region_init(&s->mmio, obj, TYPE_OT_OTBN, 0x10000u);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    memory_region_init_io(&s->regs, obj, &ot_otbn_regs_ops, s,
+                          TYPE_OT_OTBN ".regs", REGS_SIZE);
+    memory_region_add_subregion(&s->mmio, OT_OTBN_REGS_BASE, &s->regs);
+
+    /*
+     * IMEM cannot be defined as a RAM region since accesses need to be
+     * controlled and checksum to be computed in-order
+     */
+    memory_region_init_io(&s->imem, obj, &ot_otbn_imem_ops, s,
+                          TYPE_OT_OTBN ".imem", OT_OTBN_IMEM_SIZE);
+    memory_region_add_subregion(&s->mmio, OT_OTBN_IMEM_BASE, &s->imem);
+
+    /*
+     * DMEM cannot be defined as a RAM region since accesses need to be
+     * controlled and checksum to be computed in-order
+     */
+    memory_region_init_io(&s->dmem, obj, &ot_otbn_dmem_ops, s,
+                          TYPE_OT_OTBN ".dmem", OT_OTBN_DMEM_SIZE);
+    memory_region_add_subregion(&s->mmio, OT_OTBN_DMEM_BASE, &s->dmem);
+
+    ibex_sysbus_init_irq(obj, &s->irq_done);
+    ibex_qdev_init_irqs(obj, s->alerts, OT_DEVICE_ALERT, ALERT_COUNT);
+    ibex_qdev_init_irq(obj, &s->clock_active, OT_OTBN_CLOCK_ACTIVE);
+
+    for (unsigned rix = 0; rix < (unsigned)OT_OTBN_RND_COUNT; rix++) {
+        OtOTBNRandom *r = &s->rnds[rix];
+        r->proxy_entropy_req_bh = qemu_bh_new(&ot_otbn_proxy_entropy_req_bh, r);
+        ot_fifo32_create(&r->packer, OT_OTBN_RANDOM_WORD_COUNT);
+    }
+
+    s->proxy_completion_bh = qemu_bh_new(&ot_otbn_proxy_completion_bh, s);
+    s->proxy_defer = timer_new_us(OT_VIRTUAL_CLOCK, &ot_otbn_post_execute, s);
+    s->proxy =
+        ot_otbn_proxy_new(&ot_otbn_trigger_entropy_req, &s->rnds[OT_OTBN_URND],
+                          &ot_otbn_trigger_entropy_req, &s->rnds[OT_OTBN_RND],
+                          &ot_otbn_signal_on_completion, s);
+
+#ifdef OT_OTBN_DEBUG
+    s->hexstr = g_new0(char, OT_OTBN_HEXSTR_SIZE);
+#endif
+}
+
+static void ot_otbn_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_otbn_realize;
+    device_class_set_props(dc, ot_otbn_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtOTBNClass *oc = OT_OTBN_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_otbn_reset_enter, NULL,
+                                       &ot_otbn_reset_exit, &oc->parent_phases);
+
+    OtKeySinkIfClass *kc = OT_KEY_SINK_IF_CLASS(klass);
+    kc->push_key = &ot_otbn_push_key;
+}
+
+static const TypeInfo ot_otbn_info = {
+    .name = TYPE_OT_OTBN,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtOTBNState),
+    .instance_init = &ot_otbn_init,
+    .class_size = sizeof(OtOTBNClass),
+    .class_init = &ot_otbn_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_OT_KEY_SINK_IF },
+            {},
+        },
+};
+
+static void ot_otbn_register_types(void)
+{
+    type_register_static(&ot_otbn_info);
+}
+
+type_init(ot_otbn_register_types);
diff --git a/hw/opentitan/ot_otp_be_if.c b/hw/opentitan/ot_otp_be_if.c
new file mode 100644
index 0000000000000..38f89442ee775
--- /dev/null
+++ b/hw/opentitan/ot_otp_be_if.c
@@ -0,0 +1,42 @@
+/*
+ * QEMU OpenTitan OTP backend interface
+ *
+ * Copyright (c) 2024 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/opentitan/ot_otp_be_if.h"
+
+static const TypeInfo ot_otp_be_info = {
+    .name = TYPE_OT_OTP_BE_IF,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(OtOtpBeIfClass),
+};
+
+static void ot_otp_be_register_types(void)
+{
+    type_register_static(&ot_otp_be_info);
+}
+
+type_init(ot_otp_be_register_types);
diff --git a/hw/opentitan/ot_otp_dj.c b/hw/opentitan/ot_otp_dj.c
new file mode 100644
index 0000000000000..e1c9f231a7b31
--- /dev/null
+++ b/hw/opentitan/ot_otp_dj.c
@@ -0,0 +1,1342 @@
+/*
+ * QEMU OpenTitan Darjeeling One Time Programmable (OTP) implementation
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Based on OpenTitan 5fe6fe8605
+ */
+
+#define OT_OTP_COMPORTABLE_REGS
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "hw/opentitan/ot_otp_dj.h"
+#include "hw/opentitan/ot_otp_engine.h"
+#include "hw/opentitan/ot_otp_impl_if.h"
+#include "trace.h"
+
+#define NUM_ERROR_ENTRIES       24u
+#define NUM_PART                22u
+#define NUM_PART_BUF            7u
+#define NUM_PART_UNBUF          15u
+#define NUM_SRAM_KEY_REQ_SLOTS  4u
+#define NUM_SW_CFG_WINDOW_WORDS 4096u
+
+#define OTP_BYTE_ADDR_WIDTH 14u
+
+/* clang-format off */
+/* Core registers */
+REG32(STATUS, 0x010u)
+    FIELD(STATUS, VENDOR_TEST_ERROR, 0u, 1u)
+    FIELD(STATUS, CREATOR_SW_CFG_ERROR, 1u, 1u)
+    FIELD(STATUS, OWNER_SW_CFG_ERROR, 2u, 1u)
+    FIELD(STATUS, OWNERSHIP_SLOT_STATE_ERROR, 3u, 1u)
+    FIELD(STATUS, ROT_CREATOR_AUTH_ERROR, 4u, 1u)
+    FIELD(STATUS, ROT_OWNER_AUTH_SLOT0_ERROR, 5u, 1u)
+    FIELD(STATUS, ROT_OWNER_AUTH_SLOT1_ERROR, 6u, 1u)
+    FIELD(STATUS, PLAT_INTEG_AUTH_SLOT0_ERROR, 7u, 1u)
+    FIELD(STATUS, PLAT_INTEG_AUTH_SLOT1_ERROR, 8u, 1u)
+    FIELD(STATUS, PLAT_OWNER_AUTH_SLOT0_ERROR, 9u, 1u)
+    FIELD(STATUS, PLAT_OWNER_AUTH_SLOT1_ERROR, 10u, 1u)
+    FIELD(STATUS, PLAT_OWNER_AUTH_SLOT2_ERROR, 11u, 1u)
+    FIELD(STATUS, PLAT_OWNER_AUTH_SLOT3_ERROR, 12u, 1u)
+    FIELD(STATUS, EXT_NVM_ERROR, 13u, 1u)
+    FIELD(STATUS, ROM_PATCH_ERROR, 14u, 1u)
+    FIELD(STATUS, HW_CFG0_ERROR, 15u, 1u)
+    FIELD(STATUS, HW_CFG1_ERROR, 16u, 1u)
+    FIELD(STATUS, SECRET0_ERROR, 17u, 1u)
+    FIELD(STATUS, SECRET1_ERROR, 18u, 1u)
+    FIELD(STATUS, SECRET2_ERROR, 19u, 1u)
+    FIELD(STATUS, SECRET3_ERROR, 20u, 1u)
+    FIELD(STATUS, LIFE_CYCLE_ERROR, 21u, 1u)
+    FIELD(STATUS, DAI_ERROR, 22u, 1u)
+    FIELD(STATUS, LCI_ERROR, 23u, 1u)
+    FIELD(STATUS, TIMEOUT_ERROR, 24u, 1u)
+    FIELD(STATUS, LFSR_FSM_ERROR, 25u, 1u)
+    FIELD(STATUS, SCRAMBLING_FSM_ERROR, 26u, 1u)
+    FIELD(STATUS, KEY_DERIV_FSM_ERROR, 27u, 1u)
+    FIELD(STATUS, BUS_INTEG_ERROR, 28u, 1u)
+    FIELD(STATUS, DAI_IDLE, 29u, 1u)
+    FIELD(STATUS, CHECK_PENDING, 30u, 1u)
+REG32(ERR_CODE_0, 0x014u)
+REG32(ERR_CODE_1, 0x018u)
+REG32(ERR_CODE_2, 0x01cu)
+REG32(ERR_CODE_3, 0x020u)
+REG32(ERR_CODE_4, 0x024u)
+REG32(ERR_CODE_5, 0x028u)
+REG32(ERR_CODE_6, 0x02cu)
+REG32(ERR_CODE_7, 0x030u)
+REG32(ERR_CODE_8, 0x034u)
+REG32(ERR_CODE_9, 0x038u)
+REG32(ERR_CODE_10, 0x03cu)
+REG32(ERR_CODE_11, 0x040u)
+REG32(ERR_CODE_12, 0x044u)
+REG32(ERR_CODE_13, 0x048u)
+REG32(ERR_CODE_14, 0x04cu)
+REG32(ERR_CODE_15, 0x050u)
+REG32(ERR_CODE_16, 0x054u)
+REG32(ERR_CODE_17, 0x058u)
+REG32(ERR_CODE_18, 0x05cu)
+REG32(ERR_CODE_19, 0x060u)
+REG32(ERR_CODE_20, 0x064u)
+REG32(ERR_CODE_21, 0x068u)
+REG32(ERR_CODE_22, 0x06cu)
+REG32(ERR_CODE_23, 0x070u)
+REG32(DIRECT_ACCESS_REGWEN, 0x074u)
+    FIELD(DIRECT_ACCESS_REGWEN, REGWEN, 0u, 1u)
+REG32(DIRECT_ACCESS_CMD, 0x078u)
+REG32(DIRECT_ACCESS_ADDRESS, 0x07cu)
+    FIELD(DIRECT_ACCESS_ADDRESS, ADDRESS, 0u, 14u)
+REG32(DIRECT_ACCESS_WDATA_0, 0x080u)
+REG32(DIRECT_ACCESS_WDATA_1, 0x084u)
+REG32(DIRECT_ACCESS_RDATA_0, 0x088u)
+REG32(DIRECT_ACCESS_RDATA_1, 0x08cu)
+REG32(CHECK_TRIGGER_REGWEN, 0x090u)
+    FIELD(CHECK_TRIGGER_REGWEN, REGWEN, 0u, 1u)
+REG32(CHECK_TRIGGER, 0x094u)
+    FIELD(CHECK_TRIGGER, INTEGRITY, 0u, 1u)
+    FIELD(CHECK_TRIGGER, CONSISTENCY, 1u, 1u)
+REG32(CHECK_REGWEN, 0x098u)
+    FIELD(CHECK_REGWEN, REGWEN, 0u, 1u)
+REG32(CHECK_TIMEOUT, 0x09cu)
+REG32(INTEGRITY_CHECK_PERIOD, 0x0a0u)
+REG32(CONSISTENCY_CHECK_PERIOD, 0x0a4u)
+REG32(VENDOR_TEST_READ_LOCK, 0x0a8u)
+REG32(CREATOR_SW_CFG_READ_LOCK, 0x0acu)
+REG32(OWNER_SW_CFG_READ_LOCK, 0x0b0u)
+REG32(OWNERSHIP_SLOT_STATE_READ_LOCK, 0x0b4u)
+REG32(ROT_CREATOR_AUTH_READ_LOCK, 0x0b8u)
+REG32(ROT_OWNER_AUTH_SLOT0_READ_LOCK, 0x0bcu)
+REG32(ROT_OWNER_AUTH_SLOT1_READ_LOCK, 0x0c0u)
+REG32(PLAT_INTEG_AUTH_SLOT0_READ_LOCK, 0x0c4u)
+REG32(PLAT_INTEG_AUTH_SLOT1_READ_LOCK, 0x0c8u)
+REG32(PLAT_OWNER_AUTH_SLOT0_READ_LOCK, 0x0ccu)
+REG32(PLAT_OWNER_AUTH_SLOT1_READ_LOCK, 0x0d0u)
+REG32(PLAT_OWNER_AUTH_SLOT2_READ_LOCK, 0x0d4u)
+REG32(PLAT_OWNER_AUTH_SLOT3_READ_LOCK, 0x0d8u)
+REG32(EXT_NVM_READ_LOCK, 0x0dcu)
+REG32(ROM_PATCH_READ_LOCK, 0x0e0u)
+REG32(VENDOR_TEST_DIGEST_0, 0x0e4u)
+REG32(VENDOR_TEST_DIGEST_1, 0x0e8u)
+REG32(CREATOR_SW_CFG_DIGEST_0, 0x0ecu)
+REG32(CREATOR_SW_CFG_DIGEST_1, 0x0f0u)
+REG32(OWNER_SW_CFG_DIGEST_0, 0x0f4u)
+REG32(OWNER_SW_CFG_DIGEST_1, 0x0f8u)
+REG32(ROT_CREATOR_AUTH_DIGEST_0, 0x0fcu)
+REG32(ROT_CREATOR_AUTH_DIGEST_1, 0x100u)
+REG32(ROT_OWNER_AUTH_SLOT0_DIGEST_0, 0x104u)
+REG32(ROT_OWNER_AUTH_SLOT0_DIGEST_1, 0x108u)
+REG32(ROT_OWNER_AUTH_SLOT1_DIGEST_0, 0x10cu)
+REG32(ROT_OWNER_AUTH_SLOT1_DIGEST_1, 0x110u)
+REG32(PLAT_INTEG_AUTH_SLOT0_DIGEST_0, 0x114u)
+REG32(PLAT_INTEG_AUTH_SLOT0_DIGEST_1, 0x118u)
+REG32(PLAT_INTEG_AUTH_SLOT1_DIGEST_0, 0x11cu)
+REG32(PLAT_INTEG_AUTH_SLOT1_DIGEST_1, 0x120u)
+REG32(PLAT_OWNER_AUTH_SLOT0_DIGEST_0, 0x124u)
+REG32(PLAT_OWNER_AUTH_SLOT0_DIGEST_1, 0x128u)
+REG32(PLAT_OWNER_AUTH_SLOT1_DIGEST_0, 0x12cu)
+REG32(PLAT_OWNER_AUTH_SLOT1_DIGEST_1, 0x130u)
+REG32(PLAT_OWNER_AUTH_SLOT2_DIGEST_0, 0x134u)
+REG32(PLAT_OWNER_AUTH_SLOT2_DIGEST_1, 0x138u)
+REG32(PLAT_OWNER_AUTH_SLOT3_DIGEST_0, 0x13cu)
+REG32(PLAT_OWNER_AUTH_SLOT3_DIGEST_1, 0x140u)
+REG32(ROM_PATCH_DIGEST_0, 0x144u)
+REG32(ROM_PATCH_DIGEST_1, 0x148u)
+REG32(HW_CFG0_DIGEST_0, 0x14cu)
+REG32(HW_CFG0_DIGEST_1, 0x150u)
+REG32(HW_CFG1_DIGEST_0, 0x154u)
+REG32(HW_CFG1_DIGEST_1, 0x158u)
+REG32(SECRET0_DIGEST_0, 0x15cu)
+REG32(SECRET0_DIGEST_1, 0x160u)
+REG32(SECRET1_DIGEST_0, 0x164u)
+REG32(SECRET1_DIGEST_1, 0x168u)
+REG32(SECRET2_DIGEST_0, 0x16cu)
+REG32(SECRET2_DIGEST_1, 0x170u)
+REG32(SECRET3_DIGEST_0, 0x174u)
+REG32(SECRET3_DIGEST_1, 0x178u)
+
+/* Software Config Window registers (at offset SW_CFG_WINDOW_OFFSET) */
+REG32(VENDOR_TEST_SCRATCH, 0u)
+REG32(VENDOR_TEST_DIGEST, 56u)
+REG32(CREATOR_SW_CFG_AST_CFG, 64u)
+REG32(CREATOR_SW_CFG_AST_INIT_EN, 188u)
+REG32(CREATOR_SW_CFG_OVERRIDES, 192u)
+REG32(CREATOR_SW_CFG_ROM_EXT_SKU, 224u)
+REG32(CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN, 228u)
+REG32(CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN, 232u)
+REG32(CREATOR_SW_CFG_SIGVERIFY_SPX_EN, 240u)
+REG32(CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN, 244u)
+REG32(CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG, 252u)
+REG32(CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG, 256u)
+REG32(CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE, 260u)
+REG32(CREATOR_SW_CFG_RNG_EN, 264u)
+REG32(CREATOR_SW_CFG_JITTER_EN, 268u)
+REG32(CREATOR_SW_CFG_RET_RAM_RESET_MASK, 272u)
+REG32(CREATOR_SW_CFG_MANUF_STATE, 276u)
+REG32(CREATOR_SW_CFG_ROM_EXEC_EN, 280u)
+REG32(CREATOR_SW_CFG_CPUCTRL, 284u)
+REG32(CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT, 288u)
+REG32(CREATOR_SW_CFG_MIN_SEC_VER_BL0, 292u)
+REG32(CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN, 296u)
+REG32(CREATOR_SW_CFG_RMA_SPIN_EN, 300u)
+REG32(CREATOR_SW_CFG_RMA_SPIN_CYCLES, 304u)
+REG32(CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS, 308u)
+REG32(CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS, 312u)
+REG32(CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS, 316u)
+REG32(CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS, 320u)
+REG32(CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS, 324u)
+REG32(CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS, 328u)
+REG32(CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS, 332u)
+REG32(CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS, 336u)
+REG32(CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS, 340u)
+REG32(CREATOR_SW_CFG_RNG_ALERT_THRESHOLD, 344u)
+REG32(CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST, 348u)
+REG32(CREATOR_SW_CFG_SRAM_KEY_RENEW_EN, 352u)
+REG32(CREATOR_SW_CFG_DIGEST, 360u)
+REG32(OWNER_SW_CFG_ROM_ERROR_REPORTING, 368u)
+REG32(OWNER_SW_CFG_ROM_BOOTSTRAP_DIS, 372u)
+REG32(OWNER_SW_CFG_ROM_ALERT_CLASS_EN, 376u)
+REG32(OWNER_SW_CFG_ROM_ALERT_ESCALATION, 380u)
+REG32(OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION, 384u)
+REG32(OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION, 804u)
+REG32(OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH, 832u)
+REG32(OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES, 848u)
+REG32(OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES, 864u)
+REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD, 928u)
+REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END, 932u)
+REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV, 936u)
+REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA, 940u)
+REG32(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES, 944u)
+REG32(OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN, 948u)
+REG32(OWNER_SW_CFG_MANUF_STATE, 952u)
+REG32(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN, 956u)
+REG32(OWNER_SW_CFG_DIGEST, 960u)
+REG32(OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH, 968u)
+REG32(OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH, 984u)
+REG32(OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH, 1000u)
+REG32(ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY, 1016u)
+REG32(ROT_CREATOR_AUTH_OWNERSHIP_STATE, 1176u)
+REG32(ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY, 1180u)
+REG32(ROT_CREATOR_AUTH_KEYMANIFEST_KEY, 1340u)
+REG32(ROT_CREATOR_AUTH_UNLOCK4XFER_KEY, 1500u)
+REG32(ROT_CREATOR_AUTH_IDENTITY_CERT, 1660u)
+REG32(ROT_CREATOR_AUTH_DIGEST, 2432u)
+REG32(ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY, 2440u)
+REG32(ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY, 2600u)
+REG32(ROT_OWNER_AUTH_SLOT0_DIGEST, 2760u)
+REG32(ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY, 2768u)
+REG32(ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY, 2928u)
+REG32(ROT_OWNER_AUTH_SLOT1_DIGEST, 3088u)
+REG32(PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY, 3096u)
+REG32(PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY, 3256u)
+REG32(PLAT_INTEG_AUTH_SLOT0_DIGEST, 3416u)
+REG32(PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY, 3424u)
+REG32(PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY, 3584u)
+REG32(PLAT_INTEG_AUTH_SLOT1_DIGEST, 3744u)
+REG32(PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY, 3752u)
+REG32(PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY, 3912u)
+REG32(PLAT_OWNER_AUTH_SLOT0_DIGEST, 4072u)
+REG32(PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY, 4080u)
+REG32(PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY, 4240u)
+REG32(PLAT_OWNER_AUTH_SLOT1_DIGEST, 4400u)
+REG32(PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY, 4408u)
+REG32(PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY, 4568u)
+REG32(PLAT_OWNER_AUTH_SLOT2_DIGEST, 4728u)
+REG32(PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY, 4736u)
+REG32(PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY, 4896u)
+REG32(PLAT_OWNER_AUTH_SLOT3_DIGEST, 5056u)
+REG32(EXT_NVM_ANTIREPLAY_FRESHNESS_CNT, 5064u)
+REG32(ROM_PATCH_DATA, 6088u)
+REG32(ROM_PATCH_DIGEST, 15944u)
+REG32(HW_CFG0_DEVICE_ID, 15952u)
+REG32(HW_CFG0_MANUF_STATE, 15984u)
+REG32(HW_CFG0_DIGEST, 16016u)
+REG32(HW_CFG1_SOC_DBG_STATE, 16024u)
+REG32(HW_CFG1_EN_CSRNG_SW_APP_READ, 16028u)
+REG32(HW_CFG1_EN_SRAM_IFETCH, 16029u)
+REG32(HW_CFG1_DIGEST, 16032u)
+REG32(SECRET0_TEST_UNLOCK_TOKEN, 16040u)
+REG32(SECRET0_TEST_EXIT_TOKEN, 16056u)
+REG32(SECRET0_DIGEST, 16072u)
+REG32(SECRET0_ZER, 16080u)
+REG32(SECRET1_SRAM_DATA_KEY_SEED, 16088u)
+REG32(SECRET1_DIGEST, 16104u)
+REG32(SECRET1_ZER, 16112u)
+REG32(SECRET2_RMA_TOKEN, 16120u)
+REG32(SECRET2_CREATOR_ROOT_KEY_SHARE0, 16136u)
+REG32(SECRET2_CREATOR_ROOT_KEY_SHARE1, 16168u)
+REG32(SECRET2_CREATOR_SEED, 16200u)
+REG32(SECRET2_DIGEST, 16232u)
+REG32(SECRET2_ZER, 16240u)
+REG32(SECRET3_OWNER_SEED, 16248u)
+REG32(SECRET3_DIGEST, 16280u)
+REG32(SECRET3_ZER, 16288u)
+REG32(LC_TRANSITION_CNT, 16296u)
+REG32(LC_STATE, 16344u)
+/* clang-format on */
+
+#define VENDOR_TEST_SCRATCH_SIZE                             56u
+#define CREATOR_SW_CFG_AST_CFG_SIZE                          124u
+#define CREATOR_SW_CFG_AST_INIT_EN_SIZE                      4u
+#define CREATOR_SW_CFG_OVERRIDES_SIZE                        32u
+#define CREATOR_SW_CFG_ROM_EXT_SKU_SIZE                      4u
+#define CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN_SIZE    4u
+#define CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN_SIZE             8u
+#define CREATOR_SW_CFG_SIGVERIFY_SPX_EN_SIZE                 4u
+#define CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN_SIZE             8u
+#define CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_SIZE           4u
+#define CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_SIZE         4u
+#define CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_SIZE       4u
+#define CREATOR_SW_CFG_RNG_EN_SIZE                           4u
+#define CREATOR_SW_CFG_JITTER_EN_SIZE                        4u
+#define CREATOR_SW_CFG_RET_RAM_RESET_MASK_SIZE               4u
+#define CREATOR_SW_CFG_MANUF_STATE_SIZE                      4u
+#define CREATOR_SW_CFG_ROM_EXEC_EN_SIZE                      4u
+#define CREATOR_SW_CFG_CPUCTRL_SIZE                          4u
+#define CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_SIZE              4u
+#define CREATOR_SW_CFG_MIN_SEC_VER_BL0_SIZE                  4u
+#define CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_SIZE     4u
+#define CREATOR_SW_CFG_RMA_SPIN_EN_SIZE                      4u
+#define CREATOR_SW_CFG_RMA_SPIN_CYCLES_SIZE                  4u
+#define CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_SIZE            4u
+#define CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_SIZE           4u
+#define CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_SIZE         4u
+#define CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_SIZE         4u
+#define CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_SIZE            4u
+#define CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_SIZE         4u
+#define CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_SIZE         4u
+#define CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_SIZE          4u
+#define CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_SIZE          4u
+#define CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_SIZE              4u
+#define CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST_SIZE         4u
+#define CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_SIZE                4u
+#define OWNER_SW_CFG_ROM_ERROR_REPORTING_SIZE                4u
+#define OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_SIZE                  4u
+#define OWNER_SW_CFG_ROM_ALERT_CLASS_EN_SIZE                 4u
+#define OWNER_SW_CFG_ROM_ALERT_ESCALATION_SIZE               4u
+#define OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_SIZE           420u
+#define OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_SIZE     28u
+#define OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_SIZE             16u
+#define OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_SIZE           16u
+#define OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_SIZE             64u
+#define OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_SIZE              4u
+#define OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_SIZE          4u
+#define OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_SIZE               4u
+#define OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_SIZE               4u
+#define OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_SIZE 4u
+#define OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN_SIZE         4u
+#define OWNER_SW_CFG_MANUF_STATE_SIZE                        4u
+#define OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_SIZE                 4u
+#define OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH_SIZE             16u
+#define OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH_SIZE            16u
+#define OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH_SIZE            16u
+#define ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY_SIZE       160u
+#define ROT_CREATOR_AUTH_OWNERSHIP_STATE_SIZE                4u
+#define ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY_SIZE       160u
+#define ROT_CREATOR_AUTH_KEYMANIFEST_KEY_SIZE                160u
+#define ROT_CREATOR_AUTH_UNLOCK4XFER_KEY_SIZE                160u
+#define ROT_CREATOR_AUTH_IDENTITY_CERT_SIZE                  768u
+#define ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE            160u
+#define ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE            160u
+#define ROT_OWNER_AUTH_SLOT1_SIZE                            328u
+#define ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE            160u
+#define ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE            160u
+#define PLAT_INTEG_AUTH_SLOT0_SIZE                           328u
+#define PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE           160u
+#define PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE           160u
+#define PLAT_INTEG_AUTH_SLOT1_SIZE                           328u
+#define PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE           160u
+#define PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE           160u
+#define PLAT_OWNER_AUTH_SLOT0_SIZE                           328u
+#define PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY_SIZE           160u
+#define PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY_SIZE           160u
+#define PLAT_OWNER_AUTH_SLOT1_SIZE                           328u
+#define PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY_SIZE           160u
+#define PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY_SIZE           160u
+#define PLAT_OWNER_AUTH_SLOT2_SIZE                           328u
+#define PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY_SIZE           160u
+#define PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY_SIZE           160u
+#define PLAT_OWNER_AUTH_SLOT3_SIZE                           328u
+#define PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY_SIZE           160u
+#define PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY_SIZE           160u
+#define EXT_NVM_ANTIREPLAY_FRESHNESS_CNT_SIZE                1024u
+#define ROM_PATCH_DATA_SIZE                                  9192u
+#define HW_CFG0_DEVICE_ID_SIZE                               32u
+#define HW_CFG0_MANUF_STATE_SIZE                             32u
+#define HW_CFG1_SOC_DBG_STATE_SIZE                           4u
+#define HW_CFG1_EN_CSRNG_SW_APP_READ_SIZE                    1u
+#define HW_CFG1_EN_SRAM_IFETCH_SIZE                          1u
+#define SECRET0_TEST_UNLOCK_TOKEN_SIZE                       16u
+#define SECRET0_TEST_EXIT_TOKEN_SIZE                         16u
+#define SECRET1_SRAM_DATA_KEY_SEED_SIZE                      16u
+#define SECRET2_RMA_TOKEN_SIZE                               16u
+#define SECRET2_CREATOR_ROOT_KEY_SHARE0_SIZE                 32u
+#define SECRET2_CREATOR_ROOT_KEY_SHARE1_SIZE                 32u
+#define SECRET2_CREATOR_SEED_SIZE                            32u
+#define SECRET3_OWNER_SEED_SIZE                              32u
+
+#define SW_CFG_WINDOW_OFFSET 0x4000u
+#define SW_CFG_WINDOW_SIZE   (NUM_SW_CFG_WINDOW_WORDS * sizeof(uint32_t))
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_SECRET3_DIGEST_1)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+/* note: useless casts are required for GCC linter */
+static_assert((unsigned)R_STATUS == (unsigned)R_OTP_FIRST_IMPL_REG,
+              "Invalid register address");
+
+typedef enum {
+    OTP_PART_VENDOR_TEST,
+    OTP_PART_CREATOR_SW_CFG,
+    OTP_PART_OWNER_SW_CFG,
+    OTP_PART_OWNERSHIP_SLOT_STATE,
+    OTP_PART_ROT_CREATOR_AUTH,
+    OTP_PART_ROT_OWNER_AUTH_SLOT0,
+    OTP_PART_ROT_OWNER_AUTH_SLOT1,
+    OTP_PART_PLAT_INTEG_AUTH_SLOT0,
+    OTP_PART_PLAT_INTEG_AUTH_SLOT1,
+    OTP_PART_PLAT_OWNER_AUTH_SLOT0,
+    OTP_PART_PLAT_OWNER_AUTH_SLOT1,
+    OTP_PART_PLAT_OWNER_AUTH_SLOT2,
+    OTP_PART_PLAT_OWNER_AUTH_SLOT3,
+    OTP_PART_EXT_NVM,
+    OTP_PART_ROM_PATCH,
+    OTP_PART_HW_CFG0,
+    OTP_PART_HW_CFG1,
+    OTP_PART_SECRET0,
+    OTP_PART_SECRET1,
+    OTP_PART_SECRET2,
+    OTP_PART_SECRET3,
+    OTP_PART_LIFE_CYCLE,
+    OTP_PART_OTP_COUNT, /* count of "real" OTP partitions */
+    OTP_ENTRY_DAI = OTP_PART_OTP_COUNT, /* Fake partitions for error (...) */
+    OTP_ENTRY_KDI, /* Key derivation issue, not really OTP */
+    OTP_ENTRY_COUNT,
+} OtOTPPartitionType;
+
+static_assert(OTP_PART_OTP_COUNT == NUM_PART, "Invalid partition count");
+#define OT_OTP_DJ_PARTS
+
+/* NOLINTNEXTLINE */
+#include "ot_otp_dj_parts.c"
+
+static_assert(OTP_PART_OTP_COUNT == OTP_PART_COUNT, "Invalid partition count");
+static_assert(OTP_PART_COUNT <= 64, "Maximum part count reached");
+
+static_assert(OTP_BYTE_ADDR_WIDTH == R_DIRECT_ACCESS_ADDRESS_ADDRESS_LENGTH,
+              "OTP byte address width mismatch");
+
+struct OtOTPDjState {
+    OtOTPEngineState parent_obj;
+
+    struct {
+        MemoryRegion ctrl;
+        struct {
+            MemoryRegion regs;
+            MemoryRegion swcfg;
+        } sub;
+    } mmio;
+};
+
+struct OtOTPDjClass {
+    OtOTPEngineClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(ERR_CODE_0),
+    REG_NAME_ENTRY(ERR_CODE_1),
+    REG_NAME_ENTRY(ERR_CODE_2),
+    REG_NAME_ENTRY(ERR_CODE_3),
+    REG_NAME_ENTRY(ERR_CODE_4),
+    REG_NAME_ENTRY(ERR_CODE_5),
+    REG_NAME_ENTRY(ERR_CODE_6),
+    REG_NAME_ENTRY(ERR_CODE_7),
+    REG_NAME_ENTRY(ERR_CODE_8),
+    REG_NAME_ENTRY(ERR_CODE_9),
+    REG_NAME_ENTRY(ERR_CODE_10),
+    REG_NAME_ENTRY(ERR_CODE_11),
+    REG_NAME_ENTRY(ERR_CODE_12),
+    REG_NAME_ENTRY(ERR_CODE_13),
+    REG_NAME_ENTRY(ERR_CODE_14),
+    REG_NAME_ENTRY(ERR_CODE_15),
+    REG_NAME_ENTRY(ERR_CODE_16),
+    REG_NAME_ENTRY(ERR_CODE_17),
+    REG_NAME_ENTRY(ERR_CODE_18),
+    REG_NAME_ENTRY(ERR_CODE_19),
+    REG_NAME_ENTRY(ERR_CODE_20),
+    REG_NAME_ENTRY(ERR_CODE_21),
+    REG_NAME_ENTRY(ERR_CODE_22),
+    REG_NAME_ENTRY(ERR_CODE_23),
+    REG_NAME_ENTRY(DIRECT_ACCESS_REGWEN),
+    REG_NAME_ENTRY(DIRECT_ACCESS_CMD),
+    REG_NAME_ENTRY(DIRECT_ACCESS_ADDRESS),
+    REG_NAME_ENTRY(DIRECT_ACCESS_WDATA_0),
+    REG_NAME_ENTRY(DIRECT_ACCESS_WDATA_1),
+    REG_NAME_ENTRY(DIRECT_ACCESS_RDATA_0),
+    REG_NAME_ENTRY(DIRECT_ACCESS_RDATA_1),
+    REG_NAME_ENTRY(CHECK_TRIGGER_REGWEN),
+    REG_NAME_ENTRY(CHECK_TRIGGER),
+    REG_NAME_ENTRY(CHECK_REGWEN),
+    REG_NAME_ENTRY(CHECK_TIMEOUT),
+    REG_NAME_ENTRY(INTEGRITY_CHECK_PERIOD),
+    REG_NAME_ENTRY(CONSISTENCY_CHECK_PERIOD),
+    REG_NAME_ENTRY(VENDOR_TEST_READ_LOCK),
+    REG_NAME_ENTRY(CREATOR_SW_CFG_READ_LOCK),
+    REG_NAME_ENTRY(OWNER_SW_CFG_READ_LOCK),
+    REG_NAME_ENTRY(OWNERSHIP_SLOT_STATE_READ_LOCK),
+    REG_NAME_ENTRY(ROT_CREATOR_AUTH_READ_LOCK),
+    REG_NAME_ENTRY(ROT_OWNER_AUTH_SLOT0_READ_LOCK),
+    REG_NAME_ENTRY(ROT_OWNER_AUTH_SLOT1_READ_LOCK),
+    REG_NAME_ENTRY(PLAT_INTEG_AUTH_SLOT0_READ_LOCK),
+    REG_NAME_ENTRY(PLAT_INTEG_AUTH_SLOT1_READ_LOCK),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT0_READ_LOCK),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT1_READ_LOCK),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT2_READ_LOCK),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT3_READ_LOCK),
+    REG_NAME_ENTRY(EXT_NVM_READ_LOCK),
+    REG_NAME_ENTRY(ROM_PATCH_READ_LOCK),
+    REG_NAME_ENTRY(VENDOR_TEST_DIGEST_0),
+    REG_NAME_ENTRY(VENDOR_TEST_DIGEST_1),
+    REG_NAME_ENTRY(CREATOR_SW_CFG_DIGEST_0),
+    REG_NAME_ENTRY(CREATOR_SW_CFG_DIGEST_1),
+    REG_NAME_ENTRY(OWNER_SW_CFG_DIGEST_0),
+    REG_NAME_ENTRY(OWNER_SW_CFG_DIGEST_1),
+    REG_NAME_ENTRY(ROT_CREATOR_AUTH_DIGEST_0),
+    REG_NAME_ENTRY(ROT_CREATOR_AUTH_DIGEST_1),
+    REG_NAME_ENTRY(ROT_OWNER_AUTH_SLOT0_DIGEST_0),
+    REG_NAME_ENTRY(ROT_OWNER_AUTH_SLOT0_DIGEST_1),
+    REG_NAME_ENTRY(ROT_OWNER_AUTH_SLOT1_DIGEST_0),
+    REG_NAME_ENTRY(ROT_OWNER_AUTH_SLOT1_DIGEST_1),
+    REG_NAME_ENTRY(PLAT_INTEG_AUTH_SLOT0_DIGEST_0),
+    REG_NAME_ENTRY(PLAT_INTEG_AUTH_SLOT0_DIGEST_1),
+    REG_NAME_ENTRY(PLAT_INTEG_AUTH_SLOT1_DIGEST_0),
+    REG_NAME_ENTRY(PLAT_INTEG_AUTH_SLOT1_DIGEST_1),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT0_DIGEST_0),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT0_DIGEST_1),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT1_DIGEST_0),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT1_DIGEST_1),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT2_DIGEST_0),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT2_DIGEST_1),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT3_DIGEST_0),
+    REG_NAME_ENTRY(PLAT_OWNER_AUTH_SLOT3_DIGEST_1),
+    REG_NAME_ENTRY(ROM_PATCH_DIGEST_0),
+    REG_NAME_ENTRY(ROM_PATCH_DIGEST_1),
+    REG_NAME_ENTRY(HW_CFG0_DIGEST_0),
+    REG_NAME_ENTRY(HW_CFG0_DIGEST_1),
+    REG_NAME_ENTRY(HW_CFG1_DIGEST_0),
+    REG_NAME_ENTRY(HW_CFG1_DIGEST_1),
+    REG_NAME_ENTRY(SECRET0_DIGEST_0),
+    REG_NAME_ENTRY(SECRET0_DIGEST_1),
+    REG_NAME_ENTRY(SECRET1_DIGEST_0),
+    REG_NAME_ENTRY(SECRET1_DIGEST_1),
+    REG_NAME_ENTRY(SECRET2_DIGEST_0),
+    REG_NAME_ENTRY(SECRET2_DIGEST_1),
+    REG_NAME_ENTRY(SECRET3_DIGEST_0),
+    REG_NAME_ENTRY(SECRET3_DIGEST_1),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+#define OT_OTP_NAME_ENTRY(_st_) [OT_OTP_##_st_] = stringify(OT_OTP_##_st_)
+
+static const char *OTP_TOKEN_NAMES[] = {
+    /* clang-format off */
+    OT_OTP_NAME_ENTRY(TOKEN_TEST_UNLOCK),
+    OT_OTP_NAME_ENTRY(TOKEN_TEST_EXIT),
+    OT_OTP_NAME_ENTRY(TOKEN_RMA),
+    /* clang-format on */
+};
+
+#define OTP_TOKEN_NAME(_tk_) \
+    ((unsigned)(_tk_) < ARRAY_SIZE(OTP_TOKEN_NAMES) ? \
+         OTP_TOKEN_NAMES[(_tk_)] : \
+         "?")
+
+static uint32_t ot_otp_dj_get_status(const OtOTPEngineState *s)
+{
+    uint32_t status;
+
+    status = FIELD_DP32(s->regs[R_STATUS], STATUS, DAI_IDLE,
+                        !ot_otp_engine_dai_is_busy(s));
+
+    return status;
+}
+
+static uint64_t ot_otp_dj_reg_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(opaque);
+    OtOTPEngineClass *c = OT_OTP_ENGINE_GET_CLASS(s);
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_ERR_CODE_0 ... R_ERR_CODE_23:
+    case R_DIRECT_ACCESS_WDATA_0:
+    case R_DIRECT_ACCESS_WDATA_1:
+    case R_DIRECT_ACCESS_RDATA_0:
+    case R_DIRECT_ACCESS_RDATA_1:
+    case R_DIRECT_ACCESS_ADDRESS:
+    case R_VENDOR_TEST_READ_LOCK ... R_ROM_PATCH_READ_LOCK:
+    case R_CHECK_TRIGGER_REGWEN:
+    case R_CHECK_REGWEN:
+        val32 = s->regs[reg];
+        break;
+    case R_STATUS:
+        val32 = ot_otp_dj_get_status(s);
+        break;
+    case R_DIRECT_ACCESS_REGWEN:
+        /* disabled either if SW locked, or if DAI is busy. */
+        val32 = s->regs[reg];
+        val32 &= FIELD_DP32(0u, DIRECT_ACCESS_REGWEN, REGWEN,
+                            (uint32_t)!ot_otp_engine_dai_is_busy(s));
+        break;
+    /* NOLINTNEXTLINE */
+    case R_DIRECT_ACCESS_CMD:
+    case R_CHECK_TRIGGER:
+        val32 = 0; /* R0W1C */
+        break;
+    case R_CHECK_TIMEOUT:
+    case R_INTEGRITY_CHECK_PERIOD:
+    case R_CONSISTENCY_CHECK_PERIOD:
+        /* @todo: not yet implemented, but these are R/W registers */
+        qemu_log_mask(LOG_UNIMP, "%s: %s: %s is not supported\n", __func__,
+                      s->ot_id, REG_NAME(reg));
+        val32 = s->regs[reg];
+        break;
+    case R_VENDOR_TEST_DIGEST_0 ... R_SECRET3_DIGEST_1:
+        /*
+         * In all partitions with a digest, the digest itself is ALWAYS
+         * readable.
+         */
+        val32 = c->get_part_digest_reg(s, reg - R_VENDOR_TEST_DIGEST_0);
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_otp_io_reg_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                                 pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_otp_dj_reg_write(void *opaque, hwaddr addr, uint64_t value,
+                                unsigned size)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(opaque);
+    OtOTPEngineClass *c = OT_OTP_ENGINE_GET_CLASS(s);
+    (void)size;
+    uint32_t val32 = (uint32_t)value;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+
+    trace_ot_otp_io_reg_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                              pc);
+
+    switch (reg) {
+    case R_DIRECT_ACCESS_CMD:
+    case R_DIRECT_ACCESS_ADDRESS:
+    case R_DIRECT_ACCESS_WDATA_0:
+    case R_DIRECT_ACCESS_WDATA_1:
+    case R_VENDOR_TEST_READ_LOCK ... R_ROM_PATCH_READ_LOCK:
+        if (!(s->regs[R_DIRECT_ACCESS_REGWEN] &
+              R_DIRECT_ACCESS_REGWEN_REGWEN_MASK)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: %s is not enabled, %s is protected\n",
+                          __func__, s->ot_id, REG_NAME(R_DIRECT_ACCESS_REGWEN),
+                          REG_NAME(reg));
+            return;
+        }
+        break;
+    case R_CHECK_TRIGGER:
+        if (!(s->regs[R_CHECK_TRIGGER_REGWEN] &
+              R_CHECK_TRIGGER_REGWEN_REGWEN_MASK)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: %s is not enabled, %s is protected\n",
+                          __func__, s->ot_id, REG_NAME(R_CHECK_TRIGGER_REGWEN),
+                          REG_NAME(reg));
+            return;
+        }
+        break;
+    case R_CHECK_TIMEOUT:
+    case R_INTEGRITY_CHECK_PERIOD:
+    case R_CONSISTENCY_CHECK_PERIOD:
+        if (!(s->regs[R_CHECK_REGWEN] & R_CHECK_REGWEN_REGWEN_MASK)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: %s is not enabled, %s is protected\n",
+                          __func__, s->ot_id, REG_NAME(R_CHECK_REGWEN),
+                          REG_NAME(reg));
+            return;
+        }
+        break;
+    case R_STATUS:
+    case R_ERR_CODE_0 ... R_ERR_CODE_23:
+    case R_DIRECT_ACCESS_RDATA_0:
+    case R_DIRECT_ACCESS_RDATA_1:
+    case R_VENDOR_TEST_DIGEST_0 ... R_SECRET3_DIGEST_1:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        return;
+    default:
+        break;
+    }
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_WMASK;
+        s->regs[R_INTR_STATE] &= ~val32; /* RW1C */
+        c->update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_WMASK;
+        s->regs[R_INTR_ENABLE] = val32;
+        c->update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_WMASK;
+        s->regs[R_INTR_STATE] = val32;
+        c->update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_WMASK;
+        s->regs[reg] = val32;
+        c->update_alerts(s);
+        break;
+    case R_DIRECT_ACCESS_REGWEN:
+        val32 &= R_DIRECT_ACCESS_REGWEN_REGWEN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_DIRECT_ACCESS_CMD:
+        if (FIELD_EX32(val32, OT_OTP_DIRECT_ACCESS_CMD, RD)) {
+            c->dai_read(s);
+        } else if (FIELD_EX32(val32, OT_OTP_DIRECT_ACCESS_CMD, WR)) {
+            c->dai_write(s);
+        } else if (FIELD_EX32(val32, OT_OTP_DIRECT_ACCESS_CMD, DIGEST)) {
+            c->dai_digest(s);
+        }
+        /* @todo implement ZEROIZE command */
+        break;
+    case R_DIRECT_ACCESS_ADDRESS:
+        val32 &= R_DIRECT_ACCESS_ADDRESS_ADDRESS_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_DIRECT_ACCESS_WDATA_0:
+    case R_DIRECT_ACCESS_WDATA_1:
+        s->regs[reg] = val32;
+        break;
+    case R_VENDOR_TEST_READ_LOCK ... R_ROM_PATCH_READ_LOCK:
+        val32 &= OT_OTP_READ_LOCK_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CHECK_TRIGGER_REGWEN:
+        val32 &= R_CHECK_TRIGGER_REGWEN_REGWEN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CHECK_REGWEN:
+        val32 &= R_CHECK_REGWEN_REGWEN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CHECK_TRIGGER:
+    case R_CHECK_TIMEOUT:
+    case R_INTEGRITY_CHECK_PERIOD:
+    case R_CONSISTENCY_CHECK_PERIOD:
+        qemu_log_mask(LOG_UNIMP, "%s: %s: %s is not supported\n", __func__,
+                      s->ot_id, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static const char *ot_otp_dj_swcfg_reg_name(unsigned swreg)
+{
+#define CASE_BYTE(_reg_) \
+    case A_##_reg_: \
+        return stringify(_reg_)
+#define CASE_SUB(_reg_, _sz_) \
+    case A_##_reg_...(A_##_reg_ + (_sz_) - 1u): \
+        return stringify(_reg_)
+#define CASE_REG(_reg_) \
+    case A_##_reg_...(A_##_reg_ + 3u): \
+        return stringify(_reg_)
+#define CASE_WIDE(_reg_) \
+    case A_##_reg_...(A_##_reg_ + 7u): \
+        return stringify(_reg_)
+#define CASE_RANGE(_reg_) \
+    case A_##_reg_...(A_##_reg_ + (_reg_##_SIZE) - 1u): \
+        return stringify(_reg_)
+
+    switch (swreg) {
+        CASE_RANGE(VENDOR_TEST_SCRATCH);
+        CASE_WIDE(VENDOR_TEST_DIGEST);
+        CASE_RANGE(CREATOR_SW_CFG_AST_CFG);
+        CASE_REG(CREATOR_SW_CFG_AST_INIT_EN);
+        CASE_RANGE(CREATOR_SW_CFG_OVERRIDES);
+        CASE_REG(CREATOR_SW_CFG_ROM_EXT_SKU);
+        CASE_REG(CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN);
+        CASE_RANGE(CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN);
+        CASE_REG(CREATOR_SW_CFG_SIGVERIFY_SPX_EN);
+        CASE_RANGE(CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN);
+        CASE_REG(CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG);
+        CASE_REG(CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG);
+        CASE_REG(CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE);
+        CASE_REG(CREATOR_SW_CFG_RNG_EN);
+        CASE_REG(CREATOR_SW_CFG_JITTER_EN);
+        CASE_REG(CREATOR_SW_CFG_RET_RAM_RESET_MASK);
+        CASE_REG(CREATOR_SW_CFG_MANUF_STATE);
+        CASE_REG(CREATOR_SW_CFG_ROM_EXEC_EN);
+        CASE_REG(CREATOR_SW_CFG_CPUCTRL);
+        CASE_REG(CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT);
+        CASE_REG(CREATOR_SW_CFG_MIN_SEC_VER_BL0);
+        CASE_REG(CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN);
+        CASE_REG(CREATOR_SW_CFG_RMA_SPIN_EN);
+        CASE_REG(CREATOR_SW_CFG_RMA_SPIN_CYCLES);
+        CASE_REG(CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_ALERT_THRESHOLD);
+        CASE_REG(CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST);
+        CASE_REG(CREATOR_SW_CFG_SRAM_KEY_RENEW_EN);
+        CASE_WIDE(CREATOR_SW_CFG_DIGEST);
+        CASE_REG(OWNER_SW_CFG_ROM_ERROR_REPORTING);
+        CASE_REG(OWNER_SW_CFG_ROM_BOOTSTRAP_DIS);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_CLASS_EN);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_ESCALATION);
+        CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION);
+        CASE_RANGE(OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION);
+        CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH);
+        CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES);
+        CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA);
+        CASE_REG(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES);
+        CASE_REG(OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN);
+        CASE_REG(OWNER_SW_CFG_MANUF_STATE);
+        CASE_REG(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN);
+        CASE_WIDE(OWNER_SW_CFG_DIGEST);
+        CASE_RANGE(OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH);
+        CASE_RANGE(OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH);
+        CASE_RANGE(OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH);
+        CASE_RANGE(ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY);
+        CASE_REG(ROT_CREATOR_AUTH_OWNERSHIP_STATE);
+        CASE_RANGE(ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY);
+        CASE_RANGE(ROT_CREATOR_AUTH_KEYMANIFEST_KEY);
+        CASE_RANGE(ROT_CREATOR_AUTH_UNLOCK4XFER_KEY);
+        CASE_RANGE(ROT_CREATOR_AUTH_IDENTITY_CERT);
+        CASE_WIDE(ROT_CREATOR_AUTH_DIGEST);
+        CASE_RANGE(ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY);
+        CASE_RANGE(ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY);
+        CASE_WIDE(ROT_OWNER_AUTH_SLOT0_DIGEST);
+        CASE_RANGE(ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY);
+        CASE_RANGE(ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY);
+        CASE_WIDE(ROT_OWNER_AUTH_SLOT1_DIGEST);
+        CASE_RANGE(PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY);
+        CASE_RANGE(PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY);
+        CASE_WIDE(PLAT_INTEG_AUTH_SLOT0_DIGEST);
+        CASE_RANGE(PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY);
+        CASE_RANGE(PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY);
+        CASE_WIDE(PLAT_INTEG_AUTH_SLOT1_DIGEST);
+        CASE_RANGE(PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY);
+        CASE_RANGE(PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY);
+        CASE_WIDE(PLAT_OWNER_AUTH_SLOT0_DIGEST);
+        CASE_RANGE(PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY);
+        CASE_RANGE(PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY);
+        CASE_WIDE(PLAT_OWNER_AUTH_SLOT1_DIGEST);
+        CASE_RANGE(PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY);
+        CASE_RANGE(PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY);
+        CASE_WIDE(PLAT_OWNER_AUTH_SLOT2_DIGEST);
+        CASE_RANGE(PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY);
+        CASE_RANGE(PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY);
+        CASE_WIDE(PLAT_OWNER_AUTH_SLOT3_DIGEST);
+        CASE_RANGE(EXT_NVM_ANTIREPLAY_FRESHNESS_CNT);
+        CASE_RANGE(ROM_PATCH_DATA);
+        CASE_WIDE(ROM_PATCH_DIGEST);
+        CASE_RANGE(HW_CFG0_DEVICE_ID);
+        CASE_RANGE(HW_CFG0_MANUF_STATE);
+        CASE_WIDE(HW_CFG0_DIGEST);
+        CASE_REG(HW_CFG1_SOC_DBG_STATE);
+        CASE_BYTE(HW_CFG1_EN_CSRNG_SW_APP_READ);
+        CASE_BYTE(HW_CFG1_EN_SRAM_IFETCH);
+        CASE_WIDE(HW_CFG1_DIGEST);
+        CASE_RANGE(SECRET0_TEST_UNLOCK_TOKEN);
+        CASE_RANGE(SECRET0_TEST_EXIT_TOKEN);
+        CASE_WIDE(SECRET0_DIGEST);
+        CASE_WIDE(SECRET0_ZER);
+        CASE_RANGE(SECRET1_SRAM_DATA_KEY_SEED);
+        CASE_WIDE(SECRET1_DIGEST);
+        CASE_WIDE(SECRET1_ZER);
+        CASE_RANGE(SECRET2_RMA_TOKEN);
+        CASE_RANGE(SECRET2_CREATOR_ROOT_KEY_SHARE0);
+        CASE_RANGE(SECRET2_CREATOR_ROOT_KEY_SHARE1);
+        CASE_RANGE(SECRET2_CREATOR_SEED);
+        CASE_WIDE(SECRET2_DIGEST);
+        CASE_WIDE(SECRET2_ZER);
+        CASE_RANGE(SECRET3_OWNER_SEED);
+        CASE_WIDE(SECRET3_DIGEST);
+        CASE_WIDE(SECRET3_ZER);
+        CASE_RANGE(LC_TRANSITION_CNT);
+        CASE_RANGE(LC_STATE);
+    default:
+        return "<?>";
+    }
+
+#undef CASE_BYTE
+#undef CASE_SUB
+#undef CASE_REG
+#undef CASE_RANGE
+#undef CASE_DIGEST
+}
+
+static MemTxResult ot_otp_dj_swcfg_read_with_attrs(
+    void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(opaque);
+    OtOTPEngineClass *c = OT_OTP_ENGINE_GET_CLASS(s);
+    (void)size;
+    (void)attrs;
+
+    hwaddr reg = R32_OFF(addr);
+    int partition = c->get_part_from_address(s, addr);
+
+    if (partition < 0) {
+        trace_ot_otp_access_error_on(s->ot_id, partition, addr, "invalid");
+        *data = 0ull;
+
+        return MEMTX_DECODE_ERROR;
+    }
+
+    unsigned part_ix = (unsigned)partition;
+
+    if (ot_otp_engine_is_buffered(s, part_ix)) {
+        trace_ot_otp_access_error_on(s->ot_id, partition, addr, "buffered");
+        c->set_error(s, part_ix, OT_OTP_ACCESS_ERROR);
+
+        /* real HW seems to stall the Tile Link bus in this case */
+        return MEMTX_ACCESS_ERROR;
+    }
+
+    bool is_readable = c->is_readable(s, part_ix);
+    bool is_digest = ot_otp_engine_is_part_digest_offset(s, part_ix, addr);
+    bool is_zer = ot_otp_engine_is_part_zer_offset(s, part_ix, addr);
+
+    if (!is_readable && !(is_digest || is_zer)) {
+        trace_ot_otp_access_error_on(s->ot_id, partition, addr, "not readable");
+        c->set_error(s, part_ix, OT_OTP_ACCESS_ERROR);
+
+        return MEMTX_DECODE_ERROR;
+    }
+
+    uint32_t val32 = s->otp->data[reg];
+    c->set_error(s, part_ix, OT_OTP_NO_ERROR);
+
+    uint64_t pc;
+
+    pc = ibex_get_current_pc();
+    trace_ot_otp_io_swcfg_read_out(s->ot_id, (uint32_t)addr,
+                                   ot_otp_dj_swcfg_reg_name(addr), val32, pc);
+
+    *data = (uint64_t)val32;
+
+    return MEMTX_OK;
+}
+
+static void ot_otp_dj_get_lc_info(
+    const OtOTPIf *dev, uint16_t *lc_tcount, uint16_t *lc_state,
+    uint8_t *lc_valid, uint8_t *secret_valid, const OtOTPTokens **tokens)
+{
+    const OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+    const OtOTPStorage *otp = s->otp;
+
+    if (lc_tcount) {
+        memcpy(lc_tcount, &otp->data[R_LC_TRANSITION_CNT],
+               LC_TRANSITION_CNT_SIZE);
+    }
+
+    if (lc_state) {
+        memcpy(lc_state, &otp->data[R_LC_STATE], LC_STATE_SIZE);
+    }
+
+    if (lc_valid) {
+        *lc_valid = !(s->part_ctrls[OTP_PART_SECRET0].failed ||
+                      s->part_ctrls[OTP_PART_SECRET2].failed ||
+                      s->part_ctrls[s->part_lc_num].failed) ?
+                        OT_MULTIBITBOOL_LC4_TRUE :
+                        OT_MULTIBITBOOL_LC4_FALSE;
+    }
+    if (secret_valid) {
+        *secret_valid = (!s->part_ctrls[OTP_PART_SECRET2].failed &&
+                         s->part_ctrls[OTP_PART_SECRET2].locked) ?
+                            OT_MULTIBITBOOL_LC4_TRUE :
+                            OT_MULTIBITBOOL_LC4_FALSE;
+    }
+    if (tokens) {
+        *tokens = s->tokens;
+    }
+}
+
+static void ot_otp_dj_get_keymgr_secret(
+    OtOTPIf *dev, OtOTPKeyMgrSecretType type, OtOTPKeyMgrSecret *secret)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+    int partition;
+    size_t offset;
+
+    switch (type) {
+    case OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE0:
+        partition = OTP_PART_SECRET2;
+        offset =
+            A_SECRET2_CREATOR_ROOT_KEY_SHARE0 - s->part_descs[partition].offset;
+        break;
+    case OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE1:
+        partition = OTP_PART_SECRET2;
+        offset =
+            A_SECRET2_CREATOR_ROOT_KEY_SHARE1 - s->part_descs[partition].offset;
+        break;
+    case OT_OTP_KEYMGR_SECRET_CREATOR_SEED:
+        partition = OTP_PART_SECRET2;
+        offset = A_SECRET2_CREATOR_SEED - s->part_descs[partition].offset;
+        break;
+    case OT_OTP_KEYMGR_SECRET_OWNER_SEED:
+        partition = OTP_PART_SECRET3;
+        offset = A_SECRET3_OWNER_SEED - s->part_descs[partition].offset;
+        break;
+    default:
+        error_report("%s: %s: invalid OTP keymgr secret type: %d", __func__,
+                     s->ot_id, type);
+        secret->valid = false;
+        memset(secret->secret, 0, OT_OTP_KEYMGR_SECRET_SIZE);
+        return;
+    }
+
+    unsigned part_ix = (unsigned)partition;
+    g_assert(ot_otp_engine_is_buffered(s, part_ix));
+
+    const uint8_t *data_ptr;
+    if (s->lc_broadcast.current_level & BIT(OT_OTP_LC_SEED_HW_RD_EN)) {
+        data_ptr = (const uint8_t *)s->part_ctrls[part_ix].buffer.data;
+    } else {
+        /* source data from PartInvDefault instead of real buffer */
+        OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+        data_ptr = pctrl->inv_default_data;
+    }
+
+    secret->valid = s->part_ctrls[part_ix].digest != 0;
+    memcpy(secret->secret, &data_ptr[offset], OT_OTP_KEYMGR_SECRET_SIZE);
+}
+
+static void
+ot_otp_dj_update_status_error(OtOTPImplIf *dev, OtOTPStatus error, bool set)
+{
+    const OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+
+    uint32_t mask;
+    switch (error) {
+    case OT_OTP_STATUS_DAI:
+        mask = R_STATUS_DAI_ERROR_MASK;
+        break;
+    case OT_OTP_STATUS_LCI:
+        mask = R_STATUS_LCI_ERROR_MASK;
+        break;
+    default:
+        g_assert_not_reached();
+        return;
+    }
+
+    if (set) {
+        s->regs[R_STATUS] |= mask;
+    } else {
+        s->regs[R_STATUS] &= ~mask;
+    }
+}
+
+static void ot_otp_dj_pwr_load_hw_cfg(OtOTPEngineState *s)
+{
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(s);
+
+    const OtOTPPartDesc *pdesc0 = &ic->part_descs[OTP_PART_HW_CFG0];
+    const OtOTPPartDesc *pdesc1 = &ic->part_descs[OTP_PART_HW_CFG1];
+    const OtOTPPartController *pctrl0 = &s->part_ctrls[OTP_PART_HW_CFG0];
+    const OtOTPPartController *pctrl1 = &s->part_ctrls[OTP_PART_HW_CFG1];
+    const uint8_t *pdata0 = (const uint8_t *)pctrl0->buffer.data;
+    const uint8_t *pdata1 = (const uint8_t *)pctrl1->buffer.data;
+
+    OtOTPHWCfg *hw_cfg = s->hw_cfg;
+
+    memcpy(hw_cfg->device_id, &pdata0[A_HW_CFG0_DEVICE_ID - pdesc0->offset],
+           sizeof(hw_cfg->device_id));
+    memcpy(hw_cfg->manuf_state, &pdata0[A_HW_CFG0_MANUF_STATE - pdesc0->offset],
+           sizeof(hw_cfg->manuf_state));
+    memcpy(hw_cfg->soc_dbg_state,
+           &pdata1[A_HW_CFG1_SOC_DBG_STATE - pdesc1->offset],
+           sizeof(hw_cfg->soc_dbg_state));
+    /* do not prevent execution from SRAM if no OTP configuration is loaded */
+    hw_cfg->en_sram_ifetch_mb8 =
+        s->blk ? pdata1[A_HW_CFG1_EN_SRAM_IFETCH - pdesc1->offset] :
+                 OT_MULTIBITBOOL8_TRUE;
+    /* do not prevent CSRNG app reads if no OTP configuration is loaded */
+    hw_cfg->en_csrng_sw_app_read_mb8 =
+        s->blk ? pdata1[A_HW_CFG1_EN_CSRNG_SW_APP_READ - pdesc1->offset] :
+                 OT_MULTIBITBOOL8_TRUE;
+}
+
+static void ot_otp_dj_pwr_load_tokens(OtOTPEngineState *s)
+{
+    memset(s->tokens, 0, sizeof(*s->tokens));
+
+    OtOTPTokens *tokens = s->tokens;
+
+    static_assert(sizeof(OtOTPTokenValue) == 16u, "Invalid token size");
+
+    for (unsigned tkx = 0; tkx < OT_OTP_TOKEN_COUNT; tkx++) {
+        unsigned partition;
+        uint32_t secret_addr;
+
+        switch (tkx) {
+        case OT_OTP_TOKEN_TEST_UNLOCK:
+            partition = (unsigned)OTP_PART_SECRET0;
+            secret_addr = A_SECRET0_TEST_UNLOCK_TOKEN;
+            break;
+        case OT_OTP_TOKEN_TEST_EXIT:
+            partition = (unsigned)OTP_PART_SECRET0;
+            secret_addr = A_SECRET0_TEST_EXIT_TOKEN;
+            break;
+        case OT_OTP_TOKEN_RMA:
+            partition = (unsigned)OTP_PART_SECRET2;
+            secret_addr = A_SECRET2_RMA_TOKEN;
+            break;
+        default:
+            g_assert_not_reached();
+            break;
+        }
+
+        OtOTPPartController *pctrl = &s->part_ctrls[partition];
+        g_assert(pctrl->buffer.data != NULL);
+
+        /* byte offset of the secret within the partition */
+        unsigned secret_offset =
+            secret_addr - ot_otp_engine_part_data_offset(s, partition);
+        g_assert(secret_offset + sizeof(OtOTPTokenValue) <=
+                 OT_OTP_PART_DESCS[partition].size);
+
+        OtOTPTokenValue value;
+        memcpy(&value, &pctrl->buffer.data[secret_offset / sizeof(uint32_t)],
+               sizeof(OtOTPTokenValue));
+
+        if (s->part_ctrls[partition].locked) {
+            tokens->values[tkx] = value;
+            tokens->valid_bm |= 1u << tkx;
+        }
+        trace_ot_otp_load_token(s->ot_id, OTP_TOKEN_NAME(tkx), tkx, value.hi,
+                                value.lo,
+                                (s->tokens->valid_bm & (1u << tkx)) ? "" :
+                                                                      "in");
+    }
+}
+
+static void ot_otp_dj_signal_pwr_sequence(OtOTPImplIf *dev)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+
+    ot_otp_dj_pwr_load_hw_cfg(s);
+    ot_otp_dj_pwr_load_tokens(s);
+}
+
+static const MemoryRegionOps ot_otp_dj_reg_ops = {
+    .read = &ot_otp_dj_reg_read,
+    .write = &ot_otp_dj_reg_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const MemoryRegionOps ot_otp_dj_swcfg_ops = {
+    .read_with_attrs = &ot_otp_dj_swcfg_read_with_attrs,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static void ot_otp_dj_reset_enter(Object *obj, ResetType type)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(obj);
+    OtOTPDjClass *dc = OT_OTP_DJ_GET_CLASS(obj);
+
+    memset(s->regs, 0, REGS_SIZE);
+    s->regs[R_DIRECT_ACCESS_REGWEN] = 0x00000001u;
+    s->regs[R_CHECK_TRIGGER_REGWEN] = 0x00000001u;
+    s->regs[R_CHECK_REGWEN] = 0x00000001u;
+    s->regs[R_VENDOR_TEST_READ_LOCK] = 0x00000001u;
+    s->regs[R_CREATOR_SW_CFG_READ_LOCK] = 0x00000001u;
+    s->regs[R_OWNER_SW_CFG_READ_LOCK] = 0x00000001u;
+    s->regs[R_OWNERSHIP_SLOT_STATE_READ_LOCK] = 0x00000001u;
+    s->regs[R_ROT_CREATOR_AUTH_READ_LOCK] = 0x00000001u;
+    s->regs[R_ROT_OWNER_AUTH_SLOT0_READ_LOCK] = 0x00000001u;
+    s->regs[R_ROT_OWNER_AUTH_SLOT1_READ_LOCK] = 0x00000001u;
+    s->regs[R_PLAT_INTEG_AUTH_SLOT0_READ_LOCK] = 0x00000001u;
+    s->regs[R_PLAT_INTEG_AUTH_SLOT1_READ_LOCK] = 0x00000001u;
+    s->regs[R_PLAT_OWNER_AUTH_SLOT0_READ_LOCK] = 0x00000001u;
+    s->regs[R_PLAT_OWNER_AUTH_SLOT1_READ_LOCK] = 0x00000001u;
+    s->regs[R_PLAT_OWNER_AUTH_SLOT2_READ_LOCK] = 0x00000001u;
+    s->regs[R_PLAT_OWNER_AUTH_SLOT3_READ_LOCK] = 0x00000001u;
+    s->regs[R_EXT_NVM_READ_LOCK] = 0x00000001u;
+    s->regs[R_ROM_PATCH_READ_LOCK] = 0x00000001u;
+
+    if (dc->parent_phases.enter) {
+        /* OtOTPEngineState cleanup */
+        dc->parent_phases.enter(obj, type);
+    }
+}
+
+static void ot_otp_dj_init(Object *obj)
+{
+    OtOTPDjState *s = OT_OTP_DJ(obj);
+    OtOTPEngineState *es = OT_OTP_ENGINE(obj);
+
+    /* note: device realization is implemented in OtOTPEngineState */
+
+    es->regs = g_new0(uint32_t, REGS_COUNT);
+    es->reg_offset.dai_base = R_DIRECT_ACCESS_REGWEN;
+    es->reg_offset.err_code_base = R_ERR_CODE_0;
+    es->reg_offset.read_lock_base = R_VENDOR_TEST_READ_LOCK;
+
+    /*
+     * "ctrl" region covers two sub-regions:
+     *   - "regs", registers:
+     *     offset 0, size REGS_SIZE
+     *   - "swcfg", software config window
+     *     offset SW_CFG_WINDOW_OFFSET, size SW_CFG_WINDOW_SIZE
+     */
+    memory_region_init(&s->mmio.ctrl, obj, TYPE_OT_OTP_DJ "-ctrl",
+                       SW_CFG_WINDOW_OFFSET + SW_CFG_WINDOW_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio.ctrl);
+
+    memory_region_init_io(&s->mmio.sub.regs, obj, &ot_otp_dj_reg_ops, s,
+                          TYPE_OT_OTP_DJ "-regs", REGS_SIZE);
+    memory_region_add_subregion(&s->mmio.ctrl, 0u, &s->mmio.sub.regs);
+
+    /* @todo it might be worthwhile to use a ROM-kind here */
+    memory_region_init_io(&s->mmio.sub.swcfg, obj, &ot_otp_dj_swcfg_ops, s,
+                          TYPE_OT_OTP_DJ "-swcfg", SW_CFG_WINDOW_SIZE);
+    memory_region_add_subregion(&s->mmio.ctrl, SW_CFG_WINDOW_OFFSET,
+                                &s->mmio.sub.swcfg);
+}
+
+static void ot_otp_dj_class_init(ObjectClass *klass, const void *data)
+{
+    (void)data;
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtOTPDjClass *dc = OT_OTP_DJ_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_otp_dj_reset_enter, NULL, NULL,
+                                       &dc->parent_phases);
+
+    OtOTPEngineClass *ec = OT_OTP_ENGINE_CLASS(klass);
+    OtOTPIfClass *oc = OT_OTP_IF_CLASS(klass);
+    oc->get_lc_info = &ot_otp_dj_get_lc_info;
+    oc->get_hw_cfg = ec->get_hw_cfg;
+    oc->get_otp_key = ec->get_otp_key;
+    oc->get_keymgr_secret = &ot_otp_dj_get_keymgr_secret;
+    oc->program_req = ec->program_req;
+
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_CLASS(klass);
+    ic->signal_pwr_sequence = &ot_otp_dj_signal_pwr_sequence;
+    ic->update_status_error = &ot_otp_dj_update_status_error;
+
+    ic->part_descs = OT_OTP_PART_DESCS;
+    ic->part_count = (unsigned)OTP_PART_COUNT;
+    ic->part_lc_num = (unsigned)OTP_PART_LIFE_CYCLE;
+    ic->sram_key_req_slot_count = NUM_SRAM_KEY_REQ_SLOTS;
+
+    ic->key_seeds = OT_OTP_KEY_SEEDS;
+    ic->has_flash_support = false;
+    ic->has_zer_support = true;
+
+    g_assert(OT_OTP_KEY_SEEDS[OT_OTP_KEY_SRAM].size ==
+             SECRET1_SRAM_DATA_KEY_SEED_SIZE);
+}
+
+static const TypeInfo ot_otp_dj_info = {
+    .name = TYPE_OT_OTP_DJ,
+    .parent = TYPE_OT_OTP_ENGINE,
+    .instance_size = sizeof(OtOTPDjState),
+    .instance_init = &ot_otp_dj_init,
+    .class_size = sizeof(OtOTPDjClass),
+    .class_init = &ot_otp_dj_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_OT_OTP_IF }, /* public OTP API */
+            { TYPE_OT_OTP_IMPL_IF }, /* private OTP API for OTP engine */
+            {},
+        },
+};
+
+static void ot_otp_dj_register_types(void)
+{
+    type_register_static(&ot_otp_dj_info);
+}
+
+type_init(ot_otp_dj_register_types);
diff --git a/hw/opentitan/ot_otp_dj_parts.c b/hw/opentitan/ot_otp_dj_parts.c
new file mode 100644
index 0000000000000..dda4c81752dff
--- /dev/null
+++ b/hw/opentitan/ot_otp_dj_parts.c
@@ -0,0 +1,378 @@
+/*
+ * Generated from otp_ctrl_mmap.hjson with otptool.py
+ * Top version: 5fe6fe8605
+ */
+
+/* this prevents linters from checking this file without its parent file */
+#ifdef OT_OTP_DJ_PARTS
+
+/* clang-format off */
+/* NOLINTBEGIN */
+static const OtOTPPartDesc OT_OTP_PART_DESCS[] = {
+    [OTP_PART_VENDOR_TEST] = {
+        .name = "VENDOR_TEST",
+        .size = 64u,
+        .offset = 0u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 56u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = false,
+        .zeroizable = false,
+    },
+    [OTP_PART_CREATOR_SW_CFG] = {
+        .name = "CREATOR_SW_CFG",
+        .size = 304u,
+        .offset = 64u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 360u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_OWNER_SW_CFG] = {
+        .name = "OWNER_SW_CFG",
+        .size = 600u,
+        .offset = 368u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 960u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_OWNERSHIP_SLOT_STATE] = {
+        .name = "OWNERSHIP_SLOT_STATE",
+        .size = 48u,
+        .offset = 968u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = UINT16_MAX,
+        .hw_digest = false,
+        .sw_digest = false,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_ROT_CREATOR_AUTH] = {
+        .name = "ROT_CREATOR_AUTH",
+        .size = 1424u,
+        .offset = 1016u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 2432u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_ROT_OWNER_AUTH_SLOT0] = {
+        .name = "ROT_OWNER_AUTH_SLOT0",
+        .size = 328u,
+        .offset = 2440u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 2760u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_ROT_OWNER_AUTH_SLOT1] = {
+        .name = "ROT_OWNER_AUTH_SLOT1",
+        .size = 328u,
+        .offset = 2768u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 3088u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_PLAT_INTEG_AUTH_SLOT0] = {
+        .name = "PLAT_INTEG_AUTH_SLOT0",
+        .size = 328u,
+        .offset = 3096u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 3416u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_PLAT_INTEG_AUTH_SLOT1] = {
+        .name = "PLAT_INTEG_AUTH_SLOT1",
+        .size = 328u,
+        .offset = 3424u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 3744u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_PLAT_OWNER_AUTH_SLOT0] = {
+        .name = "PLAT_OWNER_AUTH_SLOT0",
+        .size = 328u,
+        .offset = 3752u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 4072u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_PLAT_OWNER_AUTH_SLOT1] = {
+        .name = "PLAT_OWNER_AUTH_SLOT1",
+        .size = 328u,
+        .offset = 4080u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 4400u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_PLAT_OWNER_AUTH_SLOT2] = {
+        .name = "PLAT_OWNER_AUTH_SLOT2",
+        .size = 328u,
+        .offset = 4408u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 4728u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_PLAT_OWNER_AUTH_SLOT3] = {
+        .name = "PLAT_OWNER_AUTH_SLOT3",
+        .size = 328u,
+        .offset = 4736u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 5056u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_EXT_NVM] = {
+        .name = "EXT_NVM",
+        .size = 1024u,
+        .offset = 5064u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = UINT16_MAX,
+        .hw_digest = false,
+        .sw_digest = false,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = false,
+        .zeroizable = false,
+    },
+    [OTP_PART_ROM_PATCH] = {
+        .name = "ROM_PATCH",
+        .size = 9864u,
+        .offset = 6088u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 15944u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_HW_CFG0] = {
+        .name = "HW_CFG0",
+        .size = 72u,
+        .offset = 15952u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 16016u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = false,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = false,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_HW_CFG1] = {
+        .name = "HW_CFG1",
+        .size = 16u,
+        .offset = 16024u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 16032u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = false,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = false,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_SECRET0] = {
+        .name = "SECRET0",
+        .size = 48u,
+        .offset = 16040u,
+        .zer_offset = 16080u,
+        .digest_offset = 16072u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = true,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = true,
+    },
+    [OTP_PART_SECRET1] = {
+        .name = "SECRET1",
+        .size = 32u,
+        .offset = 16088u,
+        .zer_offset = 16112u,
+        .digest_offset = 16104u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = true,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = true,
+    },
+    [OTP_PART_SECRET2] = {
+        .name = "SECRET2",
+        .size = 128u,
+        .offset = 16120u,
+        .zer_offset = 16240u,
+        .digest_offset = 16232u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = true,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = true,
+        .iskeymgr_creator = true,
+    },
+    [OTP_PART_SECRET3] = {
+        .name = "SECRET3",
+        .size = 48u,
+        .offset = 16248u,
+        .zer_offset = 16288u,
+        .digest_offset = 16280u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = true,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = true,
+        .iskeymgr_owner = true,
+    },
+    [OTP_PART_LIFE_CYCLE] = {
+        .name = "LIFE_CYCLE",
+        .size = 88u,
+        .offset = 16296u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = UINT16_MAX,
+        .hw_digest = false,
+        .sw_digest = false,
+        .secret = false,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = false,
+        .integrity = true,
+    },
+};
+
+#define OTP_PART_COUNT ARRAY_SIZE(OT_OTP_PART_DESCS)
+
+static const OtOTPKeySeed OT_OTP_KEY_SEEDS[OT_OTP_KEY_COUNT] = {
+    [OT_OTP_KEY_OTBN] = {
+        .partition = OTP_PART_SECRET1,
+        .offset = 0,
+        .size = 16,
+    },
+    [OT_OTP_KEY_SRAM] = {
+        .partition = OTP_PART_SECRET1,
+        .offset = 0,
+        .size = 16,
+    },
+};
+
+/* NOLINTEND */
+/* clang-format on */
+
+#endif /* OT_OTP_DJ_PARTS */
diff --git a/hw/opentitan/ot_otp_eg.c b/hw/opentitan/ot_otp_eg.c
new file mode 100644
index 0000000000000..1412bc6d9c67a
--- /dev/null
+++ b/hw/opentitan/ot_otp_eg.c
@@ -0,0 +1,1227 @@
+/*
+ * QEMU OpenTitan EarlGrey One Time Programmable (OTP) implementation
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define OT_OTP_COMPORTABLE_REGS
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "hw/opentitan/ot_otp_eg.h"
+#include "hw/opentitan/ot_otp_engine.h"
+#include "hw/opentitan/ot_otp_impl_if.h"
+#include "trace.h"
+
+#define NUM_ERROR_ENTRIES       13u
+#define NUM_PART                11u
+#define NUM_PART_BUF            6u
+#define NUM_PART_UNBUF          5u
+#define NUM_SRAM_KEY_REQ_SLOTS  4u
+#define NUM_SW_CFG_WINDOW_WORDS 512u
+
+#define OTP_BYTE_ADDR_WIDTH 11u
+
+/* clang-format off */
+/* Core registers */
+REG32(STATUS, 0x10u)
+    FIELD(STATUS, VENDOR_TEST_ERROR, 0u, 1u)
+    FIELD(STATUS, CREATOR_SW_CFG_ERROR, 1u, 1u)
+    FIELD(STATUS, OWNER_SW_CFG_ERROR, 2u, 1u)
+    FIELD(STATUS, ROT_CREATOR_AUTH_CODESIGN_ERROR, 3u, 1u)
+    FIELD(STATUS, ROT_CREATOR_AUTH_STATE_ERROR, 4u, 1u)
+    FIELD(STATUS, HW_CFG0_ERROR, 5u, 1u)
+    FIELD(STATUS, HW_CFG1_ERROR, 6u, 1u)
+    FIELD(STATUS, SECRET0_ERROR, 7u, 1u)
+    FIELD(STATUS, SECRET1_ERROR, 8u, 1u)
+    FIELD(STATUS, SECRET2_ERROR, 9u, 1u)
+    FIELD(STATUS, LIFE_CYCLE_ERROR, 10u, 1u)
+    FIELD(STATUS, DAI_ERROR, 11u, 1u)
+    FIELD(STATUS, LCI_ERROR, 12u, 1u)
+    FIELD(STATUS, TIMEOUT_ERROR, 13u, 1u)
+    FIELD(STATUS, LFSR_FSM_ERROR, 14u, 1u)
+    FIELD(STATUS, SCRAMBLING_FSM_ERROR, 15u, 1u)
+    FIELD(STATUS, KEY_DERIV_FSM_ERROR, 16u, 1u)
+    FIELD(STATUS, BUS_INTEG_ERROR, 17u, 1u)
+    FIELD(STATUS, DAI_IDLE, 18u, 1u)
+    FIELD(STATUS, CHECK_PENDING, 19u, 1u)
+REG32(ERR_CODE_0, 0x14u)
+REG32(ERR_CODE_1, 0x18u)
+REG32(ERR_CODE_2, 0x1cu)
+REG32(ERR_CODE_3, 0x20u)
+REG32(ERR_CODE_4, 0x24u)
+REG32(ERR_CODE_5, 0x28u)
+REG32(ERR_CODE_6, 0x2cu)
+REG32(ERR_CODE_7, 0x30u)
+REG32(ERR_CODE_8, 0x34u)
+REG32(ERR_CODE_9, 0x38u)
+REG32(ERR_CODE_10, 0x3cu)
+REG32(ERR_CODE_11, 0x40u)
+REG32(ERR_CODE_12, 0x44u)
+REG32(DIRECT_ACCESS_REGWEN, 0x48u)
+    FIELD(DIRECT_ACCESS_REGWEN, REGWEN, 0u, 1u)
+REG32(DIRECT_ACCESS_CMD, 0x4cu)
+REG32(DIRECT_ACCESS_ADDRESS, 0x50u)
+    FIELD(DIRECT_ACCESS_ADDRESS, ADDRESS, 0, 11u)
+REG32(DIRECT_ACCESS_WDATA_0, 0x54u)
+REG32(DIRECT_ACCESS_WDATA_1, 0x58u)
+REG32(DIRECT_ACCESS_RDATA_0, 0x5cu)
+REG32(DIRECT_ACCESS_RDATA_1, 0x60u)
+REG32(CHECK_TRIGGER_REGWEN, 0x64u)
+    FIELD(CHECK_TRIGGER_REGWEN, REGWEN, 0u, 1u)
+REG32(CHECK_TRIGGER, 0x68u)
+    FIELD(CHECK_TRIGGER, INTEGRITY, 0u, 1u)
+    FIELD(CHECK_TRIGGER, CONSISTENCY, 1u, 1u)
+REG32(CHECK_REGWEN, 0x6cu)
+    FIELD(CHECK_REGWEN, REGWEN, 0u, 1u)
+REG32(CHECK_TIMEOUT, 0x70u)
+REG32(INTEGRITY_CHECK_PERIOD, 0x74u)
+REG32(CONSISTENCY_CHECK_PERIOD, 0x78u)
+REG32(VENDOR_TEST_READ_LOCK, 0x7cu)
+REG32(CREATOR_SW_CFG_READ_LOCK, 0x80u)
+REG32(OWNER_SW_CFG_READ_LOCK, 0x84u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_READ_LOCK, 0x88u)
+REG32(ROT_CREATOR_AUTH_STATE_READ_LOCK, 0x8cu)
+REG32(VENDOR_TEST_DIGEST_0, 0x90u)
+REG32(VENDOR_TEST_DIGEST_1, 0x94u)
+REG32(CREATOR_SW_CFG_DIGEST_0, 0x98u)
+REG32(CREATOR_SW_CFG_DIGEST_1, 0x9cu)
+REG32(OWNER_SW_CFG_DIGEST_0, 0xa0u)
+REG32(OWNER_SW_CFG_DIGEST_1, 0xa4u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_DIGEST_0, 0xa8u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_DIGEST_1, 0xacu)
+REG32(ROT_CREATOR_AUTH_STATE_DIGEST_0, 0xb0u)
+REG32(ROT_CREATOR_AUTH_STATE_DIGEST_1, 0xb4u)
+REG32(HW_CFG0_DIGEST_0, 0xb8u)
+REG32(HW_CFG0_DIGEST_1, 0xbcu)
+REG32(HW_CFG1_DIGEST_0, 0xc0u)
+REG32(HW_CFG1_DIGEST_1, 0xc4u)
+REG32(SECRET0_DIGEST_0, 0xc8u)
+REG32(SECRET0_DIGEST_1, 0xccu)
+REG32(SECRET1_DIGEST_0, 0xd0u)
+REG32(SECRET1_DIGEST_1, 0xd4u)
+REG32(SECRET2_DIGEST_0, 0xd8u)
+REG32(SECRET2_DIGEST_1, 0xdcu)
+
+/* Software Config Window registers (at offset SW_CFG_WINDOW_OFFSET) */
+REG32(VENDOR_TEST_SCRATCH, 0u)
+REG32(VENDOR_TEST_DIGEST, 56u)
+REG32(CREATOR_SW_CFG_AST_CFG, 64u)
+REG32(CREATOR_SW_CFG_AST_INIT_EN, 220u)
+REG32(CREATOR_SW_CFG_ROM_EXT_SKU, 224u)
+REG32(CREATOR_SW_CFG_SIGVERIFY_SPX_EN, 228u)
+REG32(CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG, 232u)
+REG32(CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG, 236u)
+REG32(CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE, 240u)
+REG32(CREATOR_SW_CFG_RNG_EN, 244u)
+REG32(CREATOR_SW_CFG_JITTER_EN, 248u)
+REG32(CREATOR_SW_CFG_RET_RAM_RESET_MASK, 252u)
+REG32(CREATOR_SW_CFG_MANUF_STATE, 256u)
+REG32(CREATOR_SW_CFG_ROM_EXEC_EN, 260u)
+REG32(CREATOR_SW_CFG_CPUCTRL, 264u)
+REG32(CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT, 268u)
+REG32(CREATOR_SW_CFG_MIN_SEC_VER_BL0, 272u)
+REG32(CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN, 276u)
+REG32(CREATOR_SW_CFG_RMA_SPIN_EN, 280u)
+REG32(CREATOR_SW_CFG_RMA_SPIN_CYCLES, 284u)
+REG32(CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS, 288u)
+REG32(CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS, 292u)
+REG32(CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS, 296u)
+REG32(CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS, 300u)
+REG32(CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS, 304u)
+REG32(CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS, 308u)
+REG32(CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS, 312u)
+REG32(CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS, 316u)
+REG32(CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS, 320u)
+REG32(CREATOR_SW_CFG_RNG_ALERT_THRESHOLD, 324u)
+REG32(CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST, 328u)
+REG32(CREATOR_SW_CFG_SRAM_KEY_RENEW_EN, 332u)
+REG32(CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_EN, 336u)
+REG32(CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_START_OFFSET, 340u)
+REG32(CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_LENGTH, 344u)
+REG32(CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH, 348u)
+REG32(CREATOR_SW_CFG_RESERVED, 380u)
+REG32(CREATOR_SW_CFG_DIGEST, 424u)
+REG32(OWNER_SW_CFG_ROM_ERROR_REPORTING, 432u)
+REG32(OWNER_SW_CFG_ROM_BOOTSTRAP_DIS, 436u)
+REG32(OWNER_SW_CFG_ROM_ALERT_CLASS_EN, 440u)
+REG32(OWNER_SW_CFG_ROM_ALERT_ESCALATION, 444u)
+REG32(OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION, 448u)
+REG32(OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION, 768u)
+REG32(OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH, 832u)
+REG32(OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES, 848u)
+REG32(OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES, 864u)
+REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD, 928u)
+REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END, 932u)
+REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV, 936u)
+REG32(OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA, 940u)
+REG32(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES, 944u)
+REG32(OWNER_SW_CFG_ROM_KEYMGR_OTP_MEAS_EN, 948u)
+REG32(OWNER_SW_CFG_MANUF_STATE, 952u)
+REG32(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN, 956u)
+REG32(OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN, 960u)
+REG32(OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG, 964u)
+REG32(OWNER_SW_CFG_ROM_SRAM_READBACK_EN, 976u)
+REG32(OWNER_SW_CFG_ROM_PRESERVE_RESET_REASON_EN, 980u)
+REG32(OWNER_SW_CFG_ROM_RESET_REASON_CHECK_VALUE, 984u)
+REG32(OWNER_SW_CFG_ROM_BANNER_EN, 988u)
+REG32(OWNER_SW_CFG_ROM_FLASH_ECC_EXC_HANDLER_EN, 992u)
+REG32(OWNER_SW_CFG_RESERVED, 996u)
+REG32(OWNER_SW_CFG_DIGEST, 1136u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE0, 1144u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0, 1148u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE1, 1212u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1, 1216u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE2, 1280u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2, 1284u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE3, 1348u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3, 1352u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE0, 1416u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0, 1420u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG0, 1452u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE1, 1456u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1, 1460u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG1, 1492u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE2, 1496u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2, 1500u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG2, 1532u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE3, 1536u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3, 1540u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG3, 1572u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH, 1576u)
+REG32(ROT_CREATOR_AUTH_CODESIGN_DIGEST, 1608u)
+REG32(ROT_CREATOR_AUTH_STATE_ECDSA_KEY0, 1616u)
+REG32(ROT_CREATOR_AUTH_STATE_ECDSA_KEY1, 1620u)
+REG32(ROT_CREATOR_AUTH_STATE_ECDSA_KEY2, 1624u)
+REG32(ROT_CREATOR_AUTH_STATE_ECDSA_KEY3, 1628u)
+REG32(ROT_CREATOR_AUTH_STATE_SPX_KEY0, 1632u)
+REG32(ROT_CREATOR_AUTH_STATE_SPX_KEY1, 1636u)
+REG32(ROT_CREATOR_AUTH_STATE_SPX_KEY2, 1640u)
+REG32(ROT_CREATOR_AUTH_STATE_SPX_KEY3, 1644u)
+REG32(ROT_CREATOR_AUTH_STATE_DIGEST, 1648u)
+REG32(HW_CFG0_DEVICE_ID, 1656u)
+REG32(HW_CFG0_MANUF_STATE, 1688u)
+REG32(HW_CFG0_DIGEST, 1720u)
+REG32(HW_CFG1_EN_SRAM_IFETCH, 1728u)
+REG32(HW_CFG1_EN_CSRNG_SW_APP_READ, 1729u)
+REG32(HW_CFG1_DIS_RV_DM_LATE_DEBUG, 1730u)
+REG32(HW_CFG1_DIGEST, 1736u)
+REG32(SECRET0_TEST_UNLOCK_TOKEN, 1744u)
+REG32(SECRET0_TEST_EXIT_TOKEN, 1760u)
+REG32(SECRET0_DIGEST, 1776u)
+REG32(SECRET1_FLASH_ADDR_KEY_SEED, 1784u)
+REG32(SECRET1_FLASH_DATA_KEY_SEED, 1816u)
+REG32(SECRET1_SRAM_DATA_KEY_SEED, 1848u)
+REG32(SECRET1_DIGEST, 1864u)
+REG32(SECRET2_RMA_TOKEN, 1872u)
+REG32(SECRET2_CREATOR_ROOT_KEY_SHARE0, 1888u)
+REG32(SECRET2_CREATOR_ROOT_KEY_SHARE1, 1920u)
+REG32(SECRET2_DIGEST, 1952u)
+REG32(LC_TRANSITION_CNT, 1960u)
+REG32(LC_STATE, 2008u)
+/* clang-format on */
+
+#define VENDOR_TEST_SCRATCH_SIZE                             56u
+#define CREATOR_SW_CFG_AST_CFG_SIZE                          156u
+#define CREATOR_SW_CFG_AST_INIT_EN_SIZE                      4u
+#define CREATOR_SW_CFG_ROM_EXT_SKU_SIZE                      4u
+#define CREATOR_SW_CFG_SIGVERIFY_SPX_EN_SIZE                 4u
+#define CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG_SIZE           4u
+#define CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG_SIZE         4u
+#define CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE_SIZE       4u
+#define CREATOR_SW_CFG_RNG_EN_SIZE                           4u
+#define CREATOR_SW_CFG_JITTER_EN_SIZE                        4u
+#define CREATOR_SW_CFG_RET_RAM_RESET_MASK_SIZE               4u
+#define CREATOR_SW_CFG_MANUF_STATE_SIZE                      4u
+#define CREATOR_SW_CFG_ROM_EXEC_EN_SIZE                      4u
+#define CREATOR_SW_CFG_CPUCTRL_SIZE                          4u
+#define CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT_SIZE              4u
+#define CREATOR_SW_CFG_MIN_SEC_VER_BL0_SIZE                  4u
+#define CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN_SIZE     4u
+#define CREATOR_SW_CFG_RMA_SPIN_EN_SIZE                      4u
+#define CREATOR_SW_CFG_RMA_SPIN_CYCLES_SIZE                  4u
+#define CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS_SIZE            4u
+#define CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS_SIZE           4u
+#define CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS_SIZE         4u
+#define CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS_SIZE         4u
+#define CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS_SIZE            4u
+#define CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS_SIZE         4u
+#define CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS_SIZE         4u
+#define CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS_SIZE          4u
+#define CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS_SIZE          4u
+#define CREATOR_SW_CFG_RNG_ALERT_THRESHOLD_SIZE              4u
+#define CREATOR_SW_CFG_SRAM_KEY_RENEW_EN_SIZE                4u
+#define CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_EN_SIZE             4u
+#define CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_START_OFFSET_SIZE   4u
+#define CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_LENGTH_SIZE         4u
+#define CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH_SIZE    32u
+#define CREATOR_SW_CFG_RESERVED_SIZE                         32u
+#define OWNER_SW_CFG_ROM_ERROR_REPORTING_SIZE                4u
+#define OWNER_SW_CFG_ROM_BOOTSTRAP_DIS_SIZE                  4u
+#define OWNER_SW_CFG_ROM_ALERT_CLASS_EN_SIZE                 4u
+#define OWNER_SW_CFG_ROM_ALERT_ESCALATION_SIZE               4u
+#define OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION_SIZE           320u
+#define OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION_SIZE     64u
+#define OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH_SIZE             16u
+#define OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES_SIZE           16u
+#define OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES_SIZE             64u
+#define OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_SIZE              4u
+#define OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END_SIZE          4u
+#define OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV_SIZE               4u
+#define OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA_SIZE               4u
+#define OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES_SIZE 4u
+#define OWNER_SW_CFG_ROM_KEYMGR_OTP_MEAS_EN_SIZE             4u
+#define OWNER_SW_CFG_MANUF_STATE_SIZE                        4u
+#define OWNER_SW_CFG_ROM_RSTMGR_INFO_EN_SIZE                 4u
+#define OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN_SIZE               4u
+#define OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG_SIZE          12u
+#define OWNER_SW_CFG_ROM_SRAM_READBACK_EN_SIZE               4u
+#define OWNER_SW_CFG_ROM_PRESERVE_RESET_REASON_EN_SIZE       4u
+#define OWNER_SW_CFG_ROM_RESET_REASON_CHECK_VALUE_SIZE       4u
+#define OWNER_SW_CFG_ROM_BANNER_EN_SIZE                      4u
+#define OWNER_SW_CFG_ROM_FLASH_ECC_EXC_HANDLER_EN_SIZE       4u
+#define OWNER_SW_CFG_RESERVED_SIZE                           128u
+#define ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE0_SIZE       4u
+#define ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0_SIZE            64u
+#define ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE1_SIZE       4u
+#define ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1_SIZE            64u
+#define ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE2_SIZE       4u
+#define ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2_SIZE            64u
+#define ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE3_SIZE       4u
+#define ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3_SIZE            64u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE0_SIZE         4u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0_SIZE              32u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG0_SIZE       4u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE1_SIZE         4u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1_SIZE              32u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG1_SIZE       4u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE2_SIZE         4u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2_SIZE              32u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG2_SIZE       4u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE3_SIZE         4u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3_SIZE              32u
+#define ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG3_SIZE       4u
+#define ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH_SIZE   32u
+#define ROT_CREATOR_AUTH_STATE_ECDSA_KEY0_SIZE               4u
+#define ROT_CREATOR_AUTH_STATE_ECDSA_KEY1_SIZE               4u
+#define ROT_CREATOR_AUTH_STATE_ECDSA_KEY2_SIZE               4u
+#define ROT_CREATOR_AUTH_STATE_ECDSA_KEY3_SIZE               4u
+#define ROT_CREATOR_AUTH_STATE_SPX_KEY0_SIZE                 4u
+#define ROT_CREATOR_AUTH_STATE_SPX_KEY1_SIZE                 4u
+#define ROT_CREATOR_AUTH_STATE_SPX_KEY2_SIZE                 4u
+#define ROT_CREATOR_AUTH_STATE_SPX_KEY3_SIZE                 4u
+#define HW_CFG0_DEVICE_ID_SIZE                               32u
+#define HW_CFG0_MANUF_STATE_SIZE                             32u
+#define HW_CFG1_EN_SRAM_IFETCH_SIZE                          1u
+#define HW_CFG1_EN_CSRNG_SW_APP_READ_SIZE                    1u
+#define HW_CFG1_DIS_RV_DM_LATE_DEBUG_SIZE                    1u
+#define SECRET0_TEST_UNLOCK_TOKEN_SIZE                       16u
+#define SECRET0_TEST_EXIT_TOKEN_SIZE                         16u
+#define SECRET1_FLASH_ADDR_KEY_SEED_SIZE                     32u
+#define SECRET1_FLASH_DATA_KEY_SEED_SIZE                     32u
+#define SECRET1_SRAM_DATA_KEY_SEED_SIZE                      16u
+#define SECRET2_RMA_TOKEN_SIZE                               16u
+#define SECRET2_CREATOR_ROOT_KEY_SHARE0_SIZE                 32u
+#define SECRET2_CREATOR_ROOT_KEY_SHARE1_SIZE                 32u
+
+#define SW_CFG_WINDOW_OFFSET 0x800u
+#define SW_CFG_WINDOW_SIZE   (NUM_SW_CFG_WINDOW_WORDS * sizeof(uint32_t))
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_SECRET2_DIGEST_1)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+/* note: useless casts are required for GCC linter */
+static_assert((unsigned)R_STATUS == (unsigned)R_OTP_FIRST_IMPL_REG,
+              "Invalid register address");
+
+typedef enum {
+    OTP_PART_VENDOR_TEST,
+    OTP_PART_CREATOR_SW_CFG,
+    OTP_PART_OWNER_SW_CFG,
+    OTP_PART_ROT_CREATOR_AUTH_CODESIGN,
+    OTP_PART_ROT_CREATOR_AUTH_STATE,
+    OTP_PART_HW_CFG0,
+    OTP_PART_HW_CFG1,
+    OTP_PART_SECRET0,
+    OTP_PART_SECRET1,
+    OTP_PART_SECRET2,
+    OTP_PART_LIFE_CYCLE,
+    OTP_PART_OTP_COUNT, /* count of "real" OTP partitions */
+    OTP_ENTRY_DAI = OTP_PART_OTP_COUNT, /* Fake partitions for error (...) */
+    OTP_ENTRY_KDI, /* Key derivation issue, not really OTP */
+    OTP_ENTRY_COUNT,
+} OtOTPPartitionType;
+
+static_assert(OTP_PART_OTP_COUNT == NUM_PART, "Invalid partition count");
+
+#define OT_OTP_EG_PARTS
+
+/* NOLINTNEXTLINE */
+#include "ot_otp_eg_parts.c"
+
+static_assert(OTP_PART_OTP_COUNT == OTP_PART_COUNT, "Invalid partition count");
+static_assert(OTP_PART_COUNT <= 64, "Maximum part count reached");
+
+static_assert(OTP_BYTE_ADDR_WIDTH == R_DIRECT_ACCESS_ADDRESS_ADDRESS_LENGTH,
+              "OTP byte address width mismatch");
+struct OtOTPEgState {
+    OtOTPEngineState parent_obj;
+
+    struct {
+        MemoryRegion ctrl;
+        struct {
+            MemoryRegion regs;
+            MemoryRegion swcfg;
+        } sub;
+    } mmio;
+};
+
+struct OtOTPEgClass {
+    OtOTPEngineClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(ERR_CODE_0),
+    REG_NAME_ENTRY(ERR_CODE_1),
+    REG_NAME_ENTRY(ERR_CODE_2),
+    REG_NAME_ENTRY(ERR_CODE_3),
+    REG_NAME_ENTRY(ERR_CODE_4),
+    REG_NAME_ENTRY(ERR_CODE_5),
+    REG_NAME_ENTRY(ERR_CODE_6),
+    REG_NAME_ENTRY(ERR_CODE_7),
+    REG_NAME_ENTRY(ERR_CODE_8),
+    REG_NAME_ENTRY(ERR_CODE_9),
+    REG_NAME_ENTRY(ERR_CODE_10),
+    REG_NAME_ENTRY(ERR_CODE_11),
+    REG_NAME_ENTRY(ERR_CODE_12),
+    REG_NAME_ENTRY(DIRECT_ACCESS_REGWEN),
+    REG_NAME_ENTRY(DIRECT_ACCESS_CMD),
+    REG_NAME_ENTRY(DIRECT_ACCESS_ADDRESS),
+    REG_NAME_ENTRY(DIRECT_ACCESS_WDATA_0),
+    REG_NAME_ENTRY(DIRECT_ACCESS_WDATA_1),
+    REG_NAME_ENTRY(DIRECT_ACCESS_RDATA_0),
+    REG_NAME_ENTRY(DIRECT_ACCESS_RDATA_1),
+    REG_NAME_ENTRY(CHECK_TRIGGER_REGWEN),
+    REG_NAME_ENTRY(CHECK_TRIGGER),
+    REG_NAME_ENTRY(CHECK_REGWEN),
+    REG_NAME_ENTRY(CHECK_TIMEOUT),
+    REG_NAME_ENTRY(INTEGRITY_CHECK_PERIOD),
+    REG_NAME_ENTRY(CONSISTENCY_CHECK_PERIOD),
+    REG_NAME_ENTRY(VENDOR_TEST_READ_LOCK),
+    REG_NAME_ENTRY(CREATOR_SW_CFG_READ_LOCK),
+    REG_NAME_ENTRY(OWNER_SW_CFG_READ_LOCK),
+    REG_NAME_ENTRY(ROT_CREATOR_AUTH_CODESIGN_READ_LOCK),
+    REG_NAME_ENTRY(ROT_CREATOR_AUTH_STATE_READ_LOCK),
+    REG_NAME_ENTRY(VENDOR_TEST_DIGEST_0),
+    REG_NAME_ENTRY(VENDOR_TEST_DIGEST_1),
+    REG_NAME_ENTRY(CREATOR_SW_CFG_DIGEST_0),
+    REG_NAME_ENTRY(CREATOR_SW_CFG_DIGEST_1),
+    REG_NAME_ENTRY(OWNER_SW_CFG_DIGEST_0),
+    REG_NAME_ENTRY(OWNER_SW_CFG_DIGEST_1),
+    REG_NAME_ENTRY(ROT_CREATOR_AUTH_CODESIGN_DIGEST_0),
+    REG_NAME_ENTRY(ROT_CREATOR_AUTH_CODESIGN_DIGEST_1),
+    REG_NAME_ENTRY(ROT_CREATOR_AUTH_STATE_DIGEST_0),
+    REG_NAME_ENTRY(ROT_CREATOR_AUTH_STATE_DIGEST_1),
+    REG_NAME_ENTRY(HW_CFG0_DIGEST_0),
+    REG_NAME_ENTRY(HW_CFG0_DIGEST_1),
+    REG_NAME_ENTRY(HW_CFG1_DIGEST_0),
+    REG_NAME_ENTRY(HW_CFG1_DIGEST_1),
+    REG_NAME_ENTRY(SECRET0_DIGEST_0),
+    REG_NAME_ENTRY(SECRET0_DIGEST_1),
+    REG_NAME_ENTRY(SECRET1_DIGEST_0),
+    REG_NAME_ENTRY(SECRET1_DIGEST_1),
+    REG_NAME_ENTRY(SECRET2_DIGEST_0),
+    REG_NAME_ENTRY(SECRET2_DIGEST_1),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+#define OT_OTP_NAME_ENTRY(_st_) [OT_OTP_##_st_] = stringify(OT_OTP_##_st_)
+
+static const char *OTP_TOKEN_NAMES[] = {
+    /* clang-format off */
+    OT_OTP_NAME_ENTRY(TOKEN_TEST_UNLOCK),
+    OT_OTP_NAME_ENTRY(TOKEN_TEST_EXIT),
+    OT_OTP_NAME_ENTRY(TOKEN_RMA),
+    /* clang-format on */
+};
+
+#define OTP_TOKEN_NAME(_tk_) \
+    ((unsigned)(_tk_) < ARRAY_SIZE(OTP_TOKEN_NAMES) ? \
+         OTP_TOKEN_NAMES[(_tk_)] : \
+         "?")
+
+static uint32_t ot_otp_eg_get_status(const OtOTPEngineState *s)
+{
+    uint32_t status;
+
+    status = FIELD_DP32(s->regs[R_STATUS], STATUS, DAI_IDLE,
+                        !ot_otp_engine_dai_is_busy(s));
+
+    return status;
+}
+
+static uint64_t ot_otp_eg_reg_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(opaque);
+    OtOTPEngineClass *c = OT_OTP_ENGINE_GET_CLASS(s);
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_ERR_CODE_0 ... R_ERR_CODE_12:
+    case R_DIRECT_ACCESS_WDATA_0:
+    case R_DIRECT_ACCESS_WDATA_1:
+    case R_DIRECT_ACCESS_RDATA_0:
+    case R_DIRECT_ACCESS_RDATA_1:
+    case R_DIRECT_ACCESS_ADDRESS:
+    case R_VENDOR_TEST_READ_LOCK ... R_ROT_CREATOR_AUTH_STATE_READ_LOCK:
+    case R_CHECK_TRIGGER_REGWEN:
+    case R_CHECK_REGWEN:
+        val32 = s->regs[reg];
+        break;
+    case R_STATUS:
+        val32 = ot_otp_eg_get_status(s);
+        break;
+    case R_DIRECT_ACCESS_REGWEN:
+        /* disabled either if SW locked, or if DAI is busy. */
+        val32 = s->regs[reg];
+        val32 &= FIELD_DP32(0u, DIRECT_ACCESS_REGWEN, REGWEN,
+                            (uint32_t)!ot_otp_engine_dai_is_busy(s));
+        break;
+    /* NOLINTNEXTLINE */
+    case R_DIRECT_ACCESS_CMD:
+    case R_CHECK_TRIGGER:
+        val32 = 0; /* R0W1C */
+        break;
+    case R_CHECK_TIMEOUT:
+    case R_INTEGRITY_CHECK_PERIOD:
+    case R_CONSISTENCY_CHECK_PERIOD:
+        /* @todo: not yet implemented, but these are R/W registers */
+        qemu_log_mask(LOG_UNIMP, "%s: %s: %s is not supported\n", __func__,
+                      s->ot_id, REG_NAME(reg));
+        val32 = s->regs[reg];
+        break;
+    case R_VENDOR_TEST_DIGEST_0 ... R_SECRET2_DIGEST_1:
+        /*
+         * In all partitions with a digest, the digest itself is ALWAYS
+         * readable.
+         */
+        val32 = c->get_part_digest_reg(s, reg - R_VENDOR_TEST_DIGEST_0);
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x03%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_otp_io_reg_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                                 pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_otp_eg_reg_write(void *opaque, hwaddr addr, uint64_t value,
+                                unsigned size)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(opaque);
+    OtOTPEngineClass *c = OT_OTP_ENGINE_GET_CLASS(s);
+    (void)size;
+    uint32_t val32 = (uint32_t)value;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+
+    trace_ot_otp_io_reg_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                              pc);
+
+    switch (reg) {
+    case R_DIRECT_ACCESS_CMD:
+    case R_DIRECT_ACCESS_ADDRESS:
+    case R_DIRECT_ACCESS_WDATA_0:
+    case R_DIRECT_ACCESS_WDATA_1:
+    case R_VENDOR_TEST_READ_LOCK ... R_ROT_CREATOR_AUTH_STATE_READ_LOCK:
+        if (!(s->regs[R_DIRECT_ACCESS_REGWEN] &
+              R_DIRECT_ACCESS_REGWEN_REGWEN_MASK)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: %s is not enabled, %s is protected\n",
+                          __func__, s->ot_id, REG_NAME(R_DIRECT_ACCESS_REGWEN),
+                          REG_NAME(reg));
+            return;
+        }
+        break;
+    case R_CHECK_TRIGGER:
+        if (!(s->regs[R_CHECK_TRIGGER_REGWEN] &
+              R_CHECK_TRIGGER_REGWEN_REGWEN_MASK)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: %s is not enabled, %s is protected\n",
+                          __func__, s->ot_id, REG_NAME(R_CHECK_TRIGGER_REGWEN),
+                          REG_NAME(reg));
+            return;
+        }
+        break;
+    case R_CHECK_TIMEOUT:
+    case R_INTEGRITY_CHECK_PERIOD:
+    case R_CONSISTENCY_CHECK_PERIOD:
+        if (!(s->regs[R_CHECK_REGWEN] & R_CHECK_REGWEN_REGWEN_MASK)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: %s is not enabled, %s is protected\n",
+                          __func__, s->ot_id, REG_NAME(R_CHECK_REGWEN),
+                          REG_NAME(reg));
+            return;
+        }
+        break;
+    case R_STATUS:
+    case R_ERR_CODE_0 ... R_ERR_CODE_12:
+    case R_DIRECT_ACCESS_RDATA_0:
+    case R_DIRECT_ACCESS_RDATA_1:
+    case R_VENDOR_TEST_DIGEST_0 ... R_SECRET2_DIGEST_1:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%03x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        return;
+    default:
+        break;
+    }
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_WMASK;
+        s->regs[R_INTR_STATE] &= ~val32; /* RW1C */
+        c->update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_WMASK;
+        s->regs[R_INTR_ENABLE] = val32;
+        c->update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_WMASK;
+        s->regs[R_INTR_STATE] = val32;
+        c->update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_WMASK;
+        s->regs[reg] = val32;
+        c->update_alerts(s);
+        break;
+    case R_DIRECT_ACCESS_REGWEN:
+        val32 &= R_DIRECT_ACCESS_REGWEN_REGWEN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_DIRECT_ACCESS_CMD:
+        if (FIELD_EX32(val32, OT_OTP_DIRECT_ACCESS_CMD, RD)) {
+            c->dai_read(s);
+        } else if (FIELD_EX32(val32, OT_OTP_DIRECT_ACCESS_CMD, WR)) {
+            c->dai_write(s);
+        } else if (FIELD_EX32(val32, OT_OTP_DIRECT_ACCESS_CMD, DIGEST)) {
+            c->dai_digest(s);
+        }
+        break;
+    case R_DIRECT_ACCESS_ADDRESS:
+        val32 &= R_DIRECT_ACCESS_ADDRESS_ADDRESS_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_DIRECT_ACCESS_WDATA_0:
+    case R_DIRECT_ACCESS_WDATA_1:
+        s->regs[reg] = val32;
+        break;
+    case R_VENDOR_TEST_READ_LOCK ... R_ROT_CREATOR_AUTH_STATE_READ_LOCK:
+        val32 &= OT_OTP_READ_LOCK_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CHECK_TRIGGER_REGWEN:
+        val32 &= R_CHECK_TRIGGER_REGWEN_REGWEN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CHECK_REGWEN:
+        val32 &= R_CHECK_REGWEN_REGWEN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CHECK_TRIGGER:
+    case R_CHECK_TIMEOUT:
+    case R_INTEGRITY_CHECK_PERIOD:
+    case R_CONSISTENCY_CHECK_PERIOD:
+        qemu_log_mask(LOG_UNIMP, "%s: %s: %s is not supported\n", __func__,
+                      s->ot_id, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static const char *ot_otp_eg_swcfg_reg_name(unsigned swreg)
+{
+#define CASE_BYTE(_reg_) \
+    case A_##_reg_: \
+        return stringify(_reg_)
+#define CASE_SUB(_reg_, _sz_) \
+    case A_##_reg_...(A_##_reg_ + (_sz_) - 1u): \
+        return stringify(_reg_)
+#define CASE_REG(_reg_) \
+    case A_##_reg_...(A_##_reg_ + 3u): \
+        return stringify(_reg_)
+#define CASE_WIDE(_reg_) \
+    case A_##_reg_...(A_##_reg_ + 7u): \
+        return stringify(_reg_)
+#define CASE_RANGE(_reg_) \
+    case A_##_reg_...(A_##_reg_ + (_reg_##_SIZE) - 1u): \
+        return stringify(_reg_)
+
+    switch (swreg) {
+        CASE_RANGE(VENDOR_TEST_SCRATCH);
+        CASE_WIDE(VENDOR_TEST_DIGEST);
+        CASE_RANGE(CREATOR_SW_CFG_AST_CFG);
+        CASE_REG(CREATOR_SW_CFG_AST_INIT_EN);
+        CASE_REG(CREATOR_SW_CFG_ROM_EXT_SKU);
+        CASE_REG(CREATOR_SW_CFG_SIGVERIFY_SPX_EN);
+        CASE_REG(CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG);
+        CASE_REG(CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG);
+        CASE_REG(CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE);
+        CASE_REG(CREATOR_SW_CFG_RNG_EN);
+        CASE_REG(CREATOR_SW_CFG_JITTER_EN);
+        CASE_REG(CREATOR_SW_CFG_RET_RAM_RESET_MASK);
+        CASE_REG(CREATOR_SW_CFG_MANUF_STATE);
+        CASE_REG(CREATOR_SW_CFG_ROM_EXEC_EN);
+        CASE_REG(CREATOR_SW_CFG_CPUCTRL);
+        CASE_REG(CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT);
+        CASE_REG(CREATOR_SW_CFG_MIN_SEC_VER_BL0);
+        CASE_REG(CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN);
+        CASE_REG(CREATOR_SW_CFG_RMA_SPIN_EN);
+        CASE_REG(CREATOR_SW_CFG_RMA_SPIN_CYCLES);
+        CASE_REG(CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS);
+        CASE_REG(CREATOR_SW_CFG_RNG_ALERT_THRESHOLD);
+        CASE_REG(CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST);
+        CASE_REG(CREATOR_SW_CFG_SRAM_KEY_RENEW_EN);
+        CASE_REG(CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_EN);
+        CASE_REG(CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_START_OFFSET);
+        CASE_REG(CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_LENGTH);
+        CASE_RANGE(CREATOR_SW_CFG_IMMUTABLE_ROM_EXT_SHA256_HASH);
+        CASE_RANGE(CREATOR_SW_CFG_RESERVED);
+        CASE_WIDE(CREATOR_SW_CFG_DIGEST);
+        CASE_REG(OWNER_SW_CFG_ROM_ERROR_REPORTING);
+        CASE_REG(OWNER_SW_CFG_ROM_BOOTSTRAP_DIS);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_CLASS_EN);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_ESCALATION);
+        CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION);
+        CASE_RANGE(OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION);
+        CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH);
+        CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES);
+        CASE_RANGE(OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV);
+        CASE_REG(OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA);
+        CASE_REG(OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES);
+        CASE_REG(OWNER_SW_CFG_ROM_KEYMGR_OTP_MEAS_EN);
+        CASE_REG(OWNER_SW_CFG_MANUF_STATE);
+        CASE_REG(OWNER_SW_CFG_ROM_RSTMGR_INFO_EN);
+        CASE_REG(OWNER_SW_CFG_ROM_EXT_BOOTSTRAP_EN);
+        CASE_RANGE(OWNER_SW_CFG_ROM_SENSOR_CTRL_ALERT_CFG);
+        CASE_REG(OWNER_SW_CFG_ROM_SRAM_READBACK_EN);
+        CASE_REG(OWNER_SW_CFG_ROM_PRESERVE_RESET_REASON_EN);
+        CASE_REG(OWNER_SW_CFG_ROM_RESET_REASON_CHECK_VALUE);
+        CASE_REG(OWNER_SW_CFG_ROM_BANNER_EN);
+        CASE_REG(OWNER_SW_CFG_ROM_FLASH_ECC_EXC_HANDLER_EN);
+        CASE_RANGE(OWNER_SW_CFG_RESERVED);
+        CASE_WIDE(OWNER_SW_CFG_DIGEST);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE0);
+        CASE_RANGE(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY0);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE1);
+        CASE_RANGE(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY1);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE2);
+        CASE_RANGE(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY2);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY_TYPE3);
+        CASE_RANGE(ROT_CREATOR_AUTH_CODESIGN_ECDSA_KEY3);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE0);
+        CASE_RANGE(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY0);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG0);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE1);
+        CASE_RANGE(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY1);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG1);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE2);
+        CASE_RANGE(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY2);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG2);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_TYPE3);
+        CASE_RANGE(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY3);
+        CASE_REG(ROT_CREATOR_AUTH_CODESIGN_SPX_KEY_CONFIG3);
+        CASE_RANGE(ROT_CREATOR_AUTH_CODESIGN_BLOCK_SHA2_256_HASH);
+        CASE_WIDE(ROT_CREATOR_AUTH_CODESIGN_DIGEST);
+        CASE_REG(ROT_CREATOR_AUTH_STATE_ECDSA_KEY0);
+        CASE_REG(ROT_CREATOR_AUTH_STATE_ECDSA_KEY1);
+        CASE_REG(ROT_CREATOR_AUTH_STATE_ECDSA_KEY2);
+        CASE_REG(ROT_CREATOR_AUTH_STATE_ECDSA_KEY3);
+        CASE_REG(ROT_CREATOR_AUTH_STATE_SPX_KEY0);
+        CASE_REG(ROT_CREATOR_AUTH_STATE_SPX_KEY1);
+        CASE_REG(ROT_CREATOR_AUTH_STATE_SPX_KEY2);
+        CASE_REG(ROT_CREATOR_AUTH_STATE_SPX_KEY3);
+        CASE_WIDE(ROT_CREATOR_AUTH_STATE_DIGEST);
+        CASE_RANGE(HW_CFG0_DEVICE_ID);
+        CASE_RANGE(HW_CFG0_MANUF_STATE);
+        CASE_WIDE(HW_CFG0_DIGEST);
+        CASE_BYTE(HW_CFG1_EN_SRAM_IFETCH);
+        CASE_BYTE(HW_CFG1_EN_CSRNG_SW_APP_READ);
+        CASE_BYTE(HW_CFG1_DIS_RV_DM_LATE_DEBUG);
+        CASE_WIDE(HW_CFG1_DIGEST);
+        CASE_RANGE(SECRET0_TEST_UNLOCK_TOKEN);
+        CASE_RANGE(SECRET0_TEST_EXIT_TOKEN);
+        CASE_WIDE(SECRET0_DIGEST);
+        CASE_RANGE(SECRET1_FLASH_ADDR_KEY_SEED);
+        CASE_RANGE(SECRET1_FLASH_DATA_KEY_SEED);
+        CASE_RANGE(SECRET1_SRAM_DATA_KEY_SEED);
+        CASE_WIDE(SECRET1_DIGEST);
+        CASE_RANGE(SECRET2_RMA_TOKEN);
+        CASE_RANGE(SECRET2_CREATOR_ROOT_KEY_SHARE0);
+        CASE_RANGE(SECRET2_CREATOR_ROOT_KEY_SHARE1);
+        CASE_WIDE(SECRET2_DIGEST);
+        CASE_RANGE(LC_TRANSITION_CNT);
+        CASE_RANGE(LC_STATE);
+    default:
+        return "<?>";
+    }
+
+#undef CASE_BYTE
+#undef CASE_SUB
+#undef CASE_REG
+#undef CASE_RANGE
+#undef CASE_DIGEST
+}
+
+static MemTxResult ot_otp_eg_swcfg_read_with_attrs(
+    void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(opaque);
+    OtOTPEngineClass *c = OT_OTP_ENGINE_GET_CLASS(s);
+    (void)size;
+    (void)attrs;
+
+    hwaddr reg = R32_OFF(addr);
+    int partition = c->get_part_from_address(s, addr);
+
+    if (partition < 0) {
+        trace_ot_otp_access_error_on(s->ot_id, partition, addr, "invalid");
+        *data = 0ull;
+
+        return MEMTX_DECODE_ERROR;
+    }
+
+    unsigned part_ix = (unsigned)partition;
+
+    if (ot_otp_engine_is_buffered(s, part_ix)) {
+        trace_ot_otp_access_error_on(s->ot_id, partition, addr, "buffered");
+        c->set_error(s, part_ix, OT_OTP_ACCESS_ERROR);
+
+        /* real HW seems to stall the Tile Link bus in this case */
+        return MEMTX_ACCESS_ERROR;
+    }
+
+    bool is_readable = c->is_readable(s, part_ix);
+    bool is_digest = ot_otp_engine_is_part_digest_offset(s, part_ix, addr);
+    bool is_zer = ot_otp_engine_is_part_zer_offset(s, part_ix, addr);
+
+    if (!is_readable && !(is_digest || is_zer)) {
+        trace_ot_otp_access_error_on(s->ot_id, partition, addr, "not readable");
+        c->set_error(s, part_ix, OT_OTP_ACCESS_ERROR);
+
+        return MEMTX_DECODE_ERROR;
+    }
+
+    uint32_t val32 = s->otp->data[reg];
+    c->set_error(s, part_ix, OT_OTP_NO_ERROR);
+
+    uint64_t pc;
+
+    pc = ibex_get_current_pc();
+    trace_ot_otp_io_swcfg_read_out(s->ot_id, (uint32_t)addr,
+                                   ot_otp_eg_swcfg_reg_name(addr), val32, pc);
+
+    *data = (uint64_t)val32;
+
+    return MEMTX_OK;
+}
+
+static void ot_otp_eg_get_lc_info(
+    const OtOTPIf *dev, uint16_t *lc_tcount, uint16_t *lc_state,
+    uint8_t *lc_valid, uint8_t *secret_valid, const OtOTPTokens **tokens)
+{
+    const OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+    const OtOTPStorage *otp = s->otp;
+
+    if (lc_tcount) {
+        memcpy(lc_tcount, &otp->data[R_LC_TRANSITION_CNT],
+               LC_TRANSITION_CNT_SIZE);
+    }
+
+    if (lc_state) {
+        memcpy(lc_state, &otp->data[R_LC_STATE], LC_STATE_SIZE);
+    }
+
+    if (lc_valid) {
+        *lc_valid = !(s->part_ctrls[OTP_PART_SECRET0].failed ||
+                      s->part_ctrls[OTP_PART_SECRET2].failed ||
+                      s->part_ctrls[s->part_lc_num].failed) ?
+                        OT_MULTIBITBOOL_LC4_TRUE :
+                        OT_MULTIBITBOOL_LC4_FALSE;
+    }
+    if (secret_valid) {
+        *secret_valid = (!s->part_ctrls[OTP_PART_SECRET2].failed &&
+                         s->part_ctrls[OTP_PART_SECRET2].locked) ?
+                            OT_MULTIBITBOOL_LC4_TRUE :
+                            OT_MULTIBITBOOL_LC4_FALSE;
+    }
+    if (tokens) {
+        *tokens = s->tokens;
+    }
+}
+static void ot_otp_eg_get_keymgr_secret(
+    OtOTPIf *dev, OtOTPKeyMgrSecretType type, OtOTPKeyMgrSecret *secret)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+    int partition;
+    size_t offset;
+
+    switch (type) {
+    case OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE0:
+        partition = OTP_PART_SECRET2;
+        offset =
+            A_SECRET2_CREATOR_ROOT_KEY_SHARE0 - s->part_descs[partition].offset;
+        break;
+    case OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE1:
+        partition = OTP_PART_SECRET2;
+        offset =
+            A_SECRET2_CREATOR_ROOT_KEY_SHARE1 - s->part_descs[partition].offset;
+        break;
+    case OT_OTP_KEYMGR_SECRET_CREATOR_SEED:
+    case OT_OTP_KEYMGR_SECRET_OWNER_SEED:
+    default:
+        error_report("%s: %s: invalid OTP keymgr secret type: %d", __func__,
+                     s->ot_id, type);
+        secret->valid = false;
+        memset(secret->secret, 0, OT_OTP_KEYMGR_SECRET_SIZE);
+        return;
+    }
+
+    unsigned part_ix = (unsigned)partition;
+    g_assert(ot_otp_engine_is_buffered(s, part_ix));
+
+    const uint8_t *data_ptr;
+    if (s->lc_broadcast.current_level & BIT(OT_OTP_LC_SEED_HW_RD_EN)) {
+        data_ptr = (const uint8_t *)s->part_ctrls[part_ix].buffer.data;
+    } else {
+        /* source data from PartInvDefault instead of real buffer */
+        OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+        data_ptr = pctrl->inv_default_data;
+    }
+
+    secret->valid = s->part_ctrls[part_ix].digest != 0;
+    memcpy(secret->secret, &data_ptr[offset], OT_OTP_KEYMGR_SECRET_SIZE);
+}
+
+static void
+ot_otp_eg_update_status_error(OtOTPImplIf *dev, OtOTPStatus error, bool set)
+{
+    const OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+
+    uint32_t mask;
+    switch (error) {
+    case OT_OTP_STATUS_DAI:
+        mask = R_STATUS_DAI_ERROR_MASK;
+        break;
+    case OT_OTP_STATUS_LCI:
+        mask = R_STATUS_LCI_ERROR_MASK;
+        break;
+    default:
+        g_assert_not_reached();
+        return;
+    }
+
+    if (set) {
+        s->regs[R_STATUS] |= mask;
+    } else {
+        s->regs[R_STATUS] &= ~mask;
+    }
+}
+
+static void ot_otp_eg_pwr_load_hw_cfg(OtOTPEngineState *s)
+{
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(s);
+
+    const OtOTPPartDesc *pdesc0 = &ic->part_descs[OTP_PART_HW_CFG0];
+    const OtOTPPartDesc *pdesc1 = &ic->part_descs[OTP_PART_HW_CFG1];
+    const OtOTPPartController *pctrl0 = &s->part_ctrls[OTP_PART_HW_CFG0];
+    const OtOTPPartController *pctrl1 = &s->part_ctrls[OTP_PART_HW_CFG1];
+    const uint8_t *pdata0 = (const uint8_t *)pctrl0->buffer.data;
+    const uint8_t *pdata1 = (const uint8_t *)pctrl1->buffer.data;
+
+    OtOTPHWCfg *hw_cfg = s->hw_cfg;
+
+    memcpy(hw_cfg->device_id, &pdata0[A_HW_CFG0_DEVICE_ID - pdesc0->offset],
+           sizeof(hw_cfg->device_id));
+    memcpy(hw_cfg->manuf_state, &pdata0[A_HW_CFG0_MANUF_STATE - pdesc0->offset],
+           sizeof(hw_cfg->manuf_state));
+    /* do not prevent execution from SRAM if no OTP configuration is loaded */
+    hw_cfg->en_sram_ifetch_mb8 =
+        s->blk ? pdata1[A_HW_CFG1_EN_SRAM_IFETCH - pdesc1->offset] :
+                 OT_MULTIBITBOOL8_TRUE;
+    /* do not prevent CSRNG app reads if no OTP configuration is loaded */
+    hw_cfg->en_csrng_sw_app_read_mb8 =
+        s->blk ? pdata1[A_HW_CFG1_EN_CSRNG_SW_APP_READ - pdesc1->offset] :
+                 OT_MULTIBITBOOL8_TRUE;
+}
+
+static void ot_otp_eg_pwr_load_tokens(OtOTPEngineState *s)
+{
+    memset(s->tokens, 0, sizeof(*s->tokens));
+
+    OtOTPTokens *tokens = s->tokens;
+
+    static_assert(sizeof(OtOTPTokenValue) == 16u, "Invalid token size");
+
+    for (unsigned tkx = 0; tkx < OT_OTP_TOKEN_COUNT; tkx++) {
+        unsigned partition;
+        uint32_t secret_addr;
+
+        switch (tkx) {
+        case OT_OTP_TOKEN_TEST_UNLOCK:
+            partition = (unsigned)OTP_PART_SECRET0;
+            secret_addr = A_SECRET0_TEST_UNLOCK_TOKEN;
+            break;
+        case OT_OTP_TOKEN_TEST_EXIT:
+            partition = (unsigned)OTP_PART_SECRET0;
+            secret_addr = A_SECRET0_TEST_EXIT_TOKEN;
+            break;
+        case OT_OTP_TOKEN_RMA:
+            partition = (unsigned)OTP_PART_SECRET2;
+            secret_addr = A_SECRET2_RMA_TOKEN;
+            break;
+        default:
+            g_assert_not_reached();
+            break;
+        }
+
+        OtOTPPartController *pctrl = &s->part_ctrls[partition];
+        g_assert(pctrl->buffer.data != NULL);
+
+        /* byte offset of the secret within the partition */
+        unsigned secret_offset =
+            secret_addr - ot_otp_engine_part_data_offset(s, partition);
+        g_assert(secret_offset + sizeof(OtOTPTokenValue) <=
+                 OT_OTP_PART_DESCS[partition].size);
+
+        OtOTPTokenValue value;
+        memcpy(&value, &pctrl->buffer.data[secret_offset / sizeof(uint32_t)],
+               sizeof(OtOTPTokenValue));
+
+        if (s->part_ctrls[partition].locked) {
+            tokens->values[tkx] = value;
+            tokens->valid_bm |= 1u << tkx;
+        }
+        trace_ot_otp_load_token(s->ot_id, OTP_TOKEN_NAME(tkx), tkx, value.hi,
+                                value.lo,
+                                (s->tokens->valid_bm & (1u << tkx)) ? "" :
+                                                                      "in");
+    }
+}
+
+static void ot_otp_eg_signal_pwr_sequence(OtOTPImplIf *dev)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+
+    ot_otp_eg_pwr_load_hw_cfg(s);
+    ot_otp_eg_pwr_load_tokens(s);
+}
+
+static const MemoryRegionOps ot_otp_eg_reg_ops = {
+    .read = &ot_otp_eg_reg_read,
+    .write = &ot_otp_eg_reg_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const MemoryRegionOps ot_otp_eg_swcfg_ops = {
+    .read_with_attrs = &ot_otp_eg_swcfg_read_with_attrs,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static void ot_otp_eg_reset_enter(Object *obj, ResetType type)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(obj);
+    OtOTPEgClass *dc = OT_OTP_EG_GET_CLASS(obj);
+
+    memset(s->regs, 0, REGS_SIZE);
+
+    s->regs[R_DIRECT_ACCESS_REGWEN] = 0x1u;
+    s->regs[R_CHECK_TRIGGER_REGWEN] = 0x1u;
+    s->regs[R_CHECK_REGWEN] = 0x1u;
+    s->regs[R_VENDOR_TEST_READ_LOCK] = 0x1u;
+    s->regs[R_CREATOR_SW_CFG_READ_LOCK] = 0x1u;
+    s->regs[R_OWNER_SW_CFG_READ_LOCK] = 0x1u;
+    s->regs[R_ROT_CREATOR_AUTH_CODESIGN_READ_LOCK] = 0x1u;
+    s->regs[R_ROT_CREATOR_AUTH_STATE_READ_LOCK] = 0x1u;
+
+    if (dc->parent_phases.enter) {
+        /* OtOTPEngineState cleanup */
+        dc->parent_phases.enter(obj, type);
+    }
+}
+
+static void ot_otp_eg_init(Object *obj)
+{
+    OtOTPEgState *s = OT_OTP_EG(obj);
+    OtOTPEngineState *es = OT_OTP_ENGINE(obj);
+
+    /* note: device realization is implemented in OtOTPEngineState */
+
+    es->regs = g_new0(uint32_t, REGS_COUNT);
+    es->reg_offset.dai_base = R_DIRECT_ACCESS_REGWEN;
+    es->reg_offset.err_code_base = R_ERR_CODE_0;
+    es->reg_offset.read_lock_base = R_VENDOR_TEST_READ_LOCK;
+
+    /*
+     * "ctrl" region covers two sub-regions:
+     *   - "regs", registers:
+     *     offset 0, size REGS_SIZE
+     *   - "swcfg", software config window
+     *     offset SW_CFG_WINDOW_OFFSET, size SW_CFG_WINDOW_SIZE
+     */
+    memory_region_init(&s->mmio.ctrl, obj, TYPE_OT_OTP_EG "-ctrl",
+                       SW_CFG_WINDOW_OFFSET + SW_CFG_WINDOW_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio.ctrl);
+
+    memory_region_init_io(&s->mmio.sub.regs, obj, &ot_otp_eg_reg_ops, s,
+                          TYPE_OT_OTP_EG "-regs", REGS_SIZE);
+    memory_region_add_subregion(&s->mmio.ctrl, 0u, &s->mmio.sub.regs);
+
+    /* @todo it might be worthwhile to use a ROM-kind here */
+    memory_region_init_io(&s->mmio.sub.swcfg, obj, &ot_otp_eg_swcfg_ops, s,
+                          TYPE_OT_OTP_EG "-swcfg", SW_CFG_WINDOW_SIZE);
+    memory_region_add_subregion(&s->mmio.ctrl, SW_CFG_WINDOW_OFFSET,
+                                &s->mmio.sub.swcfg);
+}
+
+static void ot_otp_eg_class_init(ObjectClass *klass, const void *data)
+{
+    (void)data;
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtOTPEgClass *dc = OT_OTP_EG_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_otp_eg_reset_enter, NULL, NULL,
+                                       &dc->parent_phases);
+
+    OtOTPEngineClass *ec = OT_OTP_ENGINE_CLASS(klass);
+    OtOTPIfClass *oc = OT_OTP_IF_CLASS(klass);
+    oc->get_lc_info = &ot_otp_eg_get_lc_info;
+    oc->get_hw_cfg = ec->get_hw_cfg;
+    oc->get_otp_key = ec->get_otp_key;
+    oc->get_keymgr_secret = &ot_otp_eg_get_keymgr_secret;
+    oc->program_req = ec->program_req;
+
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_CLASS(klass);
+    ic->signal_pwr_sequence = &ot_otp_eg_signal_pwr_sequence;
+    ic->update_status_error = &ot_otp_eg_update_status_error;
+
+    ic->part_descs = OT_OTP_PART_DESCS;
+    ic->part_count = (unsigned)OTP_PART_COUNT;
+    ic->part_lc_num = (unsigned)OTP_PART_LIFE_CYCLE;
+    ic->sram_key_req_slot_count = NUM_SRAM_KEY_REQ_SLOTS;
+
+    ic->key_seeds = OT_OTP_KEY_SEEDS;
+    ic->has_flash_support = true;
+    ic->has_zer_support = false;
+    for (unsigned part_ix = 0; part_ix < ic->part_count; part_ix++) {
+        g_assert(!ic->part_descs[part_ix].zeroizable &&
+                 ic->part_descs[part_ix].zer_offset == UINT16_MAX);
+    }
+
+    g_assert(OT_OTP_KEY_SEEDS[OT_OTP_KEY_FLASH_ADDR].size ==
+             SECRET1_FLASH_ADDR_KEY_SEED_SIZE);
+    g_assert(OT_OTP_KEY_SEEDS[OT_OTP_KEY_FLASH_DATA].size ==
+             SECRET1_FLASH_DATA_KEY_SEED_SIZE);
+    g_assert(OT_OTP_KEY_SEEDS[OT_OTP_KEY_SRAM].size ==
+             SECRET1_SRAM_DATA_KEY_SEED_SIZE);
+}
+
+static const TypeInfo ot_otp_eg_info = {
+    .name = TYPE_OT_OTP_EG,
+    .parent = TYPE_OT_OTP_ENGINE,
+    .instance_size = sizeof(OtOTPEgState),
+    .instance_init = &ot_otp_eg_init,
+    .class_size = sizeof(OtOTPEgClass),
+    .class_init = &ot_otp_eg_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_OT_OTP_IF }, /* public OTP API */
+            { TYPE_OT_OTP_IMPL_IF }, /* private OTP API for OTP engine */
+            {},
+        },
+};
+
+static void ot_otp_eg_register_types(void)
+{
+    type_register_static(&ot_otp_eg_info);
+}
+
+type_init(ot_otp_eg_register_types);
diff --git a/hw/opentitan/ot_otp_eg_parts.c b/hw/opentitan/ot_otp_eg_parts.c
new file mode 100644
index 0000000000000..a8c76dd53897d
--- /dev/null
+++ b/hw/opentitan/ot_otp_eg_parts.c
@@ -0,0 +1,213 @@
+/*
+ * Generated from otp_ctrl_mmap.hjson with otptool.py
+ * Top version: 011b6ea1fe
+ */
+
+/* this prevents linters from checking this file without its parent file */
+#ifdef OT_OTP_EG_PARTS
+
+/* clang-format off */
+/* NOLINTBEGIN */
+static const OtOTPPartDesc OT_OTP_PART_DESCS[] = {
+    [OTP_PART_VENDOR_TEST] = {
+        .name = "VENDOR_TEST",
+        .size = 64u,
+        .offset = 0u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 56u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = false,
+        .zeroizable = false,
+    },
+    [OTP_PART_CREATOR_SW_CFG] = {
+        .name = "CREATOR_SW_CFG",
+        .size = 368u,
+        .offset = 64u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 424u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_OWNER_SW_CFG] = {
+        .name = "OWNER_SW_CFG",
+        .size = 712u,
+        .offset = 432u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 1136u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_ROT_CREATOR_AUTH_CODESIGN] = {
+        .name = "ROT_CREATOR_AUTH_CODESIGN",
+        .size = 472u,
+        .offset = 1144u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 1608u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_ROT_CREATOR_AUTH_STATE] = {
+        .name = "ROT_CREATOR_AUTH_STATE",
+        .size = 40u,
+        .offset = 1616u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 1648u,
+        .hw_digest = false,
+        .sw_digest = true,
+        .secret = false,
+        .buffered = false,
+        .write_lock = false,
+        .read_lock_csr = true,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_HW_CFG0] = {
+        .name = "HW_CFG0",
+        .size = 72u,
+        .offset = 1656u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 1720u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = false,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = false,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_HW_CFG1] = {
+        .name = "HW_CFG1",
+        .size = 16u,
+        .offset = 1728u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 1736u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = false,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = false,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_SECRET0] = {
+        .name = "SECRET0",
+        .size = 40u,
+        .offset = 1744u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 1776u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = true,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_SECRET1] = {
+        .name = "SECRET1",
+        .size = 88u,
+        .offset = 1784u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 1864u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = true,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = true,
+        .integrity = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_SECRET2] = {
+        .name = "SECRET2",
+        .size = 88u,
+        .offset = 1872u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = 1952u,
+        .hw_digest = true,
+        .sw_digest = false,
+        .secret = true,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = true,
+        .integrity = true,
+        .iskeymgr_creator = true,
+        .zeroizable = false,
+    },
+    [OTP_PART_LIFE_CYCLE] = {
+        .name = "LIFE_CYCLE",
+        .size = 88u,
+        .offset = 1960u,
+        .zer_offset = UINT16_MAX,
+        .digest_offset = UINT16_MAX,
+        .hw_digest = false,
+        .sw_digest = false,
+        .secret = false,
+        .buffered = true,
+        .write_lock = false,
+        .read_lock = false,
+        .integrity = true,
+        .zeroizable = false,
+    },
+};
+
+#define OTP_PART_COUNT ARRAY_SIZE(OT_OTP_PART_DESCS)
+
+static const OtOTPKeySeed OT_OTP_KEY_SEEDS[OT_OTP_KEY_COUNT] = {
+    [OT_OTP_KEY_FLASH_ADDR] = {
+        .partition = OTP_PART_SECRET1,
+        .offset = 0,
+        .size = 32,
+    },
+    [OT_OTP_KEY_FLASH_DATA] = {
+        .partition = OTP_PART_SECRET1,
+        .offset = 32,
+        .size = 32,
+    },
+    [OT_OTP_KEY_OTBN] = {
+        .partition = OTP_PART_SECRET1,
+        .offset = 64,
+        .size = 16,
+    },
+    [OT_OTP_KEY_SRAM] = {
+        .partition = OTP_PART_SECRET1,
+        .offset = 64,
+        .size = 16,
+    },
+};
+
+/* NOLINTEND */
+/* clang-format on */
+
+#endif /* OT_OTP_EG_PARTS */
diff --git a/hw/opentitan/ot_otp_engine.c b/hw/opentitan/ot_otp_engine.c
new file mode 100644
index 0000000000000..7ae0657af0ca4
--- /dev/null
+++ b/hw/opentitan/ot_otp_engine.c
@@ -0,0 +1,2986 @@
+/*
+ * QEMU OpenTitan EarlGrey One Time Programmable (OTP) memory controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define OT_OTP_COMPORTABLE_REGS
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_fifo32.h"
+#include "hw/opentitan/ot_lc_ctrl.h"
+#include "hw/opentitan/ot_otp_engine.h"
+#include "hw/opentitan/ot_otp_impl_if.h"
+#include "hw/opentitan/ot_present.h"
+#include "hw/opentitan/ot_prng.h"
+#include "hw/opentitan/ot_pwrmgr.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "system/block-backend.h"
+#include "trace.h"
+
+/*
+ * The OTP may be used before any CPU is started, This may cause the default
+ * virtual clock to stall, as the hart does not execute. OTP nevertheless may
+ * be active, updating the OTP content where write delays are still needed.
+ * Use the alternative clock source which counts even when the CPU is stalled.
+ */
+#define OT_OTP_HW_CLOCK QEMU_CLOCK_VIRTUAL_RT
+
+/* the following delays are arbitrary for now */
+#define DAI_DIGEST_DELAY_NS 50000 /* 50us */
+#define LCI_PROG_SCHED_NS   1000 /* 1us */
+
+/* Use a timer with a small delay instead of a BH for reliability */
+#define DIGEST_DECOUPLE_DELAY_NS    100 /* 100 ns */
+#define ENTROPY_RESCHEDULE_DELAY_NS 100 /* 100 ns */
+
+/* The size of keys used for OTP scrambling */
+#define OTP_SCRAMBLING_KEY_WIDTH 128u
+#define OTP_SCRAMBLING_KEY_BYTES ((OTP_SCRAMBLING_KEY_WIDTH) / 8u)
+
+#define LC_TRANSITION_CNT_SIZE 48u
+#define LC_STATE_SIZE          40u
+
+/* Sizes of constants used for deriving scrambling keys */
+#define KEY_MGR_KEY_WIDTH 256u
+
+#define OT_OTP_NAME_ENTRY(_st_) [OT_OTP_##_st_] = stringify(OT_OTP_##_st_)
+
+static const char *DAI_STATE_NAMES[] = {
+    /* clang-format off */
+    OT_OTP_NAME_ENTRY(DAI_RESET),
+    OT_OTP_NAME_ENTRY(DAI_INIT_OTP),
+    OT_OTP_NAME_ENTRY(DAI_INIT_PART),
+    OT_OTP_NAME_ENTRY(DAI_IDLE),
+    OT_OTP_NAME_ENTRY(DAI_ERROR),
+    OT_OTP_NAME_ENTRY(DAI_READ),
+    OT_OTP_NAME_ENTRY(DAI_READ_WAIT),
+    OT_OTP_NAME_ENTRY(DAI_DESCR),
+    OT_OTP_NAME_ENTRY(DAI_DESCR_WAIT),
+    OT_OTP_NAME_ENTRY(DAI_WRITE),
+    OT_OTP_NAME_ENTRY(DAI_WRITE_WAIT),
+    OT_OTP_NAME_ENTRY(DAI_SCR),
+    OT_OTP_NAME_ENTRY(DAI_SCR_WAIT),
+    OT_OTP_NAME_ENTRY(DAI_DIG_CLR),
+    OT_OTP_NAME_ENTRY(DAI_DIG_READ),
+    OT_OTP_NAME_ENTRY(DAI_DIG_READ_WAIT),
+    OT_OTP_NAME_ENTRY(DAI_DIG),
+    OT_OTP_NAME_ENTRY(DAI_DIG_PAD),
+    OT_OTP_NAME_ENTRY(DAI_DIG_FIN),
+    OT_OTP_NAME_ENTRY(DAI_DIG_WAIT),
+    /* clang-format on */
+};
+
+static const char *LCI_STATE_NAMES[] = {
+    /* clang-format off */
+    OT_OTP_NAME_ENTRY(LCI_RESET),
+    OT_OTP_NAME_ENTRY(LCI_IDLE),
+    OT_OTP_NAME_ENTRY(LCI_WRITE),
+    OT_OTP_NAME_ENTRY(LCI_WRITE_WAIT),
+    OT_OTP_NAME_ENTRY(LCI_ERROR),
+    /* clang-format on */
+};
+
+static const char *ERR_CODE_NAMES[] = {
+    /* clang-format off */
+    OT_OTP_NAME_ENTRY(NO_ERROR),
+    OT_OTP_NAME_ENTRY(MACRO_ERROR),
+    OT_OTP_NAME_ENTRY(MACRO_ECC_CORR_ERROR),
+    OT_OTP_NAME_ENTRY(MACRO_ECC_UNCORR_ERROR),
+    OT_OTP_NAME_ENTRY(MACRO_WRITE_BLANK_ERROR),
+    OT_OTP_NAME_ENTRY(ACCESS_ERROR),
+    OT_OTP_NAME_ENTRY(CHECK_FAIL_ERROR),
+    OT_OTP_NAME_ENTRY(FSM_STATE_ERROR),
+    /* clang-format on */
+};
+
+#define BUF_STATE_NAME(_st_) \
+    ((unsigned)(_st_) < ARRAY_SIZE(BUF_STATE_NAMES) ? \
+         BUF_STATE_NAMES[(_st_)] : \
+         "?")
+#define UNBUF_STATE_NAME(_st_) \
+    ((unsigned)(_st_) < ARRAY_SIZE(UNBUF_STATE_NAMES) ? \
+         UNBUF_STATE_NAMES[(_st_)] : \
+         "?")
+#define DAI_STATE_NAME(_st_) \
+    ((unsigned)(_st_) < ARRAY_SIZE(DAI_STATE_NAMES) ? \
+         DAI_STATE_NAMES[(_st_)] : \
+         "?")
+#define LCI_STATE_NAME(_st_) \
+    ((unsigned)(_st_) < ARRAY_SIZE(LCI_STATE_NAMES) ? \
+         LCI_STATE_NAMES[(_st_)] : \
+         "?")
+#define ERR_CODE_NAME(_err_) \
+    (((unsigned)(_err_)) < ARRAY_SIZE(ERR_CODE_NAMES) ? \
+         ERR_CODE_NAMES[(_err_)] : \
+         "?")
+
+/* @todo add assertion to validate those */
+#define OTP_ENTRY_DAI(_s_)   ((_s_)->part_count + 0u)
+#define OTP_ENTRY_KDI(_s_)   ((_s_)->part_count + 1u)
+#define OTP_ENTRY_COUNT(_s_) ((_s_)->part_count + 2u)
+
+#define DIRECT_ACCESS_REG(_s_, _reg_) \
+    ((_s_)->regs[(_s_)->reg_offset.dai_base + \
+                 (unsigned)(OT_OTP_DA_REG_##_reg_)])
+#define ERR_CODE_PART_REG(_s_, _pix_) \
+    ((_s_)->regs[(_s_)->reg_offset.err_code_base + (_pix_)])
+
+/*
+ * See RTL files otp_ctrl/rtl/otp_ctrl_kdi.sv and otp_ctrl/rtl/otp_ctrl_pkg.sv
+ * and OTP doc otp_ctrl/theory_of_operation.html#scrambling-key-derivation.
+ */
+#define SRAM_KEY_BYTES(_ic_)   ((_ic_)->key_seeds[OT_OTP_KEY_SRAM].size)
+#define SRAM_NONCE_BYTES(_ic_) ((_ic_)->key_seeds[OT_OTP_KEY_SRAM].size)
+#define OTBN_KEY_BYTES(_ic_)   ((_ic_)->key_seeds[OT_OTP_KEY_OTBN].size)
+#define OTBN_NONCE_BYTES(_ic_) (((_ic_)->key_seeds[OT_OTP_KEY_OTBN].size) / 2u)
+
+#define OT_OTP_SCRMBL_KEY_SIZE  16u
+#define OT_OTP_SCRMBL_NONE_SIZE (OT_OTP_SCRMBL_KEY_SIZE)
+
+/* Need 128 bits of entropy to compute each 64-bit key part */
+#define OTP_ENTROPY_PRESENT_BYTES(_ic_) \
+    (((((_ic_)->sram_key_req_slot_count) * SRAM_KEY_BYTES(_ic_)) + \
+      (OTBN_KEY_BYTES(_ic_))) * \
+     2u)
+#define OTP_ENTROPY_NONCE_BYTES(_ic_) \
+    (((_ic_)->sram_key_req_slot_count) * SRAM_NONCE_BYTES(_ic_) + \
+     OTBN_NONCE_BYTES(_ic_))
+#define OTP_ENTROPY_BUF_COUNT(_ic_) \
+    ((OTP_ENTROPY_PRESENT_BYTES(_ic_) + OTP_ENTROPY_NONCE_BYTES(_ic_)) / 4u)
+
+#ifdef OT_OTP_DEBUG
+#define OT_OTP_HEXSTR_SIZE  256u
+#define TRACE_OTP(msg, ...) qemu_log("%s: " msg "\n", __func__, ##__VA_ARGS__);
+#define ot_otp_hexdump(_s_, _b_, _l_) \
+    ot_common_lhexdump((const uint8_t *)_b_, _l_, false, (_s_)->hexstr, \
+                       OT_OTP_HEXSTR_SIZE)
+#else
+#define TRACE_OTP(msg, ...)
+#define ot_otp_hexdump(_s_, _b_, _l_)
+#endif
+
+#define DAI_CHANGE_STATE(_s_, _st_) \
+    ot_otp_engine_dai_change_state_line(_s_, _st_, __LINE__)
+#define LCI_CHANGE_STATE(_s_, _st_) \
+    ot_otp_engine_lci_change_state_line(_s_, _st_, __LINE__)
+
+static void ot_otp_engine_dai_set_error(OtOTPEngineState *s, OtOTPError err);
+static void ot_otp_engine_dai_change_state_line(OtOTPEngineState *s,
+                                                OtOTPDAIState state, int line);
+static void ot_otp_engine_lci_change_state_line(OtOTPEngineState *s,
+                                                OtOTPLCIState state, int line);
+
+struct OtOTPScrmblKeyInit_ {
+    uint8_t key[OT_OTP_SCRMBL_KEY_SIZE];
+    uint8_t nonce[OT_OTP_SCRMBL_NONE_SIZE];
+};
+
+struct OtOTPKeyGen_ {
+    QEMUTimer *request_entropy;
+    OtPresentState *present;
+    OtPrngState *prng;
+    OtFifo32 entropy_buf;
+    bool edn_sched;
+};
+
+static void ot_otp_engine_update_irqs(OtOTPEngineState *s)
+{
+    uint32_t levels = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->irqs); ix++) {
+        int level = (int)((levels >> ix) & 0x1u);
+        if (level != ibex_irq_get_level(&s->irqs[ix])) {
+            trace_ot_otp_update_irq(s->ot_id, ibex_irq_get_level(&s->irqs[ix]),
+                                    level);
+        }
+        ibex_irq_set(&s->irqs[ix], level);
+    }
+}
+
+static void ot_otp_engine_update_alerts(OtOTPEngineState *s)
+{
+    uint32_t levels = s->regs[R_ALERT_TEST];
+
+    levels |= s->alert_bm;
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        int level = (int)((levels >> ix) & 0x1u);
+        if (level != ibex_irq_get_level(&s->alerts[ix])) {
+            trace_ot_otp_update_alert(s->ot_id,
+                                      ibex_irq_get_level(&s->alerts[ix]),
+                                      level);
+        }
+        ibex_irq_set(&s->alerts[ix], level);
+    }
+
+    /* alert test is transient */
+    if (s->regs[R_ALERT_TEST]) {
+        s->regs[R_ALERT_TEST] = 0;
+
+        levels = s->alert_bm;
+        for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+            int level = (int)((levels >> ix) & 0x1u);
+            if (level != ibex_irq_get_level(&s->alerts[ix])) {
+                trace_ot_otp_update_alert(s->ot_id,
+                                          ibex_irq_get_level(&s->alerts[ix]),
+                                          level);
+            }
+            ibex_irq_set(&s->alerts[ix], level);
+        }
+    }
+}
+
+static const char *
+ot_otp_engine_part_name(const OtOTPEngineState *s, unsigned part_ix)
+{
+    if (part_ix < s->part_count) {
+        return s->part_descs[part_ix].name;
+    }
+
+    if (part_ix == OTP_ENTRY_DAI(s)) {
+        return "DAI";
+    }
+
+    if (part_ix == OTP_ENTRY_KDI(s)) {
+        return "KDI";
+    }
+
+    return "?";
+}
+
+static void ot_otp_engine_disable_all_partitions(OtOTPEngineState *s)
+{
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_ERROR);
+    LCI_CHANGE_STATE(s, OT_OTP_LCI_ERROR);
+
+    for (unsigned pix = 0; pix < s->part_count; pix++) {
+        OtOTPPartController *pctrl = &s->part_ctrls[pix];
+        pctrl->failed = true;
+    }
+}
+
+static void ot_otp_engine_set_error(OtOTPEngineState *s, unsigned part_ix,
+                                    OtOTPError err)
+{
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(s);
+    g_assert(part_ix < OTP_ENTRY_COUNT(s));
+
+    uint32_t errval = ((uint32_t)err) & OT_OTP_ERR_CODE_MASK;
+    if (errval || errval != ERR_CODE_PART_REG(s, part_ix)) {
+        trace_ot_otp_set_error(s->ot_id, ot_otp_engine_part_name(s, part_ix),
+                               part_ix, ERR_CODE_NAME(err), err);
+    }
+    ERR_CODE_PART_REG(s, part_ix) = errval;
+
+    switch (err) {
+    case OT_OTP_MACRO_ERROR:
+    case OT_OTP_MACRO_ECC_UNCORR_ERROR:
+        s->alert_bm |= ALERT_FATAL_MACRO_ERROR_MASK;
+        ot_otp_engine_update_alerts(s);
+        break;
+    /* NOLINTNEXTLINE */
+    case OT_OTP_MACRO_ECC_CORR_ERROR:
+        /*
+         * "The corresponding controller automatically recovers from this error
+         *  when issuing a new command."
+         */
+        break;
+    case OT_OTP_MACRO_WRITE_BLANK_ERROR:
+        break;
+    case OT_OTP_ACCESS_ERROR:
+        ic->update_status_error(OT_OTP_IMPL_IF(s), OT_OTP_STATUS_DAI, true);
+        break;
+    case OT_OTP_CHECK_FAIL_ERROR:
+    case OT_OTP_FSM_STATE_ERROR:
+        s->alert_bm |= ALERT_FATAL_CHECK_ERROR_MASK;
+        ot_otp_engine_update_alerts(s);
+        break;
+    default:
+        break;
+    }
+
+    if (s->alert_bm & ALERT_FATAL_CHECK_ERROR_MASK) {
+        ot_otp_engine_disable_all_partitions(s);
+        error_report("%s: %s: OTP disabled on fatal error", __func__, s->ot_id);
+    }
+
+    if (err != OT_OTP_NO_ERROR) {
+        s->regs[R_INTR_STATE] |= INTR_OTP_ERROR_MASK;
+        ot_otp_engine_update_irqs(s);
+    }
+}
+
+static int
+ot_otp_engine_get_part_from_address(const OtOTPEngineState *s, hwaddr addr)
+{
+    for (unsigned part_ix = 0; part_ix < s->part_count; part_ix++) {
+        const OtOTPPartDesc *part = &s->part_descs[part_ix];
+        if ((addr >= part->offset) &&
+            ((addr + sizeof(uint32_t)) <= (part->offset + part->size))) {
+            trace_ot_otp_addr_to_part(s->ot_id, (uint32_t)addr,
+                                      ot_otp_engine_part_name(s, part_ix),
+                                      part_ix);
+            return (int)part_ix;
+        }
+    }
+
+    return -1;
+}
+
+static uint8_t ot_otp_engine_compute_ecc_u16(uint16_t data)
+{
+    uint32_t data_o = (uint32_t)data;
+
+    data_o |= __builtin_parity(data_o & 0x00ad5bu) << 16u;
+    data_o |= __builtin_parity(data_o & 0x00366du) << 17u;
+    data_o |= __builtin_parity(data_o & 0x00c78eu) << 18u;
+    data_o |= __builtin_parity(data_o & 0x0007f0u) << 19u;
+    data_o |= __builtin_parity(data_o & 0x00f800u) << 20u;
+    data_o |= __builtin_parity(data_o & 0x1fffffu) << 21u;
+
+    return (uint8_t)(data_o >> 16u);
+}
+
+static uint16_t ot_otp_engine_compute_ecc_u32(uint32_t data)
+{
+    uint16_t data_lo = (uint16_t)(data & UINT16_MAX);
+    uint16_t data_hi = (uint16_t)(data >> 16u);
+
+    uint16_t ecc_lo = (uint16_t)ot_otp_engine_compute_ecc_u16(data_lo);
+    uint16_t ecc_hi = (uint16_t)ot_otp_engine_compute_ecc_u16(data_hi);
+
+    return (ecc_hi << 8u) | ecc_lo;
+}
+
+static uint32_t ot_otp_engine_compute_ecc_u64(uint64_t data)
+{
+    uint32_t data_lo = (uint32_t)(data & UINT32_MAX);
+    uint32_t data_hi = (uint32_t)(data >> 32u);
+
+    uint32_t ecc_lo = (uint32_t)ot_otp_engine_compute_ecc_u32(data_lo);
+    uint32_t ecc_hi = (uint32_t)ot_otp_engine_compute_ecc_u32(data_hi);
+
+    return (ecc_hi << 16u) | ecc_lo;
+}
+
+static uint32_t ot_otp_engine_verify_ecc_22_16_u16(
+    const OtOTPEngineState *s, uint32_t data_i, unsigned *err_o)
+{
+    unsigned syndrome = 0u;
+
+    syndrome |= __builtin_parity(data_i & 0x01ad5bu) << 0u;
+    syndrome |= __builtin_parity(data_i & 0x02366du) << 1u;
+    syndrome |= __builtin_parity(data_i & 0x04c78eu) << 2u;
+    syndrome |= __builtin_parity(data_i & 0x0807f0u) << 3u;
+    syndrome |= __builtin_parity(data_i & 0x10f800u) << 4u;
+    syndrome |= __builtin_parity(data_i & 0x3fffffu) << 5u;
+
+    unsigned err = (syndrome >> 5u) & 1u;
+    if (!err && (syndrome & 0x1fu)) {
+        err = 2u;
+    }
+
+    *err_o = err;
+
+    if (!err) {
+        return data_i & UINT16_MAX;
+    }
+
+    uint32_t data_o = 0;
+
+#define OTP_ECC_RECOVER(_sy_, _di_, _ix_) \
+    ((unsigned)((syndrome == (_sy_)) ^ (bool)((_di_) & (1u << (_ix_)))) \
+     << (_ix_))
+
+    data_o |= OTP_ECC_RECOVER(0x23u, data_i, 0u);
+    data_o |= OTP_ECC_RECOVER(0x25u, data_i, 1u);
+    data_o |= OTP_ECC_RECOVER(0x26u, data_i, 2u);
+    data_o |= OTP_ECC_RECOVER(0x27u, data_i, 3u);
+    data_o |= OTP_ECC_RECOVER(0x29u, data_i, 4u);
+    data_o |= OTP_ECC_RECOVER(0x2au, data_i, 5u);
+    data_o |= OTP_ECC_RECOVER(0x2bu, data_i, 6u);
+    data_o |= OTP_ECC_RECOVER(0x2cu, data_i, 7u);
+    data_o |= OTP_ECC_RECOVER(0x2du, data_i, 8u);
+    data_o |= OTP_ECC_RECOVER(0x2eu, data_i, 9u);
+    data_o |= OTP_ECC_RECOVER(0x2fu, data_i, 10u);
+    data_o |= OTP_ECC_RECOVER(0x31u, data_i, 11u);
+    data_o |= OTP_ECC_RECOVER(0x32u, data_i, 12u);
+    data_o |= OTP_ECC_RECOVER(0x33u, data_i, 13u);
+    data_o |= OTP_ECC_RECOVER(0x34u, data_i, 14u);
+    data_o |= OTP_ECC_RECOVER(0x35u, data_i, 15u);
+
+#undef OTP_ECC_RECOVER
+
+    if (err > 1u) {
+        trace_ot_otp_ecc_unrecoverable_error(s->ot_id, data_i & UINT16_MAX);
+    } else {
+        if ((data_i & UINT16_MAX) != data_o) {
+            trace_ot_otp_ecc_recovered_error(s->ot_id, data_i & UINT16_MAX,
+                                             data_o);
+        } else {
+            /* ECC bit is corrupted */
+            trace_ot_otp_ecc_parity_error(s->ot_id, data_i & UINT16_MAX,
+                                          data_i >> 16u);
+        }
+    }
+
+    return data_o;
+}
+
+static uint32_t ot_otp_engine_verify_ecc(
+    const OtOTPEngineState *s, uint32_t data, uint32_t ecc, unsigned *err)
+{
+    uint32_t data_lo_i, data_lo_o, data_hi_i, data_hi_o;
+    unsigned err_lo, err_hi;
+
+    data_lo_i = (data & 0xffffu) | ((ecc & 0xffu) << 16u);
+    data_lo_o = ot_otp_engine_verify_ecc_22_16_u16(s, data_lo_i, &err_lo);
+
+    data_hi_i = (data >> 16u) | (((ecc >> 8u) & 0xffu) << 16u);
+    data_hi_o = ot_otp_engine_verify_ecc_22_16_u16(s, data_hi_i, &err_hi);
+
+    *err |= err_lo | err_hi;
+
+    return (data_hi_o << 16u) | data_lo_o;
+}
+
+static uint64_t ot_otp_engine_apply_digest_ecc(
+    OtOTPEngineState *s, unsigned partition, uint64_t digest, uint32_t ecc)
+{
+    uint32_t dig_lo = (uint32_t)(digest & UINT32_MAX);
+    uint32_t dig_hi = (uint32_t)(digest >> 32u);
+
+    unsigned err = 0;
+    dig_lo = ot_otp_engine_verify_ecc(s, dig_lo, ecc & 0xffffu, &err);
+    dig_hi = ot_otp_engine_verify_ecc(s, dig_hi, ecc >> 16u, &err);
+    digest = (((uint64_t)dig_hi) << 32u) | ((uint64_t)dig_lo);
+
+    if (err) {
+        OtOTPError otp_err = (err > 1) ? OT_OTP_MACRO_ECC_UNCORR_ERROR :
+                                         OT_OTP_MACRO_ECC_CORR_ERROR;
+        /*
+         * Note: need to check if any caller could override the error/state
+         * in this case
+         */
+        ot_otp_engine_set_error(s, partition, otp_err);
+    }
+
+    return digest;
+}
+
+static int ot_otp_engine_apply_ecc(OtOTPEngineState *s, unsigned part_ix)
+{
+    g_assert(ot_otp_engine_is_ecc_enabled(s));
+
+    unsigned start = s->part_descs[part_ix].offset >> 2u;
+    unsigned end = (ot_otp_engine_is_buffered(s, (int)part_ix) &&
+                    ot_otp_engine_has_digest(s, part_ix)) ?
+                       (unsigned)(s->part_descs[part_ix].digest_offset >> 2u) :
+                       start + (unsigned)(s->part_descs[part_ix].size >> 2u);
+
+    g_assert(start < end && (end / sizeof(uint32_t)) < s->otp->data_size);
+    for (unsigned ix = start; ix < end; ix++) {
+        unsigned err = 0;
+        uint32_t *word = &s->otp->data[ix];
+        uint16_t ecc = ((const uint16_t *)s->otp->ecc)[ix];
+        *word = ot_otp_engine_verify_ecc(s, *word, (uint32_t)ecc, &err);
+        if (err) {
+            OtOTPError otp_err = (err > 1) ? OT_OTP_MACRO_ECC_UNCORR_ERROR :
+                                             OT_OTP_MACRO_ECC_CORR_ERROR;
+            /*
+             *  Note: need to check if any caller could override the error/state
+             * in this case
+             */
+            ot_otp_engine_set_error(s, part_ix, otp_err);
+            if (err > 1) {
+                trace_ot_otp_ecc_init_error(s->ot_id,
+                                            ot_otp_engine_part_name(s, part_ix),
+                                            part_ix, ix << 2u, *word, ecc);
+                s->part_ctrls[part_ix].failed = true;
+                return -1;
+            }
+        }
+    }
+
+    return 0;
+}
+
+static uint64_t
+ot_otp_engine_get_part_digest(OtOTPEngineState *s, unsigned part_ix)
+{
+    g_assert(!ot_otp_engine_is_buffered(s, part_ix));
+
+    uint16_t offset = s->part_descs[part_ix].digest_offset;
+
+    if (offset == UINT16_MAX) {
+        return 0u;
+    }
+
+    const uint8_t *data = (const uint8_t *)s->otp->data;
+    uint64_t digest = ldq_le_p(data + offset);
+
+    if (s->part_descs[part_ix].integrity && ot_otp_engine_is_ecc_enabled(s)) {
+        unsigned waddr = offset >> 2u;
+        unsigned ewaddr = waddr >> 1u;
+        g_assert(ewaddr < s->otp->ecc_size);
+        uint32_t ecc = s->otp->ecc[ewaddr];
+        digest = ot_otp_engine_apply_digest_ecc(s, part_ix, digest, ecc);
+    }
+
+    return digest;
+}
+
+static uint32_t
+ot_otp_engine_get_part_digest_reg(OtOTPEngineState *s, uint32_t offset)
+{
+    /*
+     * Offset is the register offset from the first read 32-bit digest register.
+     * All digests are 64-bits, which means each partition have two 32-bit
+     * registers to expose their digest.
+     *
+     * Not all partitions have digests, which means the offset argument is the
+     * relative partition offset for those partitions that features a digest, as
+     * there is no defined digest access registers defined for partitions that
+     * do not have a digest.
+     *
+     * Need to traverse the partition table to only account for those partitions
+     * with a digest to match the proper offset.
+     */
+
+    /*
+     * part_look_ix is the index of the partition in the contiguous array of
+     * digest registers, which would be equivalent as the index of the partition
+     * that would exist in a virtual partition-with-digest array.
+     */
+    unsigned part_look_ix = (unsigned)(offset / OT_OTP_NUM_DIGEST_WORDS);
+    /* whether to retrieve the top most 32-bit of the digest or not */
+    bool hi = (bool)(offset & 0x1u);
+
+    /* part_ix: the partition number in the global partition array */
+    unsigned part_ix = 0;
+    /* traverse the partition array and count each partition with a digest */
+    for (unsigned part_dig_ix = 0; part_ix < s->part_count; part_ix++) {
+        if (ot_otp_engine_has_digest(s, part_ix)) {
+            /*
+             * stop searching if we've found the part-with-digest defined from
+             * the offset argument. Otherwise, increment the part-with-digest
+             * index and continue.
+             */
+            if (part_dig_ix == part_look_ix) {
+                break;
+            }
+            part_dig_ix++;
+        }
+    }
+
+    /*
+     * If the part_ix as reached the latest partition, there is something wrong
+     * with the partition table or the register definitions, as it is assumed
+     * that LifeCycle partition is the last partition.
+     */
+    g_assert(s->part_lc_num == s->part_count - 1u);
+    g_assert(part_ix < s->part_count);
+
+    const OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+    uint64_t digest = pctrl->digest;
+
+    if (hi) {
+        digest >>= 32u;
+    }
+
+    return (uint32_t)digest;
+}
+
+static uint32_t
+ot_otp_engine_get_sw_readlock(const OtOTPEngineState *s, unsigned rdlk_ix)
+{
+    uint32_t reg = s->reg_offset.read_lock_base + rdlk_ix;
+
+    return (bool)SHARED_FIELD_EX32(s->regs[reg], OT_OTP_READ_LOCK);
+}
+
+static bool ot_otp_engine_is_readable(const OtOTPEngineState *s,
+                                      unsigned part_ix)
+{
+    g_assert(part_ix < s->part_count);
+
+    const OtOTPPartDesc *pdesc = &s->part_descs[part_ix];
+    const OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+
+    if (pdesc->secret) {
+        /* secret partitions are only readable if digest is not yet set. */
+        return pctrl->digest == 0u;
+    }
+
+    if (!pdesc->read_lock_csr) {
+        if (!pdesc->read_lock) {
+            /* read lock is not supported for this partition */
+            return true;
+        }
+
+        /* hw read lock, not locked */
+        return !pctrl->read_lock;
+    }
+
+    unsigned roffset = 0;
+    unsigned pix;
+    for (pix = 0; pix < s->part_count; pix++) {
+        if (pix == part_ix) {
+            break;
+        }
+        if (pdesc->read_lock_csr) {
+            roffset++;
+        }
+    }
+    /*
+     * know for sure last partition is the life cycle one, which never
+     * support a read_lock_csr. Ideally this g_assert should be a
+     * static_assert, but C being C, constants are not defined as such
+     * at build time...
+     */
+    g_assert(!s->part_descs[s->part_lc_num].read_lock_csr);
+
+    /*
+     * If the previous loop reached the last partition, something
+     * seriously wrong occurred. Use this feature as a sanity check
+     */
+    g_assert(pix < s->part_lc_num);
+
+    /*
+     * now that the count of read_lock_csr is known, use it to access
+     * the register for the selected partition
+     */
+    return ot_otp_engine_get_sw_readlock(s, roffset);
+}
+
+static void ot_otp_engine_dai_change_state_line(OtOTPEngineState *s,
+                                                OtOTPDAIState state, int line)
+{
+    trace_ot_otp_dai_change_state(s->ot_id, line, DAI_STATE_NAME(s->dai->state),
+                                  s->dai->state, DAI_STATE_NAME(state), state);
+
+    s->dai->state = state;
+}
+
+static void ot_otp_engine_lci_change_state_line(OtOTPEngineState *s,
+                                                OtOTPLCIState state, int line)
+{
+    trace_ot_otp_lci_change_state(s->ot_id, line, LCI_STATE_NAME(s->lci->state),
+                                  s->lci->state, LCI_STATE_NAME(state), state);
+
+    s->lci->state = state;
+}
+
+static void ot_otp_engine_lc_broadcast_recv(void *opaque, int n, int level)
+{
+    OtOTPEngineState *s = opaque;
+    OtOTPLcBroadcast *bcast = &s->lc_broadcast;
+
+    g_assert((unsigned)n < OT_OTP_LC_BROADCAST_COUNT);
+
+    uint16_t bit = 1u << (unsigned)n;
+    bcast->signal |= bit;
+    /*
+     * as these signals are only used to change permissions, it is valid to
+     * override a signal value that has not been processed yet
+     */
+    if (level) {
+        bcast->level |= bit;
+    } else {
+        bcast->level &= ~bit;
+    }
+
+    /* use a BH to decouple IRQ signaling from actual handling */
+    qemu_bh_schedule(s->lc_broadcast.bh);
+}
+
+static void ot_otp_engine_lc_broadcast_bh(void *opaque)
+{
+    OtOTPEngineState *s = opaque;
+    OtOTPLcBroadcast *bcast = &s->lc_broadcast;
+
+    /* handle all flagged signals */
+    while (bcast->signal) {
+        /* pick and clear */
+        unsigned sig = ctz16(bcast->signal);
+        uint16_t bit = 1u << (unsigned)sig;
+        bcast->signal &= ~bit;
+        bcast->current_level =
+            (bcast->current_level & ~bit) | (bcast->level & bit);
+        bool level = (bool)(bcast->current_level & bit);
+
+        trace_ot_otp_lc_broadcast(s->ot_id, sig, level);
+
+        switch ((int)sig) {
+        case OT_OTP_LC_DFT_EN:
+            qemu_log_mask(LOG_UNIMP, "%s: %s: DFT feature not supported\n",
+                          __func__, s->ot_id);
+            break;
+        case OT_OTP_LC_ESCALATE_EN:
+            if (level) {
+                DAI_CHANGE_STATE(s, OT_OTP_DAI_ERROR);
+                LCI_CHANGE_STATE(s, OT_OTP_LCI_ERROR);
+                /* @todo manage other FSMs */
+                qemu_log_mask(LOG_UNIMP,
+                              "%s: %s: ESCALATE partially implemented\n",
+                              __func__, s->ot_id);
+                if (s->fatal_escalate) {
+                    error_setg(&error_fatal, "%s: OTP LC escalate", s->ot_id);
+                }
+            }
+            break;
+        case OT_OTP_LC_CHECK_BYP_EN:
+            qemu_log_mask(LOG_UNIMP, "%s: %s: bypass is ignored\n", __func__,
+                          s->ot_id);
+            break;
+        case OT_OTP_LC_CREATOR_SEED_SW_RW_EN:
+            for (unsigned ix = 0; ix < s->part_count; ix++) {
+                if (s->part_descs[ix].iskeymgr_creator) {
+                    s->part_ctrls[ix].read_lock = !level;
+                    s->part_ctrls[ix].write_lock = !level;
+                }
+            }
+            break;
+        case OT_OTP_LC_OWNER_SEED_SW_RW_EN:
+            for (unsigned ix = 0; ix < s->part_count; ix++) {
+                if (s->part_descs[ix].iskeymgr_owner) {
+                    s->part_ctrls[ix].read_lock = !level;
+                    s->part_ctrls[ix].write_lock = !level;
+                }
+            }
+            break;
+        case OT_OTP_LC_SEED_HW_RD_EN:
+            /* nothing to do here, SEED_HW_RD_EN flag is in current_level */
+            break;
+        default:
+            error_setg(&error_fatal, "%s: %s: unexpected LC broadcast %d\n",
+                       __func__, s->ot_id, sig);
+            g_assert_not_reached();
+            break;
+        }
+    }
+}
+
+static uint64_t ot_otp_engine_compute_partition_digest(
+    OtOTPEngineState *s, const uint8_t *base, unsigned size)
+{
+    OtPresentState *ps = ot_present_new();
+
+    g_assert((size & (sizeof(uint64_t) - 1u)) == 0);
+
+    uint8_t buf[sizeof(uint64_t) * 2u];
+    uint64_t state = s->digest_iv;
+    uint64_t out;
+    for (unsigned off = 0; off < size; off += sizeof(buf)) {
+        memcpy(buf, base + off, sizeof(uint64_t));
+        if (off + sizeof(uint64_t) != size) {
+            memcpy(&buf[sizeof(uint64_t)], base + off + sizeof(uint64_t),
+                   sizeof(uint64_t));
+        } else {
+            /* special case, duplicate last block if block number is odd */
+            memcpy(&buf[sizeof(uint64_t)], base + off, sizeof(uint64_t));
+        }
+
+        ot_present_init(ps, buf);
+        ot_present_encrypt(ps, state, &out);
+        state ^= out;
+    }
+
+    ot_present_init(ps, s->digest_const);
+    ot_present_encrypt(ps, state, &out);
+    state ^= out;
+
+    ot_present_free(ps);
+
+    return state;
+}
+
+static uint64_t
+ot_otp_engine_load_partition_digest(OtOTPEngineState *s, unsigned partition)
+{
+    unsigned digoff = (unsigned)s->part_descs[partition].digest_offset;
+
+    if ((digoff + sizeof(uint64_t)) > s->otp->data_size) {
+        error_setg(&error_fatal, "%s: partition located outside storage?",
+                   s->ot_id);
+        /* linter doest not know the above call never returns */
+        return 0u;
+    }
+
+    const uint8_t *data = (const uint8_t *)s->otp->data;
+    uint64_t digest = ldq_le_p(data + digoff);
+
+    if (ot_otp_engine_is_ecc_enabled(s)) {
+        unsigned ewaddr = (digoff >> 3u);
+        g_assert(ewaddr < s->otp->ecc_size);
+        uint32_t ecc = s->otp->ecc[ewaddr];
+        digest = ot_otp_engine_apply_digest_ecc(s, partition, digest, ecc);
+    }
+
+    return digest;
+}
+
+static void
+ot_otp_engine_unscramble_partition(OtOTPEngineState *s, unsigned part_ix)
+{
+    OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+
+    unsigned offset = (unsigned)s->part_descs[part_ix].offset;
+    unsigned part_size = ot_otp_engine_part_data_byte_size(s, part_ix);
+
+    /* part_size should be a multiple of PRESENT block size */
+    g_assert((part_size & (sizeof(uint64_t) - 1u)) == 0u);
+    unsigned dword_count = part_size / sizeof(uint64_t);
+
+    const uint8_t *base = (const uint8_t *)s->otp->data;
+    base += offset;
+
+    /* source address should be aligned to 64-bit boundary */
+    g_assert(((uintptr_t)base & (sizeof(uint64_t) - 1u)) == 0u);
+    const uint64_t *scrambled = (const uint64_t *)base;
+
+    /* destination address should be aligned to 64-bit boundary */
+    g_assert(pctrl->buffer.data != NULL);
+    uint64_t *clear = (uint64_t *)pctrl->buffer.data;
+
+    g_assert(pctrl->otp_scramble_key);
+
+    OtPresentState *ps = ot_present_new();
+    ot_present_init(ps, pctrl->otp_scramble_key);
+
+    trace_ot_otp_unscramble_partition(s->ot_id,
+                                      ot_otp_engine_part_name(s, part_ix),
+                                      part_ix, part_size);
+    /* neither the digest block nor the zeroizable block are scrambled */
+    for (unsigned dix = 0u; dix < dword_count; dix++) {
+        ot_present_decrypt(ps, scrambled[dix], &clear[dix]);
+    }
+
+    ot_present_free(ps);
+}
+
+static void
+ot_otp_engine_bufferize_partition(OtOTPEngineState *s, unsigned part_ix)
+{
+    OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+
+    g_assert(pctrl->buffer.data != NULL);
+
+    if (s->part_descs[part_ix].hw_digest) {
+        pctrl->digest = ot_otp_engine_load_partition_digest(s, part_ix);
+    } else {
+        pctrl->digest = 0;
+    }
+
+    if (s->part_descs[part_ix].secret) {
+        /* secret partitions need to be unscrambled */
+        if (s->blk) {
+            /*
+             * nothing to unscramble if no OTP data is loaded
+             * scrambling keys in this case may not be known
+             */
+            ot_otp_engine_unscramble_partition(s, part_ix);
+        }
+    } else {
+        unsigned offset = (unsigned)s->part_descs[part_ix].offset;
+        unsigned part_size = ot_otp_engine_part_data_byte_size(s, part_ix);
+
+        const uint8_t *base = (const uint8_t *)s->otp->data;
+        base += offset;
+
+        memcpy(pctrl->buffer.data, base, part_size);
+    }
+}
+
+static void ot_otp_engine_check_buffered_partition_integrity(
+    OtOTPEngineState *s, unsigned part_ix)
+{
+    OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+
+    if (pctrl->digest == 0) {
+        trace_ot_otp_skip_digest(s->ot_id, ot_otp_engine_part_name(s, part_ix),
+                                 part_ix);
+        pctrl->locked = false;
+        return;
+    }
+
+    pctrl->locked = true;
+
+    /*
+     * digests are always calculated over the original data (scrambled or not)
+     */
+    const uint8_t *part_data = ((const uint8_t *)s->otp->data) +
+                               ot_otp_engine_part_data_offset(s, part_ix);
+    unsigned part_size = ot_otp_engine_part_data_byte_size(s, part_ix);
+
+    uint64_t digest =
+        ot_otp_engine_compute_partition_digest(s, part_data, part_size);
+
+    if (digest != pctrl->digest) {
+        trace_ot_otp_mismatch_digest(s->ot_id,
+                                     ot_otp_engine_part_name(s, part_ix),
+                                     part_ix, digest, pctrl->digest);
+
+        TRACE_OTP("compute digest of %s: %016" PRIx64 " from %s\n",
+                  ot_otp_engine_part_name(s, part_ix), digest,
+                  ot_otp_hexdump(s, part_data, part_size));
+
+        pctrl->failed = true;
+        /* this is a fatal error */
+        ot_otp_engine_set_error(s, part_ix, OT_OTP_CHECK_FAIL_ERROR);
+        /* @todo revert buffered part to default */
+    } else {
+        trace_ot_otp_integrity_report(s->ot_id,
+                                      ot_otp_engine_part_name(s, part_ix),
+                                      part_ix, "digest OK");
+    }
+}
+
+static bool ot_otp_engine_is_backend_writable(OtOTPEngineState *s)
+{
+    return (s->blk != NULL) && blk_is_writable(s->blk);
+}
+
+static inline int ot_otp_engine_write_backend(
+    OtOTPEngineState *s, const void *buffer, unsigned offset, size_t size)
+{
+    /*
+     * the blk_pwrite API is awful, isolate it so that linter exceptions are
+     * are not repeated over and over
+     */
+    g_assert(offset + size <= s->otp->size);
+
+    /* NOLINTBEGIN(clang-analyzer-optin.core.EnumCastOutOfRange) */
+    return blk_pwrite(s->blk, (int64_t)(intptr_t)offset, (int64_t)size, buffer,
+                      /* a bitfield of enum is not an enum item */
+                      (BdrvRequestFlags)0);
+    /* NOLINTEND(clang-analyzer-optin.core.EnumCastOutOfRange) */
+}
+
+static void ot_otp_engine_dai_init(OtOTPEngineState *s)
+{
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_IDLE);
+}
+
+static void ot_otp_engine_dai_set_error(OtOTPEngineState *s, OtOTPError err)
+{
+    ot_otp_engine_set_error(s, OTP_ENTRY_DAI(s), err);
+
+    switch (err) {
+    case OT_OTP_FSM_STATE_ERROR:
+    case OT_OTP_MACRO_ERROR:
+    case OT_OTP_MACRO_ECC_UNCORR_ERROR:
+        DAI_CHANGE_STATE(s, OT_OTP_DAI_ERROR);
+        break;
+    default:
+        DAI_CHANGE_STATE(s, OT_OTP_DAI_IDLE);
+        break;
+    }
+}
+
+static void ot_otp_engine_dai_clear_error(OtOTPEngineState *s)
+{
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(s);
+
+    ic->update_status_error(OT_OTP_IMPL_IF(s), OT_OTP_STATUS_DAI, false);
+
+    ERR_CODE_PART_REG(s, OTP_ENTRY_DAI(s)) = 0u;
+}
+
+static void ot_otp_engine_dai_read(OtOTPEngineState *s)
+{
+    if (ot_otp_engine_dai_is_busy(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: DAI controller busy: %s\n",
+                      __func__, s->ot_id, DAI_STATE_NAME(s->dai->state));
+        return;
+    }
+
+    ot_otp_engine_dai_clear_error(s);
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_READ);
+
+    unsigned address = DIRECT_ACCESS_REG(s, ADDRESS);
+
+    int partition = ot_otp_engine_get_part_from_address(s, address);
+
+    if (partition < 0) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: invalid partition address 0x%x\n", __func__,
+                      s->ot_id, address);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    unsigned part_ix = (unsigned)partition;
+    if (part_ix >= s->part_lc_num) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: life cycle partition cannot be accessed from DAI\n",
+            __func__, s->ot_id);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    const OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+    if (pctrl->failed) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: partition %s is disabled\n",
+                      __func__, s->ot_id, ot_otp_engine_part_name(s, part_ix));
+        return;
+    }
+
+    bool is_readable = ot_otp_engine_is_readable(s, part_ix);
+    bool is_buffered = ot_otp_engine_is_buffered(s, part_ix);
+    bool is_secret = ot_otp_engine_is_secret(s, part_ix);
+    bool is_digest = ot_otp_engine_is_part_digest_offset(s, part_ix, address);
+    bool is_zer = ot_otp_engine_is_part_zer_offset(s, part_ix, address);
+
+    /* in all partitions, the digest and zer fields are always readable. */
+    if (!is_digest && !is_zer && !is_readable) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: partition %s @ 0x%04x not readable\n", __func__,
+                      s->ot_id, ot_otp_engine_part_name(s, part_ix), address);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    unsigned part_offset = address - ot_otp_engine_part_data_offset(s, part_ix);
+    unsigned part_waddr = part_offset >> 2u;
+    bool do_ecc =
+        s->part_descs[part_ix].integrity && ot_otp_engine_is_ecc_enabled(s);
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_READ_WAIT);
+
+    uint32_t data_lo, data_hi;
+    unsigned err = 0;
+    unsigned cell_count = sizeof(uint32_t) + (do_ecc ? sizeof(uint16_t) : 0);
+
+    const uint32_t *data = (const uint32_t *)s->otp->data;
+    /* parenthesis inform the C linter sizeof() call is valid with 'data */
+    data += (ot_otp_engine_part_data_offset(s, part_ix) / sizeof(uint32_t));
+
+    bool is_wide = is_digest || is_zer || is_secret;
+    if (is_wide) {
+        /* 64-bit requests */
+        part_waddr &= ~0b1u;
+
+        g_assert((part_waddr + 1u) * sizeof(uint32_t) <
+                 s->part_descs[part_ix].size);
+
+        data_lo = data[part_waddr];
+        data_hi = data[part_waddr + 1u];
+
+        if (do_ecc) {
+            unsigned ewaddr = address >> 3u;
+            g_assert(ewaddr < s->otp->ecc_size);
+            uint32_t ecc = s->otp->ecc[ewaddr];
+            if (ot_otp_engine_is_ecc_enabled(s)) {
+                data_lo =
+                    ot_otp_engine_verify_ecc(s, data_lo, ecc & 0xffffu, &err);
+                data_hi =
+                    ot_otp_engine_verify_ecc(s, data_hi, ecc >> 16u, &err);
+            }
+        }
+
+        cell_count *= 2u;
+    } else {
+        /* 32-bit request */
+        g_assert(part_waddr * sizeof(uint32_t) < s->part_descs[part_ix].size);
+
+        data_lo = data[part_waddr];
+        data_hi = 0u;
+
+        if (do_ecc) {
+            unsigned ewaddr = address >> 3u;
+            g_assert(ewaddr < s->otp->ecc_size);
+            uint32_t ecc = s->otp->ecc[ewaddr];
+            if ((address >> 2u) & 1u) {
+                ecc >>= 16u;
+            }
+            if (ot_otp_engine_is_ecc_enabled(s)) {
+                data_lo =
+                    ot_otp_engine_verify_ecc(s, data_lo, ecc & 0xffffu, &err);
+            }
+            cell_count = 4u + 2u;
+        } else {
+            cell_count = 4u;
+        }
+    }
+
+    if (is_secret && !(is_zer || is_digest)) {
+        /*
+         * if the partition is a secret partition, OTP storage is scrambled
+         * except the digest and the zeroification fields
+         */
+        g_assert(pctrl->otp_scramble_key);
+        uint64_t tmp_data = ((uint64_t)data_hi << 32u) | data_lo;
+        OtPresentState *ps = ot_present_new();
+        ot_present_init(ps, pctrl->otp_scramble_key);
+        ot_present_decrypt(ps, tmp_data, &tmp_data);
+        ot_present_free(ps);
+        data_lo = (uint32_t)tmp_data;
+        data_hi = (uint32_t)(tmp_data >> 32u);
+    }
+
+    DIRECT_ACCESS_REG(s, RDATA_0) = data_lo;
+    DIRECT_ACCESS_REG(s, RDATA_1) = data_hi;
+
+    if (err) {
+        OtOTPError otp_err = (err > 1) ? OT_OTP_MACRO_ECC_UNCORR_ERROR :
+                                         OT_OTP_MACRO_ECC_CORR_ERROR;
+        ot_otp_engine_dai_set_error(s, otp_err);
+        return;
+    }
+
+    s->dai->partition = partition;
+
+    if (!is_buffered) {
+        /* fake slow access to OTP cell */
+        unsigned access_time = s->be_chars.timings.read_ns * cell_count;
+        timer_mod(s->dai->delay,
+                  qemu_clock_get_ns(OT_VIRTUAL_CLOCK) + access_time);
+    } else {
+        DAI_CHANGE_STATE(s, OT_OTP_DAI_IDLE);
+    }
+}
+
+static int ot_otp_engine_dai_write_u64(OtOTPEngineState *s, unsigned address)
+{
+    unsigned waddr = (address / sizeof(uint32_t)) & ~1u;
+    uint32_t *dst = &s->otp->data[waddr];
+
+    uint32_t dst_lo = dst[0u];
+    uint32_t dst_hi = dst[1u];
+
+    uint32_t lo = DIRECT_ACCESS_REG(s, WDATA_0);
+    uint32_t hi = DIRECT_ACCESS_REG(s, WDATA_1);
+
+    unsigned part_ix = (unsigned)s->dai->partition;
+    bool is_secret = ot_otp_engine_is_secret(s, part_ix);
+    bool is_zer = ot_otp_engine_is_part_zer_offset(s, part_ix, address);
+
+    if (is_secret && !is_zer) {
+        OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+        g_assert(pctrl->otp_scramble_key);
+
+        uint64_t data = ((uint64_t)hi << 32u) | lo;
+        OtPresentState *ps = ot_present_new();
+        ot_present_init(ps, pctrl->otp_scramble_key);
+        ot_present_encrypt(ps, data, &data);
+        lo = (uint32_t)data;
+        hi = (uint32_t)(data >> 32u);
+    }
+
+    if ((dst_lo & ~lo) || (dst_hi & ~hi)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Cannot clear OTP bits\n",
+                      __func__, s->ot_id);
+        ot_otp_engine_set_error(s, OTP_ENTRY_DAI(s),
+                                OT_OTP_MACRO_WRITE_BLANK_ERROR);
+    }
+
+    dst[0u] |= lo;
+    dst[1u] |= hi;
+
+    uintptr_t offset = (uintptr_t)s->otp->data - (uintptr_t)s->otp->storage;
+    if (ot_otp_engine_write_backend(s, dst,
+                                    (unsigned)(offset +
+                                               waddr * sizeof(uint32_t)),
+                                    sizeof(uint64_t))) {
+        error_report("%s: %s: cannot update OTP backend", __func__, s->ot_id);
+        ot_otp_engine_dai_set_error(s, OT_OTP_MACRO_ERROR);
+        return -1;
+    }
+
+    if (ot_otp_engine_is_ecc_enabled(s)) {
+        unsigned ewaddr = waddr >> 1u;
+        g_assert(ewaddr < s->otp->ecc_size);
+        uint32_t *edst = &s->otp->ecc[ewaddr];
+
+        uint32_t ecc_lo = (uint32_t)ot_otp_engine_compute_ecc_u32(lo);
+        uint32_t ecc_hi = (uint32_t)ot_otp_engine_compute_ecc_u32(hi);
+        uint32_t ecc = (ecc_hi << 16u) | ecc_lo;
+
+        if (*edst & ~ecc) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: Cannot clear OTP ECC bits\n", __func__,
+                          s->ot_id);
+            ot_otp_engine_set_error(s, OTP_ENTRY_DAI(s),
+                                    OT_OTP_MACRO_WRITE_BLANK_ERROR);
+        }
+        *edst |= ecc;
+
+        offset = (uintptr_t)s->otp->ecc - (uintptr_t)s->otp->storage;
+        if (ot_otp_engine_write_backend(s, edst,
+                                        (unsigned)(offset + (waddr << 1u)),
+                                        sizeof(uint32_t))) {
+            error_report("%s: %s: cannot update OTP backend", __func__,
+                         s->ot_id);
+            ot_otp_engine_dai_set_error(s, OT_OTP_MACRO_ERROR);
+            return -1;
+        }
+
+        trace_ot_otp_dai_new_dword_ecc(s->ot_id,
+                                       ot_otp_engine_part_name(s,
+                                                               (unsigned)s->dai
+                                                                   ->partition),
+                                       s->dai->partition, *dst, *edst);
+    }
+
+    return 0;
+}
+
+static int ot_otp_engine_dai_write_u32(OtOTPEngineState *s, unsigned address)
+{
+    unsigned waddr = address / sizeof(uint32_t);
+    uint32_t *dst = &s->otp->data[waddr];
+    uint32_t data = DIRECT_ACCESS_REG(s, WDATA_0);
+
+    if (*dst & ~data) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: cannot clear OTP bits\n",
+                      __func__, s->ot_id);
+        ot_otp_engine_set_error(s, OTP_ENTRY_DAI(s),
+                                OT_OTP_MACRO_WRITE_BLANK_ERROR);
+    }
+
+    *dst |= data;
+
+    uintptr_t offset = (uintptr_t)s->otp->data - (uintptr_t)s->otp->storage;
+    if (ot_otp_engine_write_backend(s, dst,
+                                    (unsigned)(offset +
+                                               waddr * sizeof(uint32_t)),
+                                    sizeof(uint32_t))) {
+        error_report("%s: %s: cannot update OTP backend", __func__, s->ot_id);
+        ot_otp_engine_dai_set_error(s, OT_OTP_MACRO_ERROR);
+        return -1;
+    }
+
+    if (ot_otp_engine_is_ecc_enabled(s)) {
+        g_assert((waddr >> 1u) < s->otp->ecc_size);
+        uint16_t *edst = &((uint16_t *)s->otp->ecc)[waddr];
+        uint16_t ecc = ot_otp_engine_compute_ecc_u32(*dst);
+
+        if (*edst & ~ecc) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: cannot clear OTP ECC bits\n", __func__,
+                          s->ot_id);
+            ot_otp_engine_set_error(s, OTP_ENTRY_DAI(s),
+                                    OT_OTP_MACRO_WRITE_BLANK_ERROR);
+        }
+        *edst |= ecc;
+
+        offset = (uintptr_t)s->otp->ecc - (uintptr_t)s->otp->storage;
+        if (ot_otp_engine_write_backend(s, edst,
+                                        (unsigned)(offset + (address >> 1u)),
+                                        sizeof(uint16_t))) {
+            error_report("%s: %s: cannot update OTP backend", __func__,
+                         s->ot_id);
+            ot_otp_engine_dai_set_error(s, OT_OTP_MACRO_ERROR);
+            return -1;
+        }
+
+        trace_ot_otp_dai_new_word_ecc(s->ot_id,
+                                      ot_otp_engine_part_name(s,
+                                                              (unsigned)s->dai
+                                                                  ->partition),
+                                      s->dai->partition, *dst, *edst);
+    }
+
+    return 0;
+}
+
+static void ot_otp_engine_dai_write(OtOTPEngineState *s)
+{
+    if (ot_otp_engine_dai_is_busy(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: DAI controller busy: %s\n",
+                      __func__, s->ot_id, DAI_STATE_NAME(s->dai->state));
+        return;
+    }
+
+    if (!ot_otp_engine_is_backend_writable(s)) {
+        /* OTP backend missing or read-only; reject any write request */
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: OTP backend file is missing or R/O\n", __func__,
+                      s->ot_id);
+        ot_otp_engine_dai_set_error(s, OT_OTP_MACRO_ERROR);
+        return;
+    }
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_WRITE);
+
+    ot_otp_engine_dai_clear_error(s);
+
+    unsigned address = DIRECT_ACCESS_REG(s, ADDRESS);
+
+    int partition = ot_otp_engine_get_part_from_address(s, address);
+
+    if (partition < 0) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: invalid partition address 0x%x\n", __func__,
+                      s->ot_id, address);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    unsigned part_ix = (unsigned)partition;
+
+    if (part_ix >= s->part_lc_num) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: Life cycle partition cannot be accessed from DAI\n",
+            __func__, s->ot_id);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+
+    if (pctrl->failed) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: partition %s is disabled\n",
+                      __func__, s->ot_id, ot_otp_engine_part_name(s, part_ix));
+        return;
+    }
+
+    if (pctrl->locked) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: partition %s (%u) is locked\n",
+                      __func__, s->ot_id, ot_otp_engine_part_name(s, part_ix),
+                      part_ix);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    if (pctrl->write_lock) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: artition %s (%u) is write locked\n", __func__,
+                      s->ot_id, ot_otp_engine_part_name(s, part_ix), part_ix);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    bool is_digest = ot_otp_engine_is_part_digest_offset(s, part_ix, address);
+
+    if (is_digest) {
+        if (s->part_descs[part_ix].hw_digest) {
+            /* should have been a Digest command, not a Write command */
+            qemu_log_mask(
+                LOG_GUEST_ERROR,
+                "%s: %s: partition %s (%u) HW digest cannot be directly "
+                "written\n",
+                __func__, s->ot_id, ot_otp_engine_part_name(s, part_ix),
+                part_ix);
+            ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+            return;
+        }
+    }
+
+    s->dai->partition = partition;
+
+    bool do_ecc = ot_otp_engine_is_ecc_enabled(s);
+    unsigned cell_count = sizeof(uint32_t);
+
+    bool is_secret = ot_otp_engine_is_secret(s, part_ix);
+    bool is_zer = ot_otp_engine_is_part_zer_offset(s, part_ix, address);
+
+    bool is_wide = is_secret || is_digest || is_zer;
+    if (is_wide) {
+        if (ot_otp_engine_dai_write_u64(s, address)) {
+            return;
+        }
+        cell_count *= 2u;
+    } else {
+        if (ot_otp_engine_dai_write_u32(s, address)) {
+            return;
+        }
+    }
+
+    if (do_ecc) {
+        cell_count += cell_count / 2u;
+    };
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_WRITE_WAIT);
+
+    /* fake slow update of OTP cell */
+    unsigned update_time = s->be_chars.timings.write_ns * cell_count;
+    timer_mod(s->dai->delay, qemu_clock_get_ns(OT_VIRTUAL_CLOCK) + update_time);
+}
+
+static void ot_otp_engine_dai_digest(OtOTPEngineState *s)
+{
+    if (ot_otp_engine_dai_is_busy(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: DAI controller busy: %s\n",
+                      __func__, s->ot_id, DAI_STATE_NAME(s->dai->state));
+        return;
+    }
+
+    if (!ot_otp_engine_is_backend_writable(s)) {
+        /* OTP backend missing or read-only; reject any write request */
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: OTP backend file is missing or R/O\n", __func__,
+                      s->ot_id);
+        ot_otp_engine_dai_set_error(s, OT_OTP_MACRO_ERROR);
+        return;
+    }
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_DIG_CLR);
+
+    ot_otp_engine_dai_clear_error(s);
+
+    unsigned address = DIRECT_ACCESS_REG(s, ADDRESS);
+
+    int partition = ot_otp_engine_get_part_from_address(s, address);
+
+    if (partition < 0) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Invalid partition address 0x%x\n", __func__,
+                      s->ot_id, address);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    unsigned part_ix = (unsigned)partition;
+
+    if (part_ix >= s->part_lc_num) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: Life cycle partition cannot be accessed from DAI\n",
+            __func__, s->ot_id);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    if (!s->part_descs[part_ix].hw_digest) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Invalid partition, no HW digest on %s (#%u)\n",
+                      __func__, s->ot_id, ot_otp_engine_part_name(s, part_ix),
+                      part_ix);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+
+    if (pctrl->failed) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: partition %s is disabled\n",
+                      __func__, s->ot_id, ot_otp_engine_part_name(s, part_ix));
+        return;
+    }
+
+    if (pctrl->locked) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Partition %s (%u) is locked\n",
+                      __func__, s->ot_id, ot_otp_engine_part_name(s, part_ix),
+                      part_ix);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    if (pctrl->write_lock) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Partition %s (%u) is write locked\n", __func__,
+                      s->ot_id, ot_otp_engine_part_name(s, part_ix), part_ix);
+        ot_otp_engine_dai_set_error(s, OT_OTP_ACCESS_ERROR);
+        return;
+    }
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_DIG_READ);
+
+    const uint8_t *data = ((const uint8_t *)s->otp->data) +
+                          ot_otp_engine_part_data_offset(s, part_ix);
+    unsigned part_size = ot_otp_engine_part_data_byte_size(s, part_ix);
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_DIG);
+
+    pctrl->buffer.next_digest =
+        ot_otp_engine_compute_partition_digest(s, data, part_size);
+    s->dai->partition = partition;
+
+    TRACE_OTP("%s: %s: next digest %016" PRIx64 " from %s\n", __func__,
+              s->ot_id, pctrl->buffer.next_digest,
+              ot_otp_hexdump(s, data, part_size));
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_DIG_WAIT);
+
+    /* fake slow update of OTP cell */
+    timer_mod(s->dai->delay,
+              qemu_clock_get_ns(OT_VIRTUAL_CLOCK) + DAI_DIGEST_DELAY_NS);
+}
+
+static void ot_otp_engine_dai_write_digest(void *opaque)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(opaque);
+
+    g_assert((s->dai->partition >= 0) && (s->dai->partition < s->part_count));
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_WRITE);
+
+    unsigned part_ix = (unsigned)s->dai->partition;
+    OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+    unsigned address = s->part_descs[part_ix].digest_offset;
+    unsigned dwaddr = address / sizeof(uint64_t);
+    uint64_t *dst = &((uint64_t *)s->otp->data)[dwaddr];
+    uint64_t data = pctrl->buffer.next_digest;
+    pctrl->buffer.next_digest = 0;
+
+    if (*dst & ~data) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: cannot clear OTP data bits\n",
+                      __func__, s->ot_id);
+        ot_otp_engine_set_error(s, OTP_ENTRY_DAI(s),
+                                OT_OTP_MACRO_WRITE_BLANK_ERROR);
+    }
+    *dst |= data;
+
+    uintptr_t offset;
+    offset = (uintptr_t)s->otp->data - (uintptr_t)s->otp->storage;
+    if (ot_otp_engine_write_backend(s, dst, (unsigned)(offset + address),
+                                    sizeof(uint64_t))) {
+        error_report("%s: %s: cannot update OTP backend", __func__, s->ot_id);
+        ot_otp_engine_dai_set_error(s, OT_OTP_MACRO_ERROR);
+        return;
+    }
+
+    uint32_t ecc = ot_otp_engine_compute_ecc_u64(data);
+
+    /* dwaddr is 64-bit based, convert it to 32-bit base for ECC */
+    unsigned ewaddr = (dwaddr << 1u) / s->otp->ecc_granule;
+    g_assert(ewaddr < s->otp->ecc_size);
+    uint32_t *edst = &s->otp->ecc[ewaddr];
+
+    if (*edst & ~ecc) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: cannot clear OTP ECC bits\n",
+                      __func__, s->ot_id);
+        ot_otp_engine_set_error(s, OTP_ENTRY_DAI(s),
+                                OT_OTP_MACRO_WRITE_BLANK_ERROR);
+    }
+    *edst |= ecc;
+
+    offset = (uintptr_t)s->otp->ecc - (uintptr_t)s->otp->storage;
+    if (ot_otp_engine_write_backend(s, edst,
+                                    (unsigned)(offset + (ewaddr << 2u)),
+                                    sizeof(uint32_t))) {
+        error_report("%s: %s: cannot update OTP backend", __func__, s->ot_id);
+        ot_otp_engine_dai_set_error(s, OT_OTP_MACRO_ERROR);
+        return;
+    }
+
+    trace_ot_otp_dai_new_digest_ecc(s->ot_id,
+                                    ot_otp_engine_part_name(s, part_ix),
+                                    part_ix, *dst, *edst);
+
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_WRITE_WAIT);
+
+    /* fake slow update of OTP cell */
+    unsigned cell_count = sizeof(uint64_t) + sizeof(uint32_t);
+    unsigned update_time = s->be_chars.timings.write_ns * cell_count;
+    timer_mod(s->dai->delay, qemu_clock_get_ns(OT_VIRTUAL_CLOCK) + update_time);
+}
+
+static void ot_otp_engine_dai_complete(void *opaque)
+{
+    OtOTPEngineState *s = opaque;
+
+    switch (s->dai->state) {
+    case OT_OTP_DAI_READ_WAIT:
+        g_assert(s->dai->partition >= 0);
+        trace_ot_otp_dai_read(s->ot_id,
+                              ot_otp_engine_part_name(s, (unsigned)
+                                                             s->dai->partition),
+                              (unsigned)s->dai->partition,
+                              DIRECT_ACCESS_REG(s, RDATA_0),
+                              DIRECT_ACCESS_REG(s, RDATA_1));
+        s->dai->partition = -1;
+        DAI_CHANGE_STATE(s, OT_OTP_DAI_IDLE);
+        break;
+    case OT_OTP_DAI_WRITE_WAIT:
+        g_assert(s->dai->partition >= 0);
+        s->regs[R_INTR_STATE] |= INTR_OTP_OPERATION_DONE_MASK;
+        s->dai->partition = -1;
+        DAI_CHANGE_STATE(s, OT_OTP_DAI_IDLE);
+        break;
+    case OT_OTP_DAI_DIG_WAIT:
+        g_assert(s->dai->partition >= 0);
+        int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+        timer_mod(s->dai->digest_write, now + DIGEST_DECOUPLE_DELAY_NS);
+        break;
+    case OT_OTP_DAI_ERROR:
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    };
+}
+
+static void ot_otp_engine_lci_init(OtOTPEngineState *s)
+{
+    LCI_CHANGE_STATE(s, OT_OTP_LCI_IDLE);
+}
+
+static const OtOTPHWCfg *ot_otp_engine_get_hw_cfg(const OtOTPIf *dev)
+{
+    const OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+
+    return (const OtOTPHWCfg *)s->hw_cfg;
+}
+
+static void ot_otp_engine_request_entropy(void *opaque)
+{
+    OtOTPEngineState *s = opaque;
+
+    /*
+     * Use a BH as entropy should be filled in as soon as possible after reset.
+     * However, as the EDN / OTP reset order is unknown, this initial request
+     * can only be performed once the reset sequence is over.
+     */
+    if (!s->keygen->edn_sched) {
+        int rc = ot_edn_request_entropy(s->edn, s->edn_ep);
+        g_assert(rc == 0);
+        s->keygen->edn_sched = true;
+    }
+}
+
+static void
+ot_otp_engine_keygen_push_entropy(void *opaque, uint32_t bits, bool fips)
+{
+    OtOTPEngineState *s = opaque;
+    (void)fips;
+
+    s->keygen->edn_sched = false;
+
+    if (!ot_fifo32_is_full(&s->keygen->entropy_buf)) {
+        ot_fifo32_push(&s->keygen->entropy_buf, bits);
+    }
+
+    bool resched = !ot_fifo32_is_full(&s->keygen->entropy_buf);
+
+    trace_ot_otp_keygen_entropy(s->ot_id,
+                                ot_fifo32_num_used(&s->keygen->entropy_buf),
+                                resched);
+
+    if (resched && !s->keygen->edn_sched) {
+        int64_t now = qemu_clock_get_ns(OT_OTP_HW_CLOCK);
+        timer_mod(s->keygen->request_entropy,
+                  now + ENTROPY_RESCHEDULE_DELAY_NS);
+    }
+}
+
+static void ot_otp_engine_fake_entropy(OtOTPEngineState *s, unsigned count)
+{
+    /*
+     * This part departs from real HW: OTP needs to have bufferized enough
+     * entropy for any SRAM OTP key request to be successfully completed.
+     * On real HW, entropy is requested on demand, but in QEMU this very API
+     * (#get_otp_key) needs to be synchronous, as it should be able to complete
+     * on SRAM controller I/O request, which is itself fully synchronous.
+     * When not enough entropy has been initiatially collected, this function
+     * adds some fake entropy to entropy buffer. The main use case is to enable
+     * SRAM initialization with random values and does not need to be truly
+     * secure, while limiting emulation code size and complexity.
+     */
+
+    OtOTPKeyGen *kgen = s->keygen;
+    while (count-- && !ot_fifo32_is_full(&kgen->entropy_buf)) {
+        ot_fifo32_push(&kgen->entropy_buf, ot_prng_random_u32(kgen->prng));
+    }
+}
+
+/*
+ * See
+ * https://opentitan.org/book/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/
+ * theory_of_operation.html#scrambling-datapath
+ *
+ * The `fetch_nonce_entropy` field refers to the fetching of additional
+ * entropy for the nonce output.
+ *
+ * The `ingest_entropy` field indicates whether an additional 128 bit entropy
+ * block should be ingested after the seed. That is, `true` will
+ * derive an ephemeral scrambling key (path C) and `false` will derive a static
+ * scrambling key (path D).
+ *
+ * Will fake entropy if there is not enough available, rather than waiting.
+ */
+static void ot_otp_engine_generate_scrambling_key(
+    OtOTPEngineState *s, OtOTPKey *key, OtOTPKeyType type, uint64_t k_iv,
+    const uint8_t *k_const, bool fetch_nonce_entropy, bool ingest_entropy)
+{
+    g_assert(type < OT_OTP_KEY_COUNT);
+    g_assert(key->seed_size < OT_OTP_SEED_MAX_SIZE);
+    g_assert(key->nonce_size < OT_OTP_NONCE_MAX_SIZE);
+
+    g_assert(key->seed_size % sizeof(uint32_t) == 0u);
+    g_assert(key->nonce_size % sizeof(uint32_t) == 0u);
+    unsigned seed_words = key->seed_size / sizeof(uint32_t);
+    unsigned nonce_words = key->nonce_size / sizeof(uint32_t);
+    unsigned scramble_blocks = key->seed_size / sizeof(uint64_t);
+
+    OtFifo32 *entropy = &s->keygen->entropy_buf;
+
+    /* for QEMU emulation, fake entropy instead of waiting */
+    unsigned avail_entropy = ot_fifo32_num_used(entropy);
+    unsigned needed_entropy = 0u;
+    needed_entropy += fetch_nonce_entropy ? nonce_words : 0u;
+    needed_entropy += ingest_entropy ? (seed_words * scramble_blocks) : 0u;
+    if (avail_entropy < needed_entropy) {
+        unsigned count = needed_entropy - avail_entropy;
+        error_report("%s: %s: not enough entropy for key %d, fake %u words",
+                     __func__, s->ot_id, type, count);
+        ot_otp_engine_fake_entropy(s, count);
+    }
+
+    if (fetch_nonce_entropy) {
+        /* fill in the nonce using entropy */
+        g_assert(ot_fifo32_num_used(entropy) >= nonce_words);
+        for (unsigned ix = 0; ix < nonce_words; ix++) {
+            stl_le_p(&key->nonce[ix * sizeof(uint32_t)],
+                     ot_fifo32_pop(entropy));
+        }
+    }
+
+    OtPresentState *ps = s->keygen->present;
+
+    /* obtain the key seed from the OTP SECRET partition(s) */
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(s);
+    g_assert(ic->key_seeds);
+    unsigned part_ix = ic->key_seeds[type].partition;
+    /*
+     * assume the key seeds are never stored in the first partition.
+     * if partition is zero, the slot contains no key seed.
+     * there is no reason for this API client to request a key seed which is
+     * not available on the current Top.
+     */
+    g_assert(ic->key_seeds[type].partition);
+    unsigned key_offset = ic->key_seeds[type].offset;
+    g_assert(part_ix < s->part_count);
+    g_assert(key_offset <= s->part_descs[part_ix].size - key->seed_size);
+
+    OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+    g_assert(ot_otp_engine_is_buffered(s, part_ix));
+    const uint32_t *key_seed = &pctrl->buffer.data[key_offset];
+
+    /* check the key seed's validity */
+    key->seed_valid = pctrl->locked && !pctrl->failed;
+
+    uint32_t *ephemeral_entropy = g_new0(uint32_t, seed_words);
+    for (unsigned rix = 0; rix < scramble_blocks; rix++) {
+        /* compress the IV state with the OTP key seed */
+        uint64_t data = k_iv;
+        ot_present_init(ps, (const uint8_t *)key_seed);
+        ot_present_encrypt(ps, data, &data);
+
+        if (ingest_entropy) {
+            /* ephemeral keys ingest different entropy each round */
+            g_assert(ot_fifo32_num_used(entropy) >= seed_words);
+            for (unsigned ix = 0; ix < seed_words; ix++) {
+                ephemeral_entropy[ix] = ot_fifo32_pop(entropy);
+            }
+
+            ot_present_init(ps, (uint8_t *)&ephemeral_entropy[0]);
+            ot_present_encrypt(ps, data, &data);
+        }
+
+        /* compress with the finalization constant*/
+        ot_present_init(ps, k_const);
+        ot_present_encrypt(ps, data, &data);
+
+        /* write back to the key */
+        for (unsigned ix = 0; ix < sizeof(uint64_t); ix++) {
+            unsigned seed_byte = rix * sizeof(uint64_t) + ix;
+            key->seed[seed_byte] = (uint8_t)(data >> (ix * 8u));
+        }
+    }
+    g_free(ephemeral_entropy);
+
+    trace_ot_otp_key_generated(s->ot_id, type);
+
+    if (needed_entropy) {
+        /* some entropy bits have been used, refill the buffer */
+        int64_t now = qemu_clock_get_ns(OT_OTP_HW_CLOCK);
+        timer_mod(s->keygen->request_entropy,
+                  now + ENTROPY_RESCHEDULE_DELAY_NS);
+    }
+}
+
+static void ot_otp_engine_get_otp_key(OtOTPIf *dev, OtOTPKeyType type,
+                                      OtOTPKey *key)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(s);
+
+    trace_ot_otp_get_otp_key(s->ot_id, type);
+
+    /* reference: req_bundles in OpenTitan rtl/otp_ctrl_kdi.sv */
+    const uint64_t *iv;
+    const uint8_t *constant;
+    bool ingest_entropy;
+    switch (type) {
+    case OT_OTP_KEY_FLASH_DATA:
+        if (!ic->has_flash_support) {
+            iv = NULL;
+            break;
+        }
+        key->seed_size = (uint8_t)ic->key_seeds[type].size;
+        key->nonce_size = key->seed_size;
+        iv = &s->flash_data_iv;
+        constant = s->flash_data_const;
+        ingest_entropy = false;
+        break;
+    case OT_OTP_KEY_FLASH_ADDR:
+        if (!ic->has_flash_support) {
+            iv = NULL;
+            break;
+        }
+        key->seed_size = (uint8_t)ic->key_seeds[type].size;
+        key->nonce_size = 0u;
+        iv = &s->flash_addr_iv;
+        constant = s->flash_addr_const;
+        ingest_entropy = false;
+        break;
+    case OT_OTP_KEY_OTBN:
+        key->seed_size = (uint8_t)ic->key_seeds[type].size;
+        key->nonce_size = key->seed_size / 2u;
+        iv = &s->sram_iv;
+        constant = s->sram_const;
+        ingest_entropy = true;
+        break;
+    case OT_OTP_KEY_SRAM:
+        key->seed_size = (uint8_t)ic->key_seeds[type].size;
+        key->nonce_size = key->seed_size;
+        iv = &s->sram_iv;
+        constant = s->sram_const;
+        ingest_entropy = true;
+        break;
+    default:
+        iv = NULL;
+        ingest_entropy = false;
+        break;
+    }
+
+    if (!iv) {
+        error_report("%s: %s: invalid OTP key type: %d", __func__, s->ot_id,
+                     type);
+        g_assert_not_reached();
+    }
+
+    g_assert(key->seed_size <= sizeof(s->scrmbl_key_init->key));
+    g_assert(key->nonce_size <= sizeof(s->scrmbl_key_init->nonce));
+    memcpy(key->seed, s->scrmbl_key_init->key, key->seed_size);
+    memcpy(key->nonce, s->scrmbl_key_init->nonce, key->nonce_size);
+    key->seed_valid = false;
+    ot_otp_engine_generate_scrambling_key(s, key, type, *iv, constant, true,
+                                          ingest_entropy);
+}
+
+static bool ot_otp_engine_program_req(OtOTPIf *dev, const uint16_t *lc_tcount,
+                                      const uint16_t *lc_state,
+                                      ot_otp_program_ack_fn ack, void *opaque)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+    OtOTPLCIController *lci = s->lci;
+
+    switch (lci->state) {
+    case OT_OTP_LCI_IDLE:
+    case OT_OTP_LCI_ERROR:
+        /* error case is handled asynchronously */
+        g_assert(!(lci->ack_fn || lci->ack_data));
+        break;
+    case OT_OTP_LCI_WRITE:
+    case OT_OTP_LCI_WRITE_WAIT:
+        /* another LC programming request is on-going */
+        return false;
+    case OT_OTP_LCI_RESET:
+        /* cannot reach this point if PwrMgr init has been executed */
+    default:
+        g_assert_not_reached();
+        break;
+    }
+
+    lci->ack_fn = ack;
+    lci->ack_data = opaque;
+
+    if (lci->state == OT_OTP_LCI_IDLE) {
+        unsigned hpos = 0;
+        memcpy(&lci->data[hpos], lc_tcount, LC_TRANSITION_CNT_SIZE);
+        hpos += LC_TRANSITION_CNT_SIZE / sizeof(uint16_t);
+        memcpy(&lci->data[hpos], lc_state, LC_STATE_SIZE);
+        hpos += LC_STATE_SIZE / sizeof(uint16_t);
+        g_assert(hpos == s->part_descs[s->part_lc_num].size / sizeof(uint16_t));
+
+        /* current position in LC buffer to write to backend */
+        lci->hpos = 0u;
+    }
+
+    /*
+     * schedule even if LCI FSM is already in error to report the issue
+     * asynchronously
+     */
+    timer_mod(lci->prog_delay,
+              qemu_clock_get_ns(OT_OTP_HW_CLOCK) + LCI_PROG_SCHED_NS);
+
+    return true;
+}
+
+static void ot_otp_engine_lci_write_complete(OtOTPEngineState *s, bool success)
+{
+    OtOTPLCIController *lci = s->lci;
+
+    if (lci->hpos) {
+        /*
+         * if the LC partition has been modified somehow, even if the request
+         * has failed, update the backend file
+         */
+        const OtOTPPartDesc *lcdesc = &s->part_descs[s->part_lc_num];
+        unsigned lc_off = lcdesc->offset / sizeof(uint32_t);
+        uintptr_t offset = (uintptr_t)s->otp->data - (uintptr_t)s->otp->storage;
+        if (ot_otp_engine_write_backend(s, &s->otp->data[lc_off],
+                                        (unsigned)(offset + lcdesc->offset),
+                                        lcdesc->size)) {
+            error_report("%s: %s: cannot update OTP backend", __func__,
+                         s->ot_id);
+            if (lci->error == OT_OTP_NO_ERROR) {
+                lci->error = OT_OTP_MACRO_ERROR;
+                LCI_CHANGE_STATE(s, OT_OTP_LCI_ERROR);
+            }
+        }
+        if (ot_otp_engine_is_ecc_enabled(s)) {
+            offset = (uintptr_t)s->otp->ecc - (uintptr_t)s->otp->storage;
+            if (ot_otp_engine_write_backend(s,
+                                            &((uint16_t *)s->otp->ecc)[lc_off],
+                                            (unsigned)(offset +
+                                                       (lcdesc->offset >> 1u)),
+                                            lcdesc->size >> 1u)) {
+                error_report("%s: %s: cannot update OTP backend", __func__,
+                             s->ot_id);
+                if (lci->error == OT_OTP_NO_ERROR) {
+                    lci->error = OT_OTP_MACRO_ERROR;
+                    LCI_CHANGE_STATE(s, OT_OTP_LCI_ERROR);
+                }
+            }
+        }
+    }
+
+    g_assert(lci->ack_fn);
+    ot_otp_program_ack_fn ack_fn = lci->ack_fn;
+    void *ack_data = lci->ack_data;
+    lci->ack_fn = NULL;
+    lci->ack_data = NULL;
+    lci->hpos = 0u;
+
+    if (!success && lci->error != OT_OTP_NO_ERROR) {
+        ot_otp_engine_set_error(s, s->part_lc_num, lci->error);
+    }
+
+    (*ack_fn)(ack_data, success);
+}
+
+static void ot_otp_engine_lci_write_word(void *opaque)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(opaque);
+    OtOTPLCIController *lci = s->lci;
+    const OtOTPPartDesc *lcdesc = &s->part_descs[s->part_lc_num];
+
+    /* should not be called if already in error */
+    if (lci->state == OT_OTP_LCI_ERROR) {
+        lci->error = OT_OTP_FSM_STATE_ERROR;
+        ot_otp_engine_lci_write_complete(s, false);
+        return;
+    }
+
+    if (!ot_otp_engine_is_backend_writable(s)) {
+        /* OTP backend missing or read-only; reject any write request */
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: OTP backend file is missing or R/O\n", __func__,
+                      s->ot_id);
+        lci->error = OT_OTP_MACRO_ERROR;
+        LCI_CHANGE_STATE(s, OT_OTP_LCI_ERROR);
+        ot_otp_engine_lci_write_complete(s, false);
+        /* abort immediately */
+        return;
+    }
+
+    if (lci->hpos >= lcdesc->size / sizeof(uint16_t)) {
+        /* the whole LC partition has been updated */
+        if (lci->error == OT_OTP_NO_ERROR) {
+            LCI_CHANGE_STATE(s, OT_OTP_LCI_IDLE);
+            ot_otp_engine_lci_write_complete(s, true);
+        } else {
+            LCI_CHANGE_STATE(s, OT_OTP_LCI_ERROR);
+            ot_otp_engine_lci_write_complete(s, false);
+        }
+        return;
+    }
+
+    LCI_CHANGE_STATE(s, OT_OTP_LCI_WRITE);
+
+    uint16_t *lc_dst =
+        (uint16_t *)&s->otp->data[lcdesc->offset / sizeof(uint32_t)];
+
+    uint16_t cur_val = lc_dst[lci->hpos];
+    uint16_t new_val = lci->data[lci->hpos];
+
+    trace_ot_otp_lci_write(s->ot_id, lci->hpos, cur_val, new_val);
+
+    if (cur_val & ~new_val) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: cannot clear OTP bits @ %u: 0x%04x / 0x%04x\n",
+                      __func__, s->ot_id, lci->hpos, cur_val, new_val);
+        if (lci->error == OT_OTP_NO_ERROR) {
+            lci->error = OT_OTP_MACRO_WRITE_BLANK_ERROR;
+        }
+        /*
+         * "Note that if errors occur, we aggregate the error code but still
+         *  attempt to program all remaining words. This is done to ensure that
+         *  a life cycle state with ECC correctable errors in some words can
+         *  still be scrapped."
+         */
+    }
+
+    lc_dst[lci->hpos] |= new_val;
+
+    if (ot_otp_engine_is_ecc_enabled(s)) {
+        uint8_t *lc_edst =
+            (uint8_t *)&s->otp->ecc[lcdesc->offset / (2u * sizeof(uint32_t))];
+        uint8_t cur_ecc = lc_edst[lci->hpos];
+        uint8_t new_ecc = ot_otp_engine_compute_ecc_u16(lc_dst[lci->hpos]);
+
+        trace_ot_otp_lci_write_ecc(s->ot_id, lci->hpos, cur_ecc, new_ecc);
+
+        if (cur_ecc & ~new_ecc) {
+            qemu_log_mask(
+                LOG_GUEST_ERROR,
+                "%s: %s: cannot clear OTP ECC @ %u: 0x%02x / 0x%02x\n",
+                __func__, s->ot_id, lci->hpos, cur_ecc, new_ecc);
+            if (lci->error == OT_OTP_NO_ERROR) {
+                lci->error = OT_OTP_MACRO_WRITE_BLANK_ERROR;
+            }
+        }
+
+        lc_edst[lci->hpos] |= new_ecc;
+    }
+
+    lci->hpos += 1u;
+
+    unsigned update_time = s->be_chars.timings.write_ns * sizeof(uint16_t);
+    timer_mod(lci->prog_delay,
+              qemu_clock_get_ns(OT_OTP_HW_CLOCK) + update_time);
+
+    LCI_CHANGE_STATE(s, OT_OTP_LCI_WRITE_WAIT);
+}
+
+static void ot_otp_engine_pwr_otp_req(void *opaque, int n, int level)
+{
+    OtOTPEngineState *s = opaque;
+
+    g_assert(n == 0);
+
+    if (level) {
+        trace_ot_otp_pwr_otp_req(s->ot_id, "signaled");
+        qemu_bh_schedule(s->pwr_otp_bh);
+    }
+}
+
+static void ot_otp_engine_pwr_load(OtOTPEngineState *s)
+{
+    /*
+     * HEADER_FORMAT
+     *
+     *  | magic    |     4 char | "vOFTP"                                |
+     *  | hlength  |   uint32_t | count of header bytes after this point |
+     *  | version  |   uint32_t | version of the header (v2)             |
+     *  | eccbits  |   uint16_t | ECC size in bits                       |
+     *  | eccgran  |   uint16_t | ECC granule                            |
+     *  | dlength  |   uint32_t | count of data bytes (% uint64_t)       |
+     *  | elength  |   uint32_t | count of ecc bytes (% uint64_t)        |
+     *  | -------- | ---------- | only in V2                             |
+     *  | dig_iv   |  8 uint8_t | Present digest initialization vector   |
+     *  | dig_iv   | 16 uint8_t | Present digest initialization vector   |
+     */
+
+    struct otp_header {
+        char magic[4];
+        uint32_t hlength;
+        uint32_t version;
+        uint16_t eccbits;
+        uint16_t eccgran;
+        uint32_t data_len;
+        uint32_t ecc_len;
+        /* added in V2 */
+        uint8_t digest_iv[8u];
+        uint8_t digest_constant[16u];
+    };
+
+    static_assert(sizeof(struct otp_header) == 48u, "Invalid header size");
+
+    /* data following header should always be 64-bit aligned */
+    static_assert((sizeof(struct otp_header) % sizeof(uint64_t)) == 0,
+                  "invalid header definition");
+
+    size_t header_size = sizeof(struct otp_header);
+    size_t data_size = 0u;
+    size_t ecc_size = 0u;
+
+    for (unsigned part_ix = 0u; part_ix < s->part_count; part_ix++) {
+        size_t psize = (size_t)s->part_descs[part_ix].size;
+        size_t dsize = ROUND_UP(psize, sizeof(uint64_t));
+        data_size += dsize;
+        /* up to 1 ECC byte for 2 data bytes */
+        ecc_size += DIV_ROUND_UP(dsize, 2u);
+    }
+    size_t otp_size = header_size + data_size + ecc_size;
+
+    otp_size = ROUND_UP(otp_size, 4096u);
+
+    OtOTPStorage *otp = s->otp;
+
+    /* always allocates the requested size even if blk is NULL */
+    if (!otp->storage) {
+        /* only allocated once on PoR */
+        otp->storage = blk_blockalign(s->blk, otp_size);
+    }
+
+    uintptr_t base = (uintptr_t)otp->storage;
+    g_assert(!(base & (sizeof(uint64_t) - 1u)));
+
+    memset(otp->storage, 0, otp_size);
+
+    otp->data = (uint32_t *)(base + sizeof(struct otp_header));
+    otp->ecc = (uint32_t *)(base + sizeof(struct otp_header) + data_size);
+    otp->ecc_bit_count = 0u;
+    otp->ecc_granule = 0u;
+
+    if (s->blk) {
+        /* NOLINTBEGIN(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        int rc = blk_pread(s->blk, 0, (int64_t)otp_size, otp->storage,
+                           (BdrvRequestFlags)0);
+        /* NOLINTEND(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        if (rc < 0) {
+            error_setg(&error_fatal,
+                       "%s: failed to read the initial OTP content %zu bytes: "
+                       "%d",
+                       s->ot_id, otp_size, rc);
+            return;
+        }
+
+        const struct otp_header *otp_hdr = (const struct otp_header *)base;
+
+        if (memcmp(otp_hdr->magic, "vOTP", sizeof(otp_hdr->magic)) != 0) {
+            error_setg(&error_fatal, "%s: OTP file is not a valid OTP backend",
+                       s->ot_id);
+            return;
+        }
+        if (otp_hdr->version != 1u && otp_hdr->version != 2u) {
+            error_setg(&error_fatal, "%s: OTP file version %u is not supported",
+                       s->ot_id, otp_hdr->version);
+            return;
+        }
+
+        uintptr_t data_offset = otp_hdr->hlength + 8u; /* magic & length */
+        uintptr_t ecc_offset = data_offset + otp_hdr->data_len;
+
+        otp->data = (uint32_t *)(base + data_offset);
+        otp->ecc = (uint32_t *)(base + ecc_offset);
+        otp->ecc_bit_count = otp_hdr->eccbits;
+        otp->ecc_granule = otp_hdr->eccgran;
+
+        if (otp->ecc_bit_count != 6u || !ot_otp_engine_is_ecc_enabled(s)) {
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: %s: support for ECC %u/%u not implemented\n",
+                          __func__, s->ot_id, otp->ecc_granule,
+                          otp->ecc_bit_count);
+        }
+
+        bool write = blk_supports_write_perm(s->blk);
+        trace_ot_otp_load_backend(s->ot_id, otp_hdr->version,
+                                  write ? "R/W" : "R/O", otp->ecc_bit_count,
+                                  otp->ecc_granule);
+
+        if (otp_hdr->version == 2u) {
+            /*
+             * Version 2 is deprecated and digest const/IV are now ignored.
+             * Nonetheless, keep checking for inconsistencies.
+             */
+            if (s->digest_iv != ldq_le_p(otp_hdr->digest_iv)) {
+                error_report("%s: %s: OTP file digest IV mismatch", __func__,
+                             s->ot_id);
+            }
+            if (memcmp(s->digest_const, otp_hdr->digest_constant,
+                       sizeof(s->digest_const)) != 0) {
+                error_report("%s: %s: OTP file digest const mismatch", __func__,
+                             s->ot_id);
+            }
+        }
+    }
+
+    otp->data_size = data_size;
+    otp->ecc_size = ecc_size;
+    otp->size = otp_size;
+}
+static void ot_otp_engine_pwr_initialize_partitions(OtOTPEngineState *s)
+{
+    for (unsigned ix = 0; ix < s->part_count; ix++) {
+        /* sanity check: all secret partitions are also buffered */
+        g_assert(!s->part_descs[ix].secret || s->part_descs[ix].buffered);
+
+        if (ot_otp_engine_is_ecc_enabled(s) && s->part_descs[ix].integrity) {
+            if (ot_otp_engine_apply_ecc(s, ix)) {
+                continue;
+            }
+        }
+
+        if (s->part_descs[ix].sw_digest) {
+            s->part_ctrls[ix].digest = ot_otp_engine_get_part_digest(s, ix);
+            s->part_ctrls[ix].locked = s->part_ctrls[ix].digest != 0;
+            continue;
+        }
+
+        if (s->part_descs[ix].buffered) {
+            ot_otp_engine_bufferize_partition(s, ix);
+            if (s->part_descs[ix].hw_digest) {
+                ot_otp_engine_check_buffered_partition_integrity(s, ix);
+            }
+            continue;
+        }
+    }
+}
+
+static void ot_otp_engine_pwr_otp_bh(void *opaque)
+{
+    OtOTPEngineState *s = opaque;
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(s);
+
+    /*
+     * This sequence is triggered from the Power Manager, in the early boot
+     * sequence while the OT IPs are maintained in reset.
+     * This means that all ot_otp_engine_pwr_* functions are called before the
+     * OTP IP is released from reset.
+     *
+     * The QEMU reset is not a 1:1 mapping to the actual HW.
+     */
+    trace_ot_otp_pwr_otp_req(s->ot_id, "initialize");
+
+    /* load OTP data from OTP back-end file */
+    ot_otp_engine_pwr_load(s);
+    /* check ECC, digests, configure locks and bufferize partitions */
+    ot_otp_engine_pwr_initialize_partitions(s);
+
+
+    if (ic->signal_pwr_sequence) {
+        ic->signal_pwr_sequence(OT_OTP_IMPL_IF(s));
+    }
+
+    /* initialize direct access interface */
+    ot_otp_engine_dai_init(s);
+    /* initialize LC controller interface */
+    ot_otp_engine_lci_init(s);
+
+    trace_ot_otp_pwr_otp_req(s->ot_id, "done");
+
+    /* toggle OTP completion to signal the power manager OTP init is complete */
+    ibex_irq_set(&s->pwc_otp_rsp, 1);
+    ibex_irq_set(&s->pwc_otp_rsp, 0);
+}
+
+static void ot_otp_engine_configure_scrmbl_key(OtOTPEngineState *s)
+{
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(s);
+
+    if (!s->scrmbl_key_xstr) {
+        trace_ot_otp_configure_missing(s->ot_id, "scrmbl_key");
+        return;
+    }
+
+    size_t sram_key_bytes = SRAM_KEY_BYTES(ic);
+    size_t sram_nonce_bytes = SRAM_NONCE_BYTES(ic);
+    size_t len = strlen(s->scrmbl_key_xstr);
+    if (len != (size_t)(sram_key_bytes + sram_nonce_bytes) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid scrmbl_key length\n", __func__,
+                   s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(s->scrmbl_key_init->key,
+                                 &s->scrmbl_key_xstr[0], sram_key_bytes, false,
+                                 false)) {
+        error_setg(&error_fatal, "%s: %s unable to parse scrmbl_key\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(s->scrmbl_key_init->nonce,
+                                 &s->scrmbl_key_xstr[sram_key_bytes * 2u],
+                                 sram_nonce_bytes, false, true)) {
+        error_setg(&error_fatal, "%s: %s unable to parse scrmbl_key\n",
+                   __func__, s->ot_id);
+        return;
+    }
+}
+
+static void ot_otp_engine_configure_digest(OtOTPEngineState *s)
+{
+    memset(s->digest_const, 0, sizeof(s->digest_const));
+    s->digest_iv = 0ull;
+
+    if (!s->digest_const_xstr) {
+        trace_ot_otp_configure_missing(s->ot_id, "digest_const");
+        return;
+    }
+
+    if (!s->digest_iv_xstr) {
+        trace_ot_otp_configure_missing(s->ot_id, "digest_iv");
+        return;
+    }
+
+    size_t len;
+
+    len = strlen(s->digest_const_xstr);
+    if (len != sizeof(s->digest_const) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid digest_const length\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(s->digest_const, s->digest_const_xstr,
+                                 sizeof(s->digest_const), true, true)) {
+        error_setg(&error_fatal, "%s: %s unable to parse digest_const\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    uint8_t digest_iv[sizeof(uint64_t)];
+
+    len = strlen(s->digest_iv_xstr);
+    if (len != sizeof(digest_iv) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid digest_iv length\n", __func__,
+                   s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(digest_iv, s->digest_iv_xstr,
+                                 sizeof(digest_iv), true, true)) {
+        error_setg(&error_fatal, "%s: %s unable to parse digest_iv\n", __func__,
+                   s->ot_id);
+        return;
+    }
+
+    s->digest_iv = ldq_le_p(digest_iv);
+}
+
+static void ot_otp_engine_configure_flash(OtOTPEngineState *s)
+{
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(s);
+
+    if (!ic->has_flash_support) {
+        return;
+    }
+
+    memset(s->flash_data_const, 0, sizeof(s->flash_data_const));
+    memset(s->flash_addr_const, 0, sizeof(s->flash_addr_const));
+    s->flash_data_iv = 0ull;
+    s->flash_addr_iv = 0ull;
+
+    if (!s->flash_data_const_xstr) {
+        trace_ot_otp_configure_missing(s->ot_id, "flash_data_const");
+        return;
+    }
+    if (!s->flash_addr_const_xstr) {
+        trace_ot_otp_configure_missing(s->ot_id, "flash_addr_const");
+        return;
+    }
+    if (!s->flash_data_iv_xstr) {
+        trace_ot_otp_configure_missing(s->ot_id, "flash_data_iv");
+        return;
+    }
+    if (!s->flash_addr_iv_xstr) {
+        trace_ot_otp_configure_missing(s->ot_id, "flash_addr_iv");
+        return;
+    }
+
+    size_t len;
+
+    len = strlen(s->flash_data_const_xstr);
+    if (len != sizeof(s->flash_data_const) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid flash_data_const length\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(s->flash_data_const, s->flash_data_const_xstr,
+                                 sizeof(s->flash_data_const), true, true)) {
+        error_setg(&error_fatal, "%s: %s unable to parse flash_data_const\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    len = strlen(s->flash_addr_const_xstr);
+    if (len != sizeof(s->flash_addr_const) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid flash_addr_const length\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(s->flash_addr_const, s->flash_addr_const_xstr,
+                                 sizeof(s->flash_addr_const), true, true)) {
+        error_setg(&error_fatal, "%s: %s unable to parse flash_addr_const\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    uint8_t flash_data_iv[sizeof(uint64_t)];
+
+    len = strlen(s->flash_data_iv_xstr);
+    if (len != sizeof(flash_data_iv) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid flash_data_iv length\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(flash_data_iv, s->flash_data_iv_xstr,
+                                 sizeof(flash_data_iv), true, true)) {
+        error_setg(&error_fatal, "%s: %s unable to parse flash_data_iv\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    s->flash_data_iv = ldq_le_p(flash_data_iv);
+
+    uint8_t flash_addr_iv[sizeof(uint64_t)];
+
+    len = strlen(s->flash_addr_iv_xstr);
+    if (len != sizeof(flash_addr_iv) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid flash_addr_iv length\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(flash_addr_iv, s->flash_addr_iv_xstr,
+                                 sizeof(flash_addr_iv), true, true)) {
+        error_setg(&error_fatal, "%s: %s unable to parse flash_addr_iv\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    s->flash_addr_iv = ldq_le_p(flash_addr_iv);
+}
+
+static void ot_otp_engine_configure_sram(OtOTPEngineState *s)
+{
+    memset(s->sram_const, 0, sizeof(s->sram_const));
+    s->sram_iv = 0ull;
+
+    if (!s->sram_const_xstr) {
+        trace_ot_otp_configure_missing(s->ot_id, "sram_const");
+        return;
+    }
+
+    if (!s->sram_iv_xstr) {
+        trace_ot_otp_configure_missing(s->ot_id, "sram_iv");
+        return;
+    }
+
+    size_t len;
+
+    len = strlen(s->sram_const_xstr);
+    if (len != sizeof(s->sram_const) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid sram_const length\n", __func__,
+                   s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(s->sram_const, s->sram_const_xstr,
+                                 sizeof(s->sram_const), true, true)) {
+        error_setg(&error_fatal, "%s: %s unable to parse sram_const\n",
+                   __func__, s->ot_id);
+        return;
+    }
+
+    uint8_t sram_iv[sizeof(uint64_t)];
+
+    len = strlen(s->sram_iv_xstr);
+    if (len != sizeof(sram_iv) * 2u) {
+        error_setg(&error_fatal, "%s: %s invalid sram_iv length\n", __func__,
+                   s->ot_id);
+        return;
+    }
+
+    if (ot_common_parse_hexa_str(sram_iv, s->sram_iv_xstr, sizeof(sram_iv),
+                                 true, true)) {
+        error_setg(&error_fatal, "%s: %s unable to parse sram_iv\n", __func__,
+                   s->ot_id);
+        return;
+    }
+
+    s->sram_iv = ldq_le_p(sram_iv);
+}
+
+static void ot_otp_engine_configure_part_scramble_keys(OtOTPEngineState *s)
+{
+    g_assert(s->part_count);
+
+    unsigned secret_ix = 0;
+    for (unsigned part_ix = 0u; part_ix < s->part_count; part_ix++) {
+        if (!s->part_descs[part_ix].secret) {
+            continue;
+        }
+
+        /*
+         * the property exists, but QEMU only assigns a value when the property
+         * is given a value.
+         */
+        if (!s->otp_scramble_key_xstrs[secret_ix]) {
+            /* if OTP data is loaded, unscrambling keys are mandatory */
+            if (s->blk) {
+                error_setg(&error_fatal,
+                           "%s: %s Missing OTP scrambling key for part %s (%u)",
+                           __func__, s->ot_id,
+                           ot_otp_engine_part_name(s, part_ix), part_ix);
+                return;
+            }
+            secret_ix += 1u;
+            continue;
+        }
+
+        size_t len = strlen(s->otp_scramble_key_xstrs[secret_ix]);
+        if (len != OTP_SCRAMBLING_KEY_BYTES * 2u) {
+            error_setg(
+                &error_fatal,
+                "%s: %s Invalid OTP scrambling key length %zu for part %s (%u)",
+                __func__, s->ot_id, len, ot_otp_engine_part_name(s, part_ix),
+                part_ix);
+            return;
+        }
+
+        OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+        pctrl->otp_scramble_key = g_new0(uint8_t, OTP_SCRAMBLING_KEY_BYTES);
+
+        if (ot_common_parse_hexa_str(pctrl->otp_scramble_key,
+                                     s->otp_scramble_key_xstrs[secret_ix],
+                                     OTP_SCRAMBLING_KEY_BYTES, true, true)) {
+            error_setg(&error_fatal,
+                       "%s: %s unable to parse otp_scramble_keys[%u] for %s",
+                       __func__, s->ot_id, part_ix,
+                       ot_otp_engine_part_name(s, part_ix));
+            return;
+        }
+
+        TRACE_OTP("otp_scramble_keys[%s] %s",
+                  ot_otp_engine_part_name(s, part_ix),
+                  ot_otp_hexdump(s, pctrl->otp_scramble_key,
+                                 OTP_SCRAMBLING_KEY_BYTES));
+
+        secret_ix += 1u;
+    }
+}
+
+static void ot_otp_engine_add_scramble_key_props(OtOTPEngineState *s)
+{
+    g_assert(s->part_count);
+
+    unsigned secret_part_count = 0;
+    for (unsigned part_ix = 0u; part_ix < s->part_count; part_ix++) {
+        if (s->part_descs[part_ix].secret) {
+            secret_part_count++;
+        }
+    }
+
+    s->otp_scramble_key_xstrs = g_new0(char *, secret_part_count);
+    unsigned secret_ix = 0u;
+    for (unsigned part_ix = 0u; part_ix < s->part_count; part_ix++) {
+        if (!s->part_descs[part_ix].secret) {
+            continue;
+        }
+
+        Property *prop = g_new0(Property, 1u);
+
+        /*
+         * Assumes secret partitions are sequentially ordered and named
+         * SECRET0, SECRET1, SECRET2, ...
+         */
+        prop->name = g_strdup_printf("secret%u_scramble_key", secret_ix);
+        prop->info = &qdev_prop_string;
+        /*
+         * Property stores the address of the stored string as a relative offset
+         * from the parent address
+         */
+        prop->offset =
+            (intptr_t)&s->otp_scramble_key_xstrs[secret_ix] - (intptr_t)s;
+
+        object_property_add(OBJECT(s), prop->name, prop->info->type,
+                            prop->info->get, prop->info->set,
+                            prop->info->release, prop);
+
+        secret_ix++;
+    }
+}
+
+static void ot_otp_engine_configure_inv_default_parts(OtOTPEngineState *s)
+{
+    g_assert(s->part_count);
+
+    for (unsigned part_ix = 0; part_ix < s->part_count; part_ix++) {
+        if (!s->inv_default_part_xstrs[part_ix]) {
+            continue;
+        }
+
+        const OtOTPPartDesc *part = &s->part_descs[part_ix];
+
+        size_t len;
+
+        len = strlen(s->inv_default_part_xstrs[part_ix]);
+        if (len != part->size * 2u) {
+            error_setg(&error_fatal,
+                       "%s: %s invalid inv_default_part[%u] length\n", __func__,
+                       s->ot_id, part_ix);
+            return;
+        }
+
+        OtOTPPartController *pctrl = &s->part_ctrls[part_ix];
+        pctrl->inv_default_data = g_new0(uint8_t, part->size + 1u);
+        if (ot_common_parse_hexa_str(pctrl->inv_default_data,
+                                     s->inv_default_part_xstrs[part_ix],
+                                     part->size, false, true)) {
+            error_setg(&error_fatal,
+                       "%s: %s unable to parse inv_default_part[%u]\n",
+                       __func__, s->ot_id, part_ix);
+            return;
+        }
+
+        TRACE_OTP("inv_default_part[%s] %s",
+                  ot_otp_engine_part_name(s, part_ix),
+                  ot_otp_hexdump(s, pctrl->inv_default_data, part->size));
+    }
+}
+
+static void ot_otp_engine_add_inv_def_props(OtOTPEngineState *s)
+{
+    g_assert(s->part_count);
+
+    s->inv_default_part_xstrs = g_new0(char *, s->part_count);
+
+    for (unsigned part_ix = 0; part_ix < s->part_count; part_ix++) {
+        if (!s->part_descs[part_ix].buffered) {
+            continue;
+        }
+
+        Property *prop = g_new0(Property, 1u);
+
+        prop->name = g_strdup_printf("inv_default_part_%u", part_ix);
+        prop->info = &qdev_prop_string;
+        /*
+         * Property stores the address of the stored string as a relative offset
+         * from the parent address
+         */
+        prop->offset =
+            (intptr_t)&s->inv_default_part_xstrs[part_ix] - (intptr_t)s;
+
+        object_property_add(OBJECT(s), prop->name, prop->info->type,
+                            prop->info->get, prop->info->set,
+                            prop->info->release, prop);
+    }
+}
+
+static const Property ot_otp_engine_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtOTPEngineState, ot_id),
+    DEFINE_PROP_DRIVE("drive", OtOTPEngineState, blk),
+    DEFINE_PROP_LINK("backend", OtOTPEngineState, otp_backend,
+                     TYPE_OT_OTP_BE_IF, OtOtpBeIf *),
+    DEFINE_PROP_LINK("edn", OtOTPEngineState, edn, TYPE_OT_EDN, OtEDNState *),
+    DEFINE_PROP_UINT8("edn-ep", OtOTPEngineState, edn_ep, UINT8_MAX),
+    DEFINE_PROP_STRING("scrmbl_key", OtOTPEngineState, scrmbl_key_xstr),
+    DEFINE_PROP_STRING("digest_const", OtOTPEngineState, digest_const_xstr),
+    DEFINE_PROP_STRING("digest_iv", OtOTPEngineState, digest_iv_xstr),
+    DEFINE_PROP_STRING("sram_const", OtOTPEngineState, sram_const_xstr),
+    DEFINE_PROP_STRING("sram_iv", OtOTPEngineState, sram_iv_xstr),
+    DEFINE_PROP_STRING("flash_data_const", OtOTPEngineState,
+                       flash_data_const_xstr),
+    DEFINE_PROP_STRING("flash_data_iv", OtOTPEngineState, flash_data_iv_xstr),
+    DEFINE_PROP_STRING("flash_addr_const", OtOTPEngineState,
+                       flash_addr_const_xstr),
+    DEFINE_PROP_STRING("flash_addr_iv", OtOTPEngineState, flash_addr_iv_xstr),
+    DEFINE_PROP_BOOL("fatal_escalate", OtOTPEngineState, fatal_escalate, false),
+};
+
+static void ot_otp_engine_reset_enter(Object *obj, ResetType type)
+{
+    OtOTPEngineClass *c = OT_OTP_ENGINE_GET_CLASS(obj);
+    OtOTPEngineState *s = OT_OTP_ENGINE(obj);
+
+    /*
+     * Note: beware of the special reset sequence for the OTP controller,
+     * see comments from ot_otp_engine_pwr_otp_bh, as this very QEMU reset may
+     * be called after ot_otp_engine_pwr_otp_bh is invoked, hereby changing the
+     * usual realize-reset sequence.
+     *
+     * File back-end storage (loading) is processed from
+     * the ot_otp_engine_pwr_otp_bh handler, to ensure data is reloaded from the
+     * backend on each reset, prior to this very reset function. This reset
+     * function should not alter the storage content.
+     *
+     * Ideally the OTP reset functions should be decoupled from the regular
+     * IP reset, which are exercised automatically from the SoC, since all the
+     * OT SysBysDevice IPs are connected to the private system bus of the Ibex.
+     * This is by-design in QEMU. The reset management is already far too
+     * complex to create a special case for the OTP. Keep in mind that the OTP
+     * reset_enter/reset_exit functions are QEMU regular reset functions called
+     * as part of the private bus reset and do not represent the actual OTP HW
+     * reset. Part of this reset is handled in the Power Manager handler.
+     */
+    trace_ot_otp_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    qemu_bh_cancel(s->lc_broadcast.bh);
+    qemu_bh_cancel(s->pwr_otp_bh);
+
+    timer_del(s->dai->delay);
+    timer_del(s->dai->digest_write);
+    timer_del(s->lci->prog_delay);
+    timer_del(s->keygen->request_entropy);
+    s->keygen->edn_sched = false;
+
+    memset(s->hw_cfg, 0, sizeof(*s->hw_cfg));
+
+    /* ensure OTP implementation has defined all the required values */
+    g_assert(s->reg_offset.dai_base > R_ALERT_TEST);
+    g_assert(s->reg_offset.err_code_base > R_ALERT_TEST);
+    g_assert(s->reg_offset.read_lock_base > R_ALERT_TEST);
+
+    s->alert_bm = 0;
+
+    s->lc_broadcast.current_level = 0u;
+    s->lc_broadcast.level = 0u;
+    s->lc_broadcast.signal = 0u;
+
+    ot_otp_engine_update_irqs(s);
+    ot_otp_engine_update_alerts(s);
+    ibex_irq_set(&s->pwc_otp_rsp, 0);
+
+    for (unsigned part_ix = 0; part_ix < s->part_count; part_ix++) {
+        /* @todo initialize with actual default partition data once known */
+        if (s->part_descs[part_ix].buffered) {
+            s->part_ctrls[part_ix].state.b = OT_OTP_BUF_IDLE;
+        } else {
+            s->part_ctrls[part_ix].state.u = OT_OTP_UNBUF_IDLE;
+            continue;
+        }
+        unsigned part_size = ot_otp_engine_part_data_byte_size(s, part_ix);
+        memset(s->part_ctrls[part_ix].buffer.data, 0, part_size);
+        s->part_ctrls[part_ix].digest = 0;
+        if (s->part_descs[part_ix].iskeymgr_creator ||
+            s->part_descs[part_ix].iskeymgr_owner) {
+            s->part_ctrls[part_ix].read_lock = true;
+            s->part_ctrls[part_ix].write_lock = true;
+        }
+    }
+    DAI_CHANGE_STATE(s, OT_OTP_DAI_RESET);
+    LCI_CHANGE_STATE(s, OT_OTP_LCI_RESET);
+}
+
+static void ot_otp_engine_reset_exit(Object *obj, ResetType type)
+{
+    OtOTPEngineClass *c = OT_OTP_ENGINE_GET_CLASS(obj);
+    OtOTPEngineState *s = OT_OTP_ENGINE(obj);
+
+    trace_ot_otp_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    OtOtpBeIfClass *bec = OT_OTP_BE_IF_GET_CLASS(s->otp_backend);
+    memcpy(&s->be_chars, bec->get_characteristics(s->otp_backend),
+           sizeof(OtOtpBeCharacteristics));
+
+    ot_edn_connect_endpoint(s->edn, s->edn_ep,
+                            &ot_otp_engine_keygen_push_entropy, s);
+
+    int64_t now = qemu_clock_get_ns(OT_OTP_HW_CLOCK);
+    timer_mod(s->keygen->request_entropy, now + ENTROPY_RESCHEDULE_DELAY_NS);
+}
+
+static void ot_otp_engine_realize(DeviceState *dev, Error **errp)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->otp_backend);
+
+    /* ensure OTP implementation has initialized these values */
+    g_assert(s->regs != NULL);
+
+    /*
+     * Set the OTP drive's permissions now during realization. We can't leave it
+     * until reset because QEMU might have `-daemonize`d and changed directory,
+     * invalidating the filesystem path to the OTP image.
+     */
+    if (s->blk) {
+        bool write = blk_supports_write_perm(s->blk);
+        uint64_t perm = BLK_PERM_CONSISTENT_READ | (write ? BLK_PERM_WRITE : 0);
+        if (blk_set_perm(s->blk, perm, perm, &error_fatal)) {
+            warn_report("%s: %s: OTP backend is R/O", __func__, s->ot_id);
+        }
+    }
+
+    ot_otp_engine_configure_scrmbl_key(s);
+    ot_otp_engine_configure_digest(s);
+    ot_otp_engine_configure_sram(s);
+    ot_otp_engine_configure_flash(s);
+    ot_otp_engine_configure_part_scramble_keys(s);
+    ot_otp_engine_configure_inv_default_parts(s);
+}
+
+static void ot_otp_engine_init(Object *obj)
+{
+    OtOTPEngineState *s = OT_OTP_ENGINE(obj);
+
+    OtOTPImplIfClass *ic = OT_OTP_IMPL_IF_GET_CLASS(obj);
+
+    g_assert(ic->update_status_error != NULL);
+
+    g_assert(ic->part_descs != NULL);
+    g_assert(ic->part_count > 1u);
+    g_assert(ic->part_lc_num > 0u && ic->part_lc_num < ic->part_count);
+    g_assert(ic->sram_key_req_slot_count > 0u);
+
+    /*
+     * The following members are constant values, and are used very often in
+     * this implementation. Add them to the Engine instance to avoid querying
+     * them every time from the concrete class object
+     */
+    s->part_descs = ic->part_descs;
+    s->part_count = ic->part_count;
+    s->part_lc_num = ic->part_lc_num;
+
+    ibex_qdev_init_irq(obj, &s->pwc_otp_rsp, OT_PWRMGR_OTP_RSP);
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_otp_engine_pwr_otp_req,
+                            OT_PWRMGR_OTP_REQ, 1);
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->irqs); ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_otp_engine_lc_broadcast_recv,
+                            OT_LC_BROADCAST, OT_OTP_LC_BROADCAST_COUNT);
+
+    s->part_ctrls = g_new0(OtOTPPartController, s->part_count);
+    s->hw_cfg = g_new0(OtOTPHWCfg, 1u);
+    s->tokens = g_new0(OtOTPTokens, 1u);
+    s->dai = g_new0(OtOTPDAIController, 1u);
+    s->lci = g_new0(OtOTPLCIController, 1u);
+    s->keygen = g_new0(OtOTPKeyGen, 1u);
+    s->otp = g_new0(OtOTPStorage, 1u);
+    s->scrmbl_key_init = g_new0(OtOTPScrmblKeyInit, 1u);
+    s->lci->data =
+        g_new0(uint16_t, s->part_descs[s->part_lc_num].size / sizeof(uint16_t));
+
+    ot_fifo32_create(&s->keygen->entropy_buf, OTP_ENTROPY_BUF_COUNT(ic));
+    s->keygen->present = ot_present_new();
+    s->keygen->prng = ot_prng_allocate();
+
+    s->dai->delay =
+        timer_new_ns(OT_VIRTUAL_CLOCK, &ot_otp_engine_dai_complete, s);
+    s->dai->digest_write =
+        timer_new_ns(OT_VIRTUAL_CLOCK, &ot_otp_engine_dai_write_digest, s);
+    s->lci->prog_delay =
+        timer_new_ns(OT_OTP_HW_CLOCK, &ot_otp_engine_lci_write_word, s);
+    s->keygen->request_entropy =
+        timer_new_ns(OT_OTP_HW_CLOCK, &ot_otp_engine_request_entropy, s);
+    s->pwr_otp_bh = qemu_bh_new(&ot_otp_engine_pwr_otp_bh, s);
+    s->lc_broadcast.bh = qemu_bh_new(&ot_otp_engine_lc_broadcast_bh, s);
+
+    for (unsigned part_ix = 0; part_ix < s->part_count; part_ix++) {
+        if (!s->part_descs[part_ix].buffered) {
+            continue;
+        }
+        size_t part_words =
+            ot_otp_engine_part_data_byte_size(s, part_ix) / sizeof(uint32_t);
+        s->part_ctrls[part_ix].buffer.data = g_new0(uint32_t, part_words);
+    }
+
+    ot_otp_engine_add_scramble_key_props(s);
+    ot_otp_engine_add_inv_def_props(s);
+
+    int64_t now = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
+    ot_prng_reseed(s->keygen->prng, (uint32_t)now);
+
+#ifdef OT_OTP_DEBUG
+    s->hexstr = g_new0(char, OT_OTP_HEXSTR_SIZE);
+#endif
+}
+
+static void ot_otp_engine_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_otp_engine_realize;
+    device_class_set_props(dc, ot_otp_engine_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtOTPEngineClass *ec = OT_OTP_ENGINE_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_otp_engine_reset_enter, NULL,
+                                       &ot_otp_engine_reset_exit,
+                                       &ec->parent_phases);
+
+    ec->update_irqs = &ot_otp_engine_update_irqs;
+    ec->update_alerts = &ot_otp_engine_update_alerts;
+    ec->get_part_from_address = &ot_otp_engine_get_part_from_address;
+    ec->get_part_digest_reg = &ot_otp_engine_get_part_digest_reg;
+    ec->is_readable = &ot_otp_engine_is_readable;
+    ec->set_error = &ot_otp_engine_set_error;
+    ec->dai_read = &ot_otp_engine_dai_read;
+    ec->dai_write = &ot_otp_engine_dai_write;
+    ec->dai_digest = &ot_otp_engine_dai_digest;
+    ec->get_hw_cfg = &ot_otp_engine_get_hw_cfg;
+    ec->get_otp_key = &ot_otp_engine_get_otp_key;
+    ec->program_req = &ot_otp_engine_program_req;
+}
+
+static const TypeInfo ot_otp_engine_info = {
+    .name = TYPE_OT_OTP_ENGINE,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtOTPEngineState),
+    .instance_init = &ot_otp_engine_init,
+    .class_size = sizeof(OtOTPEngineClass),
+    .class_init = &ot_otp_engine_class_init,
+    .abstract = true,
+};
+
+static void ot_otp_engine_register_types(void)
+{
+    type_register_static(&ot_otp_engine_info);
+}
+
+type_init(ot_otp_engine_register_types);
diff --git a/hw/opentitan/ot_otp_if.c b/hw/opentitan/ot_otp_if.c
new file mode 100644
index 0000000000000..ccafdab71c69c
--- /dev/null
+++ b/hw/opentitan/ot_otp_if.c
@@ -0,0 +1,42 @@
+/*
+ * QEMU OpenTitan One Time Programmable (OTP) memory controller public interface
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/opentitan/ot_otp_if.h"
+
+static const TypeInfo ot_otp_if_info = {
+    .name = TYPE_OT_OTP_IF,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(OtOTPIfClass),
+};
+
+static void ot_otp_if_register_types(void)
+{
+    type_register_static(&ot_otp_if_info);
+}
+
+type_init(ot_otp_if_register_types);
diff --git a/hw/opentitan/ot_otp_impl_if.c b/hw/opentitan/ot_otp_impl_if.c
new file mode 100644
index 0000000000000..e9687a38d4122
--- /dev/null
+++ b/hw/opentitan/ot_otp_impl_if.c
@@ -0,0 +1,43 @@
+/*
+ * QEMU OpenTitan One Time Programmable (OTP) implementer interface.
+ * An OTP device should implement this API used by the OTP engine.
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/opentitan/ot_otp_impl_if.h"
+
+static const TypeInfo ot_otp_impl_if_info = {
+    .name = TYPE_OT_OTP_IMPL_IF,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(OtOTPImplIfClass),
+};
+
+static void ot_otp_impl_if_register_types(void)
+{
+    type_register_static(&ot_otp_impl_if_info);
+}
+
+type_init(ot_otp_impl_if_register_types);
diff --git a/hw/opentitan/ot_otp_ot_be.c b/hw/opentitan/ot_otp_ot_be.c
new file mode 100644
index 0000000000000..3940d363b8ebe
--- /dev/null
+++ b/hw/opentitan/ot_otp_ot_be.c
@@ -0,0 +1,300 @@
+/*
+ * QEMU OpenTitan OTP backend
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Constants are based on what can be extracted from
+ *    https://github.com/lowRISC/opentitan-integrated/commit/eaf699f001
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_otp_be_if.h"
+#include "hw/opentitan/ot_otp_if.h"
+#include "hw/opentitan/ot_otp_ot_be.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(CSR0, 0x0u)
+    FIELD(CSR0, FIELD0, 0u, 1u)
+    FIELD(CSR0, FIELD1, 1u, 1u)
+    FIELD(CSR0, FIELD2, 2u, 1u)
+    FIELD(CSR0, FIELD3, 4u, 10u)
+    FIELD(CSR0, FIELD4, 16u, 11u)
+REG32(CSR1, 0x4u)
+    FIELD(CSR1, FIELD0, 0u, 7u)
+    FIELD(CSR1, FIELD1, 7u, 1u)
+    FIELD(CSR1, FIELD2, 8u, 7u)
+    FIELD(CSR1, FIELD3, 15u, 1u)
+    FIELD(CSR1, FIELD4, 16u, 16u)
+REG32(CSR2, 0x8u)
+    FIELD(CSR2, FIELD0, 0u, 1u)
+REG32(CSR3, 0xcu)
+    FIELD(CSR3, FIELD0, 0u, 3u)
+    FIELD(CSR3, FIELD1, 4u, 10u)
+    FIELD(CSR3, FIELD2, 16u, 1u)
+    FIELD(CSR3, FIELD3, 17u, 1u)
+    FIELD(CSR3, FIELD4, 18u, 1u)
+    FIELD(CSR3, FIELD5, 19u, 1u)
+    FIELD(CSR3, FIELD6, 20u, 1u)
+    FIELD(CSR3, FIELD7, 21u, 1u)
+    FIELD(CSR3, FIELD8, 22u, 1u)
+REG32(CSR4, 0x10u)
+    FIELD(CSR4, FIELD0, 0u, 10u)
+    FIELD(CSR4, FIELD1, 12u, 1u)
+    FIELD(CSR4, FIELD2, 13u, 1u)
+    FIELD(CSR4, FIELD3, 14u, 1u)
+REG32(CSR5, 0x14u)
+    FIELD(CSR5, FIELD0, 0u, 6u)
+    FIELD(CSR5, FIELD1, 6u, 2u)
+    FIELD(CSR5, FIELD2, 8u, 1u)
+    FIELD(CSR5, FIELD3, 9u, 3u)
+    FIELD(CSR5, FIELD4, 12u, 1u)
+    FIELD(CSR5, FIELD5, 13u, 1u)
+    FIELD(CSR5, FIELD6, 16u, 16u)
+REG32(CSR6, 0x18u)
+    FIELD(CSR6, FIELD0, 0u, 10u)
+    FIELD(CSR6, FIELD1, 11u, 1u)
+    FIELD(CSR6, FIELD2, 12u, 1u)
+    FIELD(CSR6, FIELD3, 16u, 16u)
+REG32(CSR7, 0x1cu)
+    FIELD(CSR7, FIELD0, 0u, 6u)
+    FIELD(CSR7, FIELD1, 8u, 3u)
+    FIELD(CSR7, FIELD2, 14u, 1u)
+    FIELD(CSR7, FIELD3, 15u, 1u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_CSR7)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+
+/* clang-format off */
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char REG_NAMES[REGS_COUNT][6u] = {
+    REG_NAME_ENTRY(CSR0),
+    REG_NAME_ENTRY(CSR1),
+    REG_NAME_ENTRY(CSR2),
+    REG_NAME_ENTRY(CSR3),
+    REG_NAME_ENTRY(CSR4),
+    REG_NAME_ENTRY(CSR5),
+    REG_NAME_ENTRY(CSR6),
+    REG_NAME_ENTRY(CSR7),
+};
+#undef REG_NAME_ENTRY
+/* clang-format on */
+
+struct OtOtpOtBeState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion prim_mr;
+
+    uint32_t regs[REGS_COUNT];
+    OtOtpBeCharacteristics characteristics;
+
+    char *ot_id;
+    DeviceState *parent;
+};
+
+struct OtOtpOtBeClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static const OtOtpBeCharacteristics OTP_BE_CHARACTERISTICS = {
+    .timings = {
+        .read_ns = 5000u /* 5 us */,
+        .write_ns = 50000u /* 50 us */,
+    },
+};
+
+static uint64_t ot_otp_ot_be_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtOtpOtBeState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_CSR0:
+    case R_CSR1:
+    case R_CSR2:
+    case R_CSR3:
+    case R_CSR4:
+    case R_CSR5:
+    case R_CSR6:
+    case R_CSR7:
+        /* TODO: not yet implemented */
+        val32 = s->regs[reg];
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_otp_ot_be_read_out((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_otp_ot_be_write(void *opaque, hwaddr addr, uint64_t value,
+                               unsigned size)
+{
+    OtOtpOtBeState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)value;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_otp_ot_be_write((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_CSR0:
+    case R_CSR1:
+    case R_CSR2:
+    case R_CSR3:
+    case R_CSR4:
+    case R_CSR5:
+    case R_CSR6:
+        /* TODO: not yet implemented */
+        s->regs[reg] = val32;
+        break;
+    case R_CSR7:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x02%x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+}
+
+static bool ot_otp_ot_be_is_ecc_enabled(OtOtpBeIf *beif)
+{
+    (void)beif;
+
+    return true;
+}
+
+static const OtOtpBeCharacteristics *
+ot_otp_ot_be_get_characteristics(OtOtpBeIf *beif)
+{
+    OtOtpOtBeState *s = OT_OTP_OT_BE(beif);
+
+    return &s->characteristics;
+}
+
+static const Property ot_otp_ot_be_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtOtpOtBeState, ot_id),
+    DEFINE_PROP_LINK("parent", OtOtpOtBeState, parent, TYPE_DEVICE,
+                     DeviceState *),
+    DEFINE_PROP_UINT32("write_ns", OtOtpOtBeState,
+                       characteristics.timings.write_ns,
+                       OTP_BE_CHARACTERISTICS.timings.write_ns),
+    DEFINE_PROP_UINT32("read_ns", OtOtpOtBeState,
+                       characteristics.timings.read_ns,
+                       OTP_BE_CHARACTERISTICS.timings.read_ns),
+};
+
+static const MemoryRegionOps ot_otp_ot_be_ops = {
+    .read = &ot_otp_ot_be_read,
+    .write = &ot_otp_ot_be_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static void ot_otp_ot_be_reset_enter(Object *obj, ResetType type)
+{
+    OtOtpOtBeClass *c = OT_OTP_OT_BE_GET_CLASS(obj);
+    OtOtpOtBeState *s = OT_OTP_OT_BE(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void ot_otp_ot_be_init(Object *obj)
+{
+    OtOtpOtBeState *s = OT_OTP_OT_BE(obj);
+
+    memory_region_init_io(&s->prim_mr, obj, &ot_otp_ot_be_ops, s,
+                          TYPE_OT_OTP_OT_BE, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->prim_mr);
+}
+
+static void ot_otp_ot_be_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    device_class_set_props(dc, ot_otp_ot_be_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtOtpOtBeClass *oc = OT_OTP_OT_BE_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_otp_ot_be_reset_enter, NULL,
+                                       NULL, &oc->parent_phases);
+
+    OtOtpBeIfClass *bec = OT_OTP_BE_IF_CLASS(klass);
+    bec->is_ecc_enabled = &ot_otp_ot_be_is_ecc_enabled;
+    bec->get_characteristics = &ot_otp_ot_be_get_characteristics;
+}
+
+static const TypeInfo ot_otp_ot_be_init_info = {
+    .name = TYPE_OT_OTP_OT_BE,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtOtpOtBeState),
+    .instance_init = &ot_otp_ot_be_init,
+    .class_size = sizeof(OtOtpOtBeClass),
+    .class_init = &ot_otp_ot_be_class_init,
+    .interfaces =
+        (InterfaceInfo[]){
+            { TYPE_OT_OTP_BE_IF },
+            {},
+        },
+};
+
+static void ot_otp_ot_be_init_register_types(void)
+{
+    type_register_static(&ot_otp_ot_be_init_info);
+}
+
+type_init(ot_otp_ot_be_init_register_types);
diff --git a/hw/opentitan/ot_pinmux_dj.c b/hw/opentitan/ot_pinmux_dj.c
new file mode 100644
index 0000000000000..9d2affcc791a8
--- /dev/null
+++ b/hw/opentitan/ot_pinmux_dj.c
@@ -0,0 +1,577 @@
+/*
+ * QEMU OpenTitan Darjeeling PinMux device
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "qom/object.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_pinmux_dj.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+#define PARAM_N_MIO_PERIPH_IN  4u
+#define PARAM_N_MIO_PERIPH_OUT 5u
+#define PARAM_N_MIO_PADS       12u
+#define PARAM_N_DIO_PADS       73u
+#define PARAM_N_WKUP_DETECT    8u
+#define PARAM_NUM_ALERTS       1u
+#undef BIT_PACKED_STATUS_REG
+
+#define REG_SIZE(_n_) ((_n_) * sizeof(uint32_t))
+
+#ifdef BIT_PACKED_STATUS_REG
+#define MIO_SLEEP_STATUS_COUNT    DIV_ROUND_UP(PARAM_N_MIO_PADS, 32u)
+#define DIO_SLEEP_STATUS_COUNT    DIV_ROUND_UP(PARAM_N_DIO_PADS, 32u)
+#define MIO_PAD_SLEEP_STATUS_REM  (PARAM_N_MIO_PADS & 31u)
+#define DIO_PAD_SLEEP_STATUS_REM  (PARAM_N_DIO_PADS & 31u)
+#define DIO_PAD_SLEEP_STATUS_MASK UINT32_MAX
+#define MIO_PAD_SLEEP_STATUS_MASK UINT32_MAX
+#else
+#define MIO_SLEEP_STATUS_COUNT    PARAM_N_MIO_PADS
+#define DIO_SLEEP_STATUS_COUNT    PARAM_N_DIO_PADS
+#define MIO_PAD_SLEEP_STATUS_REM  0
+#define DIO_PAD_SLEEP_STATUS_REM  0
+#define DIO_PAD_SLEEP_STATUS_MASK 1u
+#define MIO_PAD_SLEEP_STATUS_MASK 1u
+#endif
+#define N_MAX_PADS MAX(PARAM_N_MIO_PADS, PARAM_N_DIO_PADS)
+
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x0u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(MIO_PERIPH_INSEL_REGWEN, A_ALERT_TEST + REG_SIZE(1u))
+    FIELD(MIO_PERIPH_INSEL_REGWEN, EN, 0u, 1u)
+REG32(MIO_PERIPH_INSEL,
+      A_MIO_PERIPH_INSEL_REGWEN + REG_SIZE(PARAM_N_MIO_PERIPH_IN))
+REG32(MIO_OUTSEL_REGWEN,
+      A_MIO_PERIPH_INSEL + REG_SIZE(PARAM_N_MIO_PERIPH_IN))
+    FIELD(MIO_OUTSEL_REGWEN, EN, 0u, 1u)
+REG32(MIO_OUTSEL,
+      A_MIO_OUTSEL_REGWEN + REG_SIZE(PARAM_N_MIO_PADS))
+REG32(MIO_PAD_ATTR_REGWEN,
+      A_MIO_OUTSEL + REG_SIZE(PARAM_N_MIO_PADS))
+    FIELD(MIO_PAD_ATTR_REGWEN, EN, 0u, 1u)
+REG32(MIO_PAD_ATTR,
+      A_MIO_PAD_ATTR_REGWEN + REG_SIZE(PARAM_N_MIO_PADS))
+REG32(DIO_PAD_ATTR_REGWEN,
+      A_MIO_PAD_ATTR + REG_SIZE(PARAM_N_MIO_PADS))
+    FIELD(DIO_PAD_ATTR_REGWEN, EN, 0u, 1u)
+REG32(DIO_PAD_ATTR,
+      A_DIO_PAD_ATTR_REGWEN + REG_SIZE(PARAM_N_DIO_PADS))
+REG32(MIO_PAD_SLEEP_STATUS,
+      A_DIO_PAD_ATTR + REG_SIZE(PARAM_N_DIO_PADS))
+REG32(MIO_PAD_SLEEP_REGWEN,
+      A_MIO_PAD_SLEEP_STATUS + REG_SIZE(MIO_SLEEP_STATUS_COUNT))
+    FIELD(MIO_PAD_SLEEP_REGWEN, EN, 0u, 1u)
+REG32(MIO_PAD_SLEEP,
+      A_MIO_PAD_SLEEP_REGWEN + REG_SIZE(PARAM_N_MIO_PADS))
+    FIELD(MIO_PAD_SLEEP, EN, 0u, 1u)
+REG32(MIO_PAD_SLEEP_MODE,
+      A_MIO_PAD_SLEEP + REG_SIZE(PARAM_N_MIO_PADS))
+    FIELD(MIO_PAD_SLEEP_MODE, OUT, 0u, 2u)
+REG32(DIO_PAD_SLEEP_STATUS,
+      A_MIO_PAD_SLEEP_MODE + REG_SIZE(PARAM_N_MIO_PADS))
+REG32(DIO_PAD_SLEEP_REGWEN,
+      A_DIO_PAD_SLEEP_STATUS + REG_SIZE(DIO_SLEEP_STATUS_COUNT))
+    FIELD(DIO_PAD_SLEEP_REGWEN, EN, 0u, 1u)
+REG32(DIO_PAD_SLEEP,
+      A_DIO_PAD_SLEEP_REGWEN + REG_SIZE(PARAM_N_DIO_PADS))
+    FIELD(DIO_PAD_SLEEP, EN, 0u, 1u)
+REG32(DIO_PAD_SLEEP_MODE,
+      A_DIO_PAD_SLEEP + REG_SIZE(PARAM_N_DIO_PADS))
+    FIELD(DIO_PAD_SLEEP_MODE, OUT, 0u, 2u)
+REG32(WKUP_DETECTOR_REGWEN,
+     A_DIO_PAD_SLEEP_MODE + REG_SIZE(PARAM_N_DIO_PADS))
+    FIELD(WKUP_DETECTOR_REGWEN, EN, 0u, 1u)
+REG32(WKUP_DETECTOR,
+      A_WKUP_DETECTOR_REGWEN + REG_SIZE(PARAM_N_WKUP_DETECT))
+    FIELD(WKUP_DETECTOR, EN, 0u, 1u)
+REG32(WKUP_DETECTOR_CFG,
+      A_WKUP_DETECTOR + REG_SIZE(PARAM_N_WKUP_DETECT))
+    FIELD(WKUP_DETECTOR_CFG, MODE, 0u, 3u)
+    FIELD(WKUP_DETECTOR_CFG, FILTER, 3u, 1u)
+    FIELD(WKUP_DETECTOR_CFG, MIODIO, 4u, 1u)
+REG32(WKUP_DETECTOR_CNT_TH,
+      A_WKUP_DETECTOR_CFG + REG_SIZE(PARAM_N_WKUP_DETECT))
+    FIELD(WKUP_DETECTOR_CNT_TH, TH, 0u, 8u)
+REG32(WKUP_DETECTOR_PADSEL,
+      A_WKUP_DETECTOR_CNT_TH + REG_SIZE(PARAM_N_WKUP_DETECT))
+REG32(WKUP_CAUSE,
+      A_WKUP_DETECTOR_PADSEL + REG_SIZE(PARAM_N_WKUP_DETECT))
+/* clang-format on */
+
+#define MIO_PAD_ATTR_MASK               OT_PINMUX_PAD_ATTR_MASK
+#define DIO_PAD_ATTR_MASK               OT_PINMUX_PAD_ATTR_MASK
+#define MIO_PAD_SLEEP_MODE_OUT_TIE_LOW  0x0u
+#define MIO_PAD_SLEEP_MODE_OUT_TIE_HIGH 0x1u
+#define MIO_PAD_SLEEP_MODE_OUT_HIGH_Z   0x2u
+#define MIO_PAD_SLEEP_MODE_OUT_KEEP     0x3u
+#define DIO_PAD_SLEEP_MODE_OUT_TIE_LOW  0x0u
+#define DIO_PAD_SLEEP_MODE_OUT_TIE_HIGH 0x1u
+#define DIO_PAD_SLEEP_MODE_OUT_HIGH_Z   0x2u
+#define DIO_PAD_SLEEP_MODE_OUT_KEEP     0x3u
+#define WKUP_DETECTOR_MODE_POSEDGE      0x0u
+#define WKUP_DETECTOR_MODE_NEGEDGE      0x1u
+#define WKUP_DETECTOR_MODE_EDGE         0x2u
+#define WKUP_DETECTOR_MODE_TIMEDHIGH    0x3u
+#define WKUP_DETECTOR_MODE_TIMEDLOW     0x4u
+#define WKUP_CAUSE_MASK                 ((1u << PARAM_N_WKUP_DETECT) - 1u)
+#define WKUP_DETECTOR_CFG_MASK \
+    (R_WKUP_DETECTOR_CFG_MODE_MASK | R_WKUP_DETECTOR_CFG_FILTER_MASK | \
+     R_WKUP_DETECTOR_CFG_MIODIO_MASK)
+
+#define R32_OFF(_r_)             ((_r_) / sizeof(uint32_t))
+#define R_LAST_REG               (R_WKUP_CAUSE)
+#define REGS_COUNT               (R_LAST_REG + 1u)
+#define REGS_SIZE                (REGS_COUNT * sizeof(uint32_t))
+#define CASE_SCALAR(_reg_)       R_##_reg_
+#define CASE_RANGE(_reg_, _rpt_) R_##_reg_...(R_##_reg_ + (_rpt_) - (1u))
+#define PAD_ATTR_TO_IRQ(_pad_)   ((int)((_pad_) & INT32_MAX))
+#define PAD_ATTR_ENABLE(_en_)    (((unsigned)!(_en_)) << 31u)
+
+static_assert((OT_PINMUX_PAD_ATTR_MASK | OT_PINMUX_PAD_ATTR_FORCE_MODE_MASK) <
+                  (1u << 31u),
+              "Cannot encode PAD attr as IRQ");
+
+typedef struct {
+    uint32_t alert_test;
+    uint32_t mio_periph_insel_regwen[PARAM_N_MIO_PERIPH_IN];
+    uint32_t mio_periph_insel[PARAM_N_MIO_PERIPH_IN];
+    uint32_t mio_outsel_regwen[PARAM_N_MIO_PADS];
+    uint32_t mio_outsel[PARAM_N_MIO_PADS];
+    uint32_t mio_pad_attr_regwen[PARAM_N_MIO_PADS];
+    uint32_t mio_pad_attr[PARAM_N_MIO_PADS];
+    uint32_t dio_pad_attr_regwen[PARAM_N_DIO_PADS];
+    uint32_t dio_pad_attr[PARAM_N_DIO_PADS];
+    uint32_t mio_pad_sleep_status[MIO_SLEEP_STATUS_COUNT];
+    uint32_t mio_pad_sleep_regwen[PARAM_N_MIO_PADS];
+    uint32_t mio_pad_sleep[PARAM_N_MIO_PADS];
+    uint32_t mio_pad_sleep_mode[PARAM_N_MIO_PADS];
+    uint32_t dio_pad_sleep_status[DIO_SLEEP_STATUS_COUNT];
+    uint32_t dio_pad_sleep_regwen[PARAM_N_DIO_PADS];
+    uint32_t dio_pad_sleep[PARAM_N_DIO_PADS];
+    uint32_t dio_pad_sleep_mode[PARAM_N_DIO_PADS];
+    uint32_t wkup_detector_regwen[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_detector[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_detector_cfg[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_detector_cnt_th[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_detector_padsel[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_cause;
+} OtPinmuxDjStateRegs;
+
+struct OtPinmuxDjState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ alert;
+    IbexIRQ *dios;
+    IbexIRQ *mios;
+
+    OtPinmuxDjStateRegs *regs;
+};
+
+struct OtPinmuxDjClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static uint32_t ot_pinmux_dj_sel_mask(unsigned val)
+{
+    return (1u << (32 - clz32(val))) - 1u;
+}
+
+static uint64_t ot_pinmux_dj_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtPinmuxDjState *s = opaque;
+    (void)size;
+    uint32_t val32;
+    hwaddr reg = R32_OFF(addr);
+    OtPinmuxDjStateRegs *regs = s->regs;
+
+    switch (reg) {
+    case CASE_RANGE(MIO_PERIPH_INSEL_REGWEN, PARAM_N_MIO_PERIPH_IN):
+        val32 = regs->mio_periph_insel_regwen[reg - R_MIO_PERIPH_INSEL_REGWEN];
+        break;
+    case CASE_RANGE(MIO_PERIPH_INSEL, PARAM_N_MIO_PERIPH_IN):
+        val32 = regs->mio_periph_insel[reg - R_MIO_PERIPH_INSEL];
+        break;
+    case CASE_RANGE(MIO_OUTSEL_REGWEN, PARAM_N_MIO_PADS):
+        val32 = regs->mio_outsel_regwen[reg - R_MIO_OUTSEL_REGWEN];
+        break;
+    case CASE_RANGE(MIO_OUTSEL, PARAM_N_MIO_PADS):
+        val32 = regs->mio_outsel[reg - R_MIO_OUTSEL];
+        break;
+    case CASE_RANGE(MIO_PAD_ATTR_REGWEN, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_attr_regwen[reg - R_MIO_PAD_ATTR_REGWEN];
+        break;
+    case CASE_RANGE(MIO_PAD_ATTR, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_attr[reg - R_MIO_PAD_ATTR];
+        break;
+    case CASE_RANGE(DIO_PAD_ATTR_REGWEN, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_attr_regwen[reg - R_DIO_PAD_ATTR_REGWEN];
+        break;
+    case CASE_RANGE(DIO_PAD_ATTR, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_attr[reg - R_DIO_PAD_ATTR];
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_STATUS, MIO_SLEEP_STATUS_COUNT):
+        val32 = regs->mio_pad_sleep_status[reg - R_MIO_PAD_SLEEP_STATUS];
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_REGWEN, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_sleep_regwen[reg - R_MIO_PAD_SLEEP_REGWEN];
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_sleep[reg - R_MIO_PAD_SLEEP];
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_MODE, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_sleep_mode[reg - R_MIO_PAD_SLEEP_MODE];
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_STATUS, DIO_SLEEP_STATUS_COUNT):
+        val32 = regs->dio_pad_sleep_status[reg - R_DIO_PAD_SLEEP_STATUS];
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_REGWEN, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_sleep_regwen[reg - R_DIO_PAD_SLEEP_REGWEN];
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_sleep[reg - R_DIO_PAD_SLEEP];
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_MODE, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_sleep_mode[reg - R_DIO_PAD_SLEEP_MODE];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_REGWEN, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector_regwen[reg - R_WKUP_DETECTOR_REGWEN];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector[reg - R_WKUP_DETECTOR];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_CFG, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector_cfg[reg - R_WKUP_DETECTOR_CFG];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_CNT_TH, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector_cnt_th[reg - R_WKUP_DETECTOR_CNT_TH];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_PADSEL, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector_padsel[reg - R_WKUP_DETECTOR_PADSEL];
+        break;
+    case CASE_SCALAR(WKUP_CAUSE):
+        val32 = regs->wkup_cause;
+        break;
+    case CASE_SCALAR(ALERT_TEST):
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_pinmux_io_read_out((uint32_t)addr, val32, pc);
+
+    return (uint64_t)val32;
+};
+
+#define OT_PINMUX_DJ_IS_REGWEN(_off_, _ren_, _rw_) \
+    ((regs->_ren_##_regwen[(_off_) - (R_##_rw_)]) & 0x1u)
+
+static void ot_pinmux_dj_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                    unsigned size)
+{
+    OtPinmuxDjState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+    hwaddr reg = R32_OFF(addr);
+    OtPinmuxDjStateRegs *regs = s->regs;
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_pinmux_io_write((uint32_t)addr, val32, pc);
+
+    switch (reg) {
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        regs->alert_test = val32;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    case CASE_RANGE(MIO_PERIPH_INSEL_REGWEN, PARAM_N_MIO_PERIPH_IN):
+        val32 &= R_MIO_PERIPH_INSEL_REGWEN_EN_MASK;
+        regs->mio_periph_insel_regwen[reg - R_MIO_PERIPH_INSEL_REGWEN] = val32;
+        break;
+    case CASE_RANGE(MIO_PERIPH_INSEL, PARAM_N_MIO_PERIPH_IN):
+        if (OT_PINMUX_DJ_IS_REGWEN(reg, mio_periph_insel, MIO_PERIPH_INSEL)) {
+            if (val32 >= PARAM_N_MIO_PERIPH_IN + 2u) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
+                              __func__, (unsigned)reg, val32);
+                uint32_t mask =
+                    ot_pinmux_dj_sel_mask(PARAM_N_MIO_PERIPH_IN + 2u);
+                val32 &= mask;
+            }
+            regs->mio_periph_insel[reg - R_MIO_PERIPH_INSEL] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(MIO_OUTSEL_REGWEN, PARAM_N_MIO_PADS):
+        val32 &= R_MIO_OUTSEL_REGWEN_EN_MASK;
+        regs->mio_outsel_regwen[reg - R_MIO_OUTSEL_REGWEN] = val32;
+        break;
+    case CASE_RANGE(MIO_OUTSEL, PARAM_N_MIO_PADS):
+        if (OT_PINMUX_DJ_IS_REGWEN(reg, mio_outsel, MIO_OUTSEL)) {
+            if (val32 >= PARAM_N_MIO_PERIPH_OUT + 2u) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
+                              __func__, (unsigned)reg, val32);
+                uint32_t mask =
+                    ot_pinmux_dj_sel_mask(PARAM_N_MIO_PERIPH_OUT + 2u);
+                val32 &= mask;
+            }
+            regs->mio_outsel[reg - R_MIO_OUTSEL] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(MIO_PAD_ATTR_REGWEN, PARAM_N_MIO_PADS):
+        val32 &= R_MIO_PAD_ATTR_REGWEN_EN_MASK;
+        regs->mio_pad_attr_regwen[reg - R_MIO_PAD_ATTR_REGWEN] = val32;
+        break;
+    case CASE_RANGE(MIO_PAD_ATTR, PARAM_N_MIO_PADS):
+        if (OT_PINMUX_DJ_IS_REGWEN(reg, mio_pad_attr, MIO_PAD_ATTR)) {
+            val32 &= MIO_PAD_ATTR_MASK;
+            unsigned pad_no = reg - R_MIO_PAD_ATTR;
+            g_assert(pad_no < R_MIO_PAD_ATTR);
+            regs->mio_pad_attr[pad_no] = val32;
+            ibex_irq_set(&s->mios[pad_no], PAD_ATTR_TO_IRQ(val32));
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(DIO_PAD_ATTR_REGWEN, PARAM_N_DIO_PADS):
+        val32 &= R_DIO_PAD_ATTR_REGWEN_EN_MASK;
+        regs->dio_pad_attr_regwen[reg - R_DIO_PAD_ATTR_REGWEN] = val32;
+        break;
+    case CASE_RANGE(DIO_PAD_ATTR, PARAM_N_DIO_PADS):
+        if (OT_PINMUX_DJ_IS_REGWEN(reg, dio_pad_attr, DIO_PAD_ATTR)) {
+            val32 &= DIO_PAD_ATTR_MASK;
+            unsigned pad_no = reg - R_DIO_PAD_ATTR;
+            g_assert(pad_no < PARAM_N_DIO_PADS);
+            regs->dio_pad_attr[pad_no] = val32;
+            ibex_irq_set(&s->dios[pad_no], PAD_ATTR_TO_IRQ(val32));
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_STATUS, MIO_SLEEP_STATUS_COUNT):
+        val32 &= MIO_PAD_SLEEP_STATUS_MASK;
+#if defined(BIT_PACKED_STATUS_REG) && (MIO_PAD_SLEEP_STATUS_REM != 0)
+        if (reg == R_MIO_PAD_SLEEP_STATUS + MIO_SLEEP_STATUS_COUNT - 1u) {
+            val32 &= (1u << MIO_PAD_SLEEP_STATUS_REM) - 1u;
+        }
+#endif
+        regs->mio_pad_sleep_status[reg - R_MIO_PAD_SLEEP_STATUS] = val32;
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_REGWEN, PARAM_N_MIO_PADS):
+        val32 &= R_MIO_PAD_SLEEP_REGWEN_EN_MASK;
+        regs->mio_pad_sleep_regwen[reg - R_MIO_PAD_SLEEP_REGWEN] = val32;
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP, PARAM_N_MIO_PADS):
+        if (OT_PINMUX_DJ_IS_REGWEN(reg, mio_pad_sleep, MIO_PAD_SLEEP)) {
+            val32 &= R_MIO_PAD_SLEEP_EN_MASK;
+            regs->mio_pad_sleep[reg - R_MIO_PAD_SLEEP] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_MODE, PARAM_N_MIO_PADS):
+        val32 &= R_MIO_PAD_SLEEP_MODE_OUT_MASK;
+        regs->mio_pad_sleep_mode[reg - R_MIO_PAD_SLEEP_MODE] = val32;
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_STATUS, DIO_SLEEP_STATUS_COUNT):
+        val32 &= DIO_PAD_SLEEP_STATUS_MASK;
+#if defined(BIT_PACKED_STATUS_REG) && (DIO_PAD_SLEEP_STATUS_REM != 0)
+        if (reg == R_DIO_PAD_SLEEP_STATUS + DIO_SLEEP_STATUS_COUNT - 1u) {
+            val32 &= (1u << DIO_PAD_SLEEP_STATUS_REM) - 1u;
+        }
+#endif
+        regs->dio_pad_sleep_status[reg - R_DIO_PAD_SLEEP_STATUS] = val32;
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_REGWEN, PARAM_N_DIO_PADS):
+        val32 &= R_DIO_PAD_SLEEP_REGWEN_EN_MASK;
+        regs->dio_pad_sleep_regwen[reg - R_DIO_PAD_SLEEP_REGWEN] = val32;
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP, PARAM_N_DIO_PADS):
+        if (OT_PINMUX_DJ_IS_REGWEN(reg, dio_pad_sleep, DIO_PAD_SLEEP)) {
+            val32 &= R_DIO_PAD_SLEEP_EN_MASK;
+            regs->dio_pad_sleep[reg - R_DIO_PAD_SLEEP] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_MODE, PARAM_N_DIO_PADS):
+        val32 &= R_DIO_PAD_SLEEP_MODE_OUT_MASK;
+        regs->dio_pad_sleep_mode[reg - R_DIO_PAD_SLEEP_MODE] = val32;
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_REGWEN, PARAM_N_WKUP_DETECT):
+        val32 &= R_WKUP_DETECTOR_REGWEN_EN_MASK;
+        regs->wkup_detector_regwen[reg - R_WKUP_DETECTOR_REGWEN] = val32;
+        break;
+    case CASE_RANGE(WKUP_DETECTOR, PARAM_N_WKUP_DETECT):
+        if (OT_PINMUX_DJ_IS_REGWEN(reg, wkup_detector, WKUP_DETECTOR)) {
+            val32 &= R_WKUP_DETECTOR_EN_MASK;
+            regs->wkup_detector[reg - R_WKUP_DETECTOR] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_CFG, PARAM_N_WKUP_DETECT):
+        val32 &= WKUP_DETECTOR_CFG_MASK;
+        regs->wkup_detector[reg - R_WKUP_DETECTOR_CFG] = val32;
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_CNT_TH, PARAM_N_WKUP_DETECT):
+        val32 &= R_WKUP_DETECTOR_CNT_TH_TH_MASK;
+        regs->wkup_detector_cnt_th[reg - R_WKUP_DETECTOR_CNT_TH] = val32;
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_PADSEL, PARAM_N_WKUP_DETECT):
+        if (val32 >= N_MAX_PADS) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
+                          __func__, (unsigned)reg, val32);
+            uint32_t mask = ot_pinmux_dj_sel_mask(N_MAX_PADS);
+            val32 &= mask;
+        }
+        regs->wkup_detector_padsel[reg - R_WKUP_DETECTOR_PADSEL] = val32;
+        break;
+    case CASE_SCALAR(WKUP_CAUSE):
+        val32 %= WKUP_CAUSE_MASK;
+        regs->wkup_cause = val32;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+};
+
+static const MemoryRegionOps ot_pinmux_dj_regs_ops = {
+    .read = &ot_pinmux_dj_regs_read,
+    .write = &ot_pinmux_dj_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_pinmux_dj_reset_enter(Object *obj, ResetType type)
+{
+    OtPinmuxDjClass *c = OT_PINMUX_DJ_GET_CLASS(obj);
+    OtPinmuxDjState *s = OT_PINMUX_DJ(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+    OtPinmuxDjStateRegs *regs = s->regs;
+    memset(regs, 0, sizeof(*regs));
+
+    for (unsigned ix = 0; ix < PARAM_N_MIO_PERIPH_IN; ix++) {
+        regs->mio_periph_insel_regwen[ix] = 0x1u;
+    }
+    for (unsigned ix = 0; ix < PARAM_N_MIO_PADS; ix++) {
+        regs->mio_outsel_regwen[ix] = 0x1u;
+        regs->mio_outsel[ix] = 0x2u;
+        regs->mio_pad_attr_regwen[ix] = 0x1u;
+        regs->mio_pad_sleep_regwen[ix] = 0x1u;
+        regs->mio_pad_sleep_mode[ix] = 0x2u;
+    }
+    for (unsigned ix = 0; ix < PARAM_N_DIO_PADS; ix++) {
+        regs->dio_pad_attr_regwen[ix] = 0x1u;
+        regs->dio_pad_sleep_regwen[ix] = 0x1u;
+        regs->dio_pad_sleep_mode[ix] = 0x2u;
+    }
+    for (unsigned ix = 0; ix < PARAM_N_WKUP_DETECT; ix++) {
+        regs->wkup_detector_regwen[ix] = 0x1u;
+    }
+
+    ibex_irq_set(&s->alert, 0);
+}
+
+static void ot_pinmux_dj_init(Object *obj)
+{
+    OtPinmuxDjState *s = OT_PINMUX_DJ(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_pinmux_dj_regs_ops, s,
+                          TYPE_OT_PINMUX_DJ, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regs = g_new0(OtPinmuxDjStateRegs, 1u);
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    s->dios = g_new(IbexIRQ, PARAM_N_DIO_PADS);
+    s->mios = g_new(IbexIRQ, PARAM_N_MIO_PADS);
+    ibex_qdev_init_irqs_default(obj, s->dios, OT_PINMUX_DIO, PARAM_N_DIO_PADS,
+                                PAD_ATTR_ENABLE(false));
+    ibex_qdev_init_irqs_default(obj, s->mios, OT_PINMUX_MIO, PARAM_N_MIO_PADS,
+                                PAD_ATTR_ENABLE(false));
+}
+
+static void ot_pinmux_dj_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtPinmuxDjClass *pc = OT_PINMUX_DJ_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_pinmux_dj_reset_enter, NULL,
+                                       NULL, &pc->parent_phases);
+}
+
+static const TypeInfo ot_pinmux_info = {
+    .name = TYPE_OT_PINMUX_DJ,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtPinmuxDjState),
+    .instance_init = &ot_pinmux_dj_init,
+    .class_size = sizeof(OtPinmuxDjClass),
+    .class_init = &ot_pinmux_dj_class_init,
+};
+
+static void ot_pinmux_dj_register_types(void)
+{
+    type_register_static(&ot_pinmux_info);
+}
+
+type_init(ot_pinmux_dj_register_types);
diff --git a/hw/opentitan/ot_pinmux_eg.c b/hw/opentitan/ot_pinmux_eg.c
new file mode 100644
index 0000000000000..151643a431e2d
--- /dev/null
+++ b/hw/opentitan/ot_pinmux_eg.c
@@ -0,0 +1,580 @@
+/*
+ * QEMU OpenTitan EarlGrey PinMux device
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "qom/object.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_pinmux_eg.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+#define PARAM_N_MIO_PERIPH_IN  57u
+#define PARAM_N_MIO_PERIPH_OUT 75u
+#define PARAM_N_MIO_PADS       47u
+#define PARAM_N_DIO_PADS       16u
+#define PARAM_N_WKUP_DETECT    8u
+#define PARAM_NUM_ALERTS       1u
+#define BIT_PACKED_STATUS_REG  1
+
+#define REG_SIZE(_n_) ((_n_) * sizeof(uint32_t))
+
+#ifdef BIT_PACKED_STATUS_REG
+#define MIO_SLEEP_STATUS_COUNT    DIV_ROUND_UP(PARAM_N_MIO_PADS, 32u)
+#define DIO_SLEEP_STATUS_COUNT    DIV_ROUND_UP(PARAM_N_DIO_PADS, 32u)
+#define MIO_PAD_SLEEP_STATUS_REM  (PARAM_N_MIO_PADS & 31u)
+#define DIO_PAD_SLEEP_STATUS_REM  (PARAM_N_DIO_PADS & 31u)
+#define DIO_PAD_SLEEP_STATUS_MASK UINT32_MAX
+#define MIO_PAD_SLEEP_STATUS_MASK UINT32_MAX
+#else
+#define MIO_SLEEP_STATUS_COUNT    PARAM_N_MIO_PADS
+#define DIO_SLEEP_STATUS_COUNT    PARAM_N_DIO_PADS
+#define MIO_PAD_SLEEP_STATUS_REM  0
+#define DIO_PAD_SLEEP_STATUS_REM  0
+#define DIO_PAD_SLEEP_STATUS_MASK 1u
+#define MIO_PAD_SLEEP_STATUS_MASK 1u
+#endif
+#define N_MAX_PADS MAX(PARAM_N_MIO_PADS, PARAM_N_DIO_PADS)
+
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x0u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(MIO_PERIPH_INSEL_REGWEN, A_ALERT_TEST + REG_SIZE(1u))
+    FIELD(MIO_PERIPH_INSEL_REGWEN, EN, 0u, 1u)
+REG32(MIO_PERIPH_INSEL,
+      A_MIO_PERIPH_INSEL_REGWEN + REG_SIZE(PARAM_N_MIO_PERIPH_IN))
+REG32(MIO_OUTSEL_REGWEN,
+      A_MIO_PERIPH_INSEL + REG_SIZE(PARAM_N_MIO_PERIPH_IN))
+    FIELD(MIO_OUTSEL_REGWEN, EN, 0u, 1u)
+REG32(MIO_OUTSEL,
+      A_MIO_OUTSEL_REGWEN + REG_SIZE(PARAM_N_MIO_PADS))
+REG32(MIO_PAD_ATTR_REGWEN,
+      A_MIO_OUTSEL + REG_SIZE(PARAM_N_MIO_PADS))
+    FIELD(MIO_PAD_ATTR_REGWEN, EN, 0u, 1u)
+REG32(MIO_PAD_ATTR,
+      A_MIO_PAD_ATTR_REGWEN + REG_SIZE(PARAM_N_MIO_PADS))
+REG32(DIO_PAD_ATTR_REGWEN,
+      A_MIO_PAD_ATTR + REG_SIZE(PARAM_N_MIO_PADS))
+    FIELD(DIO_PAD_ATTR_REGWEN, EN, 0u, 1u)
+REG32(DIO_PAD_ATTR,
+      A_DIO_PAD_ATTR_REGWEN + REG_SIZE(PARAM_N_DIO_PADS))
+REG32(MIO_PAD_SLEEP_STATUS,
+      A_DIO_PAD_ATTR + REG_SIZE(PARAM_N_DIO_PADS))
+REG32(MIO_PAD_SLEEP_REGWEN,
+      A_MIO_PAD_SLEEP_STATUS + REG_SIZE(MIO_SLEEP_STATUS_COUNT))
+    FIELD(MIO_PAD_SLEEP_REGWEN, EN, 0u, 1u)
+REG32(MIO_PAD_SLEEP,
+      A_MIO_PAD_SLEEP_REGWEN + REG_SIZE(PARAM_N_MIO_PADS))
+    FIELD(MIO_PAD_SLEEP, EN, 0u, 1u)
+REG32(MIO_PAD_SLEEP_MODE,
+      A_MIO_PAD_SLEEP + REG_SIZE(PARAM_N_MIO_PADS))
+    FIELD(MIO_PAD_SLEEP_MODE, OUT, 0u, 2u)
+REG32(DIO_PAD_SLEEP_STATUS,
+      A_MIO_PAD_SLEEP_MODE + REG_SIZE(PARAM_N_MIO_PADS))
+REG32(DIO_PAD_SLEEP_REGWEN,
+      A_DIO_PAD_SLEEP_STATUS + REG_SIZE(DIO_SLEEP_STATUS_COUNT))
+    FIELD(DIO_PAD_SLEEP_REGWEN, EN, 0u, 1u)
+REG32(DIO_PAD_SLEEP,
+      A_DIO_PAD_SLEEP_REGWEN + REG_SIZE(PARAM_N_DIO_PADS))
+    FIELD(DIO_PAD_SLEEP, EN, 0u, 1u)
+REG32(DIO_PAD_SLEEP_MODE,
+      A_DIO_PAD_SLEEP + REG_SIZE(PARAM_N_DIO_PADS))
+    FIELD(DIO_PAD_SLEEP_MODE, OUT, 0u, 2u)
+REG32(WKUP_DETECTOR_REGWEN,
+     A_DIO_PAD_SLEEP_MODE + REG_SIZE(PARAM_N_DIO_PADS))
+    FIELD(WKUP_DETECTOR_REGWEN, EN, 0u, 1u)
+REG32(WKUP_DETECTOR,
+      A_WKUP_DETECTOR_REGWEN + REG_SIZE(PARAM_N_WKUP_DETECT))
+    FIELD(WKUP_DETECTOR, EN, 0u, 1u)
+REG32(WKUP_DETECTOR_CFG,
+      A_WKUP_DETECTOR + REG_SIZE(PARAM_N_WKUP_DETECT))
+    FIELD(WKUP_DETECTOR_CFG, MODE, 0u, 3u)
+    FIELD(WKUP_DETECTOR_CFG, FILTER, 3u, 1u)
+    FIELD(WKUP_DETECTOR_CFG, MIODIO, 4u, 1u)
+REG32(WKUP_DETECTOR_CNT_TH,
+      A_WKUP_DETECTOR_CFG + REG_SIZE(PARAM_N_WKUP_DETECT))
+    FIELD(WKUP_DETECTOR_CNT_TH, TH, 0u, 8u)
+REG32(WKUP_DETECTOR_PADSEL,
+      A_WKUP_DETECTOR_CNT_TH + REG_SIZE(PARAM_N_WKUP_DETECT))
+    FIELD(WKUP_DETECTOR_PADSEL, SEL, 0u, 6u)
+REG32(WKUP_CAUSE,
+      A_WKUP_DETECTOR_PADSEL + REG_SIZE(PARAM_N_WKUP_DETECT))
+/* clang-format on */
+
+#define MIO_PAD_ATTR_MASK               OT_PINMUX_PAD_ATTR_MASK
+#define DIO_PAD_ATTR_MASK               OT_PINMUX_PAD_ATTR_MASK
+#define MIO_PAD_SLEEP_MODE_OUT_TIE_LOW  0x0u
+#define MIO_PAD_SLEEP_MODE_OUT_TIE_HIGH 0x1u
+#define MIO_PAD_SLEEP_MODE_OUT_HIGH_Z   0x2u
+#define MIO_PAD_SLEEP_MODE_OUT_KEEP     0x3u
+#define DIO_PAD_SLEEP_MODE_OUT_TIE_LOW  0x0u
+#define DIO_PAD_SLEEP_MODE_OUT_TIE_HIGH 0x1u
+#define DIO_PAD_SLEEP_MODE_OUT_HIGH_Z   0x2u
+#define DIO_PAD_SLEEP_MODE_OUT_KEEP     0x3u
+#define WKUP_DETECTOR_MODE_POSEDGE      0x0u
+#define WKUP_DETECTOR_MODE_NEGEDGE      0x1u
+#define WKUP_DETECTOR_MODE_EDGE         0x2u
+#define WKUP_DETECTOR_MODE_TIMEDHIGH    0x3u
+#define WKUP_DETECTOR_MODE_TIMEDLOW     0x4u
+#define WKUP_CAUSE_MASK                 ((1u << PARAM_N_WKUP_DETECT) - 1u)
+#define WKUP_DETECTOR_CFG_MASK \
+    (R_WKUP_DETECTOR_CFG_MODE_MASK | R_WKUP_DETECTOR_CFG_FILTER_MASK | \
+     R_WKUP_DETECTOR_CFG_MIODIO_MASK)
+
+#define R32_OFF(_r_)             ((_r_) / sizeof(uint32_t))
+#define R_LAST_REG               (R_WKUP_CAUSE)
+#define REGS_COUNT               (R_LAST_REG + 1u)
+#define REGS_SIZE                (REGS_COUNT * sizeof(uint32_t))
+#define CASE_SCALAR(_reg_)       R_##_reg_
+#define CASE_RANGE(_reg_, _rpt_) R_##_reg_...(R_##_reg_ + (_rpt_) - (1u))
+#define PAD_ATTR_TO_IRQ(_pad_)   ((int)((_pad_) & INT32_MAX))
+#define PAD_ATTR_ENABLE(_en_)    (((unsigned)!(_en_)) << 31u)
+
+static_assert((OT_PINMUX_PAD_ATTR_MASK | OT_PINMUX_PAD_ATTR_FORCE_MODE_MASK) <
+                  (1u << 31u),
+              "Cannot encode PAD attr as IRQ");
+
+typedef struct {
+    uint32_t alert_test;
+    uint32_t mio_periph_insel_regwen[PARAM_N_MIO_PERIPH_IN];
+    uint32_t mio_periph_insel[PARAM_N_MIO_PERIPH_IN];
+    uint32_t mio_outsel_regwen[PARAM_N_MIO_PADS];
+    uint32_t mio_outsel[PARAM_N_MIO_PADS];
+    uint32_t mio_pad_attr_regwen[PARAM_N_MIO_PADS];
+    uint32_t mio_pad_attr[PARAM_N_MIO_PADS];
+    uint32_t dio_pad_attr_regwen[PARAM_N_DIO_PADS];
+    uint32_t dio_pad_attr[PARAM_N_DIO_PADS];
+    uint32_t mio_pad_sleep_status[MIO_SLEEP_STATUS_COUNT];
+    uint32_t mio_pad_sleep_regwen[PARAM_N_MIO_PADS];
+    uint32_t mio_pad_sleep[PARAM_N_MIO_PADS];
+    uint32_t mio_pad_sleep_mode[PARAM_N_MIO_PADS];
+    uint32_t dio_pad_sleep_status[DIO_SLEEP_STATUS_COUNT];
+    uint32_t dio_pad_sleep_regwen[PARAM_N_DIO_PADS];
+    uint32_t dio_pad_sleep[PARAM_N_DIO_PADS];
+    uint32_t dio_pad_sleep_mode[PARAM_N_DIO_PADS];
+    uint32_t wkup_detector_regwen[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_detector[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_detector_cfg[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_detector_cnt_th[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_detector_padsel[PARAM_N_WKUP_DETECT];
+    uint32_t wkup_cause;
+} OtPinmuxEgStateRegs;
+
+struct OtPinmuxEgState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ alert;
+    IbexIRQ *dios;
+    IbexIRQ *mios;
+
+    OtPinmuxEgStateRegs *regs;
+};
+
+struct OtPinmuxEgClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static uint32_t ot_pinmux_eg_sel_mask(unsigned val)
+{
+    return (1u << (32 - clz32(val))) - 1u;
+}
+
+static uint64_t ot_pinmux_eg_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtPinmuxEgState *s = opaque;
+    (void)size;
+    uint32_t val32;
+    hwaddr reg = R32_OFF(addr);
+    OtPinmuxEgStateRegs *regs = s->regs;
+
+    switch (reg) {
+    case CASE_RANGE(MIO_PERIPH_INSEL_REGWEN, PARAM_N_MIO_PERIPH_IN):
+        val32 = regs->mio_periph_insel_regwen[reg - R_MIO_PERIPH_INSEL_REGWEN];
+        break;
+    case CASE_RANGE(MIO_PERIPH_INSEL, PARAM_N_MIO_PERIPH_IN):
+        val32 = regs->mio_periph_insel[reg - R_MIO_PERIPH_INSEL];
+        break;
+    case CASE_RANGE(MIO_OUTSEL_REGWEN, PARAM_N_MIO_PADS):
+        val32 = regs->mio_outsel_regwen[reg - R_MIO_OUTSEL_REGWEN];
+        break;
+    case CASE_RANGE(MIO_OUTSEL, PARAM_N_MIO_PADS):
+        val32 = regs->mio_outsel[reg - R_MIO_OUTSEL];
+        break;
+    case CASE_RANGE(MIO_PAD_ATTR_REGWEN, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_attr_regwen[reg - R_MIO_PAD_ATTR_REGWEN];
+        break;
+    case CASE_RANGE(MIO_PAD_ATTR, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_attr[reg - R_MIO_PAD_ATTR];
+        break;
+    case CASE_RANGE(DIO_PAD_ATTR_REGWEN, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_attr_regwen[reg - R_DIO_PAD_ATTR_REGWEN];
+        break;
+    case CASE_RANGE(DIO_PAD_ATTR, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_attr[reg - R_DIO_PAD_ATTR];
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_STATUS, MIO_SLEEP_STATUS_COUNT):
+        val32 = regs->mio_pad_sleep_status[reg - R_MIO_PAD_SLEEP_STATUS];
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_REGWEN, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_sleep_regwen[reg - R_MIO_PAD_SLEEP_REGWEN];
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_sleep[reg - R_MIO_PAD_SLEEP];
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_MODE, PARAM_N_MIO_PADS):
+        val32 = regs->mio_pad_sleep_mode[reg - R_MIO_PAD_SLEEP_MODE];
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_STATUS, DIO_SLEEP_STATUS_COUNT):
+        val32 = regs->dio_pad_sleep_status[reg - R_DIO_PAD_SLEEP_STATUS];
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_REGWEN, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_sleep_regwen[reg - R_DIO_PAD_SLEEP_REGWEN];
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_sleep[reg - R_DIO_PAD_SLEEP];
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_MODE, PARAM_N_DIO_PADS):
+        val32 = regs->dio_pad_sleep_mode[reg - R_DIO_PAD_SLEEP_MODE];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_REGWEN, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector_regwen[reg - R_WKUP_DETECTOR_REGWEN];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector[reg - R_WKUP_DETECTOR];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_CFG, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector_cfg[reg - R_WKUP_DETECTOR_CFG];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_CNT_TH, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector_cnt_th[reg - R_WKUP_DETECTOR_CNT_TH];
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_PADSEL, PARAM_N_WKUP_DETECT):
+        val32 = regs->wkup_detector_padsel[reg - R_WKUP_DETECTOR_PADSEL];
+        break;
+    case CASE_SCALAR(WKUP_CAUSE):
+        val32 = regs->wkup_cause;
+        break;
+    case CASE_SCALAR(ALERT_TEST):
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_pinmux_io_read_out((uint32_t)addr, val32, pc);
+
+    return (uint64_t)val32;
+};
+
+#define OT_PINMUX_EG_IS_REGWEN(_off_, _ren_, _rw_) \
+    ((regs->_ren_##_regwen[(_off_) - (R_##_rw_)]) & 0x1u)
+
+static void ot_pinmux_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                    unsigned size)
+{
+    OtPinmuxEgState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+    hwaddr reg = R32_OFF(addr);
+    OtPinmuxEgStateRegs *regs = s->regs;
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_pinmux_io_write((uint32_t)addr, val32, pc);
+
+    switch (reg) {
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        if (val32) {
+            ibex_irq_set(&s->alert, (int)val32);
+        }
+        break;
+    case CASE_RANGE(MIO_PERIPH_INSEL_REGWEN, PARAM_N_MIO_PERIPH_IN):
+        val32 &= R_MIO_PERIPH_INSEL_REGWEN_EN_MASK;
+        regs->mio_periph_insel_regwen[reg - R_MIO_PERIPH_INSEL_REGWEN] = val32;
+        break;
+    case CASE_RANGE(MIO_PERIPH_INSEL, PARAM_N_MIO_PERIPH_IN):
+        if (OT_PINMUX_EG_IS_REGWEN(reg, mio_periph_insel, MIO_PERIPH_INSEL)) {
+            if (val32 >= PARAM_N_MIO_PERIPH_IN + 2u) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
+                              __func__, (unsigned)reg, val32);
+                uint32_t mask =
+                    ot_pinmux_eg_sel_mask(PARAM_N_MIO_PERIPH_IN + 2u);
+                val32 &= mask;
+            }
+            regs->mio_periph_insel[reg - R_MIO_PERIPH_INSEL] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(MIO_OUTSEL_REGWEN, PARAM_N_MIO_PADS):
+        val32 &= R_MIO_OUTSEL_REGWEN_EN_MASK;
+        regs->mio_outsel_regwen[reg - R_MIO_OUTSEL_REGWEN] = val32;
+        break;
+    case CASE_RANGE(MIO_OUTSEL, PARAM_N_MIO_PADS):
+        if (OT_PINMUX_EG_IS_REGWEN(reg, mio_outsel, MIO_OUTSEL)) {
+            if (val32 >= PARAM_N_MIO_PERIPH_OUT + 2u) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
+                              __func__, (unsigned)reg, val32);
+                uint32_t mask =
+                    ot_pinmux_eg_sel_mask(PARAM_N_MIO_PERIPH_OUT + 2u);
+                val32 &= mask;
+            }
+            regs->mio_outsel[reg - R_MIO_OUTSEL] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(MIO_PAD_ATTR_REGWEN, PARAM_N_MIO_PADS):
+        val32 &= R_MIO_PAD_ATTR_REGWEN_EN_MASK;
+        regs->mio_pad_attr_regwen[reg - R_MIO_PAD_ATTR_REGWEN] = val32;
+        break;
+    case CASE_RANGE(MIO_PAD_ATTR, PARAM_N_MIO_PADS):
+        if (OT_PINMUX_EG_IS_REGWEN(reg, mio_pad_attr, MIO_PAD_ATTR)) {
+            val32 &= MIO_PAD_ATTR_MASK;
+            unsigned pad_no = reg - R_MIO_PAD_ATTR;
+            g_assert(pad_no < R_MIO_PAD_ATTR);
+            regs->mio_pad_attr[pad_no] = val32;
+            ibex_irq_set(&s->mios[pad_no], PAD_ATTR_TO_IRQ(val32));
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(DIO_PAD_ATTR_REGWEN, PARAM_N_DIO_PADS):
+        val32 &= R_DIO_PAD_ATTR_REGWEN_EN_MASK;
+        regs->dio_pad_attr_regwen[reg - R_DIO_PAD_ATTR_REGWEN] = val32;
+        break;
+    case CASE_RANGE(DIO_PAD_ATTR, PARAM_N_DIO_PADS):
+        if (OT_PINMUX_EG_IS_REGWEN(reg, dio_pad_attr, DIO_PAD_ATTR)) {
+            val32 &= DIO_PAD_ATTR_MASK;
+            unsigned pad_no = reg - R_DIO_PAD_ATTR;
+            g_assert(pad_no < PARAM_N_DIO_PADS);
+            regs->dio_pad_attr[pad_no] = val32;
+            ibex_irq_set(&s->dios[pad_no], PAD_ATTR_TO_IRQ(val32));
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_STATUS, MIO_SLEEP_STATUS_COUNT):
+        val32 &= MIO_PAD_SLEEP_STATUS_MASK;
+#if defined(BIT_PACKED_STATUS_REG) && (MIO_PAD_SLEEP_STATUS_REM != 0)
+        if (reg == R_MIO_PAD_SLEEP_STATUS + MIO_SLEEP_STATUS_COUNT - 1u) {
+            val32 &= (1u << MIO_PAD_SLEEP_STATUS_REM) - 1u;
+        }
+#endif
+        regs->mio_pad_sleep_status[reg - R_MIO_PAD_SLEEP_STATUS] = val32;
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_REGWEN, PARAM_N_MIO_PADS):
+        val32 &= R_MIO_PAD_SLEEP_REGWEN_EN_MASK;
+        regs->mio_pad_sleep_regwen[reg - R_MIO_PAD_SLEEP_REGWEN] = val32;
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP, PARAM_N_MIO_PADS):
+        if (OT_PINMUX_EG_IS_REGWEN(reg, mio_pad_sleep, MIO_PAD_SLEEP)) {
+            val32 &= R_MIO_PAD_SLEEP_EN_MASK;
+            regs->mio_pad_sleep[reg - R_MIO_PAD_SLEEP] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(MIO_PAD_SLEEP_MODE, PARAM_N_MIO_PADS):
+        val32 &= R_MIO_PAD_SLEEP_MODE_OUT_MASK;
+        regs->mio_pad_sleep_mode[reg - R_MIO_PAD_SLEEP_MODE] = val32;
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_STATUS, DIO_SLEEP_STATUS_COUNT):
+        val32 &= DIO_PAD_SLEEP_STATUS_MASK;
+#if defined(BIT_PACKED_STATUS_REG) && (DIO_PAD_SLEEP_STATUS_REM != 0)
+        if (reg == R_DIO_PAD_SLEEP_STATUS + DIO_SLEEP_STATUS_COUNT - 1u) {
+            val32 &= (1u << DIO_PAD_SLEEP_STATUS_REM) - 1u;
+        }
+#endif
+        regs->dio_pad_sleep_status[reg - R_DIO_PAD_SLEEP_STATUS] = val32;
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_REGWEN, PARAM_N_DIO_PADS):
+        val32 &= R_DIO_PAD_SLEEP_REGWEN_EN_MASK;
+        regs->dio_pad_sleep_regwen[reg - R_DIO_PAD_SLEEP_REGWEN] = val32;
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP, PARAM_N_DIO_PADS):
+        if (OT_PINMUX_EG_IS_REGWEN(reg, dio_pad_sleep, DIO_PAD_SLEEP)) {
+            val32 &= R_DIO_PAD_SLEEP_EN_MASK;
+            regs->dio_pad_sleep[reg - R_DIO_PAD_SLEEP] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(DIO_PAD_SLEEP_MODE, PARAM_N_DIO_PADS):
+        val32 &= R_DIO_PAD_SLEEP_MODE_OUT_MASK;
+        regs->dio_pad_sleep_mode[reg - R_DIO_PAD_SLEEP_MODE] = val32;
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_REGWEN, PARAM_N_WKUP_DETECT):
+        val32 &= R_WKUP_DETECTOR_REGWEN_EN_MASK;
+        regs->wkup_detector_regwen[reg - R_WKUP_DETECTOR_REGWEN] = val32;
+        break;
+    case CASE_RANGE(WKUP_DETECTOR, PARAM_N_WKUP_DETECT):
+        if (OT_PINMUX_EG_IS_REGWEN(reg, wkup_detector, WKUP_DETECTOR)) {
+            val32 &= R_WKUP_DETECTOR_EN_MASK;
+            regs->wkup_detector[reg - R_WKUP_DETECTOR] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x access is disabled\n",
+                          __func__, (uint32_t)addr);
+        }
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_CFG, PARAM_N_WKUP_DETECT):
+        val32 &= WKUP_DETECTOR_CFG_MASK;
+        regs->wkup_detector[reg - R_WKUP_DETECTOR_CFG] = val32;
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_CNT_TH, PARAM_N_WKUP_DETECT):
+        val32 &= R_WKUP_DETECTOR_CNT_TH_TH_MASK;
+        regs->wkup_detector_cnt_th[reg - R_WKUP_DETECTOR_CNT_TH] = val32;
+        break;
+    case CASE_RANGE(WKUP_DETECTOR_PADSEL, PARAM_N_WKUP_DETECT):
+        if (val32 >= N_MAX_PADS) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: 0x%03x too large: %u\n",
+                          __func__, (unsigned)reg, val32);
+            uint32_t mask = ot_pinmux_eg_sel_mask(N_MAX_PADS);
+            val32 &= mask;
+        }
+        regs->wkup_detector_padsel[reg - R_WKUP_DETECTOR_PADSEL] = val32;
+        break;
+    case CASE_SCALAR(WKUP_CAUSE):
+        val32 %= WKUP_CAUSE_MASK;
+        regs->wkup_cause = val32;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+};
+
+static const MemoryRegionOps ot_pinmux_eg_regs_ops = {
+    .read = &ot_pinmux_eg_regs_read,
+    .write = &ot_pinmux_eg_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_pinmux_eg_reset_enter(Object *obj, ResetType type)
+{
+    OtPinmuxEgClass *c = OT_PINMUX_EG_GET_CLASS(obj);
+    OtPinmuxEgState *s = OT_PINMUX_EG(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    OtPinmuxEgStateRegs *regs = s->regs;
+    memset(regs, 0, sizeof(*regs));
+
+    for (unsigned ix = 0; ix < PARAM_N_MIO_PERIPH_IN; ix++) {
+        regs->mio_periph_insel_regwen[ix] = 0x1u;
+    }
+    for (unsigned ix = 0; ix < PARAM_N_MIO_PADS; ix++) {
+        regs->mio_outsel_regwen[ix] = 0x1u;
+        regs->mio_outsel[ix] = 0x2u;
+        regs->mio_pad_attr_regwen[ix] = 0x1u;
+        regs->mio_pad_sleep_regwen[ix] = 0x1u;
+        regs->mio_pad_sleep_mode[ix] = 0x2u;
+    }
+    for (unsigned ix = 0; ix < PARAM_N_DIO_PADS; ix++) {
+        regs->dio_pad_attr_regwen[ix] = 0x1u;
+        regs->dio_pad_sleep_regwen[ix] = 0x1u;
+        regs->dio_pad_sleep_mode[ix] = 0x2u;
+    }
+    for (unsigned ix = 0; ix < PARAM_N_WKUP_DETECT; ix++) {
+        regs->wkup_detector_regwen[ix] = 0x1u;
+    }
+
+    ibex_irq_set(&s->alert, 0);
+}
+
+static void ot_pinmux_eg_init(Object *obj)
+{
+    OtPinmuxEgState *s = OT_PINMUX_EG(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_pinmux_eg_regs_ops, s,
+                          TYPE_OT_PINMUX_EG, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regs = g_new0(OtPinmuxEgStateRegs, 1u);
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    s->dios = g_new(IbexIRQ, PARAM_N_DIO_PADS);
+    s->mios = g_new(IbexIRQ, PARAM_N_MIO_PADS);
+    ibex_qdev_init_irqs_default(obj, s->dios, OT_PINMUX_DIO, PARAM_N_DIO_PADS,
+                                PAD_ATTR_ENABLE(false));
+    ibex_qdev_init_irqs_default(obj, s->mios, OT_PINMUX_MIO, PARAM_N_MIO_PADS,
+                                PAD_ATTR_ENABLE(false));
+}
+
+static void ot_pinmux_eg_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtPinmuxEgClass *pc = OT_PINMUX_EG_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_pinmux_eg_reset_enter, NULL,
+                                       NULL, &pc->parent_phases);
+}
+
+static const TypeInfo ot_pinmux_eg_info = {
+    .name = TYPE_OT_PINMUX_EG,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtPinmuxEgState),
+    .instance_init = &ot_pinmux_eg_init,
+    .class_size = sizeof(OtPinmuxEgClass),
+    .class_init = &ot_pinmux_eg_class_init,
+};
+
+static void ot_pinmux_eg_register_types(void)
+{
+    type_register_static(&ot_pinmux_eg_info);
+}
+
+type_init(ot_pinmux_eg_register_types);
diff --git a/hw/opentitan/ot_plic_ext.c b/hw/opentitan/ot_plic_ext.c
new file mode 100644
index 0000000000000..3b15ce494209b
--- /dev/null
+++ b/hw/opentitan/ot_plic_ext.c
@@ -0,0 +1,302 @@
+/*
+ * QEMU OpenTitan PLIC extension
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_plic_ext.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "system/memory.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(MSIP0, 0x0u)
+    FIELD(MSIP0, EN, 0u, 1u)
+
+REG32(ALERT_TEST, 0x0u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+/* clang-format on */
+
+#define OT_PLIC_EXT_MSIP_BASE  0x0u
+#define OT_PLIC_EXT_ALERT_BASE 0x4000u
+#define OT_PLIC_EXT_APERTURE   0x8000u
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_MSIP_REG (R_MSIP0)
+#define MSIP_REGS_COUNT (R_LAST_MSIP_REG + 1u)
+#define MSIP_REGS_SIZE  (MSIP_REGS_COUNT * sizeof(uint32_t))
+#define MSIP_REG_NAME(_reg_) \
+    ((((_reg_) < MSIP_REGS_COUNT) && MSIP_REG_NAMES[_reg_]) ? \
+         MSIP_REG_NAMES[_reg_] : \
+         "?")
+
+#define R_LAST_ALERT_REG (R_ALERT_TEST)
+#define ALERT_REGS_COUNT (R_LAST_ALERT_REG + 1u)
+#define ALERT_REGS_SIZE  (ALERT_REGS_COUNT * sizeof(uint32_t))
+#define ALERT_REG_NAME(_reg_) \
+    ((((_reg_) < ALERT_REGS_COUNT) && ALERT_REG_NAMES[_reg_]) ? \
+         ALERT_REG_NAMES[_reg_] : \
+         "?")
+
+struct OtPlicExtState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mem;
+    MemoryRegion mmio_msip;
+    MemoryRegion mmio_alert;
+
+    IbexIRQ irq;
+    IbexIRQ alert;
+
+    uint32_t msip_regs[MSIP_REGS_COUNT];
+
+    char *ot_id;
+};
+
+struct OtPlicExtClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *MSIP_REG_NAMES[MSIP_REGS_COUNT] = {
+    REG_NAME_ENTRY(MSIP0),
+};
+
+static const char *ALERT_REG_NAMES[ALERT_REGS_COUNT] = {
+    REG_NAME_ENTRY(ALERT_TEST),
+};
+#undef REG_NAME_ENTRY
+
+static uint64_t ot_plic_ext_msip_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtPlicExtState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    /* NOLINTNEXTLINE(hicpp-multiway-paths-covered) */
+    switch (reg) {
+    case R_MSIP0:
+        val32 = s->msip_regs[reg];
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%01x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_plic_ext_io_msip_read_out(s->ot_id, (uint32_t)addr,
+                                       MSIP_REG_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_plic_ext_msip_write(void *opaque, hwaddr addr, uint64_t val64,
+                                   unsigned size)
+{
+    OtPlicExtState *s = opaque;
+    uint32_t val32 = (uint32_t)val64;
+    (void)size;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_plic_ext_io_msip_write(s->ot_id, (uint32_t)addr,
+                                    MSIP_REG_NAME(reg), val32, pc);
+
+    /* NOLINTNEXTLINE(hicpp-multiway-paths-covered) */
+    switch (reg) {
+    case R_MSIP0:
+        val32 &= R_MSIP0_EN_MASK;
+        s->msip_regs[reg] = val32;
+        ibex_irq_set(&s->irq, (int)(bool)val32);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%01x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static uint64_t ot_plic_ext_alert_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtPlicExtState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    /* NOLINTNEXTLINE(hicpp-multiway-paths-covered) */
+    switch (reg) {
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%01x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, ALERT_REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%01x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_plic_ext_io_alert_read_out(s->ot_id, (uint32_t)addr,
+                                        ALERT_REG_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_plic_ext_alert_write(void *opaque, hwaddr addr, uint64_t val64,
+                                    unsigned size)
+{
+    OtPlicExtState *s = opaque;
+    uint32_t val32 = (uint32_t)val64;
+    (void)size;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_plic_ext_io_alert_write(s->ot_id, (uint32_t)addr,
+                                     ALERT_REG_NAME(reg), val32, pc);
+
+    /* NOLINTNEXTLINE(hicpp-multiway-paths-covered) */
+    switch (reg) {
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%01x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static const Property ot_plic_ext_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtPlicExtState, ot_id),
+};
+
+static const MemoryRegionOps ot_plic_ext_msip_ops = {
+    .read = &ot_plic_ext_msip_read,
+    .write = &ot_plic_ext_msip_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_plic_ext_alert_ops = {
+    .read = &ot_plic_ext_alert_read,
+    .write = &ot_plic_ext_alert_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_plic_ext_reset_enter(Object *obj, ResetType type)
+{
+    OtPlicExtClass *c = OT_PLIC_EXT_GET_CLASS(obj);
+    OtPlicExtState *s = OT_PLIC_EXT(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    ibex_irq_set(&s->irq, 0);
+    ibex_irq_set(&s->alert, 0);
+}
+
+static void ot_plic_ext_realize(DeviceState *dev, Error **errp)
+{
+    OtPlicExtState *s = OT_PLIC_EXT(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+}
+
+static void ot_plic_ext_init(Object *obj)
+{
+    OtPlicExtState *s = OT_PLIC_EXT(obj);
+
+    /* Top-level container */
+    memory_region_init(&s->mem, obj, TYPE_OT_PLIC_EXT, OT_PLIC_EXT_APERTURE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mem);
+
+    memory_region_init_io(&s->mmio_msip, obj, &ot_plic_ext_msip_ops, s,
+                          TYPE_OT_PLIC_EXT ".msip", MSIP_REGS_SIZE);
+    memory_region_add_subregion(&s->mem, OT_PLIC_EXT_MSIP_BASE, &s->mmio_msip);
+
+    memory_region_init_io(&s->mmio_alert, obj, &ot_plic_ext_alert_ops, s,
+                          TYPE_OT_PLIC_EXT ".alert", ALERT_REGS_SIZE);
+    memory_region_add_subregion(&s->mem, OT_PLIC_EXT_ALERT_BASE,
+                                &s->mmio_alert);
+
+    ibex_qdev_init_irq(obj, &s->irq, NULL);
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+}
+
+static void ot_plic_ext_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_plic_ext_realize;
+    device_class_set_props(dc, ot_plic_ext_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtPlicExtClass *pc = OT_PLIC_EXT_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_plic_ext_reset_enter, NULL, NULL,
+                                       &pc->parent_phases);
+}
+
+static const TypeInfo ot_plic_ext_info = {
+    .name = TYPE_OT_PLIC_EXT,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtPlicExtState),
+    .instance_init = &ot_plic_ext_init,
+    .class_size = sizeof(OtPlicExtClass),
+    .class_init = &ot_plic_ext_class_init,
+};
+
+static void ot_plic_ext_register_types(void)
+{
+    type_register_static(&ot_plic_ext_info);
+}
+
+type_init(ot_plic_ext_register_types);
diff --git a/hw/opentitan/ot_present.c b/hw/opentitan/ot_present.c
new file mode 100644
index 0000000000000..74e5efa8abe80
--- /dev/null
+++ b/hw/opentitan/ot_present.c
@@ -0,0 +1,226 @@
+/*
+ * QEMU OpenTitan Present 128-bit key cipher implementation
+ *
+ * Copyright lowRISC contributors.
+ * Reworked 2024 Emmanuel Blot <eblot@rivosinc.com> from Python implementation.
+
+ * Licensed under the Apache License, Version 2.0, see LICENSE for details.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Simple unhardened reference implementation of the PRESENT cipher, following
+ * the description in
+ *
+ *   [1] Bognadov et al, PRESENT: An Ultra-Lightweight Block Cipher. LNCS 4727:
+ *       450–466. doi:10.1007/978-3-540-74735-2_31.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_present.h"
+
+/* warning: not thread safe when enabled */
+#undef OT_PRESENT_DEBUG
+
+#define OT_PRESENT_ROUND 32u
+
+typedef struct {
+    uint64_t hi;
+    uint64_t lo;
+} OtPresentKey;
+
+struct OtPresentState {
+    uint64_t keys[OT_PRESENT_ROUND];
+#ifdef OT_PRESENT_ROUND
+    char *hexstr;
+#endif
+};
+
+static const uint8_t OT_PRESENT_SBOX4[16u] = {
+    12u, 5u, 6u, 11u, 9u, 0, 10u, 13u, 3u, 14u, 15u, 8u, 4u, 7u, 1u, 2u
+};
+
+static const uint8_t OT_PRESENT_SBOX4_INV[16u] = {
+    5u, 14u, 15u, 8u, 12u, 1u, 2u, 13u, 11u, 4u, 6u, 3u, 0u, 7u, 9u, 10u
+};
+
+static const uint8_t OT_PRESENT_BIT_PERM[64u] = {
+    0,   16u, 32u, 48u, 1u,  17u, 33u, 49u, 2u,  18u, 34u, 50u, 3u,
+    19u, 35u, 51u, 4u,  20u, 36u, 52u, 5u,  21u, 37u, 53u, 6u,  22u,
+    38u, 54u, 7u,  23u, 39u, 55u, 8u,  24u, 40u, 56u, 9u,  25u, 41u,
+    57u, 10u, 26u, 42u, 58u, 11u, 27u, 43u, 59u, 12u, 28u, 44u, 60u,
+    13u, 29u, 45u, 61u, 14u, 30u, 46u, 62u, 15u, 31u, 47u, 63u
+};
+
+static const uint8_t OT_PRESENT_BIT_PERM_INV[64u] = {
+    0,   4u,  8u,  12u, 16u, 20u, 24u, 28u, 32u, 36u, 40u, 44u, 48u,
+    52u, 56u, 60u, 1u,  5u,  9u,  13u, 17u, 21u, 25u, 29u, 33u, 37u,
+    41u, 45u, 49u, 53u, 57u, 61u, 2u,  6u,  10u, 14u, 18u, 22u, 26u,
+    30u, 34u, 38u, 42u, 46u, 50u, 54u, 58u, 62u, 3u,  7u,  11u, 15u,
+    19u, 23u, 27u, 31u, 35u, 39u, 43u, 47u, 51u, 55u, 59u, 63u
+};
+
+#define MASK64(_x_) MAKE_64BIT_MASK(0, (unsigned)(_x_))
+
+#ifdef OT_PRESENT_DEBUG
+#define TRACE_PRESENT(msg, ...) \
+    qemu_log("%s: " msg "\n", __func__, ##__VA_ARGS__);
+#else
+#define TRACE_PRESENT(msg, ...)
+#endif
+
+/*----------------------------------------------------------------------------*/
+/* Helpers */
+/*----------------------------------------------------------------------------*/
+
+static OtPresentKey next_round_key(OtPresentKey k, unsigned round_count)
+{
+    assert((round_count >> 5u) == 0);
+
+    uint64_t rot_hi = (((k.hi & MASK64(3u)) << 61u) | (k.lo >> 3u));
+    uint64_t rot_lo = (((k.lo & MASK64(3u)) << 61u) | (k.hi >> 3u));
+
+    uint64_t rot_nib124 = (rot_hi >> 60u) & MASK64(4u);
+    uint64_t rot_nib120 = (rot_hi >> 56u) & MASK64(4u);
+
+    uint64_t subst_hi = (((uint64_t)OT_PRESENT_SBOX4[rot_nib124] << 60u) |
+                         ((uint64_t)OT_PRESENT_SBOX4[rot_nib120] << 56u) |
+                         (rot_hi & MASK64(56u)));
+    uint64_t subst_lo = rot_lo;
+
+    uint64_t xored_hi = subst_hi ^ ((uint64_t)round_count >> 2u);
+    uint64_t xored_lo = subst_lo ^ ((uint64_t)round_count << 62u);
+
+    OtPresentKey next = { .hi = xored_hi, .lo = xored_lo };
+
+    return next;
+}
+
+static inline uint64_t add_round_key(uint64_t data, uint64_t key)
+{
+    return data ^ key;
+}
+
+static uint64_t sbox_layer(uint64_t data)
+{
+    uint64_t ret = 0;
+
+    for (unsigned npos = 0; npos < 64u / 4u; ++npos) {
+        unsigned nibble = (data >> (4u * npos)) & 0xfu;
+        ret |= ((uint64_t)OT_PRESENT_SBOX4[nibble]) << (4u * npos);
+    }
+
+    return ret;
+}
+
+static uint64_t sbox_inv_layer(uint64_t data)
+{
+    uint64_t ret = 0;
+
+    for (unsigned npos = 0; npos < 64u / 4u; ++npos) {
+        unsigned nibble = (data >> (4u * npos)) & 0xfu;
+        ret |= ((uint64_t)OT_PRESENT_SBOX4_INV[nibble]) << (4u * npos);
+    }
+
+    return ret;
+}
+
+static uint64_t perm_layer(uint64_t data)
+{
+    uint64_t ret = 0;
+
+    for (unsigned npos = 0; npos < 64u; ++npos) {
+        uint64_t bit = (data >> npos) & 1u;
+        ret |= bit << OT_PRESENT_BIT_PERM[npos];
+    }
+
+    return ret;
+}
+
+static uint64_t perm_inv_layer(uint64_t data)
+{
+    uint64_t ret = 0;
+
+    for (unsigned npos = 0; npos < 64u; ++npos) {
+        uint64_t bit = (data >> npos) & 1u;
+        ret |= bit << OT_PRESENT_BIT_PERM_INV[npos];
+    }
+
+    return ret;
+}
+
+#ifdef OT_PRESENT_DEBUG
+#define OT_PRESENT_HEXSTR_SIZE 256u
+#define ot_present_hexdump(_s_, _b_, _l_) \
+    ot_common_lhexdump((const uint8_t *)_b_, _l_, false, (_s_)->hexstr, \
+                       OT_PRESENT_HEXSTR_SIZE)
+#else
+#define ot_present_hexdump(_s_, _b_, _l_)
+#endif
+
+/*----------------------------------------------------------------------------*/
+/* Public API */
+/*----------------------------------------------------------------------------*/
+
+OtPresentState *ot_present_new(void)
+{
+    OtPresentState *ps = g_new0(OtPresentState, 1u);
+#ifdef OT_PRESENT_DEBUG
+    ps->hexstr = g_new0(char, OT_PRESENT_HEXSTR_SIZE);
+#endif
+    return ps;
+}
+
+void ot_present_free(OtPresentState *ps)
+{
+    g_free(ps);
+}
+
+void ot_present_init(OtPresentState *ps, const uint8_t *key)
+{
+    OtPresentKey k128;
+
+    TRACE_PRESENT("present init %s", ot_present_hexdump(ps, key, 16u));
+
+    memcpy(&k128.hi, &key[8u], sizeof(uint64_t));
+    memcpy(&k128.lo, &key[0u], sizeof(uint64_t));
+
+    unsigned round = 0;
+    ps->keys[round++] = k128.hi;
+    while (round < OT_PRESENT_ROUND) {
+        k128 = next_round_key(k128, round);
+        ps->keys[round] = k128.hi;
+        round++;
+    }
+}
+
+void ot_present_encrypt(const OtPresentState *ps, uint64_t src, uint64_t *dst)
+{
+    uint64_t state = src;
+
+    for (unsigned round = 0; round < OT_PRESENT_ROUND - 1u; round++) {
+        state = add_round_key(state, ps->keys[round]);
+        state = sbox_layer(state);
+        state = perm_layer(state);
+    }
+    state = add_round_key(state, ps->keys[OT_PRESENT_ROUND - 1u]);
+
+    *dst = state;
+
+    TRACE_PRESENT("present encrypt %016llx -> %016llx", src, *dst);
+}
+
+void ot_present_decrypt(const OtPresentState *ps, uint64_t src, uint64_t *dst)
+{
+    uint64_t state = src;
+
+    for (unsigned round = OT_PRESENT_ROUND - 1u; round > 0; round--) {
+        state = add_round_key(state, ps->keys[round]);
+        state = perm_inv_layer(state);
+        state = sbox_inv_layer(state);
+    }
+    state = add_round_key(state, ps->keys[0]);
+
+    *dst = state;
+}
diff --git a/hw/opentitan/ot_prince.c b/hw/opentitan/ot_prince.c
new file mode 100644
index 0000000000000..b04876b487f55
--- /dev/null
+++ b/hw/opentitan/ot_prince.c
@@ -0,0 +1,181 @@
+/*
+ * QEMU OpenTitan Prince implementation
+ *
+ * Copyright (c) lowRISC contributors.
+ * Licensed under the Apache License, Version 2.0, see LICENSE for details.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "qemu/log.h"
+#include "hw/opentitan/ot_prince.h"
+
+/* clang-format off */
+
+static const uint8_t PRINCE_SBOX4[] = {
+    0xbu, 0xfu, 0x3u, 0x2u,
+    0xau, 0xcu, 0x9u, 0x1u,
+    0x6u, 0x7u, 0x8u, 0x0u,
+    0xeu, 0x5u, 0xdu, 0x4u
+};
+
+static const uint8_t PRINCE_SBOX4_INV[] = {
+    0xbu, 0x7u, 0x3u, 0x2u,
+    0xfu, 0xdu, 0x8u, 0x9u,
+    0xau, 0x6u, 0x4u, 0x0u,
+    0x5u, 0xeu, 0xcu, 0x1u
+};
+
+static const uint8_t PRINCE_SHIFT_ROWS64[] = {
+    0x4u, 0x9u, 0xeu, 0x3u,
+    0x8u, 0xdu, 0x2u, 0x7u,
+    0xcu, 0x1u, 0x6u, 0xbu,
+    0x0u, 0x5u, 0xau, 0xfu
+};
+
+static const uint8_t PRINCE_SHIFT_ROWS64_INV[] = {
+    0xcu, 0x9u, 0x6u, 0x3u,
+    0x0u, 0xdu, 0xau, 0x7u,
+    0x4u, 0x1u, 0xeu, 0xbu,
+    0x8u, 0x5u, 0x2u, 0xfu
+};
+
+static const uint64_t PRINCE_ROUND_CONSTS[] = {
+    0x0000000000000000ull,
+    0x13198a2e03707344ull,
+    0xa4093822299f31d0ull,
+    0x082efa98ec4e6c89ull,
+    0x452821e638d01377ull,
+    0xbe5466cf34e90c6cull,
+    0x7ef84f78fd955cb1ull,
+    0x85840851f1ac43aaull,
+    0xc882d32f25323c54ull,
+    0x64a51195e0e3610dull,
+    0xd3b5a399ca0c2399ull,
+    0xc0ac29b7c97c50ddull
+};
+
+static const uint16_t PRINCE_SHIFT_ROWS_CONSTS[] = {
+    0x7bdeu, 0xbde7u, 0xde7bu, 0xe7bdu
+};
+
+/* clang-format on */
+
+static uint64_t ot_prince_sbox(uint64_t in, unsigned width, const uint8_t *sbox)
+{
+    uint64_t full_mask = ((width >= 64u) ? 0ull : (1ull << width)) - 1ull;
+    width &= ~3ull;
+    uint64_t sbox_mask = ((width >= 64u) ? 0ull : (1ull << width)) - 1ull;
+
+    uint64_t ret = in & (full_mask & ~sbox_mask);
+
+    for (unsigned ix = 0; ix < width; ix += 4u) {
+        uint64_t nibble = (in >> ix) & 0xfull;
+        ret |= ((uint64_t)sbox[nibble]) << ix;
+    }
+
+    return ret;
+}
+
+static inline uint64_t ot_prince_nibble_red16(uint64_t data)
+{
+    uint64_t nib0 = (data >> 0u) & 0xfull;
+    uint64_t nib1 = (data >> 4u) & 0xfull;
+    uint64_t nib2 = (data >> 8u) & 0xfull;
+    uint64_t nib3 = (data >> 12u) & 0xfull;
+
+    return nib0 ^ nib1 ^ nib2 ^ nib3;
+}
+
+static uint64_t ot_prince_mult_prime(uint64_t data)
+{
+    uint64_t ret = 0u;
+    for (unsigned blk_idx = 0u; blk_idx < 4u; blk_idx++) {
+        uint64_t data_hw = (data >> (16u * blk_idx)) & 0xffffull;
+        unsigned start_sr_idx = (blk_idx == 0u || blk_idx == 3u) ? 0u : 1u;
+        for (unsigned nibble_idx = 0u; nibble_idx < 4u; nibble_idx++) {
+            unsigned sr_idx = (start_sr_idx + 3u - nibble_idx) & 0x3u;
+            uint64_t sr_const = (uint64_t)PRINCE_SHIFT_ROWS_CONSTS[sr_idx];
+            uint64_t nibble = ot_prince_nibble_red16(data_hw & sr_const);
+            ret |= nibble << (16u * blk_idx + 4u * nibble_idx);
+        }
+    }
+    return ret;
+}
+
+static uint64_t ot_prince_shiftrows(uint64_t data, bool invert)
+{
+    const uint8_t *shifts =
+        invert ? PRINCE_SHIFT_ROWS64_INV : PRINCE_SHIFT_ROWS64;
+
+    uint64_t ret = 0u;
+    for (unsigned nibble_idx = 0; nibble_idx < 64u / 4u; nibble_idx++) {
+        unsigned src_nibble_idx = shifts[nibble_idx];
+        uint64_t src_nibble = (data >> (4u * src_nibble_idx)) & 0xfu;
+        ret |= src_nibble << (4u * nibble_idx);
+    }
+    return ret;
+}
+
+static uint64_t ot_prince_fwd_round(uint64_t rc, uint64_t key, uint64_t data)
+{
+    data = ot_prince_sbox(data, 64u, PRINCE_SBOX4);
+    data = ot_prince_mult_prime(data);
+    data = ot_prince_shiftrows(data, false);
+    data ^= rc;
+    data ^= key;
+    return data;
+}
+
+static uint64_t ot_prince_inv_round(uint64_t rc, uint64_t key, uint64_t data)
+{
+    data ^= key;
+    data ^= rc;
+    data = ot_prince_shiftrows(data, true);
+    data = ot_prince_mult_prime(data);
+    data = ot_prince_sbox(data, 64u, PRINCE_SBOX4_INV);
+    return data;
+}
+
+/*
+ * Run the PRINCE cipher.
+ * This uses the new keyschedule proposed by Dinur in "Cryptanalytic
+ * Time-Memory-Data Tradeoffs for FX-Constructions with Applications to PRINCE
+ * and PRIDE".
+ */
+uint64_t ot_prince_run(uint64_t data, uint64_t khi, uint64_t klo,
+                       unsigned num_rounds_half)
+{
+    uint64_t khi_rot1 = ((khi & 1u) << 63u) | (khi >> 1u);
+    uint64_t khi_prime = khi_rot1 ^ (khi >> 63u);
+
+    data ^= khi;
+    data ^= klo;
+    data ^= PRINCE_ROUND_CONSTS[0];
+
+    for (unsigned hri = 0u; hri < num_rounds_half; hri++) {
+        unsigned round_idx = 1u + hri;
+        uint64_t rc = PRINCE_ROUND_CONSTS[round_idx];
+        uint64_t rk = (round_idx & 1u) ? khi : klo;
+        data = ot_prince_fwd_round(rc, rk, data);
+    }
+
+    data = ot_prince_sbox(data, 64u, PRINCE_SBOX4);
+    data = ot_prince_mult_prime(data);
+    data = ot_prince_sbox(data, 64u, PRINCE_SBOX4_INV);
+
+    for (unsigned hri = 0u; hri < num_rounds_half; hri++) {
+        unsigned round_idx = 11u - num_rounds_half + hri;
+        uint64_t rc = PRINCE_ROUND_CONSTS[round_idx];
+        uint64_t rk = (round_idx & 1u) ? klo : khi;
+        data = ot_prince_inv_round(rc, rk, data);
+    }
+
+    data ^= PRINCE_ROUND_CONSTS[11u];
+    data ^= klo;
+
+    data ^= khi_prime;
+
+    return data;
+}
diff --git a/hw/opentitan/ot_prng.c b/hw/opentitan/ot_prng.c
new file mode 100644
index 0000000000000..45128ae529080
--- /dev/null
+++ b/hw/opentitan/ot_prng.c
@@ -0,0 +1,81 @@
+/*
+ * QEMU OpenTitan Pseudo Random Generator
+ *
+ * Copyright (c) 2023 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+#include "hw/opentitan/ot_prng.h"
+
+DECLARE_INSTANCE_CHECKER(OtPrngState, OT_PRNG, TYPE_OT_PRNG)
+
+struct OtPrngState {
+    GRand *rand;
+};
+
+OtPrngState *ot_prng_allocate(void)
+{
+    OtPrngState *prng;
+    prng = g_new(OtPrngState, 1u);
+    prng->rand = g_rand_new();
+    return prng;
+}
+
+void ot_prng_release(OtPrngState *prng)
+{
+    g_rand_free(prng->rand);
+    g_free(prng);
+}
+
+uint32_t ot_prng_random_u32(OtPrngState *prng)
+{
+    return (uint32_t)g_rand_int(prng->rand);
+}
+
+void ot_prng_random_u32_array(OtPrngState *prng, uint32_t *array, size_t count)
+{
+    while (count--) {
+        *array++ = (uint32_t)g_rand_int(prng->rand);
+    }
+}
+
+void ot_prng_reseed(OtPrngState *prng, uint32_t seed)
+{
+    if (prng->rand) {
+        g_rand_free(prng->rand);
+    }
+
+    prng->rand = g_rand_new_with_seed((guint32)seed);
+}
+
+void ot_prng_reseed_array(OtPrngState *prng, const uint32_t *seed,
+                          size_t length)
+{
+    if (prng->rand) {
+        g_rand_free(prng->rand);
+    }
+
+    prng->rand = g_rand_new_with_seed_array((const guint32 *)seed, length);
+}
diff --git a/hw/opentitan/ot_pwrmgr.c b/hw/opentitan/ot_pwrmgr.c
new file mode 100644
index 0000000000000..03c95c94b048f
--- /dev/null
+++ b/hw/opentitan/ot_pwrmgr.c
@@ -0,0 +1,1159 @@
+/*
+ * QEMU OpenTitan Power Manager device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_clock_ctrl.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_pwrmgr.h"
+#include "hw/opentitan/ot_rstmgr.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+#define NUM_INT_RST_REQS   2u
+#define NUM_DEBUG_RST_REQS 1u
+#define NUM_SW_RST_REQ     1u
+#define NUM_ALERTS         1u
+#define RESET_MAIN_PWR_IDX 2u
+#define RESET_ESC_IDX      3u
+#define RESET_NDM_IDX      4u
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(WAKEUP, 0u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(CTRL_CFG_REGWEN, 0x10u)
+    FIELD(CTRL_CFG_REGWEN, EN, 0u, 1u)
+REG32(CONTROL, 0x14u)
+    FIELD(CONTROL, LOW_POWER_HINT, 0u, 1u)
+    FIELD(CONTROL, CORE_CLK_EN, 4u, 1u)
+    FIELD(CONTROL, IO_CLK_EN, 5u, 1u)
+    FIELD(CONTROL, USB_CLK_EN_LP, 6u, 1u)
+    FIELD(CONTROL, USB_CLK_EN_ACTIVE, 7u, 1u)
+    FIELD(CONTROL, MAIN_PD_N, 8u, 1u)
+REG32(CFG_CDC_SYNC, 0x18u)
+    FIELD(CFG_CDC_SYNC, SYNC, 0u, 1u)
+REG32(WAKEUP_EN_REGWEN, 0x1cu)
+    FIELD(WAKEUP_EN_REGWEN, EN, 0u, 1u)
+REG32(WAKEUP_EN, 0x20u)
+    /* note: wake up channel count depends on top */
+REG32(WAKE_STATUS, 0x24u)
+REG32(RESET_EN_REGWEN, 0x28u)
+    FIELD(RESET_EN_REGWEN, EN, 0u, 1u)
+REG32(RESET_EN, 0x2cu)
+REG32(RESET_STATUS, 0x30u)
+REG32(ESCALATE_RESET_STATUS, 0x34u)
+    FIELD(ESCALATE_RESET_STATUS, VAL, 0u, 1u)
+REG32(WAKE_INFO_CAPTURE_DIS, 0x38u)
+    FIELD(WAKE_INFO_CAPTURE_DIS, VAL, 0u, 1u)
+REG32(WAKE_INFO, 0x3cu)
+    /* note: wake info fields depend on top */
+REG32(FAULT_STATUS, 0x40u)
+    FIELD(FAULT_STATUS, REG_INTG_ERR, 0u, 1u)
+    FIELD(FAULT_STATUS, ESC_TIMEOUT, 1u, 1u)
+    FIELD(FAULT_STATUS, MAIN_PD_GLITCH, 2u, 1u)
+/* clang-format on */
+
+#define CDC_SYNC_PULSE_DURATION_NS 1000u /* 1us */
+
+#define PWRMGR_WAKEUP_MAX  ((unsigned)OT_PWRMGR_WAKEUP_COUNT)
+#define PWRMGR_RST_REQ_MAX 2u
+
+/* special exit error code to report escalation panic */
+#define EXIT_ESCALATION_PANIC 39
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_FAULT_STATUS)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CTRL_CFG_REGWEN),
+    REG_NAME_ENTRY(CONTROL),
+    REG_NAME_ENTRY(CFG_CDC_SYNC),
+    REG_NAME_ENTRY(WAKEUP_EN_REGWEN),
+    REG_NAME_ENTRY(WAKEUP_EN),
+    REG_NAME_ENTRY(WAKE_STATUS),
+    REG_NAME_ENTRY(RESET_EN_REGWEN),
+    REG_NAME_ENTRY(RESET_EN),
+    REG_NAME_ENTRY(RESET_STATUS),
+    REG_NAME_ENTRY(ESCALATE_RESET_STATUS),
+    REG_NAME_ENTRY(WAKE_INFO_CAPTURE_DIS),
+    REG_NAME_ENTRY(WAKE_INFO),
+    REG_NAME_ENTRY(FAULT_STATUS),
+};
+#undef REG_NAME_ENTRY
+
+typedef enum {
+    OT_PWRMGR_INIT_OTP,
+    OT_PWRMGR_INIT_LC_CTRL,
+    OT_PWRMGR_INIT_COUNT,
+} OtPwrMgrInit;
+
+typedef enum {
+    OT_PWR_FAST_ST_LOW_POWER,
+    OT_PWR_FAST_ST_ENABLE_CLOCKS,
+    OT_PWR_FAST_ST_RELEASE_LC_RST,
+    OT_PWR_FAST_ST_OTP_INIT,
+    OT_PWR_FAST_ST_LC_INIT,
+    OT_PWR_FAST_ST_STRAP,
+    OT_PWR_FAST_ST_ACK_PWR_UP,
+    OT_PWR_FAST_ST_ROM_CHECK_DONE,
+    OT_PWR_FAST_ST_ROM_CHECK_GOOD,
+    OT_PWR_FAST_ST_ACTIVE,
+    OT_PWR_FAST_ST_DIS_CLKS,
+    OT_PWR_FAST_ST_FALL_THROUGH,
+    OT_PWR_FAST_ST_NVM_IDLE_CHK,
+    OT_PWR_FAST_ST_LOW_POWER_PREP,
+    OT_PWR_FAST_ST_NVM_SHUT_DOWN, /* not used in DJ */
+    OT_PWR_FAST_ST_RESET_PREP,
+    OT_PWR_FAST_ST_RESET_WAIT,
+    OT_PWR_FAST_ST_REQ_PWR_DN,
+    OT_PWR_FAST_ST_INVALID,
+} OtPwrMgrFastState;
+
+typedef enum {
+    OT_PWR_SLOW_ST_RESET,
+    OT_PWR_SLOW_ST_LOW_POWER,
+    OT_PWR_SLOW_ST_MAIN_POWER_ON,
+    OT_PWR_SLOW_ST_PWR_CLAMP_OFF,
+    OT_PWR_SLOW_ST_CLOCKS_ON,
+    OT_PWR_SLOW_ST_REQ_PWR_UP,
+    OT_PWR_SLOW_ST_IDLE,
+    OT_PWR_SLOW_ST_ACK_PWR_DN,
+    OT_PWR_SLOW_ST_CLOCKS_OFF,
+    OT_PWR_SLOW_ST_PWR_CLAMP_ON,
+    OT_PWR_SLOW_ST_MAIN_POWER_OFF,
+    OT_PWR_SLOW_ST_INVALID,
+} OtPwrMgrSlowState;
+
+typedef struct {
+    bool good;
+    bool done;
+} OtPwrMgrRomStatus;
+
+typedef enum {
+    OT_PWRMGR_NO_DOMAIN,
+    OT_PWRMGR_SLOW_DOMAIN,
+    OT_PWRMGR_FAST_DOMAIN,
+} OtPwrMgrClockDomain;
+
+typedef struct {
+    char *name;
+} OtPwrMgrClock;
+
+typedef struct {
+    OtPwrMgrClockDomain domain;
+    int req;
+} OtPwrMgrResetReq;
+
+/*
+ * Registers in the slow clock domain which get synchronized on CDC sync
+ */
+typedef struct {
+    uint32_t reset_en;
+    uint32_t wakeup_en;
+    uint32_t control; /* for clock enablement */
+} OtPwrMgrSlowRegs;
+
+typedef union {
+    uint32_t bitmap;
+    struct {
+        uint8_t hw_reset:1; /* HW reset request */
+        uint8_t sw_reset:1; /* SW reset request */
+        uint8_t otp_done:1;
+        uint8_t lc_done:1;
+        uint8_t escalate:1; /* escalation from alert handler */
+        uint8_t holdon_fetch:1; /* custom extension */
+        /* clang-format off */
+        uint8_t rom_good:OT_PWRMGR_MAX_ROM_COUNT;
+        uint8_t rom_done:OT_PWRMGR_MAX_ROM_COUNT;
+        /* clang-format on */
+    };
+} OtPwrMgrEvents;
+
+static_assert(sizeof(OtPwrMgrEvents) == sizeof(uint32_t),
+              "Invalid OtPwrMgrEvents definition");
+static_assert(sizeof(OtPwrMgrBootStatus) == sizeof(int),
+              "Invalid OtPwrMgrBootStatus size");
+
+struct OtPwrMgrState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    QEMUTimer *cdc_sync;
+    QEMUBH *fsm_tick_bh;
+    IbexIRQ irq; /* wake from low power */
+    IbexIRQ alert;
+    IbexIRQ strap;
+    IbexIRQ cpu_enable;
+    IbexIRQ pwr_lc_req;
+    IbexIRQ pwr_otp_req;
+    IbexIRQ reset_req;
+    IbexIRQ boot_st;
+
+    OtPwrMgrFastState f_state;
+    OtPwrMgrSlowState s_state;
+    OtPwrMgrEvents fsm_events;
+    OtPwrMgrSlowRegs slow_regs;
+
+    uint32_t *regs;
+    OtPwrMgrResetReq reset_request;
+    OtPwrMgrBootStatus boot_status;
+    GList *clocks;
+
+    char *ot_id;
+    char *cfg_clocks;
+    DeviceState *clock_ctrl;
+    uint8_t num_rom;
+    uint8_t version;
+    bool main; /* main power manager (for machines w/ multiple PwrMgr) */
+    bool fetch_ctrl;
+};
+
+struct OtPwrMgrClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static const char *CFGSEP = ",";
+
+#define PWRMGR_NAME_ENTRY(_pre_, _name_) [_pre_##_##_name_] = stringify(_name_)
+
+#define FAST_ST_NAME_ENTRY(_name_) PWRMGR_NAME_ENTRY(OT_PWR_FAST_ST, _name_)
+/* clang-format off */
+static const char *FAST_ST_NAMES[] = {
+    FAST_ST_NAME_ENTRY(LOW_POWER),
+    FAST_ST_NAME_ENTRY(ENABLE_CLOCKS),
+    FAST_ST_NAME_ENTRY(RELEASE_LC_RST),
+    FAST_ST_NAME_ENTRY(OTP_INIT),
+    FAST_ST_NAME_ENTRY(LC_INIT),
+    FAST_ST_NAME_ENTRY(STRAP),
+    FAST_ST_NAME_ENTRY(ACK_PWR_UP),
+    FAST_ST_NAME_ENTRY(ROM_CHECK_DONE),
+    FAST_ST_NAME_ENTRY(ROM_CHECK_GOOD),
+    FAST_ST_NAME_ENTRY(ACTIVE),
+    FAST_ST_NAME_ENTRY(DIS_CLKS),
+    FAST_ST_NAME_ENTRY(FALL_THROUGH),
+    FAST_ST_NAME_ENTRY(NVM_IDLE_CHK),
+    FAST_ST_NAME_ENTRY(LOW_POWER_PREP),
+    FAST_ST_NAME_ENTRY(NVM_SHUT_DOWN),
+    FAST_ST_NAME_ENTRY(RESET_PREP),
+    FAST_ST_NAME_ENTRY(RESET_WAIT),
+    FAST_ST_NAME_ENTRY(REQ_PWR_DN),
+    FAST_ST_NAME_ENTRY(INVALID),
+};
+/* clang-format on */
+#undef FAST_ST_NAME_ENTRY
+#define FST_NAME(_st_) \
+    ((_st_) < ARRAY_SIZE(FAST_ST_NAMES) ? FAST_ST_NAMES[(_st_)] : "?")
+
+#define SLOW_ST_NAME_ENTRY(_name_) PWRMGR_NAME_ENTRY(OT_PWR_SLOW_ST, _name_)
+/* clang-format off */
+static const char *SLOW_ST_NAMES[] = {
+    SLOW_ST_NAME_ENTRY(RESET),
+    SLOW_ST_NAME_ENTRY(LOW_POWER),
+    SLOW_ST_NAME_ENTRY(MAIN_POWER_ON),
+    SLOW_ST_NAME_ENTRY(PWR_CLAMP_OFF),
+    SLOW_ST_NAME_ENTRY(CLOCKS_ON),
+    SLOW_ST_NAME_ENTRY(REQ_PWR_UP),
+    SLOW_ST_NAME_ENTRY(IDLE),
+    SLOW_ST_NAME_ENTRY(ACK_PWR_DN),
+    SLOW_ST_NAME_ENTRY(CLOCKS_OFF),
+    SLOW_ST_NAME_ENTRY(PWR_CLAMP_ON),
+    SLOW_ST_NAME_ENTRY(MAIN_POWER_OFF),
+    SLOW_ST_NAME_ENTRY(INVALID),
+};
+/* clang-format on */
+#undef SLOW_ST_NAME_ENTRY
+#define SST_NAME(_st_) \
+    ((_st_) < ARRAY_SIZE(SLOW_ST_NAMES) ? SLOW_ST_NAMES[(_st_)] : "?")
+
+typedef struct {
+    unsigned wakeup_count;
+    unsigned reset_count;
+    uint32_t reset_mask;
+    uint32_t control_mask;
+    uint32_t control_res_val; /* reset value for CONTROL regsisters */
+} OtPwrMgrConfig;
+
+typedef struct {
+    OtPwrMgrState *s;
+    bool enable;
+} OtPwrMgrClockConfig;
+
+/* clang-format off */
+static const OtPwrMgrConfig PWRMGR_CONFIG[OT_PWRMGR_VERSION_COUNT] = {
+    [OT_PWRMGR_VERSION_EG_1_0_0] = {
+        .wakeup_count = 6u,
+        .reset_count = 2u,
+        .reset_mask = 0x3u,
+        .control_mask = 0x1f1u,
+        .control_res_val = 0x180u, /* MAIN_PD_N | USB_CLK_EN_ACTIVE */
+    },
+    [OT_PWRMGR_VERSION_DJ] = {
+        .wakeup_count = 4u,
+        .reset_count = 2u,
+        .reset_mask = 0x3u,
+        .control_mask = 0x71u,
+        .control_res_val = 0x40u, /* MAIN_PD_N */
+    },
+};
+
+#define WAKE_INFO_REASONS_MASK(_s_) \
+    ((1u << (PWRMGR_CONFIG[(_s_)->version].wakeup_count)) - 1u)
+#define WAKE_INFO_FALL_THROUGH_MASK(_s_) \
+    (1u << (PWRMGR_CONFIG[(_s_)->version].wakeup_count))
+#define WAKE_INFO_ABORT_MASK_MASK(_s_) \
+    (1u << (PWRMGR_CONFIG[(_s_)->version].wakeup_count + 1u))
+#define WAKE_INFO_MASK(_s_) \
+    ((1u << (PWRMGR_CONFIG[(_s_)->version].wakeup_count + 2u)) - 1u)
+#define WAKEUP_MASK(_s_) WAKE_INFO_REASONS_MASK(_s_)
+#define CONTROL_MASK(_s_) (PWRMGR_CONFIG[(_s_)->version].control_mask)
+#define HW_RESET_WIDTH(_s_) \
+    ((PWRMGR_CONFIG[(_s_)->version].wakeup_count) + \
+     NUM_INT_RST_REQS + NUM_DEBUG_RST_REQS)
+#define RESET_SW_REQ_IDX(_s_) HW_RESET_WIDTH(_s_)
+
+static int
+PWRMGR_RESET_DISPATCH[OT_PWRMGR_VERSION_COUNT][PWRMGR_RST_REQ_MAX] = {
+    [OT_PWRMGR_VERSION_EG_1_0_0] = {
+        [0] = OT_RSTMGR_RESET_SYSCTRL,
+        [1] = OT_RSTMGR_RESET_AON_TIMER,
+    },
+    [OT_PWRMGR_VERSION_DJ] = {
+        [0] = OT_RSTMGR_RESET_AON_TIMER,
+        [1] = OT_RSTMGR_RESET_SOC_PROXY,
+    },
+};
+
+static const char *
+PWRMGR_WAKEUP_NAMES[OT_PWRMGR_VERSION_COUNT][PWRMGR_WAKEUP_MAX] = {
+    [OT_PWRMGR_VERSION_EG_1_0_0] = {
+        [0] = "SYSRST",
+        [1] = "ADC_CTRL",
+        [2] = "PINMUX",
+        [3] = "USBDEV",
+        [4] = "AON_TIMER",
+        [5] = "SENSOR",
+    },
+    [OT_PWRMGR_VERSION_DJ] = {
+        [0] = "PINMUX",
+        [1] = "USBDEV",
+        [2] = "AON_TIMER",
+        [3] = "SENSOR",
+        [4] = "SOC_PROXY_INT",
+        [5] = "SOC_PROXY_EXT",
+    },
+};
+
+static const char *
+PWRMGR_RST_NAMES[OT_PWRMGR_VERSION_COUNT][PWRMGR_RST_REQ_MAX] = {
+    [OT_PWRMGR_VERSION_EG_1_0_0] = {
+        [0] = "SYSRST",
+        [1] = "AON_TIMER",
+    },
+    [OT_PWRMGR_VERSION_DJ] = {
+        [0] = "AON_TIMER",
+        [1] = "SOC_PROXY",
+    }
+};
+/* clang-format on */
+
+#define WAKEUP_NAME(_s_, _w_) \
+    ((_w_) < PWRMGR_CONFIG[(_s_)->version].wakeup_count ? \
+         PWRMGR_WAKEUP_NAMES[(_s_)->version][(_w_)] : \
+         "?")
+#define RST_NAME(_s_, _r_) \
+    ((_r_) < PWRMGR_CONFIG[(_s_)->version].reset_count ? \
+         PWRMGR_RST_NAMES[(_s_)->version][(_r_)] : \
+         "?")
+
+#undef PWRMGR_NAME_ENTRY
+
+#define PWR_CHANGE_FAST_STATE(_s_, _st_) \
+    ot_pwrmgr_change_fast_state_line(_s_, OT_PWR_FAST_ST_##_st_, __LINE__)
+
+#define PWR_CHANGE_SLOW_STATE(_s_, _st_) \
+    ot_pwrmgr_change_slow_state_line(_s_, OT_PWR_SLOW_ST_##_st_, __LINE__)
+
+static void ot_pwrmgr_change_fast_state_line(OtPwrMgrState *s,
+                                             OtPwrMgrFastState state, int line)
+{
+    trace_ot_pwrmgr_change_state(s->ot_id, line, "fast", FST_NAME(s->f_state),
+                                 s->f_state, FST_NAME(state), state);
+
+    s->f_state = state;
+}
+
+static void ot_pwrmgr_change_slow_state_line(OtPwrMgrState *s,
+                                             OtPwrMgrSlowState state, int line)
+{
+    trace_ot_pwrmgr_change_state(s->ot_id, line, "slow", SST_NAME(s->s_state),
+                                 s->s_state, SST_NAME(state), state);
+
+    s->s_state = state;
+}
+
+static void ot_pwrmgr_update_irq(OtPwrMgrState *s)
+{
+    uint32_t level = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+
+    ibex_irq_set(&s->irq, (int)(bool)level);
+}
+
+#define ot_pwrmgr_schedule_fsm(_s_) \
+    ot_pwrmgr_xschedule_fsm(_s_, __func__, __LINE__)
+
+static void ot_pwrmgr_xschedule_fsm(OtPwrMgrState *s, const char *func,
+                                    int line)
+{
+    trace_ot_pwrmgr_schedule_fsm(s->ot_id, func, line);
+    qemu_bh_schedule(s->fsm_tick_bh);
+}
+
+static void ot_pwrmgr_sync_slow_regs(OtPwrMgrState *s)
+{
+    s->slow_regs.reset_en = s->regs[R_RESET_EN];
+    s->slow_regs.wakeup_en = s->regs[R_WAKEUP_EN];
+    s->slow_regs.control = s->regs[R_CONTROL];
+}
+
+static void ot_pwrmgr_cdc_sync(void *opaque)
+{
+    OtPwrMgrState *s = opaque;
+
+    trace_ot_pwrmgr_cdc_sync(s->ot_id);
+
+    ot_pwrmgr_sync_slow_regs(s);
+
+    s->regs[R_CFG_CDC_SYNC] &= ~R_CFG_CDC_SYNC_SYNC_MASK;
+}
+
+static void ot_pwrmgr_rom_good(void *opaque, int irq, int level)
+{
+    OtPwrMgrState *s = opaque;
+
+    g_assert((unsigned)irq < s->num_rom);
+
+    trace_ot_pwrmgr_rom(s->ot_id, irq, "good", level);
+
+    if (level) {
+        s->fsm_events.rom_good |= 1u << irq;
+        ot_pwrmgr_schedule_fsm(s);
+    }
+}
+
+static void ot_pwrmgr_rom_done(void *opaque, int irq, int level)
+{
+    OtPwrMgrState *s = opaque;
+
+    g_assert((unsigned)irq < s->num_rom);
+
+    trace_ot_pwrmgr_rom(s->ot_id, irq, "done", level);
+
+    if (level) {
+        s->fsm_events.rom_done |= 1u << irq;
+        ot_pwrmgr_schedule_fsm(s);
+    }
+}
+
+static void ot_pwrmgr_wkup(void *opaque, int irq, int level)
+{
+    OtPwrMgrState *s = opaque;
+    unsigned src = (unsigned)irq;
+
+    assert(src < PWRMGR_WAKEUP_MAX);
+
+    trace_ot_pwrmgr_wkup(s->ot_id, WAKEUP_NAME(s, src), src, (bool)level);
+}
+
+static void ot_pwrmgr_clock_enable(gpointer data, gpointer user_data)
+{
+    OtPwrMgrClock *clk = data;
+    OtPwrMgrClockConfig *cfg = user_data;
+    OtClockCtrlIfClass *oc = OT_CLOCK_CTRL_IF_GET_CLASS(cfg->s->clock_ctrl);
+    OtClockCtrlIf *oi = OT_CLOCK_CTRL_IF(cfg->s->clock_ctrl);
+    trace_ot_pwrmgr_clock_enable(cfg->s->ot_id, clk->name, cfg->enable);
+    oc->clock_enable(oi, clk->name, cfg->enable);
+}
+
+static void ot_pwrmgr_clock_enable_all(OtPwrMgrState *s, bool enable)
+{
+    OtPwrMgrClockConfig cfg = {
+        .s = s,
+        .enable = enable,
+    };
+
+    g_list_foreach(s->clocks, &ot_pwrmgr_clock_enable, &cfg);
+}
+
+static void ot_pwrmgr_rst_req(void *opaque, int irq, int level)
+{
+    OtPwrMgrState *s = opaque;
+
+    unsigned src = (unsigned)irq;
+    g_assert(src < PWRMGR_CONFIG[s->version].reset_count);
+
+    uint32_t rstbit = 1u << src; /* rst_req are stored in the LSBs */
+
+    if (level) {
+        trace_ot_pwrmgr_rst_req(s->ot_id, RST_NAME(s, src), src);
+        uint32_t rstmask = PWRMGR_CONFIG[s->version].reset_mask;
+
+        /* if HW reset is maskable and not HW reset is not enabled */
+        if ((rstbit & rstmask) && !(s->slow_regs.reset_en & rstbit)) {
+            bool cdc_sync = s->slow_regs.reset_en == s->regs[R_RESET_EN];
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: HW reset #%u not enabled 0x%x 0x%x%s\n",
+                          __func__, s->ot_id, src, s->regs[R_RESET_EN], rstbit,
+                          cdc_sync ? "" : ": check CFG_CDC_SYNC");
+            return;
+        }
+
+        if (s->regs[R_RESET_STATUS]) {
+            /* do nothing if a reset is already in progress */
+            /* TODO: is it true for HW vs. SW request ?*/
+            trace_ot_pwrmgr_ignore_req(s->ot_id, "reset on-going");
+            return;
+        }
+        s->regs[R_RESET_STATUS] |= rstbit;
+
+        g_assert(s->reset_request.domain == OT_PWRMGR_NO_DOMAIN);
+
+        s->reset_request.domain = OT_PWRMGR_SLOW_DOMAIN;
+
+        int req = PWRMGR_RESET_DISPATCH[s->version][src];
+        if (req < 0) {
+            /* not yet implemented */
+            g_assert_not_reached();
+        }
+        s->reset_request.req = req;
+
+        trace_ot_pwrmgr_reset_req(s->ot_id, "scheduling reset", src);
+
+        s->fsm_events.hw_reset = true;
+        ot_pwrmgr_schedule_fsm(s);
+    }
+}
+
+static void ot_pwrmgr_sw_rst_req(void *opaque, int irq, int level)
+{
+    OtPwrMgrState *s = opaque;
+
+    unsigned src = (unsigned)irq;
+    g_assert(src < NUM_SW_RST_REQ);
+
+    uint32_t rstbit = 1u << (RESET_SW_REQ_IDX(s) + src);
+
+    if (level) {
+        trace_ot_pwrmgr_rst_req(s->ot_id, "SW", src);
+
+        if (s->regs[R_RESET_STATUS]) {
+            /* do nothing if a reset is already in progress */
+            trace_ot_pwrmgr_ignore_req(s->ot_id, "reset on-going");
+            return;
+        }
+
+        s->regs[R_RESET_STATUS] |= rstbit;
+
+        g_assert(s->reset_request.domain == OT_PWRMGR_NO_DOMAIN);
+
+        s->reset_request.req = OT_RSTMGR_RESET_SW;
+        s->reset_request.domain = OT_PWRMGR_FAST_DOMAIN;
+
+        trace_ot_pwrmgr_reset_req(s->ot_id, "scheduling SW reset", 0);
+
+        s->fsm_events.sw_reset = true;
+        ot_pwrmgr_schedule_fsm(s);
+    }
+}
+
+
+static void ot_pwrmgr_slow_fsm_tick(OtPwrMgrState *s)
+{
+    /* fast forward to IDLE slow FSM state for now */
+    if (s->s_state == OT_PWR_SLOW_ST_RESET) {
+        PWR_CHANGE_SLOW_STATE(s, IDLE);
+    }
+}
+
+static void ot_pwrmgr_fast_fsm_tick(OtPwrMgrState *s)
+{
+    if (s->s_state != OT_PWR_SLOW_ST_IDLE) {
+        qemu_log_mask(LOG_UNIMP, "%s: %s: slow FSM not supported\n", __func__,
+                      s->ot_id);
+        return;
+    }
+
+    if (s->fsm_events.escalate) {
+        PWR_CHANGE_FAST_STATE(s, REQ_PWR_DN);
+        trace_ot_pwrmgr_shutdown(s->ot_id, s->main);
+        if (s->main) {
+            qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_GUEST_PANIC,
+                                                   EXIT_ESCALATION_PANIC);
+        }
+    }
+
+    switch (s->f_state) {
+    case OT_PWR_FAST_ST_LOW_POWER:
+        PWR_CHANGE_FAST_STATE(s, ENABLE_CLOCKS);
+        /* shortcut: real HW use a much more complex FSM to enable clocks */
+        ot_pwrmgr_clock_enable_all(s, true);
+        break;
+    case OT_PWR_FAST_ST_ENABLE_CLOCKS:
+        s->boot_status.main_clk_status = 1u;
+        s->boot_status.io_clk_status = 1u;
+        ibex_irq_set(&s->boot_st, s->boot_status.i32);
+        PWR_CHANGE_FAST_STATE(s, RELEASE_LC_RST);
+        /*
+         * TODO: need to release ROM controllers from reset here to emulate
+         * they are clocked and start to verify their contents.
+         */
+        break;
+    case OT_PWR_FAST_ST_RELEASE_LC_RST:
+        PWR_CHANGE_FAST_STATE(s, OTP_INIT);
+        ibex_irq_set(&s->pwr_otp_req, (int)true);
+        break;
+    case OT_PWR_FAST_ST_OTP_INIT:
+        if (s->fsm_events.otp_done) {
+            /* release the request signal */
+            ibex_irq_set(&s->pwr_otp_req, (int)false);
+            s->boot_status.otp_done = true;
+            ibex_irq_set(&s->boot_st, s->boot_status.i32);
+            PWR_CHANGE_FAST_STATE(s, LC_INIT);
+            ibex_irq_set(&s->pwr_lc_req, (int)true);
+        }
+        break;
+    case OT_PWR_FAST_ST_LC_INIT:
+        if (s->fsm_events.lc_done) {
+            /* release the request signal */
+            ibex_irq_set(&s->pwr_lc_req, (int)false);
+            s->boot_status.lc_done = true;
+            ibex_irq_set(&s->boot_st, s->boot_status.i32);
+            PWR_CHANGE_FAST_STATE(s, ACK_PWR_UP);
+        }
+        break;
+    case OT_PWR_FAST_ST_ACK_PWR_UP:
+        PWR_CHANGE_FAST_STATE(s, STRAP);
+        break;
+    case OT_PWR_FAST_ST_STRAP:
+        ibex_irq_set(&s->strap, (int)true);
+        s->boot_status.strap_sampled = true;
+        ibex_irq_set(&s->boot_st, s->boot_status.i32);
+        PWR_CHANGE_FAST_STATE(s, ROM_CHECK_DONE);
+        break;
+    case OT_PWR_FAST_ST_ROM_CHECK_DONE:
+        ibex_irq_set(&s->strap, (int)false);
+        s->boot_status.rom_done = s->fsm_events.rom_done;
+        ibex_irq_set(&s->boot_st, s->boot_status.i32);
+        if (s->fsm_events.rom_done == (1u << s->num_rom) - 1u) {
+            PWR_CHANGE_FAST_STATE(s, ROM_CHECK_GOOD);
+        }
+        break;
+    case OT_PWR_FAST_ST_ROM_CHECK_GOOD:
+        s->boot_status.rom_good = s->fsm_events.rom_good;
+        ibex_irq_set(&s->boot_st, s->boot_status.i32);
+        if ((s->fsm_events.rom_good == (1u << s->num_rom) - 1u) &&
+            !s->fsm_events.holdon_fetch) {
+            PWR_CHANGE_FAST_STATE(s, ACTIVE);
+        }
+        break;
+    case OT_PWR_FAST_ST_ACTIVE:
+        if (!s->regs[R_RESET_STATUS]) {
+            ibex_irq_set(&s->cpu_enable, (int)true);
+            s->boot_status.cpu_fetch_en = true;
+            ibex_irq_set(&s->boot_st, s->boot_status.i32);
+        } else {
+            ibex_irq_set(&s->cpu_enable, (int)false);
+            s->boot_status.cpu_fetch_en = false;
+            ibex_irq_set(&s->boot_st, s->boot_status.i32);
+            PWR_CHANGE_FAST_STATE(s, DIS_CLKS);
+        }
+        break;
+    case OT_PWR_FAST_ST_DIS_CLKS:
+        s->boot_status.main_clk_status = 0u;
+        s->boot_status.io_clk_status = 0u;
+        ibex_irq_set(&s->boot_st, s->boot_status.i32);
+        PWR_CHANGE_FAST_STATE(s, RESET_PREP);
+        break;
+    case OT_PWR_FAST_ST_FALL_THROUGH:
+    case OT_PWR_FAST_ST_NVM_IDLE_CHK:
+    case OT_PWR_FAST_ST_LOW_POWER_PREP:
+    case OT_PWR_FAST_ST_NVM_SHUT_DOWN:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: %s: low power modes are not implemented\n", __func__,
+                      s->ot_id);
+        /* fallthrough */
+    case OT_PWR_FAST_ST_RESET_PREP:
+        PWR_CHANGE_FAST_STATE(s, RESET_WAIT);
+        ibex_irq_set(&s->reset_req,
+                     OT_RSTMGR_RESET_REQUEST(s->reset_request.domain,
+                                             s->reset_request.req));
+        s->reset_request.domain = OT_PWRMGR_NO_DOMAIN;
+        break;
+    /* NOLINTNEXTLINE */
+    case OT_PWR_FAST_ST_RESET_WAIT:
+        /* wait here for QEMU to reset the Power Manager */
+        break;
+    case OT_PWR_FAST_ST_REQ_PWR_DN:
+    case OT_PWR_FAST_ST_INVALID:
+        break;
+    }
+}
+
+static void ot_pwrmgr_fsm_tick(void *opaque)
+{
+    OtPwrMgrState *s = opaque;
+
+    ot_pwrmgr_slow_fsm_tick(s);
+
+    OtPwrMgrFastState f_state = s->f_state;
+    ot_pwrmgr_fast_fsm_tick(s);
+    if (f_state != s->f_state) {
+        /* schedule FSM update once more if its state has changed */
+        ot_pwrmgr_schedule_fsm(s);
+    } else {
+        /* otherwise, go idle and wait for an external event */
+        trace_ot_pwrmgr_go_idle(s->ot_id, FST_NAME(s->f_state));
+    }
+}
+
+/*
+ * Input lines
+ */
+
+static void ot_pwrmgr_escalate_rx(void *opaque, int n, int level)
+{
+    OtPwrMgrState *s = opaque;
+
+    g_assert(n == 0);
+
+    trace_ot_pwrmgr_escalate_rx(s->ot_id, (bool)level);
+
+    if (level) {
+        s->regs[R_ESCALATE_RESET_STATUS] |= R_ESCALATE_RESET_STATUS_VAL_MASK;
+        s->fsm_events.escalate = true;
+        ot_pwrmgr_schedule_fsm(s);
+    }
+}
+
+static void ot_pwrmgr_pwr_lc_rsp(void *opaque, int n, int level)
+{
+    OtPwrMgrState *s = opaque;
+
+    g_assert(n == 0);
+
+    if (level) {
+        s->fsm_events.lc_done = true;
+        ot_pwrmgr_schedule_fsm(s);
+    }
+}
+
+static void ot_pwrmgr_pwr_otp_rsp(void *opaque, int n, int level)
+{
+    OtPwrMgrState *s = opaque;
+
+    g_assert(n == 0);
+
+    if (level) {
+        s->fsm_events.otp_done = true;
+        ot_pwrmgr_schedule_fsm(s);
+    }
+}
+
+static void ot_pwrmgr_holdon_fetch(void *opaque, int n, int level)
+{
+    OtPwrMgrState *s = opaque;
+
+    g_assert(n == 0);
+
+    s->fsm_events.holdon_fetch = (bool)level;
+    ot_pwrmgr_schedule_fsm(s);
+}
+
+static void ot_pwrmgr_parse_clocks(OtPwrMgrState *s, Error **errp)
+{
+    if (!s->cfg_clocks) {
+        error_setg(errp, "%s: %s: clocks config not defined", __func__,
+                   s->ot_id);
+        return;
+    }
+
+    for (char *clkbrk, *clkname = strtok_r(s->cfg_clocks, CFGSEP, &clkbrk);
+         clkname; clkname = strtok_r(NULL, CFGSEP, &clkbrk)) {
+        OtPwrMgrClock *clk = g_new0(OtPwrMgrClock, 1u);
+        clk->name = strdup(clkname);
+        s->clocks = g_list_append(s->clocks, clk);
+    }
+}
+
+static uint64_t ot_pwrmgr_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtPwrMgrState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_CTRL_CFG_REGWEN:
+    case R_CONTROL:
+    case R_CFG_CDC_SYNC:
+    case R_WAKEUP_EN_REGWEN:
+    case R_WAKEUP_EN:
+    case R_WAKE_STATUS:
+    case R_RESET_EN_REGWEN:
+    case R_RESET_EN:
+    case R_ESCALATE_RESET_STATUS:
+    case R_WAKE_INFO_CAPTURE_DIS:
+    case R_WAKE_INFO:
+    case R_FAULT_STATUS:
+        val32 = s->regs[reg];
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    case R_RESET_STATUS:
+        val32 = s->regs[reg] & PWRMGR_CONFIG[s->version].reset_mask;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_pwrmgr_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                                pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_pwrmgr_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                 unsigned size)
+{
+    OtPwrMgrState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_pwrmgr_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                             pc);
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= WAKEUP_MASK(s);
+        s->regs[R_INTR_STATE] &= ~val32; /* RW1C */
+        ot_pwrmgr_update_irq(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= WAKEUP_MASK(s);
+        s->regs[R_INTR_ENABLE] = val32;
+        ot_pwrmgr_update_irq(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= WAKEUP_MASK(s);
+        s->regs[R_INTR_STATE] |= val32;
+        ot_pwrmgr_update_irq(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        s->regs[reg] = val32;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    case R_CONTROL:
+        /* TODO: clear LOW_POWER_HINT on next WFI? */
+        val32 &= CONTROL_MASK(s);
+        s->regs[reg] = val32;
+        break;
+    case R_CFG_CDC_SYNC:
+        val32 &= R_CFG_CDC_SYNC_SYNC_MASK;
+        s->regs[reg] |= val32; /* not described as RW1S, but looks like it */
+        if (val32) {
+            /*
+             * schedule CDC synchronization;
+             * SW guest should poll this register till it is released.
+             */
+            timer_mod(s->cdc_sync, qemu_clock_get_ns(OT_VIRTUAL_CLOCK) +
+                                       CDC_SYNC_PULSE_DURATION_NS);
+        }
+        break;
+    case R_WAKEUP_EN_REGWEN:
+        val32 &= R_WAKEUP_EN_REGWEN_EN_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_WAKEUP_EN:
+        if (s->regs[R_WAKEUP_EN_REGWEN] & R_WAKEUP_EN_REGWEN_EN_MASK) {
+            val32 &= WAKEUP_MASK(s);
+            s->regs[reg] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ REGWEN\n",
+                          __func__, s->ot_id, REG_NAME(reg));
+        }
+        break;
+    case R_RESET_EN_REGWEN:
+        val32 &= R_RESET_EN_REGWEN_EN_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_RESET_EN:
+        if (s->regs[R_RESET_EN_REGWEN] & R_RESET_EN_REGWEN_EN_MASK) {
+            val32 &= PWRMGR_CONFIG[s->version].reset_mask;
+            s->regs[reg] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ REGWEN\n",
+                          __func__, s->ot_id, REG_NAME(reg));
+        }
+        break;
+    case R_WAKE_INFO_CAPTURE_DIS:
+        val32 &= R_WAKE_INFO_CAPTURE_DIS_VAL_MASK;
+        s->regs[reg] = val32;
+        break;
+    case R_WAKE_INFO:
+        val32 &= WAKE_INFO_MASK(s);
+        s->regs[reg] &= ~val32; /* RW1C */
+        break;
+    case R_CTRL_CFG_REGWEN:
+    case R_WAKE_STATUS:
+    case R_RESET_STATUS:
+    case R_ESCALATE_RESET_STATUS:
+    case R_FAULT_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static const Property ot_pwrmgr_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtPwrMgrState, ot_id),
+    DEFINE_PROP_STRING("clocks", OtPwrMgrState, cfg_clocks),
+    DEFINE_PROP_LINK("clock-ctrl", OtPwrMgrState, clock_ctrl, TYPE_DEVICE,
+                     DeviceState *),
+    DEFINE_PROP_UINT8("num-rom", OtPwrMgrState, num_rom, 0),
+    DEFINE_PROP_UINT8("version", OtPwrMgrState, version, UINT8_MAX),
+    DEFINE_PROP_BOOL("fetch-ctrl", OtPwrMgrState, fetch_ctrl, false),
+    DEFINE_PROP_BOOL("main", OtPwrMgrState, main, true),
+};
+
+static const MemoryRegionOps ot_pwrmgr_regs_ops = {
+    .read = &ot_pwrmgr_regs_read,
+    .write = &ot_pwrmgr_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_pwrmgr_reset_enter(Object *obj, ResetType type)
+{
+    OtPwrMgrClass *c = OT_PWRMGR_GET_CLASS(obj);
+    OtPwrMgrState *s = OT_PWRMGR(obj);
+
+    /* sanity checks for platform reset count and mask */
+    g_assert(PWRMGR_CONFIG[s->version].reset_count <= PWRMGR_RST_REQ_MAX);
+    g_assert(ctpop32(PWRMGR_CONFIG[s->version].reset_mask + 1u) == 1);
+    g_assert(PWRMGR_CONFIG[s->version].reset_mask <
+             (1u << PWRMGR_CONFIG[s->version].reset_count));
+
+    trace_ot_pwrmgr_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->cdc_sync);
+    memset(s->regs, 0, REGS_SIZE);
+
+    s->regs[R_CTRL_CFG_REGWEN] = 0x1u;
+    s->regs[R_CONTROL] = PWRMGR_CONFIG[s->version].control_res_val;
+    s->regs[R_WAKEUP_EN_REGWEN] = 0x1u;
+    s->regs[R_RESET_EN_REGWEN] = 0x1u;
+    s->fsm_events.bitmap = 0;
+    s->fsm_events.holdon_fetch = s->fetch_ctrl;
+    s->boot_status.i32 = 0;
+    s->boot_status.rom_mask = (1u << s->num_rom) - 1u;
+    ot_pwrmgr_sync_slow_regs(s);
+
+    PWR_CHANGE_FAST_STATE(s, LOW_POWER);
+    PWR_CHANGE_SLOW_STATE(s, RESET);
+
+    ot_pwrmgr_update_irq(s);
+    ibex_irq_set(&s->strap, 0);
+    ibex_irq_set(&s->cpu_enable, 0);
+    ibex_irq_set(&s->pwr_otp_req, 0);
+    ibex_irq_set(&s->pwr_lc_req, 0);
+    ibex_irq_set(&s->alert, 0);
+    ibex_irq_set(&s->reset_req, 0);
+    ibex_irq_set(&s->boot_st, s->boot_status.i32);
+}
+
+static void ot_pwrmgr_reset_exit(Object *obj, ResetType type)
+{
+    OtPwrMgrClass *c = OT_PWRMGR_GET_CLASS(obj);
+    OtPwrMgrState *s = OT_PWRMGR(obj);
+
+    trace_ot_pwrmgr_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    qemu_bh_cancel(s->fsm_tick_bh);
+
+    ot_pwrmgr_schedule_fsm(s);
+}
+
+static void ot_pwrmgr_realize(DeviceState *dev, Error **errp)
+{
+    OtPwrMgrState *s = OT_PWRMGR(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->version < OT_PWRMGR_VERSION_COUNT);
+    g_assert(s->clock_ctrl);
+    OBJECT_CHECK(OtClockCtrlIf, s->clock_ctrl, TYPE_OT_CLOCK_CTRL_IF);
+
+    qdev_init_gpio_in_named(dev, &ot_pwrmgr_rst_req, OT_PWRMGR_RST,
+                            (int)PWRMGR_CONFIG[s->version].reset_count);
+
+    if (s->num_rom) {
+        if (s->num_rom > OT_PWRMGR_MAX_ROM_COUNT) {
+            error_setg(&error_fatal, "%s: %s: too many ROMs\n", __func__,
+                       s->ot_id);
+            g_assert_not_reached();
+        }
+        qdev_init_gpio_in_named(dev, &ot_pwrmgr_rom_good, OT_PWRMGR_ROM_GOOD,
+                                s->num_rom);
+        qdev_init_gpio_in_named(dev, &ot_pwrmgr_rom_done, OT_PWRMGR_ROM_DONE,
+                                s->num_rom);
+    }
+
+    if (s->fetch_ctrl) {
+        qdev_init_gpio_in_named(dev, &ot_pwrmgr_holdon_fetch,
+                                OT_PWRMGR_HOLDON_FETCH, 1u);
+    }
+
+    ot_pwrmgr_parse_clocks(s, &error_fatal);
+}
+
+static void ot_pwrmgr_init(Object *obj)
+{
+    OtPwrMgrState *s = OT_PWRMGR(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_pwrmgr_regs_ops, s, TYPE_OT_PWRMGR,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+    ibex_sysbus_init_irq(obj, &s->irq);
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+    ibex_qdev_init_irq(obj, &s->pwr_lc_req, OT_PWRMGR_LC_REQ);
+    ibex_qdev_init_irq(obj, &s->pwr_otp_req, OT_PWRMGR_OTP_REQ);
+    ibex_qdev_init_irq(obj, &s->cpu_enable, OT_PWRMGR_CPU_EN);
+    ibex_qdev_init_irq(obj, &s->strap, OT_PWRMGR_STRAP);
+    ibex_qdev_init_irq(obj, &s->reset_req, OT_PWRMGR_RST_REQ);
+    ibex_qdev_init_irq(obj, &s->boot_st, OT_PWRMGR_BOOT_STATUS);
+
+    s->cdc_sync = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_pwrmgr_cdc_sync, s);
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_pwrmgr_wkup, OT_PWRMGR_WKUP,
+                            PWRMGR_WAKEUP_MAX);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_pwrmgr_sw_rst_req,
+                            OT_PWRMGR_SW_RST, NUM_SW_RST_REQ);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_pwrmgr_pwr_lc_rsp,
+                            OT_PWRMGR_LC_RSP, 1);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_pwrmgr_pwr_otp_rsp,
+                            OT_PWRMGR_OTP_RSP, 1);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_pwrmgr_escalate_rx,
+                            OT_ALERT_ESCALATE, 1);
+
+    s->fsm_tick_bh = qemu_bh_new(&ot_pwrmgr_fsm_tick, s);
+}
+
+static void ot_pwrmgr_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_pwrmgr_realize;
+    device_class_set_props(dc, ot_pwrmgr_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(dc);
+    OtPwrMgrClass *pc = OT_PWRMGR_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_pwrmgr_reset_enter, NULL,
+                                       &ot_pwrmgr_reset_exit,
+                                       &pc->parent_phases);
+}
+
+static const TypeInfo ot_pwrmgr_info = {
+    .name = TYPE_OT_PWRMGR,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtPwrMgrState),
+    .instance_init = &ot_pwrmgr_init,
+    .class_init = &ot_pwrmgr_class_init,
+    .class_size = sizeof(OtPwrMgrClass)
+};
+
+static void ot_pwrmgr_register_types(void)
+{
+    type_register_static(&ot_pwrmgr_info);
+}
+
+type_init(ot_pwrmgr_register_types);
diff --git a/hw/opentitan/ot_rom_ctrl.c b/hw/opentitan/ot_rom_ctrl.c
new file mode 100644
index 0000000000000..1b7af912042eb
--- /dev/null
+++ b/hw/opentitan/ot_rom_ctrl.c
@@ -0,0 +1,1321 @@
+/*
+ * QEMU OpenTitan ROM controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Notes:
+ *  - KeyMgr interface (to send digest to Key Manager) is not yet supported
+ *  - Unscrambling & ECC are performed at boot time when a VMEM or HEX file
+ *    is loaded, not when the data are fetched from the system bus as on real
+ *    HW, for execution performance reason. Moreover any ECC unrecoverable error
+ *    discards the whole ROM content, whereas the real HW reports TL-UL error on
+ *    a per-address basis. As any recoverable or unrecoverable error leads to an
+ *    invalid digest and the ROM reporting an error to the PwrMfr and preventing
+ *    execution, this should not be a real issue for emulation.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "qemu/log.h"
+#include "qemu/memalign.h"
+#include "qapi/error.h"
+#include "elf.h"
+#include "hw/core/rust_demangle.h"
+#include "hw/loader.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_kmac.h"
+#include "hw/opentitan/ot_prince.h"
+#include "hw/opentitan/ot_rom_ctrl.h"
+#include "hw/opentitan/ot_rom_ctrl_img.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+#define PARAM_NUM_ALERTS 1u
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x0u)
+    FIELD(ALERT_TEST, FATAL_ERROR, 0u, 1u)
+REG32(FATAL_ALERT_CAUSE, 0x4u)
+    FIELD(FATAL_ALERT_CAUSE, CHECKER_ERROR, 0u, 1u)
+    FIELD(FATAL_ALERT_CAUSE, INTEGRITY_ERROR, 1u, 1u)
+REG32(DIGEST_0, 0x8u)
+REG32(DIGEST_1, 0xcu)
+REG32(DIGEST_2, 0x10u)
+REG32(DIGEST_3, 0x14u)
+REG32(DIGEST_4, 0x18u)
+REG32(DIGEST_5, 0x1cu)
+REG32(DIGEST_6, 0x20u)
+REG32(DIGEST_7, 0x24u)
+REG32(EXP_DIGEST_0, 0x28u)
+REG32(EXP_DIGEST_1, 0x2cu)
+REG32(EXP_DIGEST_2, 0x30u)
+REG32(EXP_DIGEST_3, 0x34u)
+REG32(EXP_DIGEST_4, 0x38u)
+REG32(EXP_DIGEST_5, 0x3cu)
+REG32(EXP_DIGEST_6, 0x40u)
+REG32(EXP_DIGEST_7, 0x44u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_EXP_DIGEST_7)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(ALERT_TEST),   REG_NAME_ENTRY(FATAL_ALERT_CAUSE),
+    REG_NAME_ENTRY(DIGEST_0),     REG_NAME_ENTRY(DIGEST_1),
+    REG_NAME_ENTRY(DIGEST_2),     REG_NAME_ENTRY(DIGEST_3),
+    REG_NAME_ENTRY(DIGEST_4),     REG_NAME_ENTRY(DIGEST_5),
+    REG_NAME_ENTRY(DIGEST_6),     REG_NAME_ENTRY(DIGEST_7),
+    REG_NAME_ENTRY(EXP_DIGEST_0), REG_NAME_ENTRY(EXP_DIGEST_1),
+    REG_NAME_ENTRY(EXP_DIGEST_2), REG_NAME_ENTRY(EXP_DIGEST_3),
+    REG_NAME_ENTRY(EXP_DIGEST_4), REG_NAME_ENTRY(EXP_DIGEST_5),
+    REG_NAME_ENTRY(EXP_DIGEST_6), REG_NAME_ENTRY(EXP_DIGEST_7),
+};
+#undef REG_NAME_ENTRY
+
+#define OT_ROM_CTRL_NUM_ADDR_SUBST_PERM_ROUNDS 2u
+#define OT_ROM_CTRL_NUM_DATA_SUBST_PERM_ROUNDS 2u
+#define OT_ROM_CTRL_NUM_PRINCE_HALF_ROUNDS     3u
+
+#define OT_ROM_CTRL_DATA_BITS  (sizeof(uint32_t) * 8u)
+#define OT_ROM_CTRL_ECC_BITS   7u
+#define OT_ROM_CTRL_WORD_BITS  (OT_ROM_CTRL_DATA_BITS + OT_ROM_CTRL_ECC_BITS)
+#define OT_ROM_CTRL_WORD_BYTES ((OT_ROM_CTRL_WORD_BITS + 7u) / 8u)
+
+#define ROM_DIGEST_WORDS (OT_ROM_DIGEST_BYTES / sizeof(uint32_t))
+
+#define OT_ROM_CTRL_HEXSTR_SIZE (OT_ROM_DIGEST_BYTES * 2u + 2u)
+
+/* clang-format off */
+static const uint8_t SBOX4[16u] = {
+    12u, 5u, 6u, 11u, 9u, 0u, 10u, 13u, 3u, 14u, 15u, 8u, 4u, 7u, 1u, 2u
+};
+
+static const uint64_t INV_HSIAO[7u] = {
+    0x012606bd25ull,
+    0x02deba8050ull,
+    0x04413d89aaull,
+    0x0831234ed1ull,
+    0x10c2c1323bull,
+    0x202dcc624cull,
+    0x4098505586ull,
+};
+/* clang-format on */
+
+#define INV_HSIAO_COUNT ARRAY_SIZE(INV_HSIAO)
+#define HSIAO_MASK      0x2a00000000ull
+
+static const OtKMACAppCfg KMAC_APP_CFG =
+    OT_KMAC_CONFIG(CSHAKE, 256u, "", "ROM_CTRL");
+
+typedef struct {
+    uint64_t *buffer; /* OT_ROM_CTRL_WORD_BYTES array, in logical order */
+    unsigned word_count; /* count of words in the buffer */
+    unsigned word_pos; /* current index in for computed KMAC digest */
+    bool local_gen; /* scrambling/ECC generated locally, not read from file */
+} OtRomCtrlScrambled;
+
+struct OtRomCtrlState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mem;
+    MemoryRegion mmio;
+    IbexIRQ pwrmgr_good;
+    IbexIRQ pwrmgr_done;
+    IbexIRQ alert;
+
+    uint32_t regs[REGS_COUNT];
+
+    uint64_t keys[2u]; /* may be NULL */
+    uint64_t nonce;
+    uint64_t addr_nonce;
+    uint64_t data_nonce;
+    unsigned addr_width; /* bit count */
+    unsigned data_nonce_width; /* bit count */
+    OtRomCtrlScrambled scrambled;
+    unsigned recovered_error_count;
+    unsigned unrecoverable_error_count;
+    char *hexstr;
+    bool first_reset;
+    bool loaded;
+
+    char *ot_id;
+    uint32_t size;
+    OtKMACState *kmac;
+    uint8_t kmac_app;
+    char *nonce_xstr;
+    char *key_xstr;
+};
+
+static void ot_rom_ctrl_get_mem_bounds(OtRomCtrlState *s, hwaddr *minaddr,
+                                       hwaddr *maxaddr)
+{
+    *minaddr = s->mem.addr;
+    *maxaddr = s->mem.addr + (hwaddr)memory_region_size(&s->mem);
+}
+
+static void ot_rom_ctrl_rust_demangle_fn(const char *st_name, int st_info,
+                                         uint64_t st_value, uint64_t st_size)
+{
+    (void)st_info;
+    (void)st_value;
+
+    if (!st_size) {
+        return;
+    }
+
+    rust_demangle_replace((char *)st_name);
+}
+
+static inline uint64_t
+ot_rom_ctrl_bitswap(uint64_t in, uint64_t mask, unsigned shift)
+{
+    return ((in & mask) << shift) | ((in & ~mask) >> shift);
+}
+
+static uint64_t ot_rom_ctrl_bitswap64(uint64_t val)
+{
+    val = ot_rom_ctrl_bitswap(val, 0x5555555555555555ull, 1u);
+    val = ot_rom_ctrl_bitswap(val, 0x3333333333333333ull, 2u);
+    val = ot_rom_ctrl_bitswap(val, 0x0f0f0f0f0f0f0f0full, 4u);
+    val = ot_rom_ctrl_bitswap(val, 0x00ff00ff00ff00ffull, 8u);
+    val = ot_rom_ctrl_bitswap(val, 0x0000ffff0000ffffull, 16u);
+    val = (val << 32u) | (val >> 32u);
+
+    return val;
+}
+
+static uint64_t ot_rom_ctrl_sbox(uint64_t in, unsigned width,
+                                 const uint8_t *sbox)
+{
+    g_assert(width < 64u);
+
+    uint64_t full_mask = (1ull << width) - 1ull;
+    width &= ~3ull;
+    uint64_t sbox_mask = (1ull << width) - 1ull;
+
+    uint64_t out = in & (full_mask & ~sbox_mask);
+    for (unsigned ix = 0u; ix < width; ix += 4u) {
+        uint64_t nibble = (in >> ix) & 0xfull;
+        out |= ((uint64_t)sbox[nibble]) << ix;
+    }
+
+    return out;
+}
+
+static uint64_t ot_rom_ctrl_flip(uint64_t in, unsigned width)
+{
+    uint64_t out = ot_rom_ctrl_bitswap64(in);
+
+    out >>= 64u - width;
+
+    return out;
+}
+
+static uint64_t ot_rom_ctrl_perm(uint64_t in, unsigned width, bool invert)
+{
+    g_assert(width < 64u);
+
+    uint64_t full_mask = (1ull << width) - 1ull;
+    width &= ~1ull;
+    uint64_t bfly_mask = (1ull << width) - 1ull;
+
+    uint64_t out = in & (full_mask & ~bfly_mask);
+
+    width >>= 1u;
+    if (!invert) {
+        for (unsigned ix = 0u; ix < width; ix++) {
+            uint64_t bit = (in >> (ix << 1u)) & 1ull;
+            out |= bit << ix;
+            bit = (in >> ((ix << 1u) + 1u)) & 1ull;
+            out |= bit << (width + ix);
+        }
+    } else {
+        for (unsigned ix = 0u; ix < width; ix++) {
+            uint64_t bit = (in >> ix) & 1ull;
+            out |= bit << (ix << 1u);
+            bit = (in >> (ix + width)) & 1ull;
+            out |= bit << ((ix << 1u) + 1);
+        }
+    }
+
+    return out;
+}
+
+static uint64_t ot_rom_ctrl_subst_perm_enc(uint64_t in, uint64_t key,
+                                           unsigned width, unsigned num_rounds)
+{
+    uint64_t state = in;
+
+    for (unsigned ix = 0u; ix < num_rounds; ix++) {
+        state ^= key;
+        state = ot_rom_ctrl_sbox(state, width, SBOX4);
+        state = ot_rom_ctrl_flip(state, width);
+        state = ot_rom_ctrl_perm(state, width, false);
+    }
+
+    state ^= key;
+
+    return state;
+}
+
+static unsigned ot_rom_ctrl_addr_sp_enc(const OtRomCtrlState *s, unsigned addr)
+{
+    return ot_rom_ctrl_subst_perm_enc(addr, s->addr_nonce, s->addr_width,
+                                      OT_ROM_CTRL_NUM_ADDR_SUBST_PERM_ROUNDS);
+}
+
+static uint64_t ot_rom_ctrl_data_sp_enc(const OtRomCtrlState *s, uint64_t in)
+{
+    (void)s;
+    return ot_rom_ctrl_subst_perm_enc(in, 0, OT_ROM_CTRL_WORD_BITS,
+                                      OT_ROM_CTRL_NUM_DATA_SUBST_PERM_ROUNDS);
+}
+
+static uint64_t
+ot_rom_ctrl_get_keystream(const OtRomCtrlState *s, unsigned addr)
+{
+    uint64_t scramble = (s->data_nonce << s->addr_width) | addr;
+    uint64_t stream = ot_prince_run(scramble, s->keys[1u], s->keys[0u],
+                                    OT_ROM_CTRL_NUM_PRINCE_HALF_ROUNDS);
+    return stream & ((1ull << OT_ROM_CTRL_WORD_BITS) - 1ull);
+}
+
+static uint64_t
+ot_rom_ctrl_unscramble_word(const OtRomCtrlState *s, unsigned addr, uint64_t in)
+{
+    uint64_t keystream = ot_rom_ctrl_get_keystream(s, addr);
+    return keystream ^ in;
+}
+
+static uint64_t
+ot_rom_ctrl_scramble_word(const OtRomCtrlState *s, unsigned addr, uint64_t in)
+{
+    uint64_t keystream = ot_rom_ctrl_get_keystream(s, addr);
+    return ot_rom_ctrl_data_sp_enc(s, keystream ^ in);
+}
+
+static uint32_t ot_rom_ctrl_verify_ecc_39_32_u32(
+    const OtRomCtrlState *s, uint64_t data_i, unsigned *err_o)
+{
+    unsigned syndrome = 0u;
+
+    for (unsigned int ix = 0u; ix < INV_HSIAO_COUNT; ix++) {
+        syndrome |=
+            __builtin_parityl((data_i ^ HSIAO_MASK) & INV_HSIAO[ix]) << ix;
+    }
+
+    unsigned err = __builtin_parity(syndrome);
+
+    if (!(err & 0x1u) && syndrome) {
+        err = 2u;
+    }
+
+    *err_o = err;
+
+    if (!err) {
+        return data_i & UINT32_MAX;
+    }
+
+    uint32_t data_o = 0u;
+
+#define ROM_CTRL_RECOVER(_sy_, _di_, _ix_) \
+    ((unsigned)((syndrome == (_sy_)) ^ (bool)((_di_) & (1ull << (_ix_)))) \
+     << (_ix_))
+
+    data_o |= ROM_CTRL_RECOVER(0x19u, data_i, 0u);
+    data_o |= ROM_CTRL_RECOVER(0x54u, data_i, 1u);
+    data_o |= ROM_CTRL_RECOVER(0x61u, data_i, 2u);
+    data_o |= ROM_CTRL_RECOVER(0x34u, data_i, 3u);
+    data_o |= ROM_CTRL_RECOVER(0x1au, data_i, 4u);
+    data_o |= ROM_CTRL_RECOVER(0x15u, data_i, 5u);
+    data_o |= ROM_CTRL_RECOVER(0x2au, data_i, 6u);
+    data_o |= ROM_CTRL_RECOVER(0x4cu, data_i, 7u);
+    data_o |= ROM_CTRL_RECOVER(0x45u, data_i, 8u);
+    data_o |= ROM_CTRL_RECOVER(0x38u, data_i, 9u);
+    data_o |= ROM_CTRL_RECOVER(0x49u, data_i, 10u);
+    data_o |= ROM_CTRL_RECOVER(0x0du, data_i, 11u);
+    data_o |= ROM_CTRL_RECOVER(0x51u, data_i, 12u);
+    data_o |= ROM_CTRL_RECOVER(0x31u, data_i, 13u);
+    data_o |= ROM_CTRL_RECOVER(0x68u, data_i, 14u);
+    data_o |= ROM_CTRL_RECOVER(0x07u, data_i, 15u);
+    data_o |= ROM_CTRL_RECOVER(0x1cu, data_i, 16u);
+    data_o |= ROM_CTRL_RECOVER(0x0bu, data_i, 17u);
+    data_o |= ROM_CTRL_RECOVER(0x25u, data_i, 18u);
+    data_o |= ROM_CTRL_RECOVER(0x26u, data_i, 19u);
+    data_o |= ROM_CTRL_RECOVER(0x46u, data_i, 20u);
+    data_o |= ROM_CTRL_RECOVER(0x0eu, data_i, 21u);
+    data_o |= ROM_CTRL_RECOVER(0x70u, data_i, 22u);
+    data_o |= ROM_CTRL_RECOVER(0x32u, data_i, 23u);
+    data_o |= ROM_CTRL_RECOVER(0x2cu, data_i, 24u);
+    data_o |= ROM_CTRL_RECOVER(0x13u, data_i, 25u);
+    data_o |= ROM_CTRL_RECOVER(0x23u, data_i, 26u);
+    data_o |= ROM_CTRL_RECOVER(0x62u, data_i, 27u);
+    data_o |= ROM_CTRL_RECOVER(0x4au, data_i, 28u);
+    data_o |= ROM_CTRL_RECOVER(0x29u, data_i, 29u);
+    data_o |= ROM_CTRL_RECOVER(0x16u, data_i, 30u);
+    data_o |= ROM_CTRL_RECOVER(0x52u, data_i, 31u);
+
+#undef OTP_ECC_RECOVER
+
+    if (err > 1u) {
+        trace_ot_rom_ctrl_unrecoverable_error(s->ot_id, (uint32_t)data_i);
+    } else {
+        if ((data_i & UINT32_MAX) != data_o) {
+            trace_ot_rom_ctrl_recovered_error(s->ot_id, (uint32_t)data_i,
+                                              (uint32_t)data_o);
+        } else {
+            /* ECC bit is corrupted */
+            trace_ot_rom_ctrl_parity_error(s->ot_id, (uint32_t)data_i,
+                                           (unsigned)(data_i >> 32u));
+        }
+    }
+
+    return data_o;
+}
+
+static uint64_t ot_rom_ctrl_add_ecc_39_32_u64(uint64_t data_i)
+{
+    uint64_t ecc = 0u;
+    bool inv = false;
+    data_i &= UINT32_MAX;
+    for (unsigned int ix = 0u; ix < INV_HSIAO_COUNT; ix++) {
+        ecc <<= 1;
+        bool parity = (bool)__builtin_parityl(
+            data_i & INV_HSIAO[INV_HSIAO_COUNT - 1u - ix]);
+        ecc |= (uint64_t)(parity ^ inv);
+        inv = !inv;
+    }
+    return data_i | (ecc << 32u);
+}
+
+static void ot_rom_ctrl_unscramble(OtRomCtrlState *s, const uint64_t *src,
+                                   uint32_t *dst)
+{
+    unsigned scr_word_size = (s->size - OT_ROM_DIGEST_BYTES) / sizeof(uint32_t);
+    unsigned dword_count = (s->size * 2u) / sizeof(uint64_t);
+    unsigned log_addr = 0u;
+    /* unscramble the whole ROM, except the trailing ROM digest bytes */
+    s->recovered_error_count = 0u;
+    s->unrecoverable_error_count = 0u;
+    for (; log_addr < scr_word_size; log_addr++) {
+        unsigned phy_addr = ot_rom_ctrl_addr_sp_enc(s, log_addr);
+        g_assert(phy_addr < dword_count);
+        uint64_t scrdata = src[phy_addr];
+        uint64_t clrdata = ot_rom_ctrl_unscramble_word(s, log_addr, scrdata);
+        dst[log_addr] = (uint32_t)clrdata;
+        unsigned err;
+        uint32_t fixdata = ot_rom_ctrl_verify_ecc_39_32_u32(s, clrdata, &err);
+        if (err & 0x1u) {
+            s->recovered_error_count += 1u;
+            dst[log_addr] = fixdata;
+        }
+        if (err & 0x2u) {
+            s->unrecoverable_error_count += 1u;
+        }
+    }
+    /* recover the ROM digest bytes, which are not scrambled */
+    for (unsigned wix = 0u; wix < ROM_DIGEST_WORDS; wix++, log_addr++) {
+        unsigned phy_addr = ot_rom_ctrl_addr_sp_enc(s, log_addr);
+        g_assert(phy_addr < dword_count);
+        s->regs[R_EXP_DIGEST_0 + wix] = (uint32_t)src[phy_addr];
+        /* note: ECC is not used for DIGEST words */
+    }
+}
+
+static void ot_rom_ctrl_scramble(OtRomCtrlState *s, const uint32_t *src,
+                                 uint64_t *dst)
+{
+    if (!s->key_xstr || !s->nonce_xstr) {
+        trace_ot_rom_ctrl_missing(s->ot_id,
+                                  "missing key/nonce to fake scrambling");
+        return;
+    }
+
+    unsigned scr_word_size = (s->size - OT_ROM_DIGEST_BYTES) / sizeof(uint32_t);
+    for (unsigned log_addr = 0u; log_addr < scr_word_size; log_addr++) {
+        uint64_t clrdata = src[log_addr];
+        uint64_t eclrdata = ot_rom_ctrl_add_ecc_39_32_u64(clrdata);
+        uint64_t scrdata = ot_rom_ctrl_scramble_word(s, log_addr, eclrdata);
+        dst[log_addr] = scrdata;
+    }
+}
+
+static void ot_rom_ctrl_compare_and_notify(OtRomCtrlState *s)
+{
+    /* compare digests */
+    bool rom_good = true;
+    for (unsigned ix = 0u; ix < ROM_DIGEST_WORDS; ix++) {
+        if (s->regs[R_EXP_DIGEST_0 + ix] != s->regs[R_DIGEST_0 + ix]) {
+            rom_good = false;
+            error_setg(&error_fatal,
+                       "ot_rom_ctrl: %s: Digest mismatch (expected 0x%08x got "
+                       "0x%08x) @ %u, errors: %u single-bit, %u double-bit\n",
+                       s->ot_id, s->regs[R_EXP_DIGEST_0 + ix],
+                       s->regs[R_DIGEST_0 + ix], ix, s->recovered_error_count,
+                       s->unrecoverable_error_count);
+        }
+    }
+
+    trace_ot_rom_ctrl_notify(s->ot_id, rom_good);
+
+    /* notify end of check */
+    ibex_irq_set(&s->pwrmgr_good, rom_good);
+    ibex_irq_set(&s->pwrmgr_done, true);
+}
+
+static void ot_rom_ctrl_send_kmac_req(OtRomCtrlState *s)
+{
+    g_assert(s->scrambled.buffer);
+    g_assert(s->scrambled.word_pos <= s->scrambled.word_count);
+
+    OtKMACAppReq req = {
+        .msg_len = OT_ROM_CTRL_WORD_BYTES,
+    };
+    stq_le_p(req.msg_data, s->scrambled.buffer[s->scrambled.word_pos]);
+    req.last = ++s->scrambled.word_pos == s->scrambled.word_count;
+
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    kc->app_request(s->kmac, s->kmac_app, &req);
+}
+
+static void
+ot_rom_ctrl_handle_kmac_response(void *opaque, const OtKMACAppRsp *rsp)
+{
+    OtRomCtrlState *s = OT_ROM_CTRL(opaque);
+
+    if (!rsp->done) {
+        ot_rom_ctrl_send_kmac_req(s);
+        return;
+    }
+    g_assert(s->scrambled.word_pos == s->scrambled.word_count);
+
+    qemu_vfree(s->scrambled.buffer);
+    s->scrambled.word_count = 0u;
+
+    /*
+     * switch to ROMD mode if no unrecoverable ECC error has been detected.
+     * Note that real HW does this on a per 32-bit address basis, but as any
+     * error triggers an invalid digest and prevents the Ibex core from booting,
+     * this use case is mostly useless anyway.
+     */
+    memory_region_rom_device_set_romd(&s->mem,
+                                      s->unrecoverable_error_count == 0u);
+
+    /* retrieve digest */
+    for (unsigned ix = 0u; ix < ROM_DIGEST_WORDS; ix++) {
+        uint32_t share0;
+        uint32_t share1;
+        memcpy(&share0, &rsp->digest_share0[ix * sizeof(uint32_t)],
+               sizeof(uint32_t));
+        memcpy(&share1, &rsp->digest_share1[ix * sizeof(uint32_t)],
+               sizeof(uint32_t));
+        s->regs[R_DIGEST_0 + ix] = share0 ^ share1;
+        if (s->scrambled.local_gen) {
+            s->regs[R_EXP_DIGEST_0 + ix] = s->regs[R_DIGEST_0 + ix];
+        }
+    }
+
+    if (trace_event_get_state(TRACE_OT_ROM_CTRL_COMPUTED_DIGEST)) {
+        uint8_t digest[OT_ROM_DIGEST_BYTES];
+        for (unsigned ix = 0u; ix < OT_ROM_DIGEST_BYTES; ix++) {
+            digest[ix] = rsp->digest_share0[ix] ^ rsp->digest_share1[ix];
+        }
+        trace_ot_rom_ctrl_computed_digest(
+            s->ot_id, ot_common_lhexdump(digest, OT_ROM_DIGEST_BYTES, true,
+                                         s->hexstr, OT_ROM_CTRL_HEXSTR_SIZE));
+    }
+
+    trace_ot_rom_ctrl_digest_mode(s->ot_id, "stored");
+
+    /* compare digests and send notification */
+    ot_rom_ctrl_compare_and_notify(s);
+}
+
+static void ot_rom_ctrl_spawn_hash_calculation(
+    OtRomCtrlState *s, uintptr_t scramble_ptr, bool generate)
+{
+    g_assert(scramble_ptr % sizeof(uint64_t) == 0ull);
+
+    OtRomCtrlScrambled *scrambled = &s->scrambled;
+    unsigned word_count = (s->size - OT_ROM_DIGEST_BYTES) / sizeof(uint32_t);
+    scrambled->buffer = (uint64_t *)scramble_ptr;
+    scrambled->word_count = word_count;
+    scrambled->word_pos = 0u;
+    scrambled->local_gen = generate;
+
+    ot_rom_ctrl_send_kmac_req(s);
+}
+
+static void ot_rom_ctrl_load_elf(OtRomCtrlState *s, const OtRomImg *ri)
+{
+    AddressSpace *as = ot_common_get_local_address_space(DEVICE(s));
+    hwaddr minaddr;
+    hwaddr maxaddr;
+    ot_rom_ctrl_get_mem_bounds(s, &minaddr, &maxaddr);
+    uint64_t loaddr;
+
+    if (load_elf_ram_sym_nosz(ri->filename, NULL, NULL, NULL, NULL, &loaddr,
+                              NULL, NULL, 0, EM_RISCV, 1, 0, as, false,
+                              &ot_rom_ctrl_rust_demangle_fn, true) <= 0) {
+        error_setg(&error_fatal,
+                   "ot_rom_ctrl: %s: ROM image '%s', ELF loading failed",
+                   s->ot_id, ri->filename);
+        return;
+    }
+    if ((loaddr < minaddr) || (loaddr > maxaddr)) {
+        /* cannot test upper load address as QEMU loader returns VMA, not LMA */
+        error_setg(&error_fatal, "ot_rom_ctrl: %s: ELF cannot fit into ROM",
+                   s->ot_id);
+    }
+
+    uintptr_t hostptr = (uintptr_t)memory_region_get_ram_ptr(&s->mem);
+
+    unsigned load_size = s->size * 2u;
+    uintptr_t tmpptr = (uintptr_t)qemu_memalign(sizeof(uint64_t), load_size);
+    ot_rom_ctrl_scramble(s, (const uint32_t *)hostptr, (uint64_t *)tmpptr);
+
+    ot_rom_ctrl_spawn_hash_calculation(s, tmpptr, true);
+}
+
+static void ot_rom_ctrl_load_binary(OtRomCtrlState *s, const OtRomImg *ri)
+{
+    if (ri->raw_size > s->size) {
+        error_setg(&error_fatal, "%s: %s: cannot fit into ROM", __func__,
+                   s->ot_id);
+        return;
+    }
+
+    /* NOLINTNEXTLINE(misc-redundant-expression) */
+    int fd = open(ri->filename, O_RDONLY | O_BINARY | O_CLOEXEC);
+    if (fd == -1) {
+        error_setg(&error_fatal, "%s: %s: could not open ROM '%s': %s",
+                   __func__, s->ot_id, ri->filename, strerror(errno));
+        return;
+    }
+
+    uint8_t *data = g_malloc0(ri->raw_size);
+    ssize_t rc = read(fd, data, ri->raw_size);
+    close(fd);
+
+    if (rc != (ssize_t)ri->raw_size) {
+        g_free(data);
+        error_setg(&error_fatal,
+                   "%s: %s: file %s: read error: rc=%zd (expected %u)",
+                   __func__, s->ot_id, ri->filename, rc, ri->raw_size);
+        return;
+    }
+
+    uintptr_t hostptr = (uintptr_t)memory_region_get_ram_ptr(&s->mem);
+    memcpy((void *)hostptr, data, ri->raw_size);
+    g_free(data);
+
+    memory_region_set_dirty(&s->mem, 0, ri->raw_size);
+
+    unsigned load_size = s->size * 2u;
+    uintptr_t tmpptr = (uintptr_t)qemu_memalign(sizeof(uint64_t), load_size);
+    ot_rom_ctrl_scramble(s, (const uint32_t *)hostptr, (uint64_t *)tmpptr);
+
+    ot_rom_ctrl_spawn_hash_calculation(s, tmpptr, true);
+}
+
+static char *ot_rom_ctrl_read_text_file(OtRomCtrlState *s, const OtRomImg *ri)
+{
+    if (!s->key_xstr || !s->nonce_xstr) {
+        error_setg(&error_fatal,
+                   "%s: %s: cannot unscrambled ROM '%s' w/o key and nonce\n",
+                   __func__, ri->filename, s->ot_id);
+        return NULL;
+    }
+
+    /* NOLINTNEXTLINE(misc-redundant-expression) */
+    int fd = open(ri->filename, O_RDONLY | O_BINARY | O_CLOEXEC);
+    if (fd == -1) {
+        error_setg(&error_fatal, "%s: %s: could not open ROM '%s': %s\n",
+                   __func__, ri->filename, s->ot_id, strerror(errno));
+        return NULL;
+    }
+
+    char *buffer = g_malloc0(ri->raw_size);
+    ssize_t rc = read(fd, buffer, ri->raw_size);
+    close(fd);
+
+    if (rc != ri->raw_size) {
+        g_free(buffer);
+        error_setg(&error_fatal,
+                   "%s: %s: file %s: read error: rc=%zd (expected %u)",
+                   __func__, s->ot_id, ri->filename, rc, ri->raw_size);
+        return NULL;
+    }
+
+    return buffer;
+}
+
+static void ot_rom_ctrl_load_vmem(OtRomCtrlState *s, const OtRomImg *ri,
+                                  bool scrambled_n_ecc)
+{
+    char *buffer = ot_rom_ctrl_read_text_file(s, ri);
+    if (!buffer) {
+        return;
+    }
+
+    uintptr_t baseptr;
+    unsigned load_size;
+    if (!scrambled_n_ecc) {
+        load_size = s->size;
+        baseptr = (uintptr_t)memory_region_get_ram_ptr(&s->mem);
+    } else {
+        /*
+         * allocate a temporary buffer to store scrambled data and ECC.
+         * The buffer needs to be twice as large as the 32-bit data since ECC
+         * byte is stored in b39..b32, so storage is managed with 64-bit values.
+         * This buffer is descrambled and ECC verified in a post-postprocessing
+         * stage where clear data are copied back to the device memory region
+         * and ECC data are discarded once used.
+         */
+        load_size = s->size * 2u;
+        baseptr = (uintptr_t)qemu_memalign(sizeof(uint64_t), load_size);
+    }
+
+    uintptr_t lastptr = baseptr + load_size;
+    uintptr_t memptr = baseptr;
+    unsigned exp_addr = 0u;
+    unsigned blk_size = scrambled_n_ecc ? sizeof(uint64_t) : sizeof(uint32_t);
+    const char *sep = "\r\n";
+    char *brks;
+    char *line;
+    for (line = strtok_r(buffer, sep, &brks); line;
+         line = strtok_r(NULL, sep, &brks)) {
+        if (strlen(line) == 0u) {
+            continue;
+        }
+
+        gchar **items = g_strsplit_set(line, " ", 0);
+        if (items[0u][0u] != '@') { /* block address */
+            g_strfreev(items);
+            continue;
+        }
+
+        unsigned blk_addr = (unsigned)g_ascii_strtoull(&items[0u][1], NULL, 16);
+        if (blk_addr < exp_addr) {
+            g_strfreev(items);
+            g_free(buffer);
+            error_setg(&error_fatal,
+                       "%s: %s: address discrepancy in VMEM file '%s'",
+                       __func__, s->ot_id, ri->filename);
+            return;
+        }
+        if (blk_addr != exp_addr) {
+            /* each block contains 32-bit of data */
+            unsigned pad_size = (blk_addr - exp_addr) * sizeof(uint32_t);
+            memptr += pad_size;
+        }
+
+        unsigned blk_count = 0u;
+        while (items[1u + blk_count]) {
+            blk_count++;
+        }
+
+        if ((memptr + (uintptr_t)(blk_count * blk_size)) > lastptr) {
+            g_free(buffer);
+            error_setg(&error_fatal, "%s: %s: VMEM file '%s' too large",
+                       __func__, s->ot_id, ri->filename);
+            return;
+        }
+
+        for (unsigned blk = 0u; blk < blk_count; blk++) {
+            uint64_t value = g_ascii_strtoull(items[1u + blk], NULL, 16);
+            if (!scrambled_n_ecc) {
+                /* direct store to ROM controller memory */
+                stl_le_p((void *)memptr, value & UINT32_MAX);
+                memptr += sizeof(uint32_t);
+            } else {
+                /* store to an intermediate buffer for delayed descrambling */
+                stq_le_p((void *)memptr, value);
+                memptr += sizeof(uint64_t);
+            }
+        }
+        exp_addr += blk_count;
+        g_strfreev(items);
+    }
+    g_free(buffer);
+
+    uintptr_t scrptr;
+
+    if (scrambled_n_ecc) {
+        uintptr_t dst = (uintptr_t)memory_region_get_ram_ptr(&s->mem);
+        g_assert((dst & 0x3u) == 0u);
+        ot_rom_ctrl_unscramble(s, (const uint64_t *)baseptr, (uint32_t *)dst);
+
+        /*
+         * hash buffer needs to be in logicial order, input file is in physical
+         * order. Create an intermediate copy
+         */
+        uint64_t *logbuf = qemu_memalign(sizeof(uint64_t), load_size);
+        const uint64_t *phybuf = (const uint64_t *)baseptr;
+        unsigned dword_count = load_size / sizeof(uint64_t);
+        for (unsigned log_addr = 0u; log_addr < dword_count; log_addr++) {
+            unsigned phy_addr = ot_rom_ctrl_addr_sp_enc(s, log_addr);
+            g_assert(phy_addr < dword_count);
+            logbuf[log_addr] = phybuf[phy_addr];
+        }
+        /* physical buffer is not longer needed */
+        qemu_vfree((void *)baseptr);
+
+        /* hash completion discard temporary baseptr */
+        scrptr = (uintptr_t)logbuf;
+    } else {
+        load_size = s->size * 2u;
+        uintptr_t tmpptr =
+            (uintptr_t)qemu_memalign(sizeof(uint64_t), load_size);
+        ot_rom_ctrl_scramble(s, (const uint32_t *)baseptr, (uint64_t *)tmpptr);
+        /*
+         * hash completion discard temporary tmpptr,
+         * baseptr points to the real QEMU host memory and should be kept.
+         */
+        scrptr = tmpptr;
+    }
+
+    ot_rom_ctrl_spawn_hash_calculation(s, scrptr, !scrambled_n_ecc);
+}
+
+static void ot_rom_ctrl_load_hex(OtRomCtrlState *s, const OtRomImg *ri)
+{
+    char *buffer = ot_rom_ctrl_read_text_file(s, ri);
+    if (!buffer) {
+        return;
+    }
+
+    /*
+     * allocate a temporary buffer to store scrambled data and ECC.
+     * The buffer needs to be twice as large as the 32-bit data since ECC
+     * byte is stored in b39..b32, so storage is managed with 64-bit values.
+     * This buffer is descrambled and ECC verified in a post-postprocessing
+     * stage where clear data are copied back to the device memory region
+     * and ECC data are discarded once used.
+     */
+    unsigned load_size = s->size * 2u;
+    uintptr_t baseptr = (uintptr_t)qemu_memalign(sizeof(uint64_t), load_size);
+    uintptr_t lastptr = baseptr + load_size;
+    uintptr_t memptr = baseptr;
+
+    const char *sep = "\r\n";
+    char *brks;
+    char *line;
+    for (line = strtok_r(buffer, sep, &brks); line;
+         line = strtok_r(NULL, sep, &brks)) {
+        if (strlen(line) == 0u) {
+            continue;
+        }
+
+        if (memptr >= lastptr) {
+            g_free(buffer);
+            error_setg(&error_fatal, "%s: %s: HEX file '%s' too large",
+                       __func__, s->ot_id, ri->filename);
+            return;
+        }
+
+        char *end;
+        uint64_t value = g_ascii_strtoull(line, &end, 16);
+        if (((uintptr_t)end - (uintptr_t)line) != 10u) {
+            g_free(buffer);
+            error_setg(&error_fatal, "%s: %s: invalid line in HEX file '%s'",
+                       __func__, s->ot_id, ri->filename);
+            return;
+        }
+        stq_le_p((void *)memptr, value);
+        memptr += sizeof(uint64_t);
+    }
+    g_free(buffer);
+
+    uintptr_t dst = (uintptr_t)memory_region_get_ram_ptr(&s->mem);
+    g_assert((dst & 0x3u) == 0u);
+    ot_rom_ctrl_unscramble(s, (const uint64_t *)baseptr, (uint32_t *)dst);
+
+    if (memptr > baseptr) {
+        memory_region_set_dirty(&s->mem, 0, memptr - baseptr);
+
+        unsigned loaded_size = (unsigned)(memptr - baseptr);
+        if (loaded_size != load_size) {
+            error_setg(&error_fatal,
+                       "%s: %s: incomplete HEX file '%s': %u bytes", __func__,
+                       s->ot_id, ri->filename, loaded_size / 2u);
+            return;
+        }
+
+        /*
+         * hash buffer needs to be in logicial order, input file is in physical
+         * order. Create an intermediate copy
+         */
+        uint64_t *logbuf = qemu_memalign(sizeof(uint64_t), load_size);
+        const uint64_t *phybuf = (const uint64_t *)baseptr;
+        unsigned dword_count = load_size / sizeof(uint64_t);
+        for (unsigned log_addr = 0u; log_addr < dword_count; log_addr++) {
+            unsigned phy_addr = ot_rom_ctrl_addr_sp_enc(s, log_addr);
+            g_assert(phy_addr < dword_count);
+            logbuf[log_addr] = phybuf[phy_addr];
+        }
+        /* physical buffer is not longer needed */
+        qemu_vfree((void *)baseptr);
+
+        /* hash completion takes care of freeing the buffer */
+        ot_rom_ctrl_spawn_hash_calculation(s, (uintptr_t)logbuf, false);
+    }
+}
+
+static void ot_rom_ctrl_load_rom(OtRomCtrlState *s)
+{
+    Object *obj = NULL;
+    OtRomImg *rom_img = NULL;
+
+    /* try to find our ROM image object */
+    obj = object_resolve_path_component(object_get_objects_root(), s->ot_id);
+    if (!obj) {
+        trace_ot_rom_ctrl_load_rom_no_image(s->ot_id);
+        /*
+         * when no ROM is present, fake an empty digest. This use case is not
+         * valid on real HW. In QEMU, it is a shortcut to run the platform
+         * for specific test cases. Note that the KeyManager may not produce
+         * valid results in such a case.
+         */
+        memset(&s->regs[R_EXP_DIGEST_0], 0,
+               ROM_DIGEST_WORDS * sizeof(uint32_t));
+        memset(&s->regs[R_DIGEST_0], 0, ROM_DIGEST_WORDS * sizeof(uint32_t));
+        ot_rom_ctrl_compare_and_notify(s);
+        return;
+    }
+    rom_img = (OtRomImg *)object_dynamic_cast(obj, TYPE_OT_ROM_IMG);
+    if (!rom_img) {
+        error_setg(&error_fatal, "%s: %s: Object is not a ROM Image", __func__,
+                   s->ot_id);
+        return;
+    }
+
+    const char *basename = strrchr(rom_img->filename, '/');
+    basename = basename ? basename + 1 : rom_img->filename;
+
+    switch (rom_img->format) {
+    case OT_ROM_IMG_FORMAT_VMEM_PLAIN:
+        trace_ot_rom_ctrl_image_identify(s->ot_id, basename, "plain VMEM");
+        ot_rom_ctrl_load_vmem(s, rom_img, false);
+        break;
+    case OT_ROM_IMG_FORMAT_VMEM_SCRAMBLED_ECC:
+        trace_ot_rom_ctrl_image_identify(s->ot_id, basename,
+                                         "scrambled VMEM w/ ECC");
+        ot_rom_ctrl_load_vmem(s, rom_img, true);
+        break;
+    case OT_ROM_IMG_FORMAT_HEX_SCRAMBLED_ECC:
+        trace_ot_rom_ctrl_image_identify(s->ot_id, basename,
+                                         "scrambled HEX w/ ECC");
+        ot_rom_ctrl_load_hex(s, rom_img);
+        break;
+    case OT_ROM_IMG_FORMAT_ELF:
+        trace_ot_rom_ctrl_image_identify(s->ot_id, basename, "ELF32");
+        ot_rom_ctrl_load_elf(s, rom_img);
+        break;
+    case OT_ROM_IMG_FORMAT_BINARY:
+        trace_ot_rom_ctrl_image_identify(s->ot_id, basename, "Binary");
+        ot_rom_ctrl_load_binary(s, rom_img);
+        break;
+    case OT_ROM_IMG_FORMAT_NONE:
+    default:
+        error_setg(&error_fatal, "%s: %s: unable to read binary file '%s'",
+                   __func__, s->ot_id, rom_img->filename);
+    }
+}
+
+static uint64_t ot_rom_ctrl_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtRomCtrlState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_FATAL_ALERT_CAUSE:
+    case R_DIGEST_0:
+    case R_DIGEST_1:
+    case R_DIGEST_2:
+    case R_DIGEST_3:
+    case R_DIGEST_4:
+    case R_DIGEST_5:
+    case R_DIGEST_6:
+    case R_DIGEST_7:
+    case R_EXP_DIGEST_0:
+    case R_EXP_DIGEST_1:
+    case R_EXP_DIGEST_2:
+    case R_EXP_DIGEST_3:
+    case R_EXP_DIGEST_4:
+    case R_EXP_DIGEST_5:
+    case R_EXP_DIGEST_6:
+    case R_EXP_DIGEST_7:
+        val32 = s->regs[reg];
+        break;
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0u;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0u;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_rom_ctrl_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg),
+                                  val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_rom_ctrl_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                   unsigned size)
+{
+    OtRomCtrlState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_rom_ctrl_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                               pc);
+
+    switch (reg) {
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_ERROR_MASK;
+        s->regs[reg] = val32;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    case R_FATAL_ALERT_CAUSE:
+    case R_DIGEST_0:
+    case R_DIGEST_1:
+    case R_DIGEST_2:
+    case R_DIGEST_3:
+    case R_DIGEST_4:
+    case R_DIGEST_5:
+    case R_DIGEST_6:
+    case R_DIGEST_7:
+    case R_EXP_DIGEST_0:
+    case R_EXP_DIGEST_1:
+    case R_EXP_DIGEST_2:
+    case R_EXP_DIGEST_3:
+    case R_EXP_DIGEST_4:
+    case R_EXP_DIGEST_5:
+    case R_EXP_DIGEST_6:
+    case R_EXP_DIGEST_7:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+};
+
+static void ot_rom_ctrl_get_rom_digest(const OtRomCtrlState *s,
+                                       uint8_t digest[OT_ROM_DIGEST_BYTES])
+{
+    g_assert(s != NULL);
+    for (unsigned wix = 0; wix < ROM_DIGEST_WORDS; wix++) {
+        stl_le_p(&digest[wix * sizeof(uint32_t)], s->regs[R_DIGEST_0 + wix]);
+    }
+}
+
+static void ot_rom_ctrl_mem_write(void *opaque, hwaddr addr, uint64_t value,
+                                  unsigned size)
+{
+    OtRomCtrlState *s = opaque;
+    uint32_t pc = ibex_get_current_pc();
+
+    trace_ot_rom_ctrl_mem_write(s->ot_id, (uint32_t)addr, (uint32_t)value, pc);
+
+    uint8_t *rom_ptr = (uint8_t *)memory_region_get_ram_ptr(&s->mem);
+
+    if ((addr + size) <= s->size) {
+        stn_le_p(&rom_ptr[addr], (int)size, value);
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x, pc=0x%x\n",
+                      __func__, s->ot_id, (uint32_t)addr, pc);
+    }
+}
+
+static bool ot_rom_ctrl_mem_accepts(void *opaque, hwaddr addr, unsigned size,
+                                    bool is_write, MemTxAttrs attrs)
+{
+    OtRomCtrlState *s = opaque;
+    (void)attrs;
+    uint32_t pc = ibex_get_current_pc();
+
+    if (!is_write) {
+        /*
+         * only allow reads during first reset (after complete check, MR gets
+         * turned to ROMD mode where mem_ops->valid.accepts is no longer called.
+         */
+        return s->first_reset;
+    }
+
+    bool accept = ((addr + size) <= s->size && s->first_reset);
+
+    if (!accept) {
+        trace_ot_rom_ctrl_mem_rejects(s->ot_id, (uint32_t)addr, is_write, pc);
+    }
+
+    return accept;
+}
+
+static void ot_rom_ctrl_parse_hexstr(const char *name, uint8_t **buf,
+                                     const char *hexstr, unsigned size)
+{
+    if (!hexstr) {
+        *buf = NULL;
+        return;
+    }
+
+    size_t len = strlen(hexstr);
+    if ((unsigned)len != size * 2u) {
+        *buf = NULL;
+        /* 1 char for each nibble */
+        error_setg(&error_fatal, "%s: Invalid %s string length: %zu", __func__,
+                   name, len);
+        return;
+    }
+
+    uint8_t *out = g_new0(uint8_t, size);
+    for (unsigned ix = 0u; ix < len; ix++) {
+        if (!g_ascii_isxdigit(hexstr[ix])) {
+            g_free(out);
+            *buf = NULL;
+            error_setg(&error_fatal, "%s: %s must only contain hex digits",
+                       __func__, name);
+            return;
+        }
+        uint8_t digit = g_ascii_xdigit_value(hexstr[ix]);
+        digit = (ix & 1u) ? (digit & 0xfu) : (digit << 4u);
+        out[ix / 2] |= digit;
+    }
+
+    *buf = out;
+}
+
+static const Property ot_rom_ctrl_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtRomCtrlState, ot_id),
+    DEFINE_PROP_UINT32("size", OtRomCtrlState, size, 0u),
+    DEFINE_PROP_LINK("kmac", OtRomCtrlState, kmac, TYPE_OT_KMAC, OtKMACState *),
+    DEFINE_PROP_UINT8("kmac-app", OtRomCtrlState, kmac_app, UINT8_MAX),
+    DEFINE_PROP_STRING("nonce", OtRomCtrlState, nonce_xstr),
+    DEFINE_PROP_STRING("key", OtRomCtrlState, key_xstr),
+};
+
+static const MemoryRegionOps ot_rom_ctrl_mem_ops = {
+    .write = &ot_rom_ctrl_mem_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 1u,
+    .impl.max_access_size = 4u,
+    .valid.accepts = &ot_rom_ctrl_mem_accepts,
+};
+
+static const MemoryRegionOps ot_rom_ctrl_regs_ops = {
+    .read = &ot_rom_ctrl_regs_read,
+    .write = &ot_rom_ctrl_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_rom_ctrl_reset_hold(Object *obj, ResetType type)
+{
+    OtRomCtrlClass *c = OT_ROM_CTRL_GET_CLASS(obj);
+    OtRomCtrlState *s = OT_ROM_CTRL(obj);
+
+    trace_ot_rom_ctrl_reset(s->ot_id, "hold");
+
+    if (c->parent_phases.hold) {
+        c->parent_phases.hold(obj, type);
+    }
+
+    s->loaded = false;
+
+    /* reset all registers on first reset, otherwise keep digests */
+    if (s->first_reset) {
+        memset(memory_region_get_ram_ptr(&s->mem), 0, s->size);
+        memset(s->regs, 0, REGS_SIZE);
+    } else {
+        s->regs[R_ALERT_TEST] = 0u;
+        s->regs[R_FATAL_ALERT_CAUSE] = 0u;
+    }
+
+    ibex_irq_set(&s->pwrmgr_good, false);
+    ibex_irq_set(&s->pwrmgr_done, false);
+
+    /* connect to KMAC */
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    kc->connect_app(s->kmac, s->kmac_app, &KMAC_APP_CFG,
+                    ot_rom_ctrl_handle_kmac_response, s);
+}
+
+static void ot_rom_ctrl_set_load(Object *obj, bool value, Error **errp)
+{
+    OtRomCtrlState *s = OT_ROM_CTRL(obj);
+    (void)errp;
+
+    if (!value) {
+        return;
+    }
+
+    if (!s->loaded) {
+        s->loaded = true;
+
+        /* on initial reset, load ROM then set it read-only */
+        if (s->first_reset) {
+            /* load ROM from file */
+            ot_rom_ctrl_load_rom(s);
+
+            /* ensure ROM can no longer be written */
+            s->first_reset = false;
+        } else {
+            /* compare existing digests and send notification to pwrmgr */
+            ot_rom_ctrl_compare_and_notify(s);
+        }
+    }
+}
+
+static void ot_rom_ctrl_realize(DeviceState *dev, Error **errp)
+{
+    OtRomCtrlState *s = OT_ROM_CTRL(dev);
+
+    g_assert(s->ot_id);
+    g_assert(s->size);
+    g_assert(s->kmac);
+    g_assert(s->kmac_app != UINT8_MAX);
+    OtKMACClass *kc = OT_KMAC_GET_CLASS(s->kmac);
+    g_assert(kc->connect_app);
+    g_assert(kc->app_request);
+
+    memory_region_init_rom_device_nomigrate(&s->mem, OBJECT(dev),
+                                            &ot_rom_ctrl_mem_ops, s,
+                                            TYPE_OT_ROM_CTRL ".mem", s->size,
+                                            errp);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mem);
+
+    /*
+     * at creation, set to read-write and disable ROMD mode:
+     * - read-write required for initial loading of ROM content
+     * - ROMD mode disabled effectively disables all reads until ROMD is enabled
+     * again after a successful digest check (mem_ops.valid.accepts rejects
+     * reads).
+     */
+    s->first_reset = true;
+    memory_region_rom_device_set_romd(&s->mem, false);
+
+    size_t wsize = (size_t)s->size / sizeof(uint32_t);
+    unsigned addrbits = ctz32(wsize);
+    g_assert((wsize & ~(1ull << addrbits)) == 0ull);
+
+    uint8_t *bytes;
+
+    ot_rom_ctrl_parse_hexstr("nonce", &bytes, s->nonce_xstr, sizeof(s->nonce));
+    if (bytes) {
+        s->nonce = ldq_be_p(bytes);
+        s->data_nonce_width = (sizeof(s->nonce) * 8u) - addrbits;
+        s->addr_nonce = s->nonce >> s->data_nonce_width;
+        s->data_nonce = s->nonce & ((1ull << s->data_nonce_width) - 1u);
+        g_free(bytes);
+    }
+
+    ot_rom_ctrl_parse_hexstr("key", &bytes, s->key_xstr, sizeof(s->keys));
+    if (bytes) {
+        s->keys[0u] = ldq_be_p(&bytes[8u]);
+        s->keys[1u] = ldq_be_p(&bytes[0u]);
+        g_free(bytes);
+    }
+
+    s->addr_width = addrbits;
+}
+
+static void ot_rom_ctrl_init(Object *obj)
+{
+    OtRomCtrlState *s = OT_ROM_CTRL(obj);
+
+    ibex_qdev_init_irq(obj, &s->pwrmgr_good, OT_ROM_CTRL_GOOD);
+    ibex_qdev_init_irq(obj, &s->pwrmgr_done, OT_ROM_CTRL_DONE);
+
+    memory_region_init_io(&s->mmio, obj, &ot_rom_ctrl_regs_ops, s,
+                          TYPE_OT_ROM_CTRL ".regs", REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    object_property_add_bool(obj, "load", NULL, &ot_rom_ctrl_set_load);
+    object_property_set_description(obj, "load", "Trigger initial ROM loading");
+
+    s->hexstr = g_new0(char, OT_ROM_CTRL_HEXSTR_SIZE);
+}
+
+static void ot_rom_ctrl_class_init(ObjectClass *klass, const void *data)
+{
+    (void)data;
+
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(dc);
+    OtRomCtrlClass *rcc = OT_ROM_CTRL_CLASS(klass);
+
+    resettable_class_set_parent_phases(rc, NULL, &ot_rom_ctrl_reset_hold, NULL,
+                                       &rcc->parent_phases);
+    dc->realize = &ot_rom_ctrl_realize;
+    device_class_set_props(dc, ot_rom_ctrl_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    rcc->get_rom_digest = &ot_rom_ctrl_get_rom_digest;
+}
+
+static const TypeInfo ot_rom_ctrl_info = {
+    .name = TYPE_OT_ROM_CTRL,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtRomCtrlState),
+    .instance_init = &ot_rom_ctrl_init,
+    .class_size = sizeof(OtRomCtrlClass),
+    .class_init = &ot_rom_ctrl_class_init,
+};
+
+static void ot_rom_ctrl_register_types(void)
+{
+    type_register_static(&ot_rom_ctrl_info);
+}
+
+type_init(ot_rom_ctrl_register_types);
diff --git a/hw/opentitan/ot_rom_ctrl_img.c b/hw/opentitan/ot_rom_ctrl_img.c
new file mode 100644
index 0000000000000..48ee3f71c639a
--- /dev/null
+++ b/hw/opentitan/ot_rom_ctrl_img.c
@@ -0,0 +1,235 @@
+/*
+ * QEMU OpenTitan ROM image
+ *
+ * Copyright (c) 2023 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qom/object_interfaces.h"
+#include "hw/opentitan/ot_rom_ctrl_img.h"
+
+/* Current ROMs digests are 256 bits (32 bytes) */
+#define ROM_DIGEST_BYTES 32u
+
+static const uint8_t ELF_HEADER[] = {
+    0x7fu, 0x45u, 0x4cu, 0x46u, 0x01u, 0x01u, 0x01u, 0x00u,
+};
+
+static OtRomImgFormat ot_rom_img_guess_image_format(const char *filename)
+{
+    /* NOLINTNEXTLINE(misc-redundant-expression) */
+    int fd = open(filename, O_RDONLY | O_BINARY | O_CLOEXEC);
+    if (fd == -1) {
+        return OT_ROM_IMG_FORMAT_NONE;
+    }
+
+    uint8_t data[128u];
+    ssize_t len = read(fd, data, sizeof(data));
+    data[sizeof(data) - 1u] = '\0';
+    close(fd);
+
+    if (len < sizeof(data)) {
+        return OT_ROM_IMG_FORMAT_NONE;
+    }
+
+    if (!memcmp(data, ELF_HEADER, sizeof(ELF_HEADER))) {
+        return OT_ROM_IMG_FORMAT_ELF;
+    }
+
+    /*
+     * Discard comments; only cope with single-line comments:
+     * we do not need to handle more, since OT-generated files do not contain
+     * multi-line comments in VMEM files; keep it as simple as possible.
+     */
+    if (data[0u] == '/' && (data[1u] == '*' || data[1u] == '/')) {
+        for (unsigned ix = 2u; ix < sizeof(data) - 1u; ix++) {
+            if (data[ix] == '\n') {
+                unsigned rem = sizeof(data) - 1u - ix;
+                memmove(&data[0], &data[ix + 1u], rem);
+                len = read(fd, &data[rem], sizeof(data) - rem);
+                (void)len; /* GCC unused result warning */
+                data[sizeof(data) - 1u] = '\0';
+                break;
+            }
+        }
+    }
+
+    if (data[0u] == '@') { /* likely a VMEM file */
+        bool addr = true;
+        unsigned dlen = 0u;
+        for (unsigned ix = 1u; ix < sizeof(data); ix++) {
+            if (data[ix] == ' ') { /* separator */
+                if (addr) {
+                    addr = false;
+                    continue;
+                }
+                break;
+            }
+            if (addr) {
+                if (data[ix] != '0') {
+                    /* first address is always expected to be 0 */
+                    break;
+                }
+                continue;
+            }
+            dlen += 1u;
+        }
+        if (dlen == 8u) { /* 32 bits */
+            return OT_ROM_IMG_FORMAT_VMEM_PLAIN;
+        }
+        if (dlen == 10u) { /* 40 bits */
+            return OT_ROM_IMG_FORMAT_VMEM_SCRAMBLED_ECC;
+        }
+    }
+
+    bool hexa_only = true;
+    unsigned cr = 0u;
+    unsigned ix;
+    for (ix = 0u; ix < sizeof(data); ix++) {
+        if (data[ix] == '\r') {
+            cr = ix;
+            continue;
+        }
+        if (data[ix] == '\n') {
+            if (cr) {
+                if (cr != ix - 1) {
+                    /* the only valid pos for useless CR is right before LF */
+                    hexa_only = false;
+                } else {
+                    /* ignore CR in line length */
+                    ix -= 1u;
+                }
+            }
+            break;
+        }
+        if (!g_ascii_isxdigit(data[ix])) {
+            hexa_only = false;
+            break;
+        }
+    }
+    if (hexa_only && ix == 10u) {
+        return OT_ROM_IMG_FORMAT_HEX_SCRAMBLED_ECC;
+    }
+
+    return OT_ROM_IMG_FORMAT_BINARY;
+}
+
+static void ot_rom_img_reset(OtRomImg *ri)
+{
+    ri->filename = NULL;
+    ri->format = OT_ROM_IMG_FORMAT_NONE;
+}
+
+static void ot_rom_img_prop_set_file(Object *obj, const char *value,
+                                     Error **errp)
+{
+    OtRomImg *ri = OT_ROM_IMG(obj);
+    (void)errp;
+
+    g_free(ri->filename);
+    ri->filename = NULL;
+
+    struct stat rom_stat;
+    int res = stat(value, &rom_stat);
+    if (res) {
+        error_setg(errp, "ROM image '%s' not found", value);
+        return;
+    }
+    if ((rom_stat.st_mode & S_IFMT) != S_IFREG) {
+        error_setg(errp, "ROM image '%s' is not a file", value);
+        return;
+    }
+    ri->raw_size = (unsigned)rom_stat.st_size;
+    ri->format = ot_rom_img_guess_image_format(value);
+    ri->filename = g_strdup(value);
+}
+
+static char *ot_rom_img_prop_get_file(Object *obj, Error **errp)
+{
+    OtRomImg *ri = OT_ROM_IMG(obj);
+    (void)errp;
+
+    return g_strdup(ri->filename);
+}
+
+static void ot_rom_img_instance_init(Object *obj)
+{
+    OtRomImg *ri = OT_ROM_IMG(obj);
+
+    ot_rom_img_reset(ri);
+}
+
+static void ot_rom_img_finalize(Object *obj)
+{
+    OtRomImg *ri = OT_ROM_IMG(obj);
+
+    g_free(ri->filename);
+
+    ot_rom_img_reset(ri);
+}
+
+static void ot_rom_img_complete(UserCreatable *uc, Error **errp)
+{
+    OtRomImg *ri = OT_ROM_IMG(uc);
+
+    if (!ri->filename) {
+        error_setg(errp, "Invalid ROM filename: cannot read file");
+        return;
+    }
+
+    if (!g_file_test(ri->filename, G_FILE_TEST_EXISTS)) {
+        error_setg(errp, "ROM file %s does not exist", ri->filename);
+        return;
+    }
+}
+
+static void ot_rom_img_class_init(ObjectClass *oc, const void *data)
+{
+    UserCreatableClass *ucc = USER_CREATABLE_CLASS(oc);
+    (void)data;
+
+    ucc->complete = &ot_rom_img_complete;
+
+    object_class_property_add_str(oc, "file", &ot_rom_img_prop_get_file,
+                                  &ot_rom_img_prop_set_file);
+}
+
+static const TypeInfo ot_rom_img_info = {
+    .parent = TYPE_OBJECT,
+    .name = TYPE_OT_ROM_IMG,
+    .instance_size = sizeof(OtRomImg),
+    .instance_init = &ot_rom_img_instance_init,
+    .instance_finalize = &ot_rom_img_finalize,
+    .class_init = &ot_rom_img_class_init,
+    .interfaces = (InterfaceInfo[]){ { TYPE_USER_CREATABLE }, {} }
+};
+
+static void ot_rom_img_register_types(void)
+{
+    type_register_static(&ot_rom_img_info);
+}
+
+type_init(ot_rom_img_register_types);
diff --git a/hw/opentitan/ot_rstmgr.c b/hw/opentitan/ot_rstmgr.c
new file mode 100644
index 0000000000000..621cae0747be5
--- /dev/null
+++ b/hw/opentitan/ot_rstmgr.c
@@ -0,0 +1,713 @@
+/*
+ * QEMU OpenTitan Reset Manager device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: for now, only a minimalist subset of Power Manager device is
+ *       implemented in order to enable OpenTitan's ROM boot to progress
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_i2c.h"
+#include "hw/opentitan/ot_rstmgr.h"
+#include "hw/opentitan/ot_spi_device.h"
+#include "hw/opentitan/ot_spi_host.h"
+#include "hw/qdev-core.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+#define PARAM_NUM_ALERTS 2u
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x0u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+    FIELD(ALERT_TEST, FATAL_CNSTY_FAULT, 1u, 1u)
+REG32(RESET_REQ, 0x4u)
+    FIELD(RESET_REQ, VAL, 0u, 4u)
+REG32(RESET_INFO, 0x8u)
+    FIELD(RESET_INFO, POR, 0u, 1u)
+    FIELD(RESET_INFO, LOW_POWER_EXIT, 1u, 1u)
+    FIELD(RESET_INFO, SW_RESET, 2u, 1u)
+    FIELD(RESET_INFO, HW_REQ, 3u, 5u)
+REG32(ALERT_REGWEN, 0xcu)
+    FIELD(ALERT_REGWEN, EN, 0u, 1u)
+REG32(ALERT_INFO_CTRL, 0x10u)
+    FIELD(ALERT_INFO_CTRL, EN, 0u, 1u)
+    FIELD(ALERT_INFO_CTRL, INDEX, 4u, 4u)
+REG32(ALERT_INFO_ATTR, 0x14u)
+    FIELD(ALERT_INFO_ATTR, CNT_AVAIL, 0u, 4u)
+REG32(ALERT_INFO, 0x18u)
+REG32(CPU_REGWEN, 0x1cu)
+    FIELD(CPU_REGWEN, EN, 0u, 1u)
+REG32(CPU_INFO_CTRL, 0x20u)
+    FIELD(CPU_INFO_CTRL, EN, 0u, 1u)
+    FIELD(CPU_INFO_CTRL, INDEX, 4u, 4u)
+REG32(CPU_INFO_ATTR, 0x24u)
+    FIELD(CPU_INFO_ATTR, CNT_AVAIL, 0u, 4u)
+REG32(CPU_INFO, 0x28u)
+REG32(SW_RST_REGWEN_0, 0x2cu)
+    SHARED_FIELD(SW_RST_REGWEN_EN, 0u, 1u)
+REG32(SW_RST_REGWEN_1, 0x30u)
+REG32(SW_RST_REGWEN_2, 0x34u)
+REG32(SW_RST_REGWEN_3, 0x38u)
+REG32(SW_RST_REGWEN_4, 0x3cu)
+REG32(SW_RST_REGWEN_5, 0x40u)
+REG32(SW_RST_REGWEN_6, 0x44u)
+REG32(SW_RST_REGWEN_7, 0x48u)
+REG32(SW_RST_CTRL_N_0, 0x4cu)
+    SHARED_FIELD(SW_RST_CTRL_VAL, 0u, 1u)
+REG32(SW_RST_CTRL_N_1, 0x50u)
+REG32(SW_RST_CTRL_N_2, 0x54u)
+REG32(SW_RST_CTRL_N_3, 0x58u)
+REG32(SW_RST_CTRL_N_4, 0x5cu)
+REG32(SW_RST_CTRL_N_5, 0x60u)
+REG32(SW_RST_CTRL_N_6, 0x64u)
+REG32(SW_RST_CTRL_N_7, 0x68u)
+REG32(ERR_CODE, 0x6cu)
+    FIELD(ERR_CODE, REG_INTG_ERR, 0u, 1u)
+    FIELD(ERR_CODE, RESET_CONSISTENCY_ERR, 1u, 1u)
+    FIELD(ERR_CODE, FSM_ERR, 2u, 1u)
+/* clang-format on */
+
+#define ALERT_TEST_MASK \
+    (R_ALERT_TEST_FATAL_FAULT_MASK | R_ALERT_TEST_FATAL_CNSTY_FAULT_MASK)
+#define RESET_INFO_MASK \
+    (R_RESET_INFO_POR_MASK | R_RESET_INFO_LOW_POWER_EXIT_MASK | \
+     R_RESET_INFO_SW_RESET_MASK | R_RESET_INFO_HW_REQ_MASK)
+#define ALERT_INFO_CTRL_MASK \
+    (R_ALERT_INFO_CTRL_EN_MASK | R_ALERT_INFO_CTRL_INDEX_MASK)
+#define CPU_INFO_CTRL_MASK \
+    (R_CPU_INFO_CTRL_EN_MASK | R_CPU_INFO_CTRL_INDEX_MASK)
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_ERR_CODE)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+/* clang-format off */
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(RESET_REQ),
+    REG_NAME_ENTRY(RESET_INFO),
+    REG_NAME_ENTRY(ALERT_REGWEN),
+    REG_NAME_ENTRY(ALERT_INFO_CTRL),
+    REG_NAME_ENTRY(ALERT_INFO_ATTR),
+    REG_NAME_ENTRY(ALERT_INFO),
+    REG_NAME_ENTRY(CPU_REGWEN),
+    REG_NAME_ENTRY(CPU_INFO_CTRL),
+    REG_NAME_ENTRY(CPU_INFO_ATTR),
+    REG_NAME_ENTRY(CPU_INFO),
+    REG_NAME_ENTRY(SW_RST_REGWEN_0),
+    REG_NAME_ENTRY(SW_RST_REGWEN_1),
+    REG_NAME_ENTRY(SW_RST_REGWEN_2),
+    REG_NAME_ENTRY(SW_RST_REGWEN_3),
+    REG_NAME_ENTRY(SW_RST_REGWEN_4),
+    REG_NAME_ENTRY(SW_RST_REGWEN_5),
+    REG_NAME_ENTRY(SW_RST_REGWEN_6),
+    REG_NAME_ENTRY(SW_RST_REGWEN_7),
+    REG_NAME_ENTRY(SW_RST_CTRL_N_0),
+    REG_NAME_ENTRY(SW_RST_CTRL_N_1),
+    REG_NAME_ENTRY(SW_RST_CTRL_N_2),
+    REG_NAME_ENTRY(SW_RST_CTRL_N_3),
+    REG_NAME_ENTRY(SW_RST_CTRL_N_4),
+    REG_NAME_ENTRY(SW_RST_CTRL_N_5),
+    REG_NAME_ENTRY(SW_RST_CTRL_N_6),
+    REG_NAME_ENTRY(SW_RST_CTRL_N_7),
+    REG_NAME_ENTRY(ERR_CODE),
+};
+#undef REG_NAME_ENTRY
+/* clang-format on */
+
+#define OT_RSTMGR_SW_RESET_MAX 8u
+
+struct OtRstMgrState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ soc_reset;
+    IbexIRQ sw_reset;
+    IbexIRQ alerts[PARAM_NUM_ALERTS];
+    QEMUBH *bus_reset_bh;
+    CPUState *cpu;
+
+    uint32_t *regs;
+    bool por; /* Power-On Reset property */
+
+    char *ot_id;
+    uint32_t fatal_reset;
+    uint8_t version;
+};
+
+struct OtRstMgrClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+typedef struct {
+    const char *typename;
+    unsigned idx;
+} OtRstMgrResettable;
+
+typedef struct {
+    char *path;
+    bool reset;
+    char *ot_id;
+} OtRstMgrResetDesc;
+
+typedef struct {
+    uint32_t reset_request_codes[OT_RSTMGR_RESET_COUNT];
+    OtRstMgrResettable sw_resettable_devices[OT_RSTMGR_SW_RESET_MAX];
+} OtRstMgrConfig;
+
+static const OtRstMgrConfig RSTMGR_CONFIG[OT_RSTMGR_VERSION_COUNT] = {
+    [OT_RSTMGR_VERSION_EG_1_0_0] = {
+        .reset_request_codes = {
+            [OT_RSTMGR_RESET_POR] = BIT(0),
+            [OT_RSTMGR_RESET_LOW_POWER] = BIT(1),
+            [OT_RSTMGR_RESET_SW] = BIT(2),
+            [OT_RSTMGR_RESET_SYSCTRL] = BIT(3),
+            [OT_RSTMGR_RESET_AON_TIMER] = BIT(4),
+            [OT_RSTMGR_RESET_SENSOR] = BIT(5),
+            [OT_RSTMGR_RESET_PWRMGR] = BIT(6),
+            [OT_RSTMGR_RESET_ALERT_HANDLER] = BIT(7),
+            [OT_RSTMGR_RESET_RV_DM] = BIT(8),
+        },
+        .sw_resettable_devices = {
+            [0u] = { TYPE_OT_SPI_DEVICE, 0u },
+            [1u] = { TYPE_OT_SPI_HOST, 0u },
+            [2u] = { TYPE_OT_SPI_HOST, 1u },
+            /*
+             * Not yet supported
+             *
+             * [3u] = { TYPE_OT_USB, 0u },
+             * [4u] = { TYPE_OT_USB, 1u },
+             * [5u] = { TYPE_OT_I2C_EG, 0u },
+             * [6u] = { TYPE_OT_I2C_EG, 1u },
+             * [7u] = { TYPE_OT_I2C_EG, 2u },
+             */
+        }
+    },
+    [OT_RSTMGR_VERSION_DJ] = {
+        .reset_request_codes = {
+            [OT_RSTMGR_RESET_POR] = BIT(0),
+            [OT_RSTMGR_RESET_LOW_POWER] = BIT(1),
+            [OT_RSTMGR_RESET_SW] = BIT(2),
+            [OT_RSTMGR_RESET_AON_TIMER] = BIT(3),
+            [OT_RSTMGR_RESET_SOC_PROXY] = BIT(4),
+            [OT_RSTMGR_RESET_PWRMGR] = BIT(5),
+            [OT_RSTMGR_RESET_ALERT_HANDLER] = BIT(6),
+            [OT_RSTMGR_RESET_RV_DM] = BIT(7),
+        },
+        .sw_resettable_devices = {
+            [0u] = { TYPE_OT_SPI_DEVICE, 0u },
+            [1u] = { TYPE_OT_SPI_HOST, 0u },
+            [2u] = { TYPE_OT_I2C, 0u },
+        }
+    },
+};
+
+/* clang-format off */
+#define REQ_NAME_ENTRY(_req_) [OT_RSTMGR_RESET_##_req_] = stringify(_req_)
+static const char *OT_RST_MGR_REQUEST_NAMES[] = {
+    REQ_NAME_ENTRY(NONE),
+    REQ_NAME_ENTRY(POR),
+    REQ_NAME_ENTRY(LOW_POWER),
+    REQ_NAME_ENTRY(SW),
+    REQ_NAME_ENTRY(SYSCTRL),
+    REQ_NAME_ENTRY(SOC_PROXY),
+    REQ_NAME_ENTRY(AON_TIMER),
+    REQ_NAME_ENTRY(SYSCTRL),
+    REQ_NAME_ENTRY(SENSOR),
+    REQ_NAME_ENTRY(PWRMGR),
+    REQ_NAME_ENTRY(ALERT_HANDLER),
+    REQ_NAME_ENTRY(RV_DM),
+};
+#undef REQ_NAME_ENTRY
+/* clang-format on */
+
+#define REQ_NAME(_req_) \
+    ((_req_) < ARRAY_SIZE(OT_RST_MGR_REQUEST_NAMES)) ? \
+        OT_RST_MGR_REQUEST_NAMES[(_req_)] : \
+        "?"
+
+/* -------------------------------------------------------------------------- */
+/* Private implementation */
+/* -------------------------------------------------------------------------- */
+
+static void ot_rstmgr_update_alerts(OtRstMgrState *s)
+{
+    uint32_t level = s->regs[R_ALERT_TEST];
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_rstmgr_reset_bus(void *opaque)
+{
+    OtRstMgrState *s = opaque;
+
+    /* request the vCPU to stop */
+    s->cpu->stop = true;
+
+    /* wait for the vCPU to stop */
+    while (!s->cpu->stopped) {
+        bql_unlock();
+        qemu_cpu_kick(s->cpu);
+        bql_lock();
+    }
+    qemu_notify_event();
+
+    ibex_irq_raise(&s->soc_reset);
+}
+
+static int ot_rstmgr_sw_rst_walker(DeviceState *dev, void *opaque)
+{
+    OtRstMgrResetDesc *desc = opaque;
+
+    int match =
+        strcmp(object_get_canonical_path_component(OBJECT(dev)), desc->path);
+
+    if (match) {
+        /* not the instance that is seeked, resume walk */
+        return 0;
+    }
+
+    trace_ot_rstmgr_sw_rst(desc->ot_id, desc->path, desc->reset);
+
+    if (desc->reset) {
+        resettable_assert_reset(OBJECT(dev), RESET_TYPE_COLD);
+    } else {
+        resettable_release_reset(OBJECT(dev), RESET_TYPE_COLD);
+    }
+
+    /* abort walk immediately */
+    return -1;
+}
+
+static void ot_rstmgr_update_sw_reset(OtRstMgrState *s, unsigned devix)
+{
+    assert(devix < OT_RSTMGR_SW_RESET_MAX);
+
+    const OtRstMgrConfig *config = &RSTMGR_CONFIG[s->version];
+    const OtRstMgrResettable *rst = &config->sw_resettable_devices[devix];
+
+    if (!rst->typename) {
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: %s: Reset for slot %u not yet implemented", __func__,
+                      s->ot_id, devix);
+        return;
+    }
+
+    OtRstMgrResetDesc desc;
+
+    desc.path = g_strdup_printf("%s[%d]", rst->typename, rst->idx);
+    desc.reset = !s->regs[R_SW_RST_CTRL_N_0 + devix];
+    desc.ot_id = s->ot_id;
+
+    trace_ot_rstmgr_sw_reset(s->ot_id, desc.path);
+
+    /* search for the device on the same local bus */
+    int res =
+        qbus_walk_children(s->parent_obj.parent_obj.parent_bus,
+                           &ot_rstmgr_sw_rst_walker, NULL, NULL, NULL, &desc);
+    if (res >= 0) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Unable to locate device %s",
+                      __func__, s->ot_id, desc.path);
+    }
+
+    g_free(desc.path);
+}
+
+static void ot_rstmgr_reset_req(void *opaque, int irq, int level)
+{
+    OtRstMgrState *s = opaque;
+
+    if (!level) {
+        /* reset line released */
+        return;
+    }
+
+    g_assert(irq == 0);
+
+    bool fastclk = ((unsigned)level >> 8u) & 1u;
+
+    level &= UINT8_MAX;
+    g_assert(level < OT_RSTMGR_RESET_COUNT);
+
+    const OtRstMgrConfig *config = &RSTMGR_CONFIG[s->version];
+    uint32_t req = config->reset_request_codes[level];
+
+    if (!req) {
+        qemu_log_mask(LOG_UNIMP, "%s: %s: unsupported reset request %d\n",
+                      __func__, s->ot_id, level);
+        return;
+    }
+
+    s->regs[R_RESET_INFO] = req;
+
+    trace_ot_rstmgr_reset_req(s->ot_id, REQ_NAME(level), req, fastclk);
+
+    qemu_bh_schedule(s->bus_reset_bh);
+}
+
+static uint64_t ot_rstmgr_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtRstMgrState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_RESET_REQ:
+    case R_RESET_INFO:
+    case R_ALERT_REGWEN:
+    case R_ALERT_INFO_CTRL:
+    case R_ALERT_INFO_ATTR:
+    case R_ALERT_INFO:
+    case R_CPU_REGWEN:
+    case R_CPU_INFO_CTRL:
+    case R_CPU_INFO_ATTR:
+    case R_CPU_INFO:
+    case R_SW_RST_REGWEN_0:
+    case R_SW_RST_REGWEN_1:
+    case R_SW_RST_REGWEN_2:
+    case R_SW_RST_REGWEN_3:
+    case R_SW_RST_REGWEN_4:
+    case R_SW_RST_REGWEN_5:
+    case R_SW_RST_REGWEN_6:
+    case R_SW_RST_REGWEN_7:
+    case R_SW_RST_CTRL_N_0:
+    case R_SW_RST_CTRL_N_1:
+    case R_SW_RST_CTRL_N_2:
+    case R_SW_RST_CTRL_N_3:
+    case R_SW_RST_CTRL_N_4:
+    case R_SW_RST_CTRL_N_5:
+    case R_SW_RST_CTRL_N_6:
+    case R_SW_RST_CTRL_N_7:
+    case R_ERR_CODE:
+        val32 = s->regs[reg];
+        break;
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x02%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_rstmgr_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                                pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_rstmgr_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                 unsigned size)
+{
+    OtRstMgrState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_rstmgr_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                             pc);
+
+    switch (reg) {
+    case R_RESET_REQ:
+        val32 &= R_RESET_REQ_VAL_MASK;
+        s->regs[reg] = val32;
+        if (val32 == OT_MULTIBITBOOL4_TRUE) {
+            /*
+             * "Upon completion of reset, this bit is automatically cleared by
+             * hardware."
+             */
+            ibex_irq_raise(&s->sw_reset);
+            if (s->fatal_reset) {
+                s->fatal_reset--;
+                if (!s->fatal_reset) {
+                    error_report("%s: fatal reset triggered", s->ot_id);
+                    qemu_system_shutdown_request_with_code(
+                        SHUTDOWN_CAUSE_GUEST_SHUTDOWN, 1);
+                }
+            }
+        }
+        break;
+    case R_RESET_INFO:
+        val32 &= RESET_INFO_MASK;
+        s->regs[reg] &= ~val32; /* RW1C */
+        break;
+    case R_ALERT_REGWEN:
+        val32 &= R_ALERT_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_ALERT_INFO_CTRL:
+        if (s->regs[R_ALERT_REGWEN]) {
+            val32 &= ALERT_INFO_CTRL_MASK;
+            s->regs[reg] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ REGWEN\n",
+                          __func__, s->ot_id, REG_NAME(reg));
+        }
+        break;
+    case R_CPU_REGWEN:
+        val32 &= R_CPU_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CPU_INFO_CTRL:
+        if (s->regs[R_CPU_REGWEN]) {
+            val32 &= CPU_INFO_CTRL_MASK;
+            s->regs[reg] = val32;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ REGWEN\n",
+                          __func__, s->ot_id, REG_NAME(reg));
+        }
+        break;
+    case R_SW_RST_REGWEN_0:
+    case R_SW_RST_REGWEN_1:
+    case R_SW_RST_REGWEN_2:
+    case R_SW_RST_REGWEN_3:
+    case R_SW_RST_REGWEN_4:
+    case R_SW_RST_REGWEN_5:
+    case R_SW_RST_REGWEN_6:
+    case R_SW_RST_REGWEN_7:
+        val32 &= SW_RST_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_SW_RST_CTRL_N_0:
+    case R_SW_RST_CTRL_N_1:
+    case R_SW_RST_CTRL_N_2:
+    case R_SW_RST_CTRL_N_3:
+    case R_SW_RST_CTRL_N_4:
+    case R_SW_RST_CTRL_N_5:
+    case R_SW_RST_CTRL_N_6:
+    case R_SW_RST_CTRL_N_7:
+        if (s->regs[reg - R_SW_RST_CTRL_N_0 + R_SW_RST_REGWEN_0]) {
+            val32 &= SW_RST_CTRL_VAL_MASK;
+            uint32_t change = s->regs[reg] ^ val32;
+            s->regs[reg] = val32;
+            unsigned devix = (unsigned)reg - R_SW_RST_CTRL_N_0;
+            if (change & (1u << devix)) {
+                ot_rstmgr_update_sw_reset(s, devix);
+            }
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: %s protected w/ REGWEN\n",
+                          __func__, s->ot_id, REG_NAME(reg));
+        }
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        s->regs[reg] = val32;
+        ot_rstmgr_update_alerts(s);
+        break;
+    case R_ALERT_INFO_ATTR:
+    case R_ALERT_INFO:
+    case R_CPU_INFO_ATTR:
+    case R_CPU_INFO:
+    case R_ERR_CODE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x02%x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static const Property ot_rstmgr_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtRstMgrState, ot_id),
+    DEFINE_PROP_UINT32("fatal_reset", OtRstMgrState, fatal_reset, 0),
+    DEFINE_PROP_UINT8("version", OtRstMgrState, version, UINT8_MAX),
+};
+
+static const MemoryRegionOps ot_rstmgr_regs_ops = {
+    .read = &ot_rstmgr_regs_read,
+    .write = &ot_rstmgr_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_rstmgr_reset_enter(Object *obj, ResetType type)
+{
+    OtRstMgrClass *c = OT_RSTMGR_GET_CLASS(obj);
+    OtRstMgrState *s = OT_RSTMGR(obj);
+
+    trace_ot_rstmgr_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    qemu_bh_cancel(s->bus_reset_bh);
+
+    uint32_t reset_info = s->regs[R_RESET_INFO];
+
+    memset(s->regs, 0, REGS_SIZE);
+
+    if (s->por) {
+        s->regs[R_RESET_INFO] = R_RESET_INFO_POR_MASK;
+        s->por = false;
+    } else {
+        s->regs[R_RESET_INFO] = reset_info;
+    }
+    s->regs[R_RESET_REQ] = OT_MULTIBITBOOL4_FALSE;
+    s->regs[R_ALERT_REGWEN] = R_ALERT_REGWEN_EN_MASK;
+    s->regs[R_CPU_REGWEN] = R_CPU_REGWEN_EN_MASK;
+
+    const OtRstMgrConfig *config = &RSTMGR_CONFIG[s->version];
+
+    for (unsigned devix = 0; devix < OT_RSTMGR_SW_RESET_MAX; devix++) {
+        const OtRstMgrResettable *rst = &config->sw_resettable_devices[devix];
+        /*
+         * On Earlgrey, not all SW resettable devices are implemented yet, but
+         * there is still merit in resetting these registers so that they can
+         * be tested as part of the rstmgr implementation.
+         *
+         * TODO: remove this version check when USBDEV and I2C are implemented
+         * and connected to the `rstmgr`.
+         */
+        if (rst->typename || s->version == OT_RSTMGR_VERSION_EG_1_0_0) {
+            s->regs[R_SW_RST_REGWEN_0 + devix] = SW_RST_REGWEN_EN_MASK;
+            s->regs[R_SW_RST_CTRL_N_0 + devix] = SW_RST_CTRL_VAL_MASK;
+        }
+    }
+
+    ibex_irq_lower(&s->soc_reset);
+    ibex_irq_lower(&s->sw_reset);
+    ot_rstmgr_update_alerts(s);
+}
+
+static void ot_rstmgr_reset_exit(Object *obj, ResetType type)
+{
+    OtRstMgrClass *c = OT_RSTMGR_GET_CLASS(obj);
+    OtRstMgrState *s = OT_RSTMGR(obj);
+
+    trace_ot_rstmgr_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    if (!s->cpu) {
+        CPUState *cpu = ot_common_get_local_cpu(DEVICE(s));
+        if (!cpu) {
+            error_setg(&error_fatal, "%s: Could not find the associated vCPU",
+                       s->ot_id);
+            g_assert_not_reached();
+        }
+        s->cpu = cpu;
+    }
+}
+
+static void ot_rstmgr_realize(DeviceState *dev, Error **errp)
+{
+    OtRstMgrState *s = OT_RSTMGR(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->version < OT_RSTMGR_VERSION_COUNT);
+
+    /* only used to store initial reset reason state; never reset it */
+    s->por = true;
+}
+
+static void ot_rstmgr_init(Object *obj)
+{
+    OtRstMgrState *s = OT_RSTMGR(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_rstmgr_regs_ops, s, TYPE_OT_RSTMGR,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+
+    ibex_qdev_init_irq(obj, &s->soc_reset, OT_RSTMGR_SOC_RST);
+    ibex_qdev_init_irq(obj, &s->sw_reset, OT_RSTMGR_SW_RST);
+    ibex_qdev_init_irqs(obj, s->alerts, OT_DEVICE_ALERT, PARAM_NUM_ALERTS);
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_rstmgr_reset_req,
+                            OT_RSTMGR_RST_REQ, 1);
+
+    s->bus_reset_bh = qemu_bh_new(&ot_rstmgr_reset_bus, s);
+}
+
+static void ot_rstmgr_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_rstmgr_realize;
+    device_class_set_props(dc, ot_rstmgr_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtRstMgrClass *mc = OT_RSTMGR_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_rstmgr_reset_enter, NULL,
+                                       &ot_rstmgr_reset_exit,
+                                       &mc->parent_phases);
+}
+
+static const TypeInfo ot_rstmgr_info = {
+    .name = TYPE_OT_RSTMGR,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtRstMgrState),
+    .instance_init = &ot_rstmgr_init,
+    .class_size = sizeof(OtRstMgrClass),
+    .class_init = &ot_rstmgr_class_init,
+};
+
+static void ot_rstmgr_register_types(void)
+{
+    type_register_static(&ot_rstmgr_info);
+}
+
+type_init(ot_rstmgr_register_types);
diff --git a/hw/opentitan/ot_sensor_eg.c b/hw/opentitan/ot_sensor_eg.c
new file mode 100644
index 0000000000000..29207eba402e4
--- /dev/null
+++ b/hw/opentitan/ot_sensor_eg.c
@@ -0,0 +1,454 @@
+/*
+ * QEMU OpenTitan Sensor controller device for EarlGrey
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: for now, only a minimalist subset of Power Manager device is
+ *       implemented in order to enable OpenTitan's ROM boot to progress
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_sensor_eg.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+#define NUM_ALERTS   2u
+#define NUM_IO_RAILS 2u
+
+#define NUM_ALERT_SENSOR_COUNT 11u
+
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(INTR_IO_STATUS_CHANGE, 0u, 1u)
+    SHARED_FIELD(INTR_INIT_STATUS_CHANGE, 1u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, RECOV_ALERT, 0u, 1u)
+    FIELD(ALERT_TEST, FATAL_ALERT, 1u, 1u)
+REG32(CFG_REGWEN, 0x10u)
+    FIELD(CFG_REGWEN, EN, 0u, 1u)
+REG32(ALERT_TRIG, 0x14u)
+    FIELD(ALERT_TRIG, VAL_0, 0u, 1u)
+    FIELD(ALERT_TRIG, VAL_1, 1u, 1u)
+    FIELD(ALERT_TRIG, VAL_2, 2u, 1u)
+    FIELD(ALERT_TRIG, VAL_3, 3u, 1u)
+    FIELD(ALERT_TRIG, VAL_4, 4u, 1u)
+    FIELD(ALERT_TRIG, VAL_5, 5u, 1u)
+    FIELD(ALERT_TRIG, VAL_6, 6u, 1u)
+    FIELD(ALERT_TRIG, VAL_7, 7u, 1u)
+    FIELD(ALERT_TRIG, VAL_8, 8u, 1u)
+    FIELD(ALERT_TRIG, VAL_9, 9u, 1u)
+    FIELD(ALERT_TRIG, VAL_10, 10u, 1u)
+REG32(ALERT_EN_0, 0x18u)
+    SHARED_FIELD(ALERT_EN_VAL, 0u, 4u)
+REG32(ALERT_EN_1, 0x1cu)
+REG32(ALERT_EN_2, 0x20u)
+REG32(ALERT_EN_3, 0x24u)
+REG32(ALERT_EN_4, 0x28u)
+REG32(ALERT_EN_5, 0x2cu)
+REG32(ALERT_EN_6, 0x30u)
+REG32(ALERT_EN_7, 0x34u)
+REG32(ALERT_EN_8, 0x38u)
+REG32(ALERT_EN_9, 0x3cu)
+REG32(ALERT_EN_10, 0x40u)
+REG32(FATAL_ALERT_EN, 0x44u)
+    FIELD(FATAL_ALERT_EN, VAL_0, 0u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_1, 1u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_2, 2u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_3, 3u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_4, 4u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_5, 5u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_6, 6u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_7, 7u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_8, 8u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_9, 9u, 1u)
+    FIELD(FATAL_ALERT_EN, VAL_10, 10u, 1u)
+REG32(RECOV_ALERT, 0x48u)
+    FIELD(RECOV_ALERT, VAL_0, 0u, 1u)
+    FIELD(RECOV_ALERT, VAL_1, 1u, 1u)
+    FIELD(RECOV_ALERT, VAL_2, 2u, 1u)
+    FIELD(RECOV_ALERT, VAL_3, 3u, 1u)
+    FIELD(RECOV_ALERT, VAL_4, 4u, 1u)
+    FIELD(RECOV_ALERT, VAL_5, 5u, 1u)
+    FIELD(RECOV_ALERT, VAL_6, 6u, 1u)
+    FIELD(RECOV_ALERT, VAL_7, 7u, 1u)
+    FIELD(RECOV_ALERT, VAL_8, 8u, 1u)
+    FIELD(RECOV_ALERT, VAL_9, 9u, 1u)
+    FIELD(RECOV_ALERT, VAL_10, 10u, 1u)
+REG32(FATAL_ALERT, 0x4cu)
+    FIELD(FATAL_ALERT, VAL_0, 0u, 1u)
+    FIELD(FATAL_ALERT, VAL_1, 1u, 1u)
+    FIELD(FATAL_ALERT, VAL_2, 2u, 1u)
+    FIELD(FATAL_ALERT, VAL_3, 3u, 1u)
+    FIELD(FATAL_ALERT, VAL_4, 4u, 1u)
+    FIELD(FATAL_ALERT, VAL_5, 5u, 1u)
+    FIELD(FATAL_ALERT, VAL_6, 6u, 1u)
+    FIELD(FATAL_ALERT, VAL_7, 7u, 1u)
+    FIELD(FATAL_ALERT, VAL_8, 8u, 1u)
+    FIELD(FATAL_ALERT, VAL_9, 9u, 1u)
+    FIELD(FATAL_ALERT, VAL_10, 10u, 1u)
+    FIELD(FATAL_ALERT, VAL_11, 11u, 1u)
+REG32(STATUS, 0x50u)
+    FIELD(STATUS, AST_INIT_DONE, 0u, 1u)
+    FIELD(STATUS, IO_POK, 1u, 2u)
+REG32(MANUAL_PAD_ATTR_REGWEN_0, 0x54u)
+    SHARED_FIELD(MANUAL_PAD_ATTR_REGWEN_EN, 0u, 1u)
+REG32(MANUAL_PAD_ATTR_REGWEN_1, 0x58u)
+REG32(MANUAL_PAD_ATTR_REGWEN_2, 0x5cu)
+REG32(MANUAL_PAD_ATTR_REGWEN_3, 0x60u)
+REG32(MANUAL_PAD_ATTR_0, 0x64u)
+    SHARED_FIELD(MANUAL_PAD_ATTR_PULL_EN, 2u, 1u)
+    SHARED_FIELD(MANUAL_PAD_ATTR_PULL_SELECT, 3u, 1u)
+    SHARED_FIELD(MANUAL_PAD_ATTR_INPUT_DISABLE, 7u, 1u)
+REG32(MANUAL_PAD_ATTR_1, 0x68u)
+REG32(MANUAL_PAD_ATTR_2, 0x6cu)
+REG32(MANUAL_PAD_ATTR_3, 0x70u)
+/* clang-format on */
+
+#define INTR_MASK (INTR_IO_STATUS_CHANGE_MASK | INTR_INIT_STATUS_CHANGE_MASK)
+#define ALERT_TEST_MASK \
+    (R_ALERT_TEST_RECOV_ALERT_MASK | R_ALERT_TEST_FATAL_ALERT_MASK)
+#define ALERT_SENSOR_MASK ((1u << NUM_ALERT_SENSOR_COUNT) - 1u)
+#define MANUAL_PAD_ATTR_MASK \
+    (MANUAL_PAD_ATTR_PULL_EN_MASK | MANUAL_PAD_ATTR_PULL_SELECT_MASK | \
+     MANUAL_PAD_ATTR_INPUT_DISABLE_MASK)
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_MANUAL_PAD_ATTR_3)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+/* clang-format off */
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CFG_REGWEN),
+    REG_NAME_ENTRY(ALERT_TRIG),
+    REG_NAME_ENTRY(ALERT_EN_0),
+    REG_NAME_ENTRY(ALERT_EN_1),
+    REG_NAME_ENTRY(ALERT_EN_2),
+    REG_NAME_ENTRY(ALERT_EN_3),
+    REG_NAME_ENTRY(ALERT_EN_4),
+    REG_NAME_ENTRY(ALERT_EN_5),
+    REG_NAME_ENTRY(ALERT_EN_6),
+    REG_NAME_ENTRY(ALERT_EN_7),
+    REG_NAME_ENTRY(ALERT_EN_8),
+    REG_NAME_ENTRY(ALERT_EN_9),
+    REG_NAME_ENTRY(ALERT_EN_10),
+    REG_NAME_ENTRY(FATAL_ALERT_EN),
+    REG_NAME_ENTRY(RECOV_ALERT),
+    REG_NAME_ENTRY(FATAL_ALERT),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(MANUAL_PAD_ATTR_REGWEN_0),
+    REG_NAME_ENTRY(MANUAL_PAD_ATTR_REGWEN_1),
+    REG_NAME_ENTRY(MANUAL_PAD_ATTR_REGWEN_2),
+    REG_NAME_ENTRY(MANUAL_PAD_ATTR_REGWEN_3),
+    REG_NAME_ENTRY(MANUAL_PAD_ATTR_0),
+    REG_NAME_ENTRY(MANUAL_PAD_ATTR_1),
+    REG_NAME_ENTRY(MANUAL_PAD_ATTR_2),
+    REG_NAME_ENTRY(MANUAL_PAD_ATTR_3),
+};
+/* clang-format on */
+#undef REG_NAME_ENTRY
+
+struct OtSensorEgState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ irqs[2u];
+    IbexIRQ alerts[NUM_ALERTS];
+
+    uint32_t *regs;
+};
+
+struct OtSensorEgClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static void ot_sensor_eg_update_irqs(OtSensorEgState *s)
+{
+    uint32_t levels = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->irqs); ix++) {
+        int level = (int)(bool)(levels & (1u << ix));
+        ibex_irq_set(&s->irqs[ix], level);
+    }
+}
+
+static void ot_sensor_eg_update_alerts(OtSensorEgState *s)
+{
+    uint32_t level = s->regs[R_ALERT_TEST];
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static uint64_t ot_sensor_eg_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtSensorEgState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_CFG_REGWEN:
+    case R_ALERT_TRIG:
+    case R_ALERT_EN_0 ... R_ALERT_EN_10:
+    case R_FATAL_ALERT_EN:
+    case R_RECOV_ALERT:
+    case R_FATAL_ALERT:
+    case R_MANUAL_PAD_ATTR_REGWEN_0 ... R_MANUAL_PAD_ATTR_REGWEN_3:
+    case R_MANUAL_PAD_ATTR_0 ... R_MANUAL_PAD_ATTR_3:
+        val32 = s->regs[reg];
+        break;
+    case R_STATUS:
+        if (!s->regs[reg]) {
+            /* fake init: reports initialized */
+            s->regs[reg] |= R_STATUS_AST_INIT_DONE_MASK;
+        }
+        val32 = s->regs[reg];
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_sensor_io_read_out((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_sensor_eg_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                    unsigned size)
+{
+    OtSensorEgState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_sensor_io_write((uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] &= ~val32; /* RW1C */
+        ot_sensor_eg_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_ENABLE] = val32;
+        ot_sensor_eg_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] |= val32;
+        ot_sensor_eg_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        s->regs[reg] = val32;
+        ot_sensor_eg_update_alerts(s);
+        s->regs[reg] = 0u;
+        ot_sensor_eg_update_alerts(s);
+        break;
+    case R_CFG_REGWEN:
+        val32 &= R_CFG_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_ALERT_TRIG:
+        val32 &= ALERT_SENSOR_MASK;
+        s->regs[reg] = val32;
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_ALERT_EN_0 ... R_ALERT_EN_10:
+        if (!s->regs[R_CFG_REGWEN]) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "Cannot change %s, CFG_REGWEN disabled",
+                          REG_NAME(reg));
+            break;
+        }
+        val32 &= ALERT_EN_VAL_MASK;
+        s->regs[reg] = val32;
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_FATAL_ALERT_EN:
+        if (!s->regs[R_CFG_REGWEN]) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "Cannot change %s, CFG_REGWEN disabled",
+                          REG_NAME(reg));
+            break;
+        }
+        val32 &= ALERT_SENSOR_MASK;
+        s->regs[reg] = val32;
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_RECOV_ALERT:
+        val32 &= ALERT_SENSOR_MASK;
+        s->regs[reg] = val32;
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_FATAL_ALERT:
+        val32 &= ALERT_SENSOR_MASK;
+        s->regs[reg] = val32;
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_MANUAL_PAD_ATTR_REGWEN_0 ... R_MANUAL_PAD_ATTR_REGWEN_3:
+        val32 &= MANUAL_PAD_ATTR_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_MANUAL_PAD_ATTR_0 ... R_MANUAL_PAD_ATTR_3:
+        if (!s->regs[reg - R_MANUAL_PAD_ATTR_0 + R_MANUAL_PAD_ATTR_REGWEN_0]) {
+            qemu_log_mask(LOG_GUEST_ERROR, "Cannot change %s, %s disabled",
+                          REG_NAME(reg),
+                          REG_NAME(reg - R_MANUAL_PAD_ATTR_0 +
+                                   R_MANUAL_PAD_ATTR_REGWEN_0));
+        }
+        break;
+        val32 &= MANUAL_PAD_ATTR_MASK;
+        qemu_log_mask(LOG_UNIMP, "Unimplemented register 0x%02x (%s)\n",
+                      (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+};
+
+static const MemoryRegionOps ot_sensor_eg_regs_ops = {
+    .read = &ot_sensor_eg_regs_read,
+    .write = &ot_sensor_eg_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_sensor_eg_reset_enter(Object *obj, ResetType type)
+{
+    OtSensorEgClass *c = OT_SENSOR_EG_GET_CLASS(obj);
+    OtSensorEgState *s = OT_SENSOR_EG(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->regs, 0, REGS_SIZE);
+
+    s->regs[R_CFG_REGWEN] = 0x1u;
+    for (unsigned rix = R_ALERT_EN_0; rix <= R_ALERT_EN_10; rix++) {
+        s->regs[rix] = 0x6u;
+    }
+    for (unsigned rix = R_MANUAL_PAD_ATTR_REGWEN_0;
+         rix <= R_MANUAL_PAD_ATTR_REGWEN_3; rix++) {
+        s->regs[rix] = 0x1u;
+    }
+
+    ot_sensor_eg_update_irqs(s);
+    ot_sensor_eg_update_alerts(s);
+}
+
+static void ot_sensor_eg_init(Object *obj)
+{
+    OtSensorEgState *s = OT_SENSOR_EG(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_sensor_eg_regs_ops, s,
+                          TYPE_OT_SENSOR_EG, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->irqs); ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+}
+
+static void ot_sensor_eg_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtSensorEgClass *sc = OT_SENSOR_EG_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_sensor_eg_reset_enter, NULL,
+                                       NULL, &sc->parent_phases);
+}
+
+static const TypeInfo ot_sensor_eg_info = {
+    .name = TYPE_OT_SENSOR_EG,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtSensorEgState),
+    .instance_init = &ot_sensor_eg_init,
+    .class_size = sizeof(OtSensorEgClass),
+    .class_init = &ot_sensor_eg_class_init,
+};
+
+static void ot_sensor_eg_register_types(void)
+{
+    type_register_static(&ot_sensor_eg_info);
+}
+
+type_init(ot_sensor_eg_register_types);
diff --git a/hw/opentitan/ot_soc_dbg_ctrl.c b/hw/opentitan/ot_soc_dbg_ctrl.c
new file mode 100644
index 0000000000000..d304890028f73
--- /dev/null
+++ b/hw/opentitan/ot_soc_dbg_ctrl.c
@@ -0,0 +1,1009 @@
+/*
+ * QEMU OpenTitan SoC Debug Controller
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Based on OpenTitan c5507b4cdc
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_lc_ctrl.h"
+#include "hw/opentitan/ot_pwrmgr.h"
+#include "hw/opentitan/ot_soc_dbg_ctrl.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_gpio.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+#define NUM_ALERTS 2u
+
+/* clang-format off */
+
+/*
+ * registers on core bus
+ * note: use shared register definition to avoid defining unreadable constants
+ */
+REG32(CORE_ALERT_TEST, 0x00u)
+    FIELD(CORE_ALERT_TEST, FATAL_FAULT, 0u, 1u)
+    FIELD(CORE_ALERT_TEST, RECOV_CTRL_UPDATE_ERR, 1u, 1u)
+REG32(CORE_DEBUG_POLICY_VALID_SHADOWED, 0x04u)
+    SHARED_FIELD(DEBUG_POLICY_VALID, 0u, OT_MULTIBITBOOL4_WIDTH)
+REG32(CORE_DEBUG_POLICY_CATEGORY_SHADOWED, 0x08u)
+    SHARED_FIELD(DEBUG_POLICY_CATEGORY, 0u, 7u)
+REG32(CORE_DEBUG_POLICY_RELOCKED, 0x0cu)
+    SHARED_FIELD(DEBUG_POLICY_RELOCKED, 0u, OT_MULTIBITBOOL4_WIDTH)
+REG32(CORE_TRACE_DEBUG_POLICY_CATEGORY, 0x10u)
+    SHARED_FIELD(TRACE_DEBUG_POLICY_CATEGORY, 0u, 7u)
+REG32(CORE_TRACE_DEBUG_POLICY_VALID_RELOCKED, 0x14u)
+    SHARED_FIELD(TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID, 0u,
+                 OT_MULTIBITBOOL4_WIDTH)
+    SHARED_FIELD(TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED, 4u,
+                 OT_MULTIBITBOOL4_WIDTH)
+REG32(CORE_STATUS, 0x18u)
+    SHARED_FIELD(AUTH_DEBUG_INTENT_SET, 0u, 1u)
+    SHARED_FIELD(AUTH_WINDOW_OPEN, 4u, 1u)
+    SHARED_FIELD(AUTH_WINDOW_CLOSED, 5u, 1u)
+    SHARED_FIELD(AUTH_UNLOCK_SUCCESS, 6u, 1u)
+    SHARED_FIELD(AUTH_UNLOCK_FAILED, 7u, 1u)
+
+/* registers reachable from JTAG */
+REG32(JTAG_TRACE_DEBUG_POLICY_CATEGORY, 0x00u)
+REG32(JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED, 0x04u)
+REG32(JTAG_CONTROL, 0x08u)
+    FIELD(JTAG_CONTROL, BOOT_CONTINUE, 0u, 1u)
+REG32(JTAG_STATUS, 0x0cu)
+REG32(JTAG_BOOT_STATUS, 0x10u)
+    FIELD(JTAG_BOOT_STATUS, MAIN_CLK_STATUS, 0u, 1u)
+    FIELD(JTAG_BOOT_STATUS, IO_CLK_STATUS, 1u, 1u)
+    FIELD(JTAG_BOOT_STATUS, OTP_DONE, 2u, 1u)
+    FIELD(JTAG_BOOT_STATUS, LC_DONE, 3u, 1u)
+    FIELD(JTAG_BOOT_STATUS, CPU_FETCH_EN, 4u, 1u)
+    FIELD(JTAG_BOOT_STATUS, HALT_FSM_STATE, 5u, 6u)
+    FIELD(JTAG_BOOT_STATUS, BOOT_GREENLIGHT_DONE, 11u, 3u)
+    FIELD(JTAG_BOOT_STATUS, BOOT_GREENLIGHT_GOOD, 14u, 3u)
+REG32(JTAG_TRACE_SOC_DBG_STATE, 0x14u)
+
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_CORE_LAST_REG (R_CORE_STATUS)
+#define REGS_CORE_COUNT (R_CORE_LAST_REG + 1u)
+#define REGS_CORE_SIZE  (REGS_CORE_COUNT * sizeof(uint32_t))
+
+#define R_JTAG_LAST_REG (R_JTAG_TRACE_SOC_DBG_STATE)
+#define REGS_JTAG_COUNT (R_JTAG_LAST_REG + 1u)
+#define REGS_JTAG_SIZE  (REGS_JTAG_COUNT * sizeof(uint32_t))
+
+#define CORE_ALERT_TEST_WMASK \
+    (R_CORE_ALERT_TEST_FATAL_FAULT_MASK | \
+     R_CORE_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_MASK)
+#define CORE_STATUS_WMASK \
+    (AUTH_DEBUG_INTENT_SET_MASK | AUTH_WINDOW_OPEN_MASK | \
+     AUTH_WINDOW_CLOSED_MASK | AUTH_UNLOCK_SUCCESS_MASK | \
+     AUTH_UNLOCK_FAILED_MASK)
+#define BOOT_ROM_MASK \
+    ((1u << (R_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_DONE_LENGTH)) - 1u)
+
+enum {
+    CONTINUE_CPU_BOOT_GOOD,
+    CONTINUE_CPU_BOOT_DONE,
+    CONTINUE_CPU_BOOT_COUNT,
+} OtSoCDbgContinueCpuBoot;
+
+typedef enum {
+    ST_IDLE,
+    ST_CHECK_LC_STATE,
+    ST_WAIT4DFT_EN,
+    ST_CHECK_HALT_PIN,
+    ST_CHECK_JTAG_GO,
+    ST_HALT_DONE,
+    ST_COUNT,
+} OtSoCDbgCtrlFsmState;
+
+typedef enum {
+    ALERT_FATAL,
+    ALERT_RECOV,
+    ALERT_COUNT,
+} OtSoCDbgAlert;
+
+typedef enum {
+    ALERT_RECOV_POLICY_VALID,
+    ALERT_RECOV_POLICY_CATEGORY,
+    ALERT_RECOV_COUNT,
+} OtSoCDbgRecovAlert;
+
+typedef enum {
+    OT_SOC_DBG_CATEGORY_LOCKED = 0b1010000,
+    OT_SOC_DBG_CATEGORY_2 = 0b1001101,
+    OT_SOC_DBG_CATEGORY_3 = 0b0001010,
+    OT_SOC_DBG_CATEGORY_4 = 0b1100011,
+} OtSocDbgCategory;
+
+typedef struct {
+    /* can be any value, comes either from a register or local value */
+    uint8_t cat;
+    /* can be any 4-bit value, from a register or local value */
+    ot_mb4_t relocked;
+    /* only local, a regular bool is sufficient */
+    bool valid;
+} OtSocDbgPolicy;
+
+typedef struct {
+    struct {
+        OtShadowReg valid;
+        OtShadowReg category;
+        uint32_t relocked;
+    } debug_policy;
+    uint32_t status;
+} OtSoCDbgCtrlRegs;
+
+struct OtSoCDbgCtrlState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion core;
+    MemoryRegion jtag;
+    IbexIRQ alerts[ALERT_COUNT];
+    IbexIRQ debug_policy;
+    IbexIRQ continue_cpu_boot[CONTINUE_CPU_BOOT_COUNT];
+    QEMUBH *fsm_tick_bh;
+
+    OtSoCDbgCtrlRegs regs;
+    OtSoCDbgCtrlFsmState fsm_state;
+    OtSoCDbgState soc_dbg_state;
+    OtSocDbgPolicy soc_dbg_policy; /* calculated policy */
+    unsigned fsm_tick_count;
+    OtPwrMgrBootStatus pwr_boot_status;
+    uint16_t lc_broadcast_bm; /* OtLcCtrlBroadcast fields */
+    uint8_t fatal_alert_bm;
+    uint8_t recov_alert_bm;
+    bool halt_cpu_boot;
+    bool boot_continue;
+
+    char *ot_id;
+    OtLcCtrlState *lc_ctrl;
+    bool dft_ignore;
+};
+
+struct OtSoCDbgCtrlClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+/* clang-format off */
+static const uint8_t OT_SOC_DBG_FSM_STATE[ST_COUNT] = {
+    [ST_IDLE] = 0b101000u,
+    [ST_CHECK_LC_STATE] = 0b011101u,
+    [ST_WAIT4DFT_EN] = 0b000110u,
+    [ST_CHECK_HALT_PIN] = 0b110011u,
+    [ST_CHECK_JTAG_GO] = 0b111110u,
+    [ST_HALT_DONE] = 0b100101u,
+};
+/* clang-format on */
+
+static_assert(ALERT_COUNT == NUM_ALERTS, "Invalid alert count");
+static_assert(sizeof(OtSocDbgDebugPolicy) == sizeof(int),
+              "Invalid OtSocDbgDebugPolicy size");
+static_assert(OT_SOC_DBG_ST_COUNT == OT_LC_SOC_DBG_STATE_COUNT,
+              "Invalid SoC Debug state count");
+
+#define ROM_MASK ((1u << (R_BOOT_STATUS_ROM_CTRL_DONE_LENGTH - 1u)) - 1u)
+
+#define REG_NAME(_kind_, _reg_) \
+    ((((_reg_) < REGS_##_kind_##_COUNT) && REG_##_kind_##_NAMES[_reg_]) ? \
+         REG_##_kind_##_NAMES[_reg_] : \
+         "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+
+static const char *REG_CORE_NAMES[REGS_CORE_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(CORE_ALERT_TEST),
+    REG_NAME_ENTRY(CORE_DEBUG_POLICY_VALID_SHADOWED),
+    REG_NAME_ENTRY(CORE_DEBUG_POLICY_CATEGORY_SHADOWED),
+    REG_NAME_ENTRY(CORE_DEBUG_POLICY_RELOCKED),
+    REG_NAME_ENTRY(CORE_TRACE_DEBUG_POLICY_CATEGORY),
+    REG_NAME_ENTRY(CORE_TRACE_DEBUG_POLICY_VALID_RELOCKED),
+    REG_NAME_ENTRY(CORE_STATUS),
+    /* clang-format on */
+};
+
+static const char *REG_JTAG_NAMES[REGS_JTAG_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(JTAG_TRACE_DEBUG_POLICY_CATEGORY),
+    REG_NAME_ENTRY(JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED),
+    REG_NAME_ENTRY(JTAG_CONTROL),
+    REG_NAME_ENTRY(JTAG_STATUS),
+    REG_NAME_ENTRY(JTAG_BOOT_STATUS),
+    REG_NAME_ENTRY(JTAG_TRACE_SOC_DBG_STATE),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+#define LC_NAME_ENTRY(_st_) [_st_] = stringify(_st_)
+static const char *LC_BROADCAST_NAMES[] = {
+    /* clang-format off */
+    LC_NAME_ENTRY(OT_LC_RAW_TEST_RMA),
+    LC_NAME_ENTRY(OT_LC_DFT_EN),
+    LC_NAME_ENTRY(OT_LC_NVM_DEBUG_EN),
+    LC_NAME_ENTRY(OT_LC_HW_DEBUG_EN),
+    LC_NAME_ENTRY(OT_LC_CPU_EN),
+    LC_NAME_ENTRY(OT_LC_KEYMGR_EN),
+    LC_NAME_ENTRY(OT_LC_ESCALATE_EN),
+    LC_NAME_ENTRY(OT_LC_CHECK_BYP_EN),
+    LC_NAME_ENTRY(OT_LC_CREATOR_SEED_SW_RW_EN),
+    LC_NAME_ENTRY(OT_LC_OWNER_SEED_SW_RW_EN),
+    LC_NAME_ENTRY(OT_LC_ISO_PART_SW_RD_EN),
+    LC_NAME_ENTRY(OT_LC_ISO_PART_SW_WR_EN),
+    LC_NAME_ENTRY(OT_LC_SEED_HW_RD_EN),
+    LC_NAME_ENTRY(OT_LC_RMA),
+    /* clang-format on */
+};
+#undef LC_NAME_ENTRY
+
+#define LC_BCAST_NAME(_bit_) \
+    (((unsigned)(_bit_)) < ARRAY_SIZE(LC_BROADCAST_NAMES) ? \
+         LC_BROADCAST_NAMES[(_bit_)] : \
+         "?")
+
+#define SOC_DBG_NAME_ENTRY(_st_) [OT_SOC_DBG_ST_##_st_] = stringify(_st_)
+static const char *SOC_DBG_NAMES[] = {
+    /* clang-format off */
+    SOC_DBG_NAME_ENTRY(BLANK),
+    SOC_DBG_NAME_ENTRY(PRE_PROD),
+    SOC_DBG_NAME_ENTRY(PROD),
+    /* clang-format on */
+};
+#undef SOC_DBG_NAME_ENTRY
+
+#define SOC_DBG_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(SOC_DBG_NAMES) ? SOC_DBG_NAMES[(_st_)] : \
+                                                      "?")
+
+#define STATE_NAME_ENTRY(_st_) [ST_##_st_] = stringify(_st_)
+static const char *STATE_NAMES[ST_COUNT] = {
+    /* clang-format off */
+    STATE_NAME_ENTRY(IDLE),
+    STATE_NAME_ENTRY(CHECK_LC_STATE),
+    STATE_NAME_ENTRY(WAIT4DFT_EN),
+    STATE_NAME_ENTRY(CHECK_HALT_PIN),
+    STATE_NAME_ENTRY(CHECK_JTAG_GO),
+    STATE_NAME_ENTRY(HALT_DONE),
+    /* clang-format on */
+};
+#undef STATE_NAME_ENTRY
+#define STATE_NAME(_st_) \
+    ((_st_) >= 0 && (_st_) < ARRAY_SIZE(STATE_NAMES) ? STATE_NAMES[(_st_)] : \
+                                                       "?")
+#define CHANGE_STATE(_s_, _st_) \
+    ot_soc_dbg_ctrl_change_state_line(_s_, ST_##_st_, __LINE__)
+#define SCHEDULE_FSM(_s_) ot_soc_dbg_ctrl_schedule_fsm(_s_, __func__, __LINE__)
+
+static void ot_soc_dbg_ctrl_change_state_line(
+    OtSoCDbgCtrlState *s, OtSoCDbgCtrlFsmState state, int line)
+{
+    trace_ot_soc_dbg_ctrl_change_state(s->ot_id, line, STATE_NAME(s->fsm_state),
+                                       s->fsm_state, STATE_NAME(state), state);
+
+    s->fsm_state = state;
+}
+
+static inline bool
+ot_soc_dbg_ctrl_lc_test(const OtSoCDbgCtrlState *s, OtLcCtrlBroadcast lc_bc)
+{
+    return (bool)(s->lc_broadcast_bm & (1u << (unsigned)lc_bc));
+}
+
+static void
+ot_soc_dbg_ctrl_update_alerts(OtSoCDbgCtrlState *s, uint32_t test_bm)
+{
+    bool alert;
+
+    alert = (bool)s->fatal_alert_bm |
+            (bool)(test_bm & R_CORE_ALERT_TEST_FATAL_FAULT_MASK);
+    ibex_irq_set(&s->alerts[ALERT_FATAL], (int)alert);
+
+    alert = (bool)s->recov_alert_bm |
+            (bool)(test_bm & R_CORE_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_MASK);
+    ibex_irq_set(&s->alerts[ALERT_RECOV], (int)alert);
+
+    if (test_bm) {
+        /* alert test is transient */
+        ibex_irq_set(&s->alerts[ALERT_FATAL], (int)(bool)s->fatal_alert_bm);
+        ibex_irq_set(&s->alerts[ALERT_RECOV], (int)(bool)s->recov_alert_bm);
+    }
+}
+
+static void
+ot_soc_dbg_ctrl_schedule_fsm(OtSoCDbgCtrlState *s, const char *func, int line)
+{
+    s->fsm_tick_count += 1u;
+    trace_ot_soc_dbg_ctrl_schedule_fsm(s->ot_id, func, line, s->fsm_tick_count);
+    qemu_bh_schedule(s->fsm_tick_bh);
+}
+
+static void ot_soc_dbg_ctrl_tick_fsm(OtSoCDbgCtrlState *s)
+{
+    bool cpu_boot_done = false;
+
+    trace_ot_soc_dbg_ctrl_tick_fsm(s->ot_id, STATE_NAME(s->fsm_state),
+                                   s->lc_broadcast_bm, s->dft_ignore,
+                                   s->pwr_boot_status.lc_done, s->halt_cpu_boot,
+                                   s->boot_continue);
+
+    switch (s->fsm_state) {
+    case ST_IDLE:
+        if (s->pwr_boot_status.lc_done) {
+            CHANGE_STATE(s, CHECK_LC_STATE);
+        }
+        break;
+    case ST_CHECK_LC_STATE:
+        if ((s->lc_broadcast_bm & (1u << OT_LC_RAW_TEST_RMA)) &&
+            !s->dft_ignore) {
+            CHANGE_STATE(s, WAIT4DFT_EN);
+        } else {
+            CHANGE_STATE(s, HALT_DONE);
+        }
+        break;
+    case ST_WAIT4DFT_EN:
+        if (s->lc_broadcast_bm & (1u << OT_LC_DFT_EN)) {
+            CHANGE_STATE(s, CHECK_HALT_PIN);
+        }
+        break;
+    case ST_CHECK_HALT_PIN:
+        if (s->halt_cpu_boot) {
+            CHANGE_STATE(s, CHECK_JTAG_GO);
+        } else {
+            CHANGE_STATE(s, HALT_DONE);
+        }
+        break;
+    case ST_CHECK_JTAG_GO:
+        if (s->boot_continue) {
+            CHANGE_STATE(s, HALT_DONE);
+        }
+        break;
+    case ST_HALT_DONE:
+        cpu_boot_done = true;
+        break;
+    default:
+        /*
+         * it does not seem there is a special state for this case, i.e.
+         * the FSM does not enter a special error state, it only raises
+         * an alert.
+         */
+        ibex_irq_set(&s->alerts[ALERT_FATAL], (int)true);
+        return;
+    }
+
+    /* as with PwrMgr, use simple boolean value, not MuBi4 */
+    int cpu_boot_done_i = (int)cpu_boot_done;
+    if (ibex_irq_get_level(&s->continue_cpu_boot[CONTINUE_CPU_BOOT_DONE]) !=
+        cpu_boot_done_i) {
+        trace_ot_soc_dbg_ctrl_cpu_boot_done(s->ot_id, cpu_boot_done_i);
+    }
+    ibex_irq_set(&s->continue_cpu_boot[CONTINUE_CPU_BOOT_DONE],
+                 cpu_boot_done_i);
+}
+
+static void ot_soc_dbg_ctrl_update_policy(OtSoCDbgCtrlState *s)
+{
+    OtSocDbgPolicy policy;
+
+    ot_mb4_t relocked =
+        (ot_mb4_t)SHARED_FIELD_EX32(s->regs.debug_policy.relocked,
+                                    DEBUG_POLICY_RELOCKED);
+
+    switch (s->soc_dbg_state) {
+    case OT_SOC_DBG_ST_BLANK:
+        policy.cat = ot_soc_dbg_ctrl_lc_test(s, OT_LC_DFT_EN) ||
+                             ot_soc_dbg_ctrl_lc_test(s, OT_LC_HW_DEBUG_EN) ?
+                         OT_SOC_DBG_CATEGORY_4 :
+                         OT_SOC_DBG_CATEGORY_LOCKED;
+        policy.valid = (bool)s->pwr_boot_status.lc_done;
+        policy.relocked = OT_MULTIBITBOOL4_FALSE;
+        break;
+    case OT_SOC_DBG_ST_PRE_PROD:
+        policy.cat = OT_SOC_DBG_CATEGORY_4;
+        policy.valid = (bool)s->pwr_boot_status.lc_done;
+        policy.relocked = OT_MULTIBITBOOL4_FALSE;
+        break;
+    case OT_SOC_DBG_ST_PROD:
+        if (ot_soc_dbg_ctrl_lc_test(s, OT_LC_RMA)) {
+            policy.cat = OT_SOC_DBG_CATEGORY_4;
+            policy.valid = true;
+            policy.relocked = OT_MULTIBITBOOL4_FALSE;
+        } else if (ot_soc_dbg_ctrl_lc_test(s, OT_LC_CPU_EN)) {
+            policy.cat = ot_shadow_reg_peek(&s->regs.debug_policy.category);
+            policy.valid = true;
+            policy.relocked = relocked;
+        } else {
+            policy.cat = OT_SOC_DBG_CATEGORY_LOCKED;
+            policy.valid = (bool)s->pwr_boot_status.lc_done;
+            policy.relocked = OT_MULTIBITBOOL4_FALSE;
+        }
+        break;
+    default:
+        policy.cat = OT_SOC_DBG_CATEGORY_LOCKED;
+        policy.valid = false;
+        policy.relocked = OT_MULTIBITBOOL4_FALSE;
+        break;
+    }
+
+    /* detect valid rising edge */
+    if (policy.valid && !s->soc_dbg_policy.valid) {
+        /* decode the values into the combined output signal */
+        OtSocDbgDebugPolicy debug_policy = {
+            .cat_bm = 0u,
+            .relocked = policy.relocked == OT_MULTIBITBOOL4_TRUE,
+        };
+
+        if (policy.cat == OT_SOC_DBG_CATEGORY_4) {
+            debug_policy.cat_bm |= 1u << 4u;
+        }
+        if (!relocked) {
+            if (policy.cat == OT_SOC_DBG_CATEGORY_3 ||
+                (debug_policy.cat_bm & (1u << 4u))) {
+                debug_policy.cat_bm |= 1u << 3u;
+            }
+            if (policy.cat == OT_SOC_DBG_CATEGORY_2 ||
+                (debug_policy.cat_bm & ((1u << 4u) | (1u << 3u)))) {
+                debug_policy.cat_bm |= 1u << 2u;
+            }
+        }
+
+        int prev_policy = ibex_irq_get_level(&s->debug_policy);
+        if (prev_policy != debug_policy.i32) {
+            trace_ot_soc_dbg_ctrl_update_policy(s->ot_id,
+                                                SOC_DBG_NAME(s->soc_dbg_state),
+                                                STATE_NAME(s->fsm_state),
+                                                debug_policy.cat_bm, relocked);
+        }
+        ibex_irq_set(&s->debug_policy, debug_policy.i32);
+
+        /* store current policy for edge detection and trace registers */
+        s->soc_dbg_policy = policy;
+    } else {
+        /* store only valid level for edge detection */
+        s->soc_dbg_policy.valid = policy.valid;
+    }
+}
+
+static void ot_soc_dbg_ctrl_fsm_tick(void *opaque)
+{
+    OtSoCDbgCtrlState *s = opaque;
+
+    OtSoCDbgCtrlFsmState fsm_state = s->fsm_state;
+    g_assert(s->fsm_tick_count);
+    while (s->fsm_tick_count) {
+        ot_soc_dbg_ctrl_update_policy(s);
+        s->fsm_tick_count--;
+        ot_soc_dbg_ctrl_tick_fsm(s);
+    }
+    if (fsm_state != s->fsm_state) {
+        /* schedule FSM update once more if its state has changed */
+        SCHEDULE_FSM(s);
+    }
+}
+
+
+static void ot_soc_dbg_ctrl_halt_cpu_boot(void *opaque, int n, int level)
+{
+    OtSoCDbgCtrlState *s = opaque;
+
+    g_assert(n == 0);
+
+    trace_ot_soc_dbg_ctrl_rcv(s->ot_id, "HALT_CPU_BOOT", 0,
+                              ibex_gpio_repr(level));
+
+    /* expect an Ibex GPIO signal */
+    g_assert(ibex_gpio_check(level));
+
+    /* active low */
+    s->halt_cpu_boot = !ibex_gpio_level(level);
+
+    SCHEDULE_FSM(s);
+}
+
+static void ot_soc_dbg_ctrl_lc_broadcast(void *opaque, int n, int level)
+{
+    OtSoCDbgCtrlState *s = opaque;
+
+    unsigned bcast = (unsigned)n;
+    g_assert(bcast < OT_LC_BROADCAST_COUNT);
+    g_assert(!ibex_gpio_check(level));
+
+    trace_ot_soc_dbg_ctrl_rcv(s->ot_id, LC_BCAST_NAME(bcast), bcast,
+                              level ? '1' : '0');
+
+    switch (n) {
+    case OT_LC_RAW_TEST_RMA:
+    case OT_LC_DFT_EN:
+    case OT_LC_HW_DEBUG_EN:
+    case OT_LC_CPU_EN:
+        if (level) {
+            s->lc_broadcast_bm |= (1u << bcast);
+        } else {
+            s->lc_broadcast_bm &= (~1u << bcast);
+        }
+        break;
+    /* NOLINTBEGIN(bugprone-branch-clone) */
+    case OT_LC_NVM_DEBUG_EN:
+    case OT_LC_KEYMGR_EN:
+    case OT_LC_ISO_PART_SW_RD_EN:
+    case OT_LC_ISO_PART_SW_WR_EN:
+    case OT_LC_OWNER_SEED_SW_RW_EN:
+        /* do not seem to be routed... */
+        break;
+    case OT_LC_CREATOR_SEED_SW_RW_EN:
+    case OT_LC_SEED_HW_RD_EN:
+    case OT_LC_ESCALATE_EN:
+    case OT_LC_CHECK_BYP_EN:
+        /* verbatim from RTL: "Use unused signals to make lint clean" */
+        break;
+    /* NOLINTEND(bugprone-branch-clone) */
+    default:
+        g_assert_not_reached();
+    }
+
+    SCHEDULE_FSM(s);
+}
+
+static void ot_soc_dbg_ctrl_boot_status(void *opaque, int n, int level)
+{
+    OtSoCDbgCtrlState *s = opaque;
+
+    g_assert(n == 0);
+
+    OtPwrMgrBootStatus bs = { .i32 = level };
+
+    g_assert(bs.rom_mask != 0);
+    g_assert(!(bs.rom_mask & ~BOOT_ROM_MASK));
+
+    trace_ot_soc_dbg_ctrl_boot_status(s->ot_id, (bool)bs.main_clk_status,
+                                      (bool)bs.io_clk_status, (bool)bs.otp_done,
+                                      (bool)bs.lc_done, (bool)bs.cpu_fetch_en,
+                                      bs.rom_done & bs.rom_mask,
+                                      bs.rom_good & bs.rom_mask);
+    s->pwr_boot_status = bs;
+
+    SCHEDULE_FSM(s);
+}
+
+static uint32_t ot_soc_dbg_ctrl_get_jtag_boot_status(const OtSoCDbgCtrlState *s)
+{
+    const OtPwrMgrBootStatus *bs = &s->pwr_boot_status;
+
+    g_assert(s->fsm_state < ST_COUNT);
+
+    uint32_t bs_bm = 0;
+
+    bs_bm = FIELD_DP32(bs_bm, JTAG_BOOT_STATUS, MAIN_CLK_STATUS,
+                       bs->main_clk_status);
+    bs_bm =
+        FIELD_DP32(bs_bm, JTAG_BOOT_STATUS, IO_CLK_STATUS, bs->io_clk_status);
+    bs_bm = FIELD_DP32(bs_bm, JTAG_BOOT_STATUS, OTP_DONE, bs->otp_done);
+    bs_bm = FIELD_DP32(bs_bm, JTAG_BOOT_STATUS, LC_DONE, bs->lc_done);
+    bs_bm = FIELD_DP32(bs_bm, JTAG_BOOT_STATUS, BOOT_GREENLIGHT_DONE,
+                       bs->rom_done & bs->rom_mask);
+    bs_bm = FIELD_DP32(bs_bm, JTAG_BOOT_STATUS, BOOT_GREENLIGHT_GOOD,
+                       bs->rom_good & bs->rom_mask);
+    bs_bm = FIELD_DP32(bs_bm, JTAG_BOOT_STATUS, CPU_FETCH_EN, bs->cpu_fetch_en);
+    bs_bm = FIELD_DP32(bs_bm, JTAG_BOOT_STATUS, HALT_FSM_STATE,
+                       (uint32_t)OT_SOC_DBG_FSM_STATE[s->fsm_state]);
+
+    return bs_bm;
+}
+
+static void ot_soc_dbg_ctrl_soc_dbg_state(void *opaque, int n, int level)
+{
+    OtSoCDbgCtrlState *s = opaque;
+
+    g_assert(n == 0);
+    g_assert(!ibex_gpio_check(level));
+
+    switch (level) {
+    case 0:
+        s->soc_dbg_state = OT_SOC_DBG_ST_BLANK;
+        break;
+    case 1:
+        s->soc_dbg_state = OT_SOC_DBG_ST_PRE_PROD;
+        break;
+    case 2:
+        s->soc_dbg_state = OT_SOC_DBG_ST_PROD;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    trace_ot_soc_dbg_ctrl_rcv(s->ot_id, "SOC_DBG_STATE", 0,
+                              (char)('0' + level));
+
+    trace_ot_soc_dbg_ctrl_soc_dbg_state(s->ot_id,
+                                        SOC_DBG_NAME(s->soc_dbg_state));
+
+    SCHEDULE_FSM(s);
+}
+
+static uint64_t
+ot_soc_dbg_ctrl_core_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtSoCDbgCtrlState *s = opaque;
+    (void)size;
+    uint32_t val32 = 0;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_CORE_DEBUG_POLICY_VALID_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->regs.debug_policy.valid);
+        break;
+    case R_CORE_DEBUG_POLICY_CATEGORY_SHADOWED:
+        val32 = ot_shadow_reg_read(&s->regs.debug_policy.category);
+        break;
+    case R_CORE_DEBUG_POLICY_RELOCKED:
+        val32 = s->regs.debug_policy.relocked;
+        break;
+    case R_CORE_TRACE_DEBUG_POLICY_CATEGORY:
+        val32 = (uint32_t)s->soc_dbg_policy.cat;
+        break;
+    case R_CORE_TRACE_DEBUG_POLICY_VALID_RELOCKED:
+        val32 = (uint32_t)s->soc_dbg_policy.relocked;
+        break;
+    case R_CORE_STATUS:
+        val32 = s->regs.status;
+        break;
+    case R_CORE_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(CORE, reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_soc_dbg_ctrl_core_io_read_out(s->ot_id, (uint32_t)addr,
+                                           REG_NAME(CORE, reg), val32, pc);
+
+    return (uint32_t)val32;
+}
+
+static void ot_soc_dbg_ctrl_core_write(void *opaque, hwaddr addr,
+                                       uint64_t value, unsigned size)
+{
+    OtSoCDbgCtrlState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)value;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_soc_dbg_ctrl_core_io_write(s->ot_id, (uint32_t)addr,
+                                        REG_NAME(CORE, reg), val32, pc);
+
+    switch (reg) {
+    case R_CORE_ALERT_TEST:
+        val32 &= CORE_ALERT_TEST_WMASK;
+        ot_soc_dbg_ctrl_update_alerts(s, val32);
+        break;
+    case R_CORE_DEBUG_POLICY_VALID_SHADOWED:
+        val32 &= DEBUG_POLICY_VALID_MASK;
+        switch (ot_shadow_reg_write(&s->regs.debug_policy.valid, val32)) {
+        case OT_SHADOW_REG_STAGED:
+        case OT_SHADOW_REG_COMMITTED:
+            s->recov_alert_bm &= ~(1u << ALERT_RECOV_POLICY_VALID);
+            break;
+        case OT_SHADOW_REG_ERROR:
+            s->recov_alert_bm |= 1u << ALERT_RECOV_POLICY_VALID;
+        default:
+            break;
+        }
+        ot_soc_dbg_ctrl_update_alerts(s, 0u);
+        break;
+    case R_CORE_DEBUG_POLICY_CATEGORY_SHADOWED:
+        val32 &= DEBUG_POLICY_CATEGORY_MASK;
+        if (ot_shadow_reg_peek(&s->regs.debug_policy.valid) ==
+            OT_MULTIBITBOOL4_FALSE) {
+            /* debug policy not yet validated, can still update it */
+            switch (
+                ot_shadow_reg_write(&s->regs.debug_policy.category, val32)) {
+            case OT_SHADOW_REG_STAGED:
+            case OT_SHADOW_REG_COMMITTED:
+                s->recov_alert_bm &= ~(1u << ALERT_RECOV_POLICY_CATEGORY);
+                break;
+            case OT_SHADOW_REG_ERROR:
+                s->recov_alert_bm |= 1u << ALERT_RECOV_POLICY_CATEGORY;
+            default:
+                break;
+            }
+            ot_soc_dbg_ctrl_update_alerts(s, 0u);
+        }
+        break;
+    case R_CORE_DEBUG_POLICY_RELOCKED:
+        val32 &= DEBUG_POLICY_RELOCKED_MASK;
+        s->regs.debug_policy.relocked = val32;
+        break;
+    case R_CORE_TRACE_DEBUG_POLICY_CATEGORY:
+    case R_CORE_TRACE_DEBUG_POLICY_VALID_RELOCKED:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(CORE, reg));
+        break;
+    case R_CORE_STATUS:
+        /*
+         * this register does nothing but masks some bits and make them
+         * readable from JTAG side.
+         */
+        val32 &= CORE_STATUS_WMASK;
+        s->regs.status = val32;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static uint64_t
+ot_soc_dbg_ctrl_jtag_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtSoCDbgCtrlState *s = opaque;
+    (void)size;
+    uint32_t val32 = 0;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_JTAG_TRACE_DEBUG_POLICY_CATEGORY:
+        val32 = (uint32_t)s->soc_dbg_policy.cat;
+        break;
+    case R_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED:
+        val32 = (uint32_t)s->soc_dbg_policy.relocked;
+        break;
+    case R_JTAG_CONTROL:
+        val32 = s->boot_continue ? R_JTAG_CONTROL_BOOT_CONTINUE_MASK : 0u;
+        break;
+    case R_JTAG_STATUS:
+        val32 = s->regs.status;
+        break;
+    case R_JTAG_BOOT_STATUS:
+        if (ot_soc_dbg_ctrl_lc_test(s, OT_LC_DFT_EN)) {
+            val32 = ot_soc_dbg_ctrl_get_jtag_boot_status(s);
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: BootStatus disabled (no DFT)\n", __func__,
+                          s->ot_id);
+            val32 = 0;
+        }
+        break;
+    case R_JTAG_TRACE_SOC_DBG_STATE:
+        if (ot_soc_dbg_ctrl_lc_test(s, OT_LC_DFT_EN)) {
+            OtLcCtrlClass *lc = OT_LC_CTRL_GET_CLASS(s->lc_ctrl);
+            val32 =
+                lc->get_soc_dbg_state(s->lc_ctrl, (unsigned)s->soc_dbg_state);
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: SocDbgState disabled (no DFT)\n", __func__,
+                          s->ot_id);
+            val32 = 0u;
+        }
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    trace_ot_soc_dbg_ctrl_jtag_io_read_out(s->ot_id, (uint32_t)addr,
+                                           REG_NAME(JTAG, reg), val32);
+
+    return (uint32_t)val32;
+}
+
+static void ot_soc_dbg_ctrl_jtag_write(void *opaque, hwaddr addr,
+                                       uint64_t value, unsigned size)
+{
+    OtSoCDbgCtrlState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)value;
+
+    hwaddr reg = R32_OFF(addr);
+
+    trace_ot_soc_dbg_ctrl_jtag_io_write(s->ot_id, (uint32_t)addr,
+                                        REG_NAME(JTAG, reg), val32);
+
+    switch (reg) {
+    case R_JTAG_CONTROL:
+        s->boot_continue = (bool)(val32 & R_JTAG_CONTROL_BOOT_CONTINUE_MASK);
+        SCHEDULE_FSM(s);
+        break;
+    case R_JTAG_TRACE_DEBUG_POLICY_CATEGORY:
+    case R_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED:
+    case R_JTAG_STATUS:
+    case R_JTAG_BOOT_STATUS:
+    case R_JTAG_TRACE_SOC_DBG_STATE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(JTAG, reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s, Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static const Property ot_soc_dbg_ctrl_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtSoCDbgCtrlState, ot_id),
+    DEFINE_PROP_LINK("lc-ctrl", OtSoCDbgCtrlState, lc_ctrl, TYPE_OT_LC_CTRL,
+                     OtLcCtrlState *),
+    DEFINE_PROP_BOOL("dft-ignore", OtSoCDbgCtrlState, dft_ignore, false),
+};
+
+static const MemoryRegionOps ot_soc_dbg_ctrl_core_ops = {
+    .read = &ot_soc_dbg_ctrl_core_read,
+    .write = &ot_soc_dbg_ctrl_core_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_soc_dbg_ctrl_jtag_ops = {
+    .read = &ot_soc_dbg_ctrl_jtag_read,
+    .write = &ot_soc_dbg_ctrl_jtag_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_soc_dbg_ctrl_reset_enter(Object *obj, ResetType type)
+{
+    OtSoCDbgCtrlClass *c = OT_SOC_DBG_CTRL_GET_CLASS(obj);
+    OtSoCDbgCtrlState *s = OT_SOC_DBG_CTRL(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    ot_shadow_reg_init(&s->regs.debug_policy.valid, OT_MULTIBITBOOL4_FALSE);
+    ot_shadow_reg_init(&s->regs.debug_policy.category,
+                       OT_SOC_DBG_CATEGORY_LOCKED);
+    s->regs.debug_policy.relocked = OT_MULTIBITBOOL4_FALSE;
+
+    ibex_irq_set(&s->continue_cpu_boot[CONTINUE_CPU_BOOT_DONE], (int)false);
+    ibex_irq_set(&s->debug_policy, 0);
+
+    memset(&s->soc_dbg_policy, 0, sizeof(s->soc_dbg_policy));
+
+    CHANGE_STATE(s, IDLE);
+    s->fsm_state = ST_IDLE;
+    s->fsm_tick_count = 0u;
+    s->pwr_boot_status.i32 = 0;
+    s->lc_broadcast_bm = 0u;
+    s->soc_dbg_state = OT_SOC_DBG_ST_PROD;
+    s->halt_cpu_boot = false;
+    s->boot_continue = false;
+    s->fatal_alert_bm = 0u;
+    s->recov_alert_bm = 0u;
+
+    ot_soc_dbg_ctrl_update_alerts(s, 0u);
+}
+
+static void ot_soc_dbg_ctrl_reset_exit(Object *obj, ResetType type)
+{
+    OtSoCDbgCtrlClass *c = OT_SOC_DBG_CTRL_GET_CLASS(obj);
+    OtSoCDbgCtrlState *s = OT_SOC_DBG_CTRL(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    qemu_bh_cancel(s->fsm_tick_bh);
+
+    /* this fake ROM signal is hardcoded to true and never updated. */
+    ibex_irq_set(&s->continue_cpu_boot[CONTINUE_CPU_BOOT_GOOD], (int)true);
+
+    ot_soc_dbg_ctrl_update_policy(s);
+
+    SCHEDULE_FSM(s);
+}
+
+static void ot_soc_dbg_ctrl_realize(DeviceState *dev, Error **errp)
+{
+    OtSoCDbgCtrlState *s = OT_SOC_DBG_CTRL(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->lc_ctrl);
+}
+
+static void ot_soc_dbg_ctrl_init(Object *obj)
+{
+    OtSoCDbgCtrlState *s = OT_SOC_DBG_CTRL(obj);
+
+    memory_region_init_io(&s->core, obj, &ot_soc_dbg_ctrl_core_ops, s,
+                          TYPE_OT_SOC_DBG_CTRL, REGS_CORE_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->core);
+
+    memory_region_init_io(&s->jtag, obj, &ot_soc_dbg_ctrl_jtag_ops, s,
+                          TYPE_OT_SOC_DBG_CTRL, REGS_JTAG_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->jtag);
+
+    for (unsigned ix = 0; ix < NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+    ibex_qdev_init_irq(obj, &s->debug_policy, OT_SOC_DBG_DEBUG_POLICY);
+    ibex_qdev_init_irqs(obj, s->continue_cpu_boot, OT_SOC_DBG_CONTINUE_CPU_BOOT,
+                        ARRAY_SIZE(s->continue_cpu_boot));
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_soc_dbg_ctrl_halt_cpu_boot,
+                            OT_SOC_DBG_HALT_CPU_BOOT, 1);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_soc_dbg_ctrl_lc_broadcast,
+                            OT_SOC_DBG_LC_BCAST, OT_LC_BROADCAST_COUNT);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_soc_dbg_ctrl_soc_dbg_state,
+                            OT_SOC_DBG_STATE, 1);
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_soc_dbg_ctrl_boot_status,
+                            OT_SOC_DBG_BOOT_STATUS, 1u);
+
+    s->fsm_tick_bh = qemu_bh_new(&ot_soc_dbg_ctrl_fsm_tick, s);
+}
+
+static void ot_soc_dbg_ctrl_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_soc_dbg_ctrl_realize;
+    device_class_set_props(dc, ot_soc_dbg_ctrl_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtSoCDbgCtrlClass *sc = OT_SOC_DBG_CTRL_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_soc_dbg_ctrl_reset_enter, NULL,
+                                       &ot_soc_dbg_ctrl_reset_exit,
+                                       &sc->parent_phases);
+}
+
+static const TypeInfo ot_soc_dbg_ctrl_info = {
+    .name = TYPE_OT_SOC_DBG_CTRL,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtSoCDbgCtrlState),
+    .instance_init = &ot_soc_dbg_ctrl_init,
+    .class_size = sizeof(OtSoCDbgCtrlClass),
+    .class_init = &ot_soc_dbg_ctrl_class_init,
+};
+
+static void ot_soc_dbg_ctrl_register_types(void)
+{
+    type_register_static(&ot_soc_dbg_ctrl_info);
+}
+
+type_init(ot_soc_dbg_ctrl_register_types);
diff --git a/hw/opentitan/ot_soc_proxy.c b/hw/opentitan/ot_soc_proxy.c
new file mode 100644
index 0000000000000..5a4632241f989
--- /dev/null
+++ b/hw/opentitan/ot_soc_proxy.c
@@ -0,0 +1,313 @@
+/*
+ * QEMU OpenTitan SocProxy
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMIT_ADDRED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note that system-side interrupts are not managed by the DOE Mailbox.
+ * Registers dedicated to system-side interrupt management are only storage
+ * space that the guest software (called the host side to get more confusing,
+ * not related to the VM host) should read and act accordingly, using other
+ * devices to signal the requester that a response is ready to be read.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_soc_proxy.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "system/memory.h"
+#include "trace.h"
+
+#define PARAM_NUM_EXTERNAL_IRQS 32u
+#define PARAM_NUM_ALERTS        29u
+
+/* clang-format off */
+
+REG32(INTR_STATE, 0x0)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+
+/* clang-format on */
+
+#define ALERT_TEST_FATAL_ALERT_INTG           0
+#define ALERT_TEST_FATAL_ALERT_EXTERNAL_BASE  1u
+#define ALERT_TEST_FATAL_ALERT_EXTERNAL_COUNT 24u
+#define ALERT_TEST_RECOV_ALERT_EXTERNAL_BASE  25u
+#define ALERT_TEST_RECOV_ALERT_EXTERNAL_COUNT 4u
+
+#define ALERT_TEST_MASK ((1u << PARAM_NUM_ALERTS) - 1u)
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_ALERT_TEST)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define INTR_COUNT PARAM_NUM_EXTERNAL_IRQS
+
+static_assert(1u + ALERT_TEST_FATAL_ALERT_EXTERNAL_COUNT +
+                      ALERT_TEST_RECOV_ALERT_EXTERNAL_COUNT ==
+                  PARAM_NUM_ALERTS,
+              "Invalid external IRQ configuration");
+static_assert(OT_SOC_PROXY_REGS_COUNT == REGS_COUNT, "Invalid regs");
+
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+
+/* clang-format off */
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+};
+/* clang-format on */
+
+#undef REG_NAME_ENTRY
+
+enum {
+    ALERT_RECOVERABLE,
+    ALERT_FATAL,
+};
+
+typedef struct {
+} OtMbxHost;
+
+struct OtSoCProxyState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ irqs[INTR_COUNT];
+    IbexIRQ alerts[PARAM_NUM_ALERTS];
+    uint32_t regs[REGS_COUNT];
+
+    char *ot_id;
+};
+
+struct OtSoCProxyClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static void ot_soc_proxy_update_irqs(OtSoCProxyState *s)
+{
+    uint32_t levels = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->irqs); ix++) {
+        int level = (int)(bool)(levels & (1u << ix));
+        if (level != ibex_irq_get_level(&s->irqs[ix])) {
+            trace_ot_soc_proxy_update_irq(s->ot_id, ix,
+                                          ibex_irq_get_level(&s->irqs[ix]),
+                                          level);
+        }
+        ibex_irq_set(&s->irqs[ix], level);
+    }
+}
+
+static void ot_soc_proxy_update_alerts(OtSoCProxyState *s)
+{
+    uint32_t level = s->regs[R_ALERT_TEST];
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static void ot_soc_proxy_ingress_irq(void *opaque, int n, int level)
+{
+    OtSoCProxyState *s = opaque;
+
+    g_assert(n < INTR_COUNT);
+
+    trace_ot_soc_proxy_ingress_irq(s->ot_id, (unsigned)n, (bool)level);
+
+    uint32_t bm = 1u << n;
+    if (level) { /* RW1S */
+        s->regs[R_INTR_STATE] |= bm;
+        ot_soc_proxy_update_irqs(s);
+    }
+}
+
+static uint64_t ot_soc_proxy_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtSoCProxyState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+        val32 = s->regs[reg];
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_soc_proxy_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg),
+                                   val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_soc_proxy_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                    unsigned size)
+{
+    OtSoCProxyState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_soc_proxy_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                                pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        s->regs[reg] &= ~val32; /* RW1C */
+        ot_soc_proxy_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        s->regs[reg] = val32;
+        ot_soc_proxy_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        s->regs[R_INTR_STATE] |= val32;
+        ot_soc_proxy_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        s->regs[reg] = val32;
+        ot_soc_proxy_update_alerts(s);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+}
+
+static const Property ot_soc_proxy_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtSoCProxyState, ot_id),
+};
+
+static const MemoryRegionOps ot_soc_proxy_regs_ops = {
+    .read = &ot_soc_proxy_regs_read,
+    .write = &ot_soc_proxy_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_soc_proxy_reset_enter(Object *obj, ResetType type)
+{
+    OtSoCProxyClass *c = OT_SOC_PROXY_GET_CLASS(obj);
+    OtSoCProxyState *s = OT_SOC_PROXY(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->regs, 0, sizeof(s->regs));
+
+    ot_soc_proxy_update_irqs(s);
+    ot_soc_proxy_update_alerts(s);
+}
+
+static void ot_soc_proxy_realize(DeviceState *dev, Error **errp)
+{
+    OtSoCProxyState *s = OT_SOC_PROXY(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+}
+
+static void ot_soc_proxy_init(Object *obj)
+{
+    OtSoCProxyState *s = OT_SOC_PROXY(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_soc_proxy_regs_ops, s,
+                          TYPE_OT_SOC_PROXY, REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->irqs); ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    qdev_init_gpio_in_named_with_opaque(DEVICE(s), &ot_soc_proxy_ingress_irq, s,
+                                        NULL, INTR_COUNT);
+}
+
+static void ot_soc_proxy_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_soc_proxy_realize;
+    device_class_set_props(dc, ot_soc_proxy_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtSoCProxyClass *sc = OT_SOC_PROXY_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_soc_proxy_reset_enter, NULL,
+                                       NULL, &sc->parent_phases);
+}
+
+static const TypeInfo ot_soc_proxy_info = {
+    .name = TYPE_OT_SOC_PROXY,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtSoCProxyState),
+    .instance_init = &ot_soc_proxy_init,
+    .class_size = sizeof(OtSoCProxyClass),
+    .class_init = &ot_soc_proxy_class_init,
+};
+
+static void ot_soc_proxy_register_types(void)
+{
+    type_register_static(&ot_soc_proxy_info);
+}
+
+type_init(ot_soc_proxy_register_types);
diff --git a/hw/opentitan/ot_spi_device.c b/hw/opentitan/ot_spi_device.c
new file mode 100644
index 0000000000000..da2261c684b6b
--- /dev/null
+++ b/hw/opentitan/ot_spi_device.c
@@ -0,0 +1,3016 @@
+/*
+ * QEMU OpenTitan SPI Device controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "qemu/fifo8.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "chardev/char-fe.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_fifo32.h"
+#include "hw/opentitan/ot_spi_device.h"
+#include "hw/opentitan/ot_spi_host.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+#define PARAM_SRAM_DEPTH         1024u
+#define PARAM_SRAM_EGRESS_DEPTH  848u
+#define PARAM_SRAM_INGRESS_DEPTH 112u
+#define PARAM_NUM_CMD_INFO       24u
+#define PARAM_NUM_LOCALITY       5u
+#define PARAM_TPM_RD_FIFO_DEPTH  16u
+#define PARAM_TPM_WR_FIFO_DEPTH  16u
+#define PARAM_NUM_IRQS           8u
+#define PARAM_NUM_ALERTS         1u
+#define PARAM_REG_WIDTH          32u
+
+/* SPI device registers */
+/* clang-format off */
+REG32(INTR_STATE, 0x0u)
+    SHARED_FIELD(INTR_UPLOAD_CMDFIFO_NOT_EMPTY, 0u, 1u)
+    SHARED_FIELD(INTR_UPLOAD_PAYLOAD_NOT_EMPTY, 1u, 1u)
+    SHARED_FIELD(INTR_UPLOAD_PAYLOAD_OVERFLOW, 2u, 1u)
+    SHARED_FIELD(INTR_READBUF_WATERMARK, 3u, 1u)
+    SHARED_FIELD(INTR_READBUF_FLIP, 4u, 1u)
+    SHARED_FIELD(INTR_TPM_HEADER_NOT_EMPTY, 5u, 1u)
+    SHARED_FIELD(INTR_TPM_RDFIFO_CMD_END, 6u, 1u)
+    SHARED_FIELD(INTR_TPM_RDFIFO_DROP, 7u, 1u)
+REG32(INTR_ENABLE, 0x4u)
+REG32(INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(CONTROL, 0x10u)
+    FIELD(CONTROL, FLASH_STATUS_FIFO_CLR, 0u, 1u)
+    FIELD(CONTROL, FLASH_READ_BUFFER_CLR, 1u, 1u)
+    FIELD(CONTROL, MODE, 4u, 2u)
+REG32(CFG, 0x14u)
+    FIELD(CFG, TX_ORDER, 2u, 1u)
+    FIELD(CFG, RX_ORDER, 3u, 1u)
+    FIELD(CFG, MAILBOX_EN, 24u, 1u)
+REG32(STATUS, 0x18u)
+    FIELD(STATUS, CSB, 5u, 1u)
+    FIELD(STATUS, TPM_CSB, 6u, 1u)
+REG32(INTERCEPT_EN, 0x1cu)
+    FIELD(INTERCEPT_EN, STATUS, 0u, 1u)
+    FIELD(INTERCEPT_EN, JEDEC, 1u, 1u)
+    FIELD(INTERCEPT_EN, SFDP, 2u, 1u)
+    FIELD(INTERCEPT_EN, MBX, 3u, 1u)
+REG32(ADDR_MODE, 0x20u)
+    FIELD(ADDR_MODE, ADDR_4B_EN, 0u, 1u)
+    FIELD(ADDR_MODE, PENDING, 31u, 1u)
+REG32(LAST_READ_ADDR, 0x24u)
+REG32(FLASH_STATUS, 0x28u)
+    FIELD(FLASH_STATUS, BUSY, 0u, 1u)
+    FIELD(FLASH_STATUS, WEL, 1u, 1u)
+    FIELD(FLASH_STATUS, STATUS, 2u, 22u)
+REG32(JEDEC_CC, 0x2cu)
+    FIELD(JEDEC_CC, CC, 0u, 8u)
+    FIELD(JEDEC_CC, NUM_CC, 8u, 8u)
+REG32(JEDEC_ID, 0x30u)
+    FIELD(JEDEC_ID, DEVICE, 0u, 16u)
+    FIELD(JEDEC_ID, MF, 16u, 8u)
+REG32(READ_THRESHOLD, 0x34u)
+    FIELD(READ_THRESHOLD, THRESHOLD, 0u, 10u)
+REG32(MAILBOX_ADDR, 0x38u)
+    FIELD(MAILBOX_ADDR, LOWER, 0u, 9u)
+    FIELD(MAILBOX_ADDR, UPPER, 10u, 22u)
+REG32(UPLOAD_STATUS, 0x3cu)
+    FIELD(UPLOAD_STATUS, CMDFIFO_DEPTH, 0u, 5u)
+    FIELD(UPLOAD_STATUS, CMDFIFO_NOTEMPTY, 7u, 1u)
+    FIELD(UPLOAD_STATUS, ADDRFIFO_DEPTH, 8u, 5u)
+    FIELD(UPLOAD_STATUS, ADDRFIFO_NOTEMPTY, 15u, 1u)
+REG32(UPLOAD_STATUS2, 0x40u)
+    FIELD(UPLOAD_STATUS2, PAYLOAD_DEPTH, 0u, 9u)
+    FIELD(UPLOAD_STATUS2, PAYLOAD_START_IDX, 16u, 8u)
+REG32(UPLOAD_CMDFIFO, 0x44u)
+    FIELD(UPLOAD_CMDFIFO, DATA, 0u, 8u)
+    FIELD(UPLOAD_CMDFIFO, BUSY, 13u, 1u)
+    FIELD(UPLOAD_CMDFIFO, WEL, 14u, 1u)
+    FIELD(UPLOAD_CMDFIFO, ADDR4B_MODE, 15u, 1u)
+REG32(UPLOAD_ADDRFIFO, 0x48u)
+REG32(CMD_FILTER_0, 0x4cu)
+REG32(CMD_FILTER_1, 0x50u)
+REG32(CMD_FILTER_2, 0x54u)
+REG32(CMD_FILTER_3, 0x58u)
+REG32(CMD_FILTER_4, 0x5cu)
+REG32(CMD_FILTER_5, 0x60u)
+REG32(CMD_FILTER_6, 0x64u)
+REG32(CMD_FILTER_7, 0x68u)
+REG32(ADDR_SWAP_MASK, 0x6cu)
+REG32(ADDR_SWAP_DATA, 0x70u)
+REG32(PAYLOAD_SWAP_MASK, 0x74u)
+REG32(PAYLOAD_SWAP_DATA, 0x78u)
+REG32(CMD_INFO_0, 0x7cu) /* ReadStatus1 */
+    SHARED_FIELD(CMD_INFO_OPCODE, 0u, 8u)
+    SHARED_FIELD(CMD_INFO_ADDR_MODE, 8u, 2u)
+    SHARED_FIELD(CMD_INFO_ADDR_SWAP_EN, 10u, 1u) /* not used in Flash mode */
+    SHARED_FIELD(CMD_INFO_MBYTE_EN, 11u, 1u)
+    /* limited to bits, ignore in QEMU */
+    SHARED_FIELD(CMD_INFO_DUMMY_SIZE, 12u, 3u)
+    /* only use this bit for dummy cfg */
+    SHARED_FIELD(CMD_INFO_DUMMY_EN, 15u, 1u)
+    SHARED_FIELD(CMD_INFO_PAYLOAD_EN, 16u, 4u)
+    /* not used in Flash mode (guess) */
+    SHARED_FIELD(CMD_INFO_PAYLOAD_DIR, 20u, 1u)
+    SHARED_FIELD(CMD_INFO_PAYLOAD_SWAP_EN, 21u, 1u) /* not used in Flash mode */
+    SHARED_FIELD(CMD_INFO_READ_PIPELINE_MODE, 22u, 2u)
+    SHARED_FIELD(CMD_INFO_UPLOAD, 24u, 1u)
+    SHARED_FIELD(CMD_INFO_BUSY, 25u, 1u)
+    SHARED_FIELD(CMD_INFO_VALID, 31u, 1u)
+REG32(CMD_INFO_1, 0x80u) /* ReadStatus2 */
+REG32(CMD_INFO_2, 0x84u) /* ReadStatus3 */
+REG32(CMD_INFO_3, 0x88u) /* ReadJedecId */
+REG32(CMD_INFO_4, 0x8cu) /* ReadSfdp */
+REG32(CMD_INFO_5, 0x90u) /* Read */
+REG32(CMD_INFO_6, 0x94u) /* FastRead */
+REG32(CMD_INFO_7, 0x98u) /* FastReadDual */
+REG32(CMD_INFO_8, 0x9cu) /* FastReadQuad */
+REG32(CMD_INFO_9, 0xa0u) /* FastReadDualIO */
+REG32(CMD_INFO_10, 0xa4u) /* FastReadQuadIO */
+REG32(CMD_INFO_11, 0xa8u)
+REG32(CMD_INFO_12, 0xacu)
+REG32(CMD_INFO_13, 0xb0u)
+REG32(CMD_INFO_14, 0xb4u)
+REG32(CMD_INFO_15, 0xb8u)
+REG32(CMD_INFO_16, 0xbcu)
+REG32(CMD_INFO_17, 0xc0u)
+REG32(CMD_INFO_18, 0xc4u)
+REG32(CMD_INFO_19, 0xc8u)
+REG32(CMD_INFO_20, 0xccu)
+REG32(CMD_INFO_21, 0xd0u)
+REG32(CMD_INFO_22, 0xd4u)
+REG32(CMD_INFO_23, 0xd8u)
+REG32(CMD_INFO_EN4B, 0xdcu)
+REG32(CMD_INFO_EX4B, 0xe0u)
+REG32(CMD_INFO_WREN, 0xe4u)
+REG32(CMD_INFO_WRDI, 0xe8u)
+/* clang-format on */
+
+/* TPM registers */
+/* clang-format off */
+REG32(TPM_CAP, 0x00u)
+    FIELD(TPM_CAP, REV, 0u, 8u)
+    FIELD(TPM_CAP, LOCALITY, 8u, 1u)
+    FIELD(TPM_CAP, MAX_WR_SIZE, 16u, 3u)
+    FIELD(TPM_CAP, MAX_RD_SIZE, 20u, 3u)
+REG32(TPM_CFG, 0x04u)
+    FIELD(TPM_CFG, EN, 0u, 1u)
+    FIELD(TPM_CFG, TPM_MODE, 1u, 1u)
+    FIELD(TPM_CFG, HW_REG_DIS, 2u, 1u)
+    FIELD(TPM_CFG, TPM_REG_CHK_DIS, 3u, 1u)
+    FIELD(TPM_CFG, INVALID_LOCALITY, 4u, 1u)
+REG32(TPM_STATUS, 0x08u)
+    FIELD(TPM_STATUS, CMDADDR_NOTEMPTY, 0u, 1u)
+    FIELD(TPM_STATUS, WRFIFO_PENDING, 1u, 1u)
+    FIELD(TPM_STATUS, RDFIFO_ABORTED, 2u, 1u)
+REG32(TPM_ACCESS_0, 0x0cu)
+    FIELD(TPM_ACCESS_0, ACCESS_0, 0u, 8u)
+    FIELD(TPM_ACCESS_0, ACCESS_1, 8u, 8u)
+    FIELD(TPM_ACCESS_0, ACCESS_2, 16u, 8u)
+    FIELD(TPM_ACCESS_0, ACCESS_3, 24u, 8u)
+REG32(TPM_ACCESS_1, 0x10u)
+    FIELD(TPM_ACCESS_1, ACCESS_4, 0u, 8u)
+REG32(TPM_STS, 0x14u)
+REG32(TPM_INTF_CAPABILITY, 0x18u)
+REG32(TPM_INT_ENABLE, 0x1cu)
+REG32(TPM_INT_VECTOR, 0x20u)
+    FIELD(TPM_INT_VECTOR, INT_VECTOR, 0u, 8u)
+REG32(TPM_INT_STATUS, 0x24u)
+REG32(TPM_DID_VID, 0x28u)
+    FIELD(TPM_DID_VID, VID, 0u, 16u)
+    FIELD(TPM_DID_VID, DID, 16u, 16u)
+REG32(TPM_RID, 0x2cu)
+    FIELD(TPM_RID, RID, 0u, 8u)
+REG32(TPM_CMD_ADDR, 0x30u)
+    FIELD(TPM_CMD_ADDR, ADDR, 0u, 24u)
+    FIELD(TPM_CMD_ADDR, CMD, 24u, 8u)
+REG32(TPM_READ_FIFO, 0x34u)
+/* clang-format on */
+
+#define SPI_BUS_PROTO_VER   0
+#define SPI_BUS_HEADER_SIZE (2u * sizeof(uint32_t))
+#define SPI_TPM_READ_FIFO_SIZE_BYTES \
+    (PARAM_TPM_RD_FIFO_DEPTH * sizeof(uint32_t))
+/*
+ * Pacing time to give hand back to the vCPU when a readbuf event is triggered.
+ * This is needed so guest SW can respond to the interrupt and fill the buffer.
+ *
+ * The scheduled timer tell the CharDev backend not to consume (nor push back)
+ * any more bytes from/to the SPI bus. The Chardev will resume its SPI bus
+ * bytestream management as soon as the timer is cancelled/expires. Ideally,
+ * guest SW will clear the readbuf interrupt causing the timer to expire,
+ * usually once SW has filled in the read buffer. If Guest SW does not use this
+ * (e.g. it writes across both buffers in advance and does not expect to handle
+ * a buffer flip event) then this will not happen, and the timer must exhaust
+ * on its own, thus we only set this delay to a small arbitrary value of 10 ms.
+ *
+ * @todo: A better approach might be to yield to the vCPU every few bytes/words
+ * to better emulate the concurrency of large SPI transactions with SW,
+ * potentially keeping a small additional delay on a buffer flip.
+ */
+#define SPI_BUS_FLASH_READ_DELAY_NS 10000000
+
+/*
+ * Memory layout extracted from the documentation:
+ * opentitan.org/book/hw/ip/spi_device/doc/programmers_guide.html
+ * #dual-port-sram-layout
+ *
+ *          New scheme (Egress + Ingress)      Old Scheme (DPSRAM)
+ *         +--------------------------------+    +-----------------------+
+ *         | Flash / Passthru modes         |    | Flash / Passthru modes|
+ *  0x000 -+-------------------+------+-----+   -+----------------+------+
+ *         | Read Command 0    | 1KiB | Out |    | Read Command 0 | 1KiB |
+ *  0x400 -+-------------------+------+-----+   -+----------------+------+
+ *         | Read Command 1    | 1KiB | Out |    | Read Command 1 | 1KiB |
+ *  0x800 -+-------------------+------+-----+   -+----------------+------+
+ *         | Mailbox           | 1KiB | Out |    | Mailbox        | 1KiB |
+ *  0xc00 -+-------------------+------+-----+   -+----------------+------+
+ *         | SFDP              | 256B | Out |    | SFDP           | 256B |
+ *  0xd00 -+-------------------+------+-----+   -+----------------+------+
+ *         | TPM Read Buffer   |  64B | Out |    | Payload FIFO   | 256B |
+ *  0xd40 -+-------------------+------+-----+   -+----------------+------+
+ *         |                   |      |     |    | Command FIFO   |  64B |
+ *  0xe00 -+-------------------+------+-----+   -+----------------+------+
+ *         | Payload FIFO      | 256B | In  |    | Address FIFO   |  64B |
+ *  0xf00 -+-------------------+------+-----+   -+----------------+------+
+ *         | Command FIFO      |  64B | In  |
+ *  0xf40 -+-------------------+------+-----+
+ *         | Address FIFO      |  64B | In  |
+ *  0xf80 -+-------------------+------+-----+
+ *         | TPM Write Buffer  |  64B | In  |
+ *  0xfc0 -+-------------------+------+-----+
+ *
+ */
+/* clang-format off */
+#define SPI_SRAM_READ0_OFFSET      0x0
+#define SPI_SRAM_READ_LOG2_SIZE    10u
+#define SPI_SRAM_READ_SIZE         (1u << SPI_SRAM_READ_LOG2_SIZE)
+#define SPI_SRAM_READ1_OFFSET      (SPI_SRAM_READ0_OFFSET + SPI_SRAM_READ_SIZE)
+#define SPI_SRAM_READ1_SIZE        0x400u
+#define SPI_SRAM_MBX_OFFSET        (SPI_SRAM_READ1_OFFSET + SPI_SRAM_READ_SIZE)
+#define SPI_SRAM_MBX_SIZE          0x400u
+#define SPI_SRAM_SFDP_OFFSET       (SPI_SRAM_MBX_OFFSET + SPI_SRAM_MBX_SIZE)
+#define SPI_SRAM_SFDP_SIZE         0x100u
+#define SPI_SRAM_TPM_READ_OFFSET   (SPI_SRAM_SFDP_OFFSET + SPI_SRAM_SFDP_SIZE)
+#define SPI_SRAM_TPM_READ_SIZE     0x40u
+#define SPI_SRAM_INGRESS_OFFSET    0xE00u
+#define SPI_SRAM_PAYLOAD_OFFSET    SPI_SRAM_INGRESS_OFFSET
+#define SPI_SRAM_PAYLOAD_SIZE      0x100u
+#define SPI_SRAM_CMD_OFFSET \
+    (SPI_SRAM_PAYLOAD_OFFSET + SPI_SRAM_PAYLOAD_SIZE)
+#define SPI_SRAM_CMD_SIZE          0x40u
+#define SPI_SRAM_ADDR_OFFSET       (SPI_SRAM_CMD_OFFSET + SPI_SRAM_CMD_SIZE)
+#define SPI_SRAM_ADDR_SIZE         0x40u
+#define SPI_SRAM_TPM_WRITE_OFFSET  (SPI_SRAM_ADDR_OFFSET + SPI_SRAM_ADDR_SIZE)
+#define SPI_SRAM_TPM_WRITE_SIZE    0x40u
+#define SPI_SRAM_ADDR_END \
+    (SPI_SRAM_TPM_WRITE_OFFSET + SPI_SRAM_TPM_WRITE_SIZE)
+#define SPI_SRAM_END_OFFSET        (SPI_SRAM_ADDR_END)
+#define SPI_DEVICE_SIZE            0x2000u
+#define SPI_DEVICE_SPI_REGS_OFFSET 0u
+#define SPI_DEVICE_TPM_REGS_OFFSET 0x800u
+#define SPI_DEVICE_SRAM_OFFSET     0x1000u
+/* clang-format on */
+
+#define SRAM_SIZE                 (PARAM_SRAM_DEPTH * sizeof(uint32_t))
+#define EGRESS_BUFFER_SIZE_BYTES  (PARAM_SRAM_EGRESS_DEPTH * sizeof(uint32_t))
+#define EGRESS_BUFFER_SIZE_WORDS  PARAM_SRAM_EGRESS_DEPTH
+#define INGRESS_BUFFER_SIZE_BYTES (PARAM_SRAM_INGRESS_DEPTH * sizeof(uint32_t))
+#define INGRESS_BUFFER_SIZE_WORDS PARAM_SRAM_INGRESS_DEPTH
+#define FLASH_READ_BUFFER_SIZE    (2u * SPI_SRAM_READ_SIZE)
+
+#define SPI_DEFAULT_TX_RX_VALUE ((uint8_t)0xffu)
+#define SPI_FLASH_BUFFER_SIZE   256u
+
+typedef enum {
+    /* Internal HW command slots (0-10) */
+    SLOT_HW_READ_STATUS1, /* slot 0, typically 0x05u */
+    SLOT_HW_READ_STATUS2, /* slot 1, typically 0x35u */
+    SLOT_HW_READ_STATUS3, /* slot 2, typically 0x15u */
+    SLOT_HW_READ_JEDEC, /* slot 3, typically 0x9f */
+    SLOT_HW_READ_SFDP, /* slot 4, typically 0x5a */
+    SLOT_HW_READ_NORMAL, /* slot 5, typically 0x03u */
+    SLOT_HW_READ_FAST, /* slot 6, typically 0x0bu */
+    SLOT_HW_READ_DUAL, /* slot 7, typically 0x3bu */
+    SLOT_HW_READ_QUAD, /* slot 8, typically 0x6bu */
+    SLOT_HW_READ_DUAL_IO, /* slot 9, typically 0xbbu */
+    SLOT_HW_READ_QUAD_IO, /* slot 10, typically 0xebu */
+    /* SW command slots (11-23) */
+    SLOT_SW_CMD_11,
+    SLOT_SW_CMD_12,
+    SLOT_SW_CMD_13,
+    SLOT_SW_CMD_14,
+    SLOT_SW_CMD_15,
+    SLOT_SW_CMD_16,
+    SLOT_SW_CMD_17,
+    SLOT_SW_CMD_18,
+    SLOT_SW_CMD_19,
+    SLOT_SW_CMD_20,
+    SLOT_SW_CMD_21,
+    SLOT_SW_CMD_22,
+    SLOT_SW_CMD_23,
+    /* Configurable HW command slots (EN4B-WRDI, 24-27) */
+    SLOT_HW_EN4B, /* slot 24, typically 0xb7u */
+    SLOT_HW_EX4B, /* slot 25, typically 0xe9u */
+    SLOT_HW_WREN, /* slot 26, typically 0x06u */
+    SLOT_HW_WRDI, /* slot 27, typically 0x04u */
+    SLOT_COUNT,
+    SLOT_INVALID = SLOT_COUNT,
+} OtSpiDeviceCommandSlot;
+
+#define SLOT_SW_CMD_FIRST (SLOT_SW_CMD_11)
+#define SLOT_SW_CMD_LAST  (SLOT_SW_CMD_23)
+
+static_assert(SLOT_COUNT == 28u, "Invalid command slot count");
+
+#define TPM_OPCODE_READ_BIT  7u
+#define TPM_OPCODE_SIZE_MASK 0x3Fu
+#define TPM_ADDR_HEADER      0xD4u
+#define TPM_READY            0x01u
+
+static_assert(SPI_SRAM_INGRESS_OFFSET >=
+                  (SPI_SRAM_TPM_READ_OFFSET + SPI_SRAM_TPM_READ_SIZE),
+              "SPI SRAM Egress buffers overflow into Ingress buffers");
+static_assert(SPI_SRAM_END_OFFSET == 0xfc0u, "Invalid SRAM definition");
+
+typedef enum {
+    CTRL_MODE_DISABLED,
+    CTRL_MODE_FLASH,
+    CTRL_MODE_PASSTHROUGH,
+    CTRL_MODE_INVALID,
+} OtSpiDeviceMode;
+
+typedef enum {
+    SPI_BUS_IDLE,
+    SPI_BUS_FLASH,
+    SPI_BUS_TPM,
+    SPI_BUS_DISCARD,
+    SPI_BUS_ERROR,
+} OtSpiBusState;
+
+typedef enum {
+    SPI_FLASH_IDLE, /* No command received */
+    SPI_FLASH_COLLECT, /* Collecting address or additional info after cmd */
+    SPI_FLASH_BUFFER, /* Reading out data from buffer or SFDP (-> SPI host) */
+    SPI_FLASH_READ, /* Reading out data from SRAM (-> SPI host) */
+    SPI_FLASH_UP_ADDR, /* Uploading address (<- SPI host) */
+    SPI_FLASH_UP_DUMMY, /* Uploading dummy (<- SPI host) */
+    SPI_FLASH_UP_PAYLOAD, /* Uploading payload (<- SPI host) */
+    SPI_FLASH_PASSTHROUGH_UP_ADDR, /* Passthrough mode - Uploading address */
+    SPI_FLASH_PASSTHROUGH_UP_DUMMY, /* Passthrough mode - Uploading dummy */
+    SPI_FLASH_PASSTHROUGH_UP_PAYLOAD, /* Passthrough mode - Uploading payload */
+    SPI_FLASH_DONE, /* No more clock expected for the current command */
+    SPI_FLASH_ERROR, /* On error */
+} OtSpiFlashState;
+
+typedef enum {
+    SPI_TPM_IDLE, /* Wait for the fist byte of the header.*/
+    SPI_TPM_ADDR, /* Wait for the following 3 bytes of the header.*/
+    SPI_TPM_WAIT, /* Not ready for the host to read.*/
+    SPI_TPM_START_BYTE, /* Now ready for the host to read.*/
+    SPI_TPM_READ, /* The host requested a read handled by Software.*/
+    SPI_TPM_READ_HW_REG, /* Host requested a read handled by Hardware.*/
+    SPI_TPM_WRITE, /* Host is writing.*/
+    SPI_TPM_END, /* Finished the spi transaction.*/
+} OtSpiTpmState;
+
+typedef struct {
+    unsigned address_size; /* Length of address field for current command */
+    bool cmd_addr_swap; /* Address byte swapping is enabled */
+    bool cmd_dummy; /* Command has dummy field */
+    bool cmd_payload_swap; /* Payload byte swapping is enabled */
+    bool cmd_payload_dir_out; /* Payload is from flash to host */
+} OtSpiCommandParams;
+
+typedef struct {
+    OtSpiFlashState state;
+    OtSpiDeviceCommandSlot slot; /* Command slot */
+    OtSpiCommandParams cmd_params; /* Parameters for current command */
+    unsigned pos; /* Current position in data buffer */
+    unsigned len; /* Meaning depends on command and current state */
+    uint32_t address; /* Address tracking */
+    uint32_t last_read_addr; /* Last address read before increment */
+    uint32_t next_buffer_addr; /* Next buffer boundary */
+    uint32_t cmd_info; /* Selected command info slot */
+    uint8_t *src; /* Selected read data source (alias) */
+    uint8_t *payload; /* Selected write data sink (alias) */
+    uint8_t *buffer; /* Temporary buffer to handle transfer */
+    OtFifo32 cmd_fifo; /* Command FIFO */
+    OtFifo32 address_fifo; /* Address FIFO */
+    QEMUTimer *irq_timer; /* Timer to resume processing after a READBUF_* IRQ */
+    bool loop; /* Keep reading the buffer if end is reached */
+    bool watermark_crossed; /* Read watermark hit, used as flip-flop */
+    bool new_cmd; /* New command has been pushed in current SPI transaction */
+} SpiDeviceFlash;
+
+typedef struct {
+    OtSpiTpmState state;
+    uint8_t *write_buffer;
+    uint32_t opcode;
+    unsigned write_pos;
+    unsigned len;
+    Fifo8 rdfifo;
+    unsigned can_receive;
+    unsigned transfer_size;
+    unsigned reg;
+    unsigned locality;
+    bool read;
+    bool should_sw_handle;
+} SpiDeviceTpm;
+
+typedef struct {
+    unsigned addr;
+    uint32_t offset;
+    unsigned nbytes;
+} SpiTpmHwAddrMap;
+
+typedef struct {
+    OtSpiBusState state;
+    unsigned byte_count; /* Count of SPI payload to receive */
+    Fifo8 chr_fifo; /* QEMU protocol input FIFO */
+    uint8_t mode; /* Polarity/phase mismatch */
+    bool release; /* Whether to release /CS on last byte */
+    bool failed_transaction; /* Whether to discard until /CS is deasserted */
+    bool rev_rx; /* Reverse RX bits */
+    bool rev_tx; /* Reverse TX bits */
+} SpiDeviceBus;
+
+struct OtSPIDeviceState {
+    SysBusDevice parent_obj;
+
+    struct {
+        MemoryRegion main;
+        MemoryRegion spi;
+        MemoryRegion tpm;
+        MemoryRegion buf;
+    } mmio;
+    IbexIRQ irqs[PARAM_NUM_IRQS];
+    IbexIRQ alerts[PARAM_NUM_ALERTS];
+
+    SpiDeviceBus bus;
+    SpiDeviceFlash flash;
+    SpiDeviceTpm tpm;
+
+    /* CS signal for downstream flash in passthrough mode, active low */
+    IbexIRQ passthrough_cs;
+    IbexIRQ passthrough_en;
+
+    uint32_t *spi_regs; /* Registers */
+    uint32_t *tpm_regs; /* Registers */
+    uint32_t *sram;
+
+    /* Properties */
+    char *ot_id;
+    OtSPIHostState *spi_host; /* downstream SPI Host */
+    CharFrontend chr; /* communication device */
+    guint watch_tag; /* tracker for comm device change */
+};
+
+struct OtSPIDeviceClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+#define REG_BITS     (8u * sizeof(uint32_t))
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_SPI_LAST_REG (R_CMD_INFO_WRDI)
+#define SPI_REGS_COUNT (R_SPI_LAST_REG + 1u)
+#define SPI_REGS_SIZE  (SPI_REGS_COUNT * sizeof(uint32_t))
+#define SPI_REG_NAME(_reg_) \
+    ((((_reg_) < SPI_REGS_COUNT) && SPI_REG_NAMES[_reg_]) ? \
+         SPI_REG_NAMES[_reg_] : \
+         "?")
+
+#define R_TPM_LAST_REG (R_TPM_READ_FIFO)
+#define TPM_REGS_COUNT (R_TPM_LAST_REG + 1u)
+#define TPM_REGS_SIZE  (TPM_REGS_COUNT * sizeof(uint32_t))
+#define TPM_REG_NAME(_reg_) \
+    ((((_reg_) < TPM_REGS_COUNT) && TPM_REG_NAMES[_reg_]) ? \
+         TPM_REG_NAMES[_reg_] : \
+         "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+/* clang-format off */
+static const char *SPI_REG_NAMES[SPI_REGS_COUNT] = {
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CONTROL),
+    REG_NAME_ENTRY(CFG),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(INTERCEPT_EN),
+    REG_NAME_ENTRY(ADDR_MODE),
+    REG_NAME_ENTRY(LAST_READ_ADDR),
+    REG_NAME_ENTRY(FLASH_STATUS),
+    REG_NAME_ENTRY(JEDEC_CC),
+    REG_NAME_ENTRY(JEDEC_ID),
+    REG_NAME_ENTRY(READ_THRESHOLD),
+    REG_NAME_ENTRY(MAILBOX_ADDR),
+    REG_NAME_ENTRY(UPLOAD_STATUS),
+    REG_NAME_ENTRY(UPLOAD_STATUS2),
+    REG_NAME_ENTRY(UPLOAD_CMDFIFO),
+    REG_NAME_ENTRY(UPLOAD_ADDRFIFO),
+    REG_NAME_ENTRY(CMD_FILTER_0),
+    REG_NAME_ENTRY(CMD_FILTER_1),
+    REG_NAME_ENTRY(CMD_FILTER_2),
+    REG_NAME_ENTRY(CMD_FILTER_3),
+    REG_NAME_ENTRY(CMD_FILTER_4),
+    REG_NAME_ENTRY(CMD_FILTER_5),
+    REG_NAME_ENTRY(CMD_FILTER_6),
+    REG_NAME_ENTRY(CMD_FILTER_7),
+    REG_NAME_ENTRY(ADDR_SWAP_MASK),
+    REG_NAME_ENTRY(ADDR_SWAP_DATA),
+    REG_NAME_ENTRY(PAYLOAD_SWAP_MASK),
+    REG_NAME_ENTRY(PAYLOAD_SWAP_DATA),
+    REG_NAME_ENTRY(CMD_INFO_0),
+    REG_NAME_ENTRY(CMD_INFO_1),
+    REG_NAME_ENTRY(CMD_INFO_2),
+    REG_NAME_ENTRY(CMD_INFO_3),
+    REG_NAME_ENTRY(CMD_INFO_4),
+    REG_NAME_ENTRY(CMD_INFO_5),
+    REG_NAME_ENTRY(CMD_INFO_6),
+    REG_NAME_ENTRY(CMD_INFO_7),
+    REG_NAME_ENTRY(CMD_INFO_8),
+    REG_NAME_ENTRY(CMD_INFO_9),
+    REG_NAME_ENTRY(CMD_INFO_10),
+    REG_NAME_ENTRY(CMD_INFO_11),
+    REG_NAME_ENTRY(CMD_INFO_12),
+    REG_NAME_ENTRY(CMD_INFO_13),
+    REG_NAME_ENTRY(CMD_INFO_14),
+    REG_NAME_ENTRY(CMD_INFO_15),
+    REG_NAME_ENTRY(CMD_INFO_16),
+    REG_NAME_ENTRY(CMD_INFO_17),
+    REG_NAME_ENTRY(CMD_INFO_18),
+    REG_NAME_ENTRY(CMD_INFO_19),
+    REG_NAME_ENTRY(CMD_INFO_20),
+    REG_NAME_ENTRY(CMD_INFO_21),
+    REG_NAME_ENTRY(CMD_INFO_22),
+    REG_NAME_ENTRY(CMD_INFO_23),
+    REG_NAME_ENTRY(CMD_INFO_EN4B),
+    REG_NAME_ENTRY(CMD_INFO_EX4B),
+    REG_NAME_ENTRY(CMD_INFO_WREN),
+    REG_NAME_ENTRY(CMD_INFO_WRDI),
+};
+
+static const char *TPM_REG_NAMES[TPM_REGS_COUNT] = {
+    REG_NAME_ENTRY(TPM_CAP),
+    REG_NAME_ENTRY(TPM_CFG),
+    REG_NAME_ENTRY(TPM_STATUS),
+    REG_NAME_ENTRY(TPM_ACCESS_0),
+    REG_NAME_ENTRY(TPM_ACCESS_1),
+    REG_NAME_ENTRY(TPM_STS),
+    REG_NAME_ENTRY(TPM_INTF_CAPABILITY),
+    REG_NAME_ENTRY(TPM_INT_ENABLE),
+    REG_NAME_ENTRY(TPM_INT_VECTOR),
+    REG_NAME_ENTRY(TPM_INT_STATUS),
+    REG_NAME_ENTRY(TPM_DID_VID),
+    REG_NAME_ENTRY(TPM_RID),
+    REG_NAME_ENTRY(TPM_CMD_ADDR),
+    REG_NAME_ENTRY(TPM_READ_FIFO),
+};
+/* clang-format on */
+#undef REG_NAME_ENTRY
+
+#define INTR_MASK         ((1u << PARAM_NUM_IRQS) - 1u)
+#define ALERT_TEST_MASK   (R_ALERT_TEST_FATAL_FAULT_MASK)
+#define INTR_READBUF_MASK (INTR_READBUF_WATERMARK_MASK | INTR_READBUF_FLIP_MASK)
+#define CONTROL_MASK \
+    (R_CONTROL_FLASH_STATUS_FIFO_CLR_MASK | \
+     R_CONTROL_FLASH_READ_BUFFER_CLR_MASK | R_CONTROL_MODE_MASK)
+#define CMD_INFO_GEN_MASK \
+    (CMD_INFO_OPCODE_MASK | CMD_INFO_ADDR_MODE_MASK | \
+     CMD_INFO_ADDR_SWAP_EN_MASK | CMD_INFO_MBYTE_EN_MASK | \
+     CMD_INFO_DUMMY_SIZE_MASK | CMD_INFO_DUMMY_EN_MASK | \
+     CMD_INFO_PAYLOAD_EN_MASK | CMD_INFO_PAYLOAD_DIR_MASK | \
+     CMD_INFO_PAYLOAD_SWAP_EN_MASK | CMD_INFO_UPLOAD_MASK | \
+     CMD_INFO_BUSY_MASK | CMD_INFO_VALID_MASK)
+#define CMD_INFO_SPC_MASK (CMD_INFO_OPCODE_MASK | CMD_INFO_VALID_MASK)
+#define CFG_MASK \
+    (R_CFG_TX_ORDER_MASK | R_CFG_RX_ORDER_MASK | R_CFG_MAILBOX_EN_MASK)
+#define INTERCEPT_EN_MASK \
+    (R_INTERCEPT_EN_STATUS_MASK | R_INTERCEPT_EN_JEDEC_MASK | \
+     R_INTERCEPT_EN_SFDP_MASK | R_INTERCEPT_EN_MBX_MASK)
+#define FLASH_STATUS_RW0C_MASK \
+    (R_FLASH_STATUS_BUSY_MASK | R_FLASH_STATUS_WEL_MASK)
+#define FLASH_STATUS_RW_MASK (R_FLASH_STATUS_STATUS_MASK)
+#define JEDEC_CC_MASK        (R_JEDEC_CC_CC_MASK | R_JEDEC_CC_NUM_CC_MASK)
+#define JEDEC_ID_MASK        (R_JEDEC_ID_DEVICE_MASK | R_JEDEC_ID_MF_MASK)
+
+#define COMMAND_OPCODE(_cmd_info_) \
+    ((uint8_t)((_cmd_info_) & CMD_INFO_OPCODE_MASK))
+
+#define STATE_NAME_ENTRY(_st_) [_st_] = stringify(_st_)
+/* clang-format off */
+static const char *BUS_STATE_NAMES[] = {
+    STATE_NAME_ENTRY(SPI_BUS_IDLE),
+    STATE_NAME_ENTRY(SPI_BUS_FLASH),
+    STATE_NAME_ENTRY(SPI_BUS_TPM),
+    STATE_NAME_ENTRY(SPI_BUS_DISCARD),
+    STATE_NAME_ENTRY(SPI_BUS_ERROR),
+};
+
+static const char *FLASH_STATE_NAMES[] = {
+    STATE_NAME_ENTRY(SPI_FLASH_IDLE),
+    STATE_NAME_ENTRY(SPI_FLASH_COLLECT),
+    STATE_NAME_ENTRY(SPI_FLASH_BUFFER),
+    STATE_NAME_ENTRY(SPI_FLASH_READ),
+    STATE_NAME_ENTRY(SPI_FLASH_UP_ADDR),
+    STATE_NAME_ENTRY(SPI_FLASH_UP_DUMMY),
+    STATE_NAME_ENTRY(SPI_FLASH_UP_PAYLOAD),
+    STATE_NAME_ENTRY(SPI_FLASH_PASSTHROUGH_UP_ADDR),
+    STATE_NAME_ENTRY(SPI_FLASH_PASSTHROUGH_UP_DUMMY),
+    STATE_NAME_ENTRY(SPI_FLASH_PASSTHROUGH_UP_PAYLOAD),
+    STATE_NAME_ENTRY(SPI_FLASH_DONE),
+    STATE_NAME_ENTRY(SPI_FLASH_ERROR),
+};
+/* clang-format on */
+#undef STATE_NAME_ENTRY
+
+#define BUS_STATE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(BUS_STATE_NAMES) ? \
+         BUS_STATE_NAMES[(_st_)] : \
+         "?")
+#define FLASH_STATE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(FLASH_STATE_NAMES) ? \
+         FLASH_STATE_NAMES[(_st_)] : \
+         "?")
+
+#define IRQ_NAME_ENTRY(_st_) [INTR_##_st_##_SHIFT] = stringify(_st_)
+/* clang-format off */
+static const char *IRQ_NAMES[] = {
+    IRQ_NAME_ENTRY(UPLOAD_CMDFIFO_NOT_EMPTY),
+    IRQ_NAME_ENTRY(UPLOAD_PAYLOAD_NOT_EMPTY),
+    IRQ_NAME_ENTRY(UPLOAD_PAYLOAD_OVERFLOW),
+    IRQ_NAME_ENTRY(READBUF_WATERMARK),
+    IRQ_NAME_ENTRY(READBUF_FLIP),
+    IRQ_NAME_ENTRY(TPM_HEADER_NOT_EMPTY),
+    IRQ_NAME_ENTRY(TPM_RDFIFO_CMD_END),
+    IRQ_NAME_ENTRY(TPM_RDFIFO_DROP)
+};
+/* clang-format on */
+#undef IRQ_NAME_ENTRY
+
+#define IRQ_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(IRQ_NAMES) ? IRQ_NAMES[(_st_)] : "?")
+
+#define WORD_ALIGN(_x_) ((_x_) & ~0x3u)
+
+#define BUS_CHANGE_STATE(_s_, _sst_) \
+    ot_spi_device_bus_change_state_line(_s_, SPI_BUS_##_sst_, __LINE__)
+#define FLASH_CHANGE_STATE(_s_, _sst_) \
+    ot_spi_device_flash_change_state_line(_s_, SPI_FLASH_##_sst_, __LINE__)
+
+static void ot_spi_device_bus_change_state_line(OtSPIDeviceState *s,
+                                                OtSpiBusState state, int line)
+{
+    if (s->bus.state != state) {
+        trace_ot_spi_device_bus_change_state(s->ot_id, line,
+                                             BUS_STATE_NAME(state), state);
+        s->bus.state = state;
+    }
+}
+
+static void ot_spi_device_flash_change_state_line(
+    OtSPIDeviceState *s, OtSpiFlashState state, int line)
+{
+    if (s->flash.state != state) {
+        trace_ot_spi_device_flash_change_state(s->ot_id, line,
+                                               FLASH_STATE_NAME(s->flash.state),
+                                               s->flash.state,
+                                               FLASH_STATE_NAME(state), state);
+        s->flash.state = state;
+    }
+}
+
+static bool ot_spi_device_is_sw_command(OtSpiDeviceCommandSlot slot)
+{
+    return (slot >= SLOT_SW_CMD_FIRST) && (slot <= SLOT_SW_CMD_LAST);
+}
+
+static bool ot_spi_device_flash_command_is_upload(const SpiDeviceFlash *f)
+{
+    return ot_spi_device_is_sw_command(f->slot) &&
+           ((f->cmd_info & CMD_INFO_UPLOAD_MASK) != 0u);
+}
+
+static bool ot_spi_device_flash_command_is_payload_en(const SpiDeviceFlash *f)
+{
+    return (f->cmd_info & CMD_INFO_PAYLOAD_EN_MASK) != 0u;
+}
+
+static bool ot_spi_device_flash_command_has_payload(const SpiDeviceFlash *f)
+{
+    return ot_spi_device_is_sw_command(f->slot) &&
+           ot_spi_device_flash_command_is_payload_en(f);
+}
+
+static bool ot_spi_device_flash_command_is_rx_payload(const SpiDeviceFlash *f)
+{
+    return ot_spi_device_is_sw_command(f->slot) &&
+           ((f->cmd_info & CMD_INFO_PAYLOAD_DIR_MASK) == 0u);
+}
+
+static bool ot_spi_device_flash_is_readbuf_irq(const OtSPIDeviceState *s)
+{
+    /*
+     * ignore R_INTR_ENABLE as the device may be used in poll mode, but this
+     * device nevertheless needs to hand back execution to vCPU when a readbuf
+     * interrupt is set
+     */
+    return (bool)(s->spi_regs[R_INTR_STATE] & INTR_READBUF_MASK);
+}
+
+static void ot_spi_device_clear_modes(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    timer_del(f->irq_timer);
+    FLASH_CHANGE_STATE(s, IDLE);
+    f->slot = SLOT_INVALID;
+    f->cmd_info = 0u;
+    f->address = 0u;
+    f->last_read_addr = 0u;
+    f->next_buffer_addr = SPI_SRAM_READ_SIZE;
+    f->pos = 0u;
+    f->len = 0u;
+    f->watermark_crossed = false;
+    f->new_cmd = false;
+    g_assert(s->sram);
+    f->payload = &((uint8_t *)s->sram)[SPI_SRAM_PAYLOAD_OFFSET];
+    memset(f->buffer, 0u, SPI_FLASH_BUFFER_SIZE);
+
+    SpiDeviceTpm *tpm = &s->tpm;
+    tpm->state = SPI_TPM_IDLE;
+    tpm->can_receive = 1u;
+    tpm->transfer_size = 0u;
+    tpm->read = false;
+    tpm->reg = 0u;
+    tpm->opcode = 0u;
+    tpm->locality = 0u;
+    tpm->write_buffer = &((uint8_t *)s->sram)[SPI_SRAM_TPM_WRITE_OFFSET];
+    fifo8_reset(&tpm->rdfifo);
+
+    memset(s->sram, 0u, SRAM_SIZE);
+}
+
+static void ot_spi_device_update_irqs(OtSPIDeviceState *s)
+{
+    uint32_t levels = s->spi_regs[R_INTR_STATE] & s->spi_regs[R_INTR_ENABLE];
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        bool level = (bool)((levels >> ix) & 0x1u);
+        if (level != (bool)ibex_irq_get_level(&s->irqs[ix])) {
+            trace_ot_spi_device_set_irq(s->ot_id, IRQ_NAME(ix), ix, level);
+        }
+        ibex_irq_set(&s->irqs[ix], (int)level);
+    }
+}
+
+static void ot_spi_device_update_alerts(OtSPIDeviceState *s)
+{
+    uint32_t level = s->spi_regs[R_ALERT_TEST];
+
+    for (unsigned ix = 0; ix < ARRAY_SIZE(s->alerts); ix++) {
+        ibex_irq_set(&s->alerts[ix], (int)((level >> ix) & 0x1u));
+    }
+}
+
+static bool ot_spi_device_is_tpm_enabled(const OtSPIDeviceState *s)
+{
+    return (bool)FIELD_EX32(s->tpm_regs[R_TPM_CFG], TPM_CFG, EN);
+}
+
+/*
+ * if the SW set this field to 1, the HW logic always pushes the command/addr
+ * and write data to buffers. The logic does not compare the incoming address to
+ * the list of managed-by-HW register addresses.
+ */
+static bool ot_spi_device_is_tpm_mode_crb(const OtSPIDeviceState *s)
+{
+    return (bool)FIELD_EX32(s->tpm_regs[R_TPM_CFG], TPM_CFG, TPM_MODE);
+}
+
+/*
+ * If 0, TPM submodule directly returns the return-by-HW registers for the read
+ * requests. If 1, TPM submodule uploads the TPM command regardless of the
+ * address, and the SW may return the value through the read FIFO.
+ */
+static bool ot_spi_device_tpm_disable_hw_regs(const OtSPIDeviceState *s)
+{
+    return (bool)FIELD_EX32(s->tpm_regs[R_TPM_CFG], TPM_CFG, HW_REG_DIS);
+}
+
+static OtSpiDeviceMode ot_spi_device_get_mode(const OtSPIDeviceState *s)
+{
+    return (OtSpiDeviceMode)FIELD_EX32(s->spi_regs[R_CONTROL], CONTROL, MODE);
+}
+
+static bool ot_spi_device_is_addr4b_en(const OtSPIDeviceState *s)
+{
+    return (bool)(s->spi_regs[R_ADDR_MODE] & R_ADDR_MODE_ADDR_4B_EN_MASK);
+}
+
+static bool ot_spi_device_is_mailbox_en(const OtSPIDeviceState *s)
+{
+    return (bool)(s->spi_regs[R_CFG] & R_CFG_MAILBOX_EN_MASK);
+}
+
+static unsigned
+ot_spi_device_get_command_address_size(const OtSPIDeviceState *s)
+{
+    const SpiDeviceFlash *f = &s->flash;
+
+    switch (SHARED_FIELD_EX32(f->cmd_info, CMD_INFO_ADDR_MODE)) {
+    case 0x0u: /* AddrDisabled */
+        return 0u;
+    case 0x1u: /* AddrCfg */
+        return ot_spi_device_is_addr4b_en(s) ? 4u : 3u;
+    case 0x2u: /* Addr3B */
+        return 3u;
+    case 0x3u: /* Addr4B */
+        return 4u;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static bool
+ot_spi_device_is_mailbox_match(const OtSPIDeviceState *s, uint32_t addr)
+{
+    if (!ot_spi_device_is_mailbox_en(s)) {
+        return false;
+    }
+
+    uint32_t mailbox_addr =
+        s->spi_regs[R_MAILBOX_ADDR] & R_MAILBOX_ADDR_UPPER_MASK;
+    return (addr & R_MAILBOX_ADDR_UPPER_MASK) == mailbox_addr;
+}
+
+static void ot_spi_device_release(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+    SpiDeviceBus *bus = &s->bus;
+
+    trace_ot_spi_device_release(s->ot_id);
+
+    BUS_CHANGE_STATE(s, IDLE);
+    bus->byte_count = 0u;
+    bus->failed_transaction = false;
+
+    s->spi_regs[R_STATUS] = R_STATUS_CSB_MASK | R_STATUS_TPM_CSB_MASK;
+
+    bool update_irq = false;
+
+    OtSpiDeviceMode mode = ot_spi_device_get_mode(s);
+
+    switch (mode) {
+    case CTRL_MODE_FLASH:
+    case CTRL_MODE_PASSTHROUGH:
+        /* new uploaded command */
+        if (!ot_fifo32_is_empty(&f->cmd_fifo) && f->new_cmd) {
+            s->spi_regs[R_INTR_STATE] |= INTR_UPLOAD_CMDFIFO_NOT_EMPTY_MASK;
+            update_irq = true;
+        }
+        /* update upload status register with payload information */
+        if ((mode == CTRL_MODE_FLASH && f->state == SPI_FLASH_UP_PAYLOAD) ||
+            (mode == CTRL_MODE_PASSTHROUGH &&
+             f->state == SPI_FLASH_PASSTHROUGH_UP_PAYLOAD)) {
+            unsigned payload_start, payload_len;
+            if (f->pos > SPI_SRAM_PAYLOAD_SIZE) {
+                payload_start = f->pos % SPI_SRAM_PAYLOAD_SIZE;
+                payload_len = SPI_SRAM_PAYLOAD_SIZE;
+                s->spi_regs[R_INTR_STATE] |= INTR_UPLOAD_PAYLOAD_OVERFLOW_MASK;
+                update_irq = true;
+                trace_ot_spi_device_flash_overflow(s->ot_id, "payload");
+            } else {
+                payload_start = 0u;
+                payload_len = f->pos;
+            }
+            s->spi_regs[R_UPLOAD_STATUS2] =
+                FIELD_DP32(0, UPLOAD_STATUS2, PAYLOAD_START_IDX, payload_start);
+            s->spi_regs[R_UPLOAD_STATUS2] =
+                FIELD_DP32(s->spi_regs[R_UPLOAD_STATUS2], UPLOAD_STATUS2,
+                           PAYLOAD_DEPTH, payload_len);
+            trace_ot_spi_device_flash_payload(s->ot_id, f->pos, payload_start,
+                                              payload_len);
+        }
+        /*
+         * "shows the last address accessed by the host system."
+         * "does not show the commands falling into the mailbox region or
+         *  Read SFDP command’s address."
+         */
+        if (f->slot >= SLOT_HW_READ_NORMAL && f->slot <= SLOT_HW_READ_QUAD_IO &&
+            !ot_spi_device_is_mailbox_match(s, f->last_read_addr)) {
+            trace_ot_spi_device_update_last_read_addr(s->ot_id,
+                                                      f->last_read_addr);
+            s->spi_regs[R_LAST_READ_ADDR] = f->last_read_addr;
+        }
+        FLASH_CHANGE_STATE(s, IDLE);
+        break;
+    default:
+        break;
+    }
+
+    bool upload_intr = false;
+    switch (mode) {
+    case CTRL_MODE_FLASH:
+        upload_intr = ot_spi_device_is_sw_command(f->slot);
+        break;
+    case CTRL_MODE_PASSTHROUGH:
+        /*
+         * @todo add support for payload interrupt management in Passthrough
+         * mode.
+         */
+        if (f->pos) {
+            upload_intr = true;
+        }
+        /* passthrough mode: release CS */
+        ibex_irq_raise(&s->passthrough_cs);
+        break;
+    default:
+        break;
+    }
+
+    f->new_cmd = false;
+
+    if (upload_intr) {
+        if (f->pos) {
+            s->spi_regs[R_INTR_STATE] |= INTR_UPLOAD_PAYLOAD_NOT_EMPTY_MASK;
+            update_irq = true;
+        }
+    }
+
+    if (update_irq) {
+        ot_spi_device_update_irqs(s);
+    }
+}
+
+static void ot_spi_device_flash_pace_spibus(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    timer_del(f->irq_timer);
+    int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+    trace_ot_spi_device_flash_pace(s->ot_id, "set",
+                                   timer_pending(f->irq_timer));
+    timer_mod(f->irq_timer, now + SPI_BUS_FLASH_READ_DELAY_NS);
+}
+
+static void ot_spi_device_flash_clear_readbuffer(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    f->next_buffer_addr = SPI_SRAM_READ_SIZE;
+    f->watermark_crossed = false;
+}
+
+static bool
+ot_spi_device_flash_match_command_slot(OtSPIDeviceState *s, uint8_t cmd)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    g_assert(f->state == SPI_FLASH_IDLE);
+
+    /*
+     * Find and match the opcode in the CMD_INFO registers. In case of
+     * multiple matching entries, the last one is used.
+     */
+    bool matched = false;
+    for (unsigned ix = 0u; ix < SLOT_COUNT; ix++) {
+        uint32_t cmd_info = s->spi_regs[R_CMD_INFO_0 + ix];
+        if (cmd == (uint8_t)SHARED_FIELD_EX32(cmd_info, CMD_INFO_OPCODE)) {
+            if (SHARED_FIELD_EX32(cmd_info, CMD_INFO_VALID)) {
+                f->slot = ix;
+                f->cmd_info = cmd_info;
+                matched = true;
+                const char *type =
+                    ot_spi_device_is_sw_command(f->slot) ? "SW" : "HW";
+                trace_ot_spi_device_flash_match(s->ot_id, type, cmd, f->slot);
+            } else {
+                trace_ot_spi_device_flash_disabled_slot(s->ot_id, cmd, ix);
+            }
+        }
+    }
+
+    if (matched) {
+        const char *type = ot_spi_device_is_sw_command(f->slot) ? "SW" : "HW";
+        trace_ot_spi_device_flash_new_command(s->ot_id, type, cmd, f->slot);
+        return true;
+    }
+
+    trace_ot_spi_device_flash_unmatched_command(s->ot_id, cmd);
+    return false;
+}
+
+static void ot_spi_device_flash_try_upload(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    if (ot_spi_device_flash_command_is_upload(f)) {
+        bool busy = (bool)(f->cmd_info & CMD_INFO_BUSY_MASK);
+        if (busy) {
+            s->spi_regs[R_FLASH_STATUS] |= R_FLASH_STATUS_BUSY_MASK;
+        }
+        if (ot_fifo32_is_full(&f->cmd_fifo)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: cmd fifo overflow",
+                          __func__, s->ot_id);
+        } else {
+            uint32_t data = COMMAND_OPCODE(f->cmd_info);
+            data = FIELD_DP32(data, UPLOAD_CMDFIFO, BUSY,
+                              FIELD_EX32(s->spi_regs[R_FLASH_STATUS],
+                                         FLASH_STATUS, BUSY));
+            data = FIELD_DP32(data, UPLOAD_CMDFIFO, WEL,
+                              FIELD_EX32(s->spi_regs[R_FLASH_STATUS],
+                                         FLASH_STATUS, WEL));
+            data = FIELD_DP32(data, UPLOAD_CMDFIFO, ADDR4B_MODE,
+                              ot_spi_device_is_addr4b_en(s));
+            ot_fifo32_push(&f->cmd_fifo, data);
+        }
+        f->new_cmd = true;
+        trace_ot_spi_device_flash_upload(s->ot_id, f->slot, f->cmd_info, busy);
+    }
+}
+
+static void ot_spi_device_flash_decode_read_jedec(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    uint8_t cc_count =
+        (uint8_t)FIELD_EX32(s->spi_regs[R_JEDEC_CC], JEDEC_CC, NUM_CC);
+    uint8_t cc_code =
+        (uint8_t)FIELD_EX32(s->spi_regs[R_JEDEC_CC], JEDEC_CC, CC);
+    uint8_t jedec_manuf =
+        (uint8_t)FIELD_EX32(s->spi_regs[R_JEDEC_ID], JEDEC_ID, MF);
+    uint16_t jedec_device =
+        (uint16_t)FIELD_EX32(s->spi_regs[R_JEDEC_ID], JEDEC_ID, DEVICE);
+    memset(f->buffer, (int)(uint8_t)cc_code, (size_t)cc_count);
+    f->len = cc_count;
+    f->buffer[f->len++] = jedec_manuf;
+    /*
+     * For some reason, OpenTitan device byte-swaps the device field.
+     * This is not documented, but the "flash density" field is sent first
+     *
+     * JEDEC_ID register:  |  00  |  MF  |  DEVICE_ID  |  content
+     *                     |31..24|23..16|   15 .. 0   |  bits
+     *                     |  B3  |  B2  |  B1  |  B0  |  bytes
+     * is sent in the following order: B2-B0-B1
+     */
+    f->buffer[f->len++] = (uint8_t)(jedec_device >> 0u);
+    f->buffer[f->len++] = (uint8_t)(jedec_device >> 8u);
+    /* after the end of JEDEC ID is 0s on OpenTitan */
+    memset(&f->buffer[f->len], (int)0u, SPI_FLASH_BUFFER_SIZE - f->len);
+    f->len = SPI_FLASH_BUFFER_SIZE;
+    f->src = f->buffer;
+    FLASH_CHANGE_STATE(s, BUFFER);
+}
+
+static void ot_spi_device_flash_decode_write_enable(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    bool enable = f->slot == SLOT_HW_WREN;
+    trace_ot_spi_device_flash_exec(s->ot_id, enable ? "WREN" : "WRDI");
+    if (enable) {
+        s->spi_regs[R_FLASH_STATUS] |= R_FLASH_STATUS_WEL_MASK;
+    } else {
+        s->spi_regs[R_FLASH_STATUS] &= ~R_FLASH_STATUS_WEL_MASK;
+    }
+    FLASH_CHANGE_STATE(s, DONE);
+}
+
+static void ot_spi_device_flash_decode_addr4_enable(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    bool enable = f->slot == SLOT_HW_EN4B;
+    trace_ot_spi_device_flash_exec(s->ot_id, enable ? "EN4B" : "EX4B");
+
+    if (enable) {
+        s->spi_regs[R_ADDR_MODE] |= R_ADDR_MODE_ADDR_4B_EN_MASK;
+    } else {
+        s->spi_regs[R_ADDR_MODE] &= ~R_ADDR_MODE_ADDR_4B_EN_MASK;
+    }
+    FLASH_CHANGE_STATE(s, DONE);
+}
+
+static void ot_spi_device_flash_decode_read_status(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    g_assert(f->slot <= SLOT_HW_READ_STATUS3);
+
+    uint32_t status = s->spi_regs[R_FLASH_STATUS];
+    f->buffer[0] = (uint8_t)(status >> (f->slot * 8u));
+    f->len = sizeof(uint8_t);
+    f->src = f->buffer;
+    f->loop = true;
+
+    trace_ot_spi_device_flash_read_status(s->ot_id, f->slot, f->buffer[0]);
+
+    FLASH_CHANGE_STATE(s, BUFFER);
+}
+
+static void ot_spi_device_flash_decode_read_sfdp(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    f->src = f->buffer;
+    FLASH_CHANGE_STATE(s, COLLECT);
+    f->loop = true;
+    f->len = 4; /* 3-byte address + 1 dummy byte */
+}
+
+static void ot_spi_device_flash_decode_read_data(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    unsigned dummy = 1;
+
+    switch (f->slot) {
+    case SLOT_HW_READ_NORMAL:
+        dummy = 0;
+        break;
+    case SLOT_HW_READ_FAST:
+    case SLOT_HW_READ_DUAL:
+    case SLOT_HW_READ_QUAD:
+    case SLOT_HW_READ_DUAL_IO:
+    case SLOT_HW_READ_QUAD_IO:
+        dummy = 1u;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    f->src = f->buffer;
+    FLASH_CHANGE_STATE(s, COLLECT);
+    f->len = dummy + (ot_spi_device_is_addr4b_en(s) ? 4u : 3u);
+}
+
+static void ot_spi_device_flash_decode_hw_command(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    switch (f->slot) {
+    case SLOT_HW_READ_STATUS1:
+    case SLOT_HW_READ_STATUS2:
+    case SLOT_HW_READ_STATUS3:
+        ot_spi_device_flash_decode_read_status(s);
+        break;
+    case SLOT_HW_READ_JEDEC:
+        ot_spi_device_flash_decode_read_jedec(s);
+        break;
+    case SLOT_HW_READ_SFDP:
+        ot_spi_device_flash_decode_read_sfdp(s);
+        break;
+    case SLOT_HW_READ_NORMAL:
+    case SLOT_HW_READ_FAST:
+    case SLOT_HW_READ_DUAL:
+    case SLOT_HW_READ_QUAD:
+    case SLOT_HW_READ_DUAL_IO:
+    case SLOT_HW_READ_QUAD_IO:
+        ot_spi_device_flash_decode_read_data(s);
+        break;
+    case SLOT_HW_EN4B:
+    case SLOT_HW_EX4B:
+        ot_spi_device_flash_decode_addr4_enable(s);
+        break;
+    case SLOT_HW_WREN:
+    case SLOT_HW_WRDI:
+        ot_spi_device_flash_decode_write_enable(s);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void ot_spi_device_flash_exec_read_sfdp(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    unsigned address = ldl_be_p(f->src) >> 8u; /* discard dummy byte */
+    f->pos = address % SPI_SRAM_SFDP_SIZE;
+    f->len = SPI_SRAM_SFDP_SIZE;
+    f->src = &((uint8_t *)s->sram)[SPI_SRAM_SFDP_OFFSET];
+    f->loop = true;
+    FLASH_CHANGE_STATE(s, BUFFER);
+}
+
+static void ot_spi_device_flash_exec_read_data(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    uint32_t address = ldl_be_p(f->buffer);
+    if (!ot_spi_device_is_addr4b_en(s)) {
+        address >>= 8u;
+    }
+
+    trace_ot_spi_device_flash_set_read_addr(s->ot_id, (uint32_t)address);
+
+    if ((address >> SPI_SRAM_READ_LOG2_SIZE) + 1u !=
+        (f->next_buffer_addr >> SPI_SRAM_READ_LOG2_SIZE)) {
+        /*
+         * either the FLASH_READ_BUFFER_CLR has not been triggered, or
+         * subsequent read commands do not cover a continuous address range
+         * (% buffer size)
+         */
+        trace_ot_spi_device_flash_read_config_error(s->ot_id, address,
+                                                    f->next_buffer_addr);
+    }
+
+    f->address = address;
+    FLASH_CHANGE_STATE(s, READ);
+
+    f->src = (uint8_t *)s->sram;
+    f->loop = true;
+}
+
+static void ot_spi_device_flash_exec_command(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    switch (f->slot) {
+    case SLOT_HW_READ_SFDP:
+        ot_spi_device_flash_exec_read_sfdp(s);
+        break;
+    case SLOT_HW_READ_NORMAL:
+    case SLOT_HW_READ_FAST:
+    case SLOT_HW_READ_DUAL:
+    case SLOT_HW_READ_QUAD:
+    case SLOT_HW_READ_DUAL_IO:
+    case SLOT_HW_READ_QUAD_IO:
+        ot_spi_device_flash_exec_read_data(s);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static bool ot_spi_device_flash_collect(OtSPIDeviceState *s, uint8_t rx)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    g_assert(f->src);
+
+    f->src[f->pos++] = rx;
+
+    return f->pos != f->len;
+}
+
+static uint8_t ot_spi_device_flash_read_buffer(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    g_assert(f->src);
+
+    uint8_t tx = (f->pos < f->len) ? f->src[f->pos] : SPI_DEFAULT_TX_RX_VALUE;
+
+    f->pos++;
+    if (f->pos >= f->len) {
+        if (f->loop) {
+            f->pos = 0u;
+        } else {
+            FLASH_CHANGE_STATE(s, DONE);
+        }
+    }
+
+    return tx;
+}
+
+static uint8_t ot_spi_device_flash_read_data(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    g_assert(f->src);
+
+    bool pace_spibus = false;
+    uint8_t tx;
+
+    f->pos = f->address & (FLASH_READ_BUFFER_SIZE - 1u);
+
+    if (ot_spi_device_is_mailbox_match(s, f->address)) {
+        /*
+         * Sequencing is the very same whether mailbox is matched or not,
+         * otherwise, readbuf event would not be emitted, pages would not
+         * be reloaded and HW buffer not refilled by the FW for the pages that
+         * follow the mailbox (address-wide).
+         * Not sure this is how the HW actually works, and there is no SW
+         * example that fully demontrates how the mailbox vs. regular pages are
+         * supposed to work.
+         * The current implementation therefore only substitutes the SPI MISO
+         * value, but acts exactly as if the virtual flash pages where used.
+         * This might be right or wrong.
+         */
+        uint8_t *src = f->src + SPI_SRAM_MBX_OFFSET;
+        unsigned pos = f->address & (SPI_SRAM_MBX_SIZE - 1u);
+        tx = src[pos];
+    } else {
+        uint8_t *src = f->src + SPI_SRAM_READ0_OFFSET;
+        tx = src[f->pos];
+    }
+
+    uint32_t threshold = s->spi_regs[R_READ_THRESHOLD];
+    /* "If 0, disable the watermark."" */
+    if (threshold) {
+        uint32_t lowaddr = f->address & (SPI_SRAM_READ_SIZE - 1u);
+
+        /* "when the host access above or equal to the threshold" */
+        if (lowaddr >= threshold) {
+            if (!f->watermark_crossed) {
+                trace_ot_spi_device_flash_read_threshold(s->ot_id, f->address,
+                                                         threshold);
+                s->spi_regs[R_INTR_STATE] |= INTR_READBUF_WATERMARK_MASK;
+                pace_spibus = true;
+                ot_spi_device_update_irqs(s);
+            }
+            /* should be reset on buffer switch */
+            f->watermark_crossed = true;
+        }
+    }
+
+    f->last_read_addr = f->address;
+    f->address += 1u;
+
+    /*
+     * "If a new read command crosses the current buffer boundary, the SW clears
+     *  the cross event for the HW to detect the address cross event again."
+     */
+    bool flip = f->address == f->next_buffer_addr;
+    if (flip) {
+        f->watermark_crossed = false;
+        f->next_buffer_addr += SPI_SRAM_READ_SIZE;
+        s->spi_regs[R_INTR_STATE] |= INTR_READBUF_FLIP_MASK;
+        trace_ot_spi_device_flash_cross_buffer(s->ot_id, f->address,
+                                               f->next_buffer_addr);
+        pace_spibus = true;
+        ot_spi_device_update_irqs(s);
+    }
+
+    if (pace_spibus) {
+        ot_spi_device_flash_pace_spibus(s);
+    }
+
+    return tx;
+}
+
+static void ot_spi_device_flash_init_upload(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    f->pos = 0;
+    f->len =
+        ot_spi_device_flash_command_has_payload(f) ? SPI_SRAM_PAYLOAD_SIZE : 0u;
+    s->spi_regs[R_UPLOAD_STATUS2] = 0;
+    g_assert(f->payload);
+    FLASH_CHANGE_STATE(s, UP_PAYLOAD);
+}
+
+static void ot_spi_device_flash_decode_sw_command(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    unsigned addr_size = ot_spi_device_get_command_address_size(s);
+    f->pos = 0u;
+    if (addr_size != 0u) {
+        f->len = addr_size;
+        FLASH_CHANGE_STATE(s, UP_ADDR);
+    } else if (f->cmd_info & CMD_INFO_DUMMY_EN_MASK) {
+        f->len = 1u;
+        FLASH_CHANGE_STATE(s, UP_DUMMY);
+    } else if (ot_spi_device_flash_command_is_upload(f)) {
+        ot_spi_device_flash_init_upload(s);
+    } else {
+        /*
+         * Any payload sent with a non-uploaded SW command is ignored. The
+         * behaviour of this error case is not well specified for the hardware.
+         */
+        s->spi_regs[R_UPLOAD_STATUS2] = 0;
+    }
+}
+
+static void ot_spi_device_flash_exec_sw_command(OtSPIDeviceState *s, uint8_t rx)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    switch (f->state) {
+    case SPI_FLASH_UP_ADDR:
+        if (f->pos < f->len) {
+            f->buffer[f->pos] = rx;
+        }
+        f->pos++;
+        if (f->pos == f->len) {
+            f->address = ldl_be_p(f->buffer);
+            if (!ot_spi_device_is_addr4b_en(s)) {
+                f->address >>= 8u;
+            }
+            if (!ot_fifo32_is_full(&f->address_fifo)) {
+                trace_ot_spi_device_flash_push_address(s->ot_id, f->address);
+                ot_fifo32_push(&f->address_fifo, f->address);
+            } else {
+                /* waiting for answer from OT team here */
+                g_assert_not_reached();
+            }
+            if (f->cmd_info & CMD_INFO_DUMMY_EN_MASK) {
+                f->len = 1u;
+                FLASH_CHANGE_STATE(s, UP_DUMMY);
+            } else if (ot_spi_device_flash_command_is_upload(f)) {
+                ot_spi_device_flash_init_upload(s);
+            } else {
+                /*
+                 * Any payload sent with a non-uploaded SW command is ignored.
+                 * The behaviour of this error case is not well specified for
+                 * the hardware.
+                 */
+                FLASH_CHANGE_STATE(s, DONE);
+            }
+        }
+        break;
+    case SPI_FLASH_UP_DUMMY:
+        f->pos++;
+        g_assert(f->pos == f->len);
+        f->pos = 0u;
+        if (ot_spi_device_flash_command_is_upload(f)) {
+            ot_spi_device_flash_init_upload(s);
+        } else {
+            /*
+             * Any payload sent with a non-uploaded SW command is ignored. The
+             * behaviour of this error case is not well specified for the
+             * hardware.
+             */
+            FLASH_CHANGE_STATE(s, DONE);
+        }
+        break;
+    case SPI_FLASH_UP_PAYLOAD:
+        if (ot_spi_device_flash_command_is_rx_payload(f)) {
+            f->payload[f->pos % SPI_SRAM_PAYLOAD_SIZE] = rx;
+        }
+        f->pos++;
+        break;
+    case SPI_FLASH_DONE:
+        FLASH_CHANGE_STATE(s, ERROR);
+    /* fallthrough */
+    case SPI_FLASH_ERROR:
+        trace_ot_spi_device_flash_byte_unexpected(s->ot_id, rx);
+        BUS_CHANGE_STATE(s, DISCARD);
+        break;
+    case SPI_FLASH_COLLECT:
+    case SPI_FLASH_BUFFER:
+    case SPI_FLASH_READ:
+    default:
+        g_assert_not_reached();
+        break;
+    }
+}
+
+static uint8_t ot_spi_device_flash_transfer(OtSPIDeviceState *s, uint8_t rx)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    trace_ot_spi_device_flash_transfer(s->ot_id, "->", rx);
+
+    uint8_t tx = SPI_DEFAULT_TX_RX_VALUE;
+
+    switch (f->state) {
+    case SPI_FLASH_IDLE:
+        f->slot = SLOT_INVALID;
+        f->pos = 0;
+        f->len = 0;
+        f->src = NULL;
+        f->loop = false;
+        if (ot_spi_device_flash_match_command_slot(s, rx)) {
+            if (ot_spi_device_is_sw_command(f->slot)) {
+                ot_spi_device_flash_decode_sw_command(s);
+                ot_spi_device_flash_try_upload(s);
+            } else {
+                ot_spi_device_flash_decode_hw_command(s);
+            }
+        } else {
+            /* this command cannot be processed, discard all remaining bytes */
+            trace_ot_spi_device_flash_unknown_command(s->ot_id, rx);
+            FLASH_CHANGE_STATE(s, ERROR);
+            BUS_CHANGE_STATE(s, DISCARD);
+        }
+        break;
+    case SPI_FLASH_COLLECT:
+        if (!ot_spi_device_flash_collect(s, rx)) {
+            ot_spi_device_flash_exec_command(s);
+        }
+        break;
+    case SPI_FLASH_BUFFER:
+        tx = ot_spi_device_flash_read_buffer(s);
+        break;
+    case SPI_FLASH_READ:
+        tx = ot_spi_device_flash_read_data(s);
+        break;
+    case SPI_FLASH_UP_ADDR:
+    case SPI_FLASH_UP_DUMMY:
+    case SPI_FLASH_UP_PAYLOAD:
+        ot_spi_device_flash_exec_sw_command(s, rx);
+        break;
+    case SPI_FLASH_DONE:
+        FLASH_CHANGE_STATE(s, ERROR);
+        break;
+    case SPI_FLASH_ERROR:
+        break;
+    default:
+        error_setg(&error_fatal, "unexpected state %s[%d]\n",
+                   FLASH_STATE_NAME(f->state), f->state);
+        g_assert_not_reached();
+    }
+
+    trace_ot_spi_device_flash_transfer(s->ot_id, "<-", tx);
+
+    return tx;
+}
+
+static uint8_t ot_spi_device_flash_spi_transfer(OtSPIDeviceState *s, uint8_t rx)
+{
+    OtSPIHostClass *spihostc = OT_SPI_HOST_GET_CLASS(s->spi_host);
+    return spihostc->ssi_downstream_transfer(s->spi_host, rx);
+}
+
+static void ot_spi_device_flash_resume_read(void *opaque)
+{
+    OtSPIDeviceState *s = opaque;
+
+    trace_ot_spi_device_flash_pace(s->ot_id, "release",
+                                   timer_pending(s->flash.irq_timer));
+    qemu_chr_fe_accept_input(&s->chr);
+}
+
+static bool
+ot_spi_device_flash_command_is_filter(OtSPIDeviceState *s, uint8_t cmd)
+{
+    return (bool)(s->spi_regs[R_CMD_FILTER_0 + (cmd / REG_BITS)] &
+                  (1u << (cmd % REG_BITS)));
+}
+
+static uint8_t ot_spi_device_swap_byte_data(
+    uint8_t byte, unsigned byte_sel, uint32_t swap_mask, uint32_t swap_data)
+{
+    g_assert(byte_sel < 4u);
+    uint8_t mask = (uint8_t)(swap_mask >> (byte_sel * 8u));
+    uint8_t data = (uint8_t)(swap_data >> (byte_sel * 8u));
+    return (byte & ~mask) | (data & mask);
+}
+
+static bool ot_spi_device_flash_try_intercept_hw_command(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    uint32_t intercept_val32 = s->spi_regs[R_INTERCEPT_EN];
+    bool intercepted = false;
+
+    switch (f->slot) {
+    case SLOT_HW_READ_STATUS1:
+    case SLOT_HW_READ_STATUS2:
+    case SLOT_HW_READ_STATUS3:
+        if (FIELD_EX32(intercept_val32, INTERCEPT_EN, STATUS)) {
+            ot_spi_device_flash_decode_read_status(s);
+            intercepted = true;
+        }
+        break;
+    case SLOT_HW_READ_JEDEC:
+        if (FIELD_EX32(intercept_val32, INTERCEPT_EN, JEDEC)) {
+            ot_spi_device_flash_decode_read_jedec(s);
+            intercepted = true;
+        }
+        break;
+    case SLOT_HW_READ_SFDP:
+        if (FIELD_EX32(intercept_val32, INTERCEPT_EN, SFDP)) {
+            ot_spi_device_flash_decode_read_sfdp(s);
+            intercepted = true;
+        }
+        break;
+    case SLOT_HW_READ_NORMAL:
+    case SLOT_HW_READ_FAST:
+    case SLOT_HW_READ_DUAL:
+    case SLOT_HW_READ_QUAD:
+    case SLOT_HW_READ_DUAL_IO:
+    case SLOT_HW_READ_QUAD_IO:
+        /* We try to intercept these at every read after an address is given */
+        break;
+    case SLOT_HW_EN4B:
+    case SLOT_HW_EX4B:
+        /* Always intercepted */
+        ot_spi_device_flash_decode_addr4_enable(s);
+        intercepted = true;
+        break;
+    case SLOT_HW_WREN:
+    case SLOT_HW_WRDI:
+        /* Always intercepted */
+        ot_spi_device_flash_decode_write_enable(s);
+        intercepted = true;
+        break;
+    default:
+        break;
+    }
+
+    if (intercepted) {
+        trace_ot_spi_device_flash_intercepted_command(s->ot_id, f->slot);
+    }
+
+    return intercepted;
+}
+
+static void ot_spi_device_flash_passthrough_command_params(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    OtSpiCommandParams *p = &f->cmd_params;
+
+    p->address_size = ot_spi_device_get_command_address_size(s);
+    p->cmd_addr_swap =
+        (bool)SHARED_FIELD_EX32(f->cmd_info, CMD_INFO_ADDR_SWAP_EN);
+    p->cmd_payload_swap =
+        (bool)SHARED_FIELD_EX32(f->cmd_info, CMD_INFO_PAYLOAD_SWAP_EN);
+    p->cmd_payload_dir_out =
+        (bool)SHARED_FIELD_EX32(f->cmd_info, CMD_INFO_PAYLOAD_DIR);
+
+    /*
+     * SPI transfers in QEMU are modelled at the granularity of bytes,
+     * therefore we can only support either 0 dummy cycles (dummy_en = 0), or
+     * 8 dummy cycles (dummy_en = 1, dummy_size = 7). Anything in between we
+     * round up to 1 dummy byte, so we only check dummy_en.
+     */
+    p->cmd_dummy = (bool)SHARED_FIELD_EX32(f->cmd_info, CMD_INFO_DUMMY_EN);
+
+    if (p->cmd_dummy &&
+        ((uint8_t)SHARED_FIELD_EX32(f->cmd_info, CMD_INFO_DUMMY_SIZE) != 7u)) {
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: %s: slot %d: set non-zero dummy cycle count is "
+                      "unsupported, using 8 cycles (1 byte)",
+                      __func__, s->ot_id, f->slot);
+    }
+
+    if (SHARED_FIELD_EX32(f->cmd_info, CMD_INFO_READ_PIPELINE_MODE) != 0u) {
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: %s: slot %d: 2-stage read pipeline is unsupported",
+                      __func__, s->ot_id, f->slot);
+    }
+
+    trace_ot_spi_device_flash_command_params(s->ot_id, p->address_size,
+                                             p->cmd_addr_swap, p->cmd_dummy,
+                                             p->cmd_payload_swap);
+}
+
+static void
+ot_spi_device_flash_passthrough_address_phase(OtSPIDeviceState *s, uint8_t rx)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    OtSpiCommandParams *p = &f->cmd_params;
+
+    f->len = 4u;
+
+    f->buffer[f->pos] = rx;
+    if (p->cmd_addr_swap) {
+        unsigned byte_sel = (f->len - f->pos - 1u);
+        uint8_t swapped_rx =
+            ot_spi_device_swap_byte_data(rx, byte_sel,
+                                         s->spi_regs[R_ADDR_SWAP_MASK],
+                                         s->spi_regs[R_ADDR_SWAP_DATA]);
+        trace_ot_spi_device_flash_swap_byte(s->ot_id, "address", byte_sel, rx,
+                                            swapped_rx);
+        rx = swapped_rx;
+    }
+
+    (void)ot_spi_device_flash_spi_transfer(s, rx);
+
+    f->pos++;
+    if (f->pos == f->len) { /* end of address phase */
+        f->pos = 0u;
+        f->address = ldl_be_p(f->buffer);
+
+        /* if upload command, push address FIFO */
+        if (ot_spi_device_flash_command_is_upload(f)) {
+            if (!ot_fifo32_is_full(&f->address_fifo)) {
+                ot_fifo32_push(&f->address_fifo, f->address);
+            } else {
+                g_assert_not_reached();
+            }
+        }
+
+        if (p->cmd_dummy) {
+            FLASH_CHANGE_STATE(s, PASSTHROUGH_UP_DUMMY);
+        } else {
+            FLASH_CHANGE_STATE(s, PASSTHROUGH_UP_PAYLOAD);
+        }
+    }
+}
+
+static void ot_spi_device_flash_passthrough_dummy_phase(OtSPIDeviceState *s)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    OtSpiCommandParams *p = &f->cmd_params;
+
+    g_assert(p->cmd_dummy);
+
+    (void)ot_spi_device_flash_spi_transfer(s, SPI_DEFAULT_TX_RX_VALUE);
+
+    FLASH_CHANGE_STATE(s, PASSTHROUGH_UP_PAYLOAD);
+}
+
+static uint8_t
+ot_spi_device_flash_passthrough_payload_phase(OtSPIDeviceState *s, uint8_t rx)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    OtSpiCommandParams *p = &f->cmd_params;
+
+    if (p->cmd_payload_dir_out) { /* flash -> SPI Host */
+
+        /* try intercept read to mailbox region */
+        if (FIELD_EX32(s->spi_regs[R_INTERCEPT_EN], INTERCEPT_EN, MBX) != 0u) {
+            if (f->slot >= SLOT_HW_READ_NORMAL &&
+                f->slot <= SLOT_HW_READ_QUAD_IO) {
+                if (p->address_size != 0u) {
+                    if (ot_spi_device_is_mailbox_match(s, f->address)) {
+                        trace_ot_spi_device_flash_intercept_mailbox(s->ot_id,
+                                                                    f->address);
+                        unsigned word_idx =
+                            (f->address >> 2u) & (SPI_SRAM_MBX_SIZE - 1u);
+                        unsigned byte_idx = f->address % 4u;
+                        uint32_t word =
+                            s->sram[(SPI_SRAM_MBX_OFFSET >> 2u) + word_idx];
+                        uint8_t tx = (uint8_t)(word >> (8u * byte_idx));
+
+                        f->address += 1u;
+                        return tx;
+                    }
+                } else {
+                    qemu_log_mask(
+                        LOG_GUEST_ERROR,
+                        "%s: %s: Mailbox read intercept enabled but HW READ "
+                        "CMD %d has no address field",
+                        __func__, s->ot_id, f->slot);
+                }
+            }
+        }
+
+        /* common out path: read from flash, update last read address */
+        f->last_read_addr = f->address;
+        f->address += 1u;
+        return ot_spi_device_flash_spi_transfer(s, SPI_DEFAULT_TX_RX_VALUE);
+
+    } /* SPI Host -> flash */
+
+    /* if this command is to be uploaded, upload payload */
+    if (ot_spi_device_flash_command_is_upload(f)) {
+        f->payload[f->pos % SPI_SRAM_PAYLOAD_SIZE] = rx;
+    }
+
+    /* if payload swap is enabled, swap the first 4 bytes of payload */
+    if (f->pos < 4u && p->cmd_payload_swap) {
+        uint8_t swapped_rx =
+            ot_spi_device_swap_byte_data(rx, f->pos,
+                                         s->spi_regs[R_PAYLOAD_SWAP_MASK],
+                                         s->spi_regs[R_PAYLOAD_SWAP_DATA]);
+        trace_ot_spi_device_flash_swap_byte(s->ot_id, "payload", f->pos, rx,
+                                            swapped_rx);
+        rx = swapped_rx;
+    }
+
+    f->pos++;
+
+    (void)ot_spi_device_flash_spi_transfer(s, rx);
+
+    return SPI_DEFAULT_TX_RX_VALUE;
+}
+
+static uint8_t
+ot_spi_device_flash_transfer_passthrough(OtSPIDeviceState *s, uint8_t rx)
+{
+    SpiDeviceFlash *f = &s->flash;
+
+    OtSpiCommandParams *p = &f->cmd_params;
+
+    trace_ot_spi_device_flash_transfer(s->ot_id, "->", rx);
+
+    uint8_t tx = SPI_DEFAULT_TX_RX_VALUE;
+
+    switch (f->state) {
+    case SPI_FLASH_IDLE:
+        f->slot = SLOT_INVALID;
+        f->cmd_info = 0u;
+        f->pos = 0u;
+        f->len = 0u;
+        f->address = 0u;
+        f->src = NULL;
+        f->loop = false;
+        memset(f->buffer, 0u, 4u);
+        /*
+         * Unmatched commands are not necessarily erroneous and the HW
+         * will continue the transfer with these default parameters,
+         * unless it is filtered later on.
+         */
+        memset(&f->cmd_params, 0u, sizeof(OtSpiCommandParams));
+
+        if (ot_spi_device_flash_match_command_slot(s, rx)) {
+            if (ot_spi_device_flash_try_intercept_hw_command(s)) {
+                break;
+            }
+            /* only matched software/not intercepted commands can be uploaded */
+            ot_spi_device_flash_try_upload(s);
+            ot_spi_device_flash_passthrough_command_params(s);
+        }
+
+        if (ot_spi_device_flash_command_is_filter(s, rx)) {
+            /* command opcode is filtered, do not send to downstream */
+            trace_ot_spi_device_flash_filtered_command(s->ot_id, rx);
+            ibex_irq_raise(&s->passthrough_cs);
+        } else {
+            /* issue the command: assert chip select (active low) */
+            ibex_irq_lower(&s->passthrough_cs);
+            /* pass the opcode through */
+            tx = ot_spi_device_flash_spi_transfer(s, rx);
+        }
+
+        if (p->address_size != 0u) {
+            /* command has address field */
+            f->pos = 4u - p->address_size;
+            FLASH_CHANGE_STATE(s, PASSTHROUGH_UP_ADDR);
+            break;
+        }
+        if (p->cmd_dummy) {
+            /* no address field, but has dummy */
+            FLASH_CHANGE_STATE(s, PASSTHROUGH_UP_DUMMY);
+            break;
+        }
+        /* no address or dummy field, rest is payload */
+        FLASH_CHANGE_STATE(s, PASSTHROUGH_UP_PAYLOAD);
+        break;
+    case SPI_FLASH_PASSTHROUGH_UP_ADDR:
+        ot_spi_device_flash_passthrough_address_phase(s, rx);
+        break;
+    case SPI_FLASH_PASSTHROUGH_UP_DUMMY:
+        ot_spi_device_flash_passthrough_dummy_phase(s);
+        break;
+    case SPI_FLASH_PASSTHROUGH_UP_PAYLOAD:
+        tx = ot_spi_device_flash_passthrough_payload_phase(s, rx);
+        break;
+    /* HW intercepted commands */
+    case SPI_FLASH_COLLECT:
+        if (!ot_spi_device_flash_collect(s, rx)) {
+            g_assert(f->slot == SLOT_HW_READ_SFDP);
+            ot_spi_device_flash_exec_read_sfdp(s);
+        }
+        break;
+    case SPI_FLASH_BUFFER:
+        g_assert(f->slot <= SLOT_HW_READ_SFDP);
+        tx = ot_spi_device_flash_read_buffer(s);
+        break;
+    case SPI_FLASH_DONE:
+        FLASH_CHANGE_STATE(s, ERROR);
+        break;
+    case SPI_FLASH_ERROR:
+        break;
+    default:
+        error_setg(&error_fatal, "unexpected state %s[%d]",
+                   FLASH_STATE_NAME(f->state), f->state);
+        g_assert_not_reached();
+    }
+
+    trace_ot_spi_device_flash_transfer(s->ot_id, "<-", tx);
+
+    return tx;
+}
+
+static uint64_t
+ot_spi_device_spi_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtSPIDeviceState *s = opaque;
+    (void)size;
+    SpiDeviceFlash *f = &s->flash;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_CONTROL:
+    case R_CFG:
+    case R_INTERCEPT_EN:
+    case R_ADDR_MODE:
+    case R_LAST_READ_ADDR:
+    case R_FLASH_STATUS:
+    case R_JEDEC_CC:
+    case R_JEDEC_ID:
+    case R_READ_THRESHOLD:
+    case R_MAILBOX_ADDR:
+    case R_UPLOAD_STATUS2:
+    case R_CMD_FILTER_0:
+    case R_CMD_FILTER_1:
+    case R_CMD_FILTER_2:
+    case R_CMD_FILTER_3:
+    case R_CMD_FILTER_4:
+    case R_CMD_FILTER_5:
+    case R_CMD_FILTER_6:
+    case R_CMD_FILTER_7:
+    case R_ADDR_SWAP_MASK:
+    case R_ADDR_SWAP_DATA:
+    case R_PAYLOAD_SWAP_MASK:
+    case R_PAYLOAD_SWAP_DATA:
+    case R_CMD_INFO_0:
+    case R_CMD_INFO_1:
+    case R_CMD_INFO_2:
+    case R_CMD_INFO_3:
+    case R_CMD_INFO_4:
+    case R_CMD_INFO_5:
+    case R_CMD_INFO_6:
+    case R_CMD_INFO_7:
+    case R_CMD_INFO_8:
+    case R_CMD_INFO_9:
+    case R_CMD_INFO_10:
+    case R_CMD_INFO_11:
+    case R_CMD_INFO_12:
+    case R_CMD_INFO_13:
+    case R_CMD_INFO_14:
+    case R_CMD_INFO_15:
+    case R_CMD_INFO_16:
+    case R_CMD_INFO_17:
+    case R_CMD_INFO_18:
+    case R_CMD_INFO_19:
+    case R_CMD_INFO_20:
+    case R_CMD_INFO_21:
+    case R_CMD_INFO_22:
+    case R_CMD_INFO_23:
+    case R_CMD_INFO_EN4B:
+    case R_CMD_INFO_EX4B:
+    case R_CMD_INFO_WREN:
+    case R_CMD_INFO_WRDI:
+    case R_STATUS:
+        val32 = s->spi_regs[reg];
+        break;
+    case R_UPLOAD_STATUS:
+        val32 = 0;
+        val32 = FIELD_DP32(val32, UPLOAD_STATUS, CMDFIFO_DEPTH,
+                           ot_fifo32_num_used(&f->cmd_fifo));
+        val32 = FIELD_DP32(val32, UPLOAD_STATUS, CMDFIFO_NOTEMPTY,
+                           !ot_fifo32_is_empty(&f->cmd_fifo));
+        val32 = FIELD_DP32(val32, UPLOAD_STATUS, ADDRFIFO_DEPTH,
+                           ot_fifo32_num_used(&f->address_fifo));
+        val32 = FIELD_DP32(val32, UPLOAD_STATUS, ADDRFIFO_NOTEMPTY,
+                           !ot_fifo32_is_empty(&f->address_fifo));
+        break;
+    case R_UPLOAD_CMDFIFO:
+        if (!ot_fifo32_is_empty(&f->cmd_fifo)) {
+            val32 = ot_fifo32_pop(&f->cmd_fifo);
+        } else {
+            qemu_log_mask(LOG_UNIMP, "%s: %s: CMD_FIFO is empty\n", __func__,
+                          s->ot_id);
+            val32 = 0;
+        }
+        break;
+    case R_UPLOAD_ADDRFIFO:
+        if (!ot_fifo32_is_empty(&f->address_fifo)) {
+            val32 = ot_fifo32_pop(&f->address_fifo);
+        } else {
+            qemu_log_mask(LOG_UNIMP, "%s: %s: ADDR_FIFO is empty\n", __func__,
+                          s->ot_id);
+            val32 = 0;
+        }
+        break;
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, SPI_REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    if (reg != R_INTR_STATE || val32 != 0) {
+        uint32_t pc = ibex_get_current_pc();
+        trace_ot_spi_device_io_spi_read_out(s->ot_id, (uint32_t)addr,
+                                            SPI_REG_NAME(reg), val32, pc);
+    }
+
+    return (uint64_t)val32;
+};
+
+static void ot_spi_device_spi_regs_write(void *opaque, hwaddr addr,
+                                         uint64_t val64, unsigned size)
+{
+    OtSPIDeviceState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_spi_device_io_spi_write_in(s->ot_id, (uint32_t)addr,
+                                        SPI_REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_MASK & ~(INTR_TPM_HEADER_NOT_EMPTY_MASK);
+        s->spi_regs[reg] &= ~val32; /* RW1C */
+        ot_spi_device_update_irqs(s);
+        if (!ot_spi_device_is_tpm_enabled(s) &&
+            !ot_spi_device_flash_is_readbuf_irq(s)) {
+            /*
+             * no need to trigger the timer if in tpm mode or readbuf IRQs have
+             * been cleared.
+             */
+            trace_ot_spi_device_flash_pace(s->ot_id, "clear",
+                                           timer_pending(s->flash.irq_timer));
+            timer_del(s->flash.irq_timer);
+            qemu_chr_fe_accept_input(&s->chr);
+        }
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->spi_regs[reg] = val32;
+        ot_spi_device_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->spi_regs[R_INTR_STATE] |= val32;
+        ot_spi_device_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= ALERT_TEST_MASK;
+        s->spi_regs[reg] = val32;
+        ot_spi_device_update_alerts(s);
+        break;
+    case R_CONTROL:
+        if (val32 & R_CONTROL_FLASH_STATUS_FIFO_CLR_MASK) {
+            if (s->bus.state != SPI_BUS_IDLE) {
+                /*
+                 * "The reset should only be used when the upstream SPI host is
+                 *  known to be inactive."
+                 */
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: %s: Flash status FIFO cleared while SPI "
+                              "host not idle\n",
+                              __func__, s->ot_id);
+                /* clear it anyway, with undefined consequences */
+            }
+            s->spi_regs[R_FLASH_STATUS] = 0x0u; /* reset value */
+        }
+        if (val32 & R_CONTROL_FLASH_READ_BUFFER_CLR_MASK) {
+            if (s->bus.state != SPI_BUS_IDLE) {
+                /*
+                 * "The reset should only be used when the upstream SPI host is
+                 *  known to be inactive."
+                 */
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: %s: Flash read buffer cleared while SPI "
+                              "host not idle",
+                              __func__, s->ot_id);
+                /* clear it anyway, with undefined consequences */
+            }
+            ot_spi_device_flash_clear_readbuffer(s);
+        }
+        val32 &= R_CONTROL_MODE_MASK;
+        if (val32 != (s->spi_regs[reg] & R_CONTROL_MODE_MASK)) {
+            ot_spi_device_clear_modes(s);
+            if (s->bus.state == SPI_BUS_FLASH) {
+                /*
+                 * Hardware assumes that control mode does not change during a
+                 * transaction, so the behaviour is undefined if that happens.
+                 * We choose to cancel any ongoing SPI transfer until the next
+                 * CS.
+                 */
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "%s: %s: Flash mode changed during transfer, "
+                              "discarding rest of transfer\n",
+                              __func__, s->ot_id);
+                BUS_CHANGE_STATE(s, DISCARD);
+            }
+        }
+        s->spi_regs[reg] = val32;
+        switch (ot_spi_device_get_mode(s)) {
+        case CTRL_MODE_INVALID:
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid mode\n", __func__,
+                          s->ot_id);
+        /* fallthrough */
+        case CTRL_MODE_FLASH:
+        case CTRL_MODE_DISABLED:
+            ibex_irq_lower(&s->passthrough_en);
+            break;
+        case CTRL_MODE_PASSTHROUGH:
+            ibex_irq_raise(&s->passthrough_en);
+            break;
+        }
+        break;
+    case R_CFG:
+        val32 &= CFG_MASK;
+        s->spi_regs[reg] = val32;
+        break;
+    case R_INTERCEPT_EN:
+        val32 &= INTERCEPT_EN_MASK;
+        s->spi_regs[reg] = val32;
+        break;
+    case R_ADDR_MODE:
+        s->spi_regs[reg] &= ~R_ADDR_MODE_ADDR_4B_EN_MASK;
+        s->spi_regs[reg] |= val32 & R_ADDR_MODE_ADDR_4B_EN_MASK; /* RW */
+        break;
+    case R_FLASH_STATUS:
+        s->spi_regs[reg] &= val32 & FLASH_STATUS_RW0C_MASK; /* RW0C */
+        s->spi_regs[reg] &= ~FLASH_STATUS_RW_MASK;
+        s->spi_regs[reg] |= val32 & FLASH_STATUS_RW_MASK; /* RW */
+        break;
+    case R_JEDEC_CC:
+        val32 &= JEDEC_CC_MASK;
+        s->spi_regs[reg] = val32;
+        break;
+    case R_JEDEC_ID:
+        val32 &= JEDEC_ID_MASK;
+        s->spi_regs[reg] = val32;
+        break;
+    case R_READ_THRESHOLD:
+        val32 &= R_READ_THRESHOLD_THRESHOLD_MASK;
+        s->spi_regs[reg] = val32;
+        break;
+    case R_MAILBOX_ADDR:
+    case R_CMD_FILTER_0:
+    case R_CMD_FILTER_1:
+    case R_CMD_FILTER_2:
+    case R_CMD_FILTER_3:
+    case R_CMD_FILTER_4:
+    case R_CMD_FILTER_5:
+    case R_CMD_FILTER_6:
+    case R_CMD_FILTER_7:
+    case R_ADDR_SWAP_MASK:
+    case R_ADDR_SWAP_DATA:
+    case R_PAYLOAD_SWAP_MASK:
+    case R_PAYLOAD_SWAP_DATA:
+        s->spi_regs[reg] = val32;
+        break;
+    case R_CMD_INFO_0:
+    case R_CMD_INFO_1:
+    case R_CMD_INFO_2:
+    case R_CMD_INFO_3:
+    case R_CMD_INFO_4:
+    case R_CMD_INFO_5:
+    case R_CMD_INFO_6:
+    case R_CMD_INFO_7:
+    case R_CMD_INFO_8:
+    case R_CMD_INFO_9:
+    case R_CMD_INFO_10:
+    case R_CMD_INFO_11:
+    case R_CMD_INFO_12:
+    case R_CMD_INFO_13:
+    case R_CMD_INFO_14:
+    case R_CMD_INFO_15:
+    case R_CMD_INFO_16:
+    case R_CMD_INFO_17:
+    case R_CMD_INFO_18:
+    case R_CMD_INFO_19:
+    case R_CMD_INFO_20:
+    case R_CMD_INFO_21:
+    case R_CMD_INFO_22:
+    case R_CMD_INFO_23:
+        val32 &= CMD_INFO_GEN_MASK;
+        s->spi_regs[reg] = val32;
+        break;
+    case R_CMD_INFO_EN4B:
+    case R_CMD_INFO_EX4B:
+    case R_CMD_INFO_WREN:
+    case R_CMD_INFO_WRDI:
+        val32 &= CMD_INFO_SPC_MASK;
+        s->spi_regs[reg] = val32;
+        break;
+    case R_LAST_READ_ADDR:
+    case R_STATUS:
+    case R_UPLOAD_STATUS:
+    case R_UPLOAD_STATUS2:
+    case R_UPLOAD_CMDFIFO:
+    case R_UPLOAD_ADDRFIFO:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, SPI_REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static uint64_t
+ot_spi_device_tpm_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtSPIDeviceState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_TPM_CMD_ADDR:
+        s->tpm_regs[R_TPM_STATUS] &= ~R_TPM_STATUS_CMDADDR_NOTEMPTY_MASK;
+        s->spi_regs[R_INTR_STATE] &= ~INTR_TPM_HEADER_NOT_EMPTY_MASK;
+        ot_spi_device_update_irqs(s);
+        /* fall through*/
+    case R_TPM_STATUS:
+    case R_TPM_CFG:
+    case R_TPM_CAP:
+    case R_TPM_ACCESS_0:
+    case R_TPM_ACCESS_1:
+    case R_TPM_STS:
+    case R_TPM_INTF_CAPABILITY:
+    case R_TPM_INT_ENABLE:
+    case R_TPM_INT_VECTOR:
+    case R_TPM_INT_STATUS:
+    case R_TPM_DID_VID:
+    case R_TPM_RID:
+        val32 = s->tpm_regs[reg];
+        break;
+    case R_TPM_READ_FIFO:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, TPM_REG_NAME(reg));
+        val32 = 0u;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0u;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_spi_device_io_tpm_read_out(s->ot_id, (uint32_t)addr,
+                                        TPM_REG_NAME(reg), val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_spi_device_tpm_regs_write(void *opaque, hwaddr addr,
+                                         uint64_t val64, unsigned size)
+{
+    OtSPIDeviceState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_spi_device_io_tpm_write_in(s->ot_id, (uint32_t)addr,
+                                        TPM_REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_TPM_CFG:
+    case R_TPM_ACCESS_0:
+    case R_TPM_ACCESS_1:
+    case R_TPM_STS:
+    case R_TPM_INTF_CAPABILITY:
+    case R_TPM_INT_ENABLE:
+    case R_TPM_INT_VECTOR:
+    case R_TPM_INT_STATUS:
+    case R_TPM_DID_VID:
+    case R_TPM_RID:
+        s->tpm_regs[reg] = val32;
+        break;
+    case R_TPM_STATUS:
+        val32 &= R_TPM_STATUS_WRFIFO_PENDING_MASK;
+        s->tpm_regs[reg] &=
+            val32 | ~R_TPM_STATUS_WRFIFO_PENDING_MASK; /* RW0C */
+        break;
+    case R_TPM_READ_FIFO:
+        fifo8_push(&s->tpm.rdfifo, (uint8_t)(val32 >> 0) & 0xffu);
+        fifo8_push(&s->tpm.rdfifo, (uint8_t)(val32 >> 8u) & 0xffu);
+        fifo8_push(&s->tpm.rdfifo, (uint8_t)(val32 >> 16u) & 0xffu);
+        fifo8_push(&s->tpm.rdfifo, (uint8_t)(val32 >> 24u) & 0xffu);
+        break;
+    case R_TPM_CAP:
+    case R_TPM_CMD_ADDR:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, TPM_REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static MemTxResult ot_spi_device_buf_read_with_attrs(
+    void *opaque, hwaddr addr, uint64_t *val64, unsigned size, MemTxAttrs attrs)
+{
+    OtSPIDeviceState *s = opaque;
+    (void)attrs;
+    uint32_t val32;
+
+    hwaddr last = addr + (hwaddr)(size - 1u);
+
+    if (addr < SPI_SRAM_INGRESS_OFFSET) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: cannot read egress buffer 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        return MEMTX_DECODE_ERROR;
+    }
+
+    if ((addr >= SPI_SRAM_PAYLOAD_OFFSET &&
+         last < (SPI_SRAM_PAYLOAD_OFFSET + SPI_SRAM_PAYLOAD_SIZE)) ||
+        (addr >= SPI_SRAM_TPM_WRITE_OFFSET &&
+         last < (SPI_SRAM_TPM_WRITE_OFFSET + SPI_SRAM_TPM_WRITE_SIZE))) {
+        /* flash payload and tpm write buffers */
+        val32 = s->sram[addr >> 2u];
+    } else if (addr >= SPI_SRAM_CMD_OFFSET &&
+               last < (SPI_SRAM_CMD_OFFSET + SPI_SRAM_CMD_SIZE)) {
+        /* flash command FIFO */
+        val32 = s->flash.cmd_fifo.data[addr >> 2u];
+    } else if (addr >= SPI_SRAM_ADDR_OFFSET &&
+               last < (SPI_SRAM_ADDR_OFFSET + SPI_SRAM_ADDR_SIZE)) {
+        /* flash address FIFO */
+        val32 = s->flash.address_fifo.data[addr >> 2u];
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Invalid ingress buffer access to "
+                      "0x%03x-0x%03x\n",
+                      __func__, s->ot_id, (uint32_t)addr, (uint32_t)last);
+        val32 = 0;
+    }
+
+    /* TODO: check which buffers can only be accessed as 32-bit locations */
+
+    unsigned addr_offset = (addr & 3u);
+    g_assert((addr_offset + size) <= 4u);
+    val32 >>= addr_offset << 3u;
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_spi_device_io_buf_read_out(s->ot_id, (uint32_t)addr, size, val32,
+                                        pc);
+
+    *val64 = (uint64_t)val32;
+
+    return MEMTX_OK;
+}
+
+static MemTxResult ot_spi_device_buf_write_with_attrs(
+    void *opaque, hwaddr addr, uint64_t val64, unsigned size, MemTxAttrs attrs)
+{
+    OtSPIDeviceState *s = opaque;
+    (void)attrs;
+
+    uint32_t val32 = (uint32_t)val64;
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_spi_device_io_buf_write_in(s->ot_id, (uint32_t)addr, size, val32,
+                                        pc);
+
+    hwaddr last = addr + (hwaddr)(size - 1u);
+
+    if (last >= SPI_SRAM_INGRESS_OFFSET) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: cannot write ingress buffer 0x%03x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        return MEMTX_DECODE_ERROR;
+    }
+    s->sram[addr >> 2u] = val32;
+
+    return MEMTX_OK;
+}
+
+static void ot_spi_device_tpm_init_buffers(OtSPIDeviceState *s)
+{
+    s->tpm.write_pos = 0u;
+    s->tpm.len = SPI_SRAM_TPM_WRITE_SIZE;
+}
+
+static void ot_spi_device_chr_handle_header(OtSPIDeviceState *s)
+{
+    SpiDeviceBus *bus = &s->bus;
+
+    uint32_t size = 0u;
+    const uint8_t *hdr =
+        fifo8_pop_bufptr(&bus->chr_fifo, SPI_BUS_HEADER_SIZE, &size);
+
+    if (size != SPI_BUS_HEADER_SIZE) {
+        trace_ot_spi_device_chr_error(s->ot_id, "invalid header size");
+        s->spi_regs[R_STATUS] |= R_STATUS_CSB_MASK;
+        BUS_CHANGE_STATE(s, ERROR);
+        return;
+    }
+
+    if (hdr[0] != '/' || hdr[1u] != 'C' || hdr[2u] != 'S' ||
+        hdr[3u] != SPI_BUS_PROTO_VER) {
+        trace_ot_spi_device_chr_error(s->ot_id, "invalid header");
+        s->spi_regs[R_STATUS] |= R_STATUS_CSB_MASK;
+        BUS_CHANGE_STATE(s, ERROR);
+        return;
+    }
+
+    unsigned word = ldl_le_p(&hdr[4u]);
+    bus->byte_count = word >> 16u;
+    uint8_t mode = word & 0xfu;
+    bus->release = !((word >> 7) & 0x1);
+
+    bus->rev_rx = (bool)(mode & R_CFG_RX_ORDER_MASK);
+    bus->rev_tx = (bool)(mode & R_CFG_TX_ORDER_MASK);
+    /* if phase or polarity is not mode 0, corrupt data */
+    uint8_t comm = mode ^ (uint8_t)s->spi_regs[R_CFG];
+    bus->mode = (comm != 0) ? 0xFF : 0x00;
+
+    trace_ot_spi_device_chr_handle_packet(s->ot_id, bus->byte_count,
+                                          bus->release, bus->rev_rx ? 'l' : 'm',
+                                          bus->rev_tx ? 'l' : 'm',
+                                          bus->mode ? "mismatch" : "ok");
+
+    if (!bus->byte_count) {
+        /* no payload, stay in IDLE (handle_header is only called from IDLE) */
+        return;
+    }
+
+    /* @todo: also update the TPM CSB value when used in the protocol */
+    s->spi_regs[R_STATUS] &= ~R_STATUS_CSB_MASK;
+
+    /* discard the packet if we're within a failed transaction */
+    if (bus->failed_transaction) {
+        BUS_CHANGE_STATE(s, DISCARD);
+        return;
+    }
+
+    /* @todo: Check that the tpm chip-select was assigned.*/
+    if (ot_spi_device_is_tpm_enabled(s)) {
+        ot_spi_device_tpm_init_buffers(s);
+        BUS_CHANGE_STATE(s, TPM);
+        return;
+    }
+
+    switch (ot_spi_device_get_mode(s)) {
+    case CTRL_MODE_FLASH:
+    case CTRL_MODE_PASSTHROUGH:
+        BUS_CHANGE_STATE(s, FLASH);
+        break;
+    case CTRL_MODE_DISABLED:
+    case CTRL_MODE_INVALID:
+    default:
+        BUS_CHANGE_STATE(s, DISCARD);
+        break;
+    }
+}
+
+static void ot_spi_device_chr_send_discard(OtSPIDeviceState *s, unsigned count)
+{
+    const uint8_t buf[1u] = { SPI_DEFAULT_TX_RX_VALUE };
+
+    while (count--) {
+        if (qemu_chr_fe_backend_connected(&s->chr)) {
+            qemu_chr_fe_write(&s->chr, buf, (int)sizeof(buf));
+        }
+    }
+}
+
+static void ot_spi_device_chr_recv_discard(OtSPIDeviceState *s,
+                                           const uint8_t *buf, unsigned size)
+{
+    (void)buf;
+
+    ot_spi_device_chr_send_discard(s, size);
+    s->bus.byte_count -= size;
+}
+
+static void ot_spi_device_chr_recv_flash(OtSPIDeviceState *s,
+                                         const uint8_t *buf, unsigned size)
+{
+    SpiDeviceBus *bus = &s->bus;
+    while (size) {
+        uint8_t rx = *buf++ ^ bus->mode;
+        if (bus->rev_rx) {
+            rx = revbit8(rx);
+        }
+        uint8_t tx;
+        switch (ot_spi_device_get_mode(s)) {
+        case CTRL_MODE_FLASH:
+            tx = ot_spi_device_flash_transfer(s, rx);
+            break;
+        case CTRL_MODE_PASSTHROUGH:
+            tx = ot_spi_device_flash_transfer_passthrough(s, rx);
+            break;
+        default:
+            g_assert_not_reached();
+        }
+        tx ^= bus->mode;
+        if (bus->rev_tx) {
+            tx = revbit8(tx);
+        }
+        if (qemu_chr_fe_backend_connected(&s->chr)) {
+            qemu_chr_fe_write(&s->chr, &tx, (int)sizeof(tx));
+        }
+        bus->byte_count--;
+        size--;
+    }
+}
+
+static bool
+ot_spi_device_tpm_get_hw_register(OtSPIDeviceState *s, uint32_t *reg_val)
+{
+    /* clang-format off */
+    static const SpiTpmHwAddrMap TPM_HW_ADDR[] = {
+      /*{ register_addr, tpm_register_offset, size }*/
+        { 0x000u,        R_TPM_ACCESS_0,        4u },
+        { 0x004u,        R_TPM_ACCESS_1,        4u },
+        { 0x008u,        R_TPM_INT_ENABLE,      4u },
+        { 0x00Cu,        R_TPM_INT_VECTOR,      1u },
+        { 0x010u,        R_TPM_INT_STATUS,      4u },
+        { 0x014u,        R_TPM_INTF_CAPABILITY, 4u },
+        { 0x018u,        R_TPM_STS,             4u },
+        { 0x028u,        0u,                    0u }, /* Hash Start */
+        { 0xF00u,        R_TPM_DID_VID,         4u },
+        { 0xF04u,        R_TPM_RID,             4u },
+    };
+    /* clang-format on */
+
+    if (reg_val) {
+        *reg_val = UINT32_MAX;
+    }
+    for (uint32_t idx = 0u; idx < ARRAY_SIZE(TPM_HW_ADDR); idx++) {
+        if (TPM_HW_ADDR[idx].addr == (s->tpm.reg & ~0x3u)) {
+            unsigned nbytes = TPM_HW_ADDR[idx].nbytes;
+            g_assert(nbytes <= sizeof(uint32_t));
+            if (reg_val && nbytes != 0u) {
+                uint32_t mask =
+                    UINT32_MAX >> (8u * (sizeof(uint32_t) - nbytes));
+                *reg_val &= ~mask;
+                *reg_val |= s->tpm_regs[TPM_HW_ADDR[idx].offset];
+            }
+            return true;
+        }
+    }
+    return false;
+}
+
+static void ot_spi_device_tpm_idle_state(OtSPIDeviceState *s,
+                                         const uint8_t *buf, unsigned size)
+{
+    g_assert(size == 1u);
+    SpiDeviceTpm *tpm = &s->tpm;
+    fifo8_reset(&tpm->rdfifo);
+    tpm->opcode = buf[0u];
+    tpm->read = tpm->opcode >> TPM_OPCODE_READ_BIT;
+    tpm->transfer_size = (tpm->opcode & TPM_OPCODE_SIZE_MASK) + 1u;
+    tpm->state = SPI_TPM_ADDR;
+    tpm->can_receive = 3u;
+}
+
+static void ot_spi_device_tpm_addr_state(OtSPIDeviceState *s,
+                                         const uint8_t *buf, unsigned size)
+{
+    g_assert(size == 3u);
+    SpiDeviceTpm *tpm = &s->tpm;
+    tpm->reg = buf[1u] << 8u | buf[2u];
+    tpm->locality = tpm->reg >> 12u;
+    s->tpm_regs[R_TPM_CMD_ADDR] =
+        (tpm->opcode << R_TPM_CMD_ADDR_CMD_SHIFT) | tpm->reg;
+
+    /* When read, we immediately signal the software to fill the FIFO */
+    if (tpm->read) {
+        s->tpm_regs[R_TPM_STATUS] |= R_TPM_STATUS_CMDADDR_NOTEMPTY_MASK;
+        s->spi_regs[R_INTR_STATE] |= INTR_TPM_HEADER_NOT_EMPTY_MASK;
+        ot_spi_device_update_irqs(s);
+    }
+
+    tpm->can_receive = 1u;
+    tpm->should_sw_handle = true;
+    if (!ot_spi_device_is_tpm_mode_crb(s) &&
+        !ot_spi_device_tpm_disable_hw_regs(s) && buf[0u] == TPM_ADDR_HEADER) {
+        bool is_hw_register = ot_spi_device_tpm_get_hw_register(s, NULL);
+        tpm->should_sw_handle = !is_hw_register;
+    }
+
+    tpm->state = tpm->should_sw_handle ? SPI_TPM_WAIT : SPI_TPM_START_BYTE;
+}
+
+static void ot_spi_device_tpm_write_state(OtSPIDeviceState *s,
+                                          const uint8_t *buf, unsigned size)
+{
+    SpiDeviceTpm *tpm = &s->tpm;
+    memcpy(&tpm->write_buffer[tpm->write_pos], buf, size);
+    tpm->write_pos += size;
+    tpm->state =
+        tpm->write_pos >= tpm->transfer_size ? SPI_TPM_IDLE : tpm->state;
+
+    s->tpm_regs[R_TPM_STATUS] |= R_TPM_STATUS_CMDADDR_NOTEMPTY_MASK;
+    s->spi_regs[R_INTR_STATE] |= INTR_TPM_HEADER_NOT_EMPTY_MASK;
+    ot_spi_device_update_irqs(s);
+}
+
+static void ot_spi_device_tpm_read_state(OtSPIDeviceState *s, unsigned size,
+                                         uint8_t *tx_buf)
+{
+    SpiDeviceTpm *tpm = &s->tpm;
+    g_assert(fifo8_pop_buf(&tpm->rdfifo, tx_buf, size) == size);
+    tpm->state = SPI_TPM_IDLE;
+}
+
+static void ot_spi_device_tpm_read_hw_state(OtSPIDeviceState *s, unsigned size,
+                                            uint8_t *tx_buf)
+{
+    SpiDeviceTpm *tpm = &s->tpm;
+    uint32_t val32;
+    ot_spi_device_tpm_get_hw_register(s, &val32);
+    g_assert(size == sizeof(uint32_t));
+    stl_le_p(tx_buf, val32);
+    tpm->state = SPI_TPM_IDLE;
+}
+
+static void ot_spi_device_tpm_wait_state(OtSPIDeviceState *s)
+{
+    SpiDeviceTpm *tpm = &s->tpm;
+    if (!tpm->read || (fifo8_num_used(&tpm->rdfifo) >= tpm->transfer_size)) {
+        tpm->state = SPI_TPM_START_BYTE;
+    }
+}
+
+static void ot_spi_device_tpm_start_byte_state(OtSPIDeviceState *s,
+                                               unsigned size, uint8_t *tx_buf)
+{
+    SpiDeviceTpm *tpm = &s->tpm;
+    tpm->state = SPI_TPM_WRITE;
+    if (tpm->read) {
+        tpm->state = tpm->should_sw_handle ? SPI_TPM_READ : SPI_TPM_READ_HW_REG;
+    }
+    tx_buf[size - 1u] = TPM_READY;
+    tpm->can_receive = tpm->transfer_size;
+}
+
+static void ot_spi_device_tpm_state_machine(OtSPIDeviceState *s,
+                                            const uint8_t *buf, unsigned size)
+{
+    g_assert(size <= SPI_TPM_READ_FIFO_SIZE_BYTES);
+    uint8_t tx_buf[SPI_TPM_READ_FIFO_SIZE_BYTES] = { 0u };
+
+    SpiDeviceTpm *tpm = &s->tpm;
+    switch (tpm->state) {
+    case SPI_TPM_IDLE:
+        ot_spi_device_tpm_idle_state(s, buf, size);
+        break;
+    case SPI_TPM_ADDR:
+        ot_spi_device_tpm_addr_state(s, buf, size);
+        break;
+    case SPI_TPM_WRITE:
+        ot_spi_device_tpm_write_state(s, buf, size);
+        break;
+    case SPI_TPM_READ:
+        ot_spi_device_tpm_read_state(s, size, tx_buf);
+        break;
+    case SPI_TPM_READ_HW_REG:
+        ot_spi_device_tpm_read_hw_state(s, size, tx_buf);
+        break;
+    case SPI_TPM_WAIT:
+        ot_spi_device_tpm_wait_state(s);
+        break;
+    case SPI_TPM_START_BYTE:
+        ot_spi_device_tpm_start_byte_state(s, size, tx_buf);
+        break;
+    case SPI_TPM_END:
+        /* Wait for the cs de-assertion.*/
+        s->bus.byte_count = 0u;
+        tpm->state = SPI_TPM_IDLE;
+        return;
+    default:
+        break;
+    };
+    if (qemu_chr_fe_backend_connected(&s->chr)) {
+        qemu_chr_fe_write(&s->chr, tx_buf, (int)size);
+    }
+    s->bus.byte_count -= size;
+    tpm->can_receive = tpm->state == SPI_TPM_IDLE ? 1u : tpm->can_receive;
+}
+
+static int ot_spi_device_chr_can_receive(void *opaque)
+{
+    OtSPIDeviceState *s = opaque;
+    SpiDeviceBus *bus = &s->bus;
+    unsigned length = 0u;
+
+    switch (bus->state) {
+    case SPI_BUS_IDLE:
+        length = fifo8_num_free(&bus->chr_fifo);
+        break;
+    case SPI_BUS_FLASH:
+        length = timer_pending(s->flash.irq_timer) ? 0 : 1u;
+        break;
+    case SPI_BUS_TPM:
+        length = s->tpm.can_receive;
+        break;
+    case SPI_BUS_DISCARD:
+        length = 1u;
+        break;
+    case SPI_BUS_ERROR:
+        length = 0;
+        break;
+    default:
+        error_setg(&error_fatal, "unexpected state %d\n", bus->state);
+        /* linter does not know error_setg never returns */
+        g_assert_not_reached();
+    }
+
+    return (int)length;
+}
+
+static void ot_spi_device_chr_receive(void *opaque, const uint8_t *buf,
+                                      int size)
+{
+    OtSPIDeviceState *s = opaque;
+    SpiDeviceBus *bus = &s->bus;
+
+    switch (bus->state) {
+    case SPI_BUS_IDLE:
+        g_assert(size <= fifo8_num_free(&bus->chr_fifo));
+        while (size--) {
+            fifo8_push(&bus->chr_fifo, *buf++);
+        }
+        if (fifo8_is_full(&bus->chr_fifo)) {
+            /* a full header has been received, it can be decoded */
+            ot_spi_device_chr_handle_header(s);
+        }
+        break;
+    case SPI_BUS_FLASH:
+        ot_spi_device_chr_recv_flash(s, buf, (unsigned)size);
+        break;
+    case SPI_BUS_TPM:
+        ot_spi_device_tpm_state_machine(s, buf, (unsigned)size);
+        break;
+    case SPI_BUS_DISCARD:
+    case SPI_BUS_ERROR:
+        ot_spi_device_chr_recv_discard(s, buf, (unsigned)size);
+        /* we need to discard the other packets in this transaction */
+        bus->failed_transaction = true;
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+
+    if (!bus->byte_count && bus->state != SPI_BUS_ERROR) {
+        if (bus->release) {
+            ot_spi_device_release(s);
+        } else {
+            BUS_CHANGE_STATE(s, IDLE);
+        }
+    }
+}
+
+static void ot_spi_device_chr_event_hander(void *opaque, QEMUChrEvent event)
+{
+    OtSPIDeviceState *s = opaque;
+
+    if (event == CHR_EVENT_OPENED) {
+        if (object_dynamic_cast(OBJECT(s->chr.chr), TYPE_CHARDEV_SERIAL)) {
+            ot_common_ignore_chr_status_lines(&s->chr);
+        }
+
+        if (!qemu_chr_fe_backend_connected(&s->chr)) {
+            return;
+        }
+
+        ot_spi_device_release(s);
+    }
+
+    if (event == CHR_EVENT_CLOSED) {
+        ot_spi_device_release(s);
+    }
+}
+
+static gboolean
+ot_spi_device_chr_watch_cb(void *do_not_use, GIOCondition cond, void *opaque)
+{
+    OtSPIDeviceState *s = opaque;
+    (void)do_not_use;
+    (void)cond;
+
+    s->watch_tag = 0;
+
+    return FALSE;
+}
+
+static int ot_spi_device_chr_be_change(void *opaque)
+{
+    OtSPIDeviceState *s = opaque;
+    SpiDeviceBus *bus = &s->bus;
+
+    qemu_chr_fe_set_handlers(&s->chr, &ot_spi_device_chr_can_receive,
+                             &ot_spi_device_chr_receive,
+                             &ot_spi_device_chr_event_hander,
+                             &ot_spi_device_chr_be_change, s, NULL, true);
+
+    fifo8_reset(&bus->chr_fifo);
+
+    ot_spi_device_release(s);
+
+    if (s->watch_tag > 0) {
+        g_source_remove(s->watch_tag);
+        /* NOLINTNEXTLINE(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+                                             &ot_spi_device_chr_watch_cb, s);
+    }
+
+    return 0;
+}
+
+static const Property ot_spi_device_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtSPIDeviceState, ot_id),
+    DEFINE_PROP_CHR("chardev", OtSPIDeviceState, chr),
+    DEFINE_PROP_LINK("spi-host", OtSPIDeviceState, spi_host, TYPE_OT_SPI_HOST,
+                     OtSPIHostState *),
+};
+
+static const MemoryRegionOps ot_spi_device_spi_regs_ops = {
+    .read = &ot_spi_device_spi_regs_read,
+    .write = &ot_spi_device_spi_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_spi_device_tpm_regs_ops = {
+    .read = &ot_spi_device_tpm_regs_read,
+    .write = &ot_spi_device_tpm_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_spi_device_buf_ops = {
+    .read_with_attrs = &ot_spi_device_buf_read_with_attrs,
+    .write_with_attrs = &ot_spi_device_buf_write_with_attrs,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 1u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_spi_device_reset_enter(Object *obj, ResetType type)
+{
+    OtSPIDeviceClass *c = OT_SPI_DEVICE_GET_CLASS(obj);
+    OtSPIDeviceState *s = OT_SPI_DEVICE(obj);
+    SpiDeviceFlash *f = &s->flash;
+    SpiDeviceBus *bus = &s->bus;
+
+    trace_ot_spi_device_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    ot_spi_device_clear_modes(s);
+
+    memset(s->spi_regs, 0u, SPI_REGS_SIZE);
+    memset(s->tpm_regs, 0u, TPM_REGS_SIZE);
+
+    fifo8_reset(&bus->chr_fifo);
+    /* not sure if the following FIFOs should be reset on clear_modes instead */
+    ot_fifo32_reset(&f->cmd_fifo);
+    ot_fifo32_reset(&f->address_fifo);
+
+    ot_spi_device_release(s);
+    s->spi_regs[R_CONTROL] = 0x10u;
+    s->spi_regs[R_STATUS] = 0x60u;
+    s->spi_regs[R_JEDEC_CC] = 0x7fu;
+    for (unsigned ix = 0u; ix < PARAM_NUM_CMD_INFO; ix++) {
+        s->spi_regs[R_CMD_INFO_0 + ix] = 0x7000u;
+    }
+
+    memset(&f->cmd_params, 0u, sizeof(OtSpiCommandParams));
+
+    s->tpm_regs[R_TPM_CAP] = 0x660100u;
+
+    ibex_irq_lower(&s->passthrough_en);
+    ibex_irq_raise(&s->passthrough_cs);
+
+    ot_spi_device_update_irqs(s);
+    ot_spi_device_update_alerts(s);
+}
+
+static void ot_spi_device_realize(DeviceState *dev, Error **errp)
+{
+    OtSPIDeviceState *s = OT_SPI_DEVICE(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+
+    g_assert(s->spi_host);
+
+    qemu_chr_fe_set_handlers(&s->chr, &ot_spi_device_chr_can_receive,
+                             &ot_spi_device_chr_receive,
+                             &ot_spi_device_chr_event_hander,
+                             &ot_spi_device_chr_be_change, s, NULL, true);
+}
+
+static void ot_spi_device_init(Object *obj)
+{
+    OtSPIDeviceState *s = OT_SPI_DEVICE(obj);
+    SpiDeviceFlash *f = &s->flash;
+    SpiDeviceBus *bus = &s->bus;
+
+    memory_region_init(&s->mmio.main, obj, TYPE_OT_SPI_DEVICE ".mmio",
+                       SPI_DEVICE_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio.main);
+    memory_region_init_io(&s->mmio.spi, obj, &ot_spi_device_spi_regs_ops, s,
+                          TYPE_OT_SPI_DEVICE ".spi-regs", SPI_REGS_SIZE);
+    memory_region_add_subregion(&s->mmio.main, SPI_DEVICE_SPI_REGS_OFFSET,
+                                &s->mmio.spi);
+    memory_region_init_io(&s->mmio.tpm, obj, &ot_spi_device_tpm_regs_ops, s,
+                          TYPE_OT_SPI_DEVICE ".tpm-regs", TPM_REGS_SIZE);
+    memory_region_add_subregion(&s->mmio.main, SPI_DEVICE_TPM_REGS_OFFSET,
+                                &s->mmio.tpm);
+    memory_region_init_io(&s->mmio.buf, obj, &ot_spi_device_buf_ops, s,
+                          TYPE_OT_SPI_DEVICE ".buf", SRAM_SIZE);
+    memory_region_add_subregion(&s->mmio.main, SPI_DEVICE_SRAM_OFFSET,
+                                &s->mmio.buf);
+
+    s->spi_regs = g_new0(uint32_t, SPI_REGS_COUNT);
+    s->tpm_regs = g_new0(uint32_t, TPM_REGS_COUNT);
+    s->sram = g_new(uint32_t, SRAM_SIZE / sizeof(uint32_t));
+
+    fifo8_create(&bus->chr_fifo, SPI_BUS_HEADER_SIZE);
+    ot_fifo32_create(&f->cmd_fifo, SPI_SRAM_CMD_SIZE / sizeof(uint32_t));
+    fifo8_create(&s->tpm.rdfifo, SPI_TPM_READ_FIFO_SIZE_BYTES);
+    ot_fifo32_create(&f->address_fifo, SPI_SRAM_ADDR_SIZE / sizeof(uint32_t));
+    f->buffer =
+        (uint8_t *)g_new0(uint32_t, SPI_FLASH_BUFFER_SIZE / sizeof(uint32_t));
+
+    for (unsigned ix = 0; ix < PARAM_NUM_IRQS; ix++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[ix]);
+    }
+    for (unsigned ix = 0; ix < PARAM_NUM_ALERTS; ix++) {
+        ibex_qdev_init_irq(obj, &s->alerts[ix], OT_DEVICE_ALERT);
+    }
+
+    /* Passthrough enable is active high, CS is active low */
+    ibex_qdev_init_irq_default(OBJECT(s), &s->passthrough_en,
+                               OT_SPI_DEVICE_PASSTHROUGH_EN, 0);
+    ibex_qdev_init_irq_default(OBJECT(s), &s->passthrough_cs,
+                               OT_SPI_DEVICE_PASSTHROUGH_CS, 1);
+
+    /*
+     * This timer is used to hand over to the vCPU whenever a READBUF_* irq is
+     * raised, otherwide the vCPU would not be able to get notified that a
+     * buffer refill is required by the HW. In other words, this is poor man's
+     * co-operative multitasking between the vCPU and the IO thread
+     */
+    f->irq_timer =
+        timer_new_ns(OT_VIRTUAL_CLOCK, &ot_spi_device_flash_resume_read, s);
+}
+
+static void ot_spi_device_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_spi_device_realize;
+    device_class_set_props(dc, ot_spi_device_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtSPIDeviceClass *sc = OT_SPI_DEVICE_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_spi_device_reset_enter, NULL,
+                                       NULL, &sc->parent_phases);
+}
+
+static const TypeInfo ot_spi_device_info = {
+    .name = TYPE_OT_SPI_DEVICE,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtSPIDeviceState),
+    .instance_init = &ot_spi_device_init,
+    .class_size = sizeof(OtSPIDeviceClass),
+    .class_init = &ot_spi_device_class_init,
+};
+
+static void ot_spi_device_register_types(void)
+{
+    type_register_static(&ot_spi_device_info);
+}
+
+type_init(ot_spi_device_register_types);
diff --git a/hw/opentitan/ot_spi_host.c b/hw/opentitan/ot_spi_host.c
new file mode 100644
index 0000000000000..6a1391d1db957
--- /dev/null
+++ b/hw/opentitan/ot_spi_host.c
@@ -0,0 +1,1591 @@
+/*
+ * QEMU OpenTitan SPI Host controller
+ *
+ * Copyright (C) 2022 Western Digital
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Wilfred Mallawa <wilfred.mallawa@wdc.com>
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Known limitations:
+ *  - BigEndian devices are not supported
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "qemu/fifo8.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_spi_host.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/ssi/ssi.h"
+#include "trace.h"
+
+/* ------------------------------------------------------------------------ */
+/* Configuration */
+/* ------------------------------------------------------------------------ */
+
+/* undef to get all the repeated, identical status query traces */
+#define DISCARD_REPEATED_STATUS_TRACES
+
+/* fake delayed completion of HW commands */
+#define FSM_COMPLETION_DELAY_NS 100U /* 100 ns (~ BH) */
+/* initial FSM start up delay */
+#define FSM_START_DELAY_NS 20000U /* 20 uS */
+
+#define TXFIFO_LEN  288U /* bytes */
+#define RXFIFO_LEN  256U /* bytes */
+#define CMDFIFO_LEN 4U /* slots */
+
+/* ------------------------------------------------------------------------ */
+/* Register definitions */
+/* ------------------------------------------------------------------------ */
+
+/* clang-format off */
+REG32(INTR_STATE, 0x00u)
+    SHARED_FIELD(INTR_ERROR, 0u, 1u)
+    SHARED_FIELD(INTR_SPI_EVENT, 1u, 1u)
+REG32(INTR_ENABLE, 0x04u)
+REG32(INTR_TEST, 0x08u)
+REG32(ALERT_TEST, 0x0cu)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(CONTROL, 0x10u)
+    FIELD(CONTROL, RX_WATERMARK, 0u, 8u)
+    FIELD(CONTROL, TX_WATERMARK, 8u, 8u)
+    FIELD(CONTROL, OUTPUT_EN, 29u, 1u)
+    FIELD(CONTROL, SW_RST, 30u, 1u)
+    FIELD(CONTROL, SPIEN, 31u, 1u)
+REG32(STATUS, 0x14u)
+    FIELD(STATUS, TXQD, 0u, 8u)
+    FIELD(STATUS, RXQD, 8u, 8u)
+    FIELD(STATUS, CMDQD, 16u, 4u)
+    FIELD(STATUS, RXWM, 20u, 1u)
+    FIELD(STATUS, BYTEORDER, 22u, 1u)
+    FIELD(STATUS, RXSTALL, 23u, 1u)
+    FIELD(STATUS, RXEMPTY, 24u, 1u)
+    FIELD(STATUS, RXFULL, 25u, 1u)
+    FIELD(STATUS, TXWM, 26u, 1u)
+    FIELD(STATUS, TXSTALL, 27u, 1u)
+    FIELD(STATUS, TXEMPTY, 28u, 1u)
+    FIELD(STATUS, TXFULL, 29u, 1u)
+    FIELD(STATUS, ACTIVE, 30u, 1u)
+    FIELD(STATUS, READY, 31u, 1u)
+REG32(CONFIGOPTS, 0x18u)
+    FIELD(CONFIGOPTS, CLKDIV, 0u, 16u)
+    FIELD(CONFIGOPTS, CSNIDLE, 16u, 4u)
+    FIELD(CONFIGOPTS, CSNTRAIL, 20u, 4u)
+    FIELD(CONFIGOPTS, CSNLEAD, 24u, 4u)
+    FIELD(CONFIGOPTS, FULLCYC, 29u, 1u)
+    FIELD(CONFIGOPTS, CPHA, 30u, 1u)
+    FIELD(CONFIGOPTS, CPOL, 31u, 1u)
+REG32(CSID, 0x1cu)
+    FIELD(CSID, CSID, 0u, 32u)
+REG32(COMMAND, 0x20u)
+/* v3 field definitions */
+    FIELD(COMMAND, CSAAT, 0u, 1u)
+    FIELD(COMMAND, SPEED, 1u, 2u)
+    FIELD(COMMAND, DIRECTION, 3u, 2u)
+    FIELD(COMMAND, LEN, 5u, 20u)
+/* v2 field definitions */
+    FIELD(COMMAND, V2_LEN, 0u, 9u)
+    FIELD(COMMAND, V2_CSAAT, 9u, 1u)
+    FIELD(COMMAND, V2_SPEED, 10u, 2u)
+    FIELD(COMMAND, V2_DIRECTION, 12u, 2u)
+REG32(RXDATA, 0x24u)
+REG32(TXDATA, 0x28u)
+REG32(ERROR_ENABLE, 0x2cu)
+    FIELD(ERROR_ENABLE, CMDBUSY, 0u, 1u)
+    FIELD(ERROR_ENABLE, OVERFLOW, 1u, 1u)
+    FIELD(ERROR_ENABLE, UNDERFLOW, 2u, 1u)
+    FIELD(ERROR_ENABLE, CMDINVAL, 3u, 1u)
+    FIELD(ERROR_ENABLE, CSIDINVAL, 4u, 1u)
+REG32(ERROR_STATUS, 0x30u)
+    FIELD(ERROR_STATUS, CMDBUSY, 0u, 1u)
+    FIELD(ERROR_STATUS, OVERFLOW, 1u, 1u)
+    FIELD(ERROR_STATUS, UNDERFLOW, 2u, 1u)
+    FIELD(ERROR_STATUS, CMDINVAL, 3u, 1u)
+    FIELD(ERROR_STATUS, CSIDINVAL, 4u, 1u)
+    FIELD(ERROR_STATUS, ACCESSINVAL, 5u, 1u)
+REG32(EVENT_ENABLE, 0x34u)
+    FIELD(EVENT_ENABLE, RXFULL, 0u, 1u)
+    FIELD(EVENT_ENABLE, TXEMPTY, 1u, 1u)
+    FIELD(EVENT_ENABLE, RXWM, 2u, 1u)
+    FIELD(EVENT_ENABLE, TXWM, 3u, 1u)
+    FIELD(EVENT_ENABLE, READY, 4u, 1u)
+    FIELD(EVENT_ENABLE, IDLE, 5u, 1u)
+
+#define INTR_MASK \
+    (INTR_ERROR_MASK | INTR_SPI_EVENT_MASK)
+
+#define R_CONTROL_MASK \
+    (R_CONTROL_RX_WATERMARK_MASK | \
+     R_CONTROL_TX_WATERMARK_MASK | \
+     R_CONTROL_OUTPUT_EN_MASK    | \
+     R_CONTROL_SW_RST_MASK       | \
+     R_CONTROL_SPIEN_MASK)
+
+#define R_COMMAND_MASK \
+    (R_COMMAND_LEN_MASK       | \
+     R_COMMAND_CSAAT_MASK     | \
+     R_COMMAND_SPEED_MASK     | \
+     R_COMMAND_DIRECTION_MASK)
+
+#define R_ERROR_ENABLE_MASK \
+    (R_ERROR_ENABLE_CMDBUSY_MASK   | \
+     R_ERROR_ENABLE_OVERFLOW_MASK  | \
+     R_ERROR_ENABLE_UNDERFLOW_MASK | \
+     R_ERROR_ENABLE_CMDINVAL_MASK  | \
+     R_ERROR_ENABLE_CSIDINVAL_MASK)
+
+#define R_ERROR_STATUS_MASK \
+    (R_ERROR_STATUS_CMDBUSY_MASK   | \
+     R_ERROR_STATUS_OVERFLOW_MASK  | \
+     R_ERROR_STATUS_UNDERFLOW_MASK | \
+     R_ERROR_STATUS_CMDINVAL_MASK  | \
+     R_ERROR_STATUS_CSIDINVAL_MASK | \
+     R_ERROR_STATUS_ACCESSINVAL_MASK)
+
+#define R_CONFIGOPTS_MASK \
+    (R_CONFIGOPTS_CLKDIV_MASK   | \
+     R_CONFIGOPTS_CSNIDLE_MASK  | \
+     R_CONFIGOPTS_CSNTRAIL_MASK | \
+     R_CONFIGOPTS_CSNLEAD_MASK  | \
+     R_CONFIGOPTS_FULLCYC_MASK  | \
+     R_CONFIGOPTS_CPHA_MASK     | \
+     R_CONFIGOPTS_CPOL_MASK)
+
+#define R_EVENT_ENABLE_MASK \
+    (R_EVENT_ENABLE_RXFULL_MASK  | \
+     R_EVENT_ENABLE_TXEMPTY_MASK | \
+     R_EVENT_ENABLE_RXWM_MASK    | \
+     R_EVENT_ENABLE_TXWM_MASK    | \
+     R_EVENT_ENABLE_READY_MASK   | \
+     R_EVENT_ENABLE_IDLE_MASK)
+/* clang-format on */
+
+#define REG_UPDATE(_s_, _r_, _f_, _v_) \
+    do { \
+        (_s_)->regs[R_##_r_] = \
+            FIELD_DP32((_s_)->regs[R_##_r_], _r_, _f_, _v_); \
+    } while (0)
+
+#define REG_GET(_s_, _r_, _f_) FIELD_EX32((_s_)->regs[R_##_r_], _r_, _f_)
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+/* ------------------------------------------------------------------------ */
+/* Debug */
+/* ------------------------------------------------------------------------ */
+
+#define R_LAST_REG (R_EVENT_ENABLE)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CONTROL),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(CONFIGOPTS),
+    REG_NAME_ENTRY(CSID),
+    REG_NAME_ENTRY(COMMAND),
+    REG_NAME_ENTRY(RXDATA),
+    REG_NAME_ENTRY(TXDATA),
+    REG_NAME_ENTRY(ERROR_ENABLE),
+    REG_NAME_ENTRY(ERROR_STATUS),
+    REG_NAME_ENTRY(EVENT_ENABLE),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+static const char *F_COMMAND_DIRECTION[4u] = {
+    "DUMMY",
+    "RX",
+    "TX",
+    "TX|RX",
+};
+
+static const char *F_COMMAND_SPEED[4u] = {
+    "STD",
+    "DUAL",
+    "QUAD",
+    "ERROR",
+};
+
+#ifdef DISCARD_REPEATED_STATUS_TRACES
+typedef struct {
+    uint64_t pc;
+    uint32_t addr;
+    uint32_t value;
+    size_t count;
+} TraceCache;
+#endif /* DISCARD_REPEATED_STATUS_TRACES */
+
+#define SPI_DEFAULT_TX_RX_VALUE ((uint8_t)0xffu)
+
+/* ------------------------------------------------------------------------ */
+/* Types */
+/* ------------------------------------------------------------------------ */
+
+/** RX FIFO is byte-written and word-read */
+typedef Fifo8 RxFifo;
+
+/**
+ * TX FIFO needs 36 bits of storage (32-bit word + 4-bit tracking)
+ */
+typedef struct {
+    uint32_t bits; /* which bytes are meaningful in data (4 bits) */
+    uint32_t data; /* 1..4 bytes */
+} TxFifoSlot;
+
+static_assert(sizeof(TxFifoSlot) == sizeof(uint64_t),
+              "Invalid TxFifoSlot size");
+
+/**
+ * Command FIFO stores commands along with SPI device configuration.
+ */
+typedef struct {
+    uint32_t opts; /* configopts */
+    uint32_t command; /* command */
+    unsigned cs; /* csid */
+    unsigned id; /* for debug/tracking */
+} CmdFifoSlot;
+
+/** TX FIFO contains TX data and tracks meaningful bytes in TX words */
+typedef struct {
+    TxFifoSlot *data;
+    uint32_t capacity;
+    uint32_t head;
+    uint32_t num;
+} TxFifo;
+
+/** Command FIFO contains commands and SPI device configuration */
+typedef struct {
+    CmdFifoSlot *data;
+    uint32_t capacity;
+    uint32_t head;
+    uint32_t num;
+} CmdFifo;
+
+typedef struct {
+    bool transaction; /* SPI transation (CS is active) */
+    bool rx_stall; /* RX FIFO is full while processing a command */
+    bool tx_stall; /* TX FIFO is empty while processing a command */
+    bool output_en; /* SPI host output pins are enabled */
+} OtSPIHostFsm;
+
+typedef enum {
+    CMD_NONE, /* no command (unused slot) */
+    CMD_ONGOING, /* command is being executed, not yet completed */
+    CMD_EXECUTED, /* commmand has been executed, need to be discarded */
+} OtSPIHostCmdState;
+
+/**
+ * Current command, if any.
+ */
+typedef struct {
+    CmdFifoSlot cmd;
+    OtSPIHostCmdState state;
+    int64_t ts;
+    unsigned size;
+} OtSPIHostCmd;
+
+struct OtSPIHostState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+
+    IbexIRQ *cs_lines; /* CS output lines */
+    SSIBus *ssi; /* SPI bus */
+
+    uint32_t *regs; /* Registers (except. fifos) */
+
+    RxFifo *rx_fifo;
+    TxFifo *tx_fifo;
+    CmdFifo *cmd_fifo;
+
+    QEMUTimer *fsm_delay; /* Simulate delayed SPI transfer completion */
+
+    IbexIRQ irqs[2u]; /* System bus IRQs */
+    IbexIRQ alert; /* OpenTitan alert */
+    uint64_t total_transfer; /* Transfered bytes since reset */
+    unsigned last_command_id; /* Command tracker (for debug purpose) */
+    unsigned last_clkdiv; /* SPI clock tracker (for debug purpose) */
+    OtSPIHostCmd active; /* Command being executed, if any */
+
+    OtSPIHostFsm fsm;
+    bool on_reset;
+
+    /*
+     * Upstream SPI Device Passthrough enable and chip select. If we support
+     * passthrough mode (only one CS), The SPI Host CS is muxed with the
+     * passthrough CS, controlled by the passthrough enable signal.
+     */
+    bool passthrough_en; /* Upstream SPI Device Passthrough enable line */
+    bool passthrough_cs; /* Upstream SPI Device Chip Select */
+    bool host_cs0; /* Our Chip Select 0 */
+
+    /* Already emitted a guest error on first byte of invalid transfer */
+    bool transfer_error_emitted;
+
+    unsigned pclk; /* Current input clock */
+    const char *clock_src_name; /* IRQ name once connected */
+
+    /* properties */
+    char *ot_id;
+    char *clock_name; /* clock name */
+    DeviceState *clock_src; /* clock source */
+    uint32_t start_delay_ns; /* initial command kick off delay */
+    uint32_t completion_delay_ns; /** completion delay/pacing */
+    uint32_t bus_num; /* SPI host port number */
+    uint32_t num_cs; /* Supported CS line count */
+    uint8_t version; /* HW version */
+};
+
+/* ------------------------------------------------------------------------ */
+/* FIFOs */
+/* ------------------------------------------------------------------------ */
+
+static void txfifo_create(TxFifo *fifo, uint32_t capacity)
+{
+    capacity /= sizeof(uint32_t); /* capacity is specified in bytes */
+    fifo->data = g_new(TxFifoSlot, capacity);
+    fifo->capacity = capacity;
+    fifo->head = 0u;
+    fifo->num = 0u;
+}
+
+static void txfifo_push(TxFifo *fifo, uint32_t data, uint32_t size)
+{
+    g_assert(fifo->num < fifo->capacity);
+
+    switch (size) {
+    case sizeof(uint32_t):
+    case sizeof(uint16_t):
+    case sizeof(uint8_t):
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+    TxFifoSlot slot = {
+        .bits = (1u << size) - 1u,
+        .data = data,
+    };
+    fifo->data[(fifo->head + fifo->num) % fifo->capacity] = slot;
+    fifo->num++;
+}
+
+static uint8_t txfifo_pop(TxFifo *fifo, bool last)
+{
+    g_assert(fifo->num > 0);
+    TxFifoSlot slot = fifo->data[fifo->head];
+    uint8_t ret = (uint8_t)slot.data;
+    if (slot.bits > 1u && !last) {
+        slot.data >>= 8u;
+        slot.bits >>= 1u;
+        fifo->data[fifo->head] = slot;
+    } else {
+        fifo->head++;
+        fifo->head %= fifo->capacity;
+        fifo->num--;
+    }
+    return ret;
+}
+
+static void txfifo_reset(TxFifo *fifo)
+{
+    fifo->num = 0u;
+    fifo->head = 0u;
+}
+
+static bool txfifo_is_empty(const TxFifo *fifo)
+{
+    return (fifo->num == 0u);
+}
+
+static bool txfifo_is_full(const TxFifo *fifo)
+{
+    return (fifo->num == fifo->capacity);
+}
+
+static uint32_t txfifo_slot_used(const TxFifo *fifo)
+{
+    return fifo->num;
+}
+
+static void cmdfifo_create(CmdFifo *fifo, uint32_t capacity)
+{
+    fifo->data = g_new(CmdFifoSlot, capacity);
+    fifo->capacity = capacity;
+    fifo->head = 0u;
+    fifo->num = 0u;
+}
+
+static void cmdfifo_push(CmdFifo *fifo, const CmdFifoSlot *cmd)
+{
+    g_assert(fifo->num < fifo->capacity);
+    memcpy(&fifo->data[(fifo->head + fifo->num) % fifo->capacity], cmd,
+           sizeof(*cmd));
+    fifo->num++;
+}
+
+static void cmdfifo_pop(CmdFifo *fifo, CmdFifoSlot *cmd)
+{
+    g_assert(fifo->num > 0u);
+    if (cmd) {
+        memcpy(cmd, &fifo->data[fifo->head], sizeof(*cmd));
+    }
+    fifo->head++;
+    fifo->head %= fifo->capacity;
+    fifo->num--;
+}
+
+static void cmdfifo_reset(CmdFifo *fifo)
+{
+    fifo->num = 0u;
+    fifo->head = 0u;
+}
+
+static bool cmdfifo_is_empty(const CmdFifo *fifo)
+{
+    return (fifo->num == 0);
+}
+
+static bool cmdfifo_is_full(const CmdFifo *fifo)
+{
+    return (fifo->num == fifo->capacity);
+}
+
+static uint32_t cmdfifo_num_used(const CmdFifo *fifo)
+{
+    return fifo->num;
+}
+
+/* ------------------------------------------------------------------------ */
+/* Helpers */
+/* ------------------------------------------------------------------------ */
+
+static uint32_t ot_spi_host_convert_from_c2_command(uint32_t eg_cmd)
+{
+    uint32_t csaat = FIELD_EX32(eg_cmd, COMMAND, V2_CSAAT);
+    uint32_t speed = FIELD_EX32(eg_cmd, COMMAND, V2_SPEED);
+    uint32_t direction = FIELD_EX32(eg_cmd, COMMAND, V2_DIRECTION);
+    uint32_t len = FIELD_EX32(eg_cmd, COMMAND, V2_LEN);
+
+    /* EG 1.0.0 has a narrower length field, so this conversion is safe. */
+    uint32_t cmd = 0;
+    cmd = FIELD_DP32(cmd, COMMAND, CSAAT, csaat);
+    cmd = FIELD_DP32(cmd, COMMAND, SPEED, speed);
+    cmd = FIELD_DP32(cmd, COMMAND, DIRECTION, direction);
+    cmd = FIELD_DP32(cmd, COMMAND, LEN, len);
+    return cmd;
+}
+
+static bool ot_spi_host_is_rx(uint32_t command)
+{
+    return (bool)(FIELD_EX32(command, COMMAND, DIRECTION) & 0x1u);
+}
+
+static bool ot_spi_host_is_tx(uint32_t command)
+{
+    return (bool)(FIELD_EX32(command, COMMAND, DIRECTION) & 0x2u);
+}
+
+static bool ot_spi_host_is_ready(const OtSPIHostState *s)
+{
+    return !cmdfifo_is_full(s->cmd_fifo);
+}
+
+/* Passthrough functionality is only implemented if there is one CS */
+static inline bool ot_spi_host_supports_passthrough(const OtSPIHostState *s)
+{
+    return s->num_cs == 1u;
+}
+
+static void ot_spi_host_update_muxed_cs0(OtSPIHostState *s)
+{
+    if (ot_spi_host_supports_passthrough(s)) {
+        ibex_irq_set(&s->cs_lines[0],
+                     s->passthrough_en ? s->passthrough_cs : s->host_cs0);
+    } else {
+        ibex_irq_set(&s->cs_lines[0], s->host_cs0);
+    }
+}
+
+static void ot_spi_host_chip_select(OtSPIHostState *s, unsigned csid,
+                                    bool activate)
+{
+    if (csid < s->num_cs) {
+        trace_ot_spi_host_cs(s->ot_id, csid, activate ? "" : "de");
+        if (csid == 0u) {
+            s->host_cs0 = !activate;
+            ot_spi_host_update_muxed_cs0(s);
+        } else {
+            ibex_irq_set(&s->cs_lines[csid], !activate);
+        }
+    }
+}
+
+static inline bool ot_spi_host_passthrough_active(const OtSPIHostState *s)
+{
+    return ot_spi_host_supports_passthrough(s) && s->passthrough_en;
+}
+
+static bool ot_spi_host_update_stall(OtSPIHostState *s)
+{
+    g_assert(s->active.state != CMD_NONE);
+
+    uint32_t command = s->active.cmd.command;
+    unsigned length = FIELD_EX32(command, COMMAND, LEN) + 1u;
+    bool read = ot_spi_host_is_rx(command);
+    bool write = ot_spi_host_is_tx(command);
+
+    bool resume = true;
+
+    if (write && txfifo_is_empty(s->tx_fifo)) {
+        trace_ot_spi_host_stall(s->ot_id, "TX", length);
+        s->fsm.tx_stall = true;
+        resume = false;
+    }
+
+    if (read && fifo8_is_full(s->rx_fifo)) {
+        trace_ot_spi_host_stall(s->ot_id, "RX", length);
+        s->fsm.rx_stall = true;
+
+        resume = false;
+    }
+
+    return resume;
+}
+
+static void ot_spi_host_trace_status(const OtSPIHostState *s, const char *msg,
+                                     uint32_t status)
+{
+    unsigned cmd = FIELD_EX32(status, STATUS, CMDQD);
+    unsigned rxd = FIELD_EX32(status, STATUS, RXQD);
+    unsigned txd = FIELD_EX32(status, STATUS, TXQD);
+    char str[64u];
+    int last =
+        snprintf(str, sizeof(str), "%s%s%s%s%s%s%s%s%s%s",
+                 FIELD_EX32(status, STATUS, RXWM) ? "RXM|" : "",
+                 FIELD_EX32(status, STATUS, RXSTALL) ? "RXS|" : "",
+                 FIELD_EX32(status, STATUS, RXEMPTY) ? "RXE|" : "",
+                 FIELD_EX32(status, STATUS, RXFULL) ? "RXF|" : "",
+                 FIELD_EX32(status, STATUS, TXWM) ? "TXM|" : "",
+                 FIELD_EX32(status, STATUS, TXSTALL) ? "TXS|" : "",
+                 FIELD_EX32(status, STATUS, TXEMPTY) ? "TXE|" : "",
+                 FIELD_EX32(status, STATUS, TXFULL) ? "TXF|" : "",
+                 FIELD_EX32(status, STATUS, ACTIVE) ? "ACT|" : "",
+                 FIELD_EX32(status, STATUS, READY) ? "RDY|" : "");
+    if (str[last - 1] == '|') {
+        str[last - 1] = '\0';
+    }
+    char st = (char)(s->active.state == CMD_NONE ?
+                         'N' :
+                         (s->active.state == CMD_ONGOING ? 'O' : 'X'));
+    trace_ot_spi_host_status(s->ot_id, msg, status, str, cmd, rxd, txd, st);
+}
+
+static uint32_t ot_spi_host_get_status(OtSPIHostState *s)
+{
+    uint32_t status = R_STATUS_BYTEORDER_MASK; /* always little-endian */
+
+    /* RX */
+
+    /* round down, RXD should be seen as empty till it is padded */
+    uint32_t rxqd = fifo8_num_used(s->rx_fifo) / sizeof(uint32_t);
+    bool rxwm = rxqd >= REG_GET(s, CONTROL, RX_WATERMARK);
+    status = FIELD_DP32(status, STATUS, RXQD, rxqd);
+    status = FIELD_DP32(status, STATUS, RXWM, (uint32_t)rxwm);
+    /*
+     * the RX FIFO should be considered as empty as long as less than a full
+     * slot (4 bytes) has been filled in. Otherwise the RXE bit may be set as
+     * soon as a single byte is received from the slave, whereas the RX slot
+     * padding has not yet been performed
+     */
+    bool rxe = fifo8_num_used(s->rx_fifo) < sizeof(uint32_t);
+    status = FIELD_DP32(status, STATUS, RXEMPTY, (uint32_t)rxe);
+    status =
+        FIELD_DP32(status, STATUS, RXFULL, (uint32_t)fifo8_is_full(s->rx_fifo));
+    status = FIELD_DP32(status, STATUS, RXSTALL, s->fsm.rx_stall);
+
+    /* TX */
+    uint32_t txqd = txfifo_slot_used(s->tx_fifo);
+    bool txwm = txqd < REG_GET(s, CONTROL, TX_WATERMARK);
+    status = FIELD_DP32(status, STATUS, TXQD, txqd);
+    status = FIELD_DP32(status, STATUS, TXWM, (uint32_t)txwm);
+    status = FIELD_DP32(status, STATUS, TXEMPTY,
+                        (uint32_t)txfifo_is_empty(s->tx_fifo));
+    status = FIELD_DP32(status, STATUS, TXFULL,
+                        (uint32_t)txfifo_is_full(s->tx_fifo));
+    status = FIELD_DP32(status, STATUS, TXSTALL, s->fsm.tx_stall);
+
+    /* CMD */
+    status = FIELD_DP32(status, STATUS, CMDQD, cmdfifo_num_used(s->cmd_fifo));
+
+    /* State */
+    status =
+        FIELD_DP32(status, STATUS, READY, (uint32_t)ot_spi_host_is_ready(s));
+    status = FIELD_DP32(status, STATUS, ACTIVE,
+                        (uint32_t)(s->active.state != CMD_NONE));
+
+    return status;
+}
+
+static uint32_t ot_spi_host_build_event_bits(OtSPIHostState *s)
+{
+    /* round down, RXD should be seen as empty till it is padded */
+    uint32_t rxqd = fifo8_num_used(s->rx_fifo) / sizeof(uint32_t);
+    bool rxwm = rxqd >= REG_GET(s, CONTROL, RX_WATERMARK);
+    uint32_t txqd = txfifo_slot_used(s->tx_fifo);
+    bool txwm = txqd < REG_GET(s, CONTROL, TX_WATERMARK);
+
+    uint32_t events;
+    events = FIELD_DP32(0, EVENT_ENABLE, RXFULL,
+                        (uint32_t)fifo8_is_full(s->rx_fifo));
+    events = FIELD_DP32(events, EVENT_ENABLE, TXEMPTY,
+                        (uint32_t)txfifo_is_empty(s->tx_fifo));
+    events = FIELD_DP32(events, EVENT_ENABLE, RXWM, rxwm);
+    events = FIELD_DP32(events, EVENT_ENABLE, TXWM, txwm);
+    events = FIELD_DP32(events, EVENT_ENABLE, READY,
+                        (uint32_t)ot_spi_host_is_ready(s));
+    events = FIELD_DP32(events, EVENT_ENABLE, IDLE,
+                        (uint32_t)(s->active.state == CMD_NONE));
+    return events;
+}
+
+/* ------------------------------------------------------------------------ */
+/* IRQ and alert management */
+/* ------------------------------------------------------------------------ */
+
+/** IRQ lines */
+enum OtSPIHostIrq {
+    IRQ_ERROR,
+    IRQ_SPI_EVENT,
+    IRQ_COUNT,
+};
+
+static bool ot_spi_host_update_event(OtSPIHostState *s)
+{
+    uint32_t events = ot_spi_host_build_event_bits(s);
+    uint32_t eff_events = events & s->regs[R_EVENT_ENABLE];
+    trace_ot_spi_host_events(s->ot_id, events, events, events,
+                             s->regs[R_EVENT_ENABLE], eff_events);
+
+    bool event = (bool)eff_events;
+    event |= (bool)(s->regs[R_INTR_TEST] & INTR_SPI_EVENT_MASK);
+    s->regs[R_INTR_TEST] &= ~INTR_SPI_EVENT_MASK;
+    if (event) {
+        s->regs[R_INTR_STATE] |= INTR_SPI_EVENT_MASK;
+    } else {
+        s->regs[R_INTR_STATE] &= ~INTR_SPI_EVENT_MASK;
+    }
+
+    bool event_level = (bool)(s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE] &
+                              INTR_SPI_EVENT_MASK);
+    if (event_level != (bool)ibex_irq_get_level(&s->irqs[IRQ_SPI_EVENT])) {
+        trace_ot_spi_host_update_irq(s->ot_id, "event", event_level);
+    }
+    ibex_irq_set(&s->irqs[IRQ_SPI_EVENT], event_level);
+
+    return event;
+}
+
+static bool ot_spi_host_update_error(OtSPIHostState *s)
+{
+    if (s->regs[R_ERROR_STATUS] & s->regs[R_ERROR_ENABLE]) {
+        s->regs[R_INTR_STATE] |= INTR_ERROR_MASK;
+    }
+
+    if (s->regs[R_INTR_TEST] & INTR_ERROR_MASK) {
+        s->regs[R_INTR_TEST] &= ~INTR_ERROR_MASK;
+        s->regs[R_INTR_STATE] |= INTR_ERROR_MASK;
+    }
+
+    bool error = (bool)(s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE] &
+                        INTR_ERROR_MASK);
+    if (error != (bool)ibex_irq_get_level(&s->irqs[IRQ_ERROR])) {
+        trace_ot_spi_host_update_irq(s->ot_id, "error", error);
+    }
+    ibex_irq_set(&s->irqs[IRQ_ERROR], error);
+
+    return error;
+}
+
+static void ot_spi_host_update_regs(OtSPIHostState *s)
+{
+    ot_spi_host_update_error(s);
+    ot_spi_host_update_event(s);
+}
+
+static void ot_spi_host_update_alert(OtSPIHostState *s)
+{
+    /*
+     * note: there is no other way to trigger a fatal error but the alert test
+     * register in QEMU
+     */
+    bool alert = (bool)s->regs[R_ALERT_TEST];
+    ibex_irq_set(&s->alert, alert);
+}
+
+/* ------------------------------------------------------------------------ */
+/* State machine and I/O */
+/* ------------------------------------------------------------------------ */
+
+static void ot_spi_host_internal_reset(OtSPIHostState *s)
+{
+    trace_ot_spi_host_internal_reset(s->ot_id, s->start_delay_ns,
+                                     s->completion_delay_ns);
+
+    timer_del(s->fsm_delay);
+
+    /* rxdata, txdata, and command registers are managed w/ FIFOs */
+    fifo8_reset(s->rx_fifo);
+    txfifo_reset(s->tx_fifo);
+    cmdfifo_reset(s->cmd_fifo);
+
+    memset(&s->fsm, 0, sizeof(s->fsm));
+    memset(&s->active, 0, sizeof(s->active));
+
+    for (unsigned csid = 0u; csid < s->num_cs; csid++) {
+        ot_spi_host_chip_select(s, csid, false);
+    }
+
+    s->total_transfer = 0;
+    s->last_command_id = 0;
+    s->last_clkdiv = UINT32_MAX;
+
+    ot_spi_host_update_regs(s);
+    ot_spi_host_update_alert(s);
+
+    ot_spi_host_trace_status(s, "intrst", ot_spi_host_get_status(s));
+}
+
+static void ot_spi_host_step_fsm(OtSPIHostState *s, const char *cause)
+{
+    trace_ot_spi_host_fsm(s->ot_id, s->active.cmd.id, cause);
+
+    ot_spi_host_update_event(s);
+
+    unsigned byte_count = 0;
+    bool resched = true;
+
+    if (s->active.state == CMD_EXECUTED) {
+        goto post;
+    }
+
+    uint32_t command = s->active.cmd.command;
+    bool read = ot_spi_host_is_rx(command);
+    bool write = ot_spi_host_is_tx(command);
+    unsigned speed = FIELD_EX32(command, COMMAND, SPEED);
+    unsigned clkdiv = FIELD_EX32(s->active.cmd.opts, CONFIGOPTS, CLKDIV);
+    if (trace_event_get_state(TRACE_OT_SPI_HOST_CMD_CLOCK)) {
+        if (clkdiv != s->last_clkdiv) {
+            unsigned spiclock = s->pclk / ((clkdiv + 1u) * 2u);
+            trace_ot_spi_host_cmd_clock(s->ot_id, s->active.cmd.id,
+                                        s->completion_delay_ns == 0, spiclock);
+        }
+    }
+    s->last_clkdiv = clkdiv;
+    unsigned length = FIELD_EX32(command, COMMAND, LEN) + 1u;
+    if (!(read || write)) {
+        /* dummy mode uses clock cycle count rather than byte count */
+        if (length % (1u << (3u - speed))) {
+            qemu_log_mask(
+                LOG_UNIMP,
+                "%s: %s: unsupported clk cycle count: %u for speed %u\n",
+                __func__, s->ot_id, length, speed);
+        }
+        length = DIV_ROUND_UP(length, 8u);
+    }
+
+    ot_spi_host_trace_status(s, "S>", ot_spi_host_get_status(s));
+
+    trace_ot_spi_host_exec_command(
+        s->ot_id, s->active.cmd.id,
+        F_COMMAND_DIRECTION[FIELD_EX32(command, COMMAND, DIRECTION)],
+        F_COMMAND_SPEED[FIELD_EX32(command, COMMAND, SPEED)],
+        (unsigned)s->active.cmd.cs, (bool)FIELD_EX32(command, COMMAND, CSAAT),
+        length, s->fsm.transaction);
+
+    if (s->active.size == 0) {
+        s->active.ts = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+    }
+
+    bool multi = speed != 0;
+
+    while (length) {
+        if (write && txfifo_is_empty(s->tx_fifo)) {
+            break;
+        }
+        if (read && fifo8_is_full(s->rx_fifo)) {
+            break;
+        }
+
+        if (!s->fsm.transaction) {
+            s->fsm.transaction = true;
+            if (ot_spi_host_passthrough_active(s)) {
+                qemu_log_mask(
+                    LOG_GUEST_ERROR,
+                    "%s: %s: SPI Host active CS while Passthrough is active\n",
+                    __func__, s->ot_id);
+            }
+            ot_spi_host_chip_select(s, s->active.cmd.cs, s->fsm.transaction);
+        }
+
+        uint8_t tx = write ? (uint8_t)txfifo_pop(s->tx_fifo, length == 1u) :
+                             SPI_DEFAULT_TX_RX_VALUE;
+
+        uint8_t rx = SPI_DEFAULT_TX_RX_VALUE;
+
+        if (s->fsm.output_en) {
+            if (ot_spi_host_passthrough_active(s)) {
+                if (!s->transfer_error_emitted) {
+                    s->transfer_error_emitted = true;
+                    qemu_log_mask(
+                        LOG_GUEST_ERROR,
+                        "%s: %s: Host transfer while Passthrough is active\n",
+                        __func__, s->ot_id);
+                }
+            } else {
+                rx = (uint8_t)ssi_transfer(s->ssi, tx);
+            }
+        }
+
+        if (multi && read && write) {
+            /* invalid command, lets corrupt input data */
+            trace_ot_spi_host_debug(s->ot_id,
+                                    "conflicting command: input is overridden");
+            rx ^= tx;
+        }
+
+        if (read) {
+            fifo8_push(s->rx_fifo, rx);
+        }
+
+        trace_ot_spi_host_transfer(s->ot_id, s->total_transfer, tx, rx);
+        s->total_transfer += 1u;
+
+        length--;
+        byte_count++;
+    }
+
+    if (length) {
+        /* if the transfer early ended, a stall condition has been detected */
+        s->active.cmd.command = FIELD_DP32(command, COMMAND, LEN, length - 1);
+        resched = ot_spi_host_update_stall(s);
+    } else {
+        s->active.cmd.command = FIELD_DP32(command, COMMAND, LEN, 0);
+        s->active.state = CMD_EXECUTED;
+    }
+
+post:
+    ot_spi_host_update_regs(s);
+
+    s->active.size += byte_count;
+
+    int64_t delay;
+    if (s->active.state == CMD_EXECUTED && byte_count) {
+        if (!s->completion_delay_ns) {
+            unsigned spiclock = s->pclk / ((clkdiv + 1u) * 2u);
+            delay = NANOSECONDS_PER_SECOND / (int64_t)spiclock;
+            delay *= s->active.size;
+            delay >>= speed;
+        } else {
+            delay = (int64_t)s->completion_delay_ns;
+        }
+        timer_mod(s->fsm_delay, qemu_clock_get_ns(OT_VIRTUAL_CLOCK) + delay);
+    } else if (!timer_pending(s->fsm_delay)) {
+        delay = (int64_t)s->completion_delay_ns;
+        if (resched) {
+            /*
+             * Do not reschedule the FSM when a stall prevents any further
+             * action. Once the SPI Host is read/written and data FIFO(s) get
+             * some free slots, the FSM is automatically rescheduled
+             */
+            timer_mod(s->fsm_delay,
+                      qemu_clock_get_ns(OT_VIRTUAL_CLOCK) + delay);
+        }
+    }
+
+    ot_spi_host_trace_status(s, "S<", ot_spi_host_get_status(s));
+}
+
+static void ot_spi_host_retire(OtSPIHostState *s)
+{
+    uint32_t command = s->active.cmd.command;
+
+    if (trace_event_get_state(TRACE_OT_SPI_HOST_CMD_STAT)) {
+        int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+        int64_t elapsed = now - s->active.ts;
+        if (s->active.size) {
+            unsigned speed =
+                (unsigned)((s->active.size * NANOSECONDS_PER_SECOND) / elapsed);
+            trace_ot_spi_host_cmd_stat(s->ot_id, s->active.cmd.id,
+                                       s->active.size, speed);
+        }
+    }
+
+    trace_ot_spi_host_retire_command(s->ot_id, s->active.cmd.id);
+
+    if (ot_spi_host_is_rx(command)) {
+        /*
+         * transfer has been completed, RX FIFO may need padding up to a
+         * word
+         */
+        while (!fifo8_is_full(s->rx_fifo) &&
+               fifo8_num_used(s->rx_fifo) & 0x3u) {
+            fifo8_push(s->rx_fifo, 0u);
+        }
+    }
+
+    /* release /CS if this is the last command of the current transaction */
+    if (!FIELD_EX32(command, COMMAND, CSAAT)) {
+        s->fsm.transaction = false;
+        ot_spi_host_chip_select(s, s->active.cmd.cs, s->fsm.transaction);
+    }
+
+    /* retire command */
+    s->active.state = CMD_NONE;
+
+    /* last command has completed */
+    if (!cmdfifo_is_empty(s->cmd_fifo)) {
+        /* more commands have been scheduled */
+        trace_ot_spi_host_debug(s->ot_id, "next cmd");
+        if (s->active.state == CMD_NONE) {
+            cmdfifo_pop(s->cmd_fifo, &s->active.cmd);
+            s->active.state = CMD_ONGOING;
+            s->active.size = 0u;
+        }
+        ot_spi_host_step_fsm(s, "post");
+    } else {
+        trace_ot_spi_host_debug(s->ot_id, "no resched: no cmd");
+    }
+
+    ot_spi_host_update_regs(s);
+}
+
+static void ot_spi_host_schedule_fsm(void *opaque)
+{
+    OtSPIHostState *s = opaque;
+
+    trace_ot_spi_host_fsm(s->ot_id, s->active.cmd.id, "sched");
+
+    bool retire = s->active.state == CMD_EXECUTED;
+
+    ot_spi_host_trace_status(s, "P>", ot_spi_host_get_status(s));
+
+    if (retire) {
+        ot_spi_host_retire(s);
+    } else {
+        ot_spi_host_update_regs(s);
+
+        uint32_t command = s->active.cmd.command;
+        unsigned length = FIELD_EX32(command, COMMAND, LEN) + 1u;
+        bool pending = timer_pending(s->fsm_delay);
+        trace_ot_spi_host_cmd_ongoing(s->ot_id, s->active.cmd.id, length,
+                                      pending);
+        if (!pending) {
+            ot_spi_host_step_fsm(s, "pending");
+        }
+    }
+
+    ot_spi_host_trace_status(s, "P<", ot_spi_host_get_status(s));
+}
+
+static void ot_spi_host_clock_input(void *opaque, int irq, int level)
+{
+    OtSPIHostState *s = opaque;
+
+    g_assert(irq == 0);
+
+    s->pclk = (unsigned)level;
+
+    /* TODO: disable SPI transfer when PCLK is 0 */
+    trace_ot_spi_host_clock_update(s->ot_id, s->pclk);
+}
+
+static uint64_t ot_spi_host_io_read(void *opaque, hwaddr addr,
+                                    unsigned int size)
+{
+    OtSPIHostState *s = opaque;
+    uint32_t val32;
+
+    if (s->on_reset) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: device in reset\n", __func__,
+                      s->ot_id);
+        return 0u;
+    }
+
+    /* Match reg index */
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_INTR_TEST:
+    case R_ALERT_TEST:
+    case R_COMMAND:
+    case R_TXDATA:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0u;
+        break;
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_CONTROL:
+    case R_ERROR_ENABLE:
+    case R_ERROR_STATUS:
+    case R_EVENT_ENABLE:
+    case R_CSID:
+    case R_CONFIGOPTS:
+        val32 = s->regs[reg];
+        break;
+    case R_STATUS:
+        val32 = ot_spi_host_get_status(s);
+        break;
+    case R_RXDATA: {
+        /* here, size != 4 is illegal, what to do in this case? */
+        if (fifo8_num_used(s->rx_fifo) < sizeof(uint32_t)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Read underflow: %u\n",
+                          __func__, s->ot_id, fifo8_num_used(s->rx_fifo));
+            REG_UPDATE(s, ERROR_STATUS, UNDERFLOW, 1);
+            ot_spi_host_update_regs(s);
+            val32 = 0u;
+            break;
+        }
+        val32 = 0u;
+        for (unsigned ix = 0u; ix < size; ix++) {
+            val32 <<= 8u;
+            val32 |= (uint32_t)fifo8_pop(s->rx_fifo);
+        }
+        ot_spi_host_trace_status(s, "rxd", ot_spi_host_get_status(s));
+        val32 = bswap32(val32);
+        bool resume = false;
+        if (s->active.state != CMD_NONE) {
+            if (!s->fsm.tx_stall) {
+                uint32_t rxwm = REG_GET(s, CONTROL, RX_WATERMARK);
+                if (rxwm < sizeof(uint32_t)) {
+                    rxwm = sizeof(uint32_t);
+                }
+                uint32_t inlen = fifo8_num_used(s->rx_fifo) / sizeof(uint32_t);
+                if (inlen <= rxwm) {
+                    resume = true;
+                }
+            }
+        }
+        s->fsm.rx_stall = false;
+        if (resume) {
+            ot_spi_host_step_fsm(s, "rx");
+        } else {
+            ot_spi_host_update_regs(s);
+        }
+        break;
+    }
+    default:
+        val32 = 0u;
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+
+#ifdef DISCARD_REPEATED_STATUS_TRACES
+    static TraceCache trace_cache;
+
+    if (trace_cache.pc != pc || trace_cache.addr != addr ||
+        trace_cache.value != val32) {
+        if (trace_cache.count > 1u) {
+            hwaddr rreg = R32_OFF(trace_cache.addr);
+            trace_ot_spi_host_io_read_repeat(s->ot_id, REG_NAME(rreg),
+                                             trace_cache.count);
+        }
+#endif /* DISCARD_REPEATED_STATUS_TRACES */
+        trace_ot_spi_host_io_read(s->ot_id, (uint32_t)addr, REG_NAME(reg),
+                                  val32, pc);
+        if (reg == R_STATUS) {
+            ot_spi_host_trace_status(s, "", val32);
+        }
+#ifdef DISCARD_REPEATED_STATUS_TRACES
+        trace_cache.count = 1u;
+    } else {
+        trace_cache.count += 1u;
+    }
+    trace_cache.pc = pc;
+    trace_cache.addr = addr;
+    trace_cache.value = val32;
+#endif /* DISCARD_REPEATED_STATUS_TRACES */
+
+    return val32;
+}
+
+static void ot_spi_host_io_write(void *opaque, hwaddr addr, uint64_t val64,
+                                 unsigned int size)
+{
+    OtSPIHostState *s = opaque;
+    uint32_t val32 = val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_spi_host_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                               pc);
+
+    if (s->on_reset) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: device in reset\n", __func__,
+                      s->ot_id);
+        return;
+    }
+
+    switch (reg) {
+    /* Skipping any R/O registers */
+    case R_INTR_STATE:
+        val32 &= INTR_ERROR_MASK; /* rw1c bit */
+        s->regs[R_INTR_STATE] &= ~val32;
+        /* this call also regenerates all raised events */
+        ot_spi_host_update_regs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_ENABLE] = val32;
+        ot_spi_host_update_regs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_TEST] = val32;
+        ot_spi_host_update_regs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        s->regs[R_ALERT_TEST] = val32;
+        ot_spi_host_update_alert(s);
+        break;
+    case R_CONTROL:
+        val32 &= R_CONTROL_MASK;
+        s->regs[R_CONTROL] = val32;
+        if (FIELD_EX32(val32, CONTROL, SW_RST)) {
+            ot_spi_host_internal_reset(s);
+        }
+        s->fsm.output_en = FIELD_EX32(val32, CONTROL, OUTPUT_EN);
+        if (!cmdfifo_is_empty(s->cmd_fifo)) {
+            ot_spi_host_step_fsm(s, "ctrl");
+        }
+        break;
+    case R_CONFIGOPTS:
+    case R_CSID:
+        s->regs[reg] = val32;
+        break;
+    case R_COMMAND: {
+        /* Convert command for back-compat with v2 fields */
+        if (s->version == 2u) {
+            val32 = ot_spi_host_convert_from_c2_command(val32);
+        }
+        val32 &= R_COMMAND_MASK;
+
+        /* IP not enabled */
+        if (!(REG_GET(s, CONTROL, SPIEN))) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: no SPI/EN\n", __func__,
+                          s->ot_id);
+            return;
+        }
+
+        if (!ot_spi_host_is_ready(s)) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: busy (cmd_fifo full)\n",
+                          __func__, s->ot_id);
+            REG_UPDATE(s, ERROR_STATUS, CMDBUSY, 1u);
+            ot_spi_host_update_regs(s);
+            break;
+        }
+
+        if (((FIELD_EX32(val32, COMMAND, DIRECTION) == 0x3u) &&
+             (FIELD_EX32(val32, COMMAND, SPEED) != 0u)) ||
+            (FIELD_EX32(val32, COMMAND, SPEED) == 3u)) {
+            /* dual/quad SPI cannot be used w/ full duplex mode */
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: invalid command parameters\n", __func__,
+                          s->ot_id);
+            REG_UPDATE(s, ERROR_STATUS, CMDINVAL, 1u);
+        }
+
+        unsigned csid = s->regs[R_CSID];
+
+        if (!(csid < s->num_cs)) {
+            /* CSID exceeds max num_cs */
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: invalid csid: %u\n",
+                          __func__, s->ot_id, csid);
+            REG_UPDATE(s, ERROR_STATUS, CSIDINVAL, 1u);
+            csid = 0;
+        }
+
+        CmdFifoSlot slot = {
+            .opts = s->regs[R_CONFIGOPTS],
+            .command = val32,
+            .cs = csid,
+            .id = s->last_command_id++,
+        };
+
+        trace_ot_spi_host_new_command(
+            s->ot_id, slot.id,
+            F_COMMAND_DIRECTION[FIELD_EX32(slot.command, COMMAND, DIRECTION)],
+            F_COMMAND_SPEED[FIELD_EX32(slot.command, COMMAND, SPEED)], csid,
+            (bool)FIELD_EX32(slot.command, COMMAND, CSAAT),
+            FIELD_EX32(slot.command, COMMAND, LEN) + 1u);
+
+        cmdfifo_push(s->cmd_fifo, &slot);
+
+        if (s->active.state == CMD_NONE) {
+            cmdfifo_pop(s->cmd_fifo, &s->active.cmd);
+            s->active.state = CMD_ONGOING;
+            s->active.size = 0u;
+            bool activate = ot_spi_host_update_stall(s);
+            ot_spi_host_update_regs(s);
+
+            trace_ot_spi_host_kick_command(s->ot_id, s->active.cmd.id,
+                                           activate);
+
+            if (activate) {
+                /*
+                 * add a small delay before kicking of the command FSM. This
+                 * yield execution back to the vCPU (releasing the IO thread),
+                 * so the guest can check the SPI Host status, etc. This very
+                 * short delay does not slow down execution.
+                 */
+                timer_mod(s->fsm_delay, qemu_clock_get_ns(OT_VIRTUAL_CLOCK) +
+                                            s->start_delay_ns);
+            }
+            break;
+        }
+        ot_spi_host_update_regs(s);
+        break;
+    }
+    case R_RXDATA:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_TXDATA: {
+        if (txfifo_is_full(s->tx_fifo)) {
+            REG_UPDATE(s, ERROR_STATUS, OVERFLOW, 1u);
+            ot_spi_host_update_regs(s);
+            return;
+        }
+
+        txfifo_push(s->tx_fifo, val32, size);
+        bool resume = (s->active.state != CMD_NONE) && s->fsm.tx_stall &&
+                      !s->fsm.rx_stall;
+        s->fsm.tx_stall = false;
+        if (resume) {
+            ot_spi_host_step_fsm(s, "tx");
+        } else {
+            ot_spi_host_update_regs(s);
+        }
+    } break;
+    case R_ERROR_ENABLE:
+        val32 &= R_ERROR_ENABLE_MASK;
+        s->regs[R_ERROR_ENABLE] = val32;
+        ot_spi_host_update_error(s);
+        break;
+    case R_ERROR_STATUS:
+        /*
+         * Indicates any errors that have occurred.  When an error occurs, the
+         * corresponding bit must be cleared here before issuing any further
+         * commands
+         */
+        val32 &= R_ERROR_STATUS_MASK;
+        s->regs[R_ERROR_STATUS] &= ~val32;
+        if (!cmdfifo_is_empty(s->cmd_fifo) && !s->regs[R_ERROR_STATUS] &&
+            !s->fsm.tx_stall && !s->fsm.rx_stall) {
+            ot_spi_host_step_fsm(s, "err");
+        } else {
+            ot_spi_host_update_error(s);
+        }
+        break;
+    case R_EVENT_ENABLE:
+        s->regs[R_EVENT_ENABLE] = val32 & R_EVENT_ENABLE_MASK;
+        ot_spi_host_update_event(s);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static uint8_t ot_spi_host_downstream_transfer(OtSPIHostState *s, uint8_t tx)
+{
+    if (!ot_spi_host_supports_passthrough(s)) {
+        if (!s->transfer_error_emitted) {
+            s->transfer_error_emitted = true;
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: SPI Host does not support passthrough: more "
+                          "than one CS\n",
+                          __func__, s->ot_id);
+        }
+        return SPI_DEFAULT_TX_RX_VALUE;
+    }
+
+    if (!s->passthrough_en) {
+        trace_ot_spi_host_passthrough_disabled(s->ot_id);
+        return SPI_DEFAULT_TX_RX_VALUE;
+    }
+
+    /* Forward to downstream flash */
+    return (uint8_t)ssi_transfer(s->ssi, (uint32_t)tx);
+}
+
+static void
+ot_spi_host_device_passthrough_en_input(void *opaque, int irq, int level)
+{
+    OtSPIHostState *s = opaque;
+    g_assert(irq == 0u);
+
+    s->transfer_error_emitted = false;
+
+    if (!ot_spi_host_supports_passthrough(s)) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: SPI Host does not support passthrough: more than one CS\n",
+            __func__, s->ot_id);
+        return;
+    }
+
+    if ((bool)level && !s->host_cs0) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Passthrough enabled while Host CS is active\n",
+                      __func__, s->ot_id);
+    }
+
+    s->passthrough_en = (bool)level;
+
+    ot_spi_host_update_muxed_cs0(s);
+}
+
+static void
+ot_spi_host_device_passthrough_cs_input(void *opaque, int irq, int level)
+{
+    OtSPIHostState *s = opaque;
+    g_assert(irq == 0u);
+
+    if (!ot_spi_host_supports_passthrough(s)) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: SPI Host does not support passthrough: more than one CS\n",
+            __func__, s->ot_id);
+        return;
+    }
+
+    if (!s->passthrough_en) {
+        trace_ot_spi_host_passthrough_disabled(s->ot_id);
+    }
+
+    s->passthrough_cs = (bool)level;
+
+    ot_spi_host_update_muxed_cs0(s);
+}
+
+/* ------------------------------------------------------------------------ */
+/* Device description/instanciation */
+/* ------------------------------------------------------------------------ */
+
+/* clang-format off */
+static const MemoryRegionOps ot_spi_host_ops = {
+    .read = ot_spi_host_io_read,
+    .write = ot_spi_host_io_write,
+    /* OpenTitan default LE */
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        /* although some registers only supports 2 or 4 byte write access */
+        .min_access_size = 1u,
+        .max_access_size = 4u,
+    }
+};
+/* clang-format on */
+
+static const Property ot_spi_host_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtSPIHostState, ot_id),
+    DEFINE_PROP_UINT32("num-cs", OtSPIHostState, num_cs, 1u),
+    DEFINE_PROP_UINT32("bus-num", OtSPIHostState, bus_num, 0u),
+    DEFINE_PROP_STRING("clock-name", OtSPIHostState, clock_name),
+    DEFINE_PROP_LINK("clock-src", OtSPIHostState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+    DEFINE_PROP_UINT32("start-delay", OtSPIHostState, start_delay_ns,
+                       FSM_START_DELAY_NS),
+    DEFINE_PROP_UINT32("completion-delay", OtSPIHostState, completion_delay_ns,
+                       0),
+    DEFINE_PROP_UINT8("version", OtSPIHostState, version, 0),
+};
+
+static void ot_spi_host_reset_enter(Object *obj, ResetType type)
+{
+    OtSPIHostClass *c = OT_SPI_HOST_GET_CLASS(obj);
+    OtSPIHostState *s = OT_SPI_HOST(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    s->regs[R_INTR_STATE] = 0x00u;
+    s->regs[R_INTR_ENABLE] = 0x00u;
+    s->regs[R_INTR_TEST] = 0x00u;
+    s->regs[R_ALERT_TEST] = 0x00u;
+    s->regs[R_CONTROL] = 0x7fu;
+    s->regs[R_CSID] = 0x00u;
+    s->regs[R_ERROR_ENABLE] = 0x1fu;
+    s->regs[R_ERROR_STATUS] = 0x00u;
+    s->regs[R_EVENT_ENABLE] = 0x00u;
+
+    s->on_reset = true;
+
+    s->passthrough_en = false;
+    s->passthrough_cs = true;
+    s->host_cs0 = true;
+
+    s->transfer_error_emitted = false;
+
+    if (!s->clock_src_name) {
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_name =
+            ic->get_clock_source(ii, s->clock_name, DEVICE(s), &error_fatal);
+        qemu_irq in_irq = qdev_get_gpio_in_named(DEVICE(s), "clock-in", 0);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_name, 0, in_irq);
+    }
+
+    ot_spi_host_internal_reset(s);
+}
+
+static void ot_spi_host_reset_exit(Object *obj, ResetType type)
+{
+    OtSPIHostClass *c = OT_SPI_HOST_GET_CLASS(obj);
+    OtSPIHostState *s = OT_SPI_HOST(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    s->on_reset = false;
+}
+
+static void ot_spi_host_realize(DeviceState *dev, Error **errp)
+{
+    OtSPIHostState *s = OT_SPI_HOST(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->clock_name);
+    g_assert(s->clock_src);
+    OBJECT_CHECK(IbexClockSrcIf, s->clock_src, TYPE_IBEX_CLOCK_SRC_IF);
+
+    g_assert(s->version > 1u); /* only supports v2 onward */
+
+    s->cs_lines = g_new0(IbexIRQ, (size_t)s->num_cs);
+
+    ibex_qdev_init_irqs(OBJECT(dev), &s->cs_lines[0], SSI_GPIO_CS, s->num_cs);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_spi_host_clock_input, "clock-in", 1);
+
+    char busname[16u];
+    if (snprintf(busname, sizeof(busname), "spi%u", s->bus_num) >=
+        sizeof(busname)) {
+        error_setg(&error_fatal, "Invalid SSI bus num %u", s->bus_num);
+        return;
+    }
+    s->ssi = ssi_create_bus(DEVICE(s), busname);
+}
+
+static void ot_spi_host_instance_init(Object *obj)
+{
+    OtSPIHostState *s = OT_SPI_HOST(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_spi_host_ops, s, TYPE_OT_SPI_HOST,
+                          0x40u);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    _Static_assert(IRQ_COUNT == ARRAY_SIZE(s->irqs), "Incoherent IRQ count");
+
+    ibex_qdev_init_irqs(obj, &s->irqs[0u], SYSBUS_DEVICE_GPIO_IRQ,
+                        ARRAY_SIZE(s->irqs));
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_spi_host_device_passthrough_en_input,
+                            OT_SPI_HOST_PASSTHROUGH_EN, 1);
+    qdev_init_gpio_in_named(DEVICE(s), &ot_spi_host_device_passthrough_cs_input,
+                            OT_SPI_HOST_PASSTHROUGH_CS, 1);
+
+    s->regs = g_new0(uint32_t, REGS_COUNT);
+
+    s->rx_fifo = g_new0(RxFifo, 1u);
+    s->tx_fifo = g_new0(TxFifo, 1u);
+    s->cmd_fifo = g_new0(CmdFifo, 1u);
+
+    fifo8_create(s->rx_fifo, RXFIFO_LEN);
+    txfifo_create(s->tx_fifo, TXFIFO_LEN);
+    cmdfifo_create(s->cmd_fifo, CMDFIFO_LEN);
+
+    s->fsm_delay = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_spi_host_schedule_fsm, s);
+}
+
+static void ot_spi_host_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = ot_spi_host_realize;
+    device_class_set_props(dc, ot_spi_host_properties);
+
+    OtSPIHostClass *sc = OT_SPI_HOST_CLASS(klass);
+    sc->ssi_downstream_transfer = &ot_spi_host_downstream_transfer;
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_spi_host_reset_enter, NULL,
+                                       &ot_spi_host_reset_exit,
+                                       &sc->parent_phases);
+}
+
+static const TypeInfo ot_spi_host_info = {
+    .name = TYPE_OT_SPI_HOST,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtSPIHostState),
+    .instance_init = ot_spi_host_instance_init,
+    .class_init = ot_spi_host_class_init,
+    .class_size = sizeof(OtSPIHostClass),
+};
+
+static void ot_spi_host_register_types(void)
+{
+    type_register_static(&ot_spi_host_info);
+}
+
+type_init(ot_spi_host_register_types);
diff --git a/hw/opentitan/ot_sram_ctrl.c b/hw/opentitan/ot_sram_ctrl.c
new file mode 100644
index 0000000000000..4cc4f6652f3d3
--- /dev/null
+++ b/hw/opentitan/ot_sram_ctrl.c
@@ -0,0 +1,914 @@
+/*
+ * QEMU OpenTitan SRAM controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Note: most units are based on 32-bit words as it eases alignment and
+ * management, and best fit with 32/7 ECC.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "qemu/typedefs.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_otp_if.h"
+#include "hw/opentitan/ot_prng.h"
+#include "hw/opentitan/ot_sram_ctrl.h"
+#include "hw/opentitan/ot_vmapper.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+#undef OT_SRAM_CTRL_DEBUG
+
+#define PARAM_NUM_ALERTS 1
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x0u)
+    FIELD(ALERT_TEST, FATAL_ERROR, 0u, 1u)
+REG32(STATUS, 0x4u)
+    FIELD(STATUS, BUS_INTEG_ERROR, 0u, 1u)
+    FIELD(STATUS, INIT_ERROR, 1u, 1u)
+    FIELD(STATUS, ESCALATED, 2u, 1u)
+    FIELD(STATUS, SCR_KEY_VALID, 3u, 1u)
+    FIELD(STATUS, SCR_KEY_SEED_VALID, 4u, 1u)
+    FIELD(STATUS, INIT_DONE, 5u, 1u)
+    FIELD(STATUS, READBACK_ERROR, 6u, 1u)
+    FIELD(STATUS, SRAM_ALERT, 7u, 1u)
+REG32(EXEC_REGWEN, 0x8u)
+    FIELD(EXEC_REGWEN, EN, 0u, 1u)
+REG32(EXEC, 0xcu)
+    FIELD(EXEC, EN, 0u, 4u)
+REG32(CTRL_REGWEN, 0x10u)
+    FIELD(CTRL_REGWEN_CTRL, REGWEN, 0u, 1u)
+REG32(CTRL, 0x14u)
+    FIELD(CTRL, RENEW_SCR_KEY, 0u, 1u)
+    FIELD(CTRL, INIT, 1u, 1u)
+REG32(SCR_KEY_ROTATED, 0x18u)
+    FIELD(SCR_KEY_ROTATED, SUCCESS, 0u, 4u)
+REG32(READBACK_REGWEN, 0x1cu)
+    FIELD(READBACK_REGWEN, EN, 0u, 1u)
+REG32(READBACK, 0x20u)
+    FIELD(READBACK, EN, 0u, 4u)
+
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_READBACK)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define INIT_TIMER_CHUNK_US    10u
+#define INIT_TIMER_CHUNK_WORDS (4096u / sizeof(uint32_t)) /* 4 KB */
+
+/* clang-format off */
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(EXEC_REGWEN),
+    REG_NAME_ENTRY(EXEC),
+    REG_NAME_ENTRY(CTRL_REGWEN),
+    REG_NAME_ENTRY(CTRL),
+    REG_NAME_ENTRY(SCR_KEY_ROTATED),
+    REG_NAME_ENTRY(READBACK_REGWEN),
+    REG_NAME_ENTRY(READBACK),
+};
+#undef REG_NAME_ENTRY
+/* clang-format on */
+
+typedef struct {
+    MemoryRegion alias; /* SRAM alias on one of the following */
+    MemoryRegion sram; /* SRAM memory (runtime) */
+    MemoryRegion init; /* SRAM memory (not yet initialized) */
+} OtSramCtrlMem;
+
+struct OtSramCtrlState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio; /* SRAM controller registers */
+    OtSramCtrlMem *mem; /* SRAM memory */
+    IbexIRQ alert;
+    QEMUTimer *init_timer; /* SRAM initialization timer */
+
+    uint64_t *init_sram_bm; /* initialization bitmap */
+    uint64_t *init_slot_bm; /* initialization bitmap shortcut */
+    OtPrngState *prng; /* simplified PRNG, does not match OT's */
+    OtOTPKey *otp_key;
+    uint32_t regs[REGS_COUNT];
+    unsigned init_slot_count; /* count of init_slot_bm */
+    unsigned init_slot_pos; /* current SRAM cell (word-sized) for init. */
+    unsigned wsize; /* size of RAM in words */
+    bool initialized; /* SRAM has been fully initialized at least once */
+    bool initializing; /* CTRL.INIT has been requested */
+    bool otp_ifetch; /* whether OTP enable execution from this RAM */
+    bool csr_ifetch; /* whether CSR enable execution from this RAM */
+    bool lc_hw_debug_ifetch; /* HW_DEBUG_EN signal from the lc_ctrl */
+    char *hexstr;
+
+    char *ot_id;
+    DeviceState *otp_ctrl; /* optional */
+    OtVMapperState *vmapper; /* optional */
+    uint32_t size; /* in bytes */
+    uint32_t init_chunk_words; /* init chunk size in words */
+    uint32_t init_pace_us; /* init delay pacing, in us */
+    bool ifetch; /* only used when no otp_ctrl is defined */
+    bool noinit; /* discard initialization emulation feature */
+    bool noswitch; /* do not switch to performance/host RAM after init */
+};
+
+struct OtSramCtrlClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+#ifdef OT_SRAM_CTRL_DEBUG
+#define OT_SRAM_CTRL_HEXSTR_SIZE 256u
+#define TRACE_SRAM_CTRL(msg, ...) \
+    qemu_log("%s: " msg "\n", __func__, ##__VA_ARGS__);
+#define ot_sram_ctrl_hexdump(_s_, _b_, _l_) \
+    ot_common_lhexdump((const uint8_t *)_b_, _l_, false, (_s_)->hexstr, \
+                       OT_SRAM_CTRL_HEXSTR_SIZE)
+#else
+#define TRACE_SRAM_CTRL(msg, ...)
+#define ot_sram_ctrl_hexdump(_s_, _b_, _l_)
+#endif
+
+static inline unsigned ot_sram_ctrl_get_u64_slot(unsigned idx)
+{
+    return idx >> 6; /* init_sram_bm is 64 bit wide */
+}
+
+static inline unsigned ot_sram_ctrl_get_u64_offset(unsigned idx)
+{
+    return idx & ((1u << 6u) - 1u); /* init_sram_bm is 64 bit wide */
+}
+
+static inline size_t ot_sram_ctrl_get_slot_count(size_t wsize)
+{
+    return ot_sram_ctrl_get_u64_slot(wsize);
+}
+
+static void ot_sram_ctrl_mem_switch_to_ram(OtSramCtrlState *s)
+{
+    memory_region_transaction_begin();
+    memory_region_set_enabled(&s->mem->init, false);
+    memory_region_set_enabled(&s->mem->sram, true);
+    s->mem->alias.alias = &s->mem->sram;
+    memory_region_transaction_commit();
+    memory_region_set_dirty(&s->mem->sram, 0, s->size);
+
+    trace_ot_sram_ctrl_switch_mem(s->ot_id, "ram");
+}
+
+static bool ot_sram_ctrl_mem_is_fully_initialized(const OtSramCtrlState *s)
+{
+    for (unsigned ix = 0; ix < s->init_slot_count; ix++) {
+        if (s->init_slot_bm[ix]) {
+            trace_ot_sram_ctrl_mem_not_initialized(s->ot_id, ix,
+                                                   s->init_slot_bm[ix]);
+            return false;
+        }
+    }
+
+    return true;
+}
+
+static bool ot_sram_ctrl_initialize(OtSramCtrlState *s, unsigned count,
+                                    bool expedite)
+{
+    unsigned end = s->init_slot_pos + count;
+
+    g_assert(end <= s->wsize);
+
+    trace_ot_sram_ctrl_initialize(s->ot_id, s->init_slot_pos * sizeof(uint32_t),
+                                  end * sizeof(uint32_t), count, expedite);
+
+    uint32_t *mem = memory_region_get_ram_ptr(&s->mem->sram);
+    mem += s->init_slot_pos;
+
+    ot_prng_random_u32_array(s->prng, mem, count);
+
+    memory_region_set_dirty(&s->mem->sram, s->init_slot_pos * sizeof(uint32_t),
+                            count * sizeof(uint32_t));
+
+    s->init_slot_pos = end;
+
+    if (s->init_slot_pos >= s->wsize) {
+        /* init has been completed */
+        s->regs[R_STATUS] |= R_STATUS_INIT_DONE_MASK;
+        /* enable new request for initialization */
+        s->regs[R_CTRL] &= ~R_CTRL_INIT_MASK;
+
+        s->initializing = false;
+        s->initialized = true; /* never reset */
+
+        /* clear out all dirty cell bitmaps */
+        size_t cell_slot_count = ot_sram_ctrl_get_slot_count(s->wsize);
+        memset(s->init_sram_bm, 0, cell_slot_count * sizeof(uint64_t));
+        memset(s->init_slot_bm, 0, s->init_slot_count * sizeof(uint64_t));
+
+        s->init_slot_bm = g_new0(uint64_t, s->init_slot_count);
+
+        if (!s->noswitch) {
+            /* switch memory to SRAM */
+            trace_ot_sram_ctrl_initialization_complete(s->ot_id, "ctrl");
+            ot_sram_ctrl_mem_switch_to_ram(s);
+        } else {
+            trace_ot_sram_ctrl_initialization_complete(s->ot_id,
+                                                       "ctrl/noswitch");
+        }
+
+        return true;
+    }
+
+    trace_ot_sram_ctrl_schedule_init(s->ot_id);
+
+    /* schedule a new initialization chunk */
+    int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+    timer_mod(s->init_timer, now + ((int64_t)s->init_pace_us) * 1000u);
+
+    return false;
+}
+
+static void ot_sram_ctrl_reseed(OtSramCtrlState *s)
+{
+    s->regs[R_STATUS] &=
+        ~(R_STATUS_SCR_KEY_VALID_MASK | R_STATUS_SCR_KEY_SEED_VALID_MASK);
+
+    if (!s->otp_ctrl) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s RESEED w/o OTP: stall bus\n",
+                      __func__, s->ot_id);
+        /* never returns, to simulate the bus stall */
+        for (;;) {
+            sleep(1);
+        }
+    }
+
+    trace_ot_sram_ctrl_reseed(s->ot_id);
+
+    /*
+     * Note: in order to keep the implementation simple, the full OT HW behavior
+     *       is not reproduced here (with CPU cycle delays to get the key, etc.)
+     *       Tke key retrieval is therefore synchronous, which does not
+     *       precisely emulate the HW.
+     *       Moreover the scrambling is highly simplified, as for now there is
+     *       neither PRINCE block cipher nor shallow substitution-permutation.
+     *       Seed and Nonce are combined to initialize a QEMU PRNG instance.
+     */
+    OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+    OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+
+    if (!oc->get_otp_key) {
+        /* on EarlGrey, OTP key handing has not been implemented */
+        qemu_log_mask(LOG_UNIMP, "%s: %s OTP does not support key generation\n",
+                      __func__, s->ot_id);
+    } else {
+        oc->get_otp_key(oi, OT_OTP_KEY_SRAM, s->otp_key);
+
+        TRACE_SRAM_CTRL("Scrambing seed:  %s (valid: %u)",
+                        ot_sram_ctrl_hexdump(s, s->otp_key->seed,
+                                             s->otp_key->seed_size),
+                        s->otp_key->seed_valid);
+        TRACE_SRAM_CTRL("Scrambing nonce: %s",
+                        ot_sram_ctrl_hexdump(s, s->otp_key->nonce,
+                                             s->otp_key->nonce_size));
+
+        if (s->otp_key->seed_valid) {
+            s->regs[R_STATUS] |= R_STATUS_SCR_KEY_SEED_VALID_MASK;
+        }
+
+        trace_ot_sram_ctrl_seed_status(s->ot_id, s->otp_key->seed_valid);
+
+        g_assert(s->otp_key->seed_size <= OT_OTP_SEED_MAX_SIZE);
+        g_assert(s->otp_key->nonce_size <= OT_OTP_NONCE_MAX_SIZE);
+        uint32_t buffer[(OT_OTP_SEED_MAX_SIZE + OT_OTP_NONCE_MAX_SIZE) /
+                        sizeof(uint32_t)];
+        uint8_t *buf = (uint8_t *)&buffer[0];
+        memcpy(buf, s->otp_key->seed, s->otp_key->seed_size);
+        memcpy(&buf[s->otp_key->seed_size], s->otp_key->nonce,
+               s->otp_key->nonce_size);
+        ot_prng_reseed_array(s->prng, buffer,
+                             (s->otp_key->seed_size + s->otp_key->nonce_size) /
+                                 sizeof(uint32_t));
+    }
+
+    s->regs[R_CTRL] &= ~R_CTRL_RENEW_SCR_KEY_MASK;
+    s->regs[R_STATUS] |= R_STATUS_SCR_KEY_VALID_MASK;
+}
+
+static void ot_sram_ctrl_start_initialization(OtSramCtrlState *s)
+{
+    timer_del(s->init_timer);
+
+    s->regs[R_STATUS] &= ~R_STATUS_INIT_DONE_MASK;
+
+    s->initializing = true;
+
+    trace_ot_sram_ctrl_request_hw_init(s->ot_id);
+
+    if (s->mem->alias.alias != &s->mem->init) {
+        memory_region_transaction_begin();
+        memory_region_set_enabled(&s->mem->init, true);
+        memory_region_set_enabled(&s->mem->sram, false);
+        s->mem->alias.alias = &s->mem->init;
+        memory_region_transaction_commit();
+    }
+
+    s->init_slot_pos = 0;
+
+    unsigned count = MIN(s->wsize, s->init_chunk_words);
+
+    ot_sram_ctrl_initialize(s, count, false);
+}
+
+static void ot_sram_ctrl_lc_signal(void *opaque, int irq, int level)
+{
+    OtSramCtrlState *s = opaque;
+
+    g_assert(irq == 0);
+
+    trace_ot_sram_ctrl_lc_signal(s->ot_id, level);
+
+    s->lc_hw_debug_ifetch = (bool)level;
+}
+
+static void ot_sram_ctrl_update_exec(OtSramCtrlState *s)
+{
+    /*
+     * OTP content is not known on reset, as OTP initialization is delayed.
+     * Configuration need to be loaded on demand
+     */
+    if (s->otp_ctrl) {
+        OtOTPIfClass *oc = OT_OTP_IF_GET_CLASS(s->otp_ctrl);
+        OtOTPIf *oi = OT_OTP_IF(s->otp_ctrl);
+        s->otp_ifetch =
+            oc->get_hw_cfg(oi)->en_sram_ifetch_mb8 == OT_MULTIBITBOOL8_TRUE;
+    }
+
+    bool ifetch = s->otp_ifetch ? s->csr_ifetch : s->lc_hw_debug_ifetch;
+    ifetch = ifetch && s->ifetch; /* ifetch config disable */
+
+    trace_ot_sram_ctrl_update_exec(s->ot_id, s->ifetch, s->csr_ifetch,
+                                   s->otp_ifetch, s->lc_hw_debug_ifetch,
+                                   ifetch);
+
+    if (!s->vmapper) {
+        if (!ifetch) {
+            trace_ot_sram_ctrl_ifetch_warning(s->ot_id);
+        }
+
+        /* for now, vmapper is not a mandatory feature */
+        return;
+    }
+
+    const MemoryRegion *mr = s->noinit ? &s->mem->sram : &s->mem->alias;
+
+    OtVMapperClass *vm = OT_VMAPPER_GET_CLASS(s->vmapper);
+    vm->disable_exec(s->vmapper, mr, !ifetch);
+}
+
+static uint64_t ot_sram_ctrl_regs_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtSramCtrlState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+
+    switch (reg) {
+    case R_STATUS:
+    case R_EXEC_REGWEN:
+    case R_EXEC:
+    case R_CTRL_REGWEN:
+    case R_CTRL:
+    case R_SCR_KEY_ROTATED:
+    case R_READBACK_REGWEN:
+    case R_READBACK:
+        val32 = s->regs[reg];
+        break;
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s W/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_sram_ctrl_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg),
+                                   val32, pc);
+
+    return (uint64_t)val32;
+};
+
+static void ot_sram_ctrl_regs_write(void *opaque, hwaddr addr, uint64_t val64,
+                                    unsigned size)
+{
+    OtSramCtrlState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_sram_ctrl_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                                pc);
+
+    switch (reg) {
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_ERROR_MASK;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    case R_EXEC_REGWEN:
+        val32 &= R_EXEC_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_EXEC:
+        if (!s->regs[R_EXEC_REGWEN]) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s R_EXEC protected w/ REGWEN\n", __func__,
+                          s->ot_id);
+            break;
+        }
+        val32 &= R_EXEC_EN_MASK;
+        s->regs[reg] = val32;
+        s->csr_ifetch = (s->regs[reg] == OT_MULTIBITBOOL4_TRUE);
+        ot_sram_ctrl_update_exec(s);
+        break;
+    case R_CTRL_REGWEN:
+        val32 &= R_CTRL_REGWEN_CTRL_REGWEN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_CTRL:
+        if (s->regs[R_CTRL_REGWEN]) { /* WO */
+            val32 &= R_CTRL_INIT_MASK | R_CTRL_RENEW_SCR_KEY_MASK;
+            uint32_t trig = (val32 ^ s->regs[reg]) & val32;
+            /* storing value prevents from trigerring again before completion */
+            s->regs[reg] = val32;
+            if (trig & R_CTRL_RENEW_SCR_KEY_MASK) {
+                ot_sram_ctrl_reseed(s);
+            }
+            if (trig & R_CTRL_INIT_MASK) {
+                if (s->noinit) {
+                    qemu_log_mask(LOG_GUEST_ERROR,
+                                  "%s: %s initialization support disabled\n",
+                                  __func__, s->ot_id);
+                } else {
+                    ot_sram_ctrl_start_initialization(s);
+                }
+            }
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s R_CTRL protected w/ REGWEN\n", __func__,
+                          s->ot_id);
+        }
+        break;
+    case R_SCR_KEY_ROTATED:
+        /* this register has been deprecated on Darjeeling */
+        qemu_log_mask(LOG_UNIMP, "%s: %s R_SCR_KEY_ROTATED\n", __func__,
+                      s->ot_id);
+        break;
+    case R_READBACK_REGWEN:
+        val32 &= R_READBACK_REGWEN_EN_MASK;
+        s->regs[reg] &= val32; /* RW0C */
+        break;
+    case R_READBACK:
+        if (s->regs[R_READBACK_REGWEN]) {
+            val32 &= R_READBACK_EN_MASK;
+            s->regs[reg] = val32;
+            /* readback feature is a no-op in QEMU */
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s R_READBACK_REGWEN protected w/ REGWEN\n",
+                          __func__, s->ot_id);
+        }
+        break;
+    case R_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s R/O register 0x%02x (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+};
+
+static void ot_sram_ctrl_init_chunk_fn(void *opaque)
+{
+    OtSramCtrlState *s = opaque;
+
+    unsigned count = s->wsize - s->init_slot_pos;
+    count = MIN(count, s->init_chunk_words);
+
+    (void)ot_sram_ctrl_initialize(s, count, false);
+}
+
+static MemTxResult ot_sram_ctrl_mem_init_read_with_attrs(
+    void *opaque, hwaddr addr, uint64_t *val64, unsigned size, MemTxAttrs attrs)
+{
+    OtSramCtrlState *s = opaque;
+    (void)size;
+    (void)attrs;
+
+    uint32_t pc = ibex_get_current_pc();
+
+    unsigned cell = addr >> 2u;
+    unsigned addr_offset = (addr & 3u);
+    g_assert(addr_offset + size <= 4u);
+
+    if (s->initializing) {
+        /*
+         * SRAM is being initialized. Should to release bus access till init has
+         * been completed. There is no direct way to implement this with QEMU.
+         * Instead, complete the initialization immediately so that this
+         * function only returns when init is over
+         */
+        trace_ot_sram_ctrl_expediate_init(s->ot_id, "read");
+
+        timer_del(s->init_timer);
+        unsigned count = s->wsize - s->init_slot_pos;
+        /* this function also take care of scheduling memory region swap */
+        bool done = ot_sram_ctrl_initialize(s, count, true);
+        g_assert(done);
+    }
+
+    if (!s->initialized) {
+        /*
+         * the whole RAM is not fully initialized, check if this cell has been
+         * initialized
+         */
+        unsigned slot = ot_sram_ctrl_get_u64_slot(cell);
+        unsigned offset = ot_sram_ctrl_get_u64_offset(cell);
+
+        if (s->init_sram_bm[slot] & (1ull << offset)) {
+            /* cell still flagged, i.e. not yet initialized */
+            qemu_log_mask(
+                LOG_GUEST_ERROR,
+                "%s: %s: attempt to read from uninitialized cell @ 0x%06x\n",
+                __func__, s->ot_id, (uint32_t)addr);
+
+            return MEMTX_ERROR;
+        }
+    }
+
+    /* retrieve the value from the final SRAM region */
+    uint32_t *mem = memory_region_get_ram_ptr(&s->mem->sram);
+    uint32_t val32 = mem[cell];
+    val32 >>= addr_offset << 3u;
+    *val64 = (uint64_t)val32;
+
+    trace_ot_sram_ctrl_mem_io_reado(s->ot_id, (uint32_t)addr, size, val32, pc);
+
+    return MEMTX_OK;
+}
+
+static MemTxResult ot_sram_ctrl_mem_init_write_with_attrs(
+    void *opaque, hwaddr addr, uint64_t val64, unsigned size, MemTxAttrs attrs)
+{
+    OtSramCtrlState *s = opaque;
+    (void)attrs;
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_sram_ctrl_mem_io_write(s->ot_id, (uint32_t)addr, size,
+                                    (uint32_t)val64, pc);
+
+    unsigned cell = addr >> 2u;
+    unsigned addr_offset = (addr & 3u);
+    g_assert(addr_offset + size <= 4u);
+
+    bool skip_bm_update = s->initializing;
+
+    if (s->initializing) {
+        /*
+         * SRAM is being initialized. Should to release bus access till init has
+         * been completed. There is no direct way to implement this with QEMU.
+         * Instead, complete the initialization immediately so that this
+         * function only returns when init is over
+         */
+        trace_ot_sram_ctrl_expediate_init(s->ot_id, "write");
+
+        timer_del(s->init_timer);
+        unsigned count = s->wsize - s->init_slot_pos;
+        /* this function also take care of scheduling memory region swap */
+        bool done = ot_sram_ctrl_initialize(s, count, true);
+        g_assert(done);
+    }
+
+    /* store the value into the final SRAM region */
+    uint32_t *mem = memory_region_get_ram_ptr(&s->mem->sram);
+
+    addr_offset <<= 3u; /* byte to bit */
+
+    uint32_t mask = (uint32_t)((1ull << (size << 3u)) - 1u);
+    uint32_t nval = (((uint32_t)val64) & mask) << addr_offset;
+    uint32_t word = mem[cell];
+    word &= ~(mask << addr_offset);
+    word |= nval;
+    mem[cell] = word;
+
+    if (skip_bm_update) {
+        return MEMTX_OK;
+    }
+
+    unsigned idx = addr / sizeof(uint32_t);
+    unsigned slot = ot_sram_ctrl_get_u64_slot(idx);
+    unsigned offset = ot_sram_ctrl_get_u64_offset(idx);
+
+    s->init_sram_bm[slot] &= ~(1ull << offset);
+
+    if (!s->init_sram_bm[slot]) {
+        offset = ot_sram_ctrl_get_u64_offset(slot);
+        slot = ot_sram_ctrl_get_u64_slot(slot);
+        s->init_slot_bm[slot] &= ~(1ull << offset);
+
+        if (!s->init_slot_bm[slot]) {
+            if (ot_sram_ctrl_mem_is_fully_initialized(s)) {
+                if (!s->noswitch) {
+                    /*
+                     * perform the memory switch in a BH so that the current mr
+                     * is not in use when switching
+                     */
+                    trace_ot_sram_ctrl_initialization_complete(s->ot_id,
+                                                               "write");
+
+                    ot_sram_ctrl_mem_switch_to_ram(s);
+                } else {
+                    if (!s->initialized) {
+                        trace_ot_sram_ctrl_initialization_complete(
+                            s->ot_id, "write/noswitch");
+                    }
+                }
+                s->initialized = true;
+            }
+        }
+    }
+
+    return MEMTX_OK;
+}
+
+static const Property ot_sram_ctrl_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtSramCtrlState, ot_id),
+    DEFINE_PROP_LINK("otp-ctrl", OtSramCtrlState, otp_ctrl, TYPE_OT_OTP_IF,
+                     DeviceState *),
+    DEFINE_PROP_LINK("vmapper", OtSramCtrlState, vmapper, TYPE_OT_VMAPPER,
+                     OtVMapperState *),
+    DEFINE_PROP_UINT32("size", OtSramCtrlState, size, 0u),
+    DEFINE_PROP_UINT32("wci_size", OtSramCtrlState, init_chunk_words, 0u),
+    DEFINE_PROP_UINT32("init-pace-us", OtSramCtrlState, init_pace_us,
+                       INIT_TIMER_CHUNK_US),
+    DEFINE_PROP_BOOL("ifetch", OtSramCtrlState, ifetch, false),
+    DEFINE_PROP_BOOL("noinit", OtSramCtrlState, noinit, false),
+    DEFINE_PROP_BOOL("noswitch", OtSramCtrlState, noswitch, false),
+};
+
+static const MemoryRegionOps ot_sram_ctrl_regs_ops = {
+    .read = &ot_sram_ctrl_regs_read,
+    .write = &ot_sram_ctrl_regs_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const MemoryRegionOps ot_sram_ctrl_mem_init_ops = {
+    .read_with_attrs = &ot_sram_ctrl_mem_init_read_with_attrs,
+    .write_with_attrs = &ot_sram_ctrl_mem_init_write_with_attrs,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 1u,
+    .impl.max_access_size = 4u,
+};
+
+static void ot_sram_ctrl_reset_enter(Object *obj, ResetType type)
+{
+    OtSramCtrlClass *c = OT_SRAM_CTRL_GET_CLASS(obj);
+    OtSramCtrlState *s = OT_SRAM_CTRL(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->init_timer);
+
+    memset(s->regs, 0, REGS_SIZE);
+
+    /* note: SRAM storage is -not- reset */
+
+    s->regs[R_EXEC_REGWEN] = 0x1u;
+    s->regs[R_EXEC] = OT_MULTIBITBOOL4_FALSE;
+    s->regs[R_CTRL_REGWEN] = 0x1u;
+    s->regs[R_SCR_KEY_ROTATED] = OT_MULTIBITBOOL4_FALSE;
+    s->regs[R_READBACK_REGWEN] = 0x1u;
+    s->regs[R_READBACK] = OT_MULTIBITBOOL4_FALSE;
+
+    ibex_irq_set(&s->alert, (int)(bool)s->regs[R_ALERT_TEST]);
+}
+
+static void ot_sram_ctrl_reset_exit(Object *obj, ResetType type)
+{
+    OtSramCtrlClass *c = OT_SRAM_CTRL_GET_CLASS(obj);
+    OtSramCtrlState *s = OT_SRAM_CTRL(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    int64_t now = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
+    ot_prng_reseed(s->prng, (uint32_t)now);
+
+    s->otp_ifetch = (s->otp_ctrl == NULL);
+    s->csr_ifetch = (s->regs[R_EXEC] == OT_MULTIBITBOOL4_TRUE);
+
+    ot_sram_ctrl_update_exec(s);
+}
+
+static void ot_sram_ctrl_realize(DeviceState *dev, Error **errp)
+{
+    OtSramCtrlState *s = OT_SRAM_CTRL(dev);
+
+    g_assert(s->ot_id);
+    g_assert(s->size);
+
+    /*
+     * for now, vmapper is optional if ifetch is enabled and there's no
+     * associated OTP
+     */
+    g_assert(s->ifetch || !s->otp_ctrl || s->vmapper);
+
+    (void)OBJECT_CHECK(OtOTPIf, s->otp_ctrl, TYPE_OT_OTP_IF);
+
+    s->wsize = DIV_ROUND_UP(s->size, sizeof(uint32_t));
+    unsigned size = s->wsize * sizeof(uint32_t);
+
+    if (!s->init_chunk_words) {
+        /* somewhat arbitrary */
+        s->init_chunk_words = MAX(s->wsize / 16u, INIT_TIMER_CHUNK_WORDS);
+    } else {
+        g_assert(s->init_chunk_words < s->wsize);
+    }
+
+    char *mr_name;
+
+    if (s->noinit) {
+        /*
+         * when initialization feature is disabled, simply map the final memory
+         * region as the memory backend. Init-related arrays are left
+         * uninitialized and should not be used.
+         */
+        mr_name = g_strdup_printf(TYPE_OT_SRAM_CTRL ".%s.mem", s->ot_id);
+        memory_region_init_ram_nomigrate(&s->mem->sram, OBJECT(dev), mr_name,
+                                         size, errp);
+        sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mem->sram);
+        g_free(mr_name);
+        return;
+    }
+
+    /*
+     * Use two 64-bit bitmap array to track which SRAM address have been
+     * initialized. Only consider 32-bit memory slots (which differ from HW,
+     * but should be sufficient to track common initialization): any write to
+     * a single byte of a 4-byte memory cell is considered as if the whole
+     * cell has been updated. Each 4-byte memory cell is tracked with a single
+     * bit in the init_sram_bm bitmap array, where 1 means unitialized, i.e.
+     * a fully zeroed array means that all cells have been written at least
+     * once.
+     * To avoid looping on too large arrays, use a seconday 64-bit bitmap array,
+     * namely init_slot_bm, where each bit entry tracks a 64-bit slot of the
+     * init_sram_bm array. Same logic applies for this array: once all bits are
+     * cleared, all memory cells have been written at least once.
+     * On such a condition, switch the I/O mapped memory to a RAM memory to
+     * avoid performance bottleneck - which is used when accessing I/O rather
+     * than host-backed memory.
+     */
+    size_t cell_slot_count = ot_sram_ctrl_get_slot_count(s->wsize);
+    s->init_sram_bm = g_new0(uint64_t, cell_slot_count);
+    memset(s->init_sram_bm, 0xff, cell_slot_count * sizeof(uint64_t));
+
+    s->init_slot_count = ot_sram_ctrl_get_u64_slot(cell_slot_count + 64u - 1u);
+    s->init_slot_bm = g_new0(uint64_t, s->init_slot_count);
+    memset(s->init_slot_bm, 0xff, s->init_slot_count * sizeof(uint64_t));
+    unsigned slot_offset = ot_sram_ctrl_get_u64_offset(cell_slot_count);
+    if (slot_offset) {
+        s->init_slot_bm[s->init_slot_count - 1u] = (1ull << slot_offset) - 1u;
+    }
+
+    mr_name = g_strdup_printf(TYPE_OT_SRAM_CTRL ".%s.mem.init", s->ot_id);
+    memory_region_init_io(&s->mem->init, OBJECT(dev),
+                          &ot_sram_ctrl_mem_init_ops, s, mr_name, size);
+    g_free(mr_name);
+    mr_name = g_strdup_printf(TYPE_OT_SRAM_CTRL ".%s.mem.sram", s->ot_id);
+    memory_region_init_ram_nomigrate(&s->mem->sram, OBJECT(dev), mr_name, size,
+                                     errp);
+    g_free(mr_name);
+
+    /*
+     * use an alias than points to the currently selected RAM backend, either
+     * I/O for controlling access but really slow or host RAM backend for speed
+     * but no fined-grained control, rather than directly swapping sysbus device
+     * MMIO entry on initialization status changes. The alias enables decoupling
+     * the internal implementation from the SRAM "clients" that may hold a
+     * reference of the SRAM memory region, and may not signalled when the
+     * backend is swapped. The alias enables to expose the same MemoryRegion
+     * object while changing its actual backend on initialization demand.
+     */
+    mr_name = g_strdup_printf(TYPE_OT_SRAM_CTRL ".%s.mem", s->ot_id);
+    memory_region_init_alias(&s->mem->alias, OBJECT(dev), mr_name,
+                             &s->mem->init, 0, size);
+    g_free(mr_name);
+
+    /*
+     * at start up, the SRAM memory is aliased to the I/O backend, so that
+     * access can be controlled
+     */
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mem->alias);
+}
+
+static void ot_sram_ctrl_init(Object *obj)
+{
+    OtSramCtrlState *s = OT_SRAM_CTRL(obj);
+
+    memory_region_init_io(&s->mmio, obj, &ot_sram_ctrl_regs_ops, s,
+                          TYPE_OT_SRAM_CTRL ".regs", REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_sram_ctrl_lc_signal,
+                            OT_SRAM_CTRL_HW_DEBUG_EN, 1);
+
+    s->mem = g_new0(OtSramCtrlMem, 1u);
+    s->init_timer =
+        timer_new_ns(OT_VIRTUAL_CLOCK, &ot_sram_ctrl_init_chunk_fn, s);
+    s->prng = ot_prng_allocate();
+    s->otp_key = g_new0(OtOTPKey, 1u);
+
+#ifdef OT_SRAM_CTRL_DEBUG
+    s->hexstr = g_new0(char, OT_SRAM_CTRL_HEXSTR_SIZE);
+#endif
+}
+
+static void ot_sram_ctrl_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_sram_ctrl_realize;
+    device_class_set_props(dc, ot_sram_ctrl_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtSramCtrlClass *sc = OT_SRAM_CTRL_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_sram_ctrl_reset_enter, NULL,
+                                       &ot_sram_ctrl_reset_exit,
+                                       &sc->parent_phases);
+}
+
+static const TypeInfo ot_sram_ctrl_info = {
+    .name = TYPE_OT_SRAM_CTRL,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtSramCtrlState),
+    .instance_init = &ot_sram_ctrl_init,
+    .class_size = sizeof(OtSramCtrlClass),
+    .class_init = &ot_sram_ctrl_class_init,
+};
+
+static void ot_sram_ctrl_register_types(void)
+{
+    type_register_static(&ot_sram_ctrl_info);
+}
+
+type_init(ot_sram_ctrl_register_types);
diff --git a/hw/opentitan/ot_timer.c b/hw/opentitan/ot_timer.c
new file mode 100644
index 0000000000000..9f4d783beb763
--- /dev/null
+++ b/hw/opentitan/ot_timer.c
@@ -0,0 +1,481 @@
+/*
+ * QEMU OpenTitan Timer device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "qapi/error.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_timer.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(ALERT_TEST, 0x00u)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(CTRL, 0x04u)
+    FIELD(CTRL, ACTIVE0, 0u, 1u)
+REG32(INTR_ENABLE0, 0x100u)
+    SHARED_FIELD(INTR_CMP0, 0u, 1u)
+REG32(INTR_STATE0, 0x104u)
+REG32(INTR_TEST0, 0x108u)
+REG32(CFG0, 0x10cu)
+    FIELD(CFG0, PRESCALE, 0u, 12u)
+    FIELD(CFG0, STEP, 16u, 8u)
+REG32(TIMER_V_LOWER0, 0x110u)
+REG32(TIMER_V_UPPER0, 0x114u)
+REG32(COMPARE_LOWER0_0, 0x118u)
+REG32(COMPARE_UPPER0_0, 0x11cu)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_COMPARE_UPPER0_0)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CTRL),
+    REG_NAME_ENTRY(INTR_ENABLE0),
+    REG_NAME_ENTRY(INTR_STATE0),
+    REG_NAME_ENTRY(INTR_TEST0),
+    REG_NAME_ENTRY(CFG0),
+    REG_NAME_ENTRY(TIMER_V_LOWER0),
+    REG_NAME_ENTRY(TIMER_V_UPPER0),
+    REG_NAME_ENTRY(COMPARE_LOWER0_0),
+    REG_NAME_ENTRY(COMPARE_UPPER0_0),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+struct OtTimerState {
+    SysBusDevice parent_obj;
+    MemoryRegion mmio;
+    IbexIRQ m_timer_irq;
+    IbexIRQ irq;
+    IbexIRQ alert;
+    QEMUTimer *timer;
+
+    uint32_t regs[REGS_COUNT];
+    int64_t origin_ns;
+    uint32_t pclk; /* Current input clock */
+    const char *clock_src_name; /* IRQ name once connected */
+
+    char *ot_id;
+    char *clock_name;
+    DeviceState *clock_src;
+};
+
+struct OtTimerClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static uint64_t ot_timer_ns_to_ticks(OtTimerState *s, int64_t ns)
+{
+    uint32_t prescaler = FIELD_EX32(s->regs[R_CFG0], CFG0, PRESCALE);
+    uint64_t ticks = muldiv64((uint64_t)ns, s->pclk, NANOSECONDS_PER_SECOND);
+    uint64_t step = FIELD_EX32(s->regs[R_CFG0], CFG0, STEP);
+    return (ticks / (prescaler + 1u)) * step;
+}
+
+static int64_t ot_timer_ticks_to_ns(OtTimerState *s, uint64_t ticks)
+{
+    g_assert(s->pclk);
+
+    uint32_t prescaler = FIELD_EX32(s->regs[R_CFG0], CFG0, PRESCALE);
+    uint32_t step = FIELD_EX32(s->regs[R_CFG0], CFG0, STEP);
+    uint64_t ns = muldiv64(ticks, (prescaler + 1u), step);
+    ns = muldiv64(ns, NANOSECONDS_PER_SECOND, s->pclk);
+    if (ns > INT64_MAX) {
+        return INT64_MAX;
+    }
+
+    return (int64_t)ns;
+}
+
+static uint64_t ot_timer_get_mtime(OtTimerState *s, int64_t now)
+{
+    uint64_t mtime = s->regs[R_TIMER_V_LOWER0] |
+                     ((uint64_t)s->regs[R_TIMER_V_UPPER0] << 32u);
+    return mtime + ot_timer_ns_to_ticks(s, now - s->origin_ns);
+}
+
+static int64_t
+ot_timer_compute_next_timeout(OtTimerState *s, int64_t now, int64_t delta)
+{
+    int64_t next;
+
+    g_assert(s->pclk);
+
+    /* wait at least 1 peripheral clock tick */
+    delta = MAX(delta, (int64_t)(NANOSECONDS_PER_SECOND / s->pclk));
+
+    if (sadd64_overflow(now, delta, &next)) {
+        /* we overflowed the timer, just set it as large as we can */
+        return INT64_MAX;
+    }
+
+    return next;
+}
+
+static inline bool ot_timer_is_active(OtTimerState *s)
+{
+    return s->regs[R_CTRL] & R_CTRL_ACTIVE0_MASK;
+}
+
+static void ot_timer_update_alert(OtTimerState *s)
+{
+    bool level = (bool)(s->regs[R_ALERT_TEST] & R_ALERT_TEST_FATAL_FAULT_MASK);
+    ibex_irq_set(&s->alert, level);
+}
+
+static void ot_timer_update_irqs(OtTimerState *s)
+{
+    bool level =
+        s->regs[R_INTR_STATE0] & s->regs[R_INTR_ENABLE0] & INTR_CMP0_MASK;
+    if (level != (bool)ibex_irq_get_level(&s->m_timer_irq)) {
+        trace_ot_timer_update_irq(s->ot_id, level);
+    }
+    ibex_irq_set(&s->m_timer_irq, level);
+    ibex_irq_set(&s->irq, level);
+}
+
+static void ot_timer_rearm(OtTimerState *s, bool reset_origin)
+{
+    timer_del(s->timer);
+
+    if (!s->pclk) {
+        return;
+    }
+
+    int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+
+    if (reset_origin) {
+        s->origin_ns = now;
+    }
+
+    uint32_t step = FIELD_EX32(s->regs[R_CFG0], CFG0, STEP);
+    if (!ot_timer_is_active(s) || !step) {
+        return;
+    }
+
+    uint64_t mtime = ot_timer_get_mtime(s, now);
+    uint64_t mtimecmp = s->regs[R_COMPARE_LOWER0_0] |
+                        ((uint64_t)s->regs[R_COMPARE_UPPER0_0] << 32u);
+
+    if (mtime >= mtimecmp) {
+        s->regs[R_INTR_STATE0] |= INTR_CMP0_MASK;
+    } else {
+        int64_t delta = ot_timer_ticks_to_ns(s, mtimecmp - mtime);
+        int64_t next = ot_timer_compute_next_timeout(s, now, delta);
+        if (next < INT64_MAX) {
+            trace_ot_timer_timer_mod(s->ot_id, now, next, false);
+            timer_mod(s->timer, next);
+        }
+    }
+
+    ot_timer_update_irqs(s);
+}
+
+static void ot_timer_cb(void *opaque)
+{
+    OtTimerState *s = opaque;
+    ot_timer_rearm(s, false);
+}
+
+static void ot_timer_clock_input(void *opaque, int irq, int level)
+{
+    OtTimerState *s = opaque;
+
+    g_assert(irq == 0);
+
+    s->pclk = (unsigned)level;
+
+    if (!s->pclk) {
+        timer_del(s->timer);
+    }
+
+    trace_ot_timer_update_clock(s->ot_id, s->pclk);
+    /* TODO: @loic: update on-going timer */
+}
+
+static uint64_t ot_timer_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtTimerState *s = opaque;
+    (void)size;
+    uint32_t val32 = 0;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_CTRL:
+    case R_INTR_ENABLE0:
+    case R_INTR_STATE0:
+    case R_CFG0:
+    case R_COMPARE_LOWER0_0:
+    case R_COMPARE_UPPER0_0:
+        val32 = s->regs[reg];
+        break;
+    case R_TIMER_V_LOWER0: {
+        int64_t now = ot_timer_is_active(s) ?
+                          qemu_clock_get_ns(OT_VIRTUAL_CLOCK) :
+                          s->origin_ns;
+        val32 = ot_timer_get_mtime(s, now);
+        break;
+    }
+    case R_TIMER_V_UPPER0: {
+        int64_t now = ot_timer_is_active(s) ?
+                          qemu_clock_get_ns(OT_VIRTUAL_CLOCK) :
+                          s->origin_ns;
+        val32 = ot_timer_get_mtime(s, now) >> 32u;
+        break;
+    }
+    case R_ALERT_TEST:
+    case R_INTR_TEST0:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%03x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_timer_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                               pc);
+
+    return (uint32_t)val32;
+}
+
+static void ot_timer_write(void *opaque, hwaddr addr, uint64_t value,
+                           unsigned size)
+{
+    OtTimerState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)value;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_timer_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        s->regs[reg] = val32;
+        ot_timer_update_alert(s);
+        break;
+    case R_CTRL: {
+        uint32_t prev = s->regs[R_CTRL];
+        s->regs[R_CTRL] = val32 & R_CTRL_ACTIVE0_MASK;
+        uint32_t change = prev ^ s->regs[R_CTRL];
+        if (change & R_CTRL_ACTIVE0_MASK) {
+            if (ot_timer_is_active(s)) {
+                /* start timer */
+                ot_timer_rearm(s, true);
+            } else {
+                /* stop timer */
+                timer_del(s->timer);
+                /* save current mtime */
+                int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+                uint64_t mtime = ot_timer_get_mtime(s, now);
+                s->regs[R_TIMER_V_LOWER0] = (uint32_t)mtime;
+                s->regs[R_TIMER_V_UPPER0] = (uint32_t)(mtime >> 32u);
+                s->origin_ns = now;
+            }
+        }
+        break;
+    }
+    case R_INTR_ENABLE0:
+        s->regs[R_INTR_ENABLE0] = val32 & INTR_CMP0_MASK;
+        ot_timer_update_irqs(s);
+        break;
+    case R_INTR_STATE0: {
+        s->regs[R_INTR_STATE0] &= ~(val32 & INTR_CMP0_MASK);
+        ot_timer_update_irqs(s);
+        /*
+         * schedule the timer for the next peripheral clock tick to check again
+         * for interrupt condition
+         */
+        if (s->pclk) {
+            int64_t now = qemu_clock_get_ns(OT_VIRTUAL_CLOCK);
+            int64_t next = ot_timer_compute_next_timeout(s, now, 0);
+            trace_ot_timer_timer_mod(s->ot_id, now, next, true);
+            timer_mod_anticipate(s->timer, next);
+        }
+        break;
+    }
+    case R_INTR_TEST0:
+        s->regs[R_INTR_STATE0] |= val32 & INTR_CMP0_MASK;
+        ot_timer_update_irqs(s);
+        break;
+    case R_CFG0:
+        if (!ot_timer_is_active(s)) {
+            s->regs[R_CFG0] = val32 & (R_CFG0_PRESCALE_MASK | R_CFG0_STEP_MASK);
+        }
+        break;
+    case R_TIMER_V_LOWER0:
+        s->regs[R_TIMER_V_LOWER0] = val32;
+        ot_timer_rearm(s, true);
+        break;
+    case R_TIMER_V_UPPER0:
+        s->regs[R_TIMER_V_UPPER0] = val32;
+        ot_timer_rearm(s, true);
+        break;
+    case R_COMPARE_LOWER0_0:
+        s->regs[R_COMPARE_LOWER0_0] = val32;
+        /* clear IRQ on compare change */
+        s->regs[R_INTR_STATE0] &= ~INTR_CMP0_MASK;
+        ot_timer_rearm(s, false);
+        break;
+    case R_COMPARE_UPPER0_0:
+        s->regs[R_COMPARE_UPPER0_0] = val32;
+        /* clear IRQ on compare change */
+        s->regs[R_INTR_STATE0] &= ~INTR_CMP0_MASK;
+        ot_timer_rearm(s, false);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%03x\n", __func__,
+                      (uint32_t)addr);
+    }
+}
+
+static const MemoryRegionOps ot_timer_ops = {
+    .read = &ot_timer_read,
+    .write = &ot_timer_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4u,
+    .impl.max_access_size = 4u,
+};
+
+static const Property ot_timer_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtTimerState, ot_id),
+    DEFINE_PROP_STRING("clock-name", OtTimerState, clock_name),
+    DEFINE_PROP_LINK("clock-src", OtTimerState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+};
+
+static void ot_timer_reset_enter(Object *obj, ResetType type)
+{
+    OtTimerClass *c = OT_TIMER_GET_CLASS(obj);
+    OtTimerState *s = OT_TIMER(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    timer_del(s->timer);
+
+    memset(s->regs, 0, sizeof(s->regs));
+    s->regs[R_CFG0] = 1u << R_CFG0_STEP_SHIFT;
+    s->regs[R_COMPARE_LOWER0_0] = UINT32_MAX;
+    s->regs[R_COMPARE_UPPER0_0] = UINT32_MAX;
+
+    ot_timer_update_irqs(s);
+    ot_timer_update_alert(s);
+
+    if (!s->clock_src_name) {
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_name =
+            ic->get_clock_source(ii, s->clock_name, DEVICE(s), &error_fatal);
+        qemu_irq in_irq = qdev_get_gpio_in_named(DEVICE(s), "clock-in", 0);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_name, 0, in_irq);
+    }
+}
+
+static void ot_timer_realize(DeviceState *dev, Error **errp)
+{
+    OtTimerState *s = OT_TIMER(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->clock_name);
+    g_assert(s->clock_src);
+    OBJECT_CHECK(IbexClockSrcIf, s->clock_src, TYPE_IBEX_CLOCK_SRC_IF);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_timer_clock_input, "clock-in", 1);
+}
+
+static void ot_timer_init(Object *obj)
+{
+    OtTimerState *s = OT_TIMER(obj);
+
+    ibex_sysbus_init_irq(obj, &s->irq);
+    ibex_qdev_init_irq(obj, &s->m_timer_irq, NULL);
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    memory_region_init_io(&s->mmio, obj, &ot_timer_ops, s, TYPE_OT_TIMER,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    s->timer = timer_new_ns(OT_VIRTUAL_CLOCK, &ot_timer_cb, s);
+}
+
+static void ot_timer_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_timer_realize;
+    device_class_set_props(dc, ot_timer_properties);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtTimerClass *tc = OT_TIMER_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_timer_reset_enter, NULL, NULL,
+                                       &tc->parent_phases);
+}
+
+static const TypeInfo ot_timer_info = {
+    .name = TYPE_OT_TIMER,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtTimerState),
+    .instance_init = &ot_timer_init,
+    .class_size = sizeof(OtTimerClass),
+    .class_init = &ot_timer_class_init,
+};
+
+static void ot_timer_register_types(void)
+{
+    type_register_static(&ot_timer_info);
+}
+
+type_init(ot_timer_register_types);
diff --git a/hw/opentitan/ot_uart.c b/hw/opentitan/ot_uart.c
new file mode 100644
index 0000000000000..cb9d5b67544fe
--- /dev/null
+++ b/hw/opentitan/ot_uart.c
@@ -0,0 +1,781 @@
+/*
+ * QEMU OpenTitan UART device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Based on original ibex_uart implementation:
+ *  Copyright (c) 2020 Western Digital
+ *  Alistair Francis <alistair.francis@wdc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/fifo8.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "chardev/char-fe.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_uart.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+/* clang-format off */
+REG32(INTR_STATE, 0x00u)
+    SHARED_FIELD(INTR_TX_WATERMARK, 0u, 1u)
+    SHARED_FIELD(INTR_RX_WATERMARK, 1u, 1u)
+    SHARED_FIELD(INTR_TX_DONE, 2u, 1u)
+    SHARED_FIELD(INTR_RX_OVERFLOW, 3u, 1u)
+    SHARED_FIELD(INTR_RX_FRAME_ERR, 4u, 1u)
+    SHARED_FIELD(INTR_RX_BREAK_ERR, 5u, 1u)
+    SHARED_FIELD(INTR_RX_TIMEOUT, 6u, 1u)
+    SHARED_FIELD(INTR_RX_PARITY_ERR, 7u, 1u)
+    SHARED_FIELD(INTR_TX_EMPTY, 8u, 1u)
+REG32(INTR_ENABLE, 0x04u)
+REG32(INTR_TEST, 0x08u)
+REG32(ALERT_TEST, 0x0cu)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(CTRL, 0x10u)
+    FIELD(CTRL, TX, 0u, 1u)
+    FIELD(CTRL, RX, 1u, 1u)
+    FIELD(CTRL, NF, 2u, 1u)
+    FIELD(CTRL, SLPBK, 4u, 1u)
+    FIELD(CTRL, LLPBK, 5u, 1u)
+    FIELD(CTRL, PARITY_EN, 6u, 1u)
+    FIELD(CTRL, PARITY_ODD, 7u, 1u)
+    FIELD(CTRL, RXBLVL, 8u, 2u)
+    FIELD(CTRL, NCO, 16u, 16u)
+REG32(STATUS, 0x14u)
+    FIELD(STATUS, TXFULL, 0u, 1u)
+    FIELD(STATUS, RXFULL, 1u, 1u)
+    FIELD(STATUS, TXEMPTY, 2u, 1u)
+    FIELD(STATUS, TXIDLE, 3u, 1u)
+    FIELD(STATUS, RXIDLE, 4u, 1u)
+    FIELD(STATUS, RXEMPTY, 5u, 1u)
+REG32(RDATA, 0x18u)
+    FIELD(RDATA, RDATA, 0u, 8u)
+REG32(WDATA, 0x1cu)
+    FIELD(WDATA, WDATA, 0u, 8u)
+REG32(FIFO_CTRL, 0x20u)
+    FIELD(FIFO_CTRL, RXRST, 0u, 1u)
+    FIELD(FIFO_CTRL, TXRST, 1u, 1u)
+    FIELD(FIFO_CTRL, RXILVL, 2u, 3u)
+    FIELD(FIFO_CTRL, TXILVL, 5u, 3u)
+REG32(FIFO_STATUS, 0x24u)
+    FIELD(FIFO_STATUS, TXLVL, 0u, 8u)
+    FIELD(FIFO_STATUS, RXLVL, 16u, 8u)
+REG32(OVRD, 0x28u)
+    FIELD(OVRD, TXEN, 0u, 1u)
+    FIELD(OVRD, TXVAL, 1u, 1u)
+REG32(VAL, 0x2cu)
+    FIELD(VAL, RX, 0u, 16u)
+REG32(TIMEOUT_CTRL, 0x30u)
+    FIELD(TIMEOUT_CTRL, VAL, 0u, 24)
+    FIELD(TIMEOUT_CTRL, EN, 31u, 1u)
+/* clang-format on */
+
+#define INTR_MASK \
+    (INTR_TX_WATERMARK_MASK | INTR_RX_WATERMARK_MASK | INTR_TX_DONE_MASK | \
+     INTR_RX_OVERFLOW_MASK | INTR_RX_FRAME_ERR_MASK | INTR_RX_BREAK_ERR_MASK | \
+     INTR_RX_TIMEOUT_MASK | INTR_RX_PARITY_ERR_MASK | INTR_TX_EMPTY_MASK)
+
+#define CTRL_MASK \
+    (R_CTRL_TX_MASK | R_CTRL_RX_MASK | R_CTRL_NF_MASK | R_CTRL_SLPBK_MASK | \
+     R_CTRL_LLPBK_MASK | R_CTRL_PARITY_EN_MASK | R_CTRL_PARITY_ODD_MASK | \
+     R_CTRL_RXBLVL_MASK | R_CTRL_NCO_MASK)
+
+#define CTRL_SUP_MASK \
+    (R_CTRL_RX_MASK | R_CTRL_TX_MASK | R_CTRL_SLPBK_MASK | R_CTRL_NCO_MASK)
+
+#define OT_UART_NCO_BITS     16u
+#define OT_UART_TX_FIFO_SIZE 128u
+#define OT_UART_RX_FIFO_SIZE 128u
+#define OT_UART_IRQ_NUM      9u
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG (R_TIMEOUT_CTRL)
+#define REGS_COUNT (R_LAST_REG + 1u)
+#define REGS_SIZE  (REGS_COUNT * sizeof(uint32_t))
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(INTR_STATE),
+    REG_NAME_ENTRY(INTR_ENABLE),
+    REG_NAME_ENTRY(INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(CTRL),
+    REG_NAME_ENTRY(STATUS),
+    REG_NAME_ENTRY(RDATA),
+    REG_NAME_ENTRY(WDATA),
+    REG_NAME_ENTRY(FIFO_CTRL),
+    REG_NAME_ENTRY(FIFO_STATUS),
+    REG_NAME_ENTRY(OVRD),
+    REG_NAME_ENTRY(VAL),
+    REG_NAME_ENTRY(TIMEOUT_CTRL),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+struct OtUARTState {
+    SysBusDevice parent_obj;
+    MemoryRegion mmio;
+    IbexIRQ irqs[OT_UART_IRQ_NUM];
+    IbexIRQ alert;
+
+    uint32_t regs[REGS_COUNT];
+
+    Fifo8 tx_fifo;
+    Fifo8 rx_fifo;
+    uint32_t tx_watermark_level;
+    bool in_break;
+    guint watch_tag;
+    unsigned pclk; /* Current input clock */
+    const char *clock_src_name; /* IRQ name once connected */
+
+    char *ot_id;
+    char *clock_name;
+    DeviceState *clock_src;
+    CharFrontend chr;
+    bool oversample_break; /* Should mock break in the oversampled VAL reg? */
+    bool toggle_break; /* Are incoming breaks temporary or toggled? */
+};
+
+struct OtUARTClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+static uint32_t ot_uart_get_tx_watermark_level(const OtUARTState *s)
+{
+    uint32_t tx_ilvl = (s->regs[R_FIFO_CTRL] & R_FIFO_CTRL_TXILVL_MASK) >>
+                       R_FIFO_CTRL_TXILVL_SHIFT;
+
+    return tx_ilvl < 7u ? (1u << tx_ilvl) : 64u;
+}
+
+static uint32_t ot_uart_get_rx_watermark_level(const OtUARTState *s)
+{
+    uint32_t rx_ilvl = (s->regs[R_FIFO_CTRL] & R_FIFO_CTRL_RXILVL_MASK) >>
+                       R_FIFO_CTRL_RXILVL_SHIFT;
+
+    return rx_ilvl < 7u ? (1u << rx_ilvl) : 126u;
+}
+
+static void ot_uart_update_irqs(OtUARTState *s)
+{
+    uint32_t state_masked = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+
+    trace_ot_uart_irqs(s->ot_id, s->regs[R_INTR_STATE], s->regs[R_INTR_ENABLE],
+                       state_masked);
+
+    for (int index = 0; index < OT_UART_IRQ_NUM; index++) {
+        bool level = (state_masked & (1U << index)) != 0;
+        ibex_irq_set(&s->irqs[index], level);
+    }
+}
+
+static bool ot_uart_is_sys_loopack_enabled(const OtUARTState *s)
+{
+    return (bool)FIELD_EX32(s->regs[R_CTRL], CTRL, SLPBK);
+}
+
+static bool ot_uart_is_tx_enabled(const OtUARTState *s)
+{
+    return (bool)FIELD_EX32(s->regs[R_CTRL], CTRL, TX);
+}
+
+static bool ot_uart_is_rx_enabled(const OtUARTState *s)
+{
+    return (bool)FIELD_EX32(s->regs[R_CTRL], CTRL, RX);
+}
+
+static void ot_uart_check_baudrate(const OtUARTState *s)
+{
+    uint32_t nco = FIELD_EX32(s->regs[R_CTRL], CTRL, NCO);
+
+    unsigned baudrate = (unsigned)(((uint64_t)nco * (uint64_t)s->pclk) >>
+                                   (R_CTRL_NCO_LENGTH + 4));
+
+    if (baudrate) {
+        trace_ot_uart_check_baudrate(s->ot_id, s->pclk, baudrate);
+    }
+}
+
+static void ot_uart_reset_rx_fifo(OtUARTState *s)
+{
+    fifo8_reset(&s->rx_fifo);
+    s->regs[R_INTR_STATE] &= ~INTR_RX_WATERMARK_MASK;
+    s->regs[R_INTR_STATE] &= ~INTR_RX_OVERFLOW_MASK;
+    if (ot_uart_is_rx_enabled(s) && !ot_uart_is_sys_loopack_enabled(s)) {
+        qemu_chr_fe_accept_input(&s->chr);
+    }
+}
+
+static int ot_uart_can_receive(void *opaque)
+{
+    OtUARTState *s = opaque;
+
+    if (s->regs[R_CTRL] & R_CTRL_RX_MASK) {
+        return (int)fifo8_num_free(&s->rx_fifo);
+    }
+
+    return 0;
+}
+
+static void ot_uart_receive(void *opaque, const uint8_t *buf, int size)
+{
+    OtUARTState *s = opaque;
+    uint32_t rx_watermark_level;
+    size_t count = MIN(fifo8_num_free(&s->rx_fifo), (size_t)size);
+
+    if (size && !s->toggle_break) {
+        /* no longer breaking, so emulate idle in oversampled VAL register */
+        s->in_break = false;
+    }
+
+    for (int index = 0; index < size; index++) {
+        fifo8_push(&s->rx_fifo, buf[index]);
+    }
+
+    /* update INTR_STATE */
+    if (count != size) {
+        s->regs[R_INTR_STATE] |= INTR_RX_OVERFLOW_MASK;
+    }
+    rx_watermark_level = ot_uart_get_rx_watermark_level(s);
+    if (rx_watermark_level && size >= rx_watermark_level) {
+        s->regs[R_INTR_STATE] |= INTR_RX_WATERMARK_MASK;
+    }
+
+    ot_uart_update_irqs(s);
+}
+
+static void ot_uart_event_handler(void *opaque, QEMUChrEvent event)
+{
+    OtUARTState *s = opaque;
+
+    if (event == CHR_EVENT_BREAK) {
+        if (!s->in_break || !s->oversample_break) {
+            /* ignore CTRL.RXBLVL as we have no notion of break "time" */
+            s->regs[R_INTR_STATE] |= INTR_RX_BREAK_ERR_MASK;
+            ot_uart_update_irqs(s);
+            /* emulate break in the oversampled VAL register */
+            s->in_break = true;
+        } else if (s->toggle_break) {
+            /* emulate toggling break off in the oversampled VAL register */
+            s->in_break = false;
+        }
+    }
+}
+
+static uint8_t ot_uart_read_rx_fifo(OtUARTState *s)
+{
+    uint8_t val;
+
+    if (!(s->regs[R_CTRL] & R_CTRL_RX_MASK)) {
+        return 0;
+    }
+
+    if (fifo8_is_empty(&s->rx_fifo)) {
+        return 0;
+    }
+
+    val = fifo8_pop(&s->rx_fifo);
+
+    if (ot_uart_is_rx_enabled(s) && !ot_uart_is_sys_loopack_enabled(s)) {
+        qemu_chr_fe_accept_input(&s->chr);
+    }
+
+    return val;
+}
+
+static void ot_uart_reset_tx_fifo(OtUARTState *s)
+{
+    fifo8_reset(&s->tx_fifo);
+    s->regs[R_INTR_STATE] |= INTR_TX_EMPTY_MASK;
+    s->regs[R_INTR_STATE] |= INTR_TX_DONE_MASK;
+    if (s->tx_watermark_level) {
+        s->regs[R_INTR_STATE] |= INTR_TX_WATERMARK_MASK;
+        s->tx_watermark_level = 0;
+    }
+}
+
+static void ot_uart_xmit(OtUARTState *s)
+{
+    const uint8_t *buf;
+    uint32_t size;
+    int ret;
+
+    if (fifo8_is_empty(&s->tx_fifo)) {
+        return;
+    }
+
+    if (ot_uart_is_sys_loopack_enabled(s)) {
+        /* system loopback mode, just forward to RX FIFO */
+        uint32_t count = fifo8_num_used(&s->tx_fifo);
+        buf = fifo8_pop_bufptr(&s->tx_fifo, count, &size);
+        ot_uart_receive(s, buf, (int)size);
+        count -= size;
+        /*
+         * there may be more data to send if data wraps around the end of TX
+         * FIFO
+         */
+        if (count) {
+            buf = fifo8_pop_bufptr(&s->tx_fifo, count, &size);
+            ot_uart_receive(s, buf, (int)size);
+        }
+    } else {
+        /* instant drain the fifo when there's no back-end */
+        if (!qemu_chr_fe_backend_connected(&s->chr)) {
+            ot_uart_reset_tx_fifo(s);
+            ot_uart_update_irqs(s);
+            return;
+        }
+
+        /* get a continuous buffer from the FIFO */
+        buf =
+            fifo8_peek_bufptr(&s->tx_fifo, fifo8_num_used(&s->tx_fifo), &size);
+        /* send as much as possible */
+        ret = qemu_chr_fe_write(&s->chr, buf, (int)size);
+        /* if some characters where sent, remove them from the FIFO */
+        if (ret >= 0) {
+            fifo8_drop(&s->tx_fifo, ret);
+        }
+    }
+
+    /* update INTR_STATE */
+    if (fifo8_is_empty(&s->tx_fifo)) {
+        s->regs[R_INTR_STATE] |= INTR_TX_EMPTY_MASK;
+        s->regs[R_INTR_STATE] |= INTR_TX_DONE_MASK;
+    }
+    if (s->tx_watermark_level &&
+        fifo8_num_used(&s->tx_fifo) < s->tx_watermark_level) {
+        s->regs[R_INTR_STATE] |= INTR_TX_WATERMARK_MASK;
+        s->tx_watermark_level = 0;
+    }
+
+    ot_uart_update_irqs(s);
+}
+
+static gboolean ot_uart_watch_cb(void *do_not_use, GIOCondition cond,
+                                 void *opaque)
+{
+    OtUARTState *s = opaque;
+    (void)do_not_use;
+    (void)cond;
+
+    s->watch_tag = 0;
+    ot_uart_xmit(s);
+
+    return FALSE;
+}
+
+static void uart_write_tx_fifo(OtUARTState *s, uint8_t val)
+{
+    if (fifo8_is_full(&s->tx_fifo)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "ot_uart: TX FIFO overflow");
+        return;
+    }
+
+    fifo8_push(&s->tx_fifo, val);
+
+    s->tx_watermark_level = ot_uart_get_tx_watermark_level(s);
+    if (fifo8_num_used(&s->tx_fifo) < s->tx_watermark_level) {
+        /*
+         * TX watermark interrupt is raised when FIFO depth goes from above
+         * watermark to below. If we haven't reached watermark, reset cached
+         * watermark level
+         */
+        s->tx_watermark_level = 0;
+    }
+
+    if (ot_uart_is_tx_enabled(s)) {
+        ot_uart_xmit(s);
+    }
+}
+
+static void ot_uart_clock_input(void *opaque, int irq, int level)
+{
+    OtUARTState *s = opaque;
+
+    g_assert(irq == 0);
+
+    s->pclk = (unsigned)level;
+
+    /* TODO: disable UART transfer when PCLK is 0 */
+    ot_uart_check_baudrate(s);
+}
+
+static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtUARTState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    case R_INTR_STATE:
+    case R_INTR_ENABLE:
+    case R_CTRL:
+    case R_FIFO_CTRL:
+        val32 = s->regs[reg];
+        break;
+    case R_STATUS:
+        /* assume that UART always report RXIDLE */
+        val32 = R_STATUS_RXIDLE_MASK;
+        /* report RXEMPTY or RXFULL */
+        switch (fifo8_num_used(&s->rx_fifo)) {
+        case 0:
+            val32 |= R_STATUS_RXEMPTY_MASK;
+            break;
+        case OT_UART_RX_FIFO_SIZE:
+            val32 |= R_STATUS_RXFULL_MASK;
+            break;
+        default:
+            break;
+        }
+        /* report TXEMPTY+TXIDLE or TXFULL */
+        switch (fifo8_num_used(&s->tx_fifo)) {
+        case 0:
+            val32 |= R_STATUS_TXEMPTY_MASK | R_STATUS_TXIDLE_MASK;
+            break;
+        case OT_UART_TX_FIFO_SIZE:
+            val32 |= R_STATUS_TXFULL_MASK;
+            break;
+        default:
+            break;
+        }
+        if (!ot_uart_is_tx_enabled(s)) {
+            val32 |= R_STATUS_TXIDLE_MASK;
+        }
+        if (!ot_uart_is_rx_enabled(s)) {
+            val32 |= R_STATUS_RXIDLE_MASK;
+        }
+        break;
+    case R_RDATA:
+        val32 = (uint32_t)ot_uart_read_rx_fifo(s);
+        break;
+    case R_FIFO_STATUS:
+        val32 =
+            (fifo8_num_used(&s->rx_fifo) & 0xffu) << R_FIFO_STATUS_RXLVL_SHIFT;
+        val32 |=
+            (fifo8_num_used(&s->tx_fifo) & 0xffu) << R_FIFO_STATUS_TXLVL_SHIFT;
+        break;
+    case R_VAL:
+        /*
+         * This is not trivially implemented due to the QEMU UART
+         * interface. There is no way to reliably sample or oversample
+         * given our emulated interface, but some software might poll the
+         * value of this register to determine break conditions.
+         *
+         * As such, default to reporting 16 of the last sample received
+         * instead. This defaults to 16 idle high samples (as a stop bit is
+         * always the last received), except for when the `oversample-break`
+         * property is set and a break condition is received over UART RX,
+         * where we then show 16 low samples until the next valid UART
+         * transmission is received (or break is toggled off with the
+         * `toggle-break` property enabled). This will not be accurate, but
+         * should be sufficient to support basic software flows that
+         * essentially use UART break as a strapping mechanism.
+         */
+        val32 = (s->in_break && s->oversample_break) ? 0u : UINT16_MAX;
+        qemu_log_mask(LOG_UNIMP, "%s: VAL only shows idle%s\n", __func__,
+                      (s->oversample_break ? "/break" : ""));
+        break;
+    case R_OVRD:
+    case R_TIMEOUT_CTRL:
+        val32 = s->regs[reg];
+        qemu_log_mask(LOG_UNIMP, "%s: %s is not supported\n", __func__,
+                      REG_NAME(reg));
+        break;
+    case R_ALERT_TEST:
+    case R_INTR_TEST:
+    case R_WDATA:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: W/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        val32 = 0;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_uart_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                              pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,
+                          unsigned size)
+{
+    OtUARTState *s = opaque;
+    (void)size;
+    uint32_t val32 = val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_uart_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32, pc);
+
+    switch (reg) {
+    case R_INTR_STATE:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] &= ~val32; /* RW1C */
+        ot_uart_update_irqs(s);
+        break;
+    case R_INTR_ENABLE:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_ENABLE] = val32;
+        ot_uart_update_irqs(s);
+        break;
+    case R_INTR_TEST:
+        val32 &= INTR_MASK;
+        s->regs[R_INTR_STATE] |= val32;
+        ot_uart_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        s->regs[reg] = val32;
+        ibex_irq_set(&s->alert, (int)(bool)val32);
+        break;
+    case R_CTRL:
+        if (val32 & ~CTRL_SUP_MASK) {
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: UART_CTRL feature not supported: 0x%08x\n",
+                          __func__, val32 & ~CTRL_SUP_MASK);
+        }
+        uint32_t prev = s->regs[R_CTRL];
+        s->regs[R_CTRL] = val32 & CTRL_MASK;
+        uint32_t change = prev ^ s->regs[R_CTRL];
+        if (change & R_CTRL_NCO_MASK) {
+            ot_uart_check_baudrate(s);
+        }
+        if ((change & R_CTRL_RX_MASK) && ot_uart_is_rx_enabled(s) &&
+            !ot_uart_is_sys_loopack_enabled(s)) {
+            qemu_chr_fe_accept_input(&s->chr);
+        }
+        if ((change & R_CTRL_TX_MASK) && ot_uart_is_tx_enabled(s)) {
+            /* try sending pending data from TX FIFO if any */
+            ot_uart_xmit(s);
+        }
+        break;
+    case R_WDATA:
+        uart_write_tx_fifo(s, (uint8_t)(val32 & R_WDATA_WDATA_MASK));
+        break;
+    case R_FIFO_CTRL:
+        s->regs[R_FIFO_CTRL] =
+            val32 & (R_FIFO_CTRL_RXILVL_MASK | R_FIFO_CTRL_TXILVL_MASK);
+        if (val32 & R_FIFO_CTRL_RXRST_MASK) {
+            ot_uart_reset_rx_fifo(s);
+            ot_uart_update_irqs(s);
+        }
+        if (val32 & R_FIFO_CTRL_TXRST_MASK) {
+            ot_uart_reset_tx_fifo(s);
+            ot_uart_update_irqs(s);
+        }
+        break;
+    case R_OVRD:
+        if (val32 & R_OVRD_TXEN_MASK) {
+            qemu_log_mask(LOG_UNIMP, "%s: OVRD.TXEN is not supported\n",
+                          __func__);
+        }
+        s->regs[R_OVRD] = val32 & R_OVRD_TXVAL_MASK;
+        break;
+    case R_TIMEOUT_CTRL:
+        s->regs[R_TIMEOUT_CTRL] =
+            val32 & (R_TIMEOUT_CTRL_EN_MASK | R_TIMEOUT_CTRL_VAL_MASK);
+        break;
+    case R_STATUS:
+    case R_RDATA:
+    case R_FIFO_STATUS:
+    case R_VAL:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: R/O register 0x%02x (%s)\n",
+                      __func__, (uint32_t)addr, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", __func__,
+                      (uint32_t)addr);
+        break;
+    }
+}
+
+static const MemoryRegionOps ot_uart_ops = {
+    .read = ot_uart_read,
+    .write = ot_uart_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const Property ot_uart_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtUARTState, ot_id),
+    DEFINE_PROP_CHR("chardev", OtUARTState, chr),
+    DEFINE_PROP_STRING("clock-name", OtUARTState, clock_name),
+    DEFINE_PROP_LINK("clock-src", OtUARTState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+    DEFINE_PROP_BOOL("oversample-break", OtUARTState, oversample_break, false),
+    DEFINE_PROP_BOOL("toggle-break", OtUARTState, toggle_break, false),
+};
+
+static int ot_uart_be_change(void *opaque)
+{
+    OtUARTState *s = opaque;
+
+    qemu_chr_fe_set_handlers(&s->chr, ot_uart_can_receive, ot_uart_receive,
+                             ot_uart_event_handler, ot_uart_be_change, s, NULL,
+                             true);
+
+    if (s->watch_tag > 0) {
+        g_source_remove(s->watch_tag);
+        /* NOLINTNEXTLINE(clang-analyzer-optin.core.EnumCastOutOfRange) */
+        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+                                             ot_uart_watch_cb, s);
+    }
+
+    return 0;
+}
+
+static void ot_uart_reset_enter(Object *obj, ResetType type)
+{
+    OtUARTClass *c = OT_UART_GET_CLASS(obj);
+    OtUARTState *s = OT_UART(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(&s->regs[0], 0, sizeof(s->regs));
+
+    s->tx_watermark_level = 0;
+    for (unsigned index = 0; index < ARRAY_SIZE(s->irqs); index++) {
+        ibex_irq_set(&s->irqs[index], 0);
+    }
+    ot_uart_reset_tx_fifo(s);
+    ot_uart_reset_rx_fifo(s);
+
+    /*
+     * do not reset `s->in_break`, as that tracks whether we are currently
+     * receiving a break condition over UART RX from some device talking
+     * to OpenTitan, which should survive resets. The QEMU CharDev only
+     * supports transient break events and not the notion of holding the
+     * UART in break, so remembering breaks like this is required to
+     * support mocking of break conditions in the oversampled `VAL` reg.
+     */
+    if (s->in_break) {
+        /* ignore CTRL.RXBLVL as we have no notion of break "time" */
+        s->regs[R_INTR_STATE] |= INTR_RX_BREAK_ERR_MASK;
+    }
+
+    ot_uart_update_irqs(s);
+    ibex_irq_set(&s->alert, 0);
+
+    if (!s->clock_src_name) {
+        IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
+        IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
+
+        s->clock_src_name =
+            ic->get_clock_source(ii, s->clock_name, DEVICE(s), &error_fatal);
+        qemu_irq in_irq = qdev_get_gpio_in_named(DEVICE(s), "clock-in", 0);
+        qdev_connect_gpio_out_named(s->clock_src, s->clock_src_name, 0, in_irq);
+        trace_ot_uart_connect_input_clock(s->ot_id, s->clock_src_name);
+    }
+}
+
+static void ot_uart_realize(DeviceState *dev, Error **errp)
+{
+    OtUARTState *s = OT_UART(dev);
+    (void)errp;
+
+    g_assert(s->ot_id);
+    g_assert(s->clock_name);
+    g_assert(s->clock_src);
+    OBJECT_CHECK(IbexClockSrcIf, s->clock_src, TYPE_IBEX_CLOCK_SRC_IF);
+
+    qdev_init_gpio_in_named(DEVICE(s), &ot_uart_clock_input, "clock-in", 1);
+
+    fifo8_create(&s->tx_fifo, OT_UART_TX_FIFO_SIZE);
+    fifo8_create(&s->rx_fifo, OT_UART_RX_FIFO_SIZE);
+
+    qemu_chr_fe_set_handlers(&s->chr, ot_uart_can_receive, ot_uart_receive,
+                             ot_uart_event_handler, ot_uart_be_change, s, NULL,
+                             true);
+}
+
+static void ot_uart_init(Object *obj)
+{
+    OtUARTState *s = OT_UART(obj);
+
+    for (unsigned index = 0; index < OT_UART_IRQ_NUM; index++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[index]);
+    }
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    memory_region_init_io(&s->mmio, obj, &ot_uart_ops, s, TYPE_OT_UART,
+                          REGS_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void ot_uart_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = ot_uart_realize;
+    device_class_set_props(dc, ot_uart_properties);
+    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtUARTClass *uc = OT_UART_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_uart_reset_enter, NULL, NULL,
+                                       &uc->parent_phases);
+}
+
+static const TypeInfo ot_uart_info = {
+    .name = TYPE_OT_UART,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtUARTState),
+    .instance_init = ot_uart_init,
+    .class_size = sizeof(OtUARTClass),
+    .class_init = ot_uart_class_init,
+};
+
+static void ot_uart_register_types(void)
+{
+    type_register_static(&ot_uart_info);
+}
+
+type_init(ot_uart_register_types);
diff --git a/hw/opentitan/ot_unimp.c b/hw/opentitan/ot_unimp.c
new file mode 100644
index 0000000000000..3b50a4c854563
--- /dev/null
+++ b/hw/opentitan/ot_unimp.c
@@ -0,0 +1,319 @@
+/*
+ * QEMU OpenTitan unimplemented device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "exec/hwaddr.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_unimp.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+#include "trace.h"
+
+/* Comportable special registers */
+
+REG32(INTR_STATE, 0x00u)
+REG32(INTR_ENABLE, 0x04u)
+REG32(INTR_TEST, 0x08u)
+REG32(ALERT_TEST, 0x0cu)
+
+REG32(ALERT_TEST_NO_IRQ, 0x00u)
+
+
+struct OtUnimpClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+struct OtUnimpState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion mmio;
+    IbexIRQ *irqs;
+    IbexIRQ *alerts;
+
+    uint32_t *regs;
+    bool r_warned;
+    bool w_warned;
+
+    char *ot_id;
+    uint32_t size; /* mapped size, in bytes */
+    uint32_t irq_ro_mask; /* INTR_STATE R/o bits (vs, RW1C) */
+    uint8_t irq_count; /* output IRQ lines, maybe 0 */
+    uint8_t alert_count; /* output alert lines, maybe 0 */
+    bool warn_once; /* whether to emit a warning once or on each access */
+    bool no_store; /* whether to store written values */
+};
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+static inline hwaddr ot_unimp_alert_test_reg(const OtUnimpState *s)
+{
+    return s->alert_count ?
+               (s->irq_count ? R_ALERT_TEST : R_ALERT_TEST_NO_IRQ) :
+               HWADDR_MAX;
+}
+
+static void ot_unimp_update_irqs(OtUnimpState *s)
+{
+    uint32_t level = s->regs[R_INTR_STATE] & s->regs[R_INTR_ENABLE];
+
+    for (unsigned ix = 0; ix < s->irq_count; ix++) {
+        int lvl = (int)((level >> ix) & 0x1u);
+        if (ibex_irq_get_level(&s->irqs[ix]) != lvl) {
+            trace_ot_unimp_irq(s->ot_id, ix, (bool)lvl);
+        }
+        ibex_irq_set(&s->irqs[ix], lvl);
+    }
+}
+
+static void ot_unimp_update_alerts(OtUnimpState *s, uint32_t val32)
+{
+    for (unsigned ix = 0; ix < s->alert_count; ix++) {
+        if ((val32 >> ix) & 0x1u) {
+            /* alert test signals are transient */
+            trace_ot_unimp_alert(s->ot_id, ix);
+            ibex_irq_raise(&s->alerts[ix]);
+            ibex_irq_lower(&s->alerts[ix]);
+        }
+    }
+}
+
+static uint64_t ot_unimp_io_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtUnimpState *s = OT_UNIMP(opaque);
+    (void)size;
+
+    hwaddr reg = R32_OFF(addr);
+    uint32_t val32;
+
+    if (s->irq_count) {
+        switch (reg) {
+        case R_INTR_STATE:
+        case R_INTR_ENABLE:
+            return s->regs[reg];
+        case R_INTR_TEST:
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%08x\n",
+                          __func__, s->ot_id, (uint32_t)addr);
+            return 0;
+        default:
+            break;
+        }
+    }
+
+    if (reg == ot_unimp_alert_test_reg(s)) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: W/O register 0x%08x\n",
+                      __func__, s->ot_id, (uint32_t)addr);
+        return 0u;
+    }
+
+    if (!s->no_store) {
+        val32 = s->regs[reg];
+    } else {
+        val32 = 0u;
+    }
+
+    if (s->warn_once && s->r_warned) {
+        return val32;
+    }
+
+    qemu_log_mask(LOG_UNIMP,
+                  "%s: unimplemented device read @ 0x%08x = 0x%08x\n", s->ot_id,
+                  (uint32_t)addr, val32);
+
+    s->r_warned = true;
+
+    return val32;
+}
+
+static void ot_unimp_io_write(void *opaque, hwaddr addr, uint64_t value,
+                              unsigned size)
+{
+    OtUnimpState *s = OT_UNIMP(opaque);
+    (void)size;
+
+    hwaddr reg = R32_OFF(addr);
+    uint32_t val32 = (uint32_t)value;
+
+    if (s->irq_count) {
+        switch (reg) {
+        case R_INTR_STATE:
+            val32 &= (1u << s->irq_count) - 1u;
+            val32 &= ~s->irq_ro_mask;
+            s->regs[R_INTR_STATE] &= ~val32;
+            ot_unimp_update_irqs(s);
+            return;
+        case R_INTR_ENABLE:
+            val32 &= (1u << s->irq_count) - 1u;
+            s->regs[R_INTR_ENABLE] = val32;
+            ot_unimp_update_irqs(s);
+            return;
+        case R_INTR_TEST:
+            val32 &= (1u << s->irq_count) - 1u;
+            s->regs[R_INTR_STATE] |= val32;
+            ot_unimp_update_irqs(s);
+            return;
+        default:
+            break;
+        }
+    }
+
+    if (reg == ot_unimp_alert_test_reg(s)) {
+        val32 &= (1u << s->alert_count) - 1u;
+        ot_unimp_update_alerts(s, val32);
+        return;
+    }
+
+    if (!s->no_store) {
+        s->regs[reg] = val32;
+    }
+
+    if (s->warn_once && s->w_warned) {
+        return;
+    }
+
+    qemu_log_mask(LOG_UNIMP,
+                  "%s: unimplemented device write @ 0x%08x = 0x%08x\n",
+                  s->ot_id, (uint32_t)addr, (uint32_t)value);
+
+    s->w_warned = true;
+}
+
+/* clang-format off */
+static const MemoryRegionOps ot_unimp_ops = {
+    .read = ot_unimp_io_read,
+    .write = ot_unimp_io_write,
+    /* OpenTitan default LE */
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4u,
+        .max_access_size = 4u,
+    }
+};
+/* clang-format on */
+
+static const Property ot_unimp_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtUnimpState, ot_id),
+    DEFINE_PROP_UINT32("size", OtUnimpState, size, 0),
+    DEFINE_PROP_UINT32("irq-ro-mask", OtUnimpState, irq_ro_mask, 0),
+    DEFINE_PROP_UINT8("irq-count", OtUnimpState, irq_count, 0),
+    DEFINE_PROP_UINT8("alert-count", OtUnimpState, alert_count, 0),
+    DEFINE_PROP_BOOL("warn-once", OtUnimpState, warn_once, false),
+    DEFINE_PROP_BOOL("no-store", OtUnimpState, no_store, false),
+};
+
+static void ot_unimp_reset_enter(Object *obj, ResetType type)
+{
+    OtUnimpClass *c = OT_UNIMP_GET_CLASS(obj);
+    OtUnimpState *s = OT_UNIMP(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->regs, 0, s->size);
+
+    for (unsigned ix = 0; ix < (unsigned)s->irq_count; ix++) {
+        ibex_irq_lower(&s->irqs[ix]);
+    }
+
+    for (unsigned ix = 0; ix < (unsigned)s->alert_count; ix++) {
+        ibex_irq_lower(&s->alerts[ix]);
+    }
+
+    /* note: warn-once booleans are not reset */
+}
+
+static void ot_unimp_realize(DeviceState *dev, Error **errp)
+{
+    OtUnimpState *s = OT_UNIMP(dev);
+
+    g_assert(s->ot_id);
+
+    if (!s->size || (s->size & 3u)) {
+        error_setg(errp, "%s: invalid size", s->ot_id);
+        return;
+    }
+
+    if (s->irq_ro_mask & ~((1u << s->irq_count) - 1u)) {
+        error_setg(errp, "%s: invalid irq mask/count", s->ot_id);
+        return;
+    }
+
+    s->regs = !s->no_store ? g_new(uint32_t, s->size / sizeof(uint32_t)) :
+                             (s->irq_count ? g_new(uint32_t, 2u) : NULL);
+    s->irqs = s->irq_count ? g_new(IbexIRQ, s->irq_count) : NULL;
+    s->alerts = s->alert_count ? g_new(IbexIRQ, s->alert_count) : NULL;
+
+    if (s->irq_count) {
+        ibex_qdev_init_irqs(OBJECT(dev), s->irqs, SYSBUS_DEVICE_GPIO_IRQ,
+                            s->irq_count);
+    }
+    if (s->alert_count) {
+        ibex_qdev_init_irqs(OBJECT(dev), s->alerts, OT_DEVICE_ALERT,
+                            s->alert_count);
+    }
+
+    memory_region_init_io(&s->mmio, OBJECT(s), &ot_unimp_ops, s, s->ot_id,
+                          s->size);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
+}
+
+static void ot_unimp_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = ot_unimp_realize;
+    device_class_set_props(dc, ot_unimp_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtUnimpClass *uc = OT_UNIMP_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_unimp_reset_enter, NULL, NULL,
+                                       &uc->parent_phases);
+}
+
+static const TypeInfo ot_unimp_info = {
+    .name = TYPE_OT_UNIMP,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtUnimpState),
+    .class_init = ot_unimp_class_init,
+    .class_size = sizeof(OtUnimpClass),
+};
+
+static void ot_unimp_register_types(void)
+{
+    type_register_static(&ot_unimp_info);
+}
+
+type_init(ot_unimp_register_types)
diff --git a/hw/opentitan/ot_usbdev.c b/hw/opentitan/ot_usbdev.c
new file mode 100644
index 0000000000000..28d8d082bdb7a
--- /dev/null
+++ b/hw/opentitan/ot_usbdev.c
@@ -0,0 +1,2923 @@
+/*
+ * QEMU OpenTitan USBDEV device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Amaury Pouly <amaury.pouly@lowrisc.org>
+ *  Douglas Reis <doreis@lowrisc.org>
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/*
+ * OpenTitan has a "zero-time" simulation model in
+ * hw/ip/usbdev/dv/env/usbdev_bfm.sv. This driver makes references to this
+ * behavioural model as "BFM".
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/fifo8.h"
+#include "qemu/log.h"
+#include "chardev/char-fe.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_fifo32.h"
+#include "hw/opentitan/ot_usbdev.h"
+#include "hw/qdev-properties-system.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibex_irq.h"
+#include "trace.h"
+
+
+#define USBDEV_PARAM_N_ENDPOINTS 12u
+#define USBDEV_PARAM_NUM_ALERTS  1u
+#define USBDEV_PARAM_REG_WIDTH   32u
+
+#define USBDEV_ALL_EP_MASK ((1u << USBDEV_PARAM_N_ENDPOINTS) - 1u)
+
+/*
+ * The following are not parameters of the IP but hardcoded
+ * constants in the RTL.
+ */
+#define OT_USBDEV_RX_FIFO_DEPTH       8u
+#define OT_USBDEV_AV_SETUP_FIFO_DEPTH 4u
+#define OT_USBDEV_AV_OUT_FIFO_DEPTH   8u
+#define OT_USBDEV_MAX_PACKET_SIZE     64u
+#define OT_USBDEV_BUFFER_COUNT        32u
+
+/*
+ * Time in microseconds for a bus reset to complete (spec requires at least
+ * 10ms).
+ */
+#define OT_USBDEV_BUS_RESET_TIME_US 10000u
+
+/* Time in microseconds of a frame (fixed by spec). */
+#define OT_USBDEV_FRAME_TIME_US 1000u
+
+/* Standard constants */
+#define OT_USBDEV_SETUP_PACKET_SIZE 8u
+
+/* NOLINTNEXTLINE(misc-redundant-expression) */
+static_assert(USBDEV_PARAM_N_ENDPOINTS == 12u,
+              "This driver only supports 12 endpoints");
+
+/* clang-format off */
+REG32(USBDEV_INTR_STATE, 0x0u)
+    SHARED_FIELD(USBDEV_INTR_PKT_RECEIVED, 0u, 1u)
+    SHARED_FIELD(USBDEV_INTR_PKT_SENT, 1u, 1u)
+    SHARED_FIELD(USBDEV_INTR_DISCONNECTED, 2u, 1u)
+    SHARED_FIELD(USBDEV_INTR_HOST_LOST, 3u, 1u)
+    SHARED_FIELD(USBDEV_INTR_LINK_RESET, 4u, 1u)
+    SHARED_FIELD(USBDEV_INTR_LINK_SUSPEND, 5u, 1u)
+    SHARED_FIELD(USBDEV_INTR_LINK_RESUME, 6u, 1u)
+    SHARED_FIELD(USBDEV_INTR_AV_OUT_EMPTY, 7u, 1u)
+    SHARED_FIELD(USBDEV_INTR_RX_FULL, 8u, 1u)
+    SHARED_FIELD(USBDEV_INTR_AV_OVERFLOW, 9u, 1u)
+    SHARED_FIELD(USBDEV_INTR_LINK_IN_ERR, 10u, 1u)
+    SHARED_FIELD(USBDEV_INTR_RX_CRC_ERR, 11u, 1u)
+    SHARED_FIELD(USBDEV_INTR_RX_PID_ERR, 12u, 1u)
+    SHARED_FIELD(USBDEV_INTR_RX_BITSTUFF_ERR, 13u, 1u)
+    SHARED_FIELD(USBDEV_INTR_FRAME, 14u, 1u)
+    SHARED_FIELD(USBDEV_INTR_POWERED, 15u, 1u)
+    SHARED_FIELD(USBDEV_INTR_LINK_OUT_ERR, 16u, 1u)
+    SHARED_FIELD(USBDEV_INTR_AV_SETUP_EMPTY, 17u, 1u)
+REG32(USBDEV_INTR_ENABLE, 0x4u)
+REG32(USBDEV_INTR_TEST, 0x8u)
+REG32(ALERT_TEST, 0xcu)
+    FIELD(ALERT_TEST, FATAL_FAULT, 0u, 1u)
+REG32(USBCTRL, 0x10u)
+    FIELD(USBCTRL, ENABLE, 0u, 1u)
+    FIELD(USBCTRL, RESUME_LINK_ACTIVE, 1u, 1u)
+    FIELD(USBCTRL, DEVICE_ADDRESS, 16u, 7u)
+/*
+ * The following registers use the same layout:
+ * the i-th bit corresponds to endpoint i.
+ */
+REG32(EP_OUT_ENABLE, 0x14u)
+REG32(EP_IN_ENABLE, 0x18u)
+REG32(USBSTAT, 0x1cu)
+    FIELD(USBSTAT, FRAME, 0u, 11u)
+    FIELD(USBSTAT, HOST_LOST, 11u, 1u)
+    FIELD(USBSTAT, LINK_STATE, 12u, 3u)
+    FIELD(USBSTAT, SENSE, 15u, 1u)
+    FIELD(USBSTAT, AV_OUT_DEPTH, 16u, 4u)
+    FIELD(USBSTAT, AV_SETUP_DEPTH, 20u, 3u)
+    FIELD(USBSTAT, AV_OUT_FULL, 23u, 1u)
+    FIELD(USBSTAT, RX_DEPTH, 24u, 4u)
+    FIELD(USBSTAT, AV_SETUP_FULL, 30u, 1u)
+    FIELD(USBSTAT, RX_EMPTY, 31u, 1u)
+REG32(AVOUTBUFFER, 0x20u)
+    FIELD(AVOUTBUFFER, BUFFER, 0u, 5u)
+REG32(AVSETUPBUFFER, 0x24u)
+    FIELD(AVSETUPBUFFER, BUFFER, 0u, 5u)
+REG32(RXFIFO, 0x28u)
+    FIELD(RXFIFO, BUFFER, 0u, 5u)
+    FIELD(RXFIFO, SIZE, 8u, 7u)
+    FIELD(RXFIFO, SETUP, 19u, 1u)
+    FIELD(RXFIFO, EP, 20u, 4u)
+/*
+ * The following registers use the same layout:
+ * the i-th bit corresponds to endpoint i.
+ */
+REG32(RXENABLE_SETUP, 0x2cu)
+REG32(RXENABLE_OUT, 0x30u)
+REG32(SET_NAK_OUT, 0x34u)
+REG32(IN_SENT, 0x38u)
+REG32(OUT_STALL, 0x3cu)
+REG32(IN_STALL, 0x40u)
+/*
+ * The following is a multi register with
+ * USBDEV_PARAM_N_ENDPOINTS instances.
+ */
+REG32(CONFIGIN_0, 0x44u)
+    SHARED_FIELD(CONFIGIN_BUFFER, 0u, 5u)
+    SHARED_FIELD(CONFIGIN_SIZE, 8u, 7u)
+    SHARED_FIELD(CONFIGIN_SENDING, 29u, 1u)
+    SHARED_FIELD(CONFIGIN_PEND, 30u, 1u)
+    SHARED_FIELD(CONFIGIN_RDY, 31u, 1u)
+REG32(CONFIGIN_1, 0x48u)
+REG32(CONFIGIN_2, 0x4cu)
+REG32(CONFIGIN_3, 0x50u)
+REG32(CONFIGIN_4, 0x54u)
+REG32(CONFIGIN_5, 0x58u)
+REG32(CONFIGIN_6, 0x5cu)
+REG32(CONFIGIN_7, 0x60u)
+REG32(CONFIGIN_8, 0x64u)
+REG32(CONFIGIN_9, 0x68u)
+REG32(CONFIGIN_10, 0x6cu)
+REG32(CONFIGIN_11, 0x70u)
+/*
+ * The following registers use the same layout:
+ * the i-th bit corresponds to endpoint i.
+ */
+REG32(OUT_ISO, 0x74u)
+REG32(IN_ISO, 0x78u)
+REG32(OUT_DATA_TOGGLE, 0x7cu)
+    FIELD(OUT_DATA_TOGGLE, STATUS, 0u, USBDEV_PARAM_N_ENDPOINTS)
+    FIELD(OUT_DATA_TOGGLE, MASK, 16u, USBDEV_PARAM_N_ENDPOINTS)
+REG32(IN_DATA_TOGGLE, 0x80u)
+    FIELD(IN_DATA_TOGGLE, STATUS, 0u, USBDEV_PARAM_N_ENDPOINTS)
+    FIELD(IN_DATA_TOGGLE, MASK, 16u, USBDEV_PARAM_N_ENDPOINTS)
+REG32(PHY_PINS_SENSE, 0x84u)
+    FIELD(PHY_PINS_SENSE, RX_DP_I, 0u, 1u)
+    FIELD(PHY_PINS_SENSE, RX_DN_I, 1u, 1u)
+    FIELD(PHY_PINS_SENSE, RX_D_I, 2u, 1u)
+    FIELD(PHY_PINS_SENSE, TX_DP_O, 8u, 1u)
+    FIELD(PHY_PINS_SENSE, TX_DN_O, 9u, 1u)
+    FIELD(PHY_PINS_SENSE, TX_D_O, 10u, 1u)
+    FIELD(PHY_PINS_SENSE, TX_SE0_O, 11u, 1u)
+    FIELD(PHY_PINS_SENSE, TX_OE_O, USBDEV_PARAM_N_ENDPOINTS, 1u)
+    FIELD(PHY_PINS_SENSE, PWR_SENSE, 16u, 1u)
+REG32(PHY_PINS_DRIVE, 0x88u)
+    FIELD(PHY_PINS_DRIVE, DP_O, 0u, 1u)
+    FIELD(PHY_PINS_DRIVE, DN_O, 1u, 1u)
+    FIELD(PHY_PINS_DRIVE, D_O, 2u, 1u)
+    FIELD(PHY_PINS_DRIVE, SE0_O, 3u, 1u)
+    FIELD(PHY_PINS_DRIVE, OE_O, 4u, 1u)
+    FIELD(PHY_PINS_DRIVE, RX_ENABLE_O, 5u, 1u)
+    FIELD(PHY_PINS_DRIVE, DP_PULLUP_EN_O, 6u, 1u)
+    FIELD(PHY_PINS_DRIVE, DN_PULLUP_EN_O, 7u, 1u)
+    FIELD(PHY_PINS_DRIVE, EN, 16u, 1u)
+REG32(PHY_CONFIG, 0x8cu)
+    FIELD(PHY_CONFIG, USE_DIFF_RCVR, 0u, 1u)
+    FIELD(PHY_CONFIG, TX_USE_D_SE0, 1u, 1u)
+    FIELD(PHY_CONFIG, EOP_SINGLE_BIT, 2u, 1u)
+    FIELD(PHY_CONFIG, PINFLIP, 5u, 1u)
+    FIELD(PHY_CONFIG, USB_REF_DISABLE, 6u, 1u)
+    FIELD(PHY_CONFIG, TX_OSC_TEST_MODE, 7u, 1u)
+REG32(WAKE_CONTROL, 0x90u)
+    FIELD(WAKE_CONTROL, SUSPEND_REQ, 0u, 1u)
+    FIELD(WAKE_CONTROL, WAKE_ACK, 1u, 1u)
+REG32(WAKE_EVENTS, 0x94u)
+    FIELD(WAKE_EVENTS, MODULE_ACTIVE, 0u, 1u)
+    FIELD(WAKE_EVENTS, DISCONNECTED, 8u, 1u)
+    FIELD(WAKE_EVENTS, BUS_RESET, 9u, 1u)
+    FIELD(WAKE_EVENTS, BUS_NOT_IDLE, 10u, 1u)
+REG32(FIFO_CTRL, 0x98u)
+    FIELD(FIFO_CTRL, AVOUT_RST, 0u, 1u)
+    FIELD(FIFO_CTRL, AVSETUP_RST, 1u, 1u)
+    FIELD(FIFO_CTRL, RX_RST, 2u, 1u)
+REG32(COUNT_OUT, 0x9cu)
+    FIELD(COUNT_OUT, COUNT, 0u, 8u)
+    FIELD(COUNT_OUT, DATATOG_OUT, USBDEV_PARAM_N_ENDPOINTS, 1u)
+    FIELD(COUNT_OUT, DROP_RX, 13u, 1u)
+    FIELD(COUNT_OUT, DROP_AVOUT, 14u, 1u)
+    FIELD(COUNT_OUT, IGN_AVSETUP, 15u, 1u)
+    FIELD(COUNT_OUT, ENDPOINTS, 16u, USBDEV_PARAM_N_ENDPOINTS)
+    FIELD(COUNT_OUT, RST, 31u, 1u)
+REG32(COUNT_IN, 0xa0u)
+    FIELD(COUNT_IN, COUNT, 0u, 8u)
+    FIELD(COUNT_IN, NODATA, 13u, 1u)
+    FIELD(COUNT_IN, NAK, 14u, 1u)
+    FIELD(COUNT_IN, TIMEOUT, 15u, 1u)
+    FIELD(COUNT_IN, ENDPOINTS, 16u, USBDEV_PARAM_N_ENDPOINTS)
+    FIELD(COUNT_IN, RST, 31u, 1u)
+REG32(COUNT_NODATA_IN, 0xa4u)
+    FIELD(COUNT_NODATA_IN, COUNT, 0u, 8u)
+    FIELD(COUNT_NODATA_IN, ENDPOINTS, 16u, USBDEV_PARAM_N_ENDPOINTS)
+    FIELD(COUNT_NODATA_IN, RST, 31u, 1u)
+REG32(COUNT_ERRORS, 0xa8u)
+    FIELD(COUNT_ERRORS, COUNT, 0u, 8u)
+    FIELD(COUNT_ERRORS, PID_INVALID, 27u, 1u)
+    FIELD(COUNT_ERRORS, BITSTUFF, 28u, 1u)
+    FIELD(COUNT_ERRORS, CRC16, 29u, 1u)
+    FIELD(COUNT_ERRORS, CRC5, 30u, 1u)
+    FIELD(COUNT_ERRORS, RST, 31u, 1u)
+/* clang-format on */
+
+#define R32_OFF(_r_) ((_r_) / sizeof(uint32_t))
+
+#define R_LAST_REG       (R_COUNT_ERRORS)
+#define REGS_COUNT       (R_LAST_REG + 1u)
+#define USBDEV_REGS_SIZE (REGS_COUNT * sizeof(uint32_t))
+
+#define USBDEV_INTR_NUM 18u
+
+#define USBDEV_INTR_RW1C_MASK \
+    (USBDEV_INTR_DISCONNECTED_MASK | USBDEV_INTR_HOST_LOST_MASK | \
+     USBDEV_INTR_LINK_RESET_MASK | USBDEV_INTR_LINK_SUSPEND_MASK | \
+     USBDEV_INTR_LINK_RESUME_MASK | USBDEV_INTR_AV_OVERFLOW_MASK | \
+     USBDEV_INTR_LINK_IN_ERR_MASK | USBDEV_INTR_RX_CRC_ERR_MASK | \
+     USBDEV_INTR_RX_PID_ERR_MASK | USBDEV_INTR_RX_BITSTUFF_ERR_MASK | \
+     USBDEV_INTR_FRAME_MASK | USBDEV_INTR_POWERED_MASK | \
+     USBDEV_INTR_LINK_OUT_ERR_MASK)
+
+#define USBDEV_INTR_MASK \
+    (USBDEV_INTR_RW1C_MASK | USBDEV_INTR_PKT_RECEIVED_MASK | \
+     USBDEV_INTR_PKT_SENT_MASK | USBDEV_INTR_AV_OUT_EMPTY_MASK | \
+     USBDEV_INTR_RX_FULL_MASK | USBDEV_INTR_AV_SETUP_EMPTY_MASK)
+
+#define USBDEV_USBCTRL_R_MASK \
+    (R_USBCTRL_ENABLE_MASK | R_USBCTRL_DEVICE_ADDRESS_MASK)
+
+#define USBDEV_CONFIGIN_RW1C_MASK (CONFIGIN_PEND_MASK | CONFIGIN_SENDING_MASK)
+
+static_assert(USBDEV_INTR_MASK == (1u << USBDEV_INTR_NUM) - 1u,
+              "Interrupt mask mismatch");
+
+#define USBDEV_DEVICE_SIZE   0x1000u
+#define USBDEV_REGS_OFFSET   0u
+#define USBDEV_BUFFER_OFFSET 0x800u
+#define USBDEV_BUFFER_SIZE   0x800u
+
+static_assert(OT_USBDEV_MAX_PACKET_SIZE * OT_USBDEV_BUFFER_COUNT ==
+                  USBDEV_BUFFER_SIZE,
+              "USBDEV buffer size mismatch");
+
+/*
+ * Link state: this is the register field value, which we also use to
+ * track the state of the link in general.
+ */
+typedef enum {
+    /* Link disconnected (no VBUS or no pull-up connected). */
+    OT_USBDEV_LINK_STATE_DISCONNECTED = 0,
+    /* Link powered and connected, but not reset yet. */
+    OT_USBDEV_LINK_STATE_POWERED = 1,
+    /* Link suspended (constant idle/J for > 3 ms), but not reset yet. */
+    OT_USBDEV_LINK_STATE_POWERED_SUSP = 2,
+    /* Link active. */
+    OT_USBDEV_LINK_STATE_ACTIVE = 3,
+    /*
+     * Link suspended (constant idle for > 3 ms), was active before
+     * becoming suspended.
+     */
+    OT_USBDEV_LINK_STATE_SUSPENDED = 4,
+    /* Link active but no SOF has been received since the last reset. */
+    OT_USBDEV_LINK_STATE_ACTIVE_NOSOF = 5,
+    /*
+     * Link resuming to an active state,
+     * pending the end of resume signaling.
+     */
+    OT_USBDEV_LINK_STATE_RESUMING = 6,
+    OT_USBDEV_LINK_STATE_COUNT,
+} OtUsbdevLinkState;
+
+#define LINK_STATE_ENTRY(_name) \
+    [OT_USBDEV_LINK_STATE_##_name] = stringify(_name)
+
+static const char *LINK_STATE_NAME[] = {
+    /* clang-format off */
+    LINK_STATE_ENTRY(DISCONNECTED),
+    LINK_STATE_ENTRY(POWERED),
+    LINK_STATE_ENTRY(POWERED_SUSP),
+    LINK_STATE_ENTRY(ACTIVE),
+    LINK_STATE_ENTRY(SUSPENDED),
+    LINK_STATE_ENTRY(ACTIVE_NOSOF),
+    LINK_STATE_ENTRY(RESUMING),
+    /* clang-format on */
+};
+#undef LINK_STATE_ENTRY
+
+#define LINK_STATE_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(LINK_STATE_NAME) ? \
+         LINK_STATE_NAME[(_st_)] : \
+         "?")
+
+struct OtUsbdevClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+/* Size of the communication buffer for the chardev. */
+#define CMD_BUF_SIZE 32u
+
+/* NOLINTNEXTLINE(misc-redundant-expression) */
+static_assert(USBDEV_PARAM_NUM_ALERTS == 1u,
+              "This only supports a single alert (fault)");
+
+/*
+ * USB server protocol
+ *
+ * The protocol is documented in docs/opentitan/ot_usbdev.md
+ */
+
+typedef enum {
+    OT_USBDEV_SERVER_CMD_INVALID,
+    OT_USBDEV_SERVER_CMD_HELLO,
+    OT_USBDEV_SERVER_CMD_VBUS_ON,
+    OT_USBDEV_SERVER_CMD_VBUS_OFF,
+    OT_USBDEV_SERVER_CMD_CONNECT,
+    OT_USBDEV_SERVER_CMD_DISCONNECT,
+    OT_USBDEV_SERVER_CMD_RESET,
+    OT_USBDEV_SERVER_CMD_RESUME,
+    OT_USBDEV_SERVER_CMD_SUSPEND,
+    OT_USBDEV_SERVER_CMD_SETUP,
+    OT_USBDEV_SERVER_CMD_TRANSFER,
+    OT_USBDEV_SERVER_CMD_COMPLETE,
+    OT_USBDEV_SERVER_CMD_CANCEL,
+} OtUsbdevServerCmd;
+
+typedef struct {
+    uint32_t cmd; /* Command, see OtUsbdevServerCmd */
+    uint32_t size; /* Size, excluding header */
+    uint32_t id; /* Unique ID */
+} OtUsbdevServerPktHdr;
+
+static_assert(sizeof(OtUsbdevServerPktHdr) == 12u,
+              "Packet header has the wrong size");
+
+#define OT_USBDEV_SERVER_HELLO_MAGIC "UDCX"
+#define OT_USBDEV_SERVER_MAJOR_VER   1u
+#define OT_USBDEV_SERVER_MINOR_VER   0u
+
+typedef struct {
+    char magic[4];
+    uint16_t major_version;
+    uint16_t minor_version;
+} OtUsbdevServerHelloPkt;
+
+static_assert(sizeof(OtUsbdevServerHelloPkt) == 8u,
+              "Hello packet has the wrong size");
+
+typedef struct {
+    uint8_t address;
+    uint8_t endpoint;
+    uint8_t reserved[2];
+    uint8_t setup[OT_USBDEV_SETUP_PACKET_SIZE];
+} OtUsbdevServerSetupPkt;
+
+static_assert(sizeof(OtUsbdevServerSetupPkt) == 12u,
+              "Setup packet has the wrong size");
+
+#define OT_USBDEV_EP_DIR_IN   0x80u
+#define OT_USBDEV_EP_NUM_MASK 0x7fu
+
+typedef enum {
+    OT_USBDEV_SERVER_FLAG_ZLP = 1u << 0u,
+} OtUsbdevServerTransferFlags;
+
+typedef struct {
+    uint8_t address;
+    uint8_t endpoint;
+    uint16_t packet_size;
+    uint8_t flags;
+    uint8_t reserved[3];
+    uint32_t transfer_size;
+} OtUsbdevServerTransferPkt;
+
+static_assert(sizeof(OtUsbdevServerTransferPkt) == 12u,
+              "Transfer packet has the wrong size");
+
+typedef enum {
+    OT_USBDEV_SERVER_STATUS_SUCCESS,
+    OT_USBDEV_SERVER_STATUS_STALLED,
+    OT_USBDEV_SERVER_STATUS_CANCELLED,
+    OT_USBDEV_SERVER_STATUS_ERROR,
+} OtUsbdevServerTransferStatus;
+
+typedef struct {
+    uint32_t xfer_id;
+} OtUsbdevServerCancelPkt;
+
+static_assert(sizeof(OtUsbdevServerCancelPkt) == 4u,
+              "Cancel packet has the wrong size");
+
+#define XFER_STATUS_ENTRY(_name) \
+    [OT_USBDEV_SERVER_STATUS_##_name] = stringify(_name)
+
+static const char *XFER_STATUS_NAME[] = {
+    /* clang-format off */
+    XFER_STATUS_ENTRY(SUCCESS),
+    XFER_STATUS_ENTRY(STALLED),
+    XFER_STATUS_ENTRY(CANCELLED),
+    XFER_STATUS_ENTRY(ERROR),
+    /* clang-format on */
+};
+#undef XFER_STATUS_ENTRY
+
+#define XFER_STATUS_NAME(_st_) \
+    (((unsigned)(_st_)) < ARRAY_SIZE(XFER_STATUS_NAME) ? \
+         XFER_STATUS_NAME[(_st_)] : \
+         "?")
+
+typedef struct {
+    uint8_t status;
+    uint8_t reserved[3];
+    uint32_t transfer_size;
+} OtUsbdevServerCompletePkt;
+
+/* State machine for the server receive path */
+typedef enum {
+    /* Wait for packet header */
+    OT_USBDEV_SERVER_RECV_WAIT_HEADER,
+    OT_USBDEV_SERVER_RECV_WAIT_DATA,
+} OtUsbdevServerRecvState;
+
+typedef struct {
+    bool pending; /* Is there a transfer pending? */
+    uint32_t id; /* ID of the transfer */
+    uint32_t xfer_len; /* Maximum length of the transfer */
+    uint8_t *xfer_buf; /* Buffer allocated to hold the data */
+    uint16_t max_packet_size; /* Maximum packet size */
+    uint32_t recv_rem; /* Remaining quantity to receive */
+    uint8_t *recv_buf; /* Pointer to buffer where to receive */
+} OtUsbdevServerEpInXfer;
+
+typedef struct {
+    bool pending; /* Is there a transfer pending? */
+    bool send_zlp; /* Send a ZLP */
+    uint32_t id; /* ID of the transfer */
+    uint32_t xfer_len; /* Length of the transfer */
+    uint8_t *xfer_buf; /* Buffer allocated to hold the data */
+    uint16_t max_packet_size; /* Maximum packet size */
+    uint32_t send_rem; /* Remaining quantity to send */
+    uint8_t *send_buf; /* Pointer to buffer where to send */
+} OtUsbdevServerEpOutXfer;
+
+typedef struct {
+    OtUsbdevServerEpInXfer in;
+    OtUsbdevServerEpOutXfer out;
+} OtUsbdevServerEpXfer;
+
+typedef struct {
+    /* Current state of the receiver */
+    OtUsbdevServerRecvState recv_state;
+    size_t recv_rem; /* Remaining quantity to receive */
+    uint8_t *recv_buf; /* Pointer to buffer where to receive */
+    /* Packet header under reception or processing */
+    OtUsbdevServerPktHdr recv_pkt;
+    /* Packet data under reception or processing */
+    uint8_t *recv_data;
+
+    /* endpoint transfers in progress */
+    OtUsbdevServerEpXfer ep[USBDEV_PARAM_N_ENDPOINTS];
+
+    /* Current state of server */
+    bool client_connected; /* We have a client */
+    bool vbus_connected; /* The host has turned on VBUS */
+    bool hello_done; /* Have received a HELLO? */
+} OtUsbdevServer;
+
+struct OtUsbdevState {
+    SysBusDevice parent_obj;
+    struct {
+        MemoryRegion main;
+        MemoryRegion regs;
+        MemoryRegion buffer;
+    } mmio;
+    char *ot_id;
+    /* Link to the clkmgr. */
+    DeviceState *clock_src;
+    /* Name of the USB clock. */
+    char *usbclk_name;
+    /* Name of the AON clock. */
+    char *aonclk_name;
+
+    IbexIRQ irqs[USBDEV_INTR_NUM];
+    IbexIRQ alert;
+
+    /* Register content */
+    uint32_t regs[REGS_COUNT];
+
+    /*
+     * Content of the RX FIFO: each entry is encoded like the
+     * RXFIFO register.
+     */
+    OtFifo32 rx_fifo;
+    /*
+     * Content of the available SETUP and OUT buffer FIFOs:
+     * each entry is a buffer ID.
+     */
+    Fifo8 av_setup_fifo;
+    Fifo8 av_out_fifo;
+
+    /* Buffer content */
+    uint32_t buffer[USBDEV_BUFFER_SIZE / sizeof(uint32_t)];
+
+    /* Communication device and buffer for management. */
+    CharFrontend cmd_chr;
+    char cmd_buf[CMD_BUF_SIZE];
+    unsigned cmd_buf_pos;
+    /* Communication device for the USB protocol. */
+    CharFrontend usb_chr;
+    OtUsbdevServer usb_server;
+
+    /*
+     * Timer to handle bus reset. While this timer is pending,
+     * it means that a bus reset signalling is in progress.
+     */
+    QEMUTimer bus_reset_timer;
+
+    /*
+     * Timer to handle frame counting. While this timer is pending,
+     * it means that the frame counter must not change and that an
+     * IRQ will be triggered when the timer expires. Also see remarks
+     * on the frame counter.
+     */
+    QEMUTimer frame_timer;
+
+    /*
+     * We keep the current frame number in the following variable. There
+     * are 1000 frames per second so we really want to avoid scheduling a
+     * timer for each frame if we can avoid it. It is very unlikely that
+     * the device will want to do so anyway and it is more likely to read
+     * the frame counter in the USBSTAT register. Therefore we can avoid
+     * using a timer as long as we create a consistent picture for the
+     * device code. This mostly means:
+     * - the frame counter should increase by one every millisecond,
+     * - the frame counter must not change value between two SOF IRQs.
+     * We can keep track of the second condition by noticing that unless
+     * the device code clears the SOF interrupt, it cannot actually detect
+     * when the SOF happens and therefore this consistency check can be
+     * relaxed. However if the device code *does* clear the SOF interrupt,
+     * we need to make sure to enforce the second requirement.
+     *
+     * Therefore the logic is as follows: we record the time at which the bus
+     * reset completed (this is the beginning of "frame 0").
+     * If the frame timer is not pending, we extrapolate the frame counter
+     * value based on the time elapsed since the last bus reset. If the software
+     * clear the SOF interrupt, a frozen value is recorded based on the
+     * previous logic and a frame timer is scheduled. While the frame
+     * timer is pending, the frame counter value is frozen to this value.
+     */
+    uint32_t frozen_frame;
+    int64_t frame0_time_us;
+
+    /*
+     * This is the next endpoint that should be considered when
+     * we have pending transfers and we need to choose which
+     * one receives a packet. This is used to provide a weak
+     * form of scheduling and ensure fairness.
+     */
+    uint8_t next_ep_out_sched_xfer;
+
+    /* VBUS override mode. */
+    bool vbus_override;
+    /* VBUS gate: meaning depends on the vbus_override mode */
+    bool vbus_gate;
+};
+
+#define REG_NAME(_reg_) \
+    ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : "?")
+
+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)
+static const char *REG_NAMES[REGS_COUNT] = {
+    /* clang-format off */
+    REG_NAME_ENTRY(USBDEV_INTR_STATE),
+    REG_NAME_ENTRY(USBDEV_INTR_ENABLE),
+    REG_NAME_ENTRY(USBDEV_INTR_TEST),
+    REG_NAME_ENTRY(ALERT_TEST),
+    REG_NAME_ENTRY(USBCTRL),
+    REG_NAME_ENTRY(EP_OUT_ENABLE),
+    REG_NAME_ENTRY(EP_IN_ENABLE),
+    REG_NAME_ENTRY(USBSTAT),
+    REG_NAME_ENTRY(AVOUTBUFFER),
+    REG_NAME_ENTRY(AVSETUPBUFFER),
+    REG_NAME_ENTRY(RXFIFO),
+    REG_NAME_ENTRY(RXENABLE_SETUP),
+    REG_NAME_ENTRY(RXENABLE_OUT),
+    REG_NAME_ENTRY(SET_NAK_OUT),
+    REG_NAME_ENTRY(IN_SENT),
+    REG_NAME_ENTRY(OUT_STALL),
+    REG_NAME_ENTRY(IN_STALL),
+    REG_NAME_ENTRY(CONFIGIN_0),
+    REG_NAME_ENTRY(CONFIGIN_1),
+    REG_NAME_ENTRY(CONFIGIN_2),
+    REG_NAME_ENTRY(CONFIGIN_3),
+    REG_NAME_ENTRY(CONFIGIN_4),
+    REG_NAME_ENTRY(CONFIGIN_5),
+    REG_NAME_ENTRY(CONFIGIN_6),
+    REG_NAME_ENTRY(CONFIGIN_7),
+    REG_NAME_ENTRY(CONFIGIN_8),
+    REG_NAME_ENTRY(CONFIGIN_9),
+    REG_NAME_ENTRY(CONFIGIN_10),
+    REG_NAME_ENTRY(CONFIGIN_11),
+    REG_NAME_ENTRY(OUT_ISO),
+    REG_NAME_ENTRY(IN_ISO),
+    REG_NAME_ENTRY(OUT_DATA_TOGGLE),
+    REG_NAME_ENTRY(IN_DATA_TOGGLE),
+    REG_NAME_ENTRY(PHY_PINS_SENSE),
+    REG_NAME_ENTRY(PHY_PINS_DRIVE),
+    REG_NAME_ENTRY(PHY_CONFIG),
+    REG_NAME_ENTRY(WAKE_CONTROL),
+    REG_NAME_ENTRY(WAKE_EVENTS),
+    REG_NAME_ENTRY(FIFO_CTRL),
+    REG_NAME_ENTRY(COUNT_OUT),
+    REG_NAME_ENTRY(COUNT_IN),
+    REG_NAME_ENTRY(COUNT_NODATA_IN),
+    REG_NAME_ENTRY(COUNT_ERRORS),
+    /* clang-format on */
+};
+#undef REG_NAME_ENTRY
+
+/*
+ * Forward definitions
+ */
+static void ot_usbdev_server_report_connected(OtUsbdevState *s, bool connected);
+static void ot_usbdev_server_complete_transfer(
+    OtUsbdevState *s, uint32_t id, OtUsbdevServerTransferStatus status,
+    uint32_t xfer_size, const uint8_t *data, uint32_t data_size,
+    const char *msg);
+static void ot_usbdev_complete_transfer_in(OtUsbdevState *s, uint8_t epnum,
+                                           OtUsbdevServerTransferStatus status,
+                                           const char *msg);
+static void ot_usbdev_complete_transfer_out(OtUsbdevState *s, uint8_t epnum,
+                                            OtUsbdevServerTransferStatus status,
+                                            const char *msg);
+static bool ot_usbdev_is_enabled(const OtUsbdevState *s);
+static void
+ot_usbdev_cancel_all_transfers(OtUsbdevState *s, const char *reason);
+
+/*
+ * Update the INTR_STATE register for status interrupts.
+ */
+static void ot_usbdev_update_status_irqs(OtUsbdevState *s)
+{
+    uint32_t set_mask = 0u;
+    if (ot_usbdev_is_enabled(s)) {
+        if (s->regs[R_IN_SENT]) {
+            set_mask |= USBDEV_INTR_PKT_SENT_MASK;
+        }
+        if (fifo8_is_empty(&s->av_setup_fifo)) {
+            set_mask |= USBDEV_INTR_AV_SETUP_EMPTY_MASK;
+        }
+        if (fifo8_is_empty(&s->av_out_fifo)) {
+            set_mask |= USBDEV_INTR_AV_OUT_EMPTY_MASK;
+        }
+        if (ot_fifo32_is_full(&s->rx_fifo)) {
+            set_mask |= USBDEV_INTR_RX_FULL_MASK;
+        }
+        if (!ot_fifo32_is_empty(&s->rx_fifo)) {
+            set_mask |= USBDEV_INTR_PKT_RECEIVED_MASK;
+        }
+    }
+    /*
+     * @todo The BFM says that 'Disconnected' is held at 1 during IP
+     * reset, need to investigate this detail.
+     */
+    s->regs[R_USBDEV_INTR_STATE] |= set_mask;
+}
+
+/*
+ * Update the IRQs at the Ibex given the content of the INTR_*
+ * register.
+ */
+static void ot_usbdev_update_irqs(OtUsbdevState *s)
+{
+    ot_usbdev_update_status_irqs(s);
+    uint32_t state_masked =
+        s->regs[R_USBDEV_INTR_STATE] & s->regs[R_USBDEV_INTR_ENABLE];
+
+    trace_ot_usbdev_irqs(s->ot_id, s->regs[R_USBDEV_INTR_STATE],
+                         s->regs[R_USBDEV_INTR_ENABLE], state_masked);
+
+    for (unsigned irq_index = 0u; irq_index < USBDEV_INTR_NUM; irq_index++) {
+        bool level = (state_masked & (1U << irq_index)) != 0u;
+        ibex_irq_set(&s->irqs[irq_index], level);
+    }
+}
+
+/*
+ * Update the alerts at the Ibex given the content of the ALERT_TEST
+ * register.
+ */
+static void ot_usbdev_update_alerts(OtUsbdevState *s)
+{
+    uint32_t level = s->regs[R_ALERT_TEST];
+    s->regs[R_ALERT_TEST] = 0u;
+
+    /* @todo add other sources of alerts here */
+
+    if (level & R_ALERT_TEST_FATAL_FAULT_MASK) {
+        ibex_irq_set(&s->alert, 1);
+        ibex_irq_set(&s->alert, 0);
+    }
+}
+
+/*
+ * Determine whether the USBDEV is enabled (ie asserting the pullup).
+ *
+ * @return true if enabled (USBCTRL.ENABLE is set).
+ */
+bool ot_usbdev_is_enabled(const OtUsbdevState *s)
+{
+    /*
+     * Note: this works even if the device is in reset because
+     * we clear registers on reset entry.
+     */
+    return (bool)FIELD_EX32(s->regs[R_USBCTRL], USBCTRL, ENABLE);
+}
+
+/*
+ * Determine whether VBUS is on.
+ *
+ * @return true if VBUS is present (USBSTAT.SENSE is set).
+ */
+static bool ot_usbdev_has_vbus(const OtUsbdevState *s)
+{
+    /*
+     * Note: always returns 0 when device is in reset.
+     */
+    return FIELD_EX32(s->regs[R_USBSTAT], USBSTAT, SENSE);
+}
+
+/*
+ * Return the current link state.
+ *
+ * @return value of USBSTAT.LINK_STATE.
+ */
+static OtUsbdevLinkState ot_usbdev_get_link_state(const OtUsbdevState *s)
+{
+    unsigned int v = FIELD_EX32(s->regs[R_USBSTAT], USBSTAT, LINK_STATE);
+    /* The SW cannot modify the USBSTAT register but let's be paranoid */
+    g_assert(v <= OT_USBDEV_LINK_STATE_COUNT);
+    return (OtUsbdevLinkState)v;
+}
+
+/*
+ * Return the current device address.
+ *
+ * @return value of USBCTRL.DEVICE_ADDRESS
+ */
+static uint8_t ot_usbdev_get_address(const OtUsbdevState *s)
+{
+    return (uint8_t)FIELD_EX32(s->regs[R_USBCTRL], USBCTRL, DEVICE_ADDRESS);
+}
+
+/*
+ * Determine whether an OUT endpoint is enabled.
+ *
+ * @ep endpoint number
+ * @return value of ep_out_enable.enable_<ep>
+ */
+static bool ot_usbdev_is_ep_out_enabled(const OtUsbdevState *s, uint8_t ep)
+{
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+    return (bool)((s->regs[R_EP_OUT_ENABLE] >> ep) & 1u);
+}
+
+/*
+ * Determine whether an OUT endpoint can receive a packet.
+ *
+ * @ep endpoint number
+ * @return value of rxenable_out.out_<ep>
+ */
+static bool ot_usbdev_is_ep_out_rxenabled(const OtUsbdevState *s, uint8_t ep)
+{
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+    return (bool)((s->regs[R_RXENABLE_OUT] >> ep) & 1u);
+}
+
+/*
+ * Determine whether RX reception is enabled on an endpoint.
+ *
+ * @ep endpoint number
+ * @return value of rxenable_setup.setup_<ep>
+ */
+static bool ot_usbdev_is_ep_setup_rx_enabled(const OtUsbdevState *s, uint8_t ep)
+{
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+    return (bool)((s->regs[R_RXENABLE_SETUP] >> ep) & 1u);
+}
+
+/*
+ * Determine whether an IN endpoint is enabled.
+ *
+ * @ep endpoint number
+ * @return value of ep_in_enable.enable_<ep>
+ */
+static bool ot_usbdev_is_ep_in_enabled(const OtUsbdevState *s, uint8_t ep)
+{
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+    return (bool)((s->regs[R_EP_IN_ENABLE] >> ep) & 1u);
+}
+
+/*
+ * Determine whether an IN endpoint is stalled.
+ *
+ * @ep endpoint number
+ * @return value of in_stall.endpoint_<ep>
+ */
+static bool ot_usbdev_is_ep_in_stalled(const OtUsbdevState *s, uint8_t ep)
+{
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+    return (bool)((s->regs[R_IN_STALL] >> ep) & 1u);
+}
+
+/*
+ * Determine whether an OUT endpoint is stalled.
+ *
+ * @ep endpoint number
+ * @return value of out_stall.endpoint_<ep>
+ */
+static bool ot_usbdev_is_ep_out_stalled(const OtUsbdevState *s, uint8_t ep)
+{
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+    return (bool)((s->regs[R_OUT_STALL] >> ep) & 1u);
+}
+
+/*
+ * Determine whether an OUT endpoint has "auto NAK" enabled.
+ *
+ * @ep endpoint number
+ * @return value of set_nak_out.endpoint_<ep>
+ */
+static bool ot_usbdev_is_set_nak_out_enabled(const OtUsbdevState *s, uint8_t ep)
+{
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+    return (bool)((s->regs[R_SET_NAK_OUT] >> ep) & 1u);
+}
+
+/*
+ * Change the link state in the USBSTAT register and trace change.
+ *
+ * Note: no events (IRQs, etc) are triggered, this is the caller's
+ * responsibility.
+ */
+static void
+ot_usbdev_set_raw_link_state(OtUsbdevState *s, OtUsbdevLinkState state)
+{
+    OtUsbdevLinkState old_state = ot_usbdev_get_link_state(s);
+
+    if (old_state != state) {
+        trace_ot_usbdev_link_state_changed(s->ot_id, LINK_STATE_NAME(state));
+    }
+
+    s->regs[R_USBSTAT] =
+        FIELD_DP32(s->regs[R_USBSTAT], USBSTAT, LINK_STATE, (uint32_t)state);
+}
+
+/*
+ * Write the content of a USB buffer.
+ *
+ * @buf_id ID of the buffer
+ * @buf Buffer holding the data
+ * @size How much data to copy
+ */
+static void ot_usbdev_write_buffer(OtUsbdevState *s, uint8_t buf_id,
+                                   const uint8_t *data, size_t size)
+{
+    g_assert(size <= OT_USBDEV_MAX_PACKET_SIZE);
+    g_assert(buf_id < OT_USBDEV_BUFFER_COUNT);
+
+    /*
+     * See BFM (write_pkt_bytes).
+     *
+     * The buffer is stored as words, which means that if the packet size
+     * is not a multiple of 4, the RTL will zero out the bytes at the end
+     * of the last word.
+     *
+     * This function does not fully emulate the complex behaviour w.r.t
+     * the CRC being written to the buffer or data being remembered in
+     * the flops (see BFM).
+     */
+    uint32_t *ptr =
+        &s->buffer[buf_id * OT_USBDEV_MAX_PACKET_SIZE / sizeof(uint32_t)];
+    while (size >= 4u) {
+        *ptr++ = ldl_le_p(data);
+        data += sizeof(uint32_t);
+        size -= 4u;
+    }
+    if (size == 0u) {
+        return;
+    }
+    /* Handle last incomplete word */
+    uint32_t val32 = 0u;
+    val32 |= *data++;
+    if (size >= 2u) {
+        val32 |= *data++ << 8u;
+    }
+    if (size >= 3u) {
+        val32 |= *data++ << 16u;
+    }
+    *ptr++ = val32;
+}
+
+/*
+ * Read the content of a USB buffer.
+ *
+ * @buf_id ID of the buffer
+ * @buf Buffer where to copy the data
+ * @size How much data to copy
+ */
+static void ot_usbdev_read_buffer(OtUsbdevState *s, uint8_t buf_id,
+                                  uint8_t *buf, size_t size)
+{
+    g_assert(size <= OT_USBDEV_MAX_PACKET_SIZE);
+    g_assert(buf_id < OT_USBDEV_BUFFER_COUNT);
+
+    /*
+     * The buffer is stored as words, we need to emulate that. Could be
+     * optimized.
+     */
+    uint32_t *ptr =
+        &s->buffer[buf_id * OT_USBDEV_MAX_PACKET_SIZE / sizeof(uint32_t)];
+    while (size >= 4u) {
+        stl_le_p(buf, *ptr++);
+        buf += sizeof(uint32_t);
+        size -= 4u;
+    }
+    /* Handle last incomplete word */
+    if (size >= 1u) {
+        uint32_t val32 = *ptr;
+        *buf++ = (uint8_t)val32;
+        val32 >>= 8u;
+        if (size >= 2u) {
+            *buf++ = (uint8_t)val32;
+            val32 >>= 8u;
+        }
+        if (size >= 3u) {
+            *buf++ = (uint8_t)val32;
+        }
+    }
+}
+
+/*
+ * Update the content of the USBSTAT buffer to reflect the FIFO state
+ * and update the corresponding IRQs.
+ */
+static void ot_usbdev_update_fifos_status(OtUsbdevState *s)
+{
+    uint32_t val = s->regs[R_USBSTAT];
+    val = FIELD_DP32(val, USBSTAT, RX_EMPTY,
+                     (uint32_t)ot_fifo32_is_empty(&s->rx_fifo));
+    val = FIELD_DP32(val, USBSTAT, AV_SETUP_FULL,
+                     (uint32_t)fifo8_is_full(&s->av_setup_fifo));
+    val = FIELD_DP32(val, USBSTAT, RX_DEPTH,
+                     (uint32_t)ot_fifo32_num_used(&s->rx_fifo));
+    val = FIELD_DP32(val, USBSTAT, AV_OUT_FULL,
+                     (uint32_t)fifo8_is_full(&s->av_out_fifo));
+    val = FIELD_DP32(val, USBSTAT, AV_SETUP_DEPTH,
+                     (uint32_t)fifo8_num_used(&s->av_setup_fifo));
+    val = FIELD_DP32(val, USBSTAT, AV_OUT_DEPTH,
+                     (uint32_t)fifo8_num_used(&s->av_out_fifo));
+    s->regs[R_USBSTAT] = val;
+
+    ot_usbdev_update_irqs(s);
+}
+
+/*
+ * Update the device state after a potential VBUS change.
+ *
+ * This function will trigger all necessary state and IRQs changes necessary.
+ * If the device becomes connected/disconnected as a result, the server will
+ * be notified.
+ */
+static void ot_usbdev_update_vbus(OtUsbdevState *s)
+{
+    /* Do nothing if the device is in reset */
+    if (resettable_is_in_reset(OBJECT(s))) {
+        return;
+    }
+
+    /*
+     * In VBUS override mode, VBUS sense is directly equal to
+     * the VBUS gate. Otherwise, it is the AND between the gate
+     * and the host VBUS control.
+     */
+    bool vbus_sense = s->vbus_gate;
+    if (!s->vbus_override) {
+        vbus_sense = vbus_sense && s->usb_server.vbus_connected;
+    }
+
+    bool old_vbus_sense = (bool)FIELD_EX32(s->regs[R_USBSTAT], USBSTAT, SENSE);
+    if (old_vbus_sense == vbus_sense) {
+        return;
+    }
+
+    trace_ot_usbdev_vbus_changed(s->ot_id, vbus_sense);
+
+    s->regs[R_USBSTAT] =
+        FIELD_DP32(s->regs[R_USBSTAT], USBSTAT, SENSE, vbus_sense);
+
+    /* VBUS was turned on */
+    if (vbus_sense) {
+        /* See BFM (bus_connect) */
+
+        /*
+         * If we end up in a non-disconnected state here, something is very
+         * wrong
+         */
+        g_assert(ot_usbdev_get_link_state(s) ==
+                 OT_USBDEV_LINK_STATE_DISCONNECTED);
+        s->regs[R_USBDEV_INTR_STATE] |= USBDEV_INTR_POWERED_MASK;
+
+        if (ot_usbdev_is_enabled(s)) {
+            ot_usbdev_set_raw_link_state(s, OT_USBDEV_LINK_STATE_POWERED);
+            ot_usbdev_server_report_connected(s, true);
+        }
+    }
+    /* VBUS was turned off */
+    else {
+        /* See BFM (bus_disconnect) */
+        if (ot_usbdev_get_link_state(s) != OT_USBDEV_LINK_STATE_DISCONNECTED) {
+            ot_usbdev_set_raw_link_state(s, OT_USBDEV_LINK_STATE_DISCONNECTED);
+            s->regs[R_USBDEV_INTR_STATE] |= USBDEV_INTR_DISCONNECTED_MASK;
+            s->regs[R_USBCTRL] =
+                FIELD_DP32(s->regs[R_USBCTRL], USBCTRL, DEVICE_ADDRESS, 0u);
+
+            ot_usbdev_cancel_all_transfers(s, "VBUS was disconnected");
+            /* If there is no host then any SOF or reset signalling stops. */
+            timer_del(&s->frame_timer);
+            timer_del(&s->bus_reset_timer);
+        }
+    }
+
+    ot_usbdev_update_irqs(s);
+}
+
+/*
+ * Update the VBUS gate.
+ *
+ * Changes will trigger events (see ot_usbdev_update_vbus).
+ *
+ * @gate New value of the gate.
+ */
+static void ot_usbdev_set_vbus_gate(OtUsbdevState *s, bool gate)
+{
+    s->vbus_gate = gate;
+
+    ot_usbdev_update_vbus(s);
+}
+
+/*
+ * Retire any IN packet on the given endpoint.
+ *
+ * Mark any ready packet as pending but not ready and not sending.
+ */
+static void ot_usbdev_retire_in_packets(OtUsbdevState *s, uint8_t ep)
+{
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+
+    uint32_t configin = s->regs[R_CONFIGIN_0 + ep];
+    if ((bool)SHARED_FIELD_EX32(configin, CONFIGIN_RDY)) {
+        configin = SHARED_FIELD_DP32(configin, CONFIGIN_RDY, 0u);
+        configin = SHARED_FIELD_DP32(configin, CONFIGIN_PEND, 1u);
+
+        trace_ot_usbdev_retire_in_packet(s->ot_id, ep);
+    }
+    configin = SHARED_FIELD_DP32(configin, CONFIGIN_SENDING, 0u);
+    s->regs[R_CONFIGIN_0 + ep] = configin;
+}
+
+static uint32_t ot_usbdev_get_frame(OtUsbdevState *s)
+{
+    /*
+     * See logic in the documentation of the OtUsbdevState struct:
+     * - if frame timer is pending, value is frozen
+     * - otherwise, extrapolate based on time
+     */
+    if (timer_pending(&s->frame_timer)) {
+        return s->frozen_frame;
+    }
+    int64_t time_us = qemu_clock_get_us(OT_VIRTUAL_CLOCK);
+    return (uint32_t)(time_us - s->frame0_time_us) / OT_USBDEV_FRAME_TIME_US;
+}
+
+/*
+ * Callback to simulate a start of frame. The timer is only started
+ * when needed (i.e. on bus reset complete and when the device expects
+ * an interrupt).
+ */
+static void ot_usbdev_frame_timer_expired(void *opaque)
+{
+    OtUsbdevState *s = opaque;
+
+    /*
+     * If this is the first SOF after a bus reset, we need to change the link
+     * state.
+     */
+    if (ot_usbdev_get_link_state(s) == OT_USBDEV_LINK_STATE_ACTIVE_NOSOF) {
+        ot_usbdev_set_raw_link_state(s, OT_USBDEV_LINK_STATE_ACTIVE);
+    } else if (ot_usbdev_get_link_state(s) != OT_USBDEV_LINK_STATE_ACTIVE) {
+        /*
+         * The following should not happen but if for some reason we are
+         * not in the active state, ignore.
+         */
+        error_report("%s: %s: SOF timer expired in a non-active state",
+                     __func__, s->ot_id);
+        return;
+    }
+
+    /* Set frame interrupt. */
+    s->regs[R_USBDEV_INTR_STATE] |= USBDEV_INTR_FRAME_MASK;
+    ot_usbdev_update_irqs(s);
+}
+
+/* Schedule a frame timer for the next frame. */
+static void ot_usbdev_schedule_frame_timer(OtUsbdevState *s)
+{
+    /* Do not schedule one if one is pending. */
+    if (timer_pending(&s->frame_timer)) {
+        return;
+    }
+
+    uint32_t cur_frame = ot_usbdev_get_frame(s);
+    /* Find the time at which the next frame will start. */
+    int64_t next_frame_time_us =
+        s->frame0_time_us + (cur_frame + 1u) * OT_USBDEV_FRAME_TIME_US;
+    timer_mod(&s->frame_timer, next_frame_time_us);
+}
+
+/*
+ * Callback to notify bus reset completion. The timer is started
+ * in ot_usbdev_simulate_link_reset.
+ */
+static void ot_usbdev_link_reset_complete(void *opaque)
+{
+    OtUsbdevState *s = opaque;
+
+    trace_ot_usbdev_link_reset(s->ot_id, true);
+
+    if (ot_usbdev_has_vbus(s) && ot_usbdev_is_enabled(s)) {
+        ot_usbdev_set_raw_link_state(s, OT_USBDEV_LINK_STATE_ACTIVE_NOSOF);
+        /*
+         * Record "frame 0 timer" and schedule a timer for frame 1.
+         * We need the timer so that it changes the link state to active.
+         */
+        s->frame0_time_us = qemu_clock_get_us(OT_VIRTUAL_CLOCK);
+        s->frozen_frame = 0u;
+        ot_usbdev_schedule_frame_timer(s);
+    }
+}
+
+/*
+ * Simulate a link reset.
+ *
+ * This function will trigger all necessary state and IRQs changes necessary to
+ * perform a link reset.
+ */
+static void ot_usbdev_simulate_link_reset(OtUsbdevState *s)
+{
+    g_assert(!resettable_is_in_reset(OBJECT(s)));
+    if (timer_pending(&s->bus_reset_timer)) {
+        error_report("%s: %s: Simulating a link reset while a bus reset is "
+                     "already pending!",
+                     __func__, s->ot_id);
+        return;
+    }
+
+    trace_ot_usbdev_link_reset(s->ot_id, false);
+
+    /* We cannot simulate a reset if the device is disconnected! */
+    if (ot_usbdev_get_link_state(s) == OT_USBDEV_LINK_STATE_DISCONNECTED) {
+        trace_ot_usbdev_server_protocol_error(s->ot_id,
+                                              "link reset while disconnected");
+        return;
+    }
+
+    /* See BFM (bus_reset) */
+    s->regs[R_USBCTRL] =
+        FIELD_DP32(s->regs[R_USBCTRL], USBCTRL, DEVICE_ADDRESS, 0u);
+    s->regs[R_USBDEV_INTR_STATE] |= USBDEV_INTR_LINK_RESET_MASK;
+    ot_usbdev_update_irqs(s);
+
+    for (unsigned ep = 0; ep < USBDEV_PARAM_N_ENDPOINTS; ep++) {
+        /* Cancel any pending IN packets */
+        ot_usbdev_retire_in_packets(s, ep);
+    }
+    ot_usbdev_cancel_all_transfers(s, "cancelled by link reset");
+
+    /* Stop any frame timer pending. */
+    timer_del(&s->frame_timer);
+
+    /*
+     * On real hardware, reset signalling typically takes several milliseconds
+     * so we kick a timer to trigger the link state change after the end of
+     * signalling.
+     */
+    int64_t now = qemu_clock_get_us(OT_VIRTUAL_CLOCK);
+    timer_mod(&s->bus_reset_timer, now + OT_USBDEV_BUS_RESET_TIME_US);
+}
+
+/*
+ * Simulate the reception of a SETUP token followed by an 8-byte
+ * DATA packet containing the SETUP packet.
+ *
+ * Note: when called, the trace_ot_usbdev_setup event has not been called yet.
+ */
+static void ot_usbdev_simulate_setup(OtUsbdevState *s, uint8_t ep,
+                                     uint8_t setup[OT_USBDEV_SETUP_PACKET_SIZE])
+{
+    g_assert(!resettable_is_in_reset(OBJECT(s)));
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+
+    /* We cannot simulate a reset if the device is disconnected! */
+    if (ot_usbdev_get_link_state(s) == OT_USBDEV_LINK_STATE_DISCONNECTED) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "SETUP packet while disconnected");
+        trace_ot_usbdev_setup(s->ot_id, ep,
+                              "ignored (device is not connected)");
+        return;
+    }
+
+    /* See BFM (token_packet) */
+
+    /* A SETUP packet resets the data toggles of enabled endpoints */
+    if (ot_usbdev_is_ep_out_enabled(s, ep)) {
+        s->regs[R_OUT_DATA_TOGGLE] &=
+            ~FIELD_DP32(0u, OUT_DATA_TOGGLE, STATUS, 1u << ep);
+    }
+    if (ot_usbdev_is_ep_in_enabled(s, ep)) {
+        s->regs[R_IN_DATA_TOGGLE] |=
+            FIELD_DP32(0u, IN_DATA_TOGGLE, STATUS, 1u << ep);
+    }
+
+    /* Drop SETUP if EP is not enabled or RX is not enabled for SETUP. */
+    if (!ot_usbdev_is_ep_out_enabled(s, ep)) {
+        /* Packet is silently ignored without triggering an error. */
+        trace_ot_usbdev_setup(s->ot_id, ep,
+                              "dropped (device has not enabled OUT endpoint)");
+        return;
+    }
+
+    /* See BFM (data_packet and out_packet) */
+    if (!ot_usbdev_is_ep_setup_rx_enabled(s, ep)) {
+        /* Packet is silently ignored without triggering an error. */
+        trace_ot_usbdev_setup(
+            s->ot_id, ep, "dropped (device has not enabled SETUP reception)");
+        return;
+    }
+    if (fifo8_is_empty(&s->av_setup_fifo) || ot_fifo32_is_full(&s->rx_fifo)) {
+        trace_ot_usbdev_setup(s->ot_id, ep,
+                              "dropped (AV SETUP FIFO empty or RX FIFO full)");
+        s->regs[R_USBDEV_INTR_STATE] |= USBDEV_INTR_LINK_OUT_ERR_MASK;
+        ot_usbdev_update_irqs(s);
+        return;
+    }
+
+    trace_ot_usbdev_setup(s->ot_id, ep, "accepted");
+
+    /*
+     * Obtain the next SETUP buffer ID and write the SETUP packet to the buffer
+     */
+    uint8_t buf_id = fifo8_pop(&s->av_setup_fifo);
+    ot_usbdev_write_buffer(s, buf_id, setup, OT_USBDEV_SETUP_PACKET_SIZE);
+
+    /* Create and push an entry in the RX FIFO */
+    uint32_t rx_fifo_entry = 0u;
+    rx_fifo_entry = FIELD_DP32(rx_fifo_entry, RXFIFO, BUFFER, buf_id);
+    rx_fifo_entry = FIELD_DP32(rx_fifo_entry, RXFIFO, SETUP, 1u);
+    rx_fifo_entry = FIELD_DP32(rx_fifo_entry, RXFIFO, EP, ep);
+    rx_fifo_entry =
+        FIELD_DP32(rx_fifo_entry, RXFIFO, SIZE, OT_USBDEV_SETUP_PACKET_SIZE);
+    ot_fifo32_push(&s->rx_fifo, rx_fifo_entry);
+
+    /* clear any STALL condition */
+    s->regs[R_OUT_STALL] &= ~(1u << ep);
+    s->regs[R_IN_STALL] &= ~(1u << ep);
+
+    /* Cancel any pending IN packet on this endpoint */
+    ot_usbdev_retire_in_packets(s, ep);
+
+    /* Cancel any transfer on the server side on this endpoint */
+    ot_usbdev_complete_transfer_in(s, ep, OT_USBDEV_SERVER_STATUS_CANCELLED,
+                                   "cancelled by setup packet");
+    ot_usbdev_complete_transfer_out(s, ep, OT_USBDEV_SERVER_STATUS_CANCELLED,
+                                    "cancelled by setup packet");
+
+    ot_usbdev_update_fifos_status(s);
+    ot_usbdev_update_irqs(s);
+}
+
+/*
+ * Complete an IN transfer and notify the host.
+ *
+ * If there is no transfer pending on this endpoint, this function does nothing.
+ *
+ * @epnum Endpoint number
+ * @status Status of the transfer (sent to the host)
+ * @msg Details on the transfer status (using for tracing only)
+ */
+void ot_usbdev_complete_transfer_in(OtUsbdevState *s, uint8_t epnum,
+                                    OtUsbdevServerTransferStatus status,
+                                    const char *msg)
+{
+    g_assert(epnum < USBDEV_PARAM_N_ENDPOINTS);
+    OtUsbdevServer *server = &s->usb_server;
+    OtUsbdevServerEpInXfer *xfer = &server->ep[epnum].in;
+
+    /* Nothing to do if no transfer is pending */
+    if (!xfer->pending) {
+        return;
+    }
+
+    uint32_t xfered_len = xfer->xfer_len - xfer->recv_rem;
+    ot_usbdev_server_complete_transfer(s, xfer->id, status, xfered_len,
+                                       xfer->xfer_buf, xfered_len, msg);
+
+    /* cleanup */
+    g_free(xfer->xfer_buf);
+    memset(xfer, 0, sizeof(OtUsbdevServerEpInXfer));
+}
+
+/*
+ * Complete an OUT transfer and notify the host.
+ *
+ * If there is no transfer pending on this endpoint, this function does nothing.
+ *
+ * @epnum Endpoint number
+ * @status Status of the transfer (sent to the host)
+ * @msg Details on the transfer status (using for tracing only)
+ */
+void ot_usbdev_complete_transfer_out(OtUsbdevState *s, uint8_t epnum,
+                                     OtUsbdevServerTransferStatus status,
+                                     const char *msg)
+{
+    g_assert(epnum < USBDEV_PARAM_N_ENDPOINTS);
+    OtUsbdevServer *server = &s->usb_server;
+    OtUsbdevServerEpOutXfer *xfer = &server->ep[epnum].out;
+
+    /* Nothing to do if no transfer is pending */
+    if (!xfer->pending) {
+        return;
+    }
+
+    uint32_t xfered_len = xfer->xfer_len - xfer->send_rem;
+    ot_usbdev_server_complete_transfer(s, xfer->id, status, xfered_len, NULL,
+                                       0u, msg);
+
+    /* cleanup */
+    g_free(xfer->xfer_buf);
+    memset(xfer, 0, sizeof(OtUsbdevServerEpOutXfer));
+}
+
+/*
+ * Cancel all pending transfers
+ */
+void ot_usbdev_cancel_all_transfers(OtUsbdevState *s, const char *reason)
+{
+    for (unsigned ep = 0; ep < USBDEV_PARAM_N_ENDPOINTS; ep++) {
+        /* Cancel all pending transfers on the server */
+        ot_usbdev_complete_transfer_in(s, ep, OT_USBDEV_SERVER_STATUS_CANCELLED,
+                                       reason);
+        ot_usbdev_complete_transfer_out(s, ep,
+                                        OT_USBDEV_SERVER_STATUS_CANCELLED,
+                                        reason);
+    }
+}
+
+/*
+ * Cancel a specific transfer by ID.
+ * Return true if a matching transfer was found, and false otherwise.
+ */
+static bool ot_usbdev_cancel_transfer_by_id(OtUsbdevState *s, uint32_t xfer_id,
+                                            const char *reason)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    for (unsigned ep = 0; ep < USBDEV_PARAM_N_ENDPOINTS; ep++) {
+        if (server->ep[ep].in.pending && server->ep[ep].in.id == xfer_id) {
+            ot_usbdev_complete_transfer_in(s, ep,
+                                           OT_USBDEV_SERVER_STATUS_CANCELLED,
+                                           reason);
+            return true;
+        }
+        if (server->ep[ep].out.pending && server->ep[ep].out.id == xfer_id) {
+            ot_usbdev_complete_transfer_out(s, ep,
+                                            OT_USBDEV_SERVER_STATUS_CANCELLED,
+                                            reason);
+            return true;
+        }
+    }
+    return false;
+}
+
+/*
+ * Try to make progress with an IN transfer on this endpoint.
+ *
+ * This function will check if the necessary conditions are present
+ * to send a new packet to the host and trigger the necessary events.
+ * If a STALL condition is detected, the transfer will automatically
+ * be cancelled and the host will be notified.
+ * If a NAK condition is detected (e.g. host has a pending transfer
+ * but the device has not yet given a packet for transmission), this
+ * function will do nothing.
+ */
+static void ot_usbdev_advance_transfer_in(OtUsbdevState *s, uint8_t epnum)
+{
+    g_assert(epnum < USBDEV_PARAM_N_ENDPOINTS);
+    /* See BFM (in_packet and handshake_packet) */
+
+    /* Nothing to do if there is no pending transfer */
+    OtUsbdevServer *server = &s->usb_server;
+    OtUsbdevServerEpInXfer *xfer = &server->ep[epnum].in;
+    if (!xfer->pending) {
+        return;
+    }
+
+    /*
+     * If the endpoint is not enabled, the device will silently ignore the
+     * packet, causing an error.
+     */
+    if (!ot_usbdev_is_ep_in_enabled(s, epnum)) {
+        ot_usbdev_complete_transfer_in(s, epnum, OT_USBDEV_SERVER_STATUS_ERROR,
+                                       "endpoint IN not enabled");
+        return;
+    }
+
+    /* Check for STALL */
+    if (ot_usbdev_is_ep_in_stalled(s, epnum)) {
+        ot_usbdev_complete_transfer_in(s, epnum,
+                                       OT_USBDEV_SERVER_STATUS_STALLED,
+                                       "stalled by device");
+        return;
+    }
+
+    hwaddr reg = R_CONFIGIN_0 + epnum;
+    uint32_t configin = s->regs[reg];
+    bool ready = (bool)SHARED_FIELD_EX32(configin, CONFIGIN_RDY);
+    uint32_t pkt_size = SHARED_FIELD_EX32(configin, CONFIGIN_SIZE);
+    uint8_t buf_id = (uint8_t)SHARED_FIELD_EX32(configin, CONFIGIN_BUFFER);
+
+    /* Nothing to do if no packet is ready */
+    if (!ready) {
+        return;
+    }
+
+    /*
+     * Make sure buffer ID is valid. With the current constants, this check is
+     * always true but potentially could before false if the IP became more
+     * parametrized.
+     */
+    if (buf_id >= OT_USBDEV_BUFFER_COUNT) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: write to CONFIGIN%d with invalid BUFFER (%u)\n",
+                      __func__, s->ot_id, epnum, buf_id);
+        return;
+    }
+
+    trace_ot_usbdev_packet_sent(s->ot_id, epnum, buf_id, pkt_size);
+
+    /* Mark the packet as sent and acknowledged by the host */
+    configin = SHARED_FIELD_DP32(configin, CONFIGIN_RDY, 0u);
+    s->regs[reg] = configin;
+    s->regs[R_IN_DATA_TOGGLE] ^=
+        FIELD_DP32(0u, IN_DATA_TOGGLE, STATUS, 1u << epnum);
+    s->regs[R_IN_SENT] |= 1u << epnum;
+    ot_usbdev_update_irqs(s);
+
+    /* Check for overflow */
+    if (pkt_size > xfer->max_packet_size) {
+        ot_usbdev_complete_transfer_in(
+            s, epnum, OT_USBDEV_SERVER_STATUS_ERROR,
+            "device sent packet bigger than max packet size");
+        return;
+    }
+    if (pkt_size > xfer->recv_rem) {
+        ot_usbdev_complete_transfer_in(s, epnum, OT_USBDEV_SERVER_STATUS_ERROR,
+                                       "device sent more data than expected");
+        return;
+    }
+
+    /* Copy data and advance buffers */
+    ot_usbdev_read_buffer(s, buf_id, xfer->recv_buf, pkt_size);
+
+    xfer->recv_buf += pkt_size;
+    xfer->recv_rem -= pkt_size;
+
+    /* Handle completion */
+    if (pkt_size < xfer->max_packet_size || xfer->recv_rem == 0u) {
+        ot_usbdev_complete_transfer_in(s, epnum,
+                                       OT_USBDEV_SERVER_STATUS_SUCCESS,
+                                       "success");
+        return;
+    }
+}
+
+/*
+ * Try to make progress with an OUT transfer on this endpoint.
+ *
+ * This function will check if the necessary conditions are present
+ * to receive a new packet from the host and trigger the necessary events.
+ * If a STALL condition is detected, the transfer will automatically
+ * be cancelled and the host will be notified.
+ * If a NAK condition is detected (e.g. the host has no transfer pending,
+ * or the device has not enabled reception), this
+ * function will do nothing.
+ *
+ * Return true if we were able to make progress (receive a packet), false
+ * otherwise.
+ */
+static bool ot_usbdev_advance_transfer_out(OtUsbdevState *s, uint8_t epnum)
+{
+    g_assert(epnum < USBDEV_PARAM_N_ENDPOINTS);
+    /* See BFM (out_packet) */
+
+    /* Nothing to do if there is no pending transfer */
+    OtUsbdevServer *server = &s->usb_server;
+    OtUsbdevServerEpOutXfer *xfer = &server->ep[epnum].out;
+    if (!xfer->pending) {
+        return false;
+    }
+
+    /*
+     * If the endpoint OUT is not enabled, the device will silently ignore the
+     * packet, causing an error.
+     */
+    if (!ot_usbdev_is_ep_out_enabled(s, epnum)) {
+        ot_usbdev_complete_transfer_out(s, epnum, OT_USBDEV_SERVER_STATUS_ERROR,
+                                        "endpoint OUT not enabled");
+        return false;
+    }
+
+    /* Check for STALL */
+    if (ot_usbdev_is_ep_out_stalled(s, epnum)) {
+        ot_usbdev_complete_transfer_out(s, epnum,
+                                        OT_USBDEV_SERVER_STATUS_STALLED,
+                                        "stalled by device");
+        s->regs[R_USBDEV_INTR_STATE] |= USBDEV_INTR_LINK_OUT_ERR_MASK;
+        ot_usbdev_update_irqs(s);
+        return false;
+    }
+
+    /*
+     * Only accept the DATA packet if the endpoint is enabled, and there is
+     * buffer available and there is space in the RX FIFO. The last entry of the
+     * FIFO is reserved for SETUP packets.
+     */
+    if (!ot_usbdev_is_ep_out_rxenabled(s, epnum) ||
+        fifo8_is_empty(&s->av_out_fifo) ||
+        ot_fifo32_num_free(&s->rx_fifo) <= 1u) {
+        /* Notify the software about the error */
+        s->regs[R_USBDEV_INTR_STATE] |= USBDEV_INTR_LINK_OUT_ERR_MASK;
+        ot_usbdev_update_irqs(s);
+        /* "NAK" packet, OUT transfer will be retried */
+        return false;
+    }
+
+    /* Write data to buffer and update transfer status */
+    uint8_t buf_id = fifo8_pop(&s->av_out_fifo);
+    uint32_t size = MIN((uint32_t)xfer->max_packet_size, xfer->send_rem);
+    ot_usbdev_write_buffer(s, buf_id, xfer->send_buf, (size_t)size);
+    xfer->send_buf += size;
+    xfer->send_rem -= size;
+
+    /* Create and push an entry in the RX FIFO */
+    uint32_t rx_fifo_entry = 0u;
+    rx_fifo_entry = FIELD_DP32(rx_fifo_entry, RXFIFO, BUFFER, buf_id);
+    rx_fifo_entry = FIELD_DP32(rx_fifo_entry, RXFIFO, SETUP, 0u);
+    rx_fifo_entry = FIELD_DP32(rx_fifo_entry, RXFIFO, EP, epnum);
+    rx_fifo_entry = FIELD_DP32(rx_fifo_entry, RXFIFO, SIZE, size);
+    ot_fifo32_push(&s->rx_fifo, rx_fifo_entry);
+
+    s->regs[R_OUT_DATA_TOGGLE] ^=
+        FIELD_DP32(0u, IN_DATA_TOGGLE, STATUS, 1u << epnum);
+
+    trace_ot_usbdev_packet_received(s->ot_id, epnum, buf_id, size);
+
+    /* Disable RX if auto-NAK on OUT is set. */
+    if (ot_usbdev_is_set_nak_out_enabled(s, epnum)) {
+        s->regs[R_RXENABLE_OUT] &= ~(1u << epnum);
+    }
+
+    ot_usbdev_update_fifos_status(s);
+    ot_usbdev_update_irqs(s);
+
+    /* Handle completion */
+    if (xfer->send_rem == 0 && !xfer->send_zlp) {
+        ot_usbdev_complete_transfer_out(s, epnum,
+                                        OT_USBDEV_SERVER_STATUS_SUCCESS,
+                                        "success");
+        return true;
+    }
+    if (xfer->send_rem == 0 && xfer->send_zlp) {
+        /*
+         * If we have sent everything and a ZLP is requested, go for a last
+         * round
+         */
+        xfer->send_zlp = false;
+    }
+
+    return true;
+}
+
+/*
+ * Update the value of the USBCTRL register.
+ *
+ * This function will update the USBCTRL register after a write and
+ * trigger the necessary changes if the ENABLE bit is changed. If
+ * as a result of this change the device becomes (dis)connected,
+ * the server will be notified.
+ *
+ * @val32 New value
+ */
+static void ot_usbdev_write_usbctrl(OtUsbdevState *s, uint32_t val32)
+{
+    bool old_enable = ot_usbdev_is_enabled(s);
+    uint8_t old_addr = ot_usbdev_get_address(s);
+
+    /* @todo Handle resume_link_active eventually, this is a W/O field */
+    s->regs[R_USBCTRL] = val32 & USBDEV_USBCTRL_R_MASK;
+
+    uint8_t new_addr = ot_usbdev_get_address(s);
+    if (old_addr != new_addr) {
+        trace_ot_usbdev_address_changed(s->ot_id, new_addr);
+    }
+
+    bool enable = ot_usbdev_is_enabled(s);
+    if (enable == old_enable) {
+        return;
+    }
+
+    trace_ot_usbdev_enable_changed(s->ot_id, enable);
+
+    /* Device has been enabled */
+    if (enable) {
+        /* See BFM (set_enable) */
+        g_assert(ot_usbdev_get_link_state(s) ==
+                 OT_USBDEV_LINK_STATE_DISCONNECTED);
+        if (ot_usbdev_has_vbus(s)) {
+            ot_usbdev_set_raw_link_state(s, OT_USBDEV_LINK_STATE_POWERED);
+            ot_usbdev_server_report_connected(s, true);
+        }
+    } else {
+        /* See BFM (set_enable) */
+        ot_usbdev_set_raw_link_state(s, OT_USBDEV_LINK_STATE_DISCONNECTED);
+        s->regs[R_USBDEV_INTR_STATE] |= USBDEV_INTR_DISCONNECTED_MASK;
+        s->regs[R_USBCTRL] =
+            FIELD_DP32(s->regs[R_USBCTRL], USBCTRL, DEVICE_ADDRESS, 0u);
+
+        if (ot_usbdev_has_vbus(s)) {
+            ot_usbdev_server_report_connected(s, false);
+        }
+    }
+
+    /*
+     * Status interrupts are only active when enabled, we may need to update
+     * them
+     */
+    ot_usbdev_update_status_irqs(s);
+    ot_usbdev_update_irqs(s);
+}
+
+/*
+ * Update the value of a CONFIGINx register.
+ *
+ * This function will update the CONFIGINx register after a write and
+ * trigger the necessary changes. If as a result of this change a transfer
+ * completes, the server will be notified.
+ *
+ * @reg Register index
+ * @val32 New value
+ */
+static void ot_usbdev_write_configin(OtUsbdevState *s, hwaddr reg,
+                                     uint32_t val32)
+{
+    uint8_t ep = (uint8_t)(reg - R_CONFIGIN_0);
+    g_assert(ep < USBDEV_PARAM_N_ENDPOINTS);
+
+    /*
+     * @todo clarify what writing 1 to SENDING is supposed to do since this
+     * is a hardware signal and not a status bit, doc is unclear.
+     * In this emulated driver, the SENDING bit is never set by the code.
+     */
+
+    /* clear RW1C fields */
+    uint32_t rw1c = val32 & USBDEV_CONFIGIN_RW1C_MASK;
+    s->regs[reg] &= ~rw1c;
+    /* set RW fields */
+    s->regs[reg] &= USBDEV_CONFIGIN_RW1C_MASK;
+    s->regs[reg] |= val32 & ~USBDEV_CONFIGIN_RW1C_MASK;
+
+    ot_usbdev_advance_transfer_in(s, ep);
+}
+
+/*
+ * Update the transfers pending on one or more endpoints whose status
+ * has changed.
+ *
+ * After changing the status of an endpoint (e.g. (un)stall, nak,
+ * RX/TX enable), this function must be called to re-evaluate whether
+ * the pending transfers can make progress. Only endpoints set in the
+ * mask will be considered.
+ *
+ * @dir_in True for IN transfers, false for OUT.
+ * @ep_mask The n-th bit represents the n-th endpoint.
+ *
+ */
+static void ot_usbdev_update_ep_xfers(OtUsbdevState *s, bool dir_in,
+                                      uint32_t ep_mask)
+{
+    uint8_t last_ep_out_to_progress = 0;
+    /* For each disabled ep, update the transfer to trigger an error */
+    for (uint8_t _ep = 0u; _ep < USBDEV_PARAM_N_ENDPOINTS; _ep++) {
+        uint8_t ep = _ep;
+        /* For OUT transfers, we do some round-robin scheduling */
+        if (!dir_in) {
+            ep = (_ep + s->next_ep_out_sched_xfer) % USBDEV_PARAM_N_ENDPOINTS;
+        }
+
+        if (((ep_mask >> ep) & 1u) == 0u) {
+            continue;
+        }
+        if (dir_in) {
+            ot_usbdev_advance_transfer_in(s, ep);
+        } else {
+            if (ot_usbdev_advance_transfer_out(s, ep)) {
+                last_ep_out_to_progress = ep;
+            }
+        }
+    }
+    /*
+     * For OUT transfers, set the next endpoint to consider to be the one
+     * right after the last one to make progress.
+     */
+    if (!dir_in) {
+        s->next_ep_out_sched_xfer =
+            (last_ep_out_to_progress + 1u) % USBDEV_PARAM_N_ENDPOINTS;
+    }
+}
+
+/*
+ * Handle write to register which changes whether an endpoint is
+ * enabled or not. Trigger the necessary changes to transfers if any.
+ *
+ * This function will update the content of the register with the given value.
+ *
+ * @reg One of R_EP_IN_ENABLE, R_EP_OUT_ENABLE, R_RXENABLE_SETUP or
+ * R_RXENABLE_OUT
+ * @val32 New value of the register.
+ */
+static void
+ot_usbdev_update_ep_enabled(OtUsbdevState *s, hwaddr reg, uint32_t val32)
+{
+    /* Find which endpoints have been disabled */
+    uint32_t disabled_ep = s->regs[reg] & ~val32;
+    s->regs[reg] = val32 & USBDEV_ALL_EP_MASK;
+
+    bool dir_in = reg == R_EP_IN_ENABLE;
+    /*
+     * Only update disabled endpoints: the endpoints which became enabled
+     * cannot have any pending transfers since ot_usbdev_advance_transfer_out
+     * automatically completes transfers on disabled endpoints.
+     */
+    ot_usbdev_update_ep_xfers(s, dir_in, disabled_ep);
+}
+
+/*
+ * Handle write to register which changes whether an endpoint is
+ * stalled or not. Trigger the necessary changes to transfers if any.
+ *
+ * This function will update the content of the register with the given value.
+ *
+ * @reg One of  R_OUT_STALL or R_IN_STALL:
+ * @val32 New value of the register.
+ */
+static void
+ot_usbdev_update_ep_stalled(OtUsbdevState *s, hwaddr reg, uint32_t val32)
+{
+    /* Find which endpoints have been stalled */
+    uint32_t stalled_ep = (~s->regs[reg] & val32) & USBDEV_ALL_EP_MASK;
+    s->regs[reg] = val32 & USBDEV_ALL_EP_MASK;
+
+    bool dir_in = reg == R_IN_STALL;
+    /*
+     * Only update stalled endpoints: the endpoints which became unstalled
+     * cannot have any pending transfers since ot_usbdev_advance_transfer_out
+     * automatically completes transfers on stalled endpoints.
+     */
+    ot_usbdev_update_ep_xfers(s, dir_in, stalled_ep);
+}
+
+/*
+ * Register read/write handling
+ */
+
+static uint64_t ot_usbdev_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtUsbdevState *s = opaque;
+    (void)size;
+    uint32_t val32;
+
+    hwaddr reg = R32_OFF(addr);
+    switch (reg) {
+    /* Reads with no side-effects */
+    case R_PHY_CONFIG:
+    case R_USBDEV_INTR_STATE:
+    case R_USBDEV_INTR_ENABLE:
+    case R_USBCTRL:
+    case R_EP_OUT_ENABLE:
+    case R_EP_IN_ENABLE:
+    case R_AVOUTBUFFER:
+    case R_AVSETUPBUFFER:
+    case R_RXENABLE_SETUP:
+    case R_RXENABLE_OUT:
+    case R_SET_NAK_OUT:
+    case R_IN_SENT:
+    case R_OUT_STALL:
+    case R_IN_STALL:
+    case R_CONFIGIN_0:
+    case R_CONFIGIN_1:
+    case R_CONFIGIN_2:
+    case R_CONFIGIN_3:
+    case R_CONFIGIN_4:
+    case R_CONFIGIN_5:
+    case R_CONFIGIN_6:
+    case R_CONFIGIN_7:
+    case R_CONFIGIN_8:
+    case R_CONFIGIN_9:
+    case R_CONFIGIN_10:
+    case R_CONFIGIN_11:
+    case R_OUT_ISO:
+    case R_IN_ISO:
+    case R_OUT_DATA_TOGGLE:
+    case R_IN_DATA_TOGGLE:
+    case R_PHY_PINS_SENSE:
+    case R_PHY_PINS_DRIVE:
+    case R_WAKE_CONTROL:
+    case R_WAKE_EVENTS:
+    case R_FIFO_CTRL:
+    case R_COUNT_OUT:
+    case R_COUNT_IN:
+    case R_COUNT_NODATA_IN:
+    case R_COUNT_ERRORS:
+        val32 = s->regs[reg];
+        break;
+    case R_USBSTAT:
+        /*
+         * We extrapolate the frame counter on each read to avoid frequent
+         * updates. Note that the field in the register can wrap around but we
+         * internally keep track of the frame counter with all bits, so the
+         * following code will truncate the value which is the correct
+         * behaviour.
+         */
+        val32 =
+            FIELD_DP32(s->regs[reg], USBSTAT, FRAME, ot_usbdev_get_frame(s));
+        break;
+    case R_RXFIFO:
+        if (ot_fifo32_is_empty(&s->rx_fifo)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: read to RXFIFO but FIFO is empty\n",
+                          __func__, s->ot_id);
+            val32 = 0u;
+        } else {
+            val32 = ot_fifo32_pop(&s->rx_fifo);
+            trace_ot_usbdev_pop_rx_fifo(s->ot_id, val32);
+            ot_usbdev_update_fifos_status(s);
+            /* Potentially all endpoints are now able to receive some data. */
+            if (ot_fifo32_num_free(&s->rx_fifo) == 1u) {
+                ot_usbdev_update_ep_xfers(s, /* dir_in */ false,
+                                          USBDEV_ALL_EP_MASK);
+            }
+        }
+        break;
+    case R_USBDEV_INTR_TEST:
+    case R_ALERT_TEST:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s Read to W/O register 0x%02x (%s)\n", __func__,
+                      s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        val32 = 0u;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        val32 = 0u;
+        break;
+    }
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_usbdev_io_read_out(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                                pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_usbdev_write(void *opaque, hwaddr addr, uint64_t val64,
+                            unsigned size)
+{
+    OtUsbdevState *s = opaque;
+    (void)size;
+    uint32_t val32 = (uint32_t)val64;
+
+    hwaddr reg = R32_OFF(addr);
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_usbdev_io_write(s->ot_id, (uint32_t)addr, REG_NAME(reg), val32,
+                             pc);
+
+    switch (reg) {
+    case R_USBDEV_INTR_STATE:
+        val32 &= USBDEV_INTR_RW1C_MASK;
+        /*
+         * If the frame interrupt state was previously not clear and now becomes
+         * cleared, it means that the device will now be able to observe when
+         * the next SOF arrives. Inbetween now and that time, we must ensure
+         * that the frame counter stays frozen. See explanation in OtUsbdevState
+         * struct.
+         */
+        if ((s->regs[reg] & USBDEV_INTR_FRAME_MASK) != 0u &&
+            (val32 & USBDEV_INTR_FRAME_MASK) != 0u) {
+            s->frozen_frame = ot_usbdev_get_frame(s);
+            /* Schedule a frame timer to unfreeze. This is a no-op if one is
+             * already pending. */
+            ot_usbdev_schedule_frame_timer(s);
+        }
+        s->regs[reg] &= ~val32;
+        ot_usbdev_update_irqs(s);
+        break;
+    case R_USBDEV_INTR_ENABLE:
+        val32 &= USBDEV_INTR_MASK;
+        s->regs[reg] = val32;
+        ot_usbdev_update_irqs(s);
+        break;
+    case R_USBDEV_INTR_TEST:
+        val32 &= USBDEV_INTR_MASK;
+        s->regs[R_USBDEV_INTR_STATE] |= val32;
+        ot_usbdev_update_irqs(s);
+        break;
+    case R_ALERT_TEST:
+        val32 &= R_ALERT_TEST_FATAL_FAULT_MASK;
+        /* Use the register to record alerts sets */
+        s->regs[R_ALERT_TEST] = val32;
+        ot_usbdev_update_alerts(s);
+        break;
+    case R_RXFIFO:
+    case R_USBSTAT:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: write to R/O register 0x%02x"
+                      " (%s)\n",
+                      __func__, s->ot_id, (uint32_t)addr, REG_NAME(reg));
+        break;
+    case R_PHY_CONFIG:
+        /* @todo mask against actual fields? */
+        s->regs[R_PHY_CONFIG] = val32;
+        break;
+    case R_USBCTRL:
+        ot_usbdev_write_usbctrl(s, val32);
+        break;
+    case R_EP_IN_ENABLE:
+    case R_EP_OUT_ENABLE:
+    case R_RXENABLE_SETUP:
+    case R_RXENABLE_OUT:
+        ot_usbdev_update_ep_enabled(s, reg, val32);
+        break;
+    case R_OUT_STALL:
+    case R_IN_STALL:
+        ot_usbdev_update_ep_stalled(s, reg, val32);
+        break;
+    case R_AVOUTBUFFER:
+        if (fifo8_is_full(&s->av_out_fifo)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: write to AVOUTBUFFER but FIFO is full\n",
+                          __func__, s->ot_id);
+        } else {
+            uint8_t buf_id = (uint8_t)FIELD_EX32(val32, AVOUTBUFFER, BUFFER);
+            fifo8_push(&s->av_out_fifo, buf_id);
+            trace_ot_usbdev_push_av_out_buffer(s->ot_id, buf_id);
+            ot_usbdev_update_fifos_status(s);
+            /* Potentially all endpoints are now able to receive some data. */
+            if (fifo8_num_used(&s->av_out_fifo) == 1u) {
+                ot_usbdev_update_ep_xfers(s, /* dir_in */ false,
+                                          USBDEV_ALL_EP_MASK);
+            }
+        }
+        break;
+    case R_AVSETUPBUFFER:
+        if (fifo8_is_full(&s->av_setup_fifo)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: write to AVSETUPBUFFER but FIFO is full\n",
+                          __func__, s->ot_id);
+        } else {
+            uint8_t buf_id = (uint8_t)FIELD_EX32(val32, AVSETUPBUFFER, BUFFER);
+            fifo8_push(&s->av_setup_fifo, buf_id);
+            trace_ot_usbdev_push_av_setup_buffer(s->ot_id, buf_id);
+            ot_usbdev_update_fifos_status(s);
+        }
+        break;
+    case R_CONFIGIN_0:
+    case R_CONFIGIN_1:
+    case R_CONFIGIN_2:
+    case R_CONFIGIN_3:
+    case R_CONFIGIN_4:
+    case R_CONFIGIN_5:
+    case R_CONFIGIN_6:
+    case R_CONFIGIN_7:
+    case R_CONFIGIN_8:
+    case R_CONFIGIN_9:
+    case R_CONFIGIN_10:
+    case R_CONFIGIN_11:
+        ot_usbdev_write_configin(s, reg, val32);
+        break;
+    case R_IN_SENT:
+        /* register is rw1c */
+        s->regs[reg] &= ~val32;
+        break;
+    case R_SET_NAK_OUT:
+        s->regs[reg] = val32;
+        break;
+    case R_OUT_ISO:
+    case R_IN_ISO:
+    case R_OUT_DATA_TOGGLE:
+    case R_IN_DATA_TOGGLE:
+    case R_PHY_PINS_SENSE:
+    case R_PHY_PINS_DRIVE:
+    case R_WAKE_CONTROL:
+    case R_WAKE_EVENTS:
+    case R_FIFO_CTRL:
+    case R_COUNT_OUT:
+    case R_COUNT_IN:
+    case R_COUNT_NODATA_IN:
+    case R_COUNT_ERRORS:
+        s->regs[reg] = val32;
+        qemu_log_mask(LOG_UNIMP, "%s: %s: %s is not supported\n", __func__,
+                      s->ot_id, REG_NAME(reg));
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s Bad offset 0x%02x\n", __func__,
+                      s->ot_id, (uint32_t)addr);
+        break;
+    }
+}
+
+static uint64_t ot_usbdev_buffer_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OtUsbdevState *s = opaque;
+    (void)size;
+
+    hwaddr word = R32_OFF(addr);
+    uint32_t val32 = s->buffer[word];
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_usbdev_io_buffer_read_out(s->ot_id, (uint32_t)addr, val32, pc);
+
+    return (uint64_t)val32;
+}
+
+static void ot_usbdev_buffer_write(void *opaque, hwaddr addr, uint64_t val64,
+                                   unsigned size)
+{
+    OtUsbdevState *s = opaque;
+    (void)size;
+    uint32_t val32 = val64;
+
+    hwaddr word = R32_OFF(addr);
+    s->buffer[word] = val32;
+
+    uint32_t pc = ibex_get_current_pc();
+    trace_ot_usbdev_io_buffer_write(s->ot_id, (uint32_t)addr, val32, pc);
+}
+
+/*
+ * USB server
+ */
+static void ot_usbdev_server_reset_recv_state(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    /* cleanup previous state */
+    g_free(server->recv_data);
+    server->recv_data = NULL;
+
+    server->recv_state = OT_USBDEV_SERVER_RECV_WAIT_HEADER;
+    server->recv_rem = sizeof(server->recv_pkt);
+    server->recv_buf = (uint8_t *)&server->recv_pkt;
+}
+
+/*
+ * Open a session with the server.
+ *
+ * This function will reset the server state to start a new session.
+ */
+static void ot_usbdev_server_open(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+    server->client_connected = true;
+    server->vbus_connected = false;
+    server->hello_done = false;
+    ot_usbdev_server_reset_recv_state(s);
+
+    ot_usbdev_update_vbus(s);
+}
+
+/*
+ * Close a session with the server.
+ *
+ * In particular, if VBUS is still on, it will be turned off by this call,
+ * which can trigger events on the device side.
+ */
+static void ot_usbdev_server_close(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+    server->client_connected = false;
+    server->vbus_connected = false;
+
+    ot_usbdev_update_vbus(s);
+}
+
+/*
+ * Send a message to the client.
+ *
+ * To avoid an allocation, this function supports sending the payload
+ * data in two segments, represented by two buffers (data0 and data1).
+ * Any buffer with size zero will be ignored.
+ *
+ * @todo This function must be non-blocking, clarify if that's really
+ * the case.
+ *
+ * @s Device state
+ * @cmd Command
+ * @id Packet ID
+ * @data0 First part of the payload data (can be NULL if size0 is set)
+ * @data0 Size of the first part of the payload data
+ * @data1 Second part of the payload data (can be NULL if size1 is set)
+ * @data1 Size of the second part of the payload data
+ */
+static void ot_usbdev_server_write_packet(
+    OtUsbdevState *s, OtUsbdevServerCmd cmd, uint32_t id, const uint8_t *data0,
+    size_t size0, const uint8_t *data1, size_t size1)
+{
+    /*
+     * @todo Update this to handle partial writes, by adding them to a queue and
+     * using a watch callback
+     */
+    const OtUsbdevServerPktHdr hdr = {
+        .cmd = cmd,
+        .size = size0 + size1,
+        .id = id,
+    };
+    int res =
+        qemu_chr_fe_write(&s->usb_chr, (const uint8_t *)&hdr, sizeof(hdr));
+    if (res < sizeof(hdr)) {
+        qemu_log_mask(LOG_UNIMP, "%s: %s server: unhandled partial write\n",
+                      __func__, s->ot_id);
+        return;
+    }
+    if (size0 > 0u) {
+        res = qemu_chr_fe_write(&s->usb_chr, data0, (int)size0);
+        if (res < size0) {
+            qemu_log_mask(LOG_UNIMP, "%s: %s server: unhandled partial write\n",
+                          __func__, s->ot_id);
+            return;
+        }
+    }
+    if (size1 > 0u) {
+        res = qemu_chr_fe_write(&s->usb_chr, data1, (int)size1);
+        if (res < size1) {
+            qemu_log_mask(LOG_UNIMP, "%s: %s server: unhandled partial write\n",
+                          __func__, s->ot_id);
+            return;
+        }
+    }
+}
+
+/*
+ * Report a (dis)connection event to the client.
+ *
+ * Send a message to the client to notify the connection status change.
+ * Note that this function does not keep track of the current status and will
+ * send a message if the new status is the same as the old one.
+ *
+ * @connected New connection status
+ */
+void ot_usbdev_server_report_connected(OtUsbdevState *s, bool connected)
+{
+    trace_ot_usbdev_server_report_connected(s->ot_id, connected);
+
+    /* Nothing to do if no client is connected */
+    if (!s->usb_server.client_connected) {
+        return;
+    }
+
+    /* @todo clarify ID to use */
+    ot_usbdev_server_write_packet(s,
+                                  connected ? OT_USBDEV_SERVER_CMD_CONNECT :
+                                              OT_USBDEV_SERVER_CMD_DISCONNECT,
+                                  0u, NULL, 0u, NULL, 0u);
+}
+
+/*
+ * Process a HELLO packet from the client and send one back.
+ *
+ * After this function, the server will be ready to receive messages from
+ * the client, unless the packet was invalid in which case the server will
+ * keep expecting a valid HELLO packet.
+ */
+static void ot_usbdev_server_process_hello(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    if (server->hello_done) {
+        trace_ot_usbdev_server_protocol_error(s->ot_id, "unexpected HELLO");
+        /* Not a fatal error */
+    }
+    if (server->recv_pkt.size != sizeof(OtUsbdevServerHelloPkt)) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id,
+            "HELLO packet with unexpected payload size, ignoring packet");
+        return;
+    }
+    /*
+     * @todo maybe recover packet ID and drop any packet with ID smaller than
+     * the last hello?
+     */
+    OtUsbdevServerHelloPkt hello;
+    memcpy(&hello, server->recv_data, sizeof(OtUsbdevServerHelloPkt));
+    if (memcmp(hello.magic, OT_USBDEV_SERVER_HELLO_MAGIC,
+               sizeof(hello.magic)) != 0) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id,
+            "HELLO packet with unexpected magic value, ignoring packet");
+        return;
+    }
+    if (hello.major_version != OT_USBDEV_SERVER_MAJOR_VER ||
+        hello.minor_version != OT_USBDEV_SERVER_MINOR_VER) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "HELLO packet with unexpected version, ignoring packet");
+        return;
+    }
+    server->hello_done = true;
+
+    trace_ot_usbdev_server_hello(s->ot_id, hello.major_version,
+                                 hello.minor_version);
+
+    /* Answer back */
+    OtUsbdevServerHelloPkt resp_hello;
+    memcpy(&resp_hello.magic, OT_USBDEV_SERVER_HELLO_MAGIC,
+           sizeof(resp_hello.magic));
+    resp_hello.major_version = OT_USBDEV_SERVER_MAJOR_VER;
+    resp_hello.minor_version = OT_USBDEV_SERVER_MINOR_VER;
+    ot_usbdev_server_write_packet(s, OT_USBDEV_SERVER_CMD_HELLO,
+                                  server->recv_pkt.id,
+                                  (const void *)&resp_hello, sizeof(resp_hello),
+                                  NULL, 0u);
+}
+
+static void ot_usbdev_server_process_reset(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    if (server->recv_pkt.size != 0u) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "RESET packet with unexpected payload, ignoring packet");
+        return;
+    }
+    /* Ignore if device is not enabled */
+    if (resettable_is_in_reset(OBJECT(s))) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "RESET when device is in reset, ignoring packet");
+        return;
+    }
+
+    ot_usbdev_simulate_link_reset(s);
+}
+
+static void ot_usbdev_server_process_vbus_changed(OtUsbdevState *s, bool vbus)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    if (server->recv_pkt.size != 0u) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id,
+            "VBUS_ON/OFF packet with unexpected payload, ignoring packet");
+        return;
+    }
+
+    server->vbus_connected = vbus;
+    ot_usbdev_update_vbus(s);
+}
+
+static void ot_usbdev_server_process_setup(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    if (server->recv_pkt.size != sizeof(OtUsbdevServerSetupPkt)) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id,
+            "SETUP packet with unexpected payload size, ignoring packet");
+        return;
+    }
+    /* Ignore if device is not enabled */
+    if (resettable_is_in_reset(OBJECT(s))) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "SETUP when device is in reset, ignoring packet");
+        return;
+    }
+
+    OtUsbdevServerSetupPkt setup;
+    memcpy(&setup, server->recv_data, sizeof(OtUsbdevServerSetupPkt));
+
+    /* @todo enforce that reserved is 0 */
+
+    /* Ignore SETUP if address or endpoint is not ours */
+    if (setup.address != ot_usbdev_get_address(s) ||
+        setup.endpoint >= USBDEV_PARAM_N_ENDPOINTS) {
+        trace_ot_usbdev_setup_addr(
+            s->ot_id, setup.address, setup.endpoint,
+            "ignore (mismatching address or invalid endpoint)");
+        return;
+    }
+
+    ot_usbdev_simulate_setup(s, setup.endpoint, setup.setup);
+}
+
+void ot_usbdev_server_complete_transfer(OtUsbdevState *s, uint32_t id,
+                                        OtUsbdevServerTransferStatus status,
+                                        uint32_t xfer_size, const uint8_t *data,
+                                        uint32_t data_size, const char *msg)
+{
+    trace_ot_usbdev_complete_transfer(s->ot_id, id, xfer_size,
+                                      XFER_STATUS_NAME(status), msg);
+
+    OtUsbdevServerCompletePkt pkt;
+    memset(&pkt, 0u, sizeof(pkt));
+    pkt.status = (uint8_t)status;
+    pkt.transfer_size = xfer_size;
+    ot_usbdev_server_write_packet(s, OT_USBDEV_SERVER_CMD_COMPLETE, id,
+                                  (const uint8_t *)&pkt, sizeof(pkt), data,
+                                  data_size);
+}
+
+static void ot_usbdev_server_process_transfer_in(
+    OtUsbdevState *s, uint8_t ep, uint8_t flags, uint16_t max_packet_size,
+    uint32_t transfer_size)
+{
+    OtUsbdevServer *server = &s->usb_server;
+    OtUsbdevServerEpInXfer *xfer = &server->ep[ep].in;
+
+    /* It is an error to send a transfer if one is pending */
+    if (xfer->pending) {
+        trace_ot_usbdev_transfer(s->ot_id, server->recv_pkt.id, ep, "IN", flags,
+                                 max_packet_size, transfer_size,
+                                 "error (transfer already pending)");
+        ot_usbdev_server_complete_transfer(s, server->recv_pkt.id,
+                                           OT_USBDEV_SERVER_STATUS_ERROR, 0u,
+                                           NULL, 0u,
+                                           "transfer already pending");
+    }
+
+    /* @todo check for unknown flags */
+
+    trace_ot_usbdev_transfer(s->ot_id, server->recv_pkt.id, ep, "IN", flags,
+                             max_packet_size, transfer_size, "accepted");
+
+    /* Sanity check */
+    g_assert(xfer->xfer_buf == NULL);
+
+    /* record transfer */
+    xfer->id = server->recv_pkt.id;
+    xfer->xfer_len = transfer_size;
+    /* @todo do some basic checks on reasonable length? */
+    xfer->xfer_buf = g_malloc(transfer_size);
+    xfer->max_packet_size = max_packet_size;
+    xfer->recv_buf = xfer->xfer_buf;
+    xfer->recv_rem = transfer_size;
+    xfer->pending = true;
+
+    ot_usbdev_advance_transfer_in(s, ep);
+}
+
+static void ot_usbdev_server_process_transfer_out(
+    OtUsbdevState *s, uint8_t ep, uint8_t flags, uint16_t max_packet_size,
+    uint32_t transfer_size, const uint8_t *data)
+{
+    OtUsbdevServer *server = &s->usb_server;
+    OtUsbdevServerEpOutXfer *xfer = &server->ep[ep].out;
+
+    /* It is an error to send a transfer if one is pending */
+    if (xfer->pending) {
+        trace_ot_usbdev_transfer(s->ot_id, server->recv_pkt.id, ep, "OUT",
+                                 flags, max_packet_size, transfer_size,
+                                 "error (transfer already pending)");
+        ot_usbdev_server_complete_transfer(s, server->recv_pkt.id,
+                                           OT_USBDEV_SERVER_STATUS_ERROR, 0u,
+                                           NULL, 0u,
+                                           "transfer already pending");
+    }
+
+    /* @todo check for unknown flags */
+    bool zlp = (flags & OT_USBDEV_SERVER_FLAG_ZLP) != 0u;
+
+    /* @todo check max packet size is smaller than buffer size! */
+
+    trace_ot_usbdev_transfer(s->ot_id, server->recv_pkt.id, ep, "OUT", flags,
+                             max_packet_size, transfer_size, "accepted");
+
+    /* sanity check */
+    g_assert(xfer->xfer_buf == NULL);
+
+    /* record transfer */
+    xfer->id = server->recv_pkt.id;
+    /* @todo do some basic checks on reasonable length? */
+    xfer->xfer_buf = g_malloc(transfer_size);
+    memcpy(xfer->xfer_buf, data, transfer_size);
+    xfer->xfer_len = transfer_size;
+    xfer->max_packet_size = max_packet_size;
+    xfer->send_buf = xfer->xfer_buf;
+    xfer->send_rem = transfer_size;
+    /*
+     * Due to the logic in ot_usbdev_advance_transfer_out, the ZLP flag
+     * must only be set for non-zero length transfers, otherwise we will
+     * send two ZLPs.
+     */
+    xfer->send_zlp = zlp && transfer_size != 0u;
+    xfer->pending = true;
+
+    ot_usbdev_advance_transfer_out(s, ep);
+}
+
+static void ot_usbdev_server_process_transfer(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    if (server->recv_pkt.size < sizeof(OtUsbdevServerTransferPkt)) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "TRANSFER packet with unexpectedly small payload size, "
+                      "ignoring packet");
+        return;
+    }
+
+    OtUsbdevServerTransferPkt xfer;
+    memcpy(&xfer, server->recv_data, sizeof(OtUsbdevServerTransferPkt));
+
+    uint8_t epnum = xfer.endpoint & OT_USBDEV_EP_NUM_MASK;
+    bool dir_in = (xfer.endpoint & OT_USBDEV_EP_DIR_IN) == OT_USBDEV_EP_DIR_IN;
+
+    /* Ignore if device is not enabled */
+    if (resettable_is_in_reset(OBJECT(s))) {
+        trace_ot_usbdev_transfer(s->ot_id, server->recv_pkt.id, epnum,
+                                 dir_in ? "IN" : "OUT", xfer.flags,
+                                 xfer.packet_size, xfer.transfer_size,
+                                 "ignored (device is in reset)");
+        ot_usbdev_server_complete_transfer(s, server->recv_pkt.id,
+                                           OT_USBDEV_SERVER_STATUS_ERROR, 0u,
+                                           NULL, 0u, "device is in reset");
+        return;
+    }
+
+    if (epnum >= USBDEV_PARAM_N_ENDPOINTS) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "TRANSFER to non-existent endpoint, ignoring packet");
+        return;
+    }
+
+    uint32_t expected_data_len = dir_in ? 0u : xfer.transfer_size;
+    if (server->recv_pkt.size !=
+        sizeof(OtUsbdevServerTransferPkt) + expected_data_len) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id,
+            "TRANSFER packet with unexpected payload size, ignoring packet");
+        return;
+    }
+
+    if (dir_in) {
+        ot_usbdev_server_process_transfer_in(s, epnum, xfer.flags,
+                                             xfer.packet_size,
+                                             xfer.transfer_size);
+    } else {
+        const uint8_t *data =
+            server->recv_data + sizeof(OtUsbdevServerTransferPkt);
+        ot_usbdev_server_process_transfer_out(s, epnum, xfer.flags,
+                                              xfer.packet_size,
+                                              xfer.transfer_size, data);
+    }
+}
+
+static void ot_usbdev_server_process_cancel(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    if (server->recv_pkt.size != sizeof(OtUsbdevServerCancelPkt)) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "CANCEL packet with unexpected payload size, "
+                      "ignoring packet");
+        return;
+    }
+
+    OtUsbdevServerCancelPkt xfer;
+    memcpy(&xfer, server->recv_data, sizeof(OtUsbdevServerCancelPkt));
+
+    bool success = ot_usbdev_cancel_transfer_by_id(s, xfer.xfer_id,
+                                                   "Cancelled by request");
+
+    trace_ot_usbdev_cancel(s->ot_id, xfer.xfer_id,
+                           success ? "success" : "no matching transfer found");
+}
+
+static void ot_usbdev_server_process_packet(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    /*
+     * Important note: the ->recv_data pointer is freed in
+     * ot_usbdev_server_reset_recv_state() if left non-NULL. The code below must
+     * either make a copy of the data or take ownership of the pointer and set
+     * ->recv_data to NULL.
+     */
+
+    /* If HELLO hasn't been received yet, ignore everything else */
+    if (server->recv_pkt.cmd != OT_USBDEV_SERVER_CMD_HELLO &&
+        !server->hello_done) {
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "unexpected command before HELLO, ignoring packet");
+        /* Do not process packet */
+        return;
+    }
+
+    switch (server->recv_pkt.cmd) {
+    case OT_USBDEV_SERVER_CMD_HELLO:
+        ot_usbdev_server_process_hello(s);
+        break;
+    case OT_USBDEV_SERVER_CMD_RESET:
+        ot_usbdev_server_process_reset(s);
+        break;
+    case OT_USBDEV_SERVER_CMD_VBUS_ON:
+        ot_usbdev_server_process_vbus_changed(s, true);
+        break;
+    case OT_USBDEV_SERVER_CMD_VBUS_OFF:
+        ot_usbdev_server_process_vbus_changed(s, false);
+        break;
+    case OT_USBDEV_SERVER_CMD_SETUP:
+        ot_usbdev_server_process_setup(s);
+        break;
+    case OT_USBDEV_SERVER_CMD_TRANSFER:
+        ot_usbdev_server_process_transfer(s);
+        break;
+    case OT_USBDEV_SERVER_CMD_CANCEL:
+        ot_usbdev_server_process_cancel(s);
+        break;
+    default:
+        trace_ot_usbdev_server_protocol_error(
+            s->ot_id, "unknown command, ignoring packet");
+        break;
+    }
+
+    ot_usbdev_server_reset_recv_state(s);
+}
+
+static void ot_usbdev_server_advance_recv_state(OtUsbdevState *s)
+{
+    OtUsbdevServer *server = &s->usb_server;
+
+    if (server->recv_state == OT_USBDEV_SERVER_RECV_WAIT_HEADER) {
+        /* We received a header, now receive data if necessary */
+        if (server->recv_pkt.size > 0u) {
+            /* sanity check */
+            g_assert(server->recv_data == NULL);
+            /* @todo have some bound on allocation size here? */
+            server->recv_data = g_malloc(server->recv_pkt.size);
+            server->recv_rem = server->recv_pkt.size;
+            server->recv_buf = (uint8_t *)server->recv_data;
+            server->recv_state = OT_USBDEV_SERVER_RECV_WAIT_DATA;
+        } else {
+            /* Process packet */
+            ot_usbdev_server_process_packet(s);
+        }
+    } else if (server->recv_state == OT_USBDEV_SERVER_RECV_WAIT_DATA) {
+        /* Process packet */
+        ot_usbdev_server_process_packet(s);
+    } else {
+        g_assert_not_reached();
+    }
+}
+
+static int ot_usbdev_chr_usb_can_receive(void *opaque)
+{
+    OtUsbdevState *s = opaque;
+
+    /*
+     * If bus reset signalling is in progress, delay
+     * reception until it is done.
+     */
+    if (timer_pending(&s->bus_reset_timer)) {
+        return 0;
+    }
+
+    /* Return remaining size in the buffer. */
+    return (int)s->usb_server.recv_rem;
+}
+
+static void ot_usbdev_chr_usb_receive(void *opaque, const uint8_t *buf,
+                                      int size)
+{
+    OtUsbdevState *s = opaque;
+    OtUsbdevServer *server = &s->usb_server;
+
+    if (size > server->recv_rem) {
+        error_report("%s: %s: Received too much data on the usb chardev",
+                     __func__, s->ot_id);
+        return;
+    }
+    /* Copy data at the end of the buffer. */
+    memcpy(server->recv_buf, buf, (size_t)size);
+    server->recv_buf += size;
+    server->recv_rem -= size;
+
+    /* Advance state if done */
+    if (server->recv_rem == 0u) {
+        ot_usbdev_server_advance_recv_state(s);
+    }
+}
+
+static void ot_usbdev_chr_usb_event_handler(void *opaque, QEMUChrEvent event)
+{
+    OtUsbdevState *s = opaque;
+
+    trace_ot_usbdev_chr_usb_event_handler(s->ot_id, event);
+
+    if (event == CHR_EVENT_OPENED) {
+        ot_usbdev_server_open(s);
+    }
+
+    if (event == CHR_EVENT_CLOSED) {
+        ot_usbdev_server_close(s);
+    }
+}
+
+/*
+ * Communication device handling
+ */
+
+static int ot_usbdev_chr_cmd_can_receive(void *opaque)
+{
+    OtUsbdevState *s = opaque;
+
+    /* Return remaining size in the buffer. */
+    return (int)sizeof(s->cmd_buf) - (int)s->cmd_buf_pos;
+}
+
+/*
+ * Process a nul-terminated command. A size (which does not count NUL) is
+ * provided if necessary. The following commands are supported:
+ * - "vbus_on": set the VBUS sensing signal to 1.
+ * - "vbus_off": set the VBUS sensing signal to 0.
+ */
+static void ot_usbdev_chr_process_cmd(OtUsbdevState *s, char *cmd,
+                                      size_t cmd_size)
+{
+    trace_ot_usbdev_chr_process_cmd(s->ot_id, cmd);
+
+    if (strncmp(cmd, "vbus_on", cmd_size) == 0) {
+        ot_usbdev_set_vbus_gate(s, true);
+    } else if (strncmp(cmd, "vbus_off", cmd_size) == 0) {
+        ot_usbdev_set_vbus_gate(s, false);
+    } else {
+        qemu_log_mask(LOG_UNIMP, "%s: %s: unsupported command %s\n", __func__,
+                      s->ot_id, cmd);
+    }
+}
+
+static void ot_usbdev_chr_cmd_receive(void *opaque, const uint8_t *buf,
+                                      int size)
+{
+    OtUsbdevState *s = opaque;
+
+    if (s->cmd_buf_pos + (unsigned)size > sizeof(s->cmd_buf)) {
+        error_report("%s: %s: Received too much data on the cmd chardev",
+                     __func__, s->ot_id);
+        return;
+    }
+    /* Copy data at the end of the buffer. */
+    memcpy(&s->cmd_buf[s->cmd_buf_pos], buf, (size_t)size);
+    s->cmd_buf_pos += (unsigned)size;
+    /* Process any line. */
+    while (true) {
+        /* Search end of line, stop if none is found. */
+        char *eol = memchr(s->cmd_buf, (int)'\n', s->cmd_buf_pos);
+        if (!eol) {
+            break;
+        }
+        *eol = 0;
+        /*
+         * Process command and then remove it from the buffer
+         * by shifting everything left.
+         */
+        size_t cmd_size = eol - s->cmd_buf;
+        ot_usbdev_chr_process_cmd(s, s->cmd_buf, cmd_size);
+        memmove(s->cmd_buf, eol + 1u, s->cmd_buf_pos - cmd_size - 1u);
+        s->cmd_buf_pos -= cmd_size - 1u;
+    }
+}
+
+/*
+ * QEMU Initialization
+ */
+static const Property ot_usbdev_properties[] = {
+    DEFINE_PROP_STRING("ot_id", OtUsbdevState, ot_id),
+    DEFINE_PROP_STRING("clock-name", OtUsbdevState, usbclk_name),
+    DEFINE_PROP_STRING("clock-name-aon", OtUsbdevState, aonclk_name),
+    DEFINE_PROP_LINK("clock-src", OtUsbdevState, clock_src, TYPE_DEVICE,
+                     DeviceState *),
+    /*
+     * Communication device used to control the USBDEV block. Every command
+     * must be terminated by a newline. See ot_usbdev_chr_process_cmd for
+     * the list of supported devices.
+     */
+    DEFINE_PROP_CHR("chardev-cmd", OtUsbdevState, cmd_chr),
+    /*
+     * Communication device used to emulate a USB host.
+     */
+    DEFINE_PROP_CHR("chardev-usb", OtUsbdevState, usb_chr),
+    /* VBUS control mode. */
+    DEFINE_PROP_BOOL("vbus-override", OtUsbdevState, vbus_override, false),
+};
+
+static const MemoryRegionOps ot_usbdev_ops = {
+    .read = &ot_usbdev_read,
+    .write = &ot_usbdev_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = sizeof(uint32_t),
+    .impl.max_access_size = sizeof(uint32_t),
+};
+
+static const MemoryRegionOps ot_usbdev_buffer_ops = {
+    .read = &ot_usbdev_buffer_read,
+    .write = &ot_usbdev_buffer_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    /* @todo The RTL probably supports sub-word reads, implement this */
+    .impl.min_access_size = sizeof(uint32_t),
+    .impl.max_access_size = sizeof(uint32_t),
+};
+
+/*
+ * QEMU reset handling
+ */
+
+static void ot_usbdev_reset_enter(Object *obj, ResetType type)
+{
+    OtUsbdevClass *c = OT_USBDEV_GET_CLASS(obj);
+    OtUsbdevState *s = OT_USBDEV(obj);
+
+    trace_ot_usbdev_reset(s->ot_id, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    ot_usbdev_cancel_all_transfers(s, "device going into reset");
+
+    /*
+     * If there is a bus reset in progress, we cancel it.
+     * The rationale is that on a real bus, the device
+     * reset would cause the block to disable the pullup
+     * so the host would notice the disconnection and stop
+     * reset signalling. The same applies for the frame timer.
+     */
+    timer_del(&s->frame_timer);
+    timer_del(&s->bus_reset_timer);
+
+    /* See BFM (dut_reset) */
+    memset(s->regs, 0u, sizeof(s->regs));
+
+    ot_fifo32_reset(&s->rx_fifo);
+    fifo8_reset(&s->av_setup_fifo);
+    fifo8_reset(&s->av_out_fifo);
+
+    ot_usbdev_update_status_irqs(s);
+    ot_usbdev_update_irqs(s);
+}
+
+static void ot_usbdev_reset_exit(Object *obj, ResetType type)
+{
+    OtUsbdevClass *c = OT_USBDEV_GET_CLASS(obj);
+    OtUsbdevState *s = OT_USBDEV(obj);
+
+    trace_ot_usbdev_reset(s->ot_id, "exit");
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    ot_usbdev_update_vbus(s);
+    ot_usbdev_update_fifos_status(s);
+}
+
+static void ot_usbdev_realize(DeviceState *dev, Error **errp)
+{
+    OtUsbdevState *s = OT_USBDEV(dev);
+    (void)errp;
+
+    /* @todo: clarify if we need to track events/backend changes. */
+    qemu_chr_fe_set_handlers(&s->cmd_chr, &ot_usbdev_chr_cmd_can_receive,
+                             &ot_usbdev_chr_cmd_receive, NULL, NULL, s, NULL,
+                             true);
+
+    qemu_chr_fe_set_handlers(&s->usb_chr, &ot_usbdev_chr_usb_can_receive,
+                             &ot_usbdev_chr_usb_receive,
+                             &ot_usbdev_chr_usb_event_handler, NULL, s, NULL,
+                             true);
+
+    g_assert(s->ot_id);
+    g_assert(s->usbclk_name);
+    g_assert(s->aonclk_name);
+
+    /* If not in VBUS override mode, the VBUS gate starts on by default. */
+    if (!s->vbus_override) {
+        s->vbus_gate = true;
+    }
+}
+
+static void ot_usbdev_init(Object *obj)
+{
+    OtUsbdevState *s = OT_USBDEV(obj);
+
+    for (unsigned idx = 0u; idx < ARRAY_SIZE(s->irqs); idx++) {
+        ibex_sysbus_init_irq(obj, &s->irqs[idx]);
+    }
+    ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
+
+    memory_region_init(&s->mmio.main, obj, TYPE_OT_USBDEV ".mmio",
+                       USBDEV_DEVICE_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio.main);
+    memory_region_init_io(&s->mmio.regs, obj, &ot_usbdev_ops, s,
+                          TYPE_OT_USBDEV ".reg", USBDEV_REGS_SIZE);
+    memory_region_add_subregion(&s->mmio.main, USBDEV_REGS_OFFSET,
+                                &s->mmio.regs);
+    memory_region_init_io(&s->mmio.buffer, obj, &ot_usbdev_buffer_ops, s,
+                          TYPE_OT_USBDEV ".buffer", USBDEV_BUFFER_SIZE);
+    memory_region_add_subregion(&s->mmio.main, USBDEV_BUFFER_OFFSET,
+                                &s->mmio.buffer);
+
+    ot_fifo32_create(&s->rx_fifo, OT_USBDEV_RX_FIFO_DEPTH);
+    fifo8_create(&s->av_out_fifo, OT_USBDEV_AV_OUT_FIFO_DEPTH);
+    fifo8_create(&s->av_setup_fifo, OT_USBDEV_AV_SETUP_FIFO_DEPTH);
+
+    timer_init_us(&s->bus_reset_timer, OT_VIRTUAL_CLOCK,
+                  &ot_usbdev_link_reset_complete, s);
+    timer_init_us(&s->frame_timer, OT_VIRTUAL_CLOCK,
+                  &ot_usbdev_frame_timer_expired, s);
+}
+
+static void ot_usbdev_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_usbdev_realize;
+    device_class_set_props(dc, ot_usbdev_properties);
+    /* @todo: check what does DEVICE_CATEGORY_USB entail? */
+    set_bit(DEVICE_CATEGORY_USB, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtUsbdevClass *uc = OT_USBDEV_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_usbdev_reset_enter, NULL,
+                                       &ot_usbdev_reset_exit,
+                                       &uc->parent_phases);
+}
+
+static const TypeInfo ot_usbdev_info = {
+    .name = TYPE_OT_USBDEV,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtUsbdevState),
+    .instance_init = &ot_usbdev_init,
+    .class_size = sizeof(OtUsbdevClass),
+    .class_init = &ot_usbdev_class_init,
+};
+
+static void ot_usbdev_register_types(void)
+{
+    type_register_static(&ot_usbdev_info);
+}
+
+type_init(ot_usbdev_register_types);
diff --git a/hw/opentitan/ot_vmapper.c b/hw/opentitan/ot_vmapper.c
new file mode 100644
index 0000000000000..e34d078fdde7a
--- /dev/null
+++ b/hw/opentitan/ot_vmapper.c
@@ -0,0 +1,1194 @@
+/*
+ * QEMU OpenTitan virtual mapper device
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/typedefs.h"
+#include "exec/cputlb.h"
+#include "exec/page-protection.h"
+#include "exec/target_page.h"
+#include "hw/boards.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_vmapper.h"
+#include "hw/qdev-properties.h"
+#include "hw/riscv/ibex_common.h"
+/* NOLINTBEGIN(misc-header-include-cycle) */
+#include "target/riscv/cpu.h"
+/* NOLINTEND(misc-header-include-cycle) */
+#include "trace.h"
+
+/* define to log range definitions */
+#undef SHOW_RANGE_LIST
+#undef SHOW_RANGE_TREE
+/* define to log address mapping (highly verbose) */
+#undef SHOW_ADDRESS_MAPPING
+
+/* Translatable region */
+typedef struct {
+    uint32_t start; /* first address of the region to be translated */
+    uint32_t end; /* last address of the region to be translated */
+    uint32_t dest; /* first address of the destination */
+    uint8_t prio; /* priority of the slot, 0 = highest priority */
+    bool active; /* whether this range is active or should be ignored */
+    bool execute; /* whether this range is executable (for insn range)*/
+} OtRegionRange;
+
+struct OtVMapperState {
+    DeviceState parent_obj;
+
+    OtRegionRange *dranges; /* Configured data ranges */
+    OtRegionRange *iranges; /* Configured instruction ranges */
+
+    OtRegionRange *lranges[2u]; /* Last matched data and instruction ranges */
+
+    CPUState *cpu;
+    GTree *dtree; /* Active data ranges */
+    GTree *itree; /* Active instruction ranges */
+    bool insert_mode; /* Whether trees are used in insertion or matching mode */
+    bool show; /* debug flag to enable list and tree dump */
+    bool silent_align; /* whether to silence alignment warnings */
+
+    char *ot_id;
+    uint8_t cpu_idx; /* cpu index, i.e. which vCPU is translated */
+    uint8_t trans_count; /* count of translatable regions */
+    uint8_t noexec_count; /* count of disable execution regions */
+};
+
+/*
+ * Offset to let disabled execution ranges have a higher priority over
+ * remapped ranges.
+ * - ranges for translation use a priority level greater than or equal to this
+ *   value,
+ * - ranges for disable execution use a priority level strictly less than this
+ *   value.
+ */
+#define VMAP_TRANS_PRIORITY_BASE 1u
+
+/*
+ * Default count of supported "noexec region", can be overridden with a
+ * property, should be enough for most use cases
+ */
+#define OT_VMAPPER_DEFAULT_NOEXEC_REGION_COUNT 10u
+
+#define VMAP_RANGE(_glist_) ((OtRegionRange *)((_glist_)->data))
+#define VMAP_PRIOR(_ra_, _rb_) \
+    ((VMAP_RANGE(_ra_)->pos < VMAP_RANGE(_rb_)->pos) ? VMAP_RANGE(_ra_) : \
+                                                       VMAP_RANGE(_rb_))
+#define VMAP_RANGE_TO_TREE_KEY(_s_, _e_) \
+    ((gpointer)(((uintptr_t)(_s_)) | ((uintptr_t)(_e_) << 32u)))
+#define VMAP_REGION_TO_TREE_KEY(_r_) \
+    VMAP_RANGE_TO_TREE_KEY((_r_)->start, (_r_)->end)
+#define VMAP_TREE_KEY_TO_RANGE_START(_g_) \
+    ((uint32_t)(((uintptr_t)(_g_)) & UINT32_MAX))
+#define VMAP_TREE_KEY_TO_RANGE_END(_g_) ((uint32_t)(((uintptr_t)(_g_)) >> 32u))
+
+/*
+ * order ranges for g_list_sort
+ *  1. by start address first,
+ *  2. then by end address,
+ *  3. then by priority (from higest to lowest)
+ */
+static gint ot_vmapper_compare(gconstpointer a, gconstpointer b,
+                               gpointer user_data)
+{
+    const OtRegionRange *ra = (const OtRegionRange *)a;
+    const OtRegionRange *rb = (const OtRegionRange *)b;
+    (void)user_data;
+
+    if (ra->start == rb->start) {
+        if (ra->end == rb->end) {
+            return (gint)ra->prio - (gint)rb->prio;
+        }
+        return (ra->end < rb->end) ? -1 : 1;
+    }
+    return (ra->start < rb->start) ? -1 : 1;
+}
+
+/*
+ * order range by increasing addresses, for g_tree
+ * - in insert mode, return a strict range comparison
+ * - in match mode, return equality for any A address in B range
+ */
+static gint ot_vmapper_compare_address(gconstpointer a, gconstpointer b,
+                                       gpointer user_data)
+{
+    gint ret;
+    bool insert_mode = *(const bool *)user_data;
+
+    uint32_t as = VMAP_TREE_KEY_TO_RANGE_START(a);
+    uint32_t bs = VMAP_TREE_KEY_TO_RANGE_START(b);
+
+    if (!insert_mode) {
+        uint32_t ae = VMAP_TREE_KEY_TO_RANGE_END(a);
+        uint32_t be = VMAP_TREE_KEY_TO_RANGE_END(b);
+        /* in match mode, any A start address within B range matches */
+        g_assert(ae == 0);
+        if (as < bs) {
+            ret = -1;
+        } else if (as > be) {
+            ret = 1;
+        } else {
+            ret = 0;
+        }
+    } else {
+        /* in insertion mode, compare the start address */
+        ret = as == bs ? 0 : ((as < bs) ? -1 : 1);
+    }
+
+    return ret;
+}
+
+#ifdef SHOW_RANGE_LIST
+#define VMAP_SHOW_RANGE_LIST(_s_, _i_, _l_, _m_) \
+    ot_vmapper_show_range_list(_s_, _i_, _l_, _m_)
+
+static void ot_vmapper_show_range_list(const OtVMapperState *s, bool insn,
+                                       const GList *rglist, const char *msg)
+{
+    if (!s->show || !trace_event_get_state(TRACE_OT_VMAPPER_SHOW_RANGE) ||
+        !qemu_loglevel_mask(LOG_TRACE)) {
+        return;
+    }
+    const char *kind = insn ? "insn" : "data";
+    qemu_log("%s: %s %s %s\n", __func__, s->ot_id, kind, msg);
+    const GList *current = rglist;
+    unsigned pos = 0;
+    while (current) {
+        const OtRegionRange *rg = VMAP_RANGE(current);
+        qemu_log(" * %2u: [%2u] 0x%08x..0x%08x -> 0x%08x%s\n", pos, rg->prio,
+                 rg->start, rg->end, rg->dest,
+                 (!insn || rg->execute) ? (rg->start == rg->dest ? "" : " vt") :
+                                          " nx");
+        current = current->next;
+        pos++;
+    }
+    qemu_log("%s: %s %s %u items\n\n", __func__, s->ot_id, kind, pos);
+}
+#else
+#define VMAP_SHOW_RANGE_LIST(_s_, _i_, _l_, _m_)
+#endif
+
+static GTree *ot_vmapper_create_tree(OtVMapperState *s)
+{
+    return g_tree_new_full(&ot_vmapper_compare_address, &s->insert_mode, NULL,
+                           &g_free);
+}
+
+#if (GLIB_MAJOR_VERSION == 2)
+/* 'g_tree_remove_all' is deprecated: Not available before 2.70 */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
+#endif /* (GLIB_MAJOR_VERSION == 2) */
+
+/*
+ * there should be no need for such workarounds, however some prehistoric
+ * OSes (CentOS 7, ...) rely on outdated Glib versions that lack useful
+ * functions. Some other old OSes (Ubuntu 20.x) also lack new functions...
+ */
+#if (GLIB_MAJOR_VERSION == 2)
+
+#if (GLIB_MINOR_VERSION >= 68) && (GLIB_MINOR_VERSION < 70)
+
+/*
+ * g_tree_remove_all is only available from 2.70
+ * re-implement it
+ */
+static void g_tree_remove_all(GTree *tree)
+{
+    GTreeNode *node;
+    GTreeNode *next;
+    g_return_if_fail(tree != NULL);
+    node = g_tree_node_first(tree);
+    while (node) {
+        next = g_tree_node_next(node);
+        if (tree->key_destroy_func) {
+            tree->key_destroy_func(node->key);
+        }
+        if (tree->value_destroy_func) {
+            tree->value_destroy_func(node->value);
+        }
+        g_slice_free(GTreeNode, node);
+        node = next;
+    }
+    tree->root = NULL;
+}
+#endif /* >= 2.68 < 2.70 */
+
+static void ot_vmapper_flush_tree(OtVMapperState *s, bool insn)
+{
+#if (GLIB_MINOR_VERSION < 68)
+#ifdef SHOW_RANGE_TREE
+/* non essential feature, please upgrade Glib */
+#error SHOW_RANGE_TREE not supported with current Glib version
+#endif /* SHOW_RANGE_TREE */
+    /*
+     * GTreeNode is only available from 2.68
+     * destroy the whole tree and build a new one
+     * this is ugly, but should not be used except on outdated hosts
+     */
+    if (insn) {
+        g_tree_destroy(s->itree);
+        s->itree = ot_vmapper_create_tree(s);
+    } else {
+        g_tree_destroy(s->dtree);
+        s->dtree = ot_vmapper_create_tree(s);
+    }
+#else /* >= 2.68 */
+    (void)s;
+    g_tree_remove_all(insn ? s->itree : s->dtree);
+#endif /* >= 2.68 */
+}
+
+#endif /* 2.x */
+
+#ifdef SHOW_RANGE_TREE
+#define VMAP_SHOW_RANGE_TREE(_s_, _i_) ot_vmapper_show_range_tree(_s_, _i_)
+
+typedef struct {
+    bool insn;
+    unsigned count;
+} OtVmapperTreeNodeInfo;
+
+static gboolean ot_vmapper_show_node(GTreeNode *node, gpointer data)
+{
+    const OtRegionRange *rg = (const OtRegionRange *)g_tree_node_value(node);
+    OtVmapperTreeNodeInfo *info = (OtVmapperTreeNodeInfo *)data;
+    qemu_log(" * %2u: 0x%08x..0x%08x -> 0x%08x%s\n", info->count, rg->start,
+             rg->end, rg->dest,
+             (!info->insn || rg->execute) ?
+                 (rg->start == rg->dest ? "" : " vt") :
+                 " nx");
+    info->count += 1;
+    return FALSE;
+}
+
+static void ot_vmapper_show_range_tree(const OtVMapperState *s, bool insn)
+{
+    if (!s->show || !trace_event_get_state(TRACE_OT_VMAPPER_SHOW_RANGE) ||
+        !qemu_loglevel_mask(LOG_TRACE)) {
+        return;
+    }
+    qemu_log("%s: %s %s\n", __func__, s->ot_id, insn ? "insn" : "data");
+    OtVmapperTreeNodeInfo info = {
+        .insn = insn,
+        .count = 0,
+    };
+    g_tree_foreach_node(insn ? s->itree : s->dtree, &ot_vmapper_show_node,
+                        &info);
+    qemu_log("%s: %s %u items\n\n", __func__, s->ot_id, info.count);
+}
+#else
+#define VMAP_SHOW_RANGE_TREE(_s_, _i_)
+#endif
+
+#if (GLIB_MAJOR_VERSION == 2)
+/* "-Wdeprecated-declarations" */
+#pragma GCC diagnostic pop
+#endif
+
+/* class singleton */
+static OtVMapperClass *ot_vmapper_class;
+
+static int ot_vmapper_get_phy_addr(OtVMapperState *s, hwaddr *physical,
+                                   int *ret_prot, vaddr addr, int access_type)
+{
+    bool insn = access_type == MMU_INST_FETCH;
+
+    OtRegionRange *range = s->lranges[insn];
+
+#ifdef SHOW_ADDRESS_MAPPING
+    bool trace;
+#endif
+    if (!range || (((uint32_t)addr) < range->start) ||
+        (((uint32_t)addr) > range->end)) {
+        GTree *tree = insn ? s->itree : s->dtree;
+        range = g_tree_lookup(tree, VMAP_RANGE_TO_TREE_KEY(addr, 0));
+        s->lranges[insn] = range;
+#ifdef SHOW_ADDRESS_MAPPING
+        trace = true;
+#endif
+    } else {
+#ifdef SHOW_ADDRESS_MAPPING
+        trace = false;
+#endif
+    }
+
+    if G_UNLIKELY (!range || (addr > range->end)) {
+        return TRANSLATE_FAIL;
+    }
+
+    if G_UNLIKELY (insn && !range->execute) {
+        return TRANSLATE_PMP_FAIL;
+    }
+
+    hwaddr offset = addr - (hwaddr)range->start;
+    *physical = range->dest + offset;
+    *ret_prot = PAGE_READ | PAGE_WRITE | (range->execute ? PAGE_EXEC : 0);
+
+#ifdef SHOW_ADDRESS_MAPPING
+    if (trace) {
+        trace_ot_vmapper_new_phy_addr(s->ot_id, insn, (uint32_t)addr,
+                                      *physical);
+    }
+#endif
+
+    return TRANSLATE_SUCCESS;
+}
+
+/* NOLINTBEGIN(readability-non-const-parameter) */
+static int ot_riscv_get_physical_address(
+    CPURISCVState *env, hwaddr *physical, int *ret_prot, vaddr addr,
+    target_ulong *fault_pte_addr, int access_type, int mmu_idx,
+    bool first_stage, bool two_stage, bool is_debug, bool is_probe)
+/* NOLINTEND(readability-non-const-parameter) */
+{
+    (void)fault_pte_addr;
+    (void)mmu_idx;
+    (void)first_stage;
+    (void)two_stage;
+    (void)is_debug;
+    (void)is_probe;
+
+    CPUState *cpu = env_cpu(env);
+    g_assert(cpu->cpu_index < ot_vmapper_class->num_instances);
+
+    OtVMapperState *s = ot_vmapper_class->instances[cpu->cpu_index];
+
+    return ot_vmapper_get_phy_addr(s, physical, ret_prot, addr, access_type);
+}
+
+static GList *ot_vmapper_range_discretize(OtVMapperState *s, GList *rglist)
+{
+    (void)s;
+
+    /*
+     * replace overlapping ranges with additional, non-overlapping ones,
+     * the input list should be sorted by address, and only contain active
+     * regions.
+     */
+    GList *current = rglist;
+    while (current) {
+        GList *next = current->next;
+
+        if (!next) {
+            break;
+        }
+
+        /*
+         * Note about region priority:
+         * "If a transaction matches multiple regions, the lowest indexed region
+         *  has priority."
+         * Here, region with the lower position has higher priority.
+         */
+
+        /* are two consecutive ranges overlapping? */
+        if (VMAP_RANGE(next)->start < VMAP_RANGE(current)->end) {
+            /*
+             * next item starts before current ends: do split, two cases:
+             *   +-----------------+       +---------------+
+             *   |     current     |       |    current    |
+             *   +-----+-------+---+       +-----+---------+----+
+             *         | next  |     (a)         |     next     | (b)
+             *         +-------+                 +--------------+
+             */
+            if (VMAP_RANGE(next)->end <= VMAP_RANGE(current)->end) {
+                /*
+                 * case (a): next is fully overlapped by current, two cases:
+                 *
+                 * +-----------------+        +-----------------+
+                 * |     current     |        | cur |  ...  | rh|
+                 * +-----+-------+---+        +-----+-------+---+
+                 *       |  ...  |     (a1)         | next  |     (a2)
+                 *       +-------+                  +-------+
+                 */
+                if (VMAP_RANGE(current)->prio < VMAP_RANGE(next)->prio) {
+                    /*
+                     * case (a1): next is fully masked by current, as next as
+                     * a less priority than current, skip next entirely
+                     */
+                    current = g_list_remove_link(current, next);
+                    g_list_free_1(next);
+                } else {
+                    /*
+                     * case (a2): central part of current is masked by next
+                     * 1. create a new region for the right part of current
+                     * 2. insert the new region after next
+                     * 3. update current's end position
+                     */
+                    OtRegionRange *right = g_new0(OtRegionRange, 1);
+                    right->start = VMAP_RANGE(next)->end + 1u;
+                    right->end = VMAP_RANGE(current)->end;
+                    right->dest = VMAP_RANGE(current)->dest + right->start -
+                                  VMAP_RANGE(current)->start;
+                    right->prio = VMAP_RANGE(current)->prio;
+                    right->execute = VMAP_RANGE(current)->execute;
+                    right->active = true;
+                    /* assignation is useless, but GCC won't let it go */
+                    next = g_list_insert(next, right, 1u);
+                    /* trim current on next */
+                    VMAP_RANGE(current)->end = VMAP_RANGE(next)->start - 1u;
+                }
+            } else {
+                /* case (b): next extends after current, two cases:
+                 *
+                 * +-------------+            +-------------+
+                 * |   current   |            | cur | ...   |
+                 * +-----+-------+----+       +-----+-------+---+
+                 *       |  ...  |next| (b1)        |    next   |  (b2)
+                 *       +-------+----+             +-----------+
+                 */
+                if (VMAP_RANGE(current)->prio < VMAP_RANGE(next)->prio) {
+                    /* case (b1): next is partially masked by current, trim it*/
+                    VMAP_RANGE(next)->dest +=
+                        VMAP_RANGE(current)->end - VMAP_RANGE(next)->start;
+                    VMAP_RANGE(next)->start = VMAP_RANGE(current)->end + 1u;
+                } else {
+                    /* case (b2): current is partially masked by next, trim it*/
+                    VMAP_RANGE(current)->end = VMAP_RANGE(next)->start - 1u;
+                }
+            }
+        }
+
+        /*
+         * be sure to take the immediate next element of current, which may be
+         * the left item if one has been inserted
+         */
+        current = current->next;
+    }
+
+    return rglist;
+}
+
+static GList *ot_vmapper_range_split_noexec(OtVMapperState *s, GList *rglist)
+{
+    (void)s;
+
+    /*
+     * split the list into two sub-lists
+     * - first list contains the "(no)exec" ranges; they can be identified
+     *   thanks to their higher priority
+     * - second list contains the remap ranges
+     * the input list must be sorted, highest priority first, and all overlaps
+     * must have been discretized.
+     */
+    GList *current;
+    GList *noexec = NULL;
+    GList *noexec_last = NULL;
+    GList *trans = NULL;
+    current = rglist;
+    while (current) {
+        if (VMAP_RANGE(current)->prio >= VMAP_TRANS_PRIORITY_BASE) {
+            /* first range that is not a noexec one */
+            if (current->prev) {
+                /* there is at list one range in the noexec list */
+                noexec = rglist;
+                noexec_last = current->prev;
+                /* end the noexec list */
+                noexec_last->next = NULL;
+            }
+            /* first range of the remap list is the current node */
+            trans = current;
+            trans->prev = NULL;
+            break;
+        }
+        current = current->next;
+    }
+
+    if (!noexec) {
+        /* there are no defined noexec range, end work here */
+        return rglist;
+    }
+
+    /*
+     * for each translating range, check whether it translates into one or more
+     * noexec range.
+     */
+    current = trans;
+    while (current) {
+        uint32_t dst_start = VMAP_RANGE(current)->dest;
+        uint32_t dst_end =
+            dst_start + (VMAP_RANGE(current)->end - VMAP_RANGE(current)->start);
+        GList *curnx = noexec;
+        while (curnx) {
+            if (VMAP_RANGE(curnx)->start > dst_end) {
+                /*
+                 * ranges are sorted, no other noexec range may match, move to
+                 * next translation range
+                 *   +-----------------+
+                 *   |       dst       |
+                 *   +-----------------+  +---------+
+                 *                        |  curnx  |
+                 *                        +---------+
+                 */
+                break;
+            }
+            if (VMAP_RANGE(curnx)->end < dst_start) {
+                /*
+                 * noexec range ends before translation range starts, skip
+                 * noexec and move to the next one
+                 *                 +-----------------+
+                 *                 |       dst       |
+                 *   +---------+   +-----------------+
+                 *   |  curnx  |
+                 *   +---------+
+                 */
+                curnx = curnx->next;
+                continue;
+            }
+
+            if (VMAP_RANGE(curnx)->start > dst_start) {
+                /*
+                 * noexec range starts within translation range, two cases:
+                 *   +-----------------+        +-----------------+
+                 *   |       dst       |        |       dst       |
+                 *   +---+---------+---+        +---+-------------+-----+
+                 *       |  curnx  |     (a1)       |       curnx       | (a2)
+                 *       +---------+                +-------------------+
+                 */
+
+                uint32_t left_size;
+                OtRegionRange *right;
+
+                /*
+                 * create a left region that matches the left side of the
+                 * translation region which does not care about the noexec
+                 * region; then replace the current region with the remaining
+                 * right side of the translation region
+                 */
+                left_size = VMAP_RANGE(curnx)->start - dst_start + 1u;
+                right = g_new0(OtRegionRange, 1);
+                memcpy(right, VMAP_RANGE(current), sizeof(OtRegionRange));
+                right->start = VMAP_RANGE(current)->start + left_size;
+                right->dest = VMAP_RANGE(current)->dest + left_size;
+                VMAP_RANGE(current)->end =
+                    VMAP_RANGE(current)->end + left_size - 1u;
+                dst_start += left_size;
+                current = g_list_insert(current, right, 1u);
+                current = current->next; /* i.e. right */
+                /*
+                 * the a1/a2 cases are now simplified as:
+                 *   +-------------+        +-------------+
+                 *   |    dst'     |        |    dst'     |
+                 *   +---------+---+        +-------------+-----+
+                 *   |  curnx  |     (a1')  |       curnx       | (a2)
+                 *   +---------+            +-------------------+
+                 */
+
+                if (VMAP_RANGE(curnx)->end >= dst_end) {
+                    /*
+                     * case (a2'): curnx extends up to or beyond the current
+                     * translation range. Apply the execution state of the
+                     * noexec range to the current translation range, and move
+                     * to the next one
+                     */
+                    VMAP_RANGE(current)->execute = VMAP_RANGE(curnx)->execute;
+                    break;
+                }
+                /*
+                 * case (a1'): create a new region with the right side of the
+                 * translation region which does not care about the current
+                 * no exec region, and apply the execution state of the noexec
+                 * region to the left side of the translation region
+                 */
+                left_size =
+                    VMAP_RANGE(curnx)->end - VMAP_RANGE(curnx)->start + 1u;
+                right = g_new0(OtRegionRange, 1);
+                memcpy(right, VMAP_RANGE(current), sizeof(OtRegionRange));
+                right->start = VMAP_RANGE(current)->start + left_size;
+                right->dest = VMAP_RANGE(current)->dest + left_size;
+                VMAP_RANGE(current)->end =
+                    VMAP_RANGE(current)->end + left_size - 1u;
+                VMAP_RANGE(current)->execute = VMAP_RANGE(curnx)->execute;
+                dst_start += left_size;
+                current = g_list_insert(current, right, 1u);
+                current = current->next; /* i.e. right */
+            } else {
+                /*
+                 * noexec range starts before translation range, two cases:
+                 *          +------------+              +-----------+
+                 *          |     dst    |              |    dst    |
+                 *   +------+--+---------+        +-----+-----------------+
+                 *   |  curnx  |           (b1)   |          curnx        | (b2)
+                 *   +---------+                  +-----------------------+
+                 */
+                if (VMAP_RANGE(curnx)->end >= dst_end) {
+                    /*
+                     * case (b2): curnx overlaps the whole translation range
+                     * destination: apply the execution state of the noexec
+                     * range to the translation range, and move to the next
+                     * translation range.
+                     */
+                    VMAP_RANGE(current)->execute = VMAP_RANGE(curnx)->execute;
+                    break;
+                }
+
+                /*
+                 * case (b1): curnx partially overlaps the current translation
+                 * range. Split the latter into two ranges: apply the execution
+                 * state of the noexec range to the left translation range,
+                 * leave the right transalation range state unmodified.
+                 */
+                uint32_t left_size = VMAP_RANGE(curnx)->end - dst_start + 1u;
+                OtRegionRange *right = g_new0(OtRegionRange, 1);
+                memcpy(right, VMAP_RANGE(current), sizeof(OtRegionRange));
+                right->start = VMAP_RANGE(current)->start + left_size;
+                right->dest = VMAP_RANGE(current)->dest + left_size;
+                VMAP_RANGE(current)->end =
+                    VMAP_RANGE(current)->start + left_size - 1u;
+                VMAP_RANGE(current)->execute = VMAP_RANGE(curnx)->execute;
+                current = g_list_insert(current, right, 1u);
+                current = current->next; /* i.e. right */
+            }
+
+            curnx = curnx->next;
+        }
+
+        current = current->next;
+    }
+
+    /* restore the whole range list */
+    g_assert(noexec_last);
+
+    /* reconnect the noexec list with the translation list */
+    noexec_last->next = trans;
+    trans->prev = noexec_last;
+
+    return noexec;
+}
+
+static GList *
+ot_vmapper_fill_empty_gaps(OtVMapperState *s, GList *rglist, bool insn)
+{
+    /*
+     * The full address range needs to be defined. Fill all gaps between defined
+     * ranges with no access items. The input list should be sorted by address,
+     * and only contain active regions.
+     */
+    GList *current = rglist;
+    uint32_t addr = 0;
+
+    while (current) {
+        if (addr < VMAP_RANGE(current)->start) {
+            OtRegionRange *gap = g_new0(OtRegionRange, 1);
+            gap->start = addr;
+            gap->end = VMAP_RANGE(current)->start - 1u;
+            gap->dest = gap->start;
+            /* lowest priority */
+            gap->prio =
+                s->trans_count + s->noexec_count + VMAP_TRANS_PRIORITY_BASE;
+            gap->execute = insn;
+            gap->active = true;
+            rglist = g_list_insert_before(rglist, current, gap);
+        }
+        addr = VMAP_RANGE(current)->end + 1u;
+        current = current->next;
+    }
+
+    /*
+     * if the list is empty or if the last item of the list does not end on the
+     * last valid address, append an all access item.
+     */
+    uint32_t end;
+    if (rglist) {
+        current = g_list_last(rglist);
+        end = VMAP_RANGE(current)->end;
+    } else {
+        current = NULL;
+        end = 0;
+    }
+
+    if (end != UINT32_MAX) {
+        OtRegionRange *last = g_new0(OtRegionRange, 1);
+        last->start = end ? end + 1u : 0;
+        last->end = UINT32_MAX;
+        last->dest = last->start; /* 1:1 mapping */
+        /* lowest priority */
+        last->prio =
+            s->trans_count + s->noexec_count + VMAP_TRANS_PRIORITY_BASE;
+        last->execute = insn;
+        last->active = true;
+        if (current) {
+            /* assignation is useless, but GCC won't let it go ... */
+            current = g_list_insert(current, last, 1u);
+            /* ... while clang-tidy found this stupid */
+            (void)current;
+        } else {
+            rglist = g_list_insert(NULL, last, 0u);
+        }
+    }
+
+    /* from here, its is guaranteed that rglist contains at least one item */
+
+    return rglist;
+}
+
+static GList *ot_vmapper_fuse(OtVMapperState *s, GList *rglist)
+{
+    /*
+     * simplify the list whenever possible; if contiguous items share the same
+     * access permissions, fuse them to reduce the number of memory regions to
+     * create; the input list should be sorted by address, and only contain
+     * active regions.
+     */
+    GList *current = rglist;
+    (void)s;
+
+    while (current && current->next) {
+        GList *next = current->next;
+        /* should always be valid, use this opportunity to validate the list */
+        g_assert(VMAP_RANGE(current)->end + 1u == VMAP_RANGE(next)->start);
+        if ((VMAP_RANGE(current)->execute == VMAP_RANGE(next)->execute) &&
+            ((VMAP_RANGE(next)->start - VMAP_RANGE(next)->dest) ==
+             (VMAP_RANGE(current)->start - VMAP_RANGE(current)->dest))) {
+            VMAP_RANGE(current)->end = VMAP_RANGE(next)->end;
+
+            rglist = g_list_remove_link(rglist, next);
+            g_free(next->data); /* OtRegionRange */
+            g_list_free(next);
+
+            /*
+             * do not change the current item if a fusion occured, since the
+             * current new adjacent 'next' may also be a fusion candidate.
+             */
+        } else {
+            current = current->next;
+        }
+    }
+
+    return rglist;
+}
+
+static void ot_vmapper_rebuild_tree(OtVMapperState *s, bool insn, GList *rglist)
+{
+    const GList *current = rglist;
+
+    /* empty the tree AND free any contained OtRegionRange items */
+    ot_vmapper_flush_tree(s, insn);
+
+    GTree *tree = insn ? s->itree : s->dtree;
+
+    /* configure the tree comparison for insertion */
+    s->insert_mode = true;
+
+    while (current) {
+        OtRegionRange *range = VMAP_RANGE(current);
+        g_assert(range->active);
+
+        /* transfer ownership of the OtRegionRange item from list to the tree */
+        g_tree_insert(tree, VMAP_REGION_TO_TREE_KEY(range), range);
+
+        current = current->next;
+    }
+
+    /* configure the tree comparison for matching range */
+    s->insert_mode = false;
+
+    /*
+     * free the list but not its OtRegionRange items which are now owned by the
+     * tree
+     */
+    g_list_free(rglist);
+}
+
+static void ot_vmapper_update(OtVMapperState *s, bool insn)
+{
+    GList *rglist = NULL;
+    OtRegionRange *ranges = insn ? s->iranges : s->dranges;
+    unsigned range_count = s->trans_count + (insn ? s->noexec_count : 0);
+
+    /* create sortable range items and add them to a new list */
+    for (unsigned ix = 0; ix < range_count; ix++) {
+        const OtRegionRange *crg = &ranges[ix];
+
+        /* ignore disabled range entries */
+        if (!crg->active) {
+            continue;
+        }
+
+        /* duplicate range since it may be modified */
+        OtRegionRange *range = g_new0(OtRegionRange, 1);
+        memcpy(range, crg, sizeof(OtRegionRange));
+
+        rglist = g_list_prepend(rglist, range);
+    }
+
+    if (rglist) {
+        VMAP_SHOW_RANGE_LIST(s, insn, rglist, "initial");
+
+        /* sort the list, in start address order (end address if start are
+         * equal) */
+        rglist = g_list_sort_with_data(rglist, &ot_vmapper_compare, NULL);
+
+        VMAP_SHOW_RANGE_LIST(s, insn, rglist, "sorted");
+
+        rglist = ot_vmapper_range_discretize(s, rglist);
+
+        VMAP_SHOW_RANGE_LIST(s, insn, rglist, "discretized");
+
+        /* now rglist contains a list of unique range permissions */
+
+        /*
+         * split ranges that span across execution disabled HW regions and
+         * disable ranges that redirect execution disabled HW regions
+         */
+        if (insn) {
+            rglist = ot_vmapper_range_split_noexec(s, rglist);
+
+            VMAP_SHOW_RANGE_LIST(s, insn, rglist, "split_nx");
+        }
+
+        /* fill all empty gaps with denied ranges */
+        rglist = ot_vmapper_fill_empty_gaps(s, rglist, insn);
+
+        VMAP_SHOW_RANGE_LIST(s, insn, rglist, "extended");
+
+        /* combine adjacent items sharing the same properties */
+        rglist = ot_vmapper_fuse(s, rglist);
+
+        VMAP_SHOW_RANGE_LIST(s, insn, rglist, "fused");
+    } else {
+        /* create a one item list with no access for the whole address range */
+        rglist = ot_vmapper_fill_empty_gaps(s, rglist, insn);
+
+        VMAP_SHOW_RANGE_LIST(s, insn, rglist, "default");
+    }
+
+    /* rglist is freed on return */
+    ot_vmapper_rebuild_tree(s, insn, rglist);
+
+    s->lranges[insn] = NULL;
+
+    VMAP_SHOW_RANGE_TREE(s, insn);
+}
+
+static void ot_vmapper_translate(OtVMapperState *s, bool insn, unsigned slot,
+                                 hwaddr src, hwaddr dst, size_t size)
+{
+    g_assert(slot < s->trans_count);
+    g_assert(src < UINT32_MAX);
+    g_assert(dst < UINT32_MAX);
+    g_assert(src + size <= UINT32_MAX);
+    g_assert(dst + size <= UINT32_MAX);
+
+    /*
+     * QEMU virtual address implementation is built around the size of a small
+     * MMU page, usually 4KiB. Any attempt to use non-aligned address or size
+     * makes QEMU fall back on a 1-byte page size, which leads to terrible
+     * performance issues (this usually translates into up to 3 lookups per
+     * instruction fetch or data access). This mode is not even supported here
+     * as it makes QEMU unusable.
+     *
+     * Virtual remapper should not be used when non-aligned remapping are
+     * expected. See ot_ibex_wrapper for more details.
+     */
+    struct {
+        const char *name;
+        uint32_t value;
+    } checks[] = {
+        { "source", (uint32_t)src },
+        { "dest", (uint32_t)dst },
+        { "size", (uint32_t)size },
+    };
+    for (unsigned cix = 0; cix < ARRAY_SIZE(checks); cix++) {
+        if (!s->silent_align && (checks[cix].value & (TARGET_PAGE_SIZE - 1u))) {
+            error_report("%s: %s %s %s (0x%08x) is not aligned on 4KiB, "
+                         "translation may fail",
+                         __func__, s->ot_id, insn ? "insn" : "data",
+                         checks[cix].name, checks[cix].value);
+            s->silent_align = true;
+        }
+    }
+
+    OtRegionRange *ranges = insn ? s->iranges : s->dranges;
+    OtRegionRange *range = &ranges[slot];
+
+    bool activated = range->active;
+    range->start = src;
+    range->end = size ? src + size - 1u : src;
+    range->dest = dst;
+    range->execute = insn;
+    range->active = size != 0;
+
+    if (activated != range->active) {
+        if (size) {
+            trace_ot_vmapper_translate_enable(s->ot_id, insn, slot, src, dst,
+                                              size);
+        } else {
+            trace_ot_vmapper_translate_disable(s->ot_id, insn, slot);
+        }
+        s->show = true;
+    }
+
+    ot_vmapper_update(s, insn);
+    s->show = false;
+
+    tlb_flush_all_cpus_synced(s->cpu);
+}
+
+static unsigned
+ot_vmapper_find_exec_slot(OtVMapperState *s, uint32_t start, uint32_t end)
+{
+    unsigned slot = UINT_MAX;
+
+    for (unsigned ix = 0; ix < (unsigned)s->noexec_count; ix++) {
+        OtRegionRange *irange = &s->iranges[s->trans_count + ix];
+        if (!irange->active) {
+            if (slot == UINT_MAX) {
+                /* store first free slot */
+                slot = s->trans_count + ix;
+            }
+            continue;
+        }
+        if (irange->start == start && irange->end == end) {
+            /* may override the first non-active slot */
+            slot = s->trans_count + ix;
+            continue;
+        }
+        /* ensure there is no active slot that overlaps the new one */
+        if (irange->start <= end && irange->end >= start) {
+            error_report("%s: %s: range 0x%08x..0x%08x would overlaps slot %u "
+                         "0x%08x..0x%08x",
+                         __func__, s->ot_id, start, end, s->trans_count + ix,
+                         irange->start, irange->end);
+            g_assert_not_reached();
+        }
+    }
+
+    if (slot == UINT_MAX) {
+        error_report("%s: %s: invalid exec slot 0x%08x..0x%08x\n", __func__,
+                     s->ot_id, start, end);
+        g_assert_not_reached();
+    }
+
+    return slot;
+}
+
+static hwaddr ot_vmapper_get_mr_abs_address(const MemoryRegion *mr)
+{
+    const MemoryRegion *root;
+    hwaddr abs_addr = 0;
+
+    abs_addr += mr->addr;
+    for (root = mr; root->container;) {
+        root = root->container;
+        abs_addr += root->addr;
+    }
+
+    return abs_addr;
+}
+
+static void ot_vmapper_disable_exec(OtVMapperState *s, const MemoryRegion *mr,
+                                    bool disable)
+{
+    hwaddr base = ot_vmapper_get_mr_abs_address(mr);
+    size_t size = int128_getlo(mr->size);
+
+    g_assert(base < UINT32_MAX);
+    g_assert(base + size <= UINT32_MAX);
+
+    uint32_t start = (uint32_t)base;
+    uint32_t end = size ? base + (uint32_t)size - 1u : start;
+
+    unsigned slot = ot_vmapper_find_exec_slot(s, start, end);
+    trace_ot_vmapper_disable_exec(s->ot_id, slot, memory_region_name(mr), start,
+                                  (uint32_t)size, disable);
+
+    OtRegionRange *irange = &s->iranges[slot];
+    irange->start = start;
+    irange->dest = start; /* no translation, only exec disablement */
+    irange->end = end;
+    /* whatever the execution settings, reserves this slot */
+    irange->active = true;
+    irange->execute = !disable;
+
+    s->show = true;
+    ot_vmapper_update(s, true);
+    s->show = false;
+
+    tlb_flush_all_cpus_synced(s->cpu);
+}
+
+static CPUState *ot_vmapper_retrieve_cpu(OtVMapperState *s)
+{
+    DeviceState *cs =
+        ibex_get_child_device(DEVICE(OBJECT(s)->parent), TYPE_RISCV_CPU, 0);
+    return cs ? CPU(cs) : NULL;
+}
+
+static void ot_vmapper_override_vcpu_config(OtVMapperState *s)
+{
+    g_assert(s->cpu);
+
+    RISCVCPUClass *cc = RISCV_CPU_GET_CLASS(s->cpu);
+    RISCVCPU *cpu = RISCV_CPU(s->cpu);
+
+    trace_ot_vmapper_override_vcpu_config(s->ot_id);
+
+    /* reroute riscv_get_physical_address to custom implementation */
+    cc->riscv_get_physical_address = &ot_riscv_get_physical_address;
+    /* force PMP to work with remapped address */
+    cpu->env.vaddr_pmp = true;
+}
+
+static const Property ot_vmapper_properties[] = {
+    DEFINE_PROP_STRING(OT_COMMON_DEV_ID, OtVMapperState, ot_id),
+    DEFINE_PROP_UINT8("cpu_index", OtVMapperState, cpu_idx, UINT8_MAX),
+    DEFINE_PROP_UINT8("trans_count", OtVMapperState, trans_count, UINT8_MAX),
+    DEFINE_PROP_UINT8("noexec_count", OtVMapperState, noexec_count,
+                      OT_VMAPPER_DEFAULT_NOEXEC_REGION_COUNT),
+};
+
+static void ot_vmapper_reset_enter(Object *obj, ResetType type)
+{
+    OtVMapperClass *c = OT_VMAPPER_GET_CLASS(obj);
+    OtVMapperState *s = OT_VMAPPER(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    memset(s->dranges, 0, sizeof(OtRegionRange) * s->trans_count);
+    memset(s->iranges, 0,
+           sizeof(OtRegionRange) * (s->trans_count + s->noexec_count));
+    memset(s->lranges, 0, sizeof(s->lranges));
+
+    for (unsigned ix = 0; ix < s->trans_count; ix++) {
+        s->dranges[ix].prio = VMAP_TRANS_PRIORITY_BASE + ix;
+        s->iranges[ix].prio = VMAP_TRANS_PRIORITY_BASE + ix;
+    }
+    for (unsigned ix = 0; ix < (unsigned)s->noexec_count; ix++) {
+        /*
+         * there is no priority need for disable exec ranges, however they
+         * should always have a priority higher than the remapping ranges.
+         */
+        s->iranges[s->trans_count + ix].prio = 0;
+    }
+
+    s->insert_mode = false;
+    s->show = false;
+    s->silent_align = false;
+
+    ot_vmapper_flush_tree(s, s->dtree);
+    ot_vmapper_flush_tree(s, s->itree);
+
+    s->cpu = ot_vmapper_retrieve_cpu(s);
+}
+
+static void ot_vmapper_reset_exit(Object *obj, ResetType type)
+{
+    OtVMapperClass *c = OT_VMAPPER_GET_CLASS(obj);
+    OtVMapperState *s = OT_VMAPPER(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    ot_vmapper_override_vcpu_config(s);
+
+    ot_vmapper_update(s, false);
+    ot_vmapper_update(s, true);
+}
+
+static void ot_vmapper_realize(DeviceState *dev, Error **errp)
+{
+    OtVMapperState *s = OT_VMAPPER(dev);
+    OtVMapperClass *c = OT_VMAPPER_GET_CLASS(dev);
+    (void)errp;
+
+    if (s->cpu_idx == UINT8_MAX) {
+        CPUState *cs = ot_vmapper_retrieve_cpu(s);
+        if (cs) {
+            s->cpu_idx = cs->cpu_index;
+        }
+    }
+
+    /*
+     * if the CPU cannot be retrieved from our parent, it needs to be configured
+     * from a property
+     */
+    g_assert(s->cpu_idx != UINT8_MAX);
+
+    c->instances[s->cpu_idx] = s;
+
+    s->dranges = g_new0(OtRegionRange, s->trans_count);
+    s->iranges = g_new0(OtRegionRange, s->trans_count + s->noexec_count);
+}
+
+static void ot_vmapper_init(Object *obj)
+{
+    OtVMapperState *s = OT_VMAPPER(obj);
+
+    if (!ot_vmapper_class->instances) {
+        OtVMapperClass *vc = OT_VMAPPER_GET_CLASS(obj);
+        vc->num_instances = MACHINE(qdev_get_machine())->smp.cpus;
+        vc->instances = g_new0(OtVMapperState *, vc->num_instances);
+    }
+
+    /*
+     * Binary trees where key is a translation region start address and value
+     * is an active translation region (OtRegionRange).
+     */
+    s->dtree = ot_vmapper_create_tree(s);
+    s->itree = ot_vmapper_create_tree(s);
+}
+
+static void ot_vmapper_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &ot_vmapper_realize;
+    device_class_set_props(dc, ot_vmapper_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    OtVMapperClass *vc = OT_VMAPPER_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &ot_vmapper_reset_enter, NULL,
+                                       &ot_vmapper_reset_exit,
+                                       &vc->parent_phases);
+
+    vc->translate = &ot_vmapper_translate;
+    vc->disable_exec = &ot_vmapper_disable_exec;
+
+    ot_vmapper_class = vc;
+}
+
+static const TypeInfo ot_vmapper_info = {
+    .name = TYPE_OT_VMAPPER,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(OtVMapperState),
+    .instance_init = &ot_vmapper_init,
+    .class_size = sizeof(OtVMapperClass),
+    .class_init = &ot_vmapper_class_init,
+};
+
+static void ot_vmapper_register_types(void)
+{
+    type_register_static(&ot_vmapper_info);
+}
+
+type_init(ot_vmapper_register_types);
diff --git a/hw/opentitan/otbn/Kconfig b/hw/opentitan/otbn/Kconfig
new file mode 100644
index 0000000000000..c861aa0ddf9fc
--- /dev/null
+++ b/hw/opentitan/otbn/Kconfig
@@ -0,0 +1,2 @@
+config OT_BIGNUMBER
+    bool
diff --git a/hw/opentitan/otbn/LICENSE b/hw/opentitan/otbn/LICENSE
new file mode 100644
index 0000000000000..d0c55eec33113
--- /dev/null
+++ b/hw/opentitan/otbn/LICENSE
@@ -0,0 +1,191 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
+          attribution notices from the Source form of the Work,
+          excluding those notices that do not pertain to any part of
+          the Derivative Works; and
+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+---- LLVM Exceptions to the Apache 2.0 License ----
+
+As an exception, if, as a result of your compiling your source code, portions of
+this Software are embedded into an Object form of such source code, you may
+redistribute such embedded portions in such Object form without complying with
+the conditions of Sections 4(a), 4(b) and 4(d) of the License.
+
+In addition, if you combine or link compiled forms of this Software with
+software that is licensed under the GPLv2 ("Combined Software") and if a court
+of competent jurisdiction determines that the patent provision (Section 3), the
+indemnity provision (Section 9) or other Section of the License conflicts with
+the conditions of the GPLv2, you may retroactively and prospectively choose to
+deem waived or otherwise exclude such Section(s) of the License, but only in
+their entirety and only with respect to the Combined Software.
+
+   END OF TERMS AND CONDITIONS
diff --git a/hw/opentitan/otbn/README.md b/hw/opentitan/otbn/README.md
new file mode 100644
index 0000000000000..d0785a91ee7ee
--- /dev/null
+++ b/hw/opentitan/otbn/README.md
@@ -0,0 +1,7 @@
+# Rust OpenTitan BigNumber Simulator (otbn-rs)
+
+A fork of the https://github.com/GregAC/rrs.git Rust RISC-V simulator, dedicated
+to the OTBN accelerator.
+
+RRS and the OTBN simulator are released under the Apache License Version 2.0,
+with LLVM Exceptions, see LICENSE for details.
diff --git a/hw/opentitan/otbn/meson.build b/hw/opentitan/otbn/meson.build
new file mode 100644
index 0000000000000..a743e17bab0d1
--- /dev/null
+++ b/hw/opentitan/otbn/meson.build
@@ -0,0 +1,29 @@
+bitflags_dep = subproject('bitflags').get_variable('bitflags_dep')
+paste_dep = subproject('paste').get_variable('paste_dep')
+ethnum_dep = subproject('ethnum-rs').get_variable('ethnum_dep')
+
+if build_machine.system() == 'linux'
+    dl_dep = cc.find_library('dl', required: false)
+else
+    dl_dep = dependency('', required: false)
+endif
+
+if build_machine.system() == 'linux'
+    dl_dep = cc.find_library('dl', required: false)
+else
+    dl_dep = dependency('', required: false)
+endif
+
+otbn_lib = static_library('otbn',
+                          files('otbn/src/lib.rs'),
+                          dependencies: [
+                            bitflags_dep,
+                            paste_dep,
+                            ethnum_dep,
+                            dl_dep],
+                          rust_crate_type: 'staticlib')
+
+otbn_dep = declare_dependency(link_with: otbn_lib)
+
+system_ss.add(when: 'CONFIG_OT_BIGNUMBER',
+              if_true: otbn_dep)
diff --git a/hw/opentitan/otbn/otbn/Cargo.toml b/hw/opentitan/otbn/otbn/Cargo.toml
new file mode 100644
index 0000000000000..8620eebe2a7da
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/Cargo.toml
@@ -0,0 +1,17 @@
+[package]
+name = "otbn-lib"
+version = "0.1.0"
+authors = ["Greg Chadwick <mail@gregchadwick.co.uk>",
+           "Emmanuel Blot <eblot@rivosinc.com>"]
+edition = "2018"
+license = "Apache-2.0 WITH LLVM-exception"
+keywords = ["opentitan", "emulator"]
+categories = ["emulators"]
+description = "A library for building OpenTitan Big Number simulators"
+
+# Heavily based on RSS work from Greg Chadwick https://gregchadwick.co.uk/blog/building-rrs-pt1/
+
+[dependencies]
+paste = "1"
+bitflags = "1"
+ethnum = "1"
diff --git a/hw/opentitan/otbn/otbn/meson.build b/hw/opentitan/otbn/otbn/meson.build
new file mode 100644
index 0000000000000..82a02d1072675
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/meson.build
@@ -0,0 +1,7 @@
+project('otbn', 'rust', version: '0.1.0')
+
+otbn_lib = static_library('otbn',
+                          'src/lib.rs',
+                          install: true)
+
+otbn_dep = declare_dependency(link_with: otbn_lib)
diff --git a/hw/opentitan/otbn/otbn/src/comm.rs b/hw/opentitan/otbn/otbn/src/comm.rs
new file mode 100644
index 0000000000000..e134f34df6086
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/comm.rs
@@ -0,0 +1,35 @@
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use std::fs::File;
+use std::io;
+use std::sync::mpsc;
+use std::thread;
+
+/// Commands the client may send to the executer
+pub enum Command {
+    SetTestMode(bool),
+    LogTo(Box<io::BufWriter<File>>),
+    Execute(bool),
+    WipeDMem,
+    WipeIMem,
+    Terminate,
+}
+
+/// Replies the executer may send back to the client
+pub enum Response {
+    Active(thread::ThreadId),
+    Ack,
+    Error(String),
+}
+
+/// Channel to send commands from the client to the executer and to receive response back from it
+pub type DownChannel = (mpsc::Sender<Command>, mpsc::Receiver<Response>);
+/// Channel to receive commands from the client and to send it back responses
+pub type UpChannel = (mpsc::Receiver<Command>, mpsc::Sender<Response>);
+
+/// A callback trait for core signalling
+pub trait Callback: Send {
+    fn signal(&mut self);
+}
diff --git a/hw/opentitan/otbn/otbn/src/csrs.rs b/hw/opentitan/otbn/otbn/src/csrs.rs
new file mode 100644
index 0000000000000..46ae6515887f3
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/csrs.rs
@@ -0,0 +1,556 @@
+// Copyright 2021 Gregory Chadwick <mail@gregchadwick.co.uk>
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use std::cell::Cell;
+use std::convert::TryFrom;
+use std::rc::Rc;
+use std::sync::{Arc, Mutex};
+
+use ethnum::{u256, U256};
+
+use super::insn_proc;
+use super::key;
+use super::otbn::FlagMode;
+use super::random;
+use super::{CSR, WSR};
+use crate::{ExceptionCause, CSRNG, PRNG};
+
+#[derive(PartialEq, Eq, Clone, Copy, Debug)]
+#[repr(u32)]
+#[allow(non_camel_case_types)]
+pub enum CSRAddr {
+    // OTBN custom CSRs
+    fg0 = 0x7c0,
+    fg1 = 0x7c1,
+    flags = 0x7c8,
+    mod0 = 0x7d0,
+    mod1 = 0x7d1,
+    mod2 = 0x7d2,
+    mod3 = 0x7d3,
+    mod4 = 0x7d4,
+    mod5 = 0x7d5,
+    mod6 = 0x7d6,
+    mod7 = 0x7d7,
+    rnd_prefetch = 0x7d8,
+    rnd = 0xfc0,  // CSRNG
+    urnd = 0xfc1, // PRNG
+}
+
+impl TryFrom<u32> for CSRAddr {
+    type Error = u32;
+
+    fn try_from(value: u32) -> Result<Self, Self::Error> {
+        match value {
+            0x7c0 => Ok(Self::fg0),
+            0x7c1 => Ok(Self::fg1),
+            0x7c8 => Ok(Self::flags),
+            0x7d0 => Ok(Self::mod0),
+            0x7d1 => Ok(Self::mod1),
+            0x7d2 => Ok(Self::mod2),
+            0x7d3 => Ok(Self::mod3),
+            0x7d4 => Ok(Self::mod4),
+            0x7d5 => Ok(Self::mod5),
+            0x7d6 => Ok(Self::mod6),
+            0x7d7 => Ok(Self::mod7),
+            0x7d8 => Ok(Self::rnd_prefetch),
+            0xfc0 => Ok(Self::rnd),
+            0xfc1 => Ok(Self::urnd),
+            _ => Err(value),
+        }
+    }
+}
+
+#[allow(clippy::from_over_into)]
+impl Into<u32> for CSRAddr {
+    fn into(self) -> u32 {
+        self as u32
+    }
+}
+
+impl CSRAddr {
+    pub fn string_name(csr_addr: u32) -> String {
+        match Self::try_from(csr_addr) {
+            Ok(csr) => format!("{:?}", csr),
+            Err(_) => format!("0x{:03x}", csr_addr),
+        }
+    }
+}
+
+#[derive(PartialEq, Eq, Clone, Copy, Debug)]
+#[repr(u32)]
+#[allow(non_camel_case_types)]
+pub enum WSRAddr {
+    r#mod = 0x0,
+    rnd = 0x1,
+    urnd = 0x2,
+    acc = 0x3,
+    key_s0_l = 0x4,
+    key_s0_h = 0x5,
+    key_s1_l = 0x6,
+    key_s1_h = 0x7,
+}
+
+impl TryFrom<u32> for WSRAddr {
+    type Error = u32;
+
+    fn try_from(value: u32) -> Result<Self, Self::Error> {
+        match value {
+            0x0 => Ok(Self::r#mod),
+            0x1 => Ok(Self::rnd),
+            0x2 => Ok(Self::urnd),
+            0x3 => Ok(Self::acc),
+            0x4 => Ok(Self::key_s0_l),
+            0x5 => Ok(Self::key_s0_h),
+            0x6 => Ok(Self::key_s1_l),
+            0x7 => Ok(Self::key_s1_h),
+            _ => Err(value),
+        }
+    }
+}
+
+#[allow(clippy::from_over_into)]
+impl Into<u32> for WSRAddr {
+    fn into(self) -> u32 {
+        self as u32
+    }
+}
+
+impl WSRAddr {
+    pub fn string_name(wsr_addr: u32) -> String {
+        match Self::try_from(wsr_addr) {
+            Ok(wsr) => format!("{:?}", wsr),
+            Err(_) => format!("0x{:03x}", wsr_addr),
+        }
+    }
+}
+
+#[derive(Default)]
+struct CSRFlagGroup {
+    flags: SharedFlags,
+    mode: Option<FlagMode>,
+}
+
+impl CSRFlagGroup {
+    pub fn plug(&mut self, flags: &SharedFlags, mode: FlagMode) {
+        self.flags = Rc::clone(flags);
+        self.mode = Some(mode);
+    }
+}
+
+impl CSR for CSRFlagGroup {
+    fn read(&self) -> Result<u32, ExceptionCause> {
+        let val8 = match self.mode.as_ref().unwrap() {
+            FlagMode::Fg0 => self.flags.get()[0].bits(),
+            FlagMode::Fg1 => self.flags.get()[1].bits(),
+            FlagMode::Flags => self.flags.get()[0].bits() | self.flags.get()[1].bits() << 4,
+        };
+        Ok(val8 as u32)
+    }
+
+    fn write(&mut self, val: u32) -> Result<(), ExceptionCause> {
+        let val8 = val as u8;
+        let mut flags = self.flags.get();
+        match self.mode.as_ref().unwrap() {
+            FlagMode::Fg0 => flags[0] = insn_proc::Flags::from_bits_truncate(val8 & 0x0f),
+            FlagMode::Fg1 => flags[1] = insn_proc::Flags::from_bits_truncate(val8 & 0x0f),
+            FlagMode::Flags => {
+                flags[0] = insn_proc::Flags::from_bits_truncate(val8 & 0x0f);
+                flags[1] = insn_proc::Flags::from_bits_truncate(val8 & 0x0f);
+            }
+        };
+        self.flags.set(flags);
+        Ok(())
+    }
+}
+
+type SharedFlags = Rc<Cell<[insn_proc::Flags; 2]>>;
+
+#[derive(Default)]
+struct CSRMod {
+    wsg: Rc<Cell<u256>>,
+    pos: Option<u32>,
+}
+
+impl CSR for CSRMod {
+    fn read(&self) -> Result<u32, ExceptionCause> {
+        let mut val256: u256 = self.wsg.get();
+        val256 >>= self.pos.unwrap() * 32;
+        val256 &= U256::from(u32::MAX);
+        Ok(val256.as_u32())
+    }
+
+    fn write(&mut self, val: u32) -> Result<(), ExceptionCause> {
+        let mut val256: u256 = self.wsg.get();
+        let shift = self.pos.unwrap() * 32;
+        val256 &= !(U256::from(u32::MAX).wrapping_shl(shift));
+        val256 |= U256::from(val).wrapping_shl(shift);
+        self.wsg.set(val256);
+        Ok(())
+    }
+}
+
+impl CSRMod {
+    fn plug(&mut self, wsg: &CSRWideSharedGeneric, pos: usize) {
+        self.wsg = Rc::clone(&wsg.val);
+        self.pos = Some(pos as u32);
+    }
+}
+
+/// CryptoSecure Random generator
+struct CSRRnd {
+    rng: Arc<random::Rnd>,
+}
+
+impl CSRRnd {
+    pub fn new(rng: Arc<random::Rnd>) -> Self {
+        Self { rng }
+    }
+}
+
+impl CSR for CSRRnd {
+    fn read(&self) -> Result<u32, ExceptionCause> {
+        let (val, fips, repeat) = self.rng.get_csrng_u32();
+        if !fips {
+            Err(ExceptionCause::ERndFipsChkFail)
+        } else if repeat {
+            Err(ExceptionCause::ERndRepChkFail)
+        } else {
+            Ok(val)
+        }
+    }
+
+    fn write(&mut self, _val: u32) -> Result<(), ExceptionCause> {
+        // as per OTBN definition, do not generate an error for R/O CSR
+        Ok(())
+    }
+}
+
+/// CryptoSecure Random generator
+struct CSRWideRnd {
+    rng: Arc<random::Rnd>,
+}
+
+impl CSRWideRnd {
+    pub fn new(rng: Arc<random::Rnd>) -> Self {
+        Self { rng }
+    }
+}
+
+impl WSR for CSRWideRnd {
+    fn read(&self) -> Result<u256, ExceptionCause> {
+        let (val, fips, repeat) = self.rng.get_csrng_u256();
+        if !fips {
+            Err(ExceptionCause::ERndFipsChkFail)
+        } else if repeat {
+            Err(ExceptionCause::ERndRepChkFail)
+        } else {
+            Ok(val)
+        }
+    }
+
+    fn write(&mut self, _val: u256) -> Result<(), ExceptionCause> {
+        // as per OTBN definition, do not generate an error for R/O CSR
+        Ok(())
+    }
+}
+
+/// Pseudo Random generator
+struct CSRUrnd {
+    prng: Arc<Mutex<dyn PRNG>>,
+}
+
+impl CSRUrnd {
+    pub fn new(prng: Arc<Mutex<dyn PRNG>>) -> Self {
+        Self { prng }
+    }
+}
+
+impl CSR for CSRUrnd {
+    fn read(&self) -> Result<u32, ExceptionCause> {
+        Ok(self.prng.lock().unwrap().get_prng_u32())
+    }
+
+    fn write(&mut self, _val: u32) -> Result<(), ExceptionCause> {
+        // as per OTBN definition, do not generate an error for R/O CSR
+        Ok(())
+    }
+}
+
+/// Pseudo Random generator
+struct CSRWideUrnd {
+    prng: Arc<Mutex<dyn PRNG>>,
+    test_mode: bool,
+}
+
+impl CSRWideUrnd {
+    pub fn new(prng: Arc<Mutex<dyn PRNG>>) -> Self {
+        Self {
+            prng,
+            test_mode: false,
+        }
+    }
+}
+
+impl WSR for CSRWideUrnd {
+    fn read(&self) -> Result<u256, ExceptionCause> {
+        if !self.test_mode {
+            Ok(self.prng.lock().unwrap().get_prng_u256())
+        } else {
+            Ok(U256::from_str_radix(
+                "AAAAAAAA99999999AAAAAAAA99999999AAAAAAAA99999999AAAAAAAA99999999",
+                16,
+            )
+            .unwrap())
+        }
+    }
+
+    fn write(&mut self, _val: u256) -> Result<(), ExceptionCause> {
+        // as per OTBN definition, do not generate an error for R/O CSR
+        Ok(())
+    }
+}
+
+struct CSRRndPrefetcher {
+    rng: Arc<random::Rnd>,
+}
+
+impl CSRRndPrefetcher {
+    pub fn new(rng: Arc<random::Rnd>) -> Self {
+        Self { rng }
+    }
+}
+
+impl CSR for CSRRndPrefetcher {
+    fn read(&self) -> Result<u32, ExceptionCause> {
+        Ok(0) // always 0
+    }
+
+    fn write(&mut self, _val: u32) -> Result<(), ExceptionCause> {
+        // "Writing any value to the RND_PREFETCH CSR initiates a prefetch."
+        self.rng.prefetch();
+        Ok(())
+    }
+}
+
+/// CryptoSecure Random generator
+struct CSRWideKey {
+    key: Arc<key::Key>,
+    share: u8,
+    high: bool,
+}
+
+impl CSRWideKey {
+    pub fn new(key: Arc<key::Key>, share: u8, high: bool) -> Self {
+        Self { key, share, high }
+    }
+}
+
+impl WSR for CSRWideKey {
+    fn read(&self) -> Result<u256, ExceptionCause> {
+        let store = self.key.store.lock().unwrap();
+        if !store.valid {
+            return Err(ExceptionCause::EKeyInvalid);
+        }
+        let share = if self.share == 0 { store.lo } else { store.hi };
+        let value = share[self.high as usize];
+        Ok(value)
+    }
+
+    fn write(&mut self, _val: u256) -> Result<(), ExceptionCause> {
+        // as per OTBN definition, do not generate an error for R/O CSR
+        Ok(())
+    }
+}
+
+#[derive(Default)]
+struct CSRWideGeneric {
+    pub val: u256,
+}
+
+impl WSR for CSRWideGeneric {
+    fn read(&self) -> Result<u256, ExceptionCause> {
+        Ok(self.val)
+    }
+
+    fn write(&mut self, val: u256) -> Result<(), ExceptionCause> {
+        self.val = val;
+        Ok(())
+    }
+}
+
+#[derive(Default)]
+struct CSRWideSharedGeneric {
+    // TBC: why can't I use an Option<Rc<Cell<u256>>> here (Copy trait)?
+    pub val: Rc<Cell<u256>>,
+}
+
+impl WSR for CSRWideSharedGeneric {
+    fn read(&self) -> Result<u256, ExceptionCause> {
+        Ok(self.val.get())
+    }
+
+    fn write(&mut self, val: u256) -> Result<(), ExceptionCause> {
+        self.val.set(val);
+        Ok(())
+    }
+}
+
+pub struct CSRSet {
+    fg0: CSRFlagGroup,
+    fg1: CSRFlagGroup,
+    flags: CSRFlagGroup,
+    mods: [CSRMod; 8],
+    rndprefetch: CSRRndPrefetcher,
+    rnd: CSRRnd,
+    urnd: CSRUrnd,
+
+    r#mod: CSRWideSharedGeneric,
+    wrnd: CSRWideRnd,
+    wurnd: CSRWideUrnd,
+    acc: CSRWideGeneric,
+    key_s0_l: CSRWideKey,
+    key_s0_h: CSRWideKey,
+    key_s1_l: CSRWideKey,
+    key_s1_h: CSRWideKey,
+
+    shared_flags: SharedFlags,
+}
+
+impl CSRSet {
+    pub fn new(urnd: Arc<Mutex<dyn PRNG>>, rnd: Arc<random::Rnd>, key: Arc<key::Key>) -> Self {
+        let mut csrs = Self {
+            fg0: CSRFlagGroup::default(),
+            fg1: CSRFlagGroup::default(),
+            flags: CSRFlagGroup::default(),
+            mods: <[CSRMod; 8]>::default(),
+            rndprefetch: CSRRndPrefetcher::new(rnd.clone()),
+            rnd: CSRRnd::new(rnd.clone()),
+            urnd: CSRUrnd::new(urnd.clone()),
+            r#mod: CSRWideSharedGeneric::default(),
+            wrnd: CSRWideRnd::new(rnd),
+            wurnd: CSRWideUrnd::new(urnd.clone()),
+            acc: CSRWideGeneric::default(),
+            key_s0_l: CSRWideKey::new(key.clone(), 0, false),
+            key_s0_h: CSRWideKey::new(key.clone(), 0, true),
+            key_s1_l: CSRWideKey::new(key.clone(), 1, false),
+            key_s1_h: CSRWideKey::new(key.clone(), 1, true),
+            shared_flags: SharedFlags::default(),
+        };
+        csrs.fg0.plug(&csrs.shared_flags, FlagMode::Fg0);
+        csrs.fg1.plug(&csrs.shared_flags, FlagMode::Fg1);
+        csrs.flags.plug(&csrs.shared_flags, FlagMode::Flags);
+        for (pos, otmod) in csrs.mods.iter_mut().enumerate() {
+            otmod.plug(&csrs.r#mod, pos)
+        }
+        csrs
+    }
+
+    pub fn get_flags(&self, fg: usize) -> insn_proc::Flags {
+        self.shared_flags.get()[fg]
+    }
+
+    pub fn set_flags(&mut self, fg: usize, value: insn_proc::Flags) {
+        let mut flags = self.shared_flags.get();
+        flags[fg] = value;
+        self.shared_flags.set(flags);
+    }
+
+    pub fn get_csr(&self, addr: u32) -> Option<&dyn CSR> {
+        let csr_addr = CSRAddr::try_from(addr).ok()?;
+
+        // note: we do not want to use num_enum here that draws to many dependencies
+        Some(match csr_addr {
+            CSRAddr::fg0 => &self.fg0,
+            CSRAddr::fg1 => &self.fg1,
+            CSRAddr::flags => &self.flags,
+            CSRAddr::mod0 => &self.mods[0],
+            CSRAddr::mod1 => &self.mods[1],
+            CSRAddr::mod2 => &self.mods[2],
+            CSRAddr::mod3 => &self.mods[3],
+            CSRAddr::mod4 => &self.mods[4],
+            CSRAddr::mod5 => &self.mods[5],
+            CSRAddr::mod6 => &self.mods[6],
+            CSRAddr::mod7 => &self.mods[7],
+            CSRAddr::rnd_prefetch => &self.rndprefetch,
+            CSRAddr::rnd => &self.rnd,
+            CSRAddr::urnd => &self.urnd,
+        })
+    }
+
+    pub fn get_csr_mut(&mut self, addr: u32) -> Option<&mut dyn CSR> {
+        let csr_addr = CSRAddr::try_from(addr).ok()?;
+
+        // note: we do not want to use num_enum here that draws to many dependencies
+        Some(match csr_addr {
+            CSRAddr::fg0 => &mut self.fg0,
+            CSRAddr::fg1 => &mut self.fg1,
+            CSRAddr::flags => &mut self.flags,
+            CSRAddr::mod0 => &mut self.mods[0],
+            CSRAddr::mod1 => &mut self.mods[1],
+            CSRAddr::mod2 => &mut self.mods[2],
+            CSRAddr::mod3 => &mut self.mods[3],
+            CSRAddr::mod4 => &mut self.mods[4],
+            CSRAddr::mod5 => &mut self.mods[5],
+            CSRAddr::mod6 => &mut self.mods[6],
+            CSRAddr::mod7 => &mut self.mods[7],
+            CSRAddr::rnd_prefetch => &mut self.rndprefetch,
+            CSRAddr::rnd => &mut self.rnd,
+            CSRAddr::urnd => &mut self.urnd,
+        })
+    }
+
+    pub fn get_wsr(&self, addr: u32) -> Option<&dyn WSR> {
+        let wsr_addr = WSRAddr::try_from(addr).ok()?;
+
+        Some(match wsr_addr {
+            WSRAddr::r#mod => &self.r#mod,
+            WSRAddr::rnd => &self.wrnd,
+            WSRAddr::urnd => &self.wurnd,
+            WSRAddr::acc => &self.acc,
+            WSRAddr::key_s0_l => &self.key_s0_l,
+            WSRAddr::key_s0_h => &self.key_s0_h,
+            WSRAddr::key_s1_l => &self.key_s1_l,
+            WSRAddr::key_s1_h => &self.key_s1_h,
+        })
+    }
+
+    pub fn get_wsr_mut(&mut self, addr: u32) -> Option<&mut dyn WSR> {
+        let wsr_addr = WSRAddr::try_from(addr).ok()?;
+
+        Some(match wsr_addr {
+            WSRAddr::r#mod => &mut self.r#mod,
+            WSRAddr::rnd => &mut self.wrnd,
+            WSRAddr::urnd => &mut self.wurnd,
+            WSRAddr::acc => &mut self.acc,
+            WSRAddr::key_s0_l => &mut self.key_s0_l,
+            WSRAddr::key_s0_h => &mut self.key_s0_h,
+            WSRAddr::key_s1_l => &mut self.key_s1_l,
+            WSRAddr::key_s1_h => &mut self.key_s1_h,
+        })
+    }
+
+    pub fn wipe_internal(&mut self, prng: &Arc<Mutex<dyn PRNG>>) {
+        /*
+         * real HW performs a two-step process:
+         * - wipe with PRNG randomness
+         * - zero
+         */
+        for flag in self.shared_flags.get().iter_mut() {
+            *flag = insn_proc::Flags::empty();
+        }
+
+        let mut prng = prng.lock().unwrap();
+
+        let _ = self.acc.write(U256::from(0u32));
+        let _ = self.r#mod.write(U256::from(0u32));
+
+        let _ = self.acc.write(prng.get_prng_u256());
+        let _ = self.r#mod.write(prng.get_prng_u256());
+    }
+
+    pub fn set_test_mode(&mut self, enable: bool) {
+        self.wurnd.test_mode = enable;
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/insn_decode.rs b/hw/opentitan/otbn/otbn/src/insn_decode.rs
new file mode 100644
index 0000000000000..4c2a5a76e0ab5
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/insn_decode.rs
@@ -0,0 +1,290 @@
+// Copyright 2021 Gregory Chadwick <mail@gregchadwick.co.uk>
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use super::insn_format;
+use super::insn_proc;
+
+fn process_opcode_op<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    let dec_insn = insn_format::RType::new(insn_bits);
+
+    match dec_insn.funct3 {
+        0b000 => match dec_insn.funct7 {
+            0b000_0000 => Some(processor.process_add(dec_insn)),
+            0b010_0000 => Some(processor.process_sub(dec_insn)),
+            _ => None,
+        },
+        0b001 => match dec_insn.funct7 {
+            0b000_0000 => Some(processor.process_sll(dec_insn)),
+            _ => None,
+        },
+        0b100 => match dec_insn.funct7 {
+            0b000_0000 => Some(processor.process_xor(dec_insn)),
+            _ => None,
+        },
+        0b101 => match dec_insn.funct7 {
+            0b000_0000 => Some(processor.process_srl(dec_insn)),
+            0b010_0000 => Some(processor.process_sra(dec_insn)),
+            _ => None,
+        },
+        0b110 => match dec_insn.funct7 {
+            0b000_0000 => Some(processor.process_or(dec_insn)),
+            _ => None,
+        },
+        0b111 => match dec_insn.funct7 {
+            0b000_0000 => Some(processor.process_and(dec_insn)),
+            _ => None,
+        },
+        _ => None,
+    }
+}
+
+fn process_opcode_op_imm<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    let dec_insn = insn_format::IType::new(insn_bits);
+
+    match dec_insn.funct3 {
+        0b000 => Some(processor.process_addi(dec_insn)),
+        0b001 => Some(processor.process_slli(insn_format::ITypeShamt::new(insn_bits))),
+        0b100 => Some(processor.process_xori(dec_insn)),
+        0b101 => {
+            let dec_insn_shamt = insn_format::ITypeShamt::new(insn_bits);
+            match dec_insn_shamt.funct7 {
+                0b000_0000 => Some(processor.process_srli(dec_insn_shamt)),
+                0b010_0000 => Some(processor.process_srai(dec_insn_shamt)),
+                _ => None,
+            }
+        }
+        0b110 => Some(processor.process_ori(dec_insn)),
+        0b111 => Some(processor.process_andi(dec_insn)),
+        _ => None,
+    }
+}
+
+fn process_opcode_op32<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    let dec_insn = insn_format::RType::new(insn_bits);
+
+    let (b30, b29) = (
+        (dec_insn.funct7 >> 4 & 0b10) != 0,
+        (dec_insn.funct7 >> 4 & 0b01) != 0,
+    );
+    match (b30, b29) {
+        (false, false) => Some(processor.process_bn_mulqacc(dec_insn)),
+        (false, true) => Some(processor.process_bn_mulqacc_wo(dec_insn)),
+        (true, _) => Some(processor.process_bn_mulqacc_so(dec_insn)),
+    }
+}
+
+fn process_opcode_branch<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    let dec_insn = insn_format::BType::new(insn_bits);
+
+    match dec_insn.funct3 {
+        0b000 => Some(processor.process_beq(dec_insn)),
+        0b001 => Some(processor.process_bne(dec_insn)),
+        _ => None,
+    }
+}
+
+fn process_opcode_load<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    let dec_insn = insn_format::IType::new(insn_bits);
+
+    match dec_insn.funct3 {
+        0b010 => Some(processor.process_lw(dec_insn)),
+        _ => None,
+    }
+}
+
+fn process_opcode_custom0<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    match (insn_bits >> 12) & 0x7 {
+        0b000..=0b011 => {
+            let dec_insn = insn_format::RType::new(insn_bits);
+            match dec_insn.funct3 {
+                0b000 => Some(processor.process_bn_sel(dec_insn)),
+                0b001 => Some(processor.process_bn_cmp(dec_insn)),
+                0b011 => Some(processor.process_bn_cmpb(dec_insn)),
+                _ => None,
+            }
+        }
+        0b100..=0b101 => {
+            let dec_insn = insn_format::WidType::new(insn_bits);
+            match dec_insn.funct3 {
+                0b100 => Some(processor.process_bn_lid(dec_insn)),
+                0b101 => Some(processor.process_bn_sid(dec_insn)),
+                _ => None,
+            }
+        }
+        0b110 => match insn_bits >> 31 & 0b1 {
+            0b0 => {
+                let dec_insn = insn_format::IType::new(insn_bits);
+                Some(processor.process_bn_mov(dec_insn))
+            }
+            0b1 => {
+                let dec_insn = insn_format::SType::new(insn_bits);
+                Some(processor.process_bn_movr(dec_insn))
+            }
+            _ => None,
+        },
+        0b111 => {
+            let dec_insn = insn_format::IType::new(insn_bits);
+
+            match insn_bits >> 31 {
+                0b0 => Some(processor.process_bn_wsrr(dec_insn)),
+                0b1 => Some(processor.process_bn_wsrw(dec_insn)),
+                _ => None,
+            }
+        }
+        _ => None,
+    }
+}
+
+fn process_opcode_store<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    let dec_insn = insn_format::SType::new(insn_bits);
+
+    match dec_insn.funct3 {
+        0b010 => Some(processor.process_sw(dec_insn)),
+        _ => None,
+    }
+}
+
+fn process_opcode_custom1<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    match (insn_bits >> 12) & 0x7 {
+        0b100 => {
+            let dec_insn = insn_format::IType::new(insn_bits);
+            match insn_bits >> 30 & 0b1 {
+                0 => Some(processor.process_bn_addi(dec_insn)),
+                1 => Some(processor.process_bn_subi(dec_insn)),
+                _ => None,
+            }
+        }
+        _ => {
+            let dec_insn = insn_format::RType::new(insn_bits);
+            match dec_insn.funct3 {
+                0b000 => Some(processor.process_bn_add(dec_insn)),
+                0b001 => Some(processor.process_bn_sub(dec_insn)),
+                0b010 => Some(processor.process_bn_addc(dec_insn)),
+                0b011 => Some(processor.process_bn_subb(dec_insn)),
+                0b101 => match insn_bits >> 30 & 0b1 {
+                    0b0 => Some(processor.process_bn_addm(dec_insn)),
+                    0b1 => Some(processor.process_bn_subm(dec_insn)),
+                    _ => None,
+                },
+                _ => None,
+            }
+        }
+    }
+}
+
+fn process_opcode_system<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    let dec_insn = insn_format::ITypeCSR::new(insn_bits);
+
+    match dec_insn.funct3 {
+        0b000 => {
+            if dec_insn.rd != 0 || dec_insn.rs1 != 0 || dec_insn.csr != 0 {
+                None
+            } else {
+                Some(processor.process_ecall())
+            }
+        }
+        0b001 => Some(processor.process_csrrw(dec_insn)),
+        0b010 => Some(processor.process_csrrs(dec_insn)),
+        _ => None,
+    }
+}
+
+fn process_opcode_custom3<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    match (insn_bits >> 12) & 0x7 {
+        0b000..=0b001 => {
+            let dec_insn = insn_format::IType::new(insn_bits);
+            match dec_insn.funct3 {
+                0b000 => Some(processor.process_loop(dec_insn)),
+                0b001 => Some(processor.process_loopi(dec_insn)),
+                _ => None,
+            }
+        }
+        0b010..=0b111 => {
+            let dec_insn = insn_format::RType::new(insn_bits);
+            match dec_insn.funct3 {
+                0b010 => Some(processor.process_bn_and(dec_insn)),
+                0b011 => Some(processor.process_bn_rshi(dec_insn)),
+                0b100 => Some(processor.process_bn_or(dec_insn)),
+                0b101 => Some(processor.process_bn_not(dec_insn)),
+                0b110 => Some(processor.process_bn_xor(dec_insn)),
+                0b111 => Some(processor.process_bn_rshi(dec_insn)),
+                _ => None,
+            }
+        }
+        _ => None,
+    }
+}
+
+/// Decodes instruction in `insn_bits` calling the appropriate function in `processor` returning
+/// the result it produces.
+///
+/// Returns `None` if instruction doesn't decode into a valid instruction.
+pub fn decoder<T: insn_proc::InstructionProcessor>(
+    processor: &mut T,
+    insn_bits: u32,
+) -> Option<T::InstructionResult> {
+    let opcode: u32 = insn_bits & 0x7f;
+
+    match opcode {
+        // LOAD
+        0b000_0011 => process_opcode_load(processor, insn_bits),
+        // custom-0
+        0b000_1011 => process_opcode_custom0(processor, insn_bits),
+        // OP_IMM
+        0b001_0011 => process_opcode_op_imm(processor, insn_bits),
+        // STORE
+        0b010_0011 => process_opcode_store(processor, insn_bits),
+        // custom-1
+        0b010_1011 => process_opcode_custom1(processor, insn_bits),
+        // OP
+        0b011_0011 => process_opcode_op(processor, insn_bits),
+        // LUI
+        0b011_0111 => Some(processor.process_lui(insn_format::UType::new(insn_bits))),
+        // OP32
+        // this one is suspicious, should not it be custom-2 (0b10_110_11) instead?
+        0b011_1011 => process_opcode_op32(processor, insn_bits),
+        // BRANCH
+        0b110_0011 => process_opcode_branch(processor, insn_bits),
+        // JALR
+        0b110_0111 => Some(processor.process_jalr(insn_format::IType::new(insn_bits))),
+        // JAL
+        0b110_1111 => Some(processor.process_jal(insn_format::JType::new(insn_bits))),
+        // SYSTEM
+        0b111_0011 => process_opcode_system(processor, insn_bits),
+        // custom-3
+        0b111_1011 => process_opcode_custom3(processor, insn_bits),
+        _ => None,
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/insn_disasm.rs b/hw/opentitan/otbn/otbn/src/insn_disasm.rs
new file mode 100644
index 0000000000000..6ca0334182658
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/insn_disasm.rs
@@ -0,0 +1,478 @@
+// Copyright 2021 Gregory Chadwick <mail@gregchadwick.co.uk>
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use paste::paste;
+
+use super::csrs;
+use super::insn_format;
+use super::insn_proc;
+
+pub struct InstructionStringOutputter {
+    /// PC of the instruction being output. Used to generate disassembly of
+    /// instructions with PC relative fields (such as BEQ and JAL).
+    pub insn_pc: u32,
+}
+
+// Macros to produce string outputs for various different instruction types
+macro_rules! string_out_for_alu_reg_op {
+    ($name:ident) => {
+        paste! {
+            fn [<process_ $name>](
+                &mut self,
+                dec_insn: insn_format::RType
+            ) -> Self::InstructionResult {
+                format!("{} x{}, x{}, x{}", stringify!($name), dec_insn.rd, dec_insn.rs1,
+                    dec_insn.rs2)
+            }
+        }
+    };
+}
+
+macro_rules! string_out_for_alu_imm_op {
+    ($name:ident) => {
+        paste! {
+            fn [<process_ $name i>](
+                &mut self,
+                dec_insn: insn_format::IType
+            ) -> Self::InstructionResult {
+                format!("{}i x{}, x{}, {}", stringify!($name), dec_insn.rd, dec_insn.rs1,
+                    dec_insn.imm)
+            }
+        }
+    };
+}
+
+macro_rules! string_out_for_alu_imm_shamt_op {
+    ($name:ident) => {
+        paste! {
+            fn [<process_ $name i>](
+                &mut self,
+                dec_insn: insn_format::ITypeShamt
+            ) -> Self::InstructionResult {
+                format!("{}i x{}, x{}, {}", stringify!($name), dec_insn.rd, dec_insn.rs1,
+                    dec_insn.shamt)
+            }
+        }
+    };
+}
+
+macro_rules! string_out_for_alu_ops {
+    ($($name:ident),*) => {
+        $(
+            string_out_for_alu_reg_op! {$name}
+            string_out_for_alu_imm_op! {$name}
+        )*
+    }
+}
+
+macro_rules! string_out_for_shift_ops {
+    ($($name:ident),*) => {
+        $(
+            string_out_for_alu_reg_op! {$name}
+            string_out_for_alu_imm_shamt_op! {$name}
+        )*
+    }
+}
+
+macro_rules! string_out_for_branch_ops {
+    ($($name:ident),*) => {
+        $(
+            paste! {
+                fn [<process_ $name>](
+                    &mut self,
+                    dec_insn: insn_format::BType
+                ) -> Self::InstructionResult {
+                    let branch_pc = self.insn_pc.wrapping_add(dec_insn.imm as u32);
+
+                    format!("{} x{}, x{}, 0x{:08x}", stringify!($name), dec_insn.rs1, dec_insn.rs2,
+                        branch_pc)
+                }
+            }
+        )*
+    }
+}
+
+macro_rules! string_out_for_load_ops {
+    ($($name:ident),*) => {
+        $(
+            paste! {
+                fn [<process_ $name>](
+                    &mut self,
+                    dec_insn: insn_format::IType
+                ) -> Self::InstructionResult {
+                    format!("{} x{}, {}(x{})", stringify!($name), dec_insn.rd, dec_insn.imm,
+                        dec_insn.rs1)
+                }
+            }
+        )*
+    }
+}
+
+macro_rules! string_out_for_store_ops {
+    ($($name:ident),*) => {
+        $(
+            paste! {
+                fn [<process_ $name>](
+                    &mut self,
+                    dec_insn: insn_format::SType
+                ) -> Self::InstructionResult {
+                    format!("{} x{}, {}(x{})", stringify!($name), dec_insn.rs2, dec_insn.imm,
+                        dec_insn.rs1)
+                }
+            }
+        )*
+    }
+}
+
+macro_rules! string_out_for_bn_alu_imm_op {
+    ($name:ident) => {
+        paste! {
+            fn [<process_bn_ $name i>](
+                &mut self,
+                dec_insn: insn_format::IType
+            ) -> Self::InstructionResult {
+                let imm = dec_insn.imm & 0x3ff;
+                let fg = (dec_insn.imm >> 11) & 0b1;
+                format!("{}i x{}, x{}, {}, FG{}", stringify!($name), dec_insn.rd, dec_insn.rs1,
+                        imm, fg)
+            }
+        }
+    };
+}
+
+macro_rules! string_out_for_csr_rr_op {
+    ($name:ident) => {
+        paste! {
+            fn [<process_ $name>](
+                &mut self,
+                dec_insn: insn_format::ITypeCSR
+            ) -> Self::InstructionResult {
+                format!("{} x{}, {}, x{}", stringify!($name), dec_insn.rd,
+                    csrs::CSRAddr::string_name(dec_insn.csr),
+                    dec_insn.rs1)
+            }
+        }
+    };
+}
+
+macro_rules! string_out_for_csr_ops {
+    ($($name:ident),*) => {
+        $(
+            string_out_for_csr_rr_op! {$name}
+        )*
+    };
+}
+
+// Macros to produce string outputs for various different BN instruction types
+macro_rules! string_out_for_alu_reg_bn_op {
+    ($name:ident) => {
+        paste! {
+            fn [<process_bn_ $name>](
+                &mut self,
+                dec_insn: insn_format::RType
+            ) -> Self::InstructionResult {
+                let sb_val = (dec_insn.funct7 & 0b0011111) << 3;
+                let sb = if sb_val != 0 {
+                    let st = if dec_insn.funct7 & 0b010_0000 != 0 {
+                        ">>"
+                    } else {
+                        "<<"
+                    };
+                    format!(" {} {}", st, sb_val)
+                } else {
+                    "".to_owned()
+                };
+                let fg = (dec_insn.funct7 >> 6) & 0b1;
+                format!("bn.{} w{}, w{}, w{}{}, FG{}", stringify!($name), dec_insn.rd, dec_insn.rs1,
+                        dec_insn.rs2, sb, fg)
+            }
+        }
+    };
+}
+
+// Macros to produce string outputs for various different BN instruction types
+macro_rules! string_out_for_alu_reg_bn_mod_op {
+    ($name:ident) => {
+        paste! {
+            fn [<process_bn_ $name m>](
+                &mut self,
+                dec_insn: insn_format::RType
+            ) -> Self::InstructionResult {
+                format!("bn.{}m w{}, w{}, w{}", stringify!($name), dec_insn.rd, dec_insn.rs1,
+                        dec_insn.rs2)
+            }
+        }
+    };
+}
+
+macro_rules! string_out_for_alu_reg_bn_cmp_op {
+    ($name:ident) => {
+        paste! {
+            fn [<process_bn_ $name>](
+                &mut self,
+                dec_insn: insn_format::RType
+            ) -> Self::InstructionResult {
+                let sb_val = (dec_insn.funct7 & 0b0011111) << 3;
+                let sb = if sb_val != 0 {
+                    let st = if dec_insn.funct7 & 0b010_0000 != 0 {
+                        ">>"
+                    } else {
+                        "<<"
+                    };
+                    format!(" {} {}", st, sb_val)
+                } else {
+                    "".to_owned()
+                };
+                let fg = (dec_insn.funct7 >> 6) & 0b1;
+                format!("bn.{} w{}, w{}{}, FG{}", stringify!($name),
+                        dec_insn.rs1, dec_insn.rs2, sb, fg)
+            }
+        }
+    };
+}
+
+macro_rules! string_out_for_alu_reg_bn_ops {
+    ($($name:ident),*) => {
+        $(
+            string_out_for_alu_reg_bn_op! {$name}
+        )*
+    };
+}
+
+macro_rules! string_out_for_alu_reg_bn_mod_ops {
+    ($($name:ident),*) => {
+        $(
+            string_out_for_alu_reg_bn_mod_op! {$name}
+        )*
+    };
+}
+
+macro_rules! string_out_for_alu_reg_bn_cmp_ops {
+    ($($name:ident),*) => {
+        $(
+            string_out_for_alu_reg_bn_cmp_op! {$name}
+        )*
+    };
+}
+
+impl insn_proc::InstructionProcessor for InstructionStringOutputter {
+    type InstructionResult = String;
+
+    // TODO: Make one macro that takes all names as arguments and generates all the functions
+    // together
+    string_out_for_alu_ops! {add, xor, or, and}
+    string_out_for_alu_reg_op! {sub}
+    string_out_for_shift_ops! {sll, srl, sra}
+
+    fn process_lui(&mut self, dec_insn: insn_format::UType) -> Self::InstructionResult {
+        format!("lui x{}, 0x{:08x}", dec_insn.rd, dec_insn.imm)
+    }
+
+    string_out_for_branch_ops! {beq, bne}
+    string_out_for_load_ops! {lw}
+    string_out_for_store_ops! {sw}
+
+    string_out_for_bn_alu_imm_op! {add}
+    string_out_for_bn_alu_imm_op! {sub}
+
+    fn process_jal(&mut self, dec_insn: insn_format::JType) -> Self::InstructionResult {
+        let target_pc = self.insn_pc.wrapping_add(dec_insn.imm as u32);
+        format!("jal x{}, 0x{:08x}", dec_insn.rd, target_pc)
+    }
+
+    fn process_jalr(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        format!(
+            "jalr x{}, 0x{:03x}(x{})",
+            dec_insn.rd, dec_insn.imm, dec_insn.rs1
+        )
+    }
+
+    string_out_for_csr_ops! {csrrs}
+
+    fn process_csrrw(&mut self, dec_insn: insn_format::ITypeCSR) -> Self::InstructionResult {
+        format!(
+            "csrrw x{}, {}, x{}",
+            dec_insn.rd,
+            csrs::CSRAddr::string_name(dec_insn.csr),
+            dec_insn.rs1
+        )
+    }
+
+    fn process_ecall(&mut self) -> Self::InstructionResult {
+        String::from("ecall")
+    }
+
+    fn process_loop(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        format!("loop x{}, {}", dec_insn.rs1, dec_insn.imm + 1)
+    }
+
+    fn process_loopi(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        format!(
+            "loopi {}, {}",
+            (dec_insn.rs1 << 5) | dec_insn.rd,
+            dec_insn.imm + 1
+        )
+    }
+
+    fn process_bn_lid(&mut self, dec_insn: insn_format::WidType) -> Self::InstructionResult {
+        let grs1 = dec_insn.rs1;
+        let grd = dec_insn.rs2;
+        let offset = dec_insn.imm << 5;
+
+        let grs1_inc = if (dec_insn.inc & 0b10) != 0 { "++" } else { "" };
+        let grd_inc = if (dec_insn.inc & 0b01) != 0 { "++" } else { "" };
+
+        format!(
+            "bn.lid x{}{}, {}(x{}{})",
+            grd, grd_inc, offset, grs1, grs1_inc
+        )
+    }
+
+    fn process_bn_sid(&mut self, dec_insn: insn_format::WidType) -> Self::InstructionResult {
+        let grs1 = dec_insn.rs1;
+        let grs2 = dec_insn.rs2;
+        let offset = dec_insn.imm << 5;
+
+        let grs1_inc = if (dec_insn.inc & 0b10) != 0 { "++" } else { "" };
+        let grs2_inc = if (dec_insn.inc & 0b01) != 0 { "++" } else { "" };
+
+        format!(
+            "bn.sid x{}{}, {}(x{}{})",
+            grs2, grs2_inc, offset, grs1, grs1_inc
+        )
+    }
+
+    fn process_bn_sel(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let fg = (dec_insn.funct7 >> 6) & 0b1;
+        let selbit = 1 << (dec_insn.funct7 & 0x3);
+        let flag = match insn_proc::Flags::from_bits_truncate(selbit as u8) {
+            insn_proc::Flags::CARRY => "C",
+            insn_proc::Flags::MSB => "M",
+            insn_proc::Flags::LSB => "L",
+            insn_proc::Flags::ZERO => "Z",
+            _ => "", // never happens. Is there a better way to handle this?
+        };
+        format!(
+            "bn.sel w{}, w{}, w{}, FG{}.{}",
+            dec_insn.rd, dec_insn.rs1, dec_insn.rs2, fg, flag
+        )
+    }
+
+    string_out_for_alu_reg_bn_cmp_ops! {cmp, cmpb}
+
+    fn process_bn_mov(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        format!("bn.mov w{}, w{}", dec_insn.rd, dec_insn.rs1)
+    }
+
+    fn process_bn_movr(&mut self, dec_insn: insn_format::SType) -> Self::InstructionResult {
+        let grd_inc = if dec_insn.imm & 0b0001 != 0 { "++" } else { "" };
+        let grs_inc = if dec_insn.imm & 0b0100 != 0 { "++" } else { "" };
+
+        format!(
+            "bn.movr x{}{}, x{}{}",
+            dec_insn.rs2, grd_inc, dec_insn.rs1, grs_inc
+        )
+    }
+
+    fn process_bn_wsrr(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        let wsr = dec_insn.imm & 0xff;
+
+        format!("bn.wsrr {}, {}", dec_insn.rd, wsr)
+    }
+
+    fn process_bn_wsrw(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        let wsr = dec_insn.imm & 0xff;
+
+        format!("bn.wsrw {}, {}", wsr, dec_insn.rs1)
+    }
+
+    fn process_bn_mulqacc(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let zero_acc = if dec_insn.funct3 & 0b001 != 0 {
+            ".z"
+        } else {
+            ""
+        };
+        let acc_shift = 64 * (dec_insn.funct3 >> 1);
+        let qwsel1 = dec_insn.funct7 & 0b11;
+        let qwsel2 = dec_insn.funct7 >> 2 & 0b11;
+
+        format!(
+            "bn.mulqacc{} w{}.{}, w{}.{}, {}",
+            zero_acc, dec_insn.rs1, qwsel1, dec_insn.rs2, qwsel2, acc_shift
+        )
+    }
+
+    fn process_bn_mulqacc_wo(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let zero_acc = if dec_insn.funct3 & 0b001 != 0 {
+            ".z"
+        } else {
+            ""
+        };
+        let acc_shift = 64 * (dec_insn.funct3 >> 1);
+        let fg = (dec_insn.funct7 >> 6) & 0b1;
+        let qwsel1 = dec_insn.funct7 & 0b11;
+        let qwsel2 = dec_insn.funct7 >> 2 & 0b11;
+
+        format!(
+            "bn.mulqacc.wo{} w{}, w{}.{}, w{}.{}, {} FG{}",
+            zero_acc, dec_insn.rd, dec_insn.rs1, qwsel1, dec_insn.rs2, qwsel2, acc_shift, fg
+        )
+    }
+
+    fn process_bn_mulqacc_so(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let zero_acc = if dec_insn.funct3 & 0b001 != 0 {
+            ".z"
+        } else {
+            ""
+        };
+        let acc_shift = 64 * (dec_insn.funct3 >> 1);
+        let fg = (dec_insn.funct7 >> 6) & 0b1;
+        let qwsel1 = dec_insn.funct7 & 0b11;
+        let qwsel2 = dec_insn.funct7 >> 2 & 0b11;
+        let hwsel = if dec_insn.funct7 & 0b001_0000 != 0 {
+            "u"
+        } else {
+            "l"
+        };
+
+        format!(
+            "bn.mulqacc.so{} w{}.{}, w{}.{}, w{}.{}, {} FG{}",
+            zero_acc, dec_insn.rd, hwsel, dec_insn.rs1, qwsel1, dec_insn.rs2, qwsel2, acc_shift, fg
+        )
+    }
+
+    string_out_for_alu_reg_bn_ops! {and, or, xor, add, addc, sub, subb}
+    string_out_for_alu_reg_bn_mod_ops! {add, sub}
+
+    fn process_bn_not(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let sb_val = (dec_insn.funct7 & 0b0011111) << 3;
+        let sb = if sb_val != 0 {
+            let st = if dec_insn.funct7 & 0b010_0000 != 0 {
+                ">>"
+            } else {
+                "<<"
+            };
+            format!(" {} {}", st, sb_val)
+        } else {
+            "".to_owned()
+        };
+        let fg = (dec_insn.funct7 >> 6) & 0b1;
+        format!("bn.not w{}, w{}{} FG{}", dec_insn.rd, dec_insn.rs2, sb, fg)
+    }
+
+    fn process_bn_rshi(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let imm = (dec_insn.funct7 << 1) | (dec_insn.funct3 >> 2);
+        let shimm = if imm != 0 {
+            format!(" >> {}", imm)
+        } else {
+            "".to_owned()
+        };
+
+        format!(
+            "bn.rshi w{}, w{}, w{}{}",
+            dec_insn.rd, dec_insn.rs1, dec_insn.rs2, shimm
+        )
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/insn_exec.rs b/hw/opentitan/otbn/otbn/src/insn_exec.rs
new file mode 100644
index 0000000000000..661f1dbb5ba74
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/insn_exec.rs
@@ -0,0 +1,1316 @@
+// Copyright 2021 Gregory Chadwick <mail@gregchadwick.co.uk>
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use std::convert::TryInto;
+use std::fmt;
+use std::mem::size_of;
+use std::sync::{Arc, Mutex};
+
+use ethnum::{u256, AsU256, U256};
+use paste::paste;
+
+use super::csrs;
+use super::insn_decode;
+use super::insn_format;
+use super::insn_proc;
+use super::key;
+use super::random;
+use super::Memory;
+use crate::{ExceptionCause, PRNG};
+
+/// OTBN wide register width
+const WLEN: usize = size_of::<U256>() * 8;
+
+/// Different traps that can occur during instruction execution
+#[derive(Debug, PartialEq, Eq)]
+pub enum InstructionTrap {
+    /// Trap is a synchronous exception, with a particular cause.
+    Exception(ExceptionCause, Option<u32>),
+}
+
+/// HW loop tuple
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub struct Loop {
+    /// remaining loop to execute
+    pub count: u32,
+    /// absolute start address of the loop
+    pub start: u32,
+    /// absolute end address of the loop
+    pub end: u32,
+}
+
+impl fmt::Debug for Loop {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_struct("Loop")
+            .field("count", &self.count)
+            .field("start", &format_args!("0x{:04x}", self.start))
+            .field("end", &format_args!("0x{:04x}", self.end))
+            .finish()
+    }
+}
+
+/// Track updated hart state, for debugging purpose only
+#[derive(Default)]
+pub struct StateTracker {
+    pub gpr: Option<usize>,             // GPR, if any
+    pub wgpr: Option<usize>,            // wide GPR, if any
+    pub csr: Option<(bool, u32)>,       // CSR/WCSR if any
+    pub loophead: Option<(usize, u32)>, // head of loopstack
+}
+
+impl StateTracker {
+    fn clear(&mut self) {
+        self.gpr = None;
+        self.wgpr = None;
+        self.csr = None;
+        self.loophead = None;
+    }
+}
+
+/// State of a single OTBN hart
+pub struct HartState {
+    /// x1 - x31 register values. The contents of index 0 (the x0 zero register) are ignored.
+    pub registers: [u32; 32],
+    /// w0 - w31 wide register values
+    pub wregisters: [u256; 32],
+    /// Program counter
+    pub pc: u32,
+    /// 8-loop deep HW loop stack for use with loop/loopi instructions
+    pub loopstack: Vec<Loop>,
+    /// 8-address deep HW stack for use with x1 GPR
+    pub hwstack: Vec<u32>,
+    /// Special resisters (narrow and wide)
+    pub csr_set: csrs::CSRSet,
+    /// Track state changes (debug)
+    pub updated: StateTracker,
+}
+
+impl HartState {
+    pub fn new(urnd: Arc<Mutex<dyn PRNG>>, rnd: Arc<random::Rnd>, key: Arc<key::Key>) -> Self {
+        HartState {
+            registers: [0; 32],
+            wregisters: [0.as_u256(); 32],
+            pc: 0,
+            loopstack: Vec::with_capacity(8),
+            hwstack: Vec::with_capacity(8),
+            updated: StateTracker::default(),
+            csr_set: csrs::CSRSet::new(urnd, rnd, key),
+        }
+    }
+
+    /// Write a register in the hart state. Used by executing instructions for correct zero
+    /// register handling
+    fn write_register(&mut self, reg_index: usize, data: u32) -> Result<(), InstructionTrap> {
+        if reg_index == 0 {
+            return Ok(());
+        }
+        if reg_index == 1 {
+            if self.hwstack.len() >= self.hwstack.capacity() {
+                return Err(InstructionTrap::Exception(ExceptionCause::ECallStack, None));
+            }
+            self.hwstack.push(data);
+        }
+
+        self.registers[reg_index] = data;
+        self.updated.gpr = Some(reg_index);
+        Ok(())
+    }
+
+    /// Read a register from the hart state. Used by executing instructions for correct zero
+    /// register handling
+    fn read_register(&mut self, reg_index: usize) -> Result<u32, InstructionTrap> {
+        if reg_index == 0 {
+            Ok(0)
+        } else if reg_index == 1 {
+            match self.hwstack.pop() {
+                Some(x) => {
+                    self.registers[reg_index] = x;
+                    Ok(x)
+                }
+                None => Err(InstructionTrap::Exception(ExceptionCause::ECallStack, None)),
+            }
+        } else {
+            Ok(self.registers[reg_index])
+        }
+    }
+
+    /// Write a register in the hart state. Used by executing instructions for correct zero
+    /// register handling
+    fn write_wide_register(&mut self, reg_index: usize, data: u256) -> Result<(), InstructionTrap> {
+        self.wregisters[reg_index] = data;
+        self.updated.wgpr = Some(reg_index);
+        Ok(())
+    }
+
+    /// Read a register from the hart state. Used by executing instructions for correct zero
+    /// register handling
+    fn read_wide_register(&mut self, reg_index: usize) -> Result<u256, InstructionTrap> {
+        Ok(self.wregisters[reg_index])
+    }
+
+    fn write_csr(&mut self, csr_addr: u32, data: u32) -> Result<(), InstructionTrap> {
+        let csr = self
+            .csr_set
+            .get_csr_mut(csr_addr)
+            .ok_or(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                Some(csr_addr),
+            ))?;
+
+        if let Err(exc) = csr.write(data) {
+            return Err(InstructionTrap::Exception(exc, Some(csr_addr)));
+        }
+        self.updated.csr = Some((false, csr_addr));
+        Ok(())
+    }
+
+    fn read_csr(&mut self, csr_addr: u32) -> Result<u32, InstructionTrap> {
+        let csr = self
+            .csr_set
+            .get_csr(csr_addr)
+            .ok_or(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                Some(csr_addr),
+            ))?;
+
+        csr.read()
+            .map_err(|exc| InstructionTrap::Exception(exc, Some(csr_addr)))
+    }
+
+    fn write_wsr(&mut self, wsr_addr: u32, data: u256) -> Result<(), InstructionTrap> {
+        let wsr = self
+            .csr_set
+            .get_wsr_mut(wsr_addr)
+            .ok_or(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                Some(wsr_addr),
+            ))?;
+
+        if let Err(exc) = wsr.write(data) {
+            return Err(InstructionTrap::Exception(exc, Some(wsr_addr)));
+        }
+        self.updated.csr = Some((true, wsr_addr));
+        Ok(())
+    }
+
+    fn read_wsr(&mut self, wsr_addr: u32) -> Result<u256, InstructionTrap> {
+        let wsr = self
+            .csr_set
+            .get_wsr(wsr_addr)
+            .ok_or(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                Some(wsr_addr),
+            ))?;
+
+        wsr.read()
+            .map_err(|exc| InstructionTrap::Exception(exc, Some(wsr_addr)))
+    }
+
+    fn set_mlz_wide_flags(&mut self, fg: usize, carry: bool, value: u256) {
+        let mut flags = if carry {
+            insn_proc::Flags::CARRY
+        } else {
+            insn_proc::Flags::default()
+        };
+        if (value >> 255u32).as_u32() != 0 {
+            flags |= insn_proc::Flags::MSB;
+        }
+        if (value & U256::from(1u32)) != 0 {
+            flags |= insn_proc::Flags::LSB;
+        }
+        if value == 0 {
+            flags |= insn_proc::Flags::ZERO;
+        }
+        self.csr_set.set_flags(fg, flags);
+    }
+
+    fn update_mlz_wide_flags(&mut self, fg: usize, value: u256) {
+        let mut flags = self.csr_set.get_flags(fg) & insn_proc::Flags::CARRY;
+        if (value >> 255u32).as_u32() != 0 {
+            flags |= insn_proc::Flags::MSB;
+        }
+        if (value & U256::from(1u32)) != 0 {
+            flags |= insn_proc::Flags::LSB;
+        }
+        if value == 0 {
+            flags |= insn_proc::Flags::ZERO;
+        }
+        self.csr_set.set_flags(fg, flags);
+    }
+
+    pub fn wipe_internal(&mut self, prng: &Arc<Mutex<dyn PRNG>>) {
+        {
+            let mut prng = prng.lock().unwrap();
+
+            // GPRs and WDRs
+            for reg in self.registers.iter_mut() {
+                *reg = prng.get_prng_u32();
+            }
+            for reg in self.wregisters.iter_mut() {
+                *reg = prng.get_prng_u256();
+            }
+        }
+
+        // Accumulator
+        // Flags
+        // Modulus
+        self.csr_set.wipe_internal(prng);
+
+        self.loopstack.clear();
+        self.hwstack.clear();
+        self.updated.clear();
+    }
+
+    pub fn set_test_mode(&mut self, enable: bool) {
+        self.csr_set.set_test_mode(enable)
+    }
+}
+
+/// An `InstructionProcessor` that execute instructions, updating `hart_state` as appropriate.
+pub struct InstructionExecutor<'a, M: Memory> {
+    /// Instruction memory used by fetch instructions
+    pub imem: &'a mut M,
+    /// Data memory used by load and store instructions
+    pub dmem: &'a mut M,
+    pub hart_state: &'a mut HartState,
+}
+
+impl<'a, M: Memory> InstructionExecutor<'a, M> {
+    fn execute_reg_reg_op<F>(
+        &mut self,
+        dec_insn: insn_format::RType,
+        op: F,
+    ) -> Result<(), InstructionTrap>
+    where
+        F: Fn(u32, u32) -> u32,
+    {
+        let a = self.hart_state.read_register(dec_insn.rs1)?;
+        let b = self.hart_state.read_register(dec_insn.rs2)?;
+        let result = op(a, b);
+        self.hart_state.write_register(dec_insn.rd, result)
+    }
+
+    fn execute_reg_imm_op<F>(
+        &mut self,
+        dec_insn: insn_format::IType,
+        op: F,
+    ) -> Result<(), InstructionTrap>
+    where
+        F: Fn(u32, u32) -> u32,
+    {
+        let a = self.hart_state.read_register(dec_insn.rs1)?;
+        let b = dec_insn.imm as u32;
+        let result = op(a, b);
+        self.hart_state.write_register(dec_insn.rd, result)
+    }
+
+    fn execute_reg_imm_shamt_op<F>(
+        &mut self,
+        dec_insn: insn_format::ITypeShamt,
+        op: F,
+    ) -> Result<(), InstructionTrap>
+    where
+        F: Fn(u32, u32) -> u32,
+    {
+        let a = self.hart_state.read_register(dec_insn.rs1)?;
+        let result = op(a, dec_insn.shamt);
+        self.hart_state.write_register(dec_insn.rd, result)
+    }
+
+    fn execute_reg_imm_bn_op<F>(
+        &mut self,
+        dec_insn: insn_format::IType,
+        op: F,
+    ) -> Result<(), InstructionTrap>
+    where
+        F: Fn(u256, u256) -> (u256, bool),
+    {
+        let a = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b = dec_insn.imm as u32 & 0x3ff;
+        let fg = ((dec_insn.imm >> 11) & 0b1) as usize;
+        let (res, carry) = op(a, U256::from(b));
+        self.hart_state.write_wide_register(dec_insn.rd, res)?;
+        self.hart_state.set_mlz_wide_flags(fg, carry, res);
+        Ok(())
+    }
+
+    fn execute_reg_reg_bn_op<F>(
+        &mut self,
+        dec_insn: insn_format::RType,
+        op: F,
+    ) -> Result<(), InstructionTrap>
+    where
+        F: Fn(u256, u256) -> u256,
+    {
+        let a = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b = self.hart_state.read_wide_register(dec_insn.rs2)?;
+        let st = dec_insn.funct7 & 0b010_0000 != 0;
+        let sbits = (dec_insn.funct7 & 0b001_1111) << 3;
+        let fg = ((dec_insn.funct7 >> 6) & 0b1) as usize;
+
+        let b = if st {
+            b.wrapping_shr(sbits)
+        } else {
+            b.wrapping_shl(sbits)
+        };
+
+        let res = op(a, b);
+
+        self.hart_state.write_wide_register(dec_insn.rd, res)?;
+        self.hart_state.update_mlz_wide_flags(fg, res);
+
+        Ok(())
+    }
+
+    fn execute_reg_reg_bn_of_op<F>(
+        &mut self,
+        dec_insn: insn_format::RType,
+        op: F,
+        bc: bool,
+    ) -> Result<(), InstructionTrap>
+    where
+        F: Fn(u256, u256) -> (u256, bool),
+    {
+        let mut a = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b = self.hart_state.read_wide_register(dec_insn.rs2)?;
+        let st = dec_insn.funct7 & 0b010_0000 != 0;
+        let sbits = (dec_insn.funct7 & 0b001_1111) << 3;
+        let fg = ((dec_insn.funct7 >> 6) & 0b1) as usize;
+        let b = if st {
+            b.wrapping_shr(sbits)
+        } else {
+            b.wrapping_shl(sbits)
+        };
+
+        // TBC: not sure if carry implementation works for all op
+        let mut carry = false;
+        if bc {
+            let flags = self.hart_state.csr_set.get_flags(fg);
+            if !(flags & insn_proc::Flags::CARRY).is_empty() {
+                (a, carry) = op(a, U256::from(1u32));
+            }
+        }
+        let (res, carry2) = op(a, b);
+        carry |= carry2;
+        self.hart_state.write_wide_register(dec_insn.rd, res)?;
+        self.hart_state.set_mlz_wide_flags(fg, carry, res);
+        Ok(())
+    }
+
+    fn execute_csr_op<F>(
+        &mut self,
+        dec_insn: insn_format::ITypeCSR,
+        use_imm: bool,
+        op: F,
+    ) -> Result<(), InstructionTrap>
+    where
+        F: Fn(u32, u32) -> u32,
+    {
+        let old_csr = self.hart_state.read_csr(dec_insn.csr)?;
+
+        let a = if use_imm {
+            dec_insn.rs1 as u32
+        } else {
+            self.hart_state.read_register(dec_insn.rs1)?
+        };
+
+        let new_csr = op(old_csr, a);
+
+        self.hart_state.write_csr(dec_insn.csr, new_csr)?;
+
+        self.hart_state.write_register(dec_insn.rd, old_csr)
+    }
+
+    // Returns true if branch succeeds
+    fn execute_branch<F>(
+        &mut self,
+        dec_insn: insn_format::BType,
+        cond: F,
+    ) -> Result<bool, InstructionTrap>
+    where
+        F: Fn(u32, u32) -> bool,
+    {
+        let a = self.hart_state.read_register(dec_insn.rs1)?;
+        let b = self.hart_state.read_register(dec_insn.rs2)?;
+
+        let lstack = &self.hart_state.loopstack;
+        if let Some(hwloop) = lstack.last() {
+            if self.hart_state.pc == hwloop.end {
+                return Err(InstructionTrap::Exception(ExceptionCause::ELoop, None));
+            }
+        }
+        if cond(a, b) {
+            let new_pc = self.hart_state.pc.wrapping_add(dec_insn.imm as u32);
+            self.hart_state.pc = new_pc;
+            Ok(true)
+        } else {
+            Ok(false)
+        }
+    }
+
+    fn execute_load(
+        &mut self,
+        dec_insn: insn_format::IType,
+        signed: bool,
+    ) -> Result<(), InstructionTrap> {
+        let addr = self
+            .hart_state
+            .read_register(dec_insn.rs1)?
+            .wrapping_add(dec_insn.imm as u32);
+
+        if (addr & 0x03) != 0 {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EBadDataAddr,
+                Some(addr),
+            ));
+        }
+
+        // Attempt to read data from memory, returning a LoadAccessFault as an error if it is not.
+        let mut load_data = match self.dmem.read_mem(addr) {
+            Some(d) => d,
+            None => {
+                return Err(InstructionTrap::Exception(
+                    ExceptionCause::EBadDataAddr,
+                    Some(addr),
+                ));
+            }
+        };
+
+        // Sign extend loaded data if required
+        if signed {
+            load_data = (load_data as i32) as u32;
+        }
+
+        // Write load data to destination register
+        self.hart_state.write_register(dec_insn.rd, load_data)
+    }
+
+    fn execute_store(&mut self, dec_insn: insn_format::SType) -> Result<(), InstructionTrap> {
+        let addr = self
+            .hart_state
+            .read_register(dec_insn.rs1)?
+            .wrapping_add(dec_insn.imm as u32);
+        let data = self.hart_state.read_register(dec_insn.rs2)?;
+
+        // Determine if address is aligned to size
+        if (addr & 0x3) != 0x0 {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EBadDataAddr,
+                Some(addr),
+            ));
+        }
+
+        // Write store data to memory
+        if self.dmem.write_mem(addr, data) {
+            Ok(())
+        } else {
+            Err(InstructionTrap::Exception(
+                ExceptionCause::EBadDataAddr,
+                Some(addr),
+            ))
+        }
+    }
+
+    pub fn wipe_internal(&mut self, prng: &Arc<Mutex<dyn PRNG>>) {
+        // "If OTBN cannot complete a secure wipe of the internal state (e.g., due to failing to
+        // obtain the required randomness), it immediately becomes locked."
+        // for now, wiping emulation does not involve random source, but this may be added if
+        // a remote random source gets implemented. @todo
+        self.hart_state.wipe_internal(prng);
+    }
+
+    pub fn reset(&mut self) {
+        self.hart_state.pc = 0;
+    }
+
+    /// Execute instruction pointed to by `hart_state.pc`
+    ///
+    /// Returns `Ok` where instruction execution was successful. `Err` with the relevant
+    /// [InstructionTrap] is returned when the instruction execution causes a trap.
+    pub fn step(&mut self) -> Result<(), InstructionTrap> {
+        self.hart_state.updated.clear();
+
+        if let Some(next_insn) = self.imem.read_mem(self.hart_state.pc) {
+            // Fetch next instruction from memory and eecute the instruction if fetch was
+            // successful
+            let step_result = insn_decode::decoder(self, next_insn);
+
+            match step_result {
+                Some(Ok(pc_updated)) => {
+                    if !pc_updated {
+                        let lstack = &mut self.hart_state.loopstack;
+                        let loopdepth = lstack.len();
+                        let loop_to = match lstack.last_mut() {
+                            Some(hwloop) => {
+                                if hwloop.end == self.hart_state.pc {
+                                    // one less iteration to go
+                                    hwloop.count -= 1;
+                                    self.hart_state.updated.loophead =
+                                        Some((loopdepth, hwloop.count));
+                                    if hwloop.count == 0 {
+                                        // loop exhausted, should be removed
+                                        lstack.pop();
+                                        // resume after the last loop instruction
+                                        None
+                                    } else {
+                                        // restart from the first instruction of the loop
+                                        Some(hwloop.start)
+                                    }
+                                } else {
+                                    // current PC is not the last instruction of the loop
+                                    None
+                                }
+                            }
+                            // no HW loop is active
+                            _ => None,
+                        };
+                        self.hart_state.pc = match loop_to {
+                            Some(pc) => pc,
+                            _ => self.hart_state.pc + 4,
+                        };
+                    }
+                    Ok(())
+                }
+                // Instruction produced an illegal instruction error or decode failed so return an
+                // IllegalInstruction as an error, supplying instruction bits
+                Some(Err(InstructionTrap::Exception(ExceptionCause::EIllegalInsn, _))) | None => {
+                    Err(InstructionTrap::Exception(
+                        ExceptionCause::EIllegalInsn,
+                        Some(next_insn),
+                    ))
+                }
+                // Instruction produced an error so return it
+                Some(Err(e)) => Err(e),
+            }
+        } else {
+            // FetchError
+            Err(InstructionTrap::Exception(
+                ExceptionCause::EBadInsnAddr,
+                Some(self.hart_state.pc),
+            ))
+        }
+    }
+}
+
+// Macros to implement various repeated operations (e.g. ALU reg op reg instructions).
+macro_rules! make_alu_op_reg_fn {
+    ($name:ident, $op_fn:expr) => {
+        paste! {
+            fn [<process_ $name>](
+                &mut self,
+                dec_insn: insn_format::RType
+            ) -> Self::InstructionResult {
+                self.execute_reg_reg_op(dec_insn, $op_fn)?;
+                Ok(false)
+            }
+        }
+    };
+}
+
+// Macros to implement various repeated operations (on wide registers).
+macro_rules! make_alu_bn_op_reg_fn {
+    ($name:ident, $op_fn:expr) => {
+        paste! {
+            fn [<process_bn_ $name>](
+                &mut self,
+                dec_insn: insn_format::RType
+            ) -> Self::InstructionResult {
+                self.execute_reg_reg_bn_op(dec_insn, $op_fn)?;
+                Ok(false)
+            }
+        }
+    };
+}
+
+macro_rules! make_alu_bn_of_op_reg_fn {
+    ($name:ident, $op_fn:expr, $bc:expr) => {
+        paste! {
+            fn [<process_bn_ $name>](
+                &mut self,
+                dec_insn: insn_format::RType
+            ) -> Self::InstructionResult {
+                self.execute_reg_reg_bn_of_op(dec_insn, $op_fn, $bc)?;
+                Ok(false)
+            }
+        }
+    };
+}
+
+macro_rules! make_alu_op_imm_fn {
+    ($name:ident, $op_fn:expr) => {
+        paste! {
+            fn [<process_ $name i>](
+                &mut self,
+                dec_insn: insn_format::IType
+            ) -> Self::InstructionResult {
+                self.execute_reg_imm_op(dec_insn, $op_fn)?;
+                Ok(false)
+            }
+        }
+    };
+}
+
+macro_rules! make_alu_op_imm_shamt_fn {
+    ($name:ident, $op_fn:expr) => {
+        paste! {
+            fn [<process_ $name i>](
+                &mut self,
+                dec_insn: insn_format::ITypeShamt
+            ) -> Self::InstructionResult {
+                self.execute_reg_imm_shamt_op(dec_insn, $op_fn)?;
+                Ok(false)
+            }
+        }
+    };
+}
+
+macro_rules! make_alu_op_fns {
+    ($name:ident, $op_fn:expr) => {
+        make_alu_op_reg_fn! {$name, $op_fn}
+        make_alu_op_imm_fn! {$name, $op_fn}
+    };
+}
+
+macro_rules! make_shift_op_fns {
+    ($name:ident, $op_fn:expr) => {
+        make_alu_op_reg_fn! {$name, $op_fn}
+        make_alu_op_imm_shamt_fn! {$name, $op_fn}
+    };
+}
+
+macro_rules! make_branch_op_fn {
+    ($name:ident, $cond_fn:expr) => {
+        paste! {
+            fn [<process_ $name>](
+                &mut self,
+                dec_insn: insn_format::BType
+            ) -> Self::InstructionResult {
+                self.execute_branch(dec_insn, $cond_fn)
+            }
+        }
+    };
+}
+
+macro_rules! make_load_op_fn_inner {
+    ($name:ident, $signed: expr) => {
+        paste! {
+            fn [<process_ $name>](
+                &mut self,
+                dec_insn: insn_format::IType
+            ) -> Self::InstructionResult {
+                self.execute_load(dec_insn, $signed)?;
+                Ok(false)
+            }
+        }
+    };
+}
+
+macro_rules! make_load_op_fn {
+    ($name:ident, signed) => {
+        make_load_op_fn_inner! {$name, true}
+    };
+    ($name:ident, unsigned) => {
+        make_load_op_fn_inner! {$name, false}
+    };
+}
+
+macro_rules! make_store_op_fn {
+    ($name:ident) => {
+        paste! {
+            fn [<process_ $name>](
+                &mut self,
+                dec_insn: insn_format::SType
+            ) -> Self::InstructionResult {
+                self.execute_store(dec_insn)?;
+                Ok(false)
+            }
+        }
+    };
+}
+
+macro_rules! make_alu_bn_op_imm_fn {
+    ($name:ident, $op_fn:expr) => {
+        paste! {
+            fn [<process_bn_ $name i>](
+                &mut self,
+                dec_insn: insn_format::IType
+            ) -> Self::InstructionResult {
+                self.execute_reg_imm_bn_op(dec_insn, $op_fn)?;
+                Ok(false)
+            }
+        }
+    };
+}
+
+macro_rules! make_csr_op_fns {
+    ($name:ident, $op_fn:expr) => {
+        paste! {
+            fn [<process_ $name>](
+                &mut self,
+                dec_insn: insn_format::ITypeCSR
+            ) -> Self::InstructionResult {
+                self.execute_csr_op(dec_insn, false, $op_fn)?;
+                Ok(false)
+            }
+        }
+    };
+}
+
+impl<'a, M: Memory> insn_proc::InstructionProcessor for InstructionExecutor<'a, M> {
+    /// Result is `Ok` when instruction execution is successful. `Ok(true) indicates the
+    /// instruction updated the PC and Ok(false) indicates it did not (so the PC must be
+    /// incremented to execute the next instruction).
+    type InstructionResult = Result<bool, InstructionTrap>;
+
+    make_alu_op_fns! {add, |a, b| a.wrapping_add(b)}
+    make_alu_op_reg_fn! {sub, |a, b| a.wrapping_sub(b)}
+    make_alu_op_fns! {or, |a, b| a | b}
+    make_alu_op_fns! {and, |a, b| a & b}
+    make_alu_op_fns! {xor, |a, b| a ^ b}
+
+    make_shift_op_fns! {sll, |a, b| a << (b & 0x1f)}
+    make_shift_op_fns! {srl, |a, b| a >> (b & 0x1f)}
+    make_shift_op_fns! {sra, |a, b| ((a as i32) >> (b & 0x1f)) as u32}
+
+    fn process_lui(&mut self, dec_insn: insn_format::UType) -> Self::InstructionResult {
+        self.hart_state
+            .write_register(dec_insn.rd, dec_insn.imm as u32)?;
+        Ok(false)
+    }
+
+    make_branch_op_fn! {beq, |a, b| a == b}
+    make_branch_op_fn! {bne, |a, b| a != b}
+
+    make_load_op_fn! {lw, unsigned}
+    make_store_op_fn! {sw}
+
+    fn process_jal(&mut self, dec_insn: insn_format::JType) -> Self::InstructionResult {
+        let target_pc = self.hart_state.pc.wrapping_add(dec_insn.imm as u32);
+        self.hart_state
+            .write_register(dec_insn.rd, self.hart_state.pc + 4)?;
+        self.hart_state.pc = target_pc;
+        Ok(true)
+    }
+
+    fn process_jalr(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        let target_pc = self
+            .hart_state
+            .read_register(dec_insn.rs1)?
+            .wrapping_add(dec_insn.imm as u32)
+            & !0b11;
+        self.hart_state
+            .write_register(dec_insn.rd, self.hart_state.pc + 4)?;
+        self.hart_state.pc = target_pc;
+        Ok(true)
+    }
+
+    make_csr_op_fns! {csrrw, |_old_csr, a| a}
+    make_csr_op_fns! {csrrs, |old_csr, a| old_csr | a}
+
+    fn process_ecall(&mut self) -> Self::InstructionResult {
+        Err(InstructionTrap::Exception(
+            ExceptionCause::ECallMMode,
+            Some(0),
+        ))
+    }
+
+    fn process_loop(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        let bodysize = dec_insn.imm as u32 + 1;
+        let hwloop = Loop {
+            count: self.hart_state.read_register(dec_insn.rs1)?,
+            start: self.hart_state.pc + 4, // next instruction
+            end: self.hart_state.pc + bodysize * 4,
+        };
+        if hwloop.count == 0 {
+            // to be handled properly
+            return Err(InstructionTrap::Exception(ExceptionCause::ELoop, None));
+        }
+        let lstack = &mut self.hart_state.loopstack;
+        if lstack.len() == lstack.capacity() {
+            return Err(InstructionTrap::Exception(ExceptionCause::ELoop, None));
+        }
+        if let Some(hwloop) = lstack.last() {
+            if self.hart_state.pc == hwloop.end {
+                return Err(InstructionTrap::Exception(ExceptionCause::ELoop, None));
+            }
+        }
+        // need to check this instruction is not a last instruction in an existing loop
+        lstack.push(hwloop);
+        self.hart_state.updated.loophead = Some((lstack.len(), hwloop.count));
+        Ok(false)
+    }
+
+    fn process_loopi(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        let bodysize = dec_insn.imm as u32 + 1;
+        let hwloop = Loop {
+            count: ((dec_insn.rs1 << 5) + dec_insn.rd) as u32,
+            start: self.hart_state.pc + 4, // next instruction
+            end: self.hart_state.pc + bodysize * 4,
+        };
+        if self.hart_state.loopstack.len() == self.hart_state.loopstack.capacity() {
+            // to be handled properly
+            return Err(InstructionTrap::Exception(ExceptionCause::ELoop, None));
+        }
+        if hwloop.count == 0 {
+            return Err(InstructionTrap::Exception(ExceptionCause::ELoop, None));
+        }
+        // need to check this instruction is not a last instruction in an existing loop
+        self.hart_state.loopstack.push(hwloop);
+        self.hart_state.updated.loophead = Some((self.hart_state.loopstack.len(), hwloop.count));
+        Ok(false)
+    }
+
+    fn process_bn_lid(&mut self, dec_insn: insn_format::WidType) -> Self::InstructionResult {
+        let grs1_inc = (dec_insn.inc & 0b10) != 0;
+        let grd_inc = (dec_insn.inc & 0b01) != 0;
+
+        if grs1_inc && grd_inc {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                None,
+            ));
+        }
+
+        // wide register index
+        let wri = self.hart_state.read_register(dec_insn.rs2)?;
+        if wri > 31 {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                None,
+            ));
+        }
+
+        let addr = self.hart_state.read_register(dec_insn.rs1)?;
+        if (addr as usize & (WLEN / 8 - 1)) != 0 {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EBadDataAddr,
+                Some(addr),
+            ));
+        }
+
+        let offset = dec_insn.imm << 5;
+
+        if (offset as usize & (WLEN / 8 - 1)) != 0 {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EBadDataAddr,
+                Some(offset as u32),
+            ));
+        }
+
+        // check is there is a less stupid way to do this...
+        let src = if offset >= 0 {
+            addr.wrapping_add(offset as u32)
+        } else {
+            addr.wrapping_sub(-offset as u32)
+        };
+
+        let mut bytes = [0; size_of::<U256>()];
+        const RSIZE: usize = size_of::<u32>();
+        for (pos, bchunk) in (0..bytes.len()).step_by(RSIZE).zip(bytes.chunks_mut(RSIZE)) {
+            let word = self.dmem.read_mem(src + pos as u32).unwrap();
+            bchunk.copy_from_slice(&word.to_le_bytes()[..]);
+        }
+        let wvalue = U256::from_le_bytes(bytes);
+
+        if grd_inc {
+            self.hart_state.write_register(dec_insn.rs2, wri + 1)?;
+        }
+
+        if grs1_inc {
+            let addr = addr.wrapping_add(size_of::<U256>() as u32);
+            self.hart_state.write_register(dec_insn.rs1, addr)?;
+        }
+
+        self.hart_state.write_wide_register(wri as usize, wvalue)?;
+
+        Ok(false)
+    }
+
+    fn process_bn_sid(&mut self, dec_insn: insn_format::WidType) -> Self::InstructionResult {
+        let grs1_inc = (dec_insn.inc & 0b10) != 0;
+        let grs2_inc = (dec_insn.inc & 0b01) != 0;
+
+        if grs1_inc && grs2_inc {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                None,
+            ));
+        }
+
+        // wide register index
+        let wri = self.hart_state.read_register(dec_insn.rs2)?;
+        if wri > 31 {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                None,
+            ));
+        }
+
+        let addr = self.hart_state.read_register(dec_insn.rs1)?;
+        if (addr as usize & (WLEN / 8 - 1)) != 0 {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EBadDataAddr,
+                Some(addr),
+            ));
+        }
+
+        let offset = dec_insn.imm << 5;
+
+        if (offset as usize & (WLEN / 8 - 1)) != 0 {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EBadDataAddr,
+                Some(offset as u32),
+            ));
+        }
+
+        // check is there is a less stupid way to do this...
+        let dst = if offset >= 0 {
+            addr.wrapping_add(offset as u32)
+        } else {
+            addr.wrapping_sub(-offset as u32)
+        };
+
+        if grs1_inc {
+            let addr = addr.wrapping_add(size_of::<U256>() as u32);
+            self.hart_state.write_register(dec_insn.rs1, addr)?;
+        }
+
+        if grs2_inc {
+            self.hart_state.write_register(dec_insn.rs2, wri + 1)?;
+        }
+
+        let wvalue = self.hart_state.read_wide_register(wri as usize)?;
+        let bytes = wvalue.to_le_bytes();
+        const RSIZE: usize = size_of::<u32>();
+        for pos in (0..bytes.len()).step_by(RSIZE) {
+            let word = u32::from_le_bytes(bytes[pos..pos + RSIZE].try_into().unwrap());
+            self.dmem.write_mem(dst + pos as u32, word);
+        }
+
+        Ok(false)
+    }
+
+    fn process_bn_sel(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let fg = (dec_insn.funct7 >> 6) & 0b1;
+        let flag = insn_proc::Flags::from_bits_truncate(1 << (dec_insn.funct7 & 0b11) as u8);
+        let flags = self.hart_state.csr_set.get_flags(fg as usize);
+
+        let val = if (flags & flag).is_empty() {
+            self.hart_state.read_wide_register(dec_insn.rs2)?
+        } else {
+            self.hart_state.read_wide_register(dec_insn.rs1)?
+        };
+
+        self.hart_state.write_wide_register(dec_insn.rd, val)?;
+
+        Ok(false)
+    }
+
+    fn process_bn_cmp(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let a = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b = self.hart_state.read_wide_register(dec_insn.rs2)?;
+        let st = dec_insn.funct7 & 0b010_0000 != 0;
+        let sbits = (dec_insn.funct7 & 0b001_1111) << 3;
+        let fg = ((dec_insn.funct7 >> 6) & 0b1) as usize;
+
+        let b = if st {
+            b.wrapping_shr(sbits)
+        } else {
+            b.wrapping_shl(sbits)
+        };
+
+        let (res, carry) = a.overflowing_sub(b);
+
+        self.hart_state.set_mlz_wide_flags(fg, carry, res);
+
+        Ok(false)
+    }
+
+    fn process_bn_cmpb(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let mut a = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b = self.hart_state.read_wide_register(dec_insn.rs2)?;
+        let st = dec_insn.funct7 & 0b010_0000 != 0;
+        let sbits = (dec_insn.funct7 & 0b001_1111) << 3;
+        let fg = ((dec_insn.funct7 >> 6) & 0b1) as usize;
+
+        let b = if st {
+            b.wrapping_shr(sbits)
+        } else {
+            b.wrapping_shl(sbits)
+        };
+
+        // TBC: not sure if carry implementation works
+        let mut carry = false;
+        let flags = self.hart_state.csr_set.get_flags(fg);
+        if !(flags & insn_proc::Flags::CARRY).is_empty() {
+            (a, carry) = a.overflowing_sub(U256::from(1u32));
+        }
+        let (res, carry2) = a.overflowing_sub(b);
+        carry |= carry2;
+
+        self.hart_state.set_mlz_wide_flags(fg, carry, res);
+
+        Ok(false)
+    }
+
+    fn process_bn_mov(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        let val = self.hart_state.read_wide_register(dec_insn.rs1)?;
+
+        self.hart_state.write_wide_register(dec_insn.rd, val)?;
+
+        Ok(false)
+    }
+
+    fn process_bn_movr(&mut self, dec_insn: insn_format::SType) -> Self::InstructionResult {
+        let grd_inc = dec_insn.imm & 0b0001 != 0;
+        let grs_inc = dec_insn.imm & 0b0100 != 0;
+
+        if grd_inc && grs_inc {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                None,
+            ));
+        }
+
+        let grd_val = self.hart_state.read_register(dec_insn.rs2)?;
+        let grs_val = self.hart_state.read_register(dec_insn.rs1)?;
+
+        if grd_val > 31 || grs_val > 31 {
+            return Err(InstructionTrap::Exception(
+                ExceptionCause::EIllegalInsn,
+                None,
+            ));
+        }
+
+        if grd_inc {
+            self.hart_state.write_register(dec_insn.rs2, grd_val + 1)?;
+        }
+
+        if grs_inc {
+            self.hart_state.write_register(dec_insn.rs1, grs_val + 1)?;
+        }
+
+        let val = self.hart_state.read_wide_register(grs_val as usize)?;
+        self.hart_state.write_wide_register(grd_val as usize, val)?;
+
+        Ok(false)
+    }
+
+    fn process_bn_wsrr(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        let wsr = dec_insn.imm as u32 & 0xff;
+        let wval = self.hart_state.read_wsr(wsr)?;
+
+        self.hart_state.write_wide_register(dec_insn.rd, wval)?;
+
+        Ok(false)
+    }
+
+    fn process_bn_wsrw(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult {
+        let wsr = dec_insn.imm as u32 & 0xff;
+        let val = self.hart_state.read_wide_register(dec_insn.rs1)?;
+
+        self.hart_state.write_wsr(wsr, val)?;
+
+        Ok(false)
+    }
+
+    fn process_bn_addm(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let a = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b = self.hart_state.read_wide_register(dec_insn.rs2)?;
+        let modv = self
+            .hart_state
+            .read_wsr(csrs::WSRAddr::r#mod.into())
+            .unwrap();
+
+        let (mut res, over) = a.overflowing_add(b);
+        if over || res > modv {
+            res = res.wrapping_sub(modv)
+        }
+
+        self.hart_state.write_wide_register(dec_insn.rd, res)?;
+
+        Ok(false)
+    }
+
+    fn process_bn_subm(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let a = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b = self.hart_state.read_wide_register(dec_insn.rs2)?;
+        let modv = self
+            .hart_state
+            .read_wsr(csrs::WSRAddr::r#mod.into())
+            .unwrap();
+
+        let (mut res, over) = a.overflowing_sub(b);
+        if over {
+            res = res.wrapping_add(modv)
+        }
+
+        self.hart_state.write_wide_register(dec_insn.rd, res)?;
+
+        Ok(false)
+    }
+
+    fn process_bn_mulqacc(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let zero_acc = dec_insn.funct3 & 0b001 != 0;
+        let acc_shift = 64 * (dec_insn.funct3 >> 1);
+        let qwsel1 = dec_insn.funct7 & 0b11;
+        let qwsel2 = dec_insn.funct7 >> 2 & 0b11;
+
+        let a_val = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b_val = self.hart_state.read_wide_register(dec_insn.rs2)?;
+
+        let a_qw = a_val >> (64 * qwsel1) & U256::from(u64::MAX);
+        let b_qw = b_val >> (64 * qwsel2) & U256::from(u64::MAX);
+
+        let mut mul_res = (a_qw).wrapping_mul(b_qw);
+
+        let acc = if zero_acc {
+            U256::from(0u32)
+        } else {
+            self.hart_state.read_wsr(csrs::WSRAddr::acc.into()).unwrap()
+        };
+
+        mul_res = mul_res.wrapping_shl(acc_shift);
+
+        // add and truncate
+        self.hart_state
+            .write_wsr(csrs::WSRAddr::acc.into(), acc.wrapping_add(mul_res))
+            .and(Ok(false))
+    }
+
+    fn process_bn_mulqacc_wo(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let zero_acc = dec_insn.funct3 & 0b001 != 0;
+        let acc_shift = 64 * (dec_insn.funct3 >> 1);
+        let qwsel1 = dec_insn.funct7 & 0b11;
+        let qwsel2 = dec_insn.funct7 >> 2 & 0b11;
+        let fg = ((dec_insn.funct7 >> 6) & 0b1) as usize;
+
+        let a_val = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b_val = self.hart_state.read_wide_register(dec_insn.rs2)?;
+
+        let a_qw = a_val >> (64 * qwsel1) & U256::from(u64::MAX);
+        let b_qw = b_val >> (64 * qwsel2) & U256::from(u64::MAX);
+
+        let mut mul_res = (a_qw).wrapping_mul(b_qw);
+
+        let acc: u256 = if zero_acc {
+            U256::from(0u32)
+        } else {
+            self.hart_state.read_wsr(csrs::WSRAddr::acc.into()).unwrap()
+        };
+
+        mul_res = mul_res.wrapping_shl(acc_shift);
+        let truncated = acc.wrapping_add(mul_res);
+
+        self.hart_state
+            .write_wide_register(dec_insn.rd, truncated)?;
+        self.hart_state
+            .write_wsr(csrs::WSRAddr::acc.into(), truncated)?;
+
+        self.hart_state.update_mlz_wide_flags(fg, truncated);
+        Ok(false)
+    }
+
+    fn process_bn_mulqacc_so(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let zero_acc = dec_insn.funct3 & 0b001 != 0;
+        let acc_shift = 64 * (dec_insn.funct3 >> 1);
+        let qwsel1 = dec_insn.funct7 & 0b11;
+        let qwsel2 = dec_insn.funct7 >> 2 & 0b11;
+        let hwsel = dec_insn.funct7 >> 4 & 0b1;
+        let fg = ((dec_insn.funct7 >> 6) & 0b1) as usize;
+
+        let a_val = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b_val = self.hart_state.read_wide_register(dec_insn.rs2)?;
+        let d_val = self.hart_state.read_wide_register(dec_insn.rd)?;
+
+        let a_qw = a_val >> (64 * qwsel1) & U256::from(u64::MAX);
+        let b_qw = b_val >> (64 * qwsel2) & U256::from(u64::MAX);
+
+        let mut mul_res = a_qw.wrapping_mul(b_qw);
+
+        let acc: u256 = if zero_acc {
+            U256::from(0u32)
+        } else {
+            self.hart_state.read_wsr(csrs::WSRAddr::acc.into()).unwrap()
+        };
+
+        mul_res = mul_res.wrapping_shl(acc_shift);
+        let truncated = acc.wrapping_add(mul_res);
+
+        let lo_part = U256::from(*truncated.low());
+        let hi_part = U256::from(*truncated.high());
+        let hw_shift = 128 * hwsel;
+        let hw_mask = U256::from(u128::MAX) << hw_shift;
+        let wrd = (d_val & !hw_mask) | (lo_part << hw_shift);
+
+        self.hart_state.write_wide_register(dec_insn.rd, wrd)?;
+        self.hart_state
+            .write_wsr(csrs::WSRAddr::acc.into(), hi_part)?;
+
+        let flags = self.hart_state.csr_set.get_flags(fg);
+        let mut new_flags;
+        if hwsel != 0 {
+            new_flags = flags & (insn_proc::Flags::CARRY | insn_proc::Flags::LSB);
+            if ((lo_part >> 127u32).as_u32() & 0b1) != 0 {
+                new_flags |= insn_proc::Flags::MSB;
+            }
+            if lo_part == 0 {
+                new_flags |= flags & insn_proc::Flags::ZERO;
+            }
+        } else {
+            new_flags = flags & (insn_proc::Flags::CARRY | insn_proc::Flags::MSB);
+            if (lo_part & 0b1) != 0 {
+                new_flags |= insn_proc::Flags::LSB;
+            }
+            if lo_part == 0 {
+                new_flags |= insn_proc::Flags::ZERO;
+            }
+        }
+
+        self.hart_state.csr_set.set_flags(fg, new_flags);
+
+        Ok(false)
+    }
+
+    make_alu_bn_op_reg_fn! {and, |a, b| a & b}
+    make_alu_bn_op_reg_fn! {or, |a, b| a | b}
+    make_alu_bn_op_reg_fn! {xor, |a, b| a ^ b}
+    make_alu_bn_op_imm_fn! {add, |a, b| a.overflowing_add(b)}
+    make_alu_bn_op_imm_fn! {sub, |a, b| a.overflowing_sub(b)}
+    make_alu_bn_of_op_reg_fn! {add, |a, b| a.overflowing_add(b), false}
+    make_alu_bn_of_op_reg_fn! {sub, |a, b| a.overflowing_sub(b), false}
+    make_alu_bn_of_op_reg_fn! {addc, |a, b| a.overflowing_add(b), true}
+    make_alu_bn_of_op_reg_fn! {subb, |a, b| a.overflowing_sub(b), true}
+
+    fn process_bn_not(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let a = self.hart_state.read_wide_register(dec_insn.rs2)?;
+        let st = dec_insn.funct7 & 0b010_0000 != 0;
+        let sbits = (dec_insn.funct7 & 0b001_1111) << 3;
+        let a = if st {
+            a.wrapping_shr(sbits)
+        } else {
+            a.wrapping_shl(sbits)
+        };
+        let fg = ((dec_insn.funct7 >> 6) & 0b1) as usize;
+
+        let res = !a;
+        self.hart_state.write_wide_register(dec_insn.rd, res)?;
+        self.hart_state.update_mlz_wide_flags(fg, res);
+
+        Ok(false)
+    }
+
+    fn process_bn_rshi(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult {
+        let imm = (dec_insn.funct7 << 1) | (dec_insn.funct3 >> 2);
+        let a = self.hart_state.read_wide_register(dec_insn.rs1)?;
+        let b = self.hart_state.read_wide_register(dec_insn.rs2)?;
+
+        let res = a.wrapping_shl(256 - imm) | b.wrapping_shr(imm);
+
+        self.hart_state.write_wide_register(dec_insn.rd, res)?;
+
+        Ok(false)
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/insn_format.rs b/hw/opentitan/otbn/otbn/src/insn_format.rs
new file mode 100644
index 0000000000000..1764f33ca9ad9
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/insn_format.rs
@@ -0,0 +1,220 @@
+// Copyright 2021 Gregory Chadwick <mail@gregchadwick.co.uk>
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+//! Structures for instruction decoding
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct RType {
+    pub funct7: u32,
+    pub rs2: usize,
+    pub rs1: usize,
+    pub funct3: u32,
+    pub rd: usize,
+}
+
+impl RType {
+    pub fn new(insn: u32) -> RType {
+        RType {
+            funct7: (insn >> 25) & 0x7f,
+            rs2: ((insn >> 20) & 0x1f) as usize,
+            rs1: ((insn >> 15) & 0x1f) as usize,
+            funct3: (insn >> 12) & 0x7,
+            rd: ((insn >> 7) & 0x1f) as usize,
+        }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct IType {
+    pub imm: i32,
+    pub rs1: usize,
+    pub funct3: u32,
+    pub rd: usize,
+}
+
+impl IType {
+    pub fn new(insn: u32) -> IType {
+        let uimm: i32 = ((insn >> 20) & 0x7ff) as i32;
+
+        let imm: i32 = if (insn & 0x8000_0000) != 0 {
+            uimm - (1 << 11)
+        } else {
+            uimm
+        };
+
+        IType {
+            imm,
+            rs1: ((insn >> 15) & 0x1f) as usize,
+            funct3: (insn >> 12) & 0x7,
+            rd: ((insn >> 7) & 0x1f) as usize,
+        }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct ITypeShamt {
+    pub funct7: u32,
+    pub shamt: u32,
+    pub rs1: usize,
+    pub funct3: u32,
+    pub rd: usize,
+}
+
+impl ITypeShamt {
+    pub fn new(insn: u32) -> ITypeShamt {
+        let itype = IType::new(insn);
+
+        ITypeShamt {
+            funct7: (insn >> 25) & 0x7f,
+            shamt: (itype.imm as u32) & 0x1f,
+            rs1: itype.rs1,
+            funct3: itype.funct3,
+            rd: itype.rd,
+        }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct WidType {
+    pub imm: i32,
+    pub rs2: usize,
+    pub rs1: usize,
+    pub funct3: u32,
+    pub inc: u32,
+}
+
+impl WidType {
+    pub fn new(insn: u32) -> WidType {
+        let uimm: i32 = (((insn >> 25) & 0x7f) | ((insn >> 2) & 0x380)) as i32;
+
+        let imm: i32 = if (insn & 0x800) != 0 {
+            uimm - (1 << 10)
+        } else {
+            uimm
+        };
+
+        WidType {
+            imm,
+            rs2: ((insn >> 20) & 0x1f) as usize,
+            rs1: ((insn >> 15) & 0x1f) as usize,
+            funct3: (insn >> 12) & 0x7,
+            inc: (insn >> 7) & 0x3,
+        }
+    }
+}
+
+pub struct ITypeCSR {
+    pub csr: u32,
+    pub rs1: usize,
+    pub funct3: u32,
+    pub rd: usize,
+}
+
+impl ITypeCSR {
+    pub fn new(insn: u32) -> ITypeCSR {
+        let csr: u32 = (insn >> 20) & 0xfff;
+
+        ITypeCSR {
+            csr,
+            rs1: ((insn >> 15) & 0x1f) as usize,
+            funct3: (insn >> 12) & 0x7,
+            rd: ((insn >> 7) & 0x1f) as usize,
+        }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct SType {
+    pub imm: i32,
+    pub rs2: usize,
+    pub rs1: usize,
+    pub funct3: u32,
+}
+
+impl SType {
+    pub fn new(insn: u32) -> SType {
+        let uimm: i32 = (((insn >> 20) & 0x7e0) | ((insn >> 7) & 0x1f)) as i32;
+
+        let imm: i32 = if (insn & 0x8000_0000) != 0 {
+            uimm - (1 << 11)
+        } else {
+            uimm
+        };
+
+        SType {
+            imm,
+            rs2: ((insn >> 20) & 0x1f) as usize,
+            rs1: ((insn >> 15) & 0x1f) as usize,
+            funct3: (insn >> 12) & 0x7,
+        }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct BType {
+    pub imm: i32,
+    pub rs2: usize,
+    pub rs1: usize,
+    pub funct3: u32,
+}
+
+impl BType {
+    pub fn new(insn: u32) -> BType {
+        let uimm: i32 =
+            (((insn >> 20) & 0x7e0) | ((insn >> 7) & 0x1e) | ((insn & 0x80) << 4)) as i32;
+
+        let imm: i32 = if (insn & 0x8000_0000) != 0 {
+            uimm - (1 << 12)
+        } else {
+            uimm
+        };
+
+        BType {
+            imm,
+            rs2: ((insn >> 20) & 0x1f) as usize,
+            rs1: ((insn >> 15) & 0x1f) as usize,
+            funct3: (insn >> 12) & 0x7,
+        }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct UType {
+    pub imm: i32,
+    pub rd: usize,
+}
+
+impl UType {
+    pub fn new(insn: u32) -> UType {
+        UType {
+            imm: (insn & 0xffff_f000) as i32,
+            rd: ((insn >> 7) & 0x1f) as usize,
+        }
+    }
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct JType {
+    pub imm: i32,
+    pub rd: usize,
+}
+
+impl JType {
+    pub fn new(insn: u32) -> JType {
+        let uimm: i32 =
+            ((insn & 0xff000) | ((insn & 0x100000) >> 9) | ((insn >> 20) & 0x7fe)) as i32;
+
+        let imm: i32 = if (insn & 0x8000_0000) != 0 {
+            uimm - (1 << 20)
+        } else {
+            uimm
+        };
+
+        JType {
+            imm,
+            rd: ((insn >> 7) & 0x1f) as usize,
+        }
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/insn_proc.rs b/hw/opentitan/otbn/otbn/src/insn_proc.rs
new file mode 100644
index 0000000000000..931857a5dc2f0
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/insn_proc.rs
@@ -0,0 +1,100 @@
+// Copyright 2021 Gregory Chadwick <mail@gregchadwick.co.uk>
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use bitflags::bitflags;
+
+use super::insn_format;
+
+/// A trait for objects which do something with OTBN instructions.
+///
+/// There is one function per OTBN instruction. Each function takes the appropriate struct from
+/// [insn_format] giving access to the decoded fields of the instruction. All functions
+/// return the [InstructionProcessor::InstructionResult] associated type.
+pub trait InstructionProcessor {
+    type InstructionResult;
+
+    fn process_add(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_sub(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_sll(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_xor(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_srl(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_sra(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_or(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_and(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+
+    fn process_addi(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+    fn process_slli(&mut self, dec_insn: insn_format::ITypeShamt) -> Self::InstructionResult;
+    fn process_xori(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+    fn process_srli(&mut self, dec_insn: insn_format::ITypeShamt) -> Self::InstructionResult;
+    fn process_srai(&mut self, dec_insn: insn_format::ITypeShamt) -> Self::InstructionResult;
+    fn process_ori(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+    fn process_andi(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+
+    fn process_lui(&mut self, dec_insn: insn_format::UType) -> Self::InstructionResult;
+
+    fn process_beq(&mut self, dec_insn: insn_format::BType) -> Self::InstructionResult;
+    fn process_bne(&mut self, dec_insn: insn_format::BType) -> Self::InstructionResult;
+
+    fn process_lw(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+
+    fn process_sw(&mut self, dec_insn: insn_format::SType) -> Self::InstructionResult;
+
+    fn process_jal(&mut self, dec_insn: insn_format::JType) -> Self::InstructionResult;
+    fn process_jalr(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+
+    fn process_csrrw(&mut self, dec_insn: insn_format::ITypeCSR) -> Self::InstructionResult;
+    fn process_csrrs(&mut self, dec_insn: insn_format::ITypeCSR) -> Self::InstructionResult;
+
+    fn process_ecall(&mut self) -> Self::InstructionResult;
+
+    // custom-0
+    fn process_bn_lid(&mut self, dec_insn: insn_format::WidType) -> Self::InstructionResult;
+    fn process_bn_sid(&mut self, dec_insn: insn_format::WidType) -> Self::InstructionResult;
+    fn process_bn_sel(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+
+    fn process_bn_cmp(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_cmpb(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+
+    fn process_bn_mov(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+    fn process_bn_movr(&mut self, dec_insn: insn_format::SType) -> Self::InstructionResult;
+
+    fn process_bn_wsrr(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+    fn process_bn_wsrw(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+
+    // custom-1
+    fn process_bn_add(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_addc(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_addm(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_addi(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+    fn process_bn_sub(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_subb(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_subm(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_subi(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+
+    // op-32
+    fn process_bn_mulqacc(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_mulqacc_wo(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_mulqacc_so(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+
+    // custom-3
+    fn process_loop(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+    fn process_loopi(&mut self, dec_insn: insn_format::IType) -> Self::InstructionResult;
+
+    fn process_bn_and(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_or(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_not(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_xor(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+    fn process_bn_rshi(&mut self, dec_insn: insn_format::RType) -> Self::InstructionResult;
+}
+
+bitflags! {
+    #[derive(Default)]
+    pub struct Flags: u8 {
+        const CARRY = 0b0001;
+        const MSB = 0b0010;
+        const LSB = 0b0100;
+        const ZERO = 0b1000;
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/key.rs b/hw/opentitan/otbn/otbn/src/key.rs
new file mode 100644
index 0000000000000..6df160970eae4
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/key.rs
@@ -0,0 +1,57 @@
+// Copyright 2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use std::convert::TryInto;
+use std::sync::Mutex;
+
+use ethnum::{u256, U256};
+
+#[derive(Default)]
+pub struct KeyStore {
+    pub lo: [u256; 2],
+    pub hi: [u256; 2],
+    pub valid: bool,
+}
+
+pub struct Key {
+    pub store: Mutex<KeyStore>,
+}
+
+impl Default for Key {
+    fn default() -> Self {
+        let store = KeyStore::default();
+        Self {
+            store: Mutex::new(store),
+        }
+    }
+}
+
+impl Key {
+    pub fn new() -> Self {
+        Self::default()
+    }
+
+    pub fn clear(&mut self) {
+        /* called from OTBN proxy */
+        let mut store = self.store.lock().unwrap();
+        store.lo = [U256::from(0u32), U256::from(0u32)];
+        store.hi = [U256::from(0u32), U256::from(0u32)];
+        store.valid = false;
+    }
+
+    pub fn fill(&self, share0: &[u8; 48], share1: &[u8; 48], valid: bool) {
+        /* called from OTBN proxy */
+        let lo0 = U256::from_le_bytes(share0[0..32].try_into().unwrap());
+        let lo1 = U256::from_words(0, u128::from_le_bytes(share0[32..48].try_into().unwrap()));
+
+        let hi0 = U256::from_le_bytes(share1[0..32].try_into().unwrap());
+        let hi1 = U256::from_words(0, u128::from_le_bytes(share1[32..48].try_into().unwrap()));
+
+        let mut store = self.store.lock().unwrap();
+
+        store.lo = [lo0, lo1];
+        store.hi = [hi0, hi1];
+        store.valid = valid;
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/lib.rs b/hw/opentitan/otbn/otbn/src/lib.rs
new file mode 100644
index 0000000000000..6492798c1a02a
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/lib.rs
@@ -0,0 +1,85 @@
+// Copyright 2021 Gregory Chadwick <mail@gregchadwick.co.uk>
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+//! OTBN instruction set simulator library
+
+extern crate bitflags;
+extern crate ethnum;
+extern crate paste;
+
+use ethnum::u256;
+
+pub mod comm;
+pub mod csrs;
+pub mod insn_decode;
+pub mod insn_disasm;
+pub mod insn_exec;
+pub mod insn_format;
+pub mod insn_proc;
+pub mod key;
+pub mod memory;
+pub mod otbn;
+pub mod proxy;
+pub mod random;
+pub mod xoshiro256pp;
+
+#[derive(PartialEq, Eq, Clone, Copy, Debug)]
+#[repr(u32)]
+pub enum ExceptionCause {
+    EBadDataAddr = 1 << 0,
+    EBadInsnAddr = 1 << 1,
+    ECallStack = 1 << 2,
+    EIllegalInsn = 1 << 3,
+    ELoop = 1 << 4,
+    EKeyInvalid = 1 << 5,
+    ERndRepChkFail = 1 << 6,
+    ERndFipsChkFail = 1 << 7,
+    EFatal = 1 << 20,
+    ECallMMode = 1 << 31,
+}
+
+/// Special purpose register (narrow, 32-bit)
+pub trait CSR {
+    fn read(&self) -> Result<u32, ExceptionCause>;
+    fn write(&mut self, val: u32) -> Result<(), ExceptionCause>;
+}
+
+/// Special purpose register (wide, 256-bit)
+pub trait WSR {
+    fn read(&self) -> Result<u256, ExceptionCause>;
+    fn write(&mut self, val: u256) -> Result<(), ExceptionCause>;
+}
+
+/// Cryptograph-secure random generator trait
+pub trait CSRNG {
+    fn get_csrng_u32(&self) -> (u32, bool, bool);
+    fn get_csrng_u256(&self) -> (u256, bool, bool);
+}
+
+/// Pseudo random generator trait
+pub trait PRNG {
+    fn get_prng_u32(&mut self) -> u32;
+    fn get_prng_u64(&mut self) -> u64;
+    fn get_prng_u256(&mut self) -> u256;
+}
+
+/// A trait for objects which implement memory operations
+pub trait Memory: Send {
+    /// Read `size` bytes from `addr`.
+    ///
+    /// `addr` must be aligned to `size`.
+    /// Returns `None` if `addr` doesn't exist in this memory.
+    fn read_mem(&mut self, addr: u32) -> Option<u32>;
+
+    /// Write `size` bytes of `store_data` to `addr`
+    ///
+    /// `addr` must be aligned to `size`.
+    /// Returns `true` if write succeeds.
+    fn write_mem(&mut self, addr: u32, store_data: u32) -> bool;
+
+    fn wipe(&mut self, prng: &mut dyn PRNG);
+
+    fn update_from_slice(&mut self, src: &[u32]);
+}
diff --git a/hw/opentitan/otbn/otbn/src/memory.rs b/hw/opentitan/otbn/otbn/src/memory.rs
new file mode 100644
index 0000000000000..3d55de616d632
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/memory.rs
@@ -0,0 +1,135 @@
+// Copyright 2021 Gregory Chadwick <mail@gregchadwick.co.uk>
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use crate::PRNG;
+use std::io::{self, ErrorKind, Read};
+
+use super::Memory;
+
+/// Read bytes from an [std::io::Read] into a [Memory] starting at the given address
+pub fn read_to_memory(
+    reader: &mut impl Read,
+    memory: &mut impl Memory,
+    size: usize,
+) -> io::Result<()> {
+    let mut addr: usize = 0;
+    loop {
+        let mut buffer = [0; 4];
+        if let Err(error) = reader.read_exact(&mut buffer) {
+            match error.kind() {
+                ErrorKind::UnexpectedEof => break,
+                _ => return Err(error),
+            }
+        }
+        let word = u32::from_le_bytes(buffer);
+        if !memory.write_mem(addr as u32, word) {
+            return Err(io::Error::new(
+                io::ErrorKind::Other,
+                format!("Could not write byte at address 0x{:08x}", addr),
+            ));
+        }
+        addr += 4;
+        if addr >= size {
+            break;
+        }
+    }
+
+    Ok(())
+}
+
+/// [Vec] backed memory.
+///
+/// The [Vec] uses `u32` as the base type. Any read or write that falls out of the [Vec]s size will
+/// result in a failed read or write.
+pub struct VecMemory {
+    pub mem: Vec<u32>,
+}
+
+impl VecMemory {
+    pub fn new(size: usize) -> Self {
+        Self {
+            mem: vec![0u32; size / 4],
+        }
+    }
+
+    fn random_wipe(&mut self, prng: &mut dyn PRNG) {
+        for cell in self.mem.iter_mut() {
+            *cell = prng.get_prng_u32();
+        }
+    }
+}
+
+impl Memory for VecMemory {
+    fn read_mem(&mut self, addr: u32) -> Option<u32> {
+        if (addr & 0x3) != 0 {
+            panic!("Memory read must be aligned");
+        }
+
+        // Calculate vector index required data is contained in
+        let word_addr = addr >> 2;
+
+        // Read data from vector
+        let read_data = self.mem.get(word_addr as usize).copied()?;
+
+        // Apply mask and shift to extract required data from word
+        Some(read_data)
+    }
+
+    fn write_mem(&mut self, addr: u32, store_data: u32) -> bool {
+        // Calculate a mask and shift needed to update 32-bit word
+        if (addr & 0x3) != 0 {
+            panic!("Memory write must be aligned");
+        }
+
+        // Calculate vector index data to update is contained in
+        let word_addr = (addr >> 2) as usize;
+
+        self.mem[word_addr] = store_data;
+        true
+    }
+
+    fn update_from_slice(&mut self, src: &[u32]) {
+        if src.len() < self.mem.len() {
+            let (head, _) = self.mem.split_at_mut(src.len());
+            head.copy_from_slice(src);
+        } else {
+            self.mem.copy_from_slice(src);
+        }
+    }
+
+    fn wipe(&mut self, prng: &mut dyn PRNG) {
+        self.random_wipe(prng);
+    }
+}
+
+pub struct MemoryRegion {
+    memory: Box<dyn Memory>,
+}
+
+impl MemoryRegion {
+    pub fn new(size: usize) -> Self {
+        Self {
+            memory: Box::new(VecMemory::new(size)),
+        }
+    }
+}
+
+impl Memory for MemoryRegion {
+    fn read_mem(&mut self, addr: u32) -> Option<u32> {
+        self.memory.read_mem(addr)
+    }
+
+    fn write_mem(&mut self, addr: u32, store_data: u32) -> bool {
+        self.memory.write_mem(addr, store_data)
+    }
+
+    fn update_from_slice(&mut self, src: &[u32]) {
+        self.memory.update_from_slice(src);
+    }
+
+    fn wipe(&mut self, prng: &mut dyn PRNG) {
+        self.memory.wipe(prng)
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/otbn.rs b/hw/opentitan/otbn/otbn/src/otbn.rs
new file mode 100644
index 0000000000000..a49e4d789941c
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/otbn.rs
@@ -0,0 +1,556 @@
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+extern crate ethnum;
+
+use std::fs::File;
+use std::io;
+use std::io::Write;
+use std::sync::atomic::{AtomicBool, AtomicU32, AtomicUsize, Ordering};
+use std::sync::{Arc, Mutex};
+use std::thread;
+use std::time::Duration;
+
+use bitflags::bitflags;
+
+use ethnum::U256;
+
+use super::comm;
+use super::csrs;
+use super::insn_decode;
+use super::insn_disasm;
+use super::insn_exec;
+use super::key;
+use super::memory;
+use super::random;
+use super::Memory;
+use crate::{ExceptionCause, PRNG};
+
+/// Instruction memory size
+pub const IMEM_SIZE: usize = 8 << 10;
+/// Data memory size
+pub const DMEM_SIZE: usize = 4 << 10;
+/// Data public memory size
+pub const DMEM_PUB_SIZE: usize = 3 << 10;
+
+bitflags! {
+    /// List of bits in the ERR_BITS register
+    #[derive(Default)]
+    pub struct ErrBits: u32 {
+        const BAD_DATA_ADDR = 1 << 0;
+        const BAD_INSN_ADDR = 1 << 1;
+        const CALL_STACK = 1 << 2;
+        const ILLEGAL_INSN = 1 << 3;
+        const LOOP = 1 << 4;
+        const KEY_INVALID = 1 << 5;
+        const RND_REP_CHK_FAIL = 1 << 6;
+        const RND_FIPS_CHK_FAIL = 1 << 7;
+        const IMEM_INTG_VIOLATION = 1 << 16;
+        const DMEM_INTG_VIOLATION = 1 << 17;
+        const REG_INTG_VIOLATION = 1 << 18;
+        const BUS_INTG_VIOLATION = 1 << 19;
+        const BAD_INTERNAL_STATE = 1 << 20;
+        const ILLEGAL_BUS_ACCESS = 1 << 21;
+        const LIFECYCLE_ESCALATION = 1 << 22;
+        const FATAL_SOFTWARE = 1 << 23;
+    }
+}
+
+pub enum FlagMode {
+    Fg0 = 0x0,
+    Fg1 = 0x1,
+    Flags = 0x2,
+}
+
+#[derive(Clone, Copy, Debug, Default, PartialEq, Eq)]
+pub enum Status {
+    #[default]
+    Idle = 0,
+    BusyExecute = 1,
+    BusySecWipeDMem = 2,
+    BusySecWipeIMem = 3,
+    BusySecWipeInt = 4,
+    Locked = 0xff,
+}
+
+impl Status {
+    pub fn from_u32(val: u32) -> Self {
+        match val {
+            val if val == Status::Idle as u32 => Status::Idle,
+            val if val == Status::BusyExecute as u32 => Status::BusyExecute,
+            val if val == Status::BusySecWipeDMem as u32 => Status::BusySecWipeDMem,
+            val if val == Status::BusySecWipeIMem as u32 => Status::BusySecWipeIMem,
+            val if val == Status::BusySecWipeInt as u32 => Status::BusySecWipeInt,
+            _ => Status::Locked,
+        }
+    }
+}
+
+#[derive(Default)]
+pub struct Registers {
+    /// Status bitfield
+    pub status: Arc<AtomicU32>,
+    /// ErrBits bitfield
+    pub err_bits: Arc<AtomicU32>,
+    /// ErrBits bitfield,
+    pub fatal_bits: Arc<AtomicU32>,
+    pub ctrl: Arc<AtomicBool>,
+    pub insn_count: Arc<AtomicUsize>,
+}
+
+/// OTBN executer
+/// Run from a worker thread
+/// Use two channels to communicate w/ the proxy and shared registers
+pub struct Executer {
+    hart_state: insn_exec::HartState,
+    imem: Arc<Mutex<memory::MemoryRegion>>,
+    dmem: Arc<Mutex<memory::MemoryRegion>>,
+    channel: comm::UpChannel,
+    registers: Arc<Registers>,
+    syncurnd: Arc<random::SyncUrnd>,
+    on_complete: Option<Box<dyn comm::Callback>>,
+    log_file: Option<Box<dyn io::Write>>,
+    log_asm: bool,
+}
+
+impl Executer {
+    #[allow(clippy::too_many_arguments)]
+    fn new(
+        channel: comm::UpChannel,
+        registers: Arc<Registers>,
+        imem: Arc<Mutex<memory::MemoryRegion>>,
+        dmem: Arc<Mutex<memory::MemoryRegion>>,
+        syncurnd: Arc<random::SyncUrnd>,
+        rnd: Arc<random::Rnd>,
+        key: Arc<key::Key>,
+        on_complete: Option<Box<dyn comm::Callback>>,
+        log_name: Option<String>,
+        log_asm: bool,
+    ) -> Self {
+        let log_file: Option<Box<dyn io::Write>>;
+        if let Some(logname) = log_name {
+            if logname == "stderr" {
+                log_file = Some(Box::new(io::stderr()));
+            } else {
+                log_file = Some(Box::new(File::create(logname).unwrap()));
+            }
+        } else {
+            log_file = None;
+        }
+        Self {
+            hart_state: insn_exec::HartState::new(syncurnd.urnd(), rnd, key),
+            imem,
+            dmem,
+            channel,
+            registers,
+            syncurnd,
+            on_complete,
+            log_file,
+            log_asm,
+        }
+    }
+
+    #[allow(clippy::too_many_arguments)]
+    pub fn run(
+        channel: comm::UpChannel,
+        registers: Arc<Registers>,
+        imem: Arc<Mutex<memory::MemoryRegion>>,
+        dmem: Arc<Mutex<memory::MemoryRegion>>,
+        urnd: Arc<random::SyncUrnd>,
+        rnd: Arc<random::Rnd>,
+        key: Arc<key::Key>,
+        on_complete: Option<Box<dyn comm::Callback>>,
+        log_name: Option<String>,
+        log_asm: bool,
+    ) {
+        Self::new(
+            channel,
+            registers,
+            imem,
+            dmem,
+            urnd,
+            rnd,
+            key,
+            on_complete,
+            log_name,
+            log_asm,
+        )
+        .enter();
+    }
+
+    fn enter(&mut self) {
+        self.set_status(Status::Idle);
+        let threadid = thread::current().id();
+        self.channel
+            .1
+            .send(comm::Response::Active(threadid))
+            .unwrap();
+        loop {
+            let cmd = self.channel.0.recv().unwrap();
+            let state = self.get_status();
+            match state {
+                Status::Idle => self.handle_comm(cmd),
+                Status::BusyExecute
+                | Status::BusySecWipeDMem
+                | Status::BusySecWipeIMem
+                | Status::BusySecWipeInt => {
+                    self.channel
+                        .1
+                        .send(comm::Response::Error("busy".to_string()))
+                        .unwrap();
+                }
+                Status::Locked => {
+                    self.channel
+                        .1
+                        .send(comm::Response::Error("locked".to_string()))
+                        .unwrap();
+                }
+            }
+        }
+    }
+
+    fn get_status(&self) -> Status {
+        let val = self.registers.status.load(Ordering::Relaxed);
+        Status::from_u32(val)
+    }
+
+    fn set_status(&mut self, status: Status) {
+        self.registers
+            .status
+            .store(status as u32, Ordering::Relaxed);
+    }
+
+    /// Handle requests from the proxy
+    fn handle_comm(&mut self, cmd: comm::Command) {
+        match cmd {
+            comm::Command::SetTestMode(enable) => {
+                self.hart_state.set_test_mode(enable);
+                self.channel.1.send(comm::Response::Ack).unwrap();
+                self.signal_completion();
+            }
+            comm::Command::LogTo(logfile) => {
+                self.log_file = Some(logfile);
+                self.channel.1.send(comm::Response::Ack).unwrap();
+                self.signal_completion();
+            }
+            comm::Command::Execute(dump) => {
+                // always update the state before replying
+                self.set_status(Status::BusyExecute);
+                self.channel.1.send(comm::Response::Ack).unwrap();
+                self.execute(dump);
+                self.signal_completion();
+            }
+            comm::Command::WipeDMem => {
+                // always update the state before replying
+                self.set_status(Status::BusySecWipeDMem);
+                self.channel.1.send(comm::Response::Ack).unwrap();
+                self.wipe_memory(false);
+                self.signal_completion();
+            }
+            comm::Command::WipeIMem => {
+                // always update the state before replying
+                self.set_status(Status::BusySecWipeIMem);
+                self.channel.1.send(comm::Response::Ack).unwrap();
+                self.wipe_memory(true);
+                self.signal_completion();
+            }
+            comm::Command::Terminate => {
+                self.set_status(Status::Locked);
+                self.channel.1.send(comm::Response::Ack).unwrap();
+                self.signal_completion();
+            }
+        }
+    }
+
+    /// Execute the uploaded OTBN program
+    fn execute(&mut self, dump: bool) {
+        let mut fatal;
+        // "Each new execution of OTBN will reseed the URND PRNG."
+        // Stall OTBN execution till entropy is injected
+        self.syncurnd.sync_reseed();
+        match self.do_execute(dump) {
+            insn_exec::InstructionTrap::Exception(cause, _val) => {
+                let mut error: u32;
+                // let mut registers = self.registers.lock().unwrap();
+                (fatal, error) = match cause {
+                    ExceptionCause::ECallMMode => (false, ErrBits::empty().bits()),
+                    ExceptionCause::EBadDataAddr => (false, ErrBits::BAD_DATA_ADDR.bits()),
+                    ExceptionCause::EBadInsnAddr => (false, ErrBits::BAD_INSN_ADDR.bits()),
+                    ExceptionCause::ECallStack => (false, ErrBits::CALL_STACK.bits()),
+                    ExceptionCause::EIllegalInsn => (false, ErrBits::ILLEGAL_INSN.bits()),
+                    ExceptionCause::ELoop => (false, ErrBits::LOOP.bits()),
+                    ExceptionCause::EKeyInvalid => (false, ErrBits::KEY_INVALID.bits()),
+                    ExceptionCause::ERndRepChkFail => (false, ErrBits::RND_REP_CHK_FAIL.bits()),
+                    ExceptionCause::ERndFipsChkFail => (false, ErrBits::RND_FIPS_CHK_FAIL.bits()),
+                    ExceptionCause::EFatal => {
+                        (true, self.registers.fatal_bits.load(Ordering::Relaxed))
+                    }
+                };
+
+                // ctrl: "Controls the reaction to software errors.
+                // When set software errors produce fatal errors, rather than recoverable errors."
+                if error != 0 && self.registers.ctrl.load(Ordering::Relaxed) {
+                    fatal = true;
+                    error |= ErrBits::FATAL_SOFTWARE.bits();
+                }
+                // update error bits
+                self.registers.err_bits.fetch_or(error, Ordering::Relaxed);
+            }
+        }
+        if fatal {
+            let x: Arc<Mutex<dyn PRNG>> = self.syncurnd.urnd();
+            self.dmem.try_lock().unwrap().wipe(&mut *x.lock().unwrap());
+            self.imem.try_lock().unwrap().wipe(&mut *x.lock().unwrap());
+            self.registers.insn_count.store(0, Ordering::Relaxed);
+            self.set_status(Status::Locked);
+        };
+        // note: it is required that the OTBN client calls
+        // Proxy::acknowledge_execution() to reset the OTBN status once the
+        // operation on its side is over. Busy status is updated on that ack.
+    }
+
+    fn do_execute(&mut self, dump: bool) -> insn_exec::InstructionTrap {
+        let mut executor = insn_exec::InstructionExecutor {
+            hart_state: &mut self.hart_state,
+            imem: &mut *self.imem.try_lock().unwrap(),
+            dmem: &mut *self.dmem.try_lock().unwrap(),
+        };
+
+        executor.reset();
+
+        self.registers
+            .err_bits
+            .store(ErrBits::empty().bits(), Ordering::Relaxed);
+        self.registers.insn_count.store(0, Ordering::Relaxed);
+
+        loop {
+            // Debug/traces
+            if self.log_asm {
+                if let Some(log_file) = &mut self.log_file {
+                    // Output current instruction disassembly to log
+                    if let Some(insn_bits) = executor.imem.read_mem(executor.hart_state.pc) {
+                        let mut outputter = insn_disasm::InstructionStringOutputter {
+                            insn_pc: executor.hart_state.pc,
+                        };
+                        if let Some(inst) = insn_decode::decoder(&mut outputter, insn_bits) {
+                            writeln!(
+                                log_file,
+                                "{:04x}: {:08x} {}",
+                                executor.hart_state.pc, insn_bits, inst
+                            )
+                            .expect("Log file write failed");
+                        } else {
+                            let base = (insn_bits >> 2) & 0b11111;
+                            let funct3 = (insn_bits >> 12) & 0b111;
+                            writeln!(
+                                log_file,
+                                "Unable to decode instruction @ {:x}: {:x} [{:03b}..{:05b}]",
+                                executor.hart_state.pc, insn_bits, funct3, base
+                            )
+                            .expect("Log file write failed");
+                        }
+                    } else {
+                        writeln!(log_file, "Could not read PC {:08x}", executor.hart_state.pc)
+                            .expect("Log file write failed");
+                    }
+                }
+            }
+
+            let fatalbits = self.registers.fatal_bits.load(Ordering::Relaxed);
+            let result = if fatalbits == 0 {
+                // Execute instruction
+                executor.step()
+            } else {
+                Err(insn_exec::InstructionTrap::Exception(
+                    ExceptionCause::EFatal,
+                    Some(fatalbits),
+                ))
+            };
+            if let Err(trap) = result {
+                if let Some(log_file) = &mut self.log_file {
+                    let log_line = match trap {
+                        insn_exec::InstructionTrap::Exception(cause, val) => {
+                            if let Some(val) = val {
+                                format!("[{:?} Exception, value:{:08x}]", cause, val)
+                            } else {
+                                format!("[{:?} Exception]", cause)
+                            }
+                        }
+                    };
+
+                    writeln!(log_file, "{} @ PC {:08x}", log_line, executor.hart_state.pc)
+                        .expect("Log file write failed");
+                }
+
+                if dump {
+                    Self::dump_hart_state(executor.hart_state, true);
+                }
+
+                // on a fatal error
+                // on recoverable error
+                // on operation completion
+                self.registers
+                    .status
+                    .store(Status::BusySecWipeInt as u32, Ordering::Relaxed);
+
+                // "The wiping procedure is a two-step process:
+                //   Overwrite the state with randomness from URND and request a reseed of URND.
+                //   Overwrite the state with randomness from reseeded URND."
+                let prng: Arc<Mutex<dyn PRNG>> = self.syncurnd.urnd();
+                executor.wipe_internal(&prng);
+                self.syncurnd.sync_reseed();
+                executor.wipe_internal(&prng);
+
+                let insn_exec::InstructionTrap::Exception(cause, _) = trap;
+                if cause == ExceptionCause::ECallMMode {
+                    // if the exception has been triggered by an ecall instruction,
+                    // the actual instruction has been executed; otherwise the instruction failed
+                    // to execute
+                    self.registers.insn_count.fetch_add(1, Ordering::Relaxed);
+                } else {
+                    executor.hart_state.pc = 0;
+                }
+
+                return trap;
+            }
+
+            self.registers.insn_count.fetch_add(1, Ordering::Relaxed);
+
+            if self.log_asm {
+                if let Some(log_file) = &mut self.log_file {
+                    Executer::log_changes(executor.hart_state, log_file);
+                }
+            }
+        }
+    }
+
+    fn wipe_memory(&mut self, doi: bool) {
+        let memory = if doi { &mut self.imem } else { &mut self.dmem };
+
+        memory
+            .try_lock()
+            .unwrap()
+            .wipe(&mut *self.syncurnd.urnd().lock().unwrap());
+
+        // simulate a "long lasting" op
+        thread::sleep(Duration::from_micros(200));
+
+        // note: it is expected that the OTBN client calls
+        // Proxy::acknowledge_execution() to reset the OTBN status once the
+        // operation on its side is over
+    }
+
+    fn signal_completion(&mut self) {
+        if let Some(cb) = &mut self.on_complete {
+            cb.signal();
+        }
+    }
+
+    /// Set the log file to which execution traces should be dumped - if any
+    fn log_changes(hart_state: &insn_exec::HartState, log_file: &mut Box<dyn Write>) {
+        let state = &hart_state.updated;
+        if let Some(reg_index) = state.gpr {
+            writeln!(
+                log_file,
+                "\t\t\tx{} = 0x{:08x}",
+                reg_index, hart_state.registers[reg_index]
+            )
+            .expect("Log file write failed");
+        }
+        if let Some(reg_index) = state.wgpr {
+            writeln!(
+                log_file,
+                "\t\t\tw{} = 0x{:064x}",
+                reg_index, hart_state.wregisters[reg_index]
+            )
+            .expect("Log file write failed");
+        }
+        if let Some((wide_reg, reg_addr)) = state.csr {
+            // Output special register written by instruction to log if it wrote to one
+            if !wide_reg {
+                let csr = hart_state.csr_set.get_csr(reg_addr);
+                match csr.unwrap().read() {
+                    Ok(val) => writeln!(
+                        log_file,
+                        "\t\t\tcsr:{} = 0x{:08x}",
+                        csrs::CSRAddr::string_name(reg_addr),
+                        val
+                    ),
+                    Err(exc) => writeln!(
+                        log_file,
+                        "\t\t\tcsr:{} => {:?}",
+                        csrs::CSRAddr::string_name(reg_addr),
+                        exc
+                    ),
+                }
+                .expect("Log file write failed");
+            } else {
+                let wsr = hart_state.csr_set.get_wsr(reg_addr);
+                match wsr.unwrap().read() {
+                    Ok(val) => writeln!(
+                        log_file,
+                        "\t\t\tcsr:{} = 0x{:064x}",
+                        csrs::WSRAddr::string_name(reg_addr),
+                        val
+                    ),
+                    Err(exc) => writeln!(
+                        log_file,
+                        "\t\t\tcsr:{} => {:?}",
+                        csrs::WSRAddr::string_name(reg_addr),
+                        exc
+                    ),
+                }
+                .expect("Log file write failed");
+            }
+        }
+        if let Some((depth, count)) = state.loophead {
+            writeln!(log_file, "\t\t\tloop[{}] = {}", depth, count).expect("Log file write failed");
+        }
+    }
+
+    /// Dump current content of OTBN register (RISC-V and Wide)
+    /// compact: only dump register whose content differ than zero
+    fn dump_hart_state(hart_state: &insn_exec::HartState, compact: bool) {
+        println!();
+
+        if !compact || !hart_state.hwstack.is_empty() {
+            println!("Call Stack:");
+            println!("-----------");
+            for addr in hart_state.hwstack.iter() {
+                println!("0x{:08x}", addr);
+            }
+            println!();
+        }
+
+        println!("Final Base Register Values:");
+        println!("Reg | Value");
+        println!("----------------");
+        for (reg, val) in hart_state.registers[2..].iter().enumerate() {
+            if compact && (*val == 0) {
+                continue;
+            }
+            println!("x{:<2} | 0x{:08x}", reg + 2, val);
+        }
+        println!();
+
+        println!("Final Bignum Register Values:");
+        println!("Reg | Value");
+        println!("-------------------------------------------------------------------------------");
+        for (reg, val) in hart_state.wregisters.iter().enumerate() {
+            if compact && (*val == U256::from(0u32)) {
+                continue;
+            }
+            let mut w: Vec<u32> = Vec::new();
+            let mut val256 = *val;
+            for _ in (0..256).step_by(32) {
+                w.push(val256.as_u32());
+                val256 = val256.wrapping_shr(32);
+            }
+            println!(
+                "w{:<2} | 0x{:08x}_{:08x}_{:08x}_{:08x}_{:08x}_{:08x}_{:08x}_{:08x}",
+                reg, w[7], w[6], w[5], w[4], w[3], w[2], w[1], w[0]
+            );
+        }
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/proxy.rs b/hw/opentitan/otbn/otbn/src/proxy.rs
new file mode 100644
index 0000000000000..42307dd3c14f9
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/proxy.rs
@@ -0,0 +1,573 @@
+// Copyright 2022-2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use std::convert::TryFrom;
+use std::ffi::CStr;
+use std::fs::File;
+use std::io;
+use std::os::raw::{c_char, c_int, c_void};
+use std::slice;
+use std::sync::atomic::Ordering;
+use std::sync::mpsc;
+use std::sync::{Arc, Mutex};
+use std::thread;
+
+use super::comm;
+use super::key;
+use super::memory;
+use super::otbn;
+use super::random;
+use super::Memory;
+
+/// Run from the "main" thread
+pub struct Proxy {
+    /// Instruction memory
+    imem: Arc<Mutex<memory::MemoryRegion>>,
+
+    /// Data memory
+    dmem: Arc<Mutex<memory::MemoryRegion>>,
+
+    /// Shared registers with the core
+    registers: Arc<otbn::Registers>,
+
+    /// Thread handle of the core executer
+    join_handle: Option<thread::JoinHandle<()>>,
+
+    /// Communication channel with the core
+    channel: Option<comm::DownChannel>,
+
+    /// thread identifier of the core runner
+    core_id: Option<thread::ThreadId>,
+
+    /// Pesudo random generator, reseeded from EDN
+    syncurnd: Arc<random::SyncUrnd>,
+
+    /// True random generator from EDN
+    rnd: Arc<random::Rnd>,
+
+    /// Sideload key
+    key: Arc<key::Key>,
+
+    /// Transient optional callback to invoke on completion
+    on_complete: Option<Box<dyn comm::Callback>>,
+}
+
+impl Default for Proxy {
+    fn default() -> Self {
+        Self {
+            imem: Arc::new(Mutex::new(memory::MemoryRegion::new(otbn::IMEM_SIZE))),
+            dmem: Arc::new(Mutex::new(memory::MemoryRegion::new(otbn::DMEM_SIZE))),
+            join_handle: None,
+            channel: None,
+            registers: Arc::new(otbn::Registers::default()),
+            core_id: None,
+            syncurnd: Arc::new(random::SyncUrnd::new()),
+            rnd: Arc::new(random::Rnd::new()),
+            key: Arc::new(key::Key::new()),
+            on_complete: None,
+        }
+    }
+}
+
+impl Proxy {
+    pub fn new() -> Self {
+        Default::default()
+    }
+
+    /// Report the state of the core executer
+    pub fn get_status(&mut self) -> otbn::Status {
+        otbn::Status::from_u32(self.registers.status.load(Ordering::Relaxed))
+    }
+
+    /// Tell the core executer the operation completion has been acknowledged
+    /// All registers are managed by the executer, however with QEMU sycnhronous
+    /// implementation we need a way to defer execution completion to better
+    /// simulate hardware behavior. When an operation is over, it is signalled
+    /// through the C callback (see on_complete), which is then handled at C
+    /// level through a QEMU timer that defer actual completion. The operational
+    /// status of the OTBN core is not changed till this timer is exhausted,
+    /// which gave back execution to the QEMU vCPU where the guest code can poll
+    /// the status of the OTBN registers. Without this hack, the guest code
+    /// would only see the OTBN idle since the executed command would likely
+    /// complete before the vCPU has a chance to get scheduled.
+    pub fn acknowledge_execution(&mut self) -> bool {
+        if self.get_status() == otbn::Status::Locked {
+            return false;
+        }
+        self.registers
+            .status
+            .store(otbn::Status::Idle as u32, Ordering::Relaxed);
+        true
+    }
+
+    /// Register a callback for requesting entropy from EDN
+    pub fn register_entropy_req_cb(
+        &mut self,
+        urnd_entropy_req: Box<dyn comm::Callback>,
+        rnd_entropy_req: Box<dyn comm::Callback>,
+    ) {
+        self.syncurnd.register_entropy_req_cb(urnd_entropy_req);
+        self.rnd.register_entropy_req_cb(rnd_entropy_req);
+    }
+
+    /// Register a callback for signalling a client on completion
+    pub fn register_signal_cb(&mut self, on_complete: Box<dyn comm::Callback>) {
+        self.on_complete = Some(on_complete);
+    }
+
+    /// Kick off the core executer, and create the communication channels
+    pub fn start(&mut self, test_mode: bool, log_name: Option<&str>, log_asm: bool) {
+        if self.core_id.is_some() {
+            // already started, only reset
+            // hartstate is not reset, as it is done after each execution
+            match self.get_status() {
+                otbn::Status::Idle | otbn::Status::Locked => {
+                    let regs = &self.registers;
+                    regs.status
+                        .store(otbn::Status::Idle as u32, Ordering::Relaxed);
+                    regs.err_bits.store(0, Ordering::Relaxed);
+                    regs.fatal_bits.store(0, Ordering::Relaxed);
+                    regs.ctrl.store(false, Ordering::Relaxed);
+                    regs.insn_count.store(0, Ordering::Relaxed);
+                }
+                _ => (),
+            }
+            return;
+        }
+
+        let (cmdtx, cmdrx) = mpsc::channel::<comm::Command>();
+        let (resptx, resprx) = mpsc::channel::<comm::Response>();
+        self.channel = Some((cmdtx, resprx));
+        if self.channel.is_some() {
+            let registers = Arc::clone(&self.registers);
+            let imem = Arc::clone(&self.imem);
+            let dmem = Arc::clone(&self.dmem);
+            let executer = thread::Builder::new().name("otbn_exec".into());
+            let on_complete = self.on_complete.take();
+            let urnd = self.syncurnd.clone();
+            let rnd = Arc::clone(&self.rnd);
+            let key = Arc::clone(&self.key);
+            let log_name: Option<String> = log_name.map(|l| l.into());
+            self.join_handle = Some(
+                executer
+                    .spawn(move || {
+                        otbn::Executer::run(
+                            (cmdrx, resptx),
+                            registers,
+                            imem,
+                            dmem,
+                            urnd,
+                            rnd,
+                            key,
+                            on_complete,
+                            log_name,
+                            log_asm,
+                        )
+                    })
+                    .unwrap(),
+            );
+            self.identify();
+        }
+        self.set_test_mode(test_mode);
+    }
+
+    /// Attach a log file to trace core execution
+    pub fn log_to(&mut self, logfile: Box<io::BufWriter<File>>) {
+        self.check_request();
+        let channel = self.get_channel();
+        channel.0.send(comm::Command::LogTo(logfile)).unwrap();
+        match channel.1.recv().unwrap() {
+            comm::Response::Ack => (),
+            comm::Response::Error(e) => panic!("Error: {}", e),
+            _ => panic!("Unexpected response"),
+        }
+    }
+
+    /// Read one 32-bit from memory
+    fn read_memory(&mut self, doi: bool, addr: u32) -> u32 {
+        match self.get_status() {
+            otbn::Status::Idle => (),
+            otbn::Status::Locked => return 0, // Reads return zero in Locked state
+            _ => {
+                self.registers
+                    .fatal_bits
+                    .fetch_or(otbn::ErrBits::ILLEGAL_BUS_ACCESS.bits(), Ordering::Relaxed);
+                return 0;
+            }
+        }
+
+        let mem = if doi {
+            &self.imem
+        } else {
+            if addr as usize >= otbn::DMEM_PUB_SIZE {
+                return 0;
+            }
+            &self.dmem
+        };
+
+        if let Some(data) = mem.lock().unwrap().read_mem(addr) {
+            data
+        } else {
+            0
+        }
+    }
+
+    /// Write one 32-bit to memory
+    fn write_memory(&mut self, doi: bool, addr: u32, data: u32) -> bool {
+        match self.get_status() {
+            otbn::Status::Idle => (),
+            otbn::Status::Locked => return false, // Writes have no effect in Locked state
+            _ => {
+                self.registers
+                    .fatal_bits
+                    .fetch_or(otbn::ErrBits::ILLEGAL_BUS_ACCESS.bits(), Ordering::Relaxed);
+                return false;
+            }
+        }
+
+        let mem = if doi {
+            &self.imem
+        } else {
+            if addr as usize >= otbn::DMEM_PUB_SIZE {
+                return false;
+            }
+            &self.dmem
+        };
+
+        mem.lock().unwrap().write_mem(addr, data)
+    }
+
+    /// Push a 256-bit entropy buffer
+    pub fn push_entropy(&mut self, rndix: usize, seed: &[u8], fips: bool) -> bool {
+        if seed.len() != 32 {
+            return false;
+        }
+        if let Ok(seed) = <&[u8; 32]>::try_from(seed) {
+            match rndix {
+                /* Pseudo URND */
+                0 => {
+                    self.syncurnd.fill(seed, fips);
+                    /* URND has been reseeded, OTBN engine can now start */
+                }
+                /* Secure RND */
+                1 => self.rnd.fill(seed, fips),
+                _ => return false,
+            }
+            return true;
+        }
+
+        false
+    }
+
+    /// Push a 384-bit key buffer
+    pub fn push_key(&mut self, share0: &[u8], share1: &[u8], valid: bool) -> bool {
+        if share0.len() != 48 && share1.len() != 48 {
+            return false;
+        }
+        if let (Ok(share0), Ok(share1)) =
+            (<&[u8; 48]>::try_from(share0), <&[u8; 48]>::try_from(share1))
+        {
+            self.key.fill(share0, share1, valid);
+            return true;
+        }
+
+        false
+    }
+
+    /// Execute the loaded code
+    pub fn execute(&mut self, dump: bool) -> bool {
+        self.check_request();
+        if self.join_handle.is_some() {
+            let channel = self.get_channel();
+            channel.0.send(comm::Command::Execute(dump)).unwrap();
+            match channel.1.recv().unwrap() {
+                comm::Response::Ack => true,
+                comm::Response::Error(_) => false,
+                _ => panic!("Unexpected response"),
+            }
+        } else {
+            false
+        }
+    }
+
+    /// Wipe memory
+    pub fn wipe_memory(&mut self, doi: bool) -> bool {
+        self.check_request();
+        if self.join_handle.is_some() {
+            let channel = self.get_channel();
+            let command = if doi {
+                comm::Command::WipeIMem
+            } else {
+                comm::Command::WipeDMem
+            };
+            channel.0.send(command).unwrap();
+            match channel.1.recv().unwrap() {
+                comm::Response::Ack => true,
+                comm::Response::Error(_) => false,
+                _ => panic!("Unexpected response"),
+            }
+        } else {
+            false
+        }
+    }
+
+    /// Shutdown the core executer.
+    /// Note: should only be called once, i.e. not for each execution session.
+    pub fn terminate(&mut self) {
+        self.check_request();
+        let channel = self.get_channel();
+        channel.0.send(comm::Command::Terminate).unwrap();
+        match channel.1.recv().unwrap() {
+            comm::Response::Ack => (),
+            comm::Response::Error(e) => panic!("Error: {}", e),
+            _ => panic!("Unexpected response"),
+        }
+        self.join();
+    }
+
+    /// Helper function to use the communication channel w/ the executer
+    fn get_channel(&mut self) -> &mut comm::DownChannel {
+        match &mut self.channel {
+            Some(channel) => channel,
+            // programming error
+            _ => panic!("No communication channel"),
+        }
+    }
+
+    /// Enable test mode (predefined RND values, ...)
+    fn set_test_mode(&mut self, enable: bool) {
+        let channel = self.get_channel();
+        channel.0.send(comm::Command::SetTestMode(enable)).unwrap();
+        match channel.1.recv().unwrap() {
+            comm::Response::Ack => (),
+            comm::Response::Error(e) => panic!("Error: {}", e),
+            _ => panic!("Unexpected response"),
+        }
+    }
+
+    /// Store identification of the runner thread
+    fn identify(&mut self) {
+        let channel = self.get_channel();
+        // runner starts with pushing a message w/o prior solicitation from
+        // the parent, i.e. no explicit command
+        match channel.1.recv().unwrap() {
+            comm::Response::Active(threadid) => self.core_id = Some(threadid),
+            comm::Response::Ack => panic!("Unexpected ack"),
+            comm::Response::Error(e) => panic!("Error: {}", e),
+        }
+    }
+
+    fn check_request(&self) {
+        if let Some(core_id) = self.core_id {
+            if thread::current().id() == core_id {
+                panic!("Command requested from runner thread");
+            }
+        }
+    }
+
+    /// Sync on executer thread completion
+    fn join(&mut self) {
+        self.join_handle.take().map(thread::JoinHandle::join);
+    }
+}
+
+//--------------------------------------------------------------------------------------------------
+// C API
+//--------------------------------------------------------------------------------------------------
+
+type CCallbackArg = *mut c_void;
+type CCallbackFunc = unsafe extern "C" fn(arg: CCallbackArg);
+
+/// Proxy callback for C implementation
+pub struct CCallback {
+    /// C callback
+    cb: CCallbackFunc,
+    /// optional argument to the C callback, default to C NULL
+    arg: Arc<Mutex<CCallbackArg>>,
+}
+
+impl CCallback {
+    pub fn new(cb: CCallbackFunc, arg: CCallbackArg) -> Self {
+        Self {
+            cb,
+            arg: Arc::new(Mutex::new(arg)),
+        }
+    }
+}
+
+unsafe impl Send for CCallback {}
+
+impl comm::Callback for CCallback {
+    fn signal(&mut self) {
+        unsafe {
+            (self.cb)(*self.arg.lock().unwrap());
+        }
+    }
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_new(
+    urnd_entropy_req: CCallbackFunc,
+    urnd_opaque: CCallbackArg,
+    rnd_entropy_req: CCallbackFunc,
+    rnd_opaque: CCallbackArg,
+    on_complete: CCallbackFunc,
+    on_comp_opaque: CCallbackArg,
+) -> Box<Proxy> {
+    let mut proxy = Box::new(Proxy::new());
+    proxy.register_entropy_req_cb(
+        Box::new(CCallback::new(urnd_entropy_req, urnd_opaque)),
+        Box::new(CCallback::new(rnd_entropy_req, rnd_opaque)),
+    );
+    proxy.register_signal_cb(Box::new(CCallback::new(on_complete, on_comp_opaque)));
+    proxy
+}
+
+/// # Safety
+#[no_mangle]
+pub unsafe extern "C" fn ot_otbn_proxy_start(
+    proxy: Option<&mut Proxy>,
+    test_mode: bool,
+    log_name: *const c_char,
+    log_asm: bool,
+) {
+    let log_name: Option<&str> = if !log_name.is_null() {
+        Some(CStr::from_ptr(log_name).to_str().unwrap())
+    } else {
+        None
+    };
+    proxy.unwrap().start(test_mode, log_name, log_asm);
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_terminate(proxy: Option<&mut Proxy>) {
+    proxy.unwrap().terminate();
+}
+
+/// # Safety
+#[no_mangle]
+pub unsafe extern "C" fn ot_otbn_proxy_push_entropy(
+    proxy: Option<&mut Proxy>,
+    rndix: u32,
+    seed: *const u8,
+    len: u32,
+    fips: bool,
+) -> bool {
+    assert!(!seed.is_null());
+    let rust_seed = slice::from_raw_parts(seed, len as usize);
+    proxy.unwrap().push_entropy(rndix as usize, rust_seed, fips)
+}
+
+/// # Safety
+#[no_mangle]
+pub unsafe extern "C" fn ot_otbn_proxy_push_key(
+    proxy: Option<&mut Proxy>,
+    share0: *const u8,
+    share1: *const u8,
+    len: u32,
+    valid: bool,
+) -> bool {
+    assert!(!share0.is_null());
+    assert!(!share1.is_null());
+    let rust_share0 = slice::from_raw_parts(share0, len as usize);
+    let rust_share1 = slice::from_raw_parts(share1, len as usize);
+    proxy.unwrap().push_key(rust_share0, rust_share1, valid)
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_execute(proxy: Option<&mut Proxy>, dump: bool) -> c_int {
+    if proxy.unwrap().execute(dump) {
+        0
+    } else {
+        -1
+    }
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_wipe_memory(proxy: Option<&mut Proxy>, doi: bool) -> c_int {
+    if proxy.unwrap().wipe_memory(doi) {
+        0
+    } else {
+        -1
+    }
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_acknowledge_execution(proxy: Option<&mut Proxy>) -> bool {
+    proxy.unwrap().acknowledge_execution()
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_read_memory(
+    proxy: Option<&mut Proxy>,
+    doi: bool,
+    addr: u32,
+) -> u32 {
+    proxy.unwrap().read_memory(doi, addr)
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_write_memory(
+    proxy: Option<&mut Proxy>,
+    doi: bool,
+    addr: u32,
+    val: u32,
+) -> bool {
+    proxy.unwrap().write_memory(doi, addr, val)
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_get_status(proxy: Option<&mut Proxy>) -> c_int {
+    proxy.unwrap().get_status() as c_int
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_get_instruction_count(proxy: Option<&mut Proxy>) -> u32 {
+    let proxy = proxy.unwrap();
+    if proxy.get_status() != otbn::Status::Locked {
+        proxy.registers.insn_count.load(Ordering::Relaxed) as u32
+    } else {
+        0
+    }
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_set_instruction_count(proxy: Option<&mut Proxy>, value: u32) {
+    let proxy = proxy.unwrap();
+    if proxy.get_status() == otbn::Status::Idle {
+        proxy
+            .registers
+            .insn_count
+            .store(value as usize, Ordering::Relaxed)
+    }
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_get_err_bits(proxy: Option<&mut Proxy>) -> u32 {
+    proxy.unwrap().registers.err_bits.load(Ordering::Relaxed)
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_set_err_bits(proxy: Option<&mut Proxy>, value: u32) {
+    let proxy = proxy.unwrap();
+    if proxy.get_status() == otbn::Status::Idle {
+        proxy.registers.err_bits.store(
+            otbn::ErrBits::from_bits_truncate(value).bits(),
+            Ordering::Relaxed,
+        )
+    }
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_get_ctrl(proxy: Option<&mut Proxy>) -> bool {
+    proxy.unwrap().registers.ctrl.load(Ordering::Relaxed)
+}
+
+#[no_mangle]
+pub extern "C" fn ot_otbn_proxy_set_ctrl(proxy: Option<&mut Proxy>, value: bool) {
+    let proxy = proxy.unwrap();
+    if proxy.get_status() == otbn::Status::Idle {
+        proxy.registers.ctrl.store(value, Ordering::Relaxed)
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/random.rs b/hw/opentitan/otbn/otbn/src/random.rs
new file mode 100644
index 0000000000000..71c290ae842c9
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/random.rs
@@ -0,0 +1,213 @@
+// Copyright 2023 Rivos, Inc.
+// Licensed under the Apache License Version 2.0, with LLVM Exceptions, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+use std::sync::{Arc, Condvar, Mutex};
+use std::time::Duration;
+
+use ethnum::{u256, U256};
+
+use super::comm;
+use super::xoshiro256pp::Xoshiro256PlusPlus;
+use crate::{CSRNG, PRNG};
+
+#[derive(Default)]
+pub struct RndCache {
+    value: u256,
+    available: bool,
+    fips: bool,
+    repeat: bool,
+}
+
+pub struct Rnd {
+    cache: Mutex<RndCache>,
+    wait: Condvar,
+    entropy_req: Mutex<Option<Box<dyn comm::Callback>>>,
+}
+
+impl Default for Rnd {
+    fn default() -> Self {
+        let cache = RndCache::default();
+        Self {
+            cache: Mutex::new(cache),
+            wait: Condvar::new(),
+            entropy_req: Mutex::new(None),
+        }
+    }
+}
+
+impl Rnd {
+    pub fn new() -> Self {
+        Self::default()
+    }
+
+    pub fn register_entropy_req_cb(&self, entropy_req: Box<dyn comm::Callback>) {
+        let mut func = self.entropy_req.lock().unwrap();
+        *func = Some(entropy_req);
+    }
+
+    pub fn clear(&mut self) {
+        /* called from OTBN proxy */
+        let mut cache = self.cache.lock().unwrap();
+        cache.value = U256::from(0u32);
+        cache.available = false;
+        cache.fips = false;
+        cache.repeat = false;
+    }
+
+    pub fn fill(&self, values: &[u8; 32], fips: bool) {
+        /* called from OTBN proxy */
+        let val = U256::from_le_bytes(*values);
+        let mut cache = self.cache.lock().unwrap();
+        cache.repeat = cache.value == val;
+        cache.value = val;
+        cache.available = true;
+        cache.fips = fips;
+        self.wait.notify_one();
+    }
+
+    pub fn prefetch(&self) {
+        /* called from OTBN processor (CSR) */
+        let cache = self.cache.lock().unwrap();
+        if cache.available {
+            /* cache is already loaded, nothing to do */
+            return;
+        }
+        self.fetch();
+    }
+
+    fn fetch(&self) {
+        let mut func = self.entropy_req.lock().unwrap();
+        if let Some(req) = &mut *func {
+            req.signal();
+        }
+    }
+}
+
+impl CSRNG for Rnd {
+    fn get_csrng_u32(&self) -> (u32, bool, bool) {
+        // "A read from the RND CSR returns the bottom 32b; the other 192b are discarded."
+        let (val, fips, repeat) = self.get_csrng_u256();
+        (val.as_u32(), fips, repeat)
+    }
+
+    fn get_csrng_u256(&self) -> (u256, bool, bool) {
+        let mut cache = self.cache.lock().unwrap();
+        let mut fetch = false;
+        loop {
+            let result = self
+                .wait
+                .wait_timeout(cache, Duration::from_millis(50))
+                .unwrap();
+            cache = result.0;
+            if cache.available {
+                break;
+            }
+            if !fetch {
+                self.fetch();
+                fetch = true;
+            }
+        }
+
+        let (val, fips, repeat) = (cache.value, cache.fips, cache.repeat);
+        cache.available = false;
+        cache.fips = false;
+        cache.repeat = false;
+        (val, fips, repeat)
+    }
+}
+
+#[derive(Default)]
+pub struct Urnd {
+    xoshiro: Xoshiro256PlusPlus,
+}
+
+impl PRNG for Urnd {
+    fn get_prng_u32(&mut self) -> u32 {
+        self.xoshiro.next_u32()
+    }
+
+    fn get_prng_u64(&mut self) -> u64 {
+        self.xoshiro.next_u64()
+    }
+
+    fn get_prng_u256(&mut self) -> u256 {
+        self.xoshiro.next_u256()
+    }
+}
+
+impl Urnd {
+    pub fn new() -> Self {
+        Self::default()
+    }
+
+    pub fn reseed(&mut self, seed: [u8; 32]) {
+        self.xoshiro.reseed(seed)
+    }
+}
+
+pub struct SyncUrnd {
+    urnd: Arc<Mutex<Urnd>>,
+    sync: Mutex<bool>,
+    wait: Condvar,
+    entropy_req: Mutex<Option<Box<dyn comm::Callback>>>,
+}
+
+impl Default for SyncUrnd {
+    fn default() -> Self {
+        Self {
+            sync: Mutex::new(false),
+            wait: Condvar::new(),
+            urnd: Arc::new(Mutex::new(Urnd::default())),
+            entropy_req: Mutex::new(None),
+        }
+    }
+}
+
+impl SyncUrnd {
+    pub fn new() -> Self {
+        Self::default()
+    }
+
+    pub fn register_entropy_req_cb(&self, entropy_req: Box<dyn comm::Callback>) {
+        let mut func = self.entropy_req.lock().unwrap();
+        *func = Some(entropy_req);
+    }
+
+    pub fn urnd(&self) -> Arc<Mutex<Urnd>> {
+        self.urnd.clone()
+    }
+
+    pub fn request_reseed(&self) {
+        let mut func = self.entropy_req.lock().unwrap();
+        if let Some(req) = &mut *func {
+            req.signal();
+        }
+    }
+
+    pub fn wait_reseed(&self) {
+        loop {
+            let sync = self.sync.lock().unwrap();
+            let mut go = self
+                .wait
+                .wait_timeout(sync, Duration::from_millis(5))
+                .unwrap();
+            if *go.0 {
+                *go.0 = false;
+                break;
+            }
+        }
+    }
+
+    pub fn sync_reseed(&self) {
+        self.request_reseed();
+        self.wait_reseed();
+    }
+
+    pub fn fill(&self, seed: &[u8; 32], _fips: bool) {
+        /* should fips be validated for URND? */
+        self.urnd.lock().unwrap().reseed(*seed);
+        *self.sync.lock().unwrap() = true;
+        self.wait.notify_one();
+    }
+}
diff --git a/hw/opentitan/otbn/otbn/src/xoshiro256pp.rs b/hw/opentitan/otbn/otbn/src/xoshiro256pp.rs
new file mode 100644
index 0000000000000..6d4842a4469de
--- /dev/null
+++ b/hw/opentitan/otbn/otbn/src/xoshiro256pp.rs
@@ -0,0 +1,123 @@
+// Copyright 2018 Developers of the Rand project.
+//
+// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
+// https://www.apache.org/licenses/LICENSE-2.0> or the MIT license
+// <LICENSE-MIT or https://opensource.org/licenses/MIT>, at your
+// option. This file may not be copied, modified, or distributed
+// except according to those terms.
+
+use std::convert::TryInto;
+
+use ethnum::{u256, U256};
+
+/// A xoshiro256++ random number generator.
+///
+/// The xoshiro256++ algorithm is not suitable for cryptographic purposes, but
+/// is very fast and has excellent statistical properties.
+///
+/// The algorithm used here is translated from [the `xoshiro256plusplus.c`
+/// reference source code](http://xoshiro.di.unimi.it/xoshiro256plusplus.c) by
+/// David Blackman and Sebastiano Vigna.
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct Xoshiro256PlusPlus {
+    s: [u64; 4],
+}
+
+/// Reads unsigned 64 bit integers from `src` into `dst`.
+#[inline]
+pub fn read_u64_into(src: &[u8], dst: &mut [u64]) {
+    assert!(src.len() >= 8 * dst.len());
+    for (out, chunk) in dst.iter_mut().zip(src.chunks_exact(8)) {
+        *out = u64::from_le_bytes(chunk.try_into().unwrap());
+    }
+}
+
+impl Default for Xoshiro256PlusPlus {
+    /// Create a new `Xoshiro256PlusPlus`.
+    fn default() -> Self {
+        // the generator is *not* initialized here.
+        Xoshiro256PlusPlus::from_seed([0u8; 32])
+    }
+}
+
+impl Xoshiro256PlusPlus {
+    #[inline]
+    pub fn from_seed(seed: [u8; 32]) -> Xoshiro256PlusPlus {
+        let mut state = [0; 4];
+        read_u64_into(&seed, &mut state);
+        Xoshiro256PlusPlus { s: state }
+    }
+
+    pub fn reseed(&mut self, seed: [u8; 32]) {
+        let mut state = [0; 4];
+        read_u64_into(&seed, &mut state);
+        self.s = state;
+    }
+
+    #[inline]
+    pub fn next_u32(&mut self) -> u32 {
+        // The lowest bits have some linear dependencies, so we use the
+        // upper bits instead.
+        (self.next_u64() >> 32) as u32
+    }
+
+    #[inline]
+    pub fn next_u64(&mut self) -> u64 {
+        let result_plusplus = self.s[0]
+            .wrapping_add(self.s[3])
+            .rotate_left(23)
+            .wrapping_add(self.s[0]);
+
+        let t = self.s[1] << 17;
+
+        self.s[2] ^= self.s[0];
+        self.s[3] ^= self.s[1];
+        self.s[1] ^= self.s[2];
+        self.s[0] ^= self.s[3];
+
+        self.s[2] ^= t;
+
+        self.s[3] = self.s[3].rotate_left(45);
+
+        result_plusplus
+    }
+
+    pub fn next_u256(&mut self) -> u256 {
+        let mut val = U256::from(0u32);
+        for _ in 0..4 {
+            val = val.wrapping_shl(64);
+            val |= U256::from(self.next_u64());
+        }
+        val
+    }
+
+    /// Implement `fill_bytes` via `next_u64` and `next_u32`, little-endian order.
+    ///
+    /// The fastest way to fill a slice is usually to work as long as possible with
+    /// integers. That is why this method mostly uses `next_u64`, and only when
+    /// there are 4 or less bytes remaining at the end of the slice it uses
+    /// `next_u32` once.
+    pub fn fill_bytes_via_next(&mut self, dest: &mut [u8]) {
+        let mut left = dest;
+        while left.len() >= 8 {
+            let (l, r) = { left }.split_at_mut(8);
+            left = r;
+            let chunk: [u8; 8] = self.next_u64().to_le_bytes();
+            l.copy_from_slice(&chunk);
+        }
+        let n = left.len();
+        if n > 4 {
+            let chunk: [u8; 8] = self.next_u64().to_le_bytes();
+            left.copy_from_slice(&chunk[..n]);
+        } else if n > 0 {
+            let chunk: [u8; 4] = self.next_u32().to_le_bytes();
+            left.copy_from_slice(&chunk[..n]);
+        }
+    }
+
+    #[inline]
+    pub fn fill_bytes(&mut self, dest: &mut [u8]) {
+        self.fill_bytes_via_next(dest);
+    }
+}
diff --git a/hw/opentitan/trace-events b/hw/opentitan/trace-events
new file mode 100644
index 0000000000000..8bcc0a1715edf
--- /dev/null
+++ b/hw/opentitan/trace-events
@@ -0,0 +1,693 @@
+# OpenTitan EarlGrey Trace Events
+
+# ot_aes.c
+
+ot_aes_buffer(const char *id, const char *mode, const char * msg, const char * hexbuf) "%s: [%s] %s: %s"
+ot_aes_debug(const char *func, int line, const char *id, const char *msg) "%s:%d %s: %s"
+ot_aes_error(const char *func, int line, const char *id, const char *err) "%s:%d %s: %s"
+ot_aes_fill_entropy(const char *id, uint32_t bits, bool fips) "%s: 0x%08x fips:%u"
+ot_aes_info(const char *func, int line, const char *id, const char *errl) "%s:%d %s: %s"
+ot_aes_init(const char *id, const char *what) "%s: %s"
+ot_aes_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_aes_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_aes_request_entropy(const char *id) "%s"
+ot_aes_reseed(const char *id, const char *reason) "%s: %s"
+ot_aes_reseed_rate(const char *id, unsigned rate) "%s: %u"
+ot_aes_schedule(const char *id) "%s"
+
+# ot_alert.c
+
+ot_alert_cancel_timeout(const char *id, char cls) "%s: class %c"
+ot_alert_error(const char *id, char cls, const char *msg) "%s: class %c: %s"
+ot_alert_esc_count(const char *id, char cls, const char *st, uint32_t cnt) "%s: class %c [%s] %u cycles"
+ot_alert_escalation(const char *id, char cls, unsigned esc, const char *msg) "%s: class %c esc %u %s"
+ot_alert_fsm_update(const char *id, char cls, const char *st, bool timer, bool atrig) "%s: class %c [%s] timer %u atrig %u"
+ot_alert_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%01x msk:0x%01x eff:0x%01x"
+ot_alert_timer_expire(const char *id, char cls) "%s: class %c"
+ot_alert_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_alert_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_alert_set_class_state(const char *id, char cls, const char *ost, const char *nst) "%s: class %c [%s] -> [%s]"
+ot_alert_set_class_timer(const char *id, char cls, const char *st, uint64_t us, uint32_t cycles) "%s: class %c [%s] %" PRIu64 " us (%u cycles)"
+ot_alert_signal_class(const char *id, unsigned alert, char cls, bool class_en) "%s: alert:%u -> class %c enabled:%u"
+ot_alert_signal_tx(const char *id, unsigned n, bool level, bool alert_en) "%s: alert:%u level:%u enabled:%u"
+ot_alert_skip_active(const char *id, char cls, const char *stname) "%s: class %c %s"
+
+# ot_aon_timer.c
+
+ot_aon_timer_irqs(const char *id, bool wakeup, bool bark, bool bite) "%s: wkup:%u bark:%u bite:%u"
+ot_aon_timer_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_aon_timer_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_aon_timer_reset(const char *id, const char *action) "%s: %s"
+ot_aon_timer_set_wdog(const char *id, int64_t now, int64_t next) "%s: now %" PRId64 ", next %" PRId64
+ot_aon_timer_update_clock(const char *id, int tid, uint32_t frequency) "%s: [%d] @ %u Hz"
+
+# ot_ast.c
+
+ot_ast_create_clock(const char *clock, unsigned frequency, const char *out) "%s @ %u Hz, out: %s"
+ot_ast_io_read_out(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_ast_io_write(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_ast_no_entropy(unsigned count) "only %u words available"
+ot_ast_upate_clock(const char *clock, unsigned frequency) "%s @ %u Hz"
+
+# ot_clkmgr.c
+
+ot_clkmgr_add_group(const char *id, const char *clock, const char *group) "%s: %s added to %s"
+ot_clkmgr_clock_hint(const char *id, const char *name, unsigned clock, bool active) "%s: %s(%u): %u"
+ot_clkmgr_clock_input(const char *id, const char *name, unsigned frequency) "%s: %s: %u Hz"
+ot_clkmgr_connect_input_clock(const char *id, const char * srcname, unsigned cix) "%s: %s -> clock-in[%u]"
+ot_clkmgr_create(const char *id, const char *what, const char *name) "%s: %s: %s"
+ot_clkmgr_get_clock_hints(const char *id, uint32_t req, uint32_t status, uint32_t hint) "%s: req:0x%02x clk:0x%02x hint:0x%02x"
+ot_clkmgr_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_clkmgr_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_clkmgr_define_meas(const char *id, unsigned ix, const char *name) "%s: [%u]: %s"
+ot_clkmgr_define_swcg(const char *id, unsigned ix, const char *name) "%s: [%u]: %s"
+ot_clkmgr_register_sink(const char *id, const char *irqname, const char *devtype, const char *devid) "%s: %s -> %s:%s"
+ot_clkmgr_reset_meas(const char *id, unsigned ix, const char *clkname, unsigned lo, unsigned hi) "%s: [%u] %s [%u..%u]"
+ot_clkmgr_update_clock(const char *id, const char *clock, unsigned frequency) "%s: %s @ %u Hz"
+ot_clkmgr_update_sink(const char *id, const char *irqname, unsigned frequency) "%s: %s -> %u Hz"
+
+# ot_common.c
+
+ot_common_configure_device_bool(const char *objid, const char *key, bool val) "%s: %s= %u"
+ot_common_configure_device_str(const char *objid, const char *key, const char *val) "%s: %s= %s"
+ot_common_configure_device_uint(const char *objid, const char *key, uint64_t val) "%s: %s= %" PRIx64
+
+# ot_csrng.c
+
+ot_csrng_change_state(int line, const char *old, int nold, const char *new, int nnew) "@ %d [%s:%d] -> [%s:%d]"
+ot_csrng_command_scheduler(unsigned slot, const char *action) "#%u: %s"
+ot_csrng_complete_command(unsigned slot, const char *kind, const char *cmd, unsigned acmd, int res) "#%u (%s) acmd: %s(%u): %d"
+ot_csrng_connection(unsigned slot, bool newc) "#%u new:%u"
+ot_csrng_defer_generation(unsigned slot) "#%u instanciation not yet completed"
+ot_csrng_disconnection(unsigned slot, bool explicit) "#%u explicit:%u"
+ot_csrng_end_of_gen(unsigned slot, unsigned rempack) "#%u rem %u"
+ot_csrng_entropy_injecter(unsigned slot, const char *action) "#%u: %s"
+ot_csrng_entropy_rejected(unsigned slot, const char *reason, int res) "#%u: %s (%d)"
+ot_csrng_error(const char *func, int line, const char *err) "%s:%d %s"
+ot_csrng_fill_entropy(unsigned slot, bool fips) "#%u fips %u"
+ot_csrng_generate(unsigned slot, unsigned count) "#%u %u packets to generate"
+ot_csrng_hwapp_need_entropy(unsigned slot, const char *msg) "#%u: %s"
+ot_csrng_hwapp_ready(unsigned slot, bool ready, unsigned rem) "#%u: %u rem %u"
+ot_csrng_info(const char *func, int line, const char *msg, uint32_t value) "%s:%d %s: 0x%08x"
+ot_csrng_instantiate(unsigned slot) "#%u"
+ot_csrng_invalid_state(const char *func, const char *state, int st) "%s [%s:%d]"
+ot_csrng_io_read_out(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_csrng_io_write(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_csrng_irqs(uint32_t active, uint32_t mask, uint32_t eff) "act:0x%1x msk:0x%1x eff:0x%1x"
+ot_csrng_push_command(unsigned slot, const char *cmd, unsigned acmd, char code, unsigned len) "#%u: %s(%u) %clen: %u"
+ot_csrng_read_state_db(unsigned slot, unsigned pos, uint32_t val) "#%u [%u] = 0x%08x"
+ot_csrng_reject_command(unsigned slot, uint32_t command, int res) "#%u: cmd: 0x%08x res: %d"
+ot_csrng_request_entropy(unsigned slot) "#%u"
+ot_csrng_reset(void) ""
+ot_csrng_retry_es_init(unsigned retry_count) "rescheduling initial ES request: %u to go"
+ot_csrng_schedule(unsigned slot, const char *kind) "#%u: %s"
+ot_csrng_scheduling_command(unsigned slot) "#%u"
+ot_csrng_show_buffer(const char *func, int line, unsigned appid, const char *msg, const char *hexstr) "%s:%u #%u %s: %s"
+ot_csrng_show_command(const char *msg, unsigned slot, const char *cmd, unsigned acmd) "%s slot #%u, acmd: %s(%u)"
+ot_csrng_swapp_fill(unsigned count) "%u to go"
+ot_csrng_try_schedule_genbits(unsigned slot, bool ready, bool queued, unsigned rem) "? #%u rdy:%u q:%u rem:%u"
+ot_csrng_uninstantiate(unsigned slot, bool explicit) "#%u explicit:%u"
+
+# ot_dev_proxy.c
+
+ot_dev_proxy_dispatch_request(char a, char b) "%c%c"
+ot_dev_proxy_fe_error(int err) "error: %d"
+ot_dev_proxy_intercept_irq(const char *dname, const char *did, const char *iid, bool enable) "%s (%s) %s: enable %u"
+ot_dev_proxy_read_buffer(const char *desc, bool mbx, unsigned offset, unsigned count) "%s mbx:%u 0x%02x %u"
+ot_dev_proxy_read_memory(const char *desc, unsigned offset, unsigned count) "%s 0x%08x 0x%x"
+ot_dev_proxy_read_reg(const char *desc, unsigned offset) "%s 0x%08x"
+ot_dev_proxy_route_irq(const char *dname, const char *did, unsigned irq, int level) "%s (%s) %u: level %d"
+ot_dev_proxy_signal_irq(const char *dname, const char *did, unsigned irq, int level) "%s (%s) %u: level %d"
+ot_dev_proxy_uid_error(const char *msg, unsigned expuid, unsigned realuid) "%s: expected %u, received %u"
+ot_dev_proxy_unassigned_irq(int irq) "%d non-assigned intercepted IRQ signaled"
+ot_dev_proxy_write_buffer(const char *desc, bool mbx, unsigned offset, unsigned count) "%s mbx:%u 0x%02x %u"
+ot_dev_proxy_write_memory(const char *desc, unsigned offset, unsigned count) "%s 0x%08x 0x%x"
+ot_dev_proxy_write_reg(const char *desc, unsigned offset, unsigned value) "%s 0x%08x 0x%08x"
+
+# ot_dm_tl.c
+
+ot_dm_tl_capture(const char *devname, uint32_t addr, uint32_t value) "%s: @ 0x%x: 0x%08x"
+ot_dm_tl_dtm_not_available(const char *devname) "%s"
+ot_dm_tl_invalid_addr(const char *devname, uint32_t addr) "%s: 0x%x"
+ot_dm_tl_register(const char *devname, uint32_t addr, unsigned size, bool enable, bool ok) "%s: @ 0x%04x l:0x%x en:%u -> %u"
+ot_dm_tl_update(const char *devname, uint32_t addr, uint32_t value, const char *msg, uint32_t res) "%s @ 0x%x: 0x%x (%s): %u"
+
+# ot_dma.c
+
+ot_dma_abort(const char *id) "%s"
+ot_dma_change_state(const char *id, int line, const char *state, int stateval) "%s: @%d: %s [%d]"
+ot_dma_check_device(const char *id, const char *dir, const char *asname, uint64_t addr, uint64_t size, const char *rootname, bool ram) "%s: %s as=%s addr=0x%" PRIx64 " size:0x%" PRIx64 " %s ram:%u"
+ot_dma_complete(const char *id, int res) "%s: %d"
+ot_dma_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_dma_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_dma_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%01x msk:0x%01x eff:0x%01x"
+ot_dma_new_op(const char *id, const char *dir, const char *asname, const char *mname, uint64_t addr, uint64_t size) "%s: %s as:%s m:%s a:0x%" PRIx64 " s:0x%" PRIx64
+ot_dma_operation(const char *op, bool init) "%s: %u"
+ot_dma_set_error(const char *id, const char *func, int line, unsigned err) "%s: %s:%d err:%u"
+ot_dma_transfer(const char *id, const char *dir, const char *asname, uint64_t addr, uint64_t size) "%s: %s as=%s addr=0x%" PRIx64 " size:0x%" PRIx64
+
+# ot_edn.c
+
+ot_edn_auto_dispatch(unsigned appid, bool auto_, unsigned max_reqs_cnt) "a#%u auto:%u max_reqs_cnt:%u"
+ot_edn_clean_up(unsigned appid, bool discard) "a#%u discard:%u"
+ot_edn_change_state(unsigned appid, int line, const char *old, int nold, const char *new, int nnew) "a#%u @ %d [%s:%d] -> [%s:%d]"
+ot_edn_connect_endpoint(unsigned appid, unsigned epid) "a#%u:e#%u"
+ot_edn_csrng_ack(unsigned appid, const char *state, int level) "a#%u %s %d"
+ot_edn_ctrl_in_state(unsigned appid, const char *state, int nstate, bool en, bool boot, bool auto_, bool clr, bool dis) "a#%u [%s:%d] en:%u boot:%u auto:%u clr:%u dis:%u"
+ot_edn_delay_mode_change(unsigned appid, const char *state, uint32_t ctrl) "a#%u %s ctrl:0x%08x"
+ot_edn_dinfo(unsigned appid, const char *func, int line, const char *msg, uint32_t value) "a#%u %s:%d %s %u"
+ot_edn_enable(unsigned appid, const char *msg) "a#%u: %s"
+ot_edn_ep_fifo(unsigned appid, const char *msg, unsigned remwslot) "a#%u %s rem:%u"
+ot_edn_ep_request(unsigned appid, bool avail, const char *state, int st, bool refill, unsigned rem) "a#%u avail %u, [%s:%d], refill %u, rem %u"
+ot_edn_error(unsigned appid, const char *func, int line, const char *err) "a#%u %s:%d %s"
+ot_edn_fill_bits(unsigned appid, unsigned rem, bool packet_fips, bool fips) "a#%u rem %u, fips %u/%u"
+ot_edn_fill_endpoint(unsigned appid, unsigned epid, uint32_t bits, bool fips, size_t gcnt, size_t tcnt) "a#%u:e#%u bits 0x%08x fips %u count %lu/%lu"
+ot_edn_handle_ep_request(unsigned appid, unsigned epid) "a#%u:e#%u"
+ot_edn_invalid_state(unsigned appid, const char *func, const char *state, int st) "a#%u %s [%s:%d]"
+ot_edn_io_read_out(unsigned appid, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "a#%u addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_edn_io_write(unsigned appid, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "a#%u addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_edn_irqs(unsigned appid, uint32_t active, uint32_t mask, uint32_t eff) "a#%u act:0x%08x msk:0x%08x eff:0x%08x"
+ot_edn_push_csrng_command(unsigned appid,  const char *mode, uint32_t value) "a#%u (%s) cmd:0x%08x"
+ot_edn_push_csrng_error(unsigned appid, int res) "a#%u res:%d"
+ot_edn_request_entropy(unsigned appid, unsigned epid) "a#%u:e#%u"
+ot_edn_reset(unsigned appid, const char *phase) "a#%u %s"
+ot_edn_reset_replay_fifos(unsigned appid) "a#%u"
+ot_edn_schedule(unsigned appid, const char *cause) "a#%u %s"
+ot_edn_update_genbits_ready(unsigned appid, unsigned rem, unsigned fslot, bool accept) "a#%u rem packet %u, free slot %u, accept? %u"
+ot_edn_xinfo(unsigned appid, const char *func, int line, const char *msg, uint32_t value) "a#%u %s:%d %s 0x%08x"
+
+# ot_eg_pad_ring.c
+ot_eg_pad_ring_reset(const char *id, const char *stage) "%s: %s"
+ot_eg_pad_ring_reset_value(const char *id, const char *pad, char lvl) "%s: pad %s {%c}"
+
+# ot_entropy_src.c
+
+ot_entropy_src_available(const char *id, const char *state, int st) "%s: entropy source is ready in [%s:%u]"
+ot_entropy_src_change_state(const char *id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_entropy_src_consume_entropy(const char *id, bool obs_fifo, bool bypass, bool hw_path, unsigned ncount) "%s: obs_fifo %u, bypass %u, hw_path %u ncount %u"
+ot_entropy_src_error(const char *id, const char *msg, const char *state, int st) "%s: %s [%s:%u]"
+ot_entropy_src_fill_noise(const char *id, unsigned count, unsigned infifo) "%s: up to %u, input fifo %u"
+ot_entropy_src_get_random_fips(const char *id, const char *state, bool en, bool es_route, bool es_type, bool rng_bit_en, bool cap, bool comp, bool fips) "%s: st:%s en:%u rt:%u tp:%u !rb:%u cap:%u comp:%u => %u"
+ot_entropy_src_info(const char *id, const char *msg) "%s: %s"
+ot_entropy_src_init_ongoing(const char *id, const char *state, int st, int ns) "%s: ES still initializing in [%s:%u] %d ns to go"
+ot_entropy_src_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_entropy_src_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_entropy_src_no_entropy(const char *id, unsigned count) "%s: only %u words available"
+ot_entropy_src_obs_fifo(const char *id, unsigned level, unsigned thold) "%s: level %u, threshold %u"
+ot_entropy_src_push_bypass_entropy(const char *id, unsigned slot) "%s: final FIFO depth: %u"
+ot_entropy_src_reset(const char *id, const char *phase) "%s: %s"
+ot_entropy_src_show_buffer(const char *id, const char *func, int line, const char *msg, const char *hexstr) "%s: %s:%u %s: %s"
+ot_entropy_src_update_filler(const char *id, bool iok, bool ook, bool pok, bool all) "%s: in %u, out %u, proc %u -> %u"
+
+# ot_flash.c
+
+ot_flash_change_lc_phase(const char *id, const char *phase, int nphase) "%s: [%s:%d]"
+ot_flash_data_part(const char *id, unsigned op_addr, unsigned count, unsigned remaining, unsigned bank, unsigned addr) "%s: op_addr 0x%06x count %u remaining %u bank %u addr 0x%06x"
+ot_flash_erase(const char *id, bool info_part, unsigned word_addr, unsigned num_bytes) "%s: info_part %u word_addr %u num_bytes %u"
+ot_flash_error(const char *id, const char *func, int line, const char *err) "%s: %s:%d %s"
+ot_flash_get_keymgr_secret(const char *id, const char *name, unsigned type) "%s: %s [%d]"
+ot_flash_info(const char *id, const char *func, int line, const char *msg, uint32_t value) "%s: %s:%d %s: 0x%08x"
+ot_flash_info_part(const char* id, unsigned op_addr, unsigned count, unsigned remaining, unsigned bank, unsigned infosel, unsigned addr) "%s: op_addr 0x%06x count %u remaining %u bank %u infosel %u addr 0x%06x"
+ot_flash_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_flash_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_flash_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%08x msk:0x%08x eff:0x%08x"
+ot_flash_lc_broadcast(const char* id, unsigned sig, bool level) "%s: bcast %u, level %u"
+ot_flash_mem_read_out(const char* id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%u), val=0x%08x, pc=0x%x"
+ot_flash_merge_info_qual(const char* id, unsigned bank, unsigned infosel, unsigned page, uint8_t reg_cfg, uint8_t qual, uint8_t merged) "%s: bank:%u infosel:%u page:%u, reg_cfg:0x%02x & qual:0x%02x = 0x%02x"
+ot_flash_op_complete(const char* id, const char *op, bool hw, bool success) "%s: %s (hw=%u): %u"
+ot_flash_op_execute(const char* id, const char *op, bool hw) "%s: %s (hw=%u)"
+ot_flash_op_prog(const char* id, unsigned op_addr, unsigned count, unsigned remaining, bool failed, bool fifo_empty) "%s: op_addr 0x%06x count %u remaining %u failed %u fifo_empty %u"
+ot_flash_op_start(const char* id, const char *op, bool hw) "%s: %s (hw=%u)"
+ot_flash_prog_word(const char* id, bool info_part, unsigned word_addr, uint32_t word) "%s: info_part %u word_addr %u word %u"
+ot_flash_read_keymgr_seed(const char* id, unsigned page, bool success, const char *seed) "%s: page:%u, success:%u, seed:%s"
+ot_flash_reset(const char *id, const char *phase) "%s: %s"
+ot_flash_reset_fifo(const char* id, const char *name) "%s: %s"
+ot_flash_set_error(const char* id, const char *op, bool hw, uint32_t err_code, uint32_t err_addr) "%s: %s (hw=%u): err=0x%08x at addr=0x%06x"
+ot_flash_update_alert(const char* id, int prev, int next) "%s: %d -> %d"
+ot_flash_update_prog_watermark(const char* id, unsigned val, unsigned watermark) "%s: %u <= %u"
+ot_flash_update_rd_watermark(const char* id, unsigned val, unsigned watermark) "%s: %u >= %u"
+
+# ot_gpio.c
+
+ot_gpio_backend_recv(const char *id, char cmd, uint32_t data_in) "%s: %c:%08x"
+ot_gpio_backend_send(const char *id, const char *buf) "%s: %s"
+ot_gpio_in_change(const char *id, int no, bool ign, bool on, bool weak) "%s: gpio[%02d] hiz:%u on:%u wk:%u"
+ot_gpio_in_ignore(const char *id, uint32_t cn, uint32_t gi, uint32_t bi, uint32_t oe) "%s: cx:0x%08x gi:0x%08x bi:0x%08x oe:0x%08x"
+ot_gpio_in_line(const char *id, uint32_t ii, uint32_t im, uint32_t di) "%s: ii:0x%08x im:0x%08x di:0x%08x"
+ot_gpio_in_backend(const char *id, uint32_t ib, uint32_t bm, uint32_t data_ib) "%s: ib:0x%08x bm:0x%08x bi:0x%08x"
+ot_gpio_in_pull(const char *id, uint32_t pe, uint32_t ps, uint32_t pm, uint32_t pi) "%s: pe:0x%08x ps:0x%08x pm:0x%08x pi:0x%08x"
+ot_gpio_in_update(const char *id, uint32_t iv, uint32_t di, uint32_t do_, uint32_t dm) "%s: iv:0x%08x di:0x%08x di:0x%08x dm:0x%08x"
+ot_gpio_io_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%08x, pc=0x%x"
+ot_gpio_io_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%08x, pc=0x%x"
+ot_gpio_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%08x msk:0x%08x eff:0x%08x"
+ot_gpio_pad_attr_change(const char *id, int no, uint32_t cfg, const char *conf) "%s: gpio[%02d] 0x%08x: {%s}"
+ot_gpio_refresh_config(const char *id) "%s"
+ot_gpio_reset(const char *id, const char *state) "%s: %s"
+ot_gpio_strap_en(const char *id, int no, bool en, uint32_t straps) "%s: gpio[%02d] en:%u sampled:0x%08x"
+ot_gpio_out_update(const char *id, uint32_t out, uint32_t weak, uint32_t hiz) "%s: out:0x%08x wk:0x%08x hiz:0x%08x"
+ot_gpio_out_update_line_bool(const char *id, unsigned ix, int level) "%s: [%02u]: %u"
+ot_gpio_out_update_line_ibex(const char *id, unsigned ix, char repr) "%s: [%02u]: {%c}"
+
+# ot_hmac.c
+
+ot_hmac_debug(const char *id, const char *msg) "%s: %s"
+ot_hmac_fifo_write(const char *id, uint32_t addr, uint32_t val, unsigned size, uint32_t pc) "%s: addr=0x%02x, val=0x%x (%u), pc=0x%x"
+ot_hmac_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_hmac_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_hmac_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%01x msk:0x%01x eff:0x%01x"
+
+# ot_i2c.c
+
+ot_i2c_host_recv(const char *id, unsigned int entries, unsigned int bytes_to_read) "[%s] rx_fifo_entries:%u bytes_to_read:%u"
+ot_i2c_host_send(const char *id, unsigned int entries, unsigned int host_tx_threshold) "[%s] tx_fifo_entries:%u tx_threshold:%u"
+ot_i2c_io_read(const char *id, unsigned int addr, const char *regname, uint64_t val, uint64_t pc) "[%s] addr:0x%02x (%s), val:0x%" PRIx64", pc:0x%" PRIx64
+ot_i2c_io_write(const char *id, unsigned int addr, const char *regname, uint64_t val, uint64_t pc) "[%s] addr:0x%02x (%s), val:0x%" PRIx64", pc:0x%" PRIx64
+ot_i2c_irq(const char *id, const char *irq_id, bool en) "[%s] set interrupt %s to %u"
+ot_i2c_target_recv(const char *id, unsigned int entries, uint8_t data) "[%s] tx_fifo_entries:%u data:0x%02x"
+ot_i2c_target_set_acqdata(const char *id, unsigned int entries, uint8_t data, unsigned int signal) "[%s] rx_fifo_entries:%u data:0x%02x signal:0x%02x"
+ot_i2c_update_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "[%s] act:0x%08x msk:0x%08x eff:0x%08x"
+
+# ot_ibex_wrapper.c
+
+ot_ibex_wrapper_cpu_enable(const char *id, const char *ch, bool level) "%s: %s:%u"
+ot_ibex_wrapper_error(const char *id, const char *func, int line, const char *msg) "%s: %s:%d %s"
+ot_ibex_wrapper_escalate_rx(const char *id, bool level) "%s: %u"
+ot_ibex_wrapper_exit(const char *id, const char *msg, int val) "%s: %s (%d)"
+ot_ibex_wrapper_fill_entropy(const char *id, uint32_t bits, bool fips) "%s: 0x%08x fips:%u"
+ot_ibex_wrapper_info(const char *id, const char *func, int line, const char *msg) "%s: %s:%d %s"
+ot_ibex_wrapper_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%08x, pc=0x%x"
+ot_ibex_wrapper_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%08x, pc=0x%x"
+ot_ibex_wrapper_map(const char *id, unsigned slot, uint32_t src, uint32_t dst, uint32_t size, const char *name, uint32_t offset) "%s: region %u from 0x%08x to 0x%08x on 0x%x bytes (%s), off 0x%x"
+ot_ibex_wrapper_request_entropy(const char *id, bool again) "%s: %u"
+ot_ibex_wrapper_reset(const char *id, const char *phase) "%s: %s"
+ot_ibex_wrapper_unmap(const char *id, unsigned slot) "%s: region %u"
+ot_ibex_wrapper_update_exec(const char *id, uint32_t bm, bool esc_rx, bool halted, bool in_reset, bool cpu_en) "%s: bm:0x%x esc:%u halted:%u in_reset:%u -> CPU enable %u"
+
+# ot_keymgr.c
+ot_keymgr_advance(const char *id, const char *stage, int nstage, const char *cdi, int ncdi) "%s: [%s:%d], [%s:%d]"
+ot_keymgr_bypass_failure(const char *id, const char *what) "%s: bypass failure for %s due to enabled properties"
+ot_keymgr_change_main_fsm_state(const char *id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_keymgr_change_op_status(const char *id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_keymgr_change_working_state(const char *id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_keymgr_dump_creator_root_key(const char *id, unsigned idx, bool valid, const char *hexstr) "%s: share:%u valid:%u %s"
+ot_keymgr_dump_kdf_buf(const char *id, const char *op, size_t idx, const char *hexstr) "%s: %s: kdf[%02zu] %s"
+ot_keymgr_dump_kdf_material(const char *id, const char *what, const char *hexstr) "%s: %s %s"
+ot_keymgr_entropy(const char *id, unsigned reseed_cnt, bool resched) "%s: reseed_cnt: %u, resched: %u"
+ot_keymgr_error(const char *id, const char *msg) "%s: %s"
+ot_keymgr_gen_output(const char *id, const char *stage, int nstage, const char *cdi, int ncdi, const char *dest) "%s: stage:[%s:%d] cdi:[%s:%d] dest:%s"
+ot_keymgr_go_idle(const char *id) "%s"
+ot_keymgr_io_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%08x, pc=0x%x"
+ot_keymgr_io_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%08x, pc=0x%x"
+ot_keymgr_irq(const char *id, uint32_t active, uint32_t mask, bool level) "%s: act:0x%08x msk:0x%08x lvl:%u"
+ot_keymgr_kmac_req(const char *id, uint32_t fifo_len, uint32_t offset, uint32_t msg_len, bool last) "%s: fifo_len:%u offset:%u msg_len:%u, last:%d"
+ot_keymgr_kmac_rsp(const char *id, bool done, const char *hexstr) "%s: done:%d %s"
+ot_keymgr_lc_signal(const char *id, int level) "%s: LC signal level:%d"
+ot_keymgr_main_fsm_tick(const char *id, const char *st, int nst) "%s: [%s:%d]"
+ot_keymgr_operation(const char *id, const char *stage, const char *op, int nop) "%s: stage:%s op:[%s:%d]"
+ot_keymgr_push_key(const char *id, const char *sink, bool sl, bool valid, const char *hexstr) "%s: sink:%s sideload:%u valid:%u key:%s"
+ot_keymgr_push_kdf_key(const char *id, bool valid) "%s: valid:%u"
+ot_keymgr_reset(const char *id, const char *stage) "%s: %s"
+ot_keymgr_restore_kmac_key(const char *id) "%s"
+ot_keymgr_schedule_fsm(const char *id, const char *func, int line) "%s @ %s:%d"
+ot_keymgr_seed_missing(const char *id, unsigned ix) "%s: #%u"
+ot_keymgr_sideload_clear(const char *id, const char *sc, unsigned nsc) "%s: [%s:%u]"
+ot_keymgr_update_alert(const char *id, int prev, int next) "%s: %d -> %d"
+ot_keymgr_wipe_keys(const char *id, bool key_states, bool sw_out, uint32_t sink_bm) "%s: key_states:%u sw_out:%u sink_bm:0x%08x"
+
+# ot_keymgr_dpe.c
+
+ot_keymgr_dpe_change_main_fsm_state(const char *id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_keymgr_dpe_change_op_status(const char *id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_keymgr_dpe_change_working_state(const char *id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_keymgr_dpe_dump_creator_root_key(const char *id, unsigned idx, bool valid, const char *hexstr) "%s: share:%u valid:%u %s"
+ot_keymgr_dpe_dump_kdf_buf(const char *id, const char *op, size_t idx, const char *hexstr) "%s: %s: kdf[%02zu] %s"
+ot_keymgr_dpe_dump_kdf_material(const char *id, const char *what, const char *hexstr) "%s: %s %s"
+ot_keymgr_dpe_entropy(const char *id, unsigned reseed_cnt, bool resched) "%s: reseed_cnt: %u, resched: %u"
+ot_keymgr_dpe_error(const char *id, const char *msg) "%s: %s"
+ot_keymgr_dpe_go_idle(const char *id) "%s"
+ot_keymgr_dpe_io_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%08x, pc=0x%x"
+ot_keymgr_dpe_io_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%08x, pc=0x%x"
+ot_keymgr_dpe_irq(const char *id, uint32_t active, uint32_t mask, bool level) "%s: act:0x%08x msk:0x%08x lvl:%u"
+ot_keymgr_dpe_kmac_req(const char *id, uint32_t fifo_len, uint32_t offset, uint32_t msg_len, bool last) "%s: fifo_len:%u offset:%u msg_len:%u, last:%d"
+ot_keymgr_dpe_kmac_rsp(const char *id, bool done, const char *hexstr) "%s: done:%d %s"
+ot_keymgr_dpe_lc_signal(const char *id, int level) "%s: LC signal level:%d"
+ot_keymgr_dpe_main_fsm_tick(const char *id, const char *st, int nst) "%s: [%s:%d]"
+ot_keymgr_dpe_operation(const char *id, const char *op, int nop) "%s: [%s:%d]"
+ot_keymgr_dpe_push_key(const char *id, const char *sink, bool valid, const char *hexstr) "%s: sink:%s valid:%u key:%s"
+ot_keymgr_dpe_reset(const char *id, const char *stage) "%s: %s"
+ot_keymgr_dpe_reset_kmac_key(const char *id) "%s"
+ot_keymgr_dpe_schedule_fsm(const char *id, const char *func, int line) "%s @ %s:%d"
+ot_keymgr_dpe_seed_missing(const char *id, unsigned ix) "%s: #%u"
+ot_keymgr_dpe_sideload_clear(const char *id, const char *sc, unsigned nsc) "%s: [%s:%u]"
+
+# ot_kmac.c
+
+ot_kmac_app_finished(const char *id, unsigned app_idx) "%s: #%u"
+ot_kmac_app_request(const char *id, unsigned app_idx, bool last, size_t msg_len, const char *hexstr) "%s: #%u last:%u msg_len:%zu msg_data:%s"
+ot_kmac_app_start(const char *id, unsigned app_idx) "%s: #%u"
+ot_kmac_change_state_app(const char *id, unsigned app_idx, int line, const char *old, int nold, const char *new, int nnew) "%s: #%u @ %d [%s:%d] -> [%s:%d]"
+ot_kmac_change_state_sw(const char *id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_kmac_debug(const char *id, const char *msg) "%s: %s"
+ot_kmac_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_kmac_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_kmac_msgfifo_write(const char *id, uint32_t addr, uint32_t val, unsigned size, uint32_t pc) "%s: addr=0x%03x, val=0x%x (%u), pc=0x%x"
+ot_kmac_process_sw_command(const char *id, int cmd, const char *cmd_str) "%s: cmd=0x%02x (%s)"
+ot_kmac_push_key(const char *id, bool valid, const char *hexstr) "%s: valid:%u key:%s"
+ot_kmac_report_error(const char *id, int code, const char *code_str, uint32_t info) "%s: code=0x%02x (%s) info=0x%06x"
+ot_kmac_state_read_out(const char *id, uint32_t addr, uint32_t val, uint32_t pc) "%s: addr=0x%03x, val=0x%x, pc=0x%x"
+
+# ot_lc_ctrl.c
+
+ot_lc_ctrl_change_state(const char * id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_lc_ctrl_error(const char * id, const char *msg) "%s: %s"
+ot_lc_ctrl_escalate(const char * id, const char *fsm, const char *lc) "%s: %s: %s"
+ot_lc_ctrl_escalate_rx(const char * id, unsigned line, bool level) "%s: %u: %u"
+ot_lc_ctrl_force_raw(const char * id, bool level) "%s: %u"
+ot_lc_ctrl_info(const char * id, const char *msg) "%s: %s"
+ot_lc_ctrl_initial_lifecycle(const char * id, unsigned tcount, uint32_t lc_state, unsigned stix) "%s: transcount %u, lifecyle 0x%x [%u]"
+ot_lc_ctrl_initialize(const char * id, const char *cst, int cstix, unsigned tcount, const char *state, int six) "%s: %s (%d), tcount %u, state %s (%u)"
+ot_lc_ctrl_io_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_lc_ctrl_io_read_out_repeat(const char * id, uint32_t addr, const char * regname, unsigned count, uint32_t val) "%s: addr=0x%02x (%s) repeated %u times, val=0x%x"
+ot_lc_ctrl_io_write(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_lc_ctrl_km_div_missing(const char * id, unsigned ix) "%s: #%u"
+ot_lc_ctrl_load_lc_info_force_raw(const char * id) "%s: force_raw enabled"
+ot_lc_ctrl_load_otp_hw_cfg(const char * id, const char *socdbg) "%s: socdbg_state: %s"
+ot_lc_ctrl_load_otp_token(const char * id, const char *tk, unsigned tkix, const char *inv, uint64_t hi, uint64_t lo) "%s: token %s (%u) %svalid: 0x%016" PRIx64 "%016" PRIx64
+ot_lc_ctrl_mismatch_token(const char * id, const char *tkkind, const char *tkname, unsigned tok, uint64_t htkhi, uint64_t htklo, uint64_t rtkhi, uint64_t rtklo) "%s: %s token %s (%u): 0x%016" PRIx64 "%016" PRIx64 ", ref 0x%016" PRIx64 "%016" PRIx64
+ot_lc_ctrl_pwr_lc_req(const char * id, const char *where) "%s: %s"
+ot_lc_ctrl_reset(const char * id) "%s: "
+ot_lc_ctrl_start_transition(const char * id, const char *sr, const char *kind, const char *cst, int cstix, const char *tst, int tstix, unsigned tcount) "%s: %s start %s transit from %s (%d) to %s (%d) at tcount %u"
+ot_lc_ctrl_token_missing(const char * id, const char *token) "%s: %s"
+ot_lc_ctrl_transit_request(const char * id, const char *sr, const char *cst, int cstix, const char *tst, int tstix, const char *tk, int tkix) "%s: %s req. transit from %s (%d) to %s (%d) with token %s (%d)"
+ot_lc_ctrl_transition_missing(const char *id, const char *cfg, const char *st) "%s: %s_%s"
+ot_lc_ctrl_update_broadcast(const char * id, const char *st, const char *bcast, bool olvl, bool nlvl) "%s: %s: %s %u -> %u"
+
+# ot_mbx.c
+
+ot_mbx_busy(const char * mid, const char *state) "%s: %s"
+ot_mbx_change_state(const char * mid, const char *state) "%s: %s"
+ot_mbx_host_io_read_out(const char * mid, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_mbx_host_io_write(const char * mid, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_mbx_host_update_irq(const char *mbx_id, int prev, int next) "%s: %d -> %d"
+ot_mbx_status(const char *mbx_id, int line, bool abort, bool error, bool busy) "%s: [%d] abort:%u error:%u busy:%u"
+ot_mbx_sys_io_read_out(const char * mid, uint32_t addr, const char * regname, uint32_t val) "%s: addr=0x%02x (%s), val=0x%x"
+ot_mbx_sys_io_write(const char * mid, uint32_t addr, const char * regname, uint32_t val) "%s: addr=0x%02x (%s), val=0x%x"
+
+# ot_otbn.c
+
+ot_otbn_change_status(const char * id, const char * status) "%s: status=%s"
+ot_otbn_deny(const char * id, uint32_t pc, const char *msg) "%s: pc=0x%x %s"
+ot_otbn_error(const char * id, const char *msg) "%s: %s"
+ot_otbn_io_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_otbn_io_write(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_otbn_irq(const char * id, uint32_t active, uint32_t mask, bool level) "%s: act:0x%08x msk:0x%08x lvl:%u"
+ot_otbn_mem_read(const char * id, char mem, uint32_t addr, uint32_t value) "%s: %cmem addr=0x%04x, val=0x%08x"
+ot_otbn_mem_write(const char * id, char mem, uint32_t addr, uint32_t value, const char *outcome) "%s: %cmem addr=0x%04x, val=0x%08x%s"
+ot_otbn_post_execute(const char * id, uint32_t errbits, uint32_t insncount) "%s: errbits=0x%08x, insncount=%u"
+ot_otbn_proxy_completion_bh(const char * id, unsigned cmd) "%s: aftercmd=0x%02x"
+ot_otbn_proxy_entropy_request(const char * id, unsigned rnd) "%s: %u"
+ot_otbn_proxy_entropy_req_bh(const char * id, void) "%s"
+ot_otbn_proxy_push_entropy(const char * id, const char *kind, bool fips) "%s: %s: fips %u"
+ot_otbn_request_entropy(const char * id, unsigned ep) "%s: ep:%u"
+ot_otbn_update_alert(const char * id, int prev, int next) "%s: %d -> %d"
+
+# ot_otp.c, ot_otp_engine.c
+
+ot_otp_access_error_on(const char * id, int part, uint32_t addr, const char *msg) "%s: part #%d, addr 0x%04x: %s"
+ot_otp_addr_to_part(const char * id, uint32_t addr, const char *part, unsigned pix) "%s: addr %u partition %s (#%u)"
+ot_otp_configure_missing(const char *id, const char *cfg) "%s: %s"
+ot_otp_dai_change_state(const char * id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_otp_dai_new_digest_ecc(const char * id, const char *part, unsigned pix, uint64_t digest, uint32_t eccc) "%s: partition %s (#%u) digest 0x%016" PRIx64 ", ecc 0x%08x"
+ot_otp_dai_new_dword_ecc(const char * id, const char *part, unsigned pix, uint64_t data, uint32_t eccc) "%s: partition %s (#%u) dword 0x%016" PRIx64 ", ecc 0x%08x"
+ot_otp_dai_new_word_ecc(const char * id, const char *part, unsigned pix, uint32_t data, uint16_t eccc) "%s: partition %s (#%u) dword 0x%08x, ecc 0x%04hx"
+ot_otp_dai_read(const char * id, const char* part, unsigned pix, uint32_t hi, uint32_t lo) "%s: DAI read %s (#%u): 0x%08x%08x"
+ot_otp_ecc_init_error(const char * id, const char* part, unsigned pix, unsigned off, uint32_t word, uint16_t ecc) "%s: %s (#%u): @ %u 0x%08x, ecc 0x%04hx"
+ot_otp_ecc_mismatch(const char * id, unsigned address, uint32_t secc, uint32_t lecc) "%s: @ %04x ECC OTP: 0x%08x local: 0x%08x"
+ot_otp_ecc_parity_error(const char * id, uint32_t d_i, uint32_t ecc) "%s: 0x%04x, ECC 0x%02x"
+ot_otp_ecc_recovered_error(const char * id, uint32_t d_i, uint32_t d_o) "%s: 0x%04x -> 0x%04x"
+ot_otp_ecc_unrecoverable_error(const char * id, uint32_t d_i) "%s: 0x%04x"
+ot_otp_get_otp_key(const char * id, int type) "%s: type %d"
+ot_otp_initialize(const char * id) "%s"
+ot_otp_integrity_report(const char * id, const char* part, unsigned pix, const char *msg) "%s: partition %s (#%u) %s"
+ot_otp_io_reg_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_otp_io_reg_write(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_otp_io_swcfg_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%04x (%s), val=0x%x, pc=0x%x"
+ot_otp_keygen_entropy(const char * id, unsigned slot, bool resched) "%s: %u slots, resched: %u"
+ot_otp_lc_broadcast(const char * id, unsigned sig, bool level) "%s: bcast %u, level %u"
+ot_otp_lci_change_state(const char * id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_otp_lci_write(const char * id, unsigned pos, uint16_t cval, uint16_t nval) "%s: @ %u 0x%04x -> 0x%04x"
+ot_otp_lci_write_ecc(const char * id, unsigned pos, uint8_t cval, uint8_t nval) "%s: @ %u 0x%02x -> 0x%02x"
+ot_otp_load_backend(const char * id, unsigned ver, const char *mode, unsigned eccbits, unsigned eccgran) "%s: loading OTP image v%u in %s mode w/ ECC %u bits, granule %u"
+ot_otp_load_token(const char * id, const char *token, unsigned tkx, uint64_t hi, uint64_t lo, const char *valid) "%s: %s (%u) 0x%016" PRIx64 "%016" PRIx64 ": %svalid"
+ot_otp_mismatch_digest(const char * id, const char* part, unsigned pix, uint64_t sdig, uint64_t ldig) "%s: mismatch digest on %s (#%u), computed 0x%" PRIx64 " stored 0x%" PRIx64
+ot_otp_pwr_otp_req(const char * id, const char *where) "%s: %s"
+ot_otp_reset(const char * id, const char *phase) "%s: %s"
+ot_otp_set_error(const char * id, const char *part, unsigned pix, const char* err, unsigned eix) "%s: %s (#%u): %s (%u)"
+ot_otp_skip_digest(const char * id, const char* part, unsigned pix) "%s: skipping empty digest on %s (#%u)"
+ot_otp_key_generated(const char * id, int type) "%s: type %d"
+ot_otp_unscramble_partition(const char * id, const char *part, unsigned pix, unsigned size) "%s: partition %s (#%u) size:%u"
+ot_otp_update_irq(const char * id, int prev, int next) "%s: %d -> %d"
+ot_otp_update_alert(const char * id, int prev, int next) "%s: %d -> %d"
+
+# ot_otp_ot_be.c
+
+ot_otp_ot_be_read_out(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_otp_ot_be_write(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
+
+# ot_pinmux.c
+
+ot_pinmux_io_read_out(uint32_t addr, uint32_t val, uint32_t pc) "addr=0x%03x, val=0x%x, pc=0x%x"
+ot_pinmux_io_write(uint32_t addr, uint32_t val, uint32_t pc) "addr=0x%03x, val=0x%x, pc=0x%x"
+
+# ot_plic_ext.c
+
+ot_plic_ext_io_msip_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%01x (%s), val=0x%x, pc=0x%x"
+ot_plic_ext_io_msip_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%01x (%s), val=0x%x, pc=0x%x"
+ot_plic_ext_io_alert_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%01x (%s), val=0x%x, pc=0x%x"
+ot_plic_ext_io_alert_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%01x (%s), val=0x%x, pc=0x%x"
+
+# ot_pwrmgr.c
+
+ot_pwrmgr_cdc_sync(const char *id) "%s"
+ot_pwrmgr_change_state(const char *id, int line, const char *type, const char *old, int nold, const char *new, int nnew) "%s @ %d %s: [%s:%d] -> [%s:%d]"
+ot_pwrmgr_clock_enable(const char *d, const char *clkname, bool enable) "%s: %s en:%u"
+ot_pwrmgr_escalate_rx(const char *id, bool level) "%s: level %u"
+ot_pwrmgr_go_idle(const char *id, const char *state) "%s: %s"
+ot_pwrmgr_ignore_req(const char *id, const char *reason) "%s: %s"
+ot_pwrmgr_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_pwrmgr_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_pwrmgr_reset(const char *id, const char *action) "%s: %s"
+ot_pwrmgr_reset_req(const char *id, const char *name, unsigned val) "%s: %s: %u"
+ot_pwrmgr_rom(const char *id, int n, const char *what, bool val) "%s rom #%u %s=%u"
+ot_pwrmgr_rst_req(const char *id, const char *name, unsigned src) "%s %s(%u)"
+ot_pwrmgr_schedule_fsm(const char *id, const char *func, int line) "%s @ %s:%d"
+ot_pwrmgr_shutdown(const char *id, bool main) "%s: main %u"
+ot_pwrmgr_sw_rst_req(const char *id, unsigned src, bool active) "%s: %u: %u"
+ot_pwrmgr_wkup(const char *id, const char *name, unsigned src, bool active) "%s: %s(%u): %u"
+
+# ot_rom_ctrl.c
+
+ot_rom_ctrl_computed_digest(const char *id, const char *hexstr) "%s: digest:%s"
+ot_rom_ctrl_digest_mode(const char *id, const char *mode) "%s: %s digest mode"
+ot_rom_ctrl_parity_error(const char * id, uint32_t d_i, unsigned ecc) "%s: 0x%08x, ECC 0x%02x"
+ot_rom_ctrl_recovered_error(const char * id, uint32_t d_i, uint32_t d_o) "%s: 0x%08x -> 0x%08x"
+ot_rom_ctrl_unrecoverable_error(const char * id, uint32_t d_i) "%s: 0x%08x"
+ot_rom_ctrl_image_identify(const char *id, const char *fname, const char *imgtype) "%s: file '%s' identified as %s"
+ot_rom_ctrl_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_rom_ctrl_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_rom_ctrl_load_rom_no_image(const char *id) "%s: ROM image not defined"
+ot_rom_ctrl_mem_read_out(const char *id, uint32_t addr, uint32_t val, uint32_t pc) "%s: addr=0x%04x, val=0x%08x, pc=0x%x"
+ot_rom_ctrl_mem_rejects(const char *id, uint32_t addr, bool is_write, uint32_t pc) "%s: addr=0x%04x, is_write=%u, pc=0x%x"
+ot_rom_ctrl_mem_write(const char *id, uint32_t addr, uint32_t val, uint32_t pc) "%s: addr=0x%04x, val=0x%08x, pc=0x%x"
+ot_rom_ctrl_missing(const char *id, const char *error) "%s: %s"
+ot_rom_ctrl_notify(const char *id, bool rom_good) "%s: ROM good: %u"
+ot_rom_ctrl_reset(const char *id, const char *phase) "%s: %s"
+
+# ot_rstmgr.c
+
+ot_rstmgr_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_rstmgr_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_rstmgr_reset(const char *id, const char *phase) "%s: %s"
+ot_rstmgr_reset_req(const char *id, const char *req, uint32_t reqix, bool fastclk) "%s: %s reset_info:0x%8x @%u"
+ot_rstmgr_sw_reset(const char *id, const char *devpath) "%s: SW reset %s"
+ot_rstmgr_sw_rst(const char *id, const char *path, bool reset) "%s: %s: reset:%u"
+
+# ot_sensor.c
+
+ot_sensor_io_read_out(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_sensor_io_write(uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "addr=0x%02x (%s), val=0x%x, pc=0x%x"
+
+# ot_soc_dbg_ctrl.c
+
+ot_soc_dbg_ctrl_boot_status(const char *id, bool mclk, bool ioclk, bool otp, bool lc, bool cpu, unsigned rdone, unsigned rgood) "%s: mclk:%u ioclk:%u otp:%u lc:%u cpu_en:%u rom_done:0x%x rom_good:0x%x"
+ot_soc_dbg_ctrl_change_state(const char *id, int line, const char *old, int nold, const char *new, int nnew) "%s: @ %d [%s:%d] -> [%s:%d]"
+ot_soc_dbg_ctrl_cpu_boot_done(const char *id, int level) "%s: %d"
+ot_soc_dbg_ctrl_core_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_soc_dbg_ctrl_core_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_soc_dbg_ctrl_core_update_irq(const char *id, int new) "%s: %u"
+ot_soc_dbg_ctrl_jtag_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val) "%s: addr=0x%02x (%s), val=0x%x"
+ot_soc_dbg_ctrl_jtag_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val) "%s: addr=0x%02x (%s), val=0x%x"
+ot_soc_dbg_ctrl_rcv(const char *id, const char *src, unsigned n, char sig) "%s: %s #%d: lvl %c"
+ot_soc_dbg_ctrl_schedule_fsm(const char *id, const char *func, int line, unsigned tc) "%s: @ %s:%d (%u)"
+ot_soc_dbg_ctrl_soc_dbg_state(const char *id, const char *st) "%s: %s"
+ot_soc_dbg_ctrl_tick_fsm(const char *id, const char *st, uint16_t lc, bool dfti, bool lcd, bool hcb, bool bc) "%s: %s lc:0x%02x dfti:%u lcd:%u hcb:%u bc:%u"
+ot_soc_dbg_ctrl_update_policy(const char *id, const char *socdbgst, const char *fsmst, uint8_t cat_bm, bool relocked) "%s: [%s] fsm:%s cat_bm:0x%1x relocked:%u"
+
+# ot_soc_proxy.c
+
+ot_soc_proxy_ingress_irq(const char * id, unsigned n, bool level) "%s: #%u: %u"
+ot_soc_proxy_io_read_out(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_soc_proxy_io_write(const char * id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_soc_proxy_update_irq(const char * id, unsigned n, int prev, int next) "%s: #%u %d -> %d"
+
+# ot_spi_device.c
+
+ot_spi_device_bus_change_state(const char *id, int line, const char *state, int stateval) "%s: @%d: %s [%d]"
+ot_spi_device_chr_handle_packet(const char *id, unsigned count, unsigned eot, char rx, char tx, const char *st) "%s: 0x%x bytes, eot: %u, rx: %csb, tx: %csb, mode:%s"
+ot_spi_device_chr_error(const char *id, const char *err) "%s: %s"
+ot_spi_device_flash_byte_unexpected(const char *id, uint8_t rx) "%s: unexpected byte 0x%02x after completed command"
+ot_spi_device_flash_change_state(const char *id, int line, const char *prev, int preval, const char *next, int nextval) "%s: @%d: %s[%d] -> %s[%d]"
+ot_spi_device_flash_cross_buffer(const char *id, uint32_t addr, uint32_t next_addr) "%s: addr:0x%08x next:0x%08x"
+ot_spi_device_flash_command_params(const char *id, unsigned addr_size, bool addr_swap_en, bool dummy_en, bool payload_swap_en) "%s: addrsize=%u addrswap=%u dummy=%u payloadswap=%u"
+ot_spi_device_flash_disabled_slot(const char *id, uint8_t cmd, unsigned slot) "%s: cmd 0x%02x matched disabled slot %u"
+ot_spi_device_flash_exec(const char *id, const char *cmd) "%s: %s"
+ot_spi_device_flash_match(const char *id, const char *type, uint8_t cmd, unsigned slot) "%s: %s matched cmd 0x%02x slot %u"
+ot_spi_device_flash_filtered_command(const char *id, uint8_t cmd) "%s: filtered cmd %02x"
+ot_spi_device_flash_intercepted_command(const char *id, unsigned slot) "%s: intercepted HW cmd slot %u"
+ot_spi_device_flash_intercept_mailbox(const char *id, uint32_t addr) "%s: intercepted read addr:0x%08x to mailbox region"
+ot_spi_device_flash_new_command(const char *id, const char *type, uint8_t cmd, unsigned slot) "%s: %s cmd 0x%02x slot %u"
+ot_spi_device_flash_overflow(const char *id, const char *msg) "%s: %s"
+ot_spi_device_flash_pace(const char *id, const char *msg, bool pending) "%s: %s: %u"
+ot_spi_device_flash_payload(const char *id, unsigned fpos, unsigned idx, unsigned len) "%s: pos:%u idx:%u len:%u"
+ot_spi_device_flash_push_address(const char *id, uint32_t address) "%s: 0x%08x"
+ot_spi_device_flash_read_config_error(const char *id, uint32_t addr, uint32_t next_addr) "%s: flip cannot be detected: 0x%08x next:0x%08x"
+ot_spi_device_flash_read_status(const char *id, unsigned slot, uint8_t status) "%s: sr[%u] 0x%02x"
+ot_spi_device_flash_read_threshold(const char *id, uint32_t addr, uint32_t threshold) "%s: 0x%08x @ 0x%08x"
+ot_spi_device_flash_set_read_addr(const char *id, uint32_t addr) "%s: 0x%08x"
+ot_spi_device_flash_swap_byte(const char *id, const char *type, unsigned byte_num, uint8_t prev, uint8_t cur) "%s: swapped %s byte %u 0x%02x -> 0x%02x"
+ot_spi_device_flash_transfer(const char *id, const char *dir, uint8_t byte) "%s: host %s 0x%02x"
+ot_spi_device_flash_unknown_command(const char *id, uint8_t opcode) "%s: 0x%02x"
+ot_spi_device_flash_unmatched_command(const char *id, uint8_t cmd) "%s: unmatched cmd 0x%02x"
+ot_spi_device_flash_upload(const char *id, unsigned slot, uint32_t cmd_info, bool busy) "%s: slot:%d info:0x%08x busy:%u"
+ot_spi_device_gen_fifo_error(const char *id, const char *msg) "%s: %s"
+ot_spi_device_gen_phase(const char *id, const char *func, unsigned off, unsigned lim, bool phase) "%s: %s off:0x%03x lim:0x%03x ph:%u"
+ot_spi_device_gen_rx_timeout(const char *id, unsigned count) "%s: %d"
+ot_spi_device_gen_update_fifo(const char *id, const char *fifo, int line, uint32_t val) "%s: %s@%d: 0x%08x"
+ot_spi_device_io_buf_read_out(const char *id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%03x, sz=%u, val=0x%08x, pc=0x%x"
+ot_spi_device_io_buf_write_in(const char *id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%03x, sz=%u,  val=0x%08x, pc=0x%x"
+ot_spi_device_io_spi_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_spi_device_io_spi_write_in(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_spi_device_set_irq(const char *id, const char *name, unsigned irq, bool level) "%s: %s [%u]: %u"
+ot_spi_device_io_tpm_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_spi_device_io_tpm_write_in(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_spi_device_release(const char *id) "%s"
+ot_spi_device_reset(const char *id, const char *stage) "%s: %s"
+ot_spi_device_update_last_read_addr(const char *id, uint32_t addr) "%s: 0x%08x"
+
+# ot_spi_host.c
+
+ot_spi_host_cmd_clock(const char *id, unsigned cmdid, bool auto_, unsigned speed) "%s: {%u} a:%u spd:%u"
+ot_spi_host_cmd_ongoing(const char *id, unsigned cmdid, unsigned len, bool pending) "%s: {%u} len:%u pend:%u"
+ot_spi_host_cmd_stat(const char *id, unsigned cmdid, unsigned size, unsigned speed) "%s: {%u} sz:%-3u spd:%u"
+ot_spi_host_cs(const char *id, unsigned csid, const char *level) "%s: cs#:%u %sselected"
+ot_spi_host_debug(const char *id, const char *msg) "%s: %s"
+ot_spi_host_debug1(const char *id, const char *msg, uint32_t val) "%s: %s 0x%x"
+ot_spi_host_events(const char *id, uint32_t cur, uint32_t raised, uint32_t active, uint32_t mask, uint32_t eff) "%s: cur:0x%02x rsd:0x%02x act:0x%02x msk:0x%02x eff:0x%02x"
+ot_spi_host_exec_command(const char *id, unsigned cmdid, const char *dir, const char *spd, uint32_t csid, bool active, unsigned len, bool start) "%s: {%u} d:%s s:%s cs#:%u csa:%u len:%u (t:%u)"
+ot_spi_host_fsm(const char *id, unsigned cmdid, const char *cause) "%s: {%u} step %s"
+ot_spi_host_internal_reset(const char *id, unsigned sdelay, unsigned cdelay) "%s: start:%uns comp:%uns"
+ot_spi_host_io_read(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr:0x%02x (%s), val:0x%08x, pc:0x%x"
+ot_spi_host_io_read_repeat(const char *id, const char * regname, size_t count) "%s: last %s read repeated %zu times"
+ot_spi_host_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr:0x%02x (%s), val:0x%08x, pc:0x%x"
+ot_spi_host_kick_command(const char *id, unsigned cmdid, bool start) "%s: {%u} start:%u"
+ot_spi_host_new_command(const char *id, unsigned cmdid, const char *dir, const char *spd, uint32_t csid, bool active, unsigned len) "%s: {%u} d:%s s:%s cs#:%u csa:%u len:%u"
+ot_spi_host_passthrough_disabled(const char *id) "%s: passthrough enable is not asserted"
+ot_spi_host_reset(const char *id) "%s"
+ot_spi_host_retire_command(const char *id, unsigned cmdid) "%s: {%u}"
+ot_spi_host_stall(const char *id, const char *msg, uint32_t val) "%s: %s rem %u"
+ot_spi_host_status(const char *id, const char *msg, uint32_t status, const char *str, unsigned cmd, unsigned rxd, unsigned txd, char state) "%s: %s 0x%08x s:%s cq:%u rq:%u tq:%u st:%c"
+ot_spi_host_transfer(const char *id, uint64_t transfer, uint32_t tx_data, uint32_t rx_data) "%s: {%" PRIu64 "} tx_data: 0x%02x rx_data: 0x%02x"
+ot_spi_host_clock_update(const char *id, unsigned pclk) "%s: %u Hz"
+ot_spi_host_update_irq(const char *id, const char *channel, int level) "%s: irq %s: %d"
+
+# ot_sram_ctrl.c
+
+ot_sram_ctrl_expediate_init(const char *id, const char *from) "%s from %s"
+ot_sram_ctrl_ifetch_warning(const char *id) "%s: cannot disable execution, ot_vmapper not associated"
+ot_sram_ctrl_initialize(const char *id, unsigned start, unsigned end, unsigned count, bool exp) "%s 0x%08x..0x%08x (0x%x) exp:%u"
+ot_sram_ctrl_initialization_complete(const char *id, const char *from) "%s: after %s"
+ot_sram_ctrl_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_sram_ctrl_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_sram_ctrl_lc_signal(const char *id, int level) "%s: LC signal level:%d"
+ot_sram_ctrl_mem_io_readi(const char *id, uint32_t addr, unsigned size, uint32_t pc) "%s: addr=0x%06x, size=%u, pc=0x%x"
+ot_sram_ctrl_mem_io_reado(const char *id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%06x, size=%u, val=0x%08x, pc=0x%x"
+ot_sram_ctrl_mem_io_write(const char *id, uint32_t addr, unsigned size, uint32_t val, uint32_t pc) "%s: addr=0x%06x, size=%u, val=0x%08x, pc=0x%x"
+ot_sram_ctrl_mem_not_initialized(const char *id, unsigned ix, uint64_t bm) "%s: [%u] %016" PRIx64
+ot_sram_ctrl_no_mem_change(const char *id, const char *msg) "%s: %s"
+ot_sram_ctrl_request_hw_init(const char *id) "%s"
+ot_sram_ctrl_reseed(const char *id) "%s"
+ot_sram_ctrl_schedule_init(const char *id) "%s"
+ot_sram_ctrl_seed_status(const char *id, bool seed_valid) "%s: seed valid: %u"
+ot_sram_ctrl_switch_mem(const char *id, const char *dest) "%s: to %s"
+ot_sram_ctrl_update_exec(const char *id, bool cifetch, bool rifetch, bool oifetch, bool lcfetch, bool gifetch) "%s: cfg:%u csr:%u otp:%u lc_hw_debug:%u res:%u"
+
+# ot_timer.c
+
+ot_timer_io_read_out(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_timer_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr=0x%03x (%s), val=0x%x, pc=0x%x"
+ot_timer_timer_mod(const char *id, int64_t now, int64_t next, bool anticipate) "%s: @ %" PRId64 ": %" PRId64 " ant: %u"
+ot_timer_update_clock(const char *id, uint32_t frequency) "%s: @ %u Hz"
+ot_timer_update_irq(const char *id, bool level) "%s: %d"
+
+# ot_uart.c
+
+ot_uart_check_baudrate(const char *id, unsigned pclk, unsigned baud) "%s: @ %u Hz: %u bps"
+ot_uart_connect_input_clock(const char *id, const char * srcname) "%s: %s"
+ot_uart_debug(const char *id, const char *msg) "%s: %s"
+ot_uart_io_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_uart_io_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_uart_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%08x msk:0x%08x eff:0x%08x"
+
+# ot_usbdev.c
+
+ot_usbdev_address_changed(const char *id, uint8_t address) "%s: %d"
+ot_usbdev_chr_process_cmd(const char *id, const char *cmd) "%s: %s"
+ot_usbdev_chr_usb_event_handler(const char *id, int event) "%s: server event=%d"
+ot_usbdev_cancel(const char *id, uint32_t xfer_id, const char *msg) "%s: xfer_id=%u: %s"
+ot_usbdev_complete_transfer(const char *id, uint32_t cmdid, uint32_t xfered_len, const char *status, const char *msg) "%s: cmdid=%u, len=%u, status=%s: %s"
+ot_usbdev_enable_changed(const char *id, bool enable) "%s: enable=%u"
+ot_usbdev_io_buffer_read_out(const char *id, uint32_t addr, uint32_t val, uint32_t pc) "%s: addr=0x%04x, val=0x%x, pc=0x%x"
+ot_usbdev_io_buffer_write(const char *id, uint32_t addr, uint32_t val, uint32_t pc) "%s: addr=0x%04x, val=0x%x, pc=0x%x"
+ot_usbdev_io_read_out(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_usbdev_io_write(const char *id, uint32_t addr, const char *regname, uint32_t val, uint32_t pc) "%s: addr=0x%02x (%s), val=0x%x, pc=0x%x"
+ot_usbdev_irqs(const char *id, uint32_t active, uint32_t mask, uint32_t eff) "%s: act:0x%08x msk:0x%08x eff:0x%08x"
+ot_usbdev_link_reset(const char *id, bool completed) "%s: completed=%u"
+ot_usbdev_packet_received(const char *id, uint8_t ep, uint8_t bufid, uint32_t size) "%s: ep=%u, buf_id=%u, size=%u"
+ot_usbdev_packet_sent(const char *id, uint8_t ep, uint8_t bufid, uint32_t size) "%s: ep=%u, buf_id=%u, size=%u"
+ot_usbdev_link_state_changed(const char *id, const char *state) "%s: link_state=%s"
+ot_usbdev_pop_rx_fifo(const char *id, uint32_t rxfifo_entry) "%s: entry=0x%x"
+ot_usbdev_push_av_out_buffer(const char *id, uint8_t buf_id) "%s: buf_id=%u"
+ot_usbdev_push_av_setup_buffer(const char *id, uint8_t buf_id) "%s: buf_id=%u"
+ot_usbdev_reset(const char *id, const char *stage) "%s: %s"
+ot_usbdev_retire_in_packet(const char *id, uint32_t ep) "%s: ep=%u"
+ot_usbdev_setup(const char *id, uint8_t ep, const char *msg) "%s: ep=%u: %s"
+ot_usbdev_setup_addr(const char *id, uint8_t addr, uint8_t ep, const char *msg) "%s: addr=%u, ep=%u: %s"
+ot_usbdev_transfer(const char *id, uint32_t cmdid, uint8_t ep, const char *dir, uint8_t flags, uint16_t mps, uint32_t xfer_len, const char *msg) "%s: cmdid=%u, ep=%u, dir=%s, flags=0x%x, mps=%u, len=%u: %s"
+ot_usbdev_server_protocol_error(const char *id, const char *msg) "%s: %s"
+ot_usbdev_server_hello(const char *id, uint16_t major, uint16_t minor) "%s: major=%u, minor=%u"
+ot_usbdev_server_report_connected(const char *id, bool connected) "%s: connected=%u"
+ot_usbdev_vbus_changed(const char *id, bool vbus) "%s: vbus=%u"
+
+# ot_unimp.c
+
+ot_unimp_irq(const char *id, unsigned ix, bool lvl) "%s: #%u = %u"
+ot_unimp_alert(const char *id, unsigned ix) "%s: #%u"
+
+# ot_vmapper.c
+
+ot_vmapper_disable_exec(const char *id, unsigned slot, const char *name, uint32_t src, unsigned size, bool dis) "%s: s:%u [%s] src:0x%08x size:0x%x dis:%u"
+ot_vmapper_new_phy_addr(const char *id, bool insn, uint32_t vaddr, uint32_t paddr) "%s: i:%u v:0x%08x p:0x%08x"
+ot_vmapper_override_vcpu_config(const char *id) "%s: redirect address resolution and force PMP to use virtual addresses"
+ot_vmapper_translate_enable(const char *id, bool insn, unsigned slot, uint32_t src, uint32_t dst, unsigned size) "%s: i:%u s:%u src:0x%08x dst:0x%08x size:0x%x"
+ot_vmapper_translate_disable(const char *id, bool insn, unsigned slot) "%s: i:%u s:%u"
+ot_vmapper_show_range(const char *id) "%s"
diff --git a/hw/opentitan/trace.h b/hw/opentitan/trace.h
new file mode 100644
index 0000000000000..cf8674e93b229
--- /dev/null
+++ b/hw/opentitan/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_opentitan.h"
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index fc9c35bd981ea..68a00b766951c 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -7,8 +7,134 @@ config RISCV_NUMA
 config IBEX
     bool
 
+config IBEX_CLOCK_SRC
+    bool
+
+config IBEX_COMMON
+    bool
+
+config IBEX_GPIO
+    bool
+
 # RISC-V machines in alphabetical order
 
+config OT_DARJEELING
+    bool
+    default y
+    select IBEX
+    select IBEX_CLOCK_SRC
+    select IBEX_COMMON
+    select OT_ADDRESS_SPACE
+    select OT_AES
+    select OT_ALERT
+    select OT_AON_TIMER
+    select OT_AST_DJ
+    select OT_CLKMGR
+    select OT_CSRNG
+    select OT_DEV_PROXY
+    select OT_DM_TL
+    select OT_DMA
+    select OT_ENTROPY_SRC
+    select OT_EDN
+    select OT_GPIO_DJ
+    select OT_HMAC
+    select OT_I2C
+    select OT_I2C_HOST_PROXY
+    select OT_IBEX_WRAPPER
+    select OT_KEYMGR_DPE
+    select OT_KMAC
+    select OT_LC_CTRL
+    select OT_MBX
+    select OT_OTBN
+    select OT_OTP_IF
+    select OT_OTP_DJ
+    select OT_OTP_OT_BE
+    select OT_PINMUX_DJ
+    select OT_PLIC_EXT
+    select OT_PWRMGR
+    select OT_RSTMGR
+    select OT_ROM_CTRL
+    select OT_SOC_DBG_CTRL
+    select OT_SOC_PROXY
+    select OT_SPI_DEVICE
+    select OT_SPI_HOST
+    select OT_SRAM_CTRL
+    select OT_TIMER
+    select OT_UART
+    select OT_UNIMP
+    select PULP_RV_DM
+    select RISCV_DM
+    select RISCV_DTM
+    select SIFIVE_PLIC
+    select SPLIT_IRQ
+    select TAP_CTRL_RBB
+
+config OT_EARLGREY
+    bool
+    default y
+    select IBEX
+    select IBEX_CLOCK_SRC
+    select IBEX_COMMON
+    select IBEX_GPIO
+    select OT_AES
+    select OT_ALERT
+    select OT_AON_TIMER
+    select OT_AST_EG
+    select OT_CLKMGR
+    select OT_CSRNG
+    select OT_EDN
+    select OT_EG_PAD_RING
+    select OT_ENTROPY_SRC
+    select OT_FLASH
+    select OT_GPIO_EG
+    select OT_HMAC
+    select OT_I2C
+    select OT_I2C_HOST_PROXY
+    select OT_IBEX_WRAPPER
+    select OT_KEYMGR
+    select OT_KMAC
+    select OT_LC_CTRL
+    select OT_OTBN
+    select OT_OTP_EG
+    select OT_OTP_IF
+    select OT_OTP_OT_BE
+    select OT_PINMUX_EG
+    select OT_PLIC_EXT
+    select OT_PWRMGR
+    select OT_ROM_CTRL
+    select OT_RSTMGR
+    select OT_SENSOR_EG
+    select OT_SPI_DEVICE
+    select OT_SPI_HOST
+    select OT_SRAM_CTRL
+    select OT_TIMER
+    select OT_UART
+    select OT_USBDEV
+    select OT_UNIMP
+    select PULP_RV_DM
+    select RISCV_DM
+    select RISCV_DTM
+    select SIFIVE_PLIC
+    select SPLIT_IRQ
+    select TAP_CTRL_RBB
+
+config IBEXDEMO
+    bool
+    default y
+    select IBEX
+    select IBEX_CLOCK_SRC
+    select IBEX_COMMON
+    select IBEXDEMO_GPIO
+    select IBEXDEMO_SIMCTRL
+    select IBEXDEMO_SPI
+    select IBEXDEMO_TIMER
+    select IBEXDEMO_UART
+    select RISCV_DM
+    select RISCV_DTM
+    select ST7735
+    select TAP_CTRL_RBB
+    select UNIMP
+
 config MICROCHIP_PFSOC
     bool
     default y
@@ -38,6 +164,9 @@ config OPENTITAN
     default y
     depends on RISCV32
     select IBEX
+    select IBEX_SPI_HOST
+    select IBEX_TIMER
+    select IBEX_UART
     select SIFIVE_PLIC
     select UNIMP
 
@@ -69,6 +198,17 @@ config RISCV_VIRT
     select ACPI
     select ACPI_PCI
 
+config RISCV_DEBUG
+    bool
+
+config RISCV_DM
+    select RISCV_DEBUG
+    bool
+
+config RISCV_DTM
+    select TAP_CTRL
+    bool
+
 config SHAKTI_C
     bool
     default y
diff --git a/hw/riscv/debug.c b/hw/riscv/debug.c
new file mode 100644
index 0000000000000..ed3b7b07239eb
--- /dev/null
+++ b/hw/riscv/debug.c
@@ -0,0 +1,56 @@
+/*
+ * QEMU RISC-V Debug
+ *
+ * Copyright (c) 2023 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Generated code for absract commands has been extracted from the PULP Debug
+ * module whose file (dm_mem.sv) contains the following copyright. This piece of
+ * code is self contained within the `riscv_dmi_dm_access_register` function:
+ *
+ *   Copyright and related rights are licensed under the Solderpad Hardware
+ *   License, Version 0.51 (the “License”); you may not use this file except in
+ *   compliance with the License. You may obtain a copy of the License at
+ *   http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ *   or agreed to in writing, software, hardware and materials distributed under
+ *   this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+ *   CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ *   specific language governing permissions and limitations under the License.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/riscv/debug.h"
+
+static const TypeInfo riscv_debug_device_info = {
+    .name = TYPE_RISCV_DEBUG_DEVICE,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(RISCVDebugDeviceState),
+    .class_size = sizeof(RISCVDebugDeviceClass),
+    .abstract = true,
+};
+
+static void riscv_debug_register_types(void)
+{
+    type_register_static(&riscv_debug_device_info);
+}
+
+type_init(riscv_debug_register_types);
diff --git a/hw/riscv/dm.c b/hw/riscv/dm.c
new file mode 100644
index 0000000000000..c8ef571ec6fdb
--- /dev/null
+++ b/hw/riscv/dm.c
@@ -0,0 +1,2794 @@
+/*
+ * QEMU Debug Module Interface and Controller
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without (limitation) the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Generated code for absract commands has been extracted from the PULP Debug
+ * module whose file (dm_mem.sv) contains the following copyright. This piece of
+ * code is self contained within the `riscv_dm_access_register` function:
+ *
+ *   Copyright and related rights are licensed under the Solderpad Hardware
+ *   License, Version 0.51 (the “License”); you may not use this file except in
+ *   compliance with the License. You may obtain a copy of the License at
+ *   http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ *   or agreed to in writing, software, hardware and materials distributed under
+ *   this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+ *   CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ *   specific language governing permissions and limitations under the License.
+ *
+ * Limitations:
+ * - Unsupported features:
+ *   - PMP management
+ *   - DCSR.STEPIE
+ *   - Cancellation of outstanding halt request
+ *   - Halt on reset
+ * - Not tested:
+ *   - User mode debugging
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/compiler.h"
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "accel/tcg/cpu-ldst.h"
+#include "disas/dis-asm.h"
+#include "hw/boards.h"
+#include "hw/core/cpu.h"
+#include "hw/jtag/tap_ctrl.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/debug.h"
+#include "hw/riscv/dm.h"
+#include "hw/riscv/dtm.h"
+#include "system/hw_accel.h"
+#include "system/runstate.h"
+#include "target/riscv/cpu.h"
+#include "trace.h"
+
+
+#undef TRACE_CPU_STATES
+
+/*
+ * Register definitions
+ */
+
+#define RISCV_DEBUG_DM_VERSION     2u /* Debug Module v0.13.x */
+#define RISCV_DEBUG_SB_VERSION     1u /* System Bus v1.0 */
+#define RISCVDM_ABSTRACTDATA_SLOTS 10u
+#define ADDRESS_BITS               7u
+
+/* clang-format off */
+
+/* Debug Module registers */
+REG32(DATA0, 0x04u)
+REG32(DATA1, 0x05u)
+REG32(DATA2, 0x06u)
+REG32(DATA3, 0x07u)
+REG32(DATA4, 0x08u)
+REG32(DATA5, 0x09u)
+REG32(DATA6, 0x0au)
+REG32(DATA7, 0x0bu)
+REG32(DATA8, 0x0cu)
+REG32(DATA9, 0x0du)
+REG32(DATA10, 0x0eu)
+REG32(DATA11, 0x0fu)
+REG32(DMCONTROL, 0x10u)
+    FIELD(DMCONTROL, DMACTIVE, 0u, 1u)
+    FIELD(DMCONTROL, NDMRESET, 1u, 1u)
+    FIELD(DMCONTROL, CLRRESETHALTREQ, 2u, 1u)
+    FIELD(DMCONTROL, SETRESETHALTREQ, 3u, 1u)
+    FIELD(DMCONTROL, HARTSELHI, 6u, 10u)
+    FIELD(DMCONTROL, HARTSELLO, 16u, 10u)
+    FIELD(DMCONTROL, HASEL, 26u, 1u)
+    FIELD(DMCONTROL, ACKHAVERESET, 28u, 1u)
+    FIELD(DMCONTROL, HARTRESET, 29u, 1u)
+    FIELD(DMCONTROL, RESUMEREQ, 30u, 1u)
+    FIELD(DMCONTROL, HALTREQ, 31u, 1u)
+REG32(DMSTATUS, 0x11u)
+    FIELD(DMSTATUS, VERSION, 0u, 4u)
+    FIELD(DMSTATUS, CONFSTRPTRVALID, 4u, 1u)
+    FIELD(DMSTATUS, HASRESETHALTREQ, 5u, 1u)
+    FIELD(DMSTATUS, AUTHBUSY, 6u, 1u)
+    FIELD(DMSTATUS, AUTHENTICATED, 7u, 1u)
+    FIELD(DMSTATUS, ANYHALTED, 8u, 1u)
+    FIELD(DMSTATUS, ALLHALTED, 9u, 1u)
+    FIELD(DMSTATUS, ANYRUNNING, 10u, 1u)
+    FIELD(DMSTATUS, ALLRUNNING, 11u, 1u)
+    FIELD(DMSTATUS, ANYUNAVAIL, 12u, 1u)
+    FIELD(DMSTATUS, ALLUNAVAIL, 13u, 1u)
+    FIELD(DMSTATUS, ANYNONEXISTENT, 14u, 1u)
+    FIELD(DMSTATUS, ALLNONEXISTENT, 15u, 1u)
+    FIELD(DMSTATUS, ANYRESUMEACK, 16u, 1u)
+    FIELD(DMSTATUS, ALLRESUMEACK, 17u, 1u)
+    FIELD(DMSTATUS, ANYHAVERESET, 18u, 1u)
+    FIELD(DMSTATUS, ALLHAVERESET, 19u, 1u)
+    FIELD(DMSTATUS, IMPEBREAK, 22u, 1u)
+REG32(HARTINFO, 0x12u)
+    FIELD(HARTINFO, DATAADDR, 0u, 12u)
+    FIELD(HARTINFO, DATASIZE, 12u, 4u)
+    FIELD(HARTINFO, DATAACCESS, 16u, 1u)
+    FIELD(HARTINFO, NSCRATCH, 20u, 4u)
+REG32(ABSTRACTCS, 0x16u)
+    FIELD(ABSTRACTCS, DATACOUNT, 0u, 4u)
+    FIELD(ABSTRACTCS, CMDERR, 8u, 3u)
+    FIELD(ABSTRACTCS, BUSY, 12u, 1u)
+    FIELD(ABSTRACTCS, PROGBUFSIZE, 24u, 5u)
+REG32(COMMAND, 0x17u)
+    /* muxed fields: access register */
+    FIELD(COMMAND, CONTROL, 0u, 24u)
+    FIELD(COMMAND, CMDTYPE, 24u, 8u)
+    FIELD(COMMAND, REG_REGNO, 0u, 16u)
+    FIELD(COMMAND, REG_WRITE, 16u, 1u)
+    FIELD(COMMAND, REG_TRANSFER, 17u, 1u)
+    FIELD(COMMAND, REG_POSTEXEC, 18u, 1u)
+    FIELD(COMMAND, REG_AARPOSTINCREMENT, 19u, 1u)
+    FIELD(COMMAND, REG_AARSIZE, 20u, 3u)
+    /* muxed fields: access memory */
+    FIELD(COMMAND, MEM_WRITE, 16u, 1u)
+    FIELD(COMMAND, MEM_AAMPOSTINCREMENT, 19u, 1u)
+    FIELD(COMMAND, REG_AAMSIZE, 20u, 3u)
+    FIELD(COMMAND, MEM_AAMVIRTUAL, 23u, 1u)
+REG32(ABSTRACTAUTO, 0x18u)
+    FIELD(ABSTRACTAUTO, AUTOEXECDATA, 0u, 12u)
+    FIELD(ABSTRACTAUTO, AUTOEXECPROGBUF, 16u, 16u)
+REG32(NEXTDM, 0x1d)
+REG32(PROGBUF0, 0x20u)
+REG32(PROGBUF1, 0x21u)
+REG32(PROGBUF2, 0x22u)
+REG32(PROGBUF3, 0x23u)
+REG32(PROGBUF4, 0x24u)
+REG32(PROGBUF5, 0x25u)
+REG32(PROGBUF6, 0x26u)
+REG32(PROGBUF7, 0x27u)
+REG32(PROGBUF8, 0x28u)
+REG32(PROGBUF9, 0x29u)
+REG32(PROGBUF10, 0x2au)
+REG32(PROGBUF11, 0x2bu)
+REG32(PROGBUF12, 0x2cu)
+REG32(PROGBUF13, 0x2du)
+REG32(PROGBUF14, 0x2eu)
+REG32(PROGBUF15, 0x2fu)
+REG32(SBCS, 0x38u)
+    FIELD(SBCS, SBACCESS8, 0u, 1u)
+    FIELD(SBCS, SBACCESS16, 1u, 1u)
+    FIELD(SBCS, SBACCESS32, 2u, 1u)
+    FIELD(SBCS, SBACCESS64, 3u, 1u)
+    FIELD(SBCS, SBACCESS128, 4u, 1u)
+    FIELD(SBCS, SBASIZE, 5u, 7u)
+    FIELD(SBCS, SBERROR, 12u, 3u)
+    FIELD(SBCS, SBREADONDATA, 15u, 1u)
+    FIELD(SBCS, SBAUTOINCREMENT, 16u, 1u)
+    FIELD(SBCS, SBACCESS, 17u, 3u)
+    FIELD(SBCS, SBREADONADDR, 20u, 1u)
+    FIELD(SBCS, SBBUSY, 21u, 1u)
+    FIELD(SBCS, SBBUSYERROR, 22u, 1u)
+    FIELD(SBCS, SBVERSION, 29u, 3u)
+REG32(SBADDRESS0, 0x39u)
+REG32(SBADDRESS1, 0x3au)
+REG32(SBDATA0, 0x3cu)
+REG32(SBDATA1, 0x3du)
+REG32(HALTSUM0, 0x40u)
+
+#define A_FIRST A_DATA0
+#define A_LAST  A_HALTSUM0
+
+/* Debug CSRs */
+REG32(DCSR, CSR_DCSR)
+    FIELD(DCSR, PRV, 0u, 2u)
+    FIELD(DCSR, STEP, 2u, 1u)
+    FIELD(DCSR, NMIP, 3u, 1u)
+    FIELD(DCSR, MPRVEN, 4u, 1u)
+    FIELD(DCSR, CAUSE, 6u, 3u)
+    FIELD(DCSR, STOPTIME, 9u, 1u)
+    FIELD(DCSR, STOPCOUNT, 10u, 1u)
+    FIELD(DCSR, STEPIE, 11u, 1u)
+    FIELD(DCSR, EBREAKU, 12u, 1u)
+    FIELD(DCSR, EBREAKS, 13u, 1u)
+    FIELD(DCSR, EBREAKM, 15u, 1u)
+    FIELD(DCSR, XDEBUGVER, 28u, 4u)
+
+/* Debug module remote data */
+REG32(HALTED, RISCV_DM_HALTED_OFFSET)
+    FIELD(HALTED, HALTED, 0u, 1u)
+REG32(GOING, RISCV_DM_GOING_OFFSET)
+    FIELD(GOING, GOING, 0u, 1u)
+REG32(RESUMING, RISCV_DM_RESUMING_OFFSET)
+    FIELD(RESUMING, RESUMING, 0u, 1u)
+REG32(EXCEPTION, RISCV_DM_EXCEPTION_OFFSET)
+    FIELD(EXCEPTION, EXCEPTION, 0u, 1u)
+REG32(FLAGS, RISCV_DM_FLAGS_OFFSET)
+    FIELD(FLAGS, FLAG_GO, 0u, 1u)
+    FIELD(FLAGS, FLAG_RESUME, 1u, 1u)
+/* clang-format on */
+
+/*
+ * Macros
+ */
+
+/* clang-format off */
+#define SBCS_WRITE_MASK (R_SBCS_SBERROR_MASK         | \
+                         R_SBCS_SBREADONDATA_MASK    | \
+                         R_SBCS_SBAUTOINCREMENT_MASK | \
+                         R_SBCS_SBACCESS_MASK        | \
+                         R_SBCS_SBREADONADDR_MASK    | \
+                         R_SBCS_SBBUSYERROR_MASK)
+/* clang-format on */
+
+#define GPR_ZERO 0u /* zero = x0 */
+#define GPR_S0   8u /* s0 = x8 */
+#define GPR_A0   10u /* a0 = x10 */
+
+static_assert((A_LAST - A_FIRST) < 64u, "too many registers");
+
+#define REG_BIT(_addr_) \
+    (((_addr_) >= (uint32_t)A_FIRST) ? (1ull << ((_addr_) - A_FIRST)) : 0u)
+#define REG_BIT_DEF(_reg_) REG_BIT(A_##_reg_)
+
+#define DM_REG_COUNT (1u << (ADDRESS_BITS))
+#define xtrace_riscv_dm_error(_soc_, _msg_) \
+    trace_riscv_dm_error(_soc_, __func__, __LINE__, _msg_)
+#define xtrace_riscv_dm_info(_soc_, _msg_, _val_) \
+    trace_riscv_dm_info(_soc_, __func__, __LINE__, _msg_, _val_)
+#define xtrace_reg(_soc_, _msg_, _reg_, _off_) \
+    trace_riscv_dm_access_register(_soc_, _msg_, \
+                                   get_riscv_debug_reg_name(_reg_), \
+                                   (_reg_) - (_off_));
+
+#define RISCVDM_DEFAULT_MTA 0x100000000ull /* "MEMTXATTRS_UNSPECIFIED" */
+
+/*
+ * Type definitions
+ */
+
+/** Debug Module command errors */
+typedef enum RISCVDMCmdErr {
+    CMD_ERR_NONE = 0,
+    CMD_ERR_BUSY = 1,
+    CMD_ERR_NOT_SUPPORTED = 2,
+    CMD_ERR_EXCEPTION = 3,
+    CMD_ERR_HALT_RESUME = 4,
+    CMD_ERR_BUS = 5,
+    _CMD_ERR_RSV1 = 6,
+    CMD_ERR_OTHER = 7,
+} RISCVDMCmdErr;
+
+/* For debug purpose only, used to only dump traces on any change */
+typedef struct RISCVDMStateCache {
+    struct {
+        unsigned ix;
+        bool halted;
+        bool stopped;
+        bool running;
+    } cpu;
+    struct {
+        unsigned halted;
+        unsigned running;
+        unsigned unavail;
+        unsigned nonexistent;
+        unsigned resumeack;
+        unsigned havereset;
+    } dm;
+} RISCVDMStateCache;
+
+typedef struct RISCVDMHartState {
+    RISCVCPU *cpu; /* Associated hart */
+    target_ulong hartid; /** Hart ID */
+    bool halted; /* Hart has halted execution */
+    bool resumed; /* Hart has resumed execution */
+    bool have_reset; /* Hart has reset, not yet supported */
+    bool unlock_reset; /* Whether DM may reset CPU */
+#ifdef TRACE_CPU_STATES
+    RISCVDMStateCache dbgcache;
+#endif
+} RISCVDMHartState;
+
+typedef struct RISCVDMConfig {
+    unsigned nscratch;
+    unsigned progbuf_count;
+    unsigned data_count;
+    unsigned abstractcmd_count;
+    uint32_t dmi_addr; /* note: next_dm imposes that DM use 32-bit only addr. */
+    uint32_t dmi_next; /* next_dm */
+    hwaddr dm_phyaddr;
+    hwaddr rom_phyaddr;
+    hwaddr whereto_phyaddr;
+    hwaddr data_phyaddr;
+    hwaddr progbuf_phyaddr;
+    uint64_t mta_dm; /* MemTxAttrs */
+    uint64_t mta_sba; /* MemTxAttrs */
+    uint16_t resume_offset;
+    bool sysbus_access;
+    bool abstractauto;
+    bool enable;
+} RISCVDMConfig;
+
+/** Debug Module */
+struct RISCVDMState {
+    RISCVDebugDeviceState parent;
+
+    RISCVDMCmdErr cmd_err; /* Command result */
+    RISCVDMHartState *hart; /* Currently selected hart for debug, if any */
+    RISCVDMHartState *harts; /* Hart states */
+    AddressSpace *as; /* Hart address space */
+    const char *soc; /* Subsystem name, for debug */
+    uint64_t nonexistent_bm; /* Selected harts that are not existent */
+    uint64_t unavailable_bm; /* Selected harts that are not available */
+    uint64_t haltreq_bm; /* Selected harts that have a pending halt request */
+    uint64_t reset_bm; /* Selected harts that have an ongoing reset request */
+    uint64_t to_go_bm; /* Harts that have been flagged for debug exec */
+    uint32_t address; /* DM register addr: only bADDRESS_BITS..b0 are used */
+    uint32_t *regs; /* Debug module register values */
+    uint64_t sbdata; /* Last sysbus data */
+    MemTxAttrs mta_dm; /* MemTxAttrs to access debug module implementation */
+    MemTxAttrs mta_sba; /* MemTxAttrs to access system bus devices */
+    bool cmd_busy; /* A command is being executed */
+    bool dtm_ok; /* DTM is available */
+
+    /* config */
+    RISCVDTMState *dtm;
+    RISCVDMConfig cfg;
+    uint32_t hart_count; /* Count of harts */
+    uint32_t *cpu_idx; /* array of hart_count CPU index */
+};
+
+struct RISCVDMClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+typedef RISCVDMCmdErr CmdErr;
+
+/** Abstract command types */
+typedef enum RISCVDMAbstractCommand {
+    CMD_ACCESS_REGISTER = 0,
+    CMD_QUICK_ACCESS = 1,
+    CMD_ACCESS_MEMORY = 2,
+} RISCVDMAbstractCommand;
+
+/** System bus access error */
+typedef enum RISCVDMSysbusError {
+    SYSBUS_NONE,
+    SYSBUS_TIMEOUT,
+    SYSBUS_BADADDR,
+    SYSBUS_BADALIGN,
+    SYSBUS_ASIZE,
+    SYSBUS_OTHER = 7,
+} RISCVDMSysbusError;
+
+/** Debug Module register */
+struct RISCVDMDMReg;
+typedef struct RISCVDMDMReg RISCVDMDMReg;
+
+/** Handlers for a Debug Module register */
+struct RISCVDMDMReg {
+    const char *name; /* register name, for debugging */
+    const uint32_t value; /* preset bits */
+    CmdErr (*read)(RISCVDMState *dm, uint32_t *value);
+    CmdErr (*write)(RISCVDMState *dm, uint32_t value);
+};
+
+/*
+ * Forward declarations
+ */
+
+static bool riscv_dm_cond_autoexec(RISCVDMState *dm, bool prgbf,
+                                   unsigned regix);
+static CmdErr riscv_dm_read_absdata(RISCVDMState *dm, unsigned woffset,
+                                    unsigned wcount, hwaddr *value);
+static CmdErr riscv_dm_write_absdata(RISCVDMState *dm, unsigned woffset,
+                                     unsigned wcount, hwaddr value);
+static CmdErr riscv_dm_read_progbuf(RISCVDMState *dm, unsigned woffset,
+                                    hwaddr *value);
+static CmdErr riscv_dm_write_progbuf(RISCVDMState *dm, unsigned woffset,
+                                     hwaddr value);
+static CmdErr riscv_dm_exec_command(RISCVDMState *dm, uint32_t value);
+
+static CmdErr riscv_dm_dmcontrol_write(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_command_write(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_abstractauto_read(RISCVDMState *dm, uint32_t *value);
+static CmdErr riscv_dm_abstractauto_write(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_dmstatus_read(RISCVDMState *dm, uint32_t *value);
+static CmdErr riscv_dm_sbcs_write(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_sbaddress0_write(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_sbaddress1_write(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_sbdata0_read(RISCVDMState *dm, uint32_t *value);
+static CmdErr riscv_dm_sbdata0_write(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_sbdata1_read(RISCVDMState *dm, uint32_t *value);
+static CmdErr riscv_dm_sbdata1_write(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_hartinfo_read(RISCVDMState *dm, uint32_t *value);
+static CmdErr riscv_dm_abstractcs_read(RISCVDMState *dm, uint32_t *value);
+static CmdErr riscv_dm_abstractcs_write(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_haltsum0_read(RISCVDMState *dm, uint32_t *value);
+
+static CmdErr riscv_dm_access_register(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_access_memory(RISCVDMState *dm, uint32_t value);
+static CmdErr riscv_dm_quick_access(RISCVDMState *dm, uint32_t value);
+
+static void riscv_dm_ensure_running(RISCVDMState *dm);
+static void riscv_dm_halt_hart(RISCVDMState *dm, unsigned hartsel);
+static void riscv_dm_resume_hart(RISCVDMState *dm, unsigned hartsel);
+
+/*
+ * Constants
+ */
+
+/* DM update/capture registers that should not be traced in trace log */
+static const uint64_t RISCVDM_REG_IGNORE_TRACES =
+    /* the remote debugger keeps polling dmstatus (to get hart status) */
+    REG_BIT_DEF(DMSTATUS) |
+    /* the remote debugger polls abstractcs quite often (to get busy/cmderr) */
+    REG_BIT_DEF(ABSTRACTCS);
+
+static const RISCVDMDMReg RISCVDM_DMS[DM_REG_COUNT] = {
+    [A_DMCONTROL] = {
+        .name = "dmcontrol",
+        .write = &riscv_dm_dmcontrol_write,
+    },
+    [A_DMSTATUS] = {
+        .name = "dmstatus",
+        .value = (RISCV_DEBUG_DM_VERSION << R_DMSTATUS_VERSION_SHIFT) |
+                 (1u << R_DMSTATUS_AUTHENTICATED_SHIFT),
+        .read = &riscv_dm_dmstatus_read,
+    },
+    [A_HARTINFO] = {
+        .name = "hartinfo",
+        .read = &riscv_dm_hartinfo_read,
+    },
+    [A_ABSTRACTCS] = {
+        .name = "abstractcs",
+        .read = &riscv_dm_abstractcs_read,
+        .write = &riscv_dm_abstractcs_write,
+    },
+    [A_COMMAND] = {
+        .name = "command",
+        .write = &riscv_dm_command_write,
+    },
+    [A_ABSTRACTAUTO] = {
+        .name = "abstractauto",
+        .read = &riscv_dm_abstractauto_read,
+        .write = &riscv_dm_abstractauto_write,
+    },
+    [A_NEXTDM] = {
+        .name = "nextdm",
+    },
+    [A_SBCS] = {
+        .name = "sbcs",
+        .write = &riscv_dm_sbcs_write,
+    },
+    [A_SBADDRESS0] = {
+        .name = "sbaddress0",
+        .write = &riscv_dm_sbaddress0_write,
+    },
+    [A_SBADDRESS1] = {
+        .name = "sbaddress1",
+        .write = &riscv_dm_sbaddress1_write,
+    },
+    [A_SBDATA0] = {
+        .name = "sbdata0",
+        .read = &riscv_dm_sbdata0_read,
+        .write = &riscv_dm_sbdata0_write,
+    },
+    [A_SBDATA1] = {
+        .name = "sbdata1",
+        .read = &riscv_dm_sbdata1_read,
+        .write = &riscv_dm_sbdata1_write,
+    },
+    [A_HALTSUM0] = {
+        .name = "haltsum0",
+        .read = &riscv_dm_haltsum0_read,
+    },
+};
+
+#define MAKE_NAME_ENTRY(_pfx_, _ent_) [_pfx_##_##_ent_] = stringify(_ent_)
+static const char *DCSR_CAUSE_NAMES[8u] = {
+    /* clang-format off */
+    MAKE_NAME_ENTRY(DCSR_CAUSE, NONE),
+    MAKE_NAME_ENTRY(DCSR_CAUSE, EBREAK),
+    MAKE_NAME_ENTRY(DCSR_CAUSE, BREAKPOINT),
+    MAKE_NAME_ENTRY(DCSR_CAUSE, HALTREQ),
+    MAKE_NAME_ENTRY(DCSR_CAUSE, STEP),
+    MAKE_NAME_ENTRY(DCSR_CAUSE, RESETHALTREQ),
+    /* clang-format on */
+};
+#undef MAKE_NAME_ENTRY
+
+#define MAKE_REG_ENTRY(_ent_) stringify(_ent_)
+static const char *RISCVDM_DM_DATA_NAMES[12u] = {
+    /* clang-format off */
+    MAKE_REG_ENTRY(data0),
+    MAKE_REG_ENTRY(data1),
+    MAKE_REG_ENTRY(data2),
+    MAKE_REG_ENTRY(data3),
+    MAKE_REG_ENTRY(data4),
+    MAKE_REG_ENTRY(data5),
+    MAKE_REG_ENTRY(data6),
+    MAKE_REG_ENTRY(data7),
+    MAKE_REG_ENTRY(data8),
+    MAKE_REG_ENTRY(data9),
+    MAKE_REG_ENTRY(data10),
+    MAKE_REG_ENTRY(data11),
+    /* clang-format on */
+};
+
+static const char *RISCVDM_DM_PROGBUF_NAMES[16u] = {
+    /* clang-format off */
+    MAKE_REG_ENTRY(progbuf0),
+    MAKE_REG_ENTRY(progbuf1),
+    MAKE_REG_ENTRY(progbuf2),
+    MAKE_REG_ENTRY(progbuf3),
+    MAKE_REG_ENTRY(progbuf4),
+    MAKE_REG_ENTRY(progbuf5),
+    MAKE_REG_ENTRY(progbuf6),
+    MAKE_REG_ENTRY(progbuf7),
+    MAKE_REG_ENTRY(progbuf8),
+    MAKE_REG_ENTRY(progbuf9),
+    MAKE_REG_ENTRY(progbuf10),
+    MAKE_REG_ENTRY(progbuf11),
+    MAKE_REG_ENTRY(progbuf12),
+    MAKE_REG_ENTRY(progbuf13),
+    MAKE_REG_ENTRY(progbuf14),
+    MAKE_REG_ENTRY(progbuf15),
+    /* clang-format on */
+};
+#undef MAKE_REG_ENTRY
+
+static const char *riscv_dm_get_reg_name(unsigned addr);
+
+/* -------------------------------------------------------------------------- */
+/* DMI interface implementation */
+/* -------------------------------------------------------------------------- */
+
+static RISCVDebugResult
+riscv_dm_write_rq(RISCVDebugDeviceState *dev, uint32_t addr, uint32_t value)
+{
+    RISCVDMState *dm = RISCV_DM(dev);
+
+    if (resettable_is_in_reset(OBJECT(dev))) {
+        if (addr != A_DMCONTROL) {
+            xtrace_riscv_dm_error(dm->soc, "write rejected: DM in reset");
+            return RISCV_DEBUG_FAILED;
+        }
+    }
+
+    CmdErr ret;
+    bool autoexec = false;
+
+    /* store address for next read back */
+    dm->address = addr;
+
+    if ((addr >= A_DATA0) && (addr < (A_DATA0 + dm->cfg.data_count))) {
+        unsigned dix = addr - A_DATA0;
+        if (!(ret = riscv_dm_write_absdata(dm, dix, 1u, (hwaddr)value))) {
+            dm->regs[addr] = value;
+            autoexec = riscv_dm_cond_autoexec(dm, false, dix);
+        }
+    } else if ((addr >= A_PROGBUF0) &&
+               (addr < (A_PROGBUF0 + dm->cfg.progbuf_count))) {
+        unsigned pbix = addr - A_PROGBUF0;
+        if (!(ret = riscv_dm_write_progbuf(dm, pbix, (hwaddr)value))) {
+            dm->regs[addr] = value;
+            autoexec = riscv_dm_cond_autoexec(dm, true, pbix);
+        }
+    } else if (RISCVDM_DMS[addr].write) {
+        ret = RISCVDM_DMS[addr].write(dm, value);
+    } else {
+        xtrace_riscv_dm_info(dm->soc, "write request ignored @", addr);
+        ret = CMD_ERR_NONE;
+    }
+    if (ret != CMD_ERR_NONE) {
+        xtrace_riscv_dm_error(dm->soc, "fail to write");
+    }
+
+    if ((ret == CMD_ERR_NONE) && autoexec) {
+        xtrace_riscv_dm_info(dm->soc, "autoexec last command",
+                             dm->regs[A_COMMAND]);
+        ret = riscv_dm_exec_command(dm, dm->regs[A_COMMAND]);
+    }
+
+    /* do not override a previous error, which should be explicitly cleared */
+    if (dm->cmd_err == CMD_ERR_NONE) {
+        dm->cmd_err = ret;
+    }
+
+    if ((addr >= A_FIRST) && !(RISCVDM_REG_IGNORE_TRACES & REG_BIT(addr))) {
+        trace_riscv_dm_reg_update(dm->soc, riscv_dm_get_reg_name(addr), addr,
+                                  value, "write", ret);
+    }
+
+    return RISCV_DEBUG_NOERR;
+}
+
+static RISCVDebugResult
+riscv_dm_read_rq(RISCVDebugDeviceState *dev, uint32_t addr)
+{
+    RISCVDMState *dm = RISCV_DM(dev);
+
+    CmdErr ret;
+    bool autoexec = false;
+    uint32_t value = 0;
+
+    /* store address for next read back */
+    dm->address = addr;
+
+    if ((addr >= A_DATA0) && (addr < (A_DATA0 + dm->cfg.data_count))) {
+        unsigned dix = addr - A_DATA0;
+        hwaddr val = 0u;
+        if (!(ret = riscv_dm_read_absdata(dm, dix, 1u, &val))) {
+            dm->regs[addr] = (uint32_t)val;
+            autoexec = riscv_dm_cond_autoexec(dm, false, dix);
+        }
+    } else if ((addr >= A_PROGBUF0) &&
+               (addr < (A_PROGBUF0 + dm->cfg.progbuf_count))) {
+        unsigned pbix = addr - A_PROGBUF0;
+        hwaddr val;
+        if (!(ret = riscv_dm_read_progbuf(dm, pbix, &val))) {
+            dm->regs[addr] = (uint32_t)val;
+            autoexec = riscv_dm_cond_autoexec(dm, true, pbix);
+        }
+    } else if (RISCVDM_DMS[addr].read) {
+        ret = RISCVDM_DMS[addr].read(dm, &value);
+    } else {
+        ret = CMD_ERR_NONE;
+        value = dm->regs[addr];
+    }
+
+    if (ret != CMD_ERR_NONE) {
+        xtrace_riscv_dm_error(dm->soc, "fail to read");
+    } else if (autoexec) {
+        xtrace_riscv_dm_info(dm->soc, "autoexec last command",
+                             dm->regs[A_COMMAND]);
+        ret = riscv_dm_exec_command(dm, dm->regs[A_COMMAND]);
+    }
+
+    if ((addr >= A_FIRST) && !(RISCVDM_REG_IGNORE_TRACES & REG_BIT(addr))) {
+        trace_riscv_dm_reg_update(dm->soc, riscv_dm_get_reg_name(addr), addr,
+                                  value, "read", ret);
+    }
+
+    /* do not override a previous error, which should be explicitly cleared */
+    if (dm->cmd_err == CMD_ERR_NONE) {
+        dm->cmd_err = ret;
+    }
+
+    return RISCV_DEBUG_NOERR;
+}
+
+static uint32_t riscv_dm_read_value(RISCVDebugDeviceState *dev)
+{
+    RISCVDMState *dm = RISCV_DM(dev);
+
+    if (dm->address >= DM_REG_COUNT) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid address: 0x%x\n", __func__,
+                      dm->address);
+
+        return 0;
+    }
+
+    uint32_t value = dm->regs[dm->address];
+
+    if (!(RISCVDM_REG_IGNORE_TRACES & REG_BIT(dm->address))) {
+        trace_riscv_dm_reg_capture(dm->soc, riscv_dm_get_reg_name(dm->address),
+                                   dm->address, value);
+    }
+
+    return value;
+}
+
+static void riscv_dm_set_next_dm(RISCVDebugDeviceState *dev, uint32_t addr)
+{
+    RISCVDMState *dm = RISCV_DM(dev);
+
+    dm->regs[A_NEXTDM] = addr;
+}
+
+/* -------------------------------------------------------------------------- */
+/* DM implementation */
+/* -------------------------------------------------------------------------- */
+
+static const char *riscv_dm_get_reg_name(unsigned addr)
+{
+    if ((addr >= A_DATA0) && (addr <= A_DATA11)) {
+        return RISCVDM_DM_DATA_NAMES[addr - A_DATA0];
+    }
+
+    if ((addr >= A_PROGBUF0) && (addr <= A_PROGBUF15)) {
+        return RISCVDM_DM_PROGBUF_NAMES[addr - A_PROGBUF0];
+    }
+
+    if (addr < DM_REG_COUNT) {
+        return RISCVDM_DMS[addr].name;
+    }
+
+    return "INVALID";
+}
+
+
+static bool riscv_dm_cond_autoexec(RISCVDMState *dm, bool prgbf, unsigned regix)
+{
+    uint32_t autoexec =
+        prgbf ?
+            FIELD_EX32(dm->regs[A_ABSTRACTAUTO], ABSTRACTAUTO,
+                       AUTOEXECPROGBUF) :
+            FIELD_EX32(dm->regs[A_ABSTRACTAUTO], ABSTRACTAUTO, AUTOEXECDATA);
+    return (bool)(autoexec & (1u << regix));
+}
+
+
+static CmdErr riscv_dm_read_absdata(RISCVDMState *dm, unsigned woffset,
+                                    unsigned wcount, hwaddr *value)
+{
+    if (!dm->cfg.data_phyaddr) {
+        /* CSR-shadowed implementation is not supported */
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NOT_SUPPORTED;
+    }
+
+    if ((woffset + wcount > dm->cfg.data_count) || (wcount > 2u)) {
+        xtrace_riscv_dm_error(dm->soc, "invalid arg");
+        return CMD_ERR_OTHER;
+    }
+
+    /* use a memory location to store abstract data */
+    MemTxResult res;
+    res = address_space_rw(dm->as, dm->cfg.data_phyaddr + (woffset << 2u),
+                           dm->mta_dm, value, wcount << 2u, false);
+    trace_riscv_dm_absdata(dm->soc, "read", woffset, wcount, *value, res);
+    if (res != MEMTX_OK) {
+        xtrace_riscv_dm_error(dm->soc, "memtx");
+        return CMD_ERR_BUS;
+    }
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_write_absdata(RISCVDMState *dm, unsigned woffset,
+                                     unsigned wcount, hwaddr value)
+{
+    if (!dm->cfg.data_phyaddr) {
+        /* CSR-shadowed implementation is not supported */
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NOT_SUPPORTED;
+    }
+
+    if ((woffset + wcount > dm->cfg.data_count) || (wcount > 2u)) {
+        xtrace_riscv_dm_error(dm->soc, "invalid arg");
+        return CMD_ERR_OTHER;
+    }
+
+    /* use a memory location to store abstract data */
+    MemTxResult res;
+    res = address_space_rw(dm->as, dm->cfg.data_phyaddr + (woffset << 2u),
+                           dm->mta_dm, &value, wcount << 2u, true);
+    trace_riscv_dm_absdata(dm->soc, "write", woffset, wcount, value, res);
+    if (res != MEMTX_OK) {
+        xtrace_riscv_dm_error(dm->soc, "memtx");
+        return CMD_ERR_BUS;
+    }
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_read_progbuf(RISCVDMState *dm, unsigned woffset,
+                                    hwaddr *value)
+{
+    if (!dm->cfg.progbuf_phyaddr) {
+        /* CSR-shadowed implementation is not supported */
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NOT_SUPPORTED;
+    }
+
+    if (woffset >= dm->cfg.progbuf_count) {
+        xtrace_riscv_dm_error(dm->soc, "invalid arg");
+        return CMD_ERR_OTHER;
+    }
+
+    /* use a memory location to store abstract data */
+    MemTxResult res;
+    res = address_space_rw(dm->as, dm->cfg.progbuf_phyaddr + (woffset << 2u),
+                           dm->mta_dm, value, sizeof(uint32_t), false);
+    trace_riscv_dm_progbuf(dm->soc, "read", woffset, *value, res);
+    if (res != MEMTX_OK) {
+        xtrace_riscv_dm_error(dm->soc, "memtx");
+        return CMD_ERR_BUS;
+    }
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_write_progbuf(RISCVDMState *dm, unsigned woffset,
+                                     hwaddr value)
+{
+    if (!dm->cfg.progbuf_phyaddr) {
+        /* CSR-shadowed implementation is not supported */
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NOT_SUPPORTED;
+    }
+
+    if (woffset >= dm->cfg.progbuf_count) {
+        xtrace_riscv_dm_error(dm->soc, "invalid arg");
+        return CMD_ERR_OTHER;
+    }
+
+    /* use a memory location to store abstract data */
+    MemTxResult res;
+    res = address_space_rw(dm->as, dm->cfg.progbuf_phyaddr + (woffset << 2u),
+                           dm->mta_dm, &value, sizeof(uint32_t), true);
+    trace_riscv_dm_progbuf(dm->soc, "write", woffset, value, res);
+    if (res != MEMTX_OK) {
+        xtrace_riscv_dm_error(dm->soc, "memtx");
+        return CMD_ERR_BUS;
+    }
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_write_whereto(RISCVDMState *dm, uint32_t value)
+{
+    /* use a memory location to store the where-to-jump location */
+    if (address_space_rw(dm->as, dm->cfg.whereto_phyaddr, dm->mta_dm, &value,
+                         sizeof(value), true) != MEMTX_OK) {
+        xtrace_riscv_dm_error(dm->soc, "memtx");
+        return CMD_ERR_BUS;
+    }
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_update_flags(RISCVDMState *dm, unsigned hartnum,
+                                    bool set, uint32_t flag_mask)
+{
+    if (!dm->cfg.dm_phyaddr) {
+        /* CSR-shadowed implementation is not supported */
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NOT_SUPPORTED;
+    }
+
+    if (hartnum >= dm->hart_count) {
+        xtrace_riscv_dm_error(dm->soc, "internal error");
+        return CMD_ERR_OTHER;
+    }
+
+    /*
+     * optional second scratch register is used in Debug ROM to use a different
+     * location for each hart
+     */
+    unsigned foffset = dm->cfg.nscratch > 1u ? hartnum * sizeof(uint32_t) : 0u;
+
+    /*
+     * note: not sure whether this read-modify-write sequence is required,
+     * as it seems that flag values (GO/RESUME) are exclusive; a simple write
+     * might be enough
+     */
+    MemTxResult res;
+    uint32_t flag_bm;
+    hwaddr flagaddr = dm->cfg.dm_phyaddr + A_FLAGS + foffset;
+    res = address_space_rw(dm->as, flagaddr, dm->mta_dm, &flag_bm,
+                           sizeof(flag_bm), false);
+    if (res != MEMTX_OK) {
+        xtrace_riscv_dm_error(dm->soc, "memrx");
+        return CMD_ERR_BUS;
+    }
+    if (set) {
+        flag_bm |= flag_mask;
+    } else {
+        flag_bm &= ~flag_mask;
+    }
+    res = address_space_rw(dm->as, flagaddr, dm->mta_dm, &flag_bm,
+                           sizeof(flag_bm), true);
+    if (res != MEMTX_OK) {
+        xtrace_riscv_dm_error(dm->soc, "memtx");
+        return CMD_ERR_BUS;
+    }
+
+    return CMD_ERR_NONE;
+}
+
+/*
+ * DM status acknowledgement
+ */
+
+static RISCVDMHartState *
+riscv_dm_get_hart_from_id(RISCVDMState *dm, unsigned hartid)
+{
+    /* hart debugger index is not equivalent to the hartid */
+    unsigned hix = 0;
+    while (hix < dm->hart_count) {
+        if (dm->harts[hix].hartid == (target_ulong)hartid) {
+            return &dm->harts[hix];
+        }
+        hix++;
+    }
+    return NULL;
+}
+
+static void riscv_dm_set_busy(RISCVDMState *dm, bool busy)
+{
+    dm->cmd_busy = busy;
+    trace_riscv_dm_busy(dm->soc, busy);
+}
+
+static void riscv_dm_set_cs(RISCVDMState *dm, bool enable)
+{
+    dm->hart->cpu->env.debug_cs = enable;
+    trace_riscv_dm_cs(dm->soc, enable);
+}
+
+static uint32_t riscv_dmi_get_debug_cause(RISCVCPU *cpu)
+{
+    return FIELD_EX32(cpu->env.dcsr, DCSR, CAUSE);
+}
+
+static const char *riscv_dmi_get_debug_cause_name(RISCVCPU *cpu)
+{
+    return DCSR_CAUSE_NAMES[riscv_dmi_get_debug_cause(cpu)];
+}
+
+static void riscv_dm_acknowledge(void *opaque, int irq, int level)
+{
+    /*
+     * Note: this function is called from the VCPU thread, whereas the other
+     * functions are run from the main/iothread.
+     * Nevertheless, all runs w/ iothread_locked, so there should not be race
+     * conditions (TBC...)
+     */
+    RISCVDMState *dm = opaque;
+    RISCVDMHartState *hart;
+    unsigned hartnum;
+
+    assert(bql_locked());
+
+    switch (irq) {
+    case ACK_HALTED:
+        hartnum = (unsigned)level;
+        if ((hart = riscv_dm_get_hart_from_id(dm, hartnum))) {
+            hart->halted = true;
+            uint64_t hbm = 1u << hartnum;
+            if (dm->unavailable_bm & hbm) {
+                qemu_log("%s: %s: an unavailable hart should not be halted\n",
+                         __func__, dm->soc);
+                /* ensure hart can only be a single state */
+                dm->unavailable_bm &= ~hbm;
+            }
+            riscv_dm_set_busy(dm, false);
+            trace_riscv_dm_halted(dm->soc, hart - &dm->harts[0],
+                                  hart->cpu->env.dpc,
+                                  riscv_dmi_get_debug_cause_name(hart->cpu));
+        }
+        break;
+    case ACK_GOING:
+        /* level value is meaningless */
+        if (!dm->to_go_bm) {
+            /* internal error */
+            xtrace_riscv_dm_error(dm->soc, "Go ack w/o action");
+            hart = NULL;
+            break;
+        }
+        while (dm->to_go_bm) {
+            hartnum = __builtin_ctz(dm->to_go_bm);
+            if (hartnum >= dm->hart_count) {
+                /* internal error, should never occur */
+                xtrace_riscv_dm_error(dm->soc, "incoherent go bitmap");
+                hart = NULL;
+            } else {
+                hart = &dm->harts[hartnum];
+                if (riscv_dm_update_flags(dm, hartnum, false,
+                                          R_FLAGS_FLAG_GO_MASK)) {
+                    /* nothing we can do here */
+                    xtrace_riscv_dm_error(dm->soc,
+                                          "unable to lower going flag");
+                    hart = NULL;
+                }
+            }
+            dm->to_go_bm &= ~(1u << hartnum);
+        }
+        trace_riscv_dm_hart_state(dm->soc, hartnum, "debug ongoing");
+        break;
+    case ACK_RESUMING:
+        hartnum = (unsigned)level;
+        if ((hart = riscv_dm_get_hart_from_id(dm, hartnum))) {
+            if (riscv_dm_update_flags(dm, (unsigned)level, false,
+                                      R_FLAGS_FLAG_RESUME_MASK)) {
+                /* nothing we can do here */
+                xtrace_riscv_dm_error(dm->soc, "unable to lower resume flag");
+            }
+            hart->halted = false;
+            hart->resumed = true;
+            uint64_t hbm = 1u << hartnum;
+            if (dm->unavailable_bm & hbm) {
+                qemu_log("%s: %s: an unavailable hart should not be resumed\n",
+                         __func__, dm->soc);
+                /* ensure hart can only be a single state */
+                dm->unavailable_bm &= ~hbm;
+            }
+            bool sstep = (bool)FIELD_EX32(hart->cpu->env.dcsr, DCSR, STEP);
+            riscv_dm_set_cs(dm, sstep);
+            trace_riscv_dm_hart_state(dm->soc, hartnum, "has resumed");
+        }
+        break;
+    case ACK_EXCEPTION:
+        /* level value is meaningless */
+        hart = dm->hart;
+        if (!hart) {
+            /* likely a more serious issue */
+            qemu_log("%s: no selected hart\n", __func__);
+            break;
+        }
+        dm->cmd_err = CMD_ERR_EXCEPTION;
+        riscv_dm_set_cs(dm, false);
+        riscv_dm_set_busy(dm, false);
+        trace_riscv_dm_hart_state(dm->soc, hart - &dm->harts[0],
+                                  "exception in debug");
+        break;
+    default:
+        xtrace_riscv_dm_error(dm->soc, "unknown ack line");
+        return;
+    }
+
+    if (!hart) {
+        xtrace_riscv_dm_error(dm->soc, "no hart to acknowledge");
+        return;
+    }
+}
+
+/*
+ * Instruction generation
+ */
+
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-function"
+
+static uint32_t riscv_dm_rm(uint32_t reg)
+{
+    return reg & 0x1fu;
+}
+
+static uint32_t riscv_dm_csr(uint32_t reg)
+{
+    return reg & 0xfffu;
+}
+
+static uint32_t riscv_dm_r3(uint32_t reg)
+{
+    return reg & 0x7u;
+}
+
+static uint32_t riscv_dm_bm(uint32_t bit)
+{
+    return 1u << bit;
+}
+
+static uint32_t riscv_dm_bmr(uint32_t msb, uint32_t lsb)
+{
+    return ((1u << msb) - 1u) & ~((1u << lsb) - 1u);
+}
+
+static uint32_t riscv_dm_insn_jal(uint32_t rd, uint32_t imm)
+{
+    return (get_field(imm, riscv_dm_bm(20)) << 31u) |
+           (get_field(imm, riscv_dm_bmr(10, 1)) << 21u) |
+           (get_field(imm, riscv_dm_bm(11)) << 20u) |
+           (get_field(imm, riscv_dm_bmr(19, 12)) << 12u) |
+           (riscv_dm_rm(rd) << 7u) | 0x6fu;
+}
+
+static uint32_t riscv_dm_insn_jalr(uint32_t rd, uint32_t rs1, uint32_t offset)
+{
+    return (get_field(offset, riscv_dm_bmr(11, 0)) << 20u) |
+           (riscv_dm_rm(rs1) << 15u) | (0b000u << 12u) |
+           (riscv_dm_rm(rd) << 7u) | 0x67u;
+}
+
+static uint32_t riscv_dm_insn_andi(uint32_t rd, uint32_t rs1, uint32_t imm)
+{
+    return (get_field(imm, riscv_dm_bmr(11, 0)) << 20u) |
+           (riscv_dm_rm(rs1) << 15u) | (0b111u << 12u) |
+           (riscv_dm_rm(rd) << 7u) | 0x13u;
+}
+
+static uint32_t riscv_dm_insn_slli(uint32_t rd, uint32_t rs1, uint32_t shamt)
+{
+    return (get_field(shamt, riscv_dm_bmr(5, 0)) << 20u) |
+           (riscv_dm_rm(rs1) << 15u) | (0b001u << 12u) |
+           (riscv_dm_rm(rd) << 7u) | 0x13u;
+}
+
+static uint32_t riscv_dm_insn_srli(uint32_t rd, uint32_t rs1, uint32_t shamt)
+{
+    return (get_field(shamt, riscv_dm_bmr(5, 0)) << 20u) |
+           (riscv_dm_rm(rs1) << 15u) | (0b101u << 12u) |
+           (riscv_dm_rm(rd) << 7u) | 0x13u;
+}
+
+static uint32_t riscv_dm_insn_load(uint32_t size, uint32_t dst, uint32_t base,
+                                   uint32_t offset)
+{
+    return (get_field(offset, riscv_dm_bmr(11, 0)) << 20u) |
+           (riscv_dm_rm(base) << 15u) | (riscv_dm_r3(size) << 12u) |
+           (riscv_dm_rm(dst) << 7u) | 0x03u;
+}
+
+static uint32_t riscv_dm_insn_auipc(uint32_t rd, uint32_t imm)
+{
+    return (get_field(imm, riscv_dm_bm(20)) << 31u) |
+           (get_field(imm, riscv_dm_bmr(10, 1)) << 21u) |
+           (get_field(imm, riscv_dm_bm(11)) << 20u) |
+           (get_field(imm, riscv_dm_bmr(19, 12)) << 12u) |
+           (riscv_dm_rm(rd) << 7u) | 0x17u;
+}
+
+static uint32_t riscv_dm_insn_store(uint32_t size, uint32_t src, uint32_t base,
+                                    uint32_t offset)
+{
+    return (get_field(offset, riscv_dm_bmr(11, 5)) << 25u) |
+           (riscv_dm_rm(src) << 20u) | (riscv_dm_rm(base) << 15u) |
+           (riscv_dm_r3(size) << 12u) |
+           (get_field(offset, riscv_dm_bmr(4, 0)) << 7u) | 0x23u;
+}
+
+static uint32_t riscv_dm_insn_float_load(uint32_t size, uint32_t dst,
+                                         uint32_t base, uint32_t offset)
+{
+    return (get_field(offset, riscv_dm_bmr(11, 0)) << 20u) |
+           (riscv_dm_rm(base) << 15u) | (riscv_dm_r3(size) << 10u) |
+           (riscv_dm_rm(dst) << 7u) | 0b0000111u;
+}
+
+static uint32_t riscv_dm_insn_float_store(uint32_t size, uint32_t src,
+                                          uint32_t base, uint32_t offset)
+{
+    return (get_field(offset, riscv_dm_bmr(11, 5)) << 25u) |
+           (riscv_dm_rm(src) << 20u) | (riscv_dm_rm(base) << 15u) |
+           (riscv_dm_r3(size) << 12u) |
+           (get_field(offset, riscv_dm_bmr(4, 0)) << 7u) | 0b0100111u;
+}
+
+static uint32_t riscv_dm_insn_csrw(uint32_t csr, uint32_t rs1)
+{
+    return (riscv_dm_csr(csr) << 20u) | (riscv_dm_rm(rs1) << 15u) |
+           (0b001u << 12u) | (riscv_dm_csr(0) << 7u) | 0x73u;
+}
+
+static uint32_t riscv_dm_insn_csrr(uint32_t csr, uint32_t dst)
+{
+    return (riscv_dm_csr(csr) << 20u) | (riscv_dm_rm(0) << 15u) |
+           (0b010u << 12u) | (riscv_dm_csr(dst) << 7u) | 0x73u;
+}
+
+static uint32_t riscv_dm_insn_branch(uint32_t src2, uint32_t src1,
+                                     uint32_t funct3, uint32_t offset)
+{
+    return (get_field(offset, riscv_dm_bm(11)) << 31u) |
+           (get_field(offset, riscv_dm_bmr(9, 4)) << 25u) |
+           (riscv_dm_rm(src2) << 20u) | (riscv_dm_rm(src1) << 15u) |
+           (riscv_dm_r3(funct3) << 12u) |
+           (get_field(offset, riscv_dm_bmr(3, 0)) << 8u) |
+           (get_field(offset, riscv_dm_bm(10)) << 7u) | 0b1100011u;
+}
+
+static uint16_t riscv_dm_insn_c_ebreak(void)
+{
+    return 0x9002u;
+}
+
+static uint32_t riscv_dm_insn_ebreak(void)
+{
+    return 0x00100073u;
+}
+
+static uint32_t riscv_dm_insn_wfi(void)
+{
+    return 0x10500073u;
+}
+
+static uint32_t riscv_dm_insn_nop(void)
+{
+    return 0x00000013u;
+}
+
+static uint32_t riscv_dm_insn_illegal(void)
+{
+    return 0x00000000u;
+}
+
+#pragma GCC diagnostic pop
+
+/*
+ * DM register implementation
+ */
+
+static CmdErr riscv_dm_dmcontrol_write(RISCVDMState *dm, uint32_t value)
+{
+    if (unlikely(!FIELD_EX32(value, DMCONTROL, DMACTIVE))) {
+        /* Debug Module reset */
+        if (!resettable_is_in_reset(OBJECT(dm))) {
+            trace_riscv_dm_reset(dm->soc, "debugger requested DM reset");
+            resettable_assert_reset(OBJECT(dm), RESET_TYPE_COLD);
+        }
+
+        /*
+         * "the dmactive bit is the only bit which can be written to something
+         *  other than its reset value)."
+         * if 0, reset the debug module itself. Do not exit from reset until
+         * DMCONTROL.dmactive is not set.
+         */
+        dm->regs[A_DMCONTROL] &= ~R_DMCONTROL_DMACTIVE_MASK;
+
+        /* do not update DMCONTROL while it is maintained in reset */
+        return CMD_ERR_NONE;
+    }
+
+    if (unlikely(resettable_is_in_reset(OBJECT(dm)))) {
+        trace_riscv_dm_reset(dm->soc, "debugger released DM reset");
+        resettable_release_reset(OBJECT(dm), RESET_TYPE_COLD);
+    }
+
+    bool hasel = (bool)FIELD_EX32(value, DMCONTROL, HASEL);
+
+    uint32_t hartsel = FIELD_EX32(value, DMCONTROL, HARTSELLO) |
+                       (FIELD_EX32(value, DMCONTROL, HARTSELHI)
+                        << R_DMCONTROL_HARTSELLO_LENGTH);
+
+    /* mask any bits that cannot be used for hart selection */
+    hartsel &= dm->hart_count - 1u; /* index start @ 0 */
+
+    dm->hart = NULL;
+
+    /* hart array not supported, ignore any request that uses it */
+    if (!hasel) {
+        uint64_t hbit = 1u << hartsel;
+        if (!(hartsel < dm->hart_count)) {
+            /* max supported harts: 64 */
+            dm->nonexistent_bm |= hbit;
+            /* ensure hart can only be in one state */
+            dm->unavailable_bm &= ~hbit;
+        } else {
+            RISCVDMHartState *hart = &dm->harts[hartsel];
+            dm->hart = hart;
+            g_assert(hart->cpu);
+            CPUState *cs = CPU(hart->cpu);
+
+            if (value & R_DMCONTROL_HARTRESET_MASK) {
+                trace_riscv_dm_hart_reset(dm->soc, cs->cpu_index,
+                                          dm->hart->hartid, "assert");
+                if (!cs->disabled && hart->unlock_reset) {
+                    /*
+                     * if hart is started in active reset, prevent from
+                     * resetting it since it should not be released from
+                     * reset (see below). Allowing reset w/ blocking reset
+                     * release would leave the Resettable API count with
+                     * a forever-locked reset count.
+                     */
+                    resettable_assert_reset(OBJECT(cs), RESET_TYPE_COLD);
+                    dm->unavailable_bm |= hbit;
+                    dm->reset_bm |= hbit;
+                }
+            } else if (dm->reset_bm & hbit) {
+                if (cs->disabled && hart->unlock_reset) {
+                    /*
+                     * if hart is started in active reset, prevent from
+                     * releasing it from reset, otherwise it may start
+                     * executing guest code not yet loaded, leading to an
+                     * exception. It is up to the guest code to manage the
+                     * initial out-of-reset sequence. Not sure how real HW
+                     * manages this corner case.
+                     */
+                    trace_riscv_dm_hart_reset(dm->soc, cs->cpu_index,
+                                              dm->hart->hartid, "release");
+                    resettable_release_reset(OBJECT(cs), RESET_TYPE_COLD);
+                    dm->reset_bm &= ~hbit;
+                }
+            }
+
+            if (dm->unavailable_bm & hbit) {
+                if (!cs->disabled) {
+                    /* hart exited from reset, became available */
+                    dm->unavailable_bm &= ~hbit;
+                    hart->have_reset = true;
+                    hart->halted = false;
+                    trace_riscv_dm_hart_reset(dm->soc, cs->cpu_index,
+                                              dm->hart->hartid, "exited");
+                }
+            }
+        }
+
+        if (value & R_DMCONTROL_ACKHAVERESET_MASK) {
+            unsigned hix = 0;
+            while (hix < dm->hart_count) {
+                dm->harts->have_reset = false;
+                hix++;
+            }
+        }
+    }
+
+
+    RISCVDMCmdErr ret = CMD_ERR_NONE;
+
+    if (unlikely(value & R_DMCONTROL_NDMRESET_MASK)) {
+        /* full system reset (but the Debug Module) */
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+    } else if (dm->hart) {
+        if (!hasel && (hartsel < dm->hart_count)) {
+            uint64_t hartbit = 1u << hartsel;
+            if (value & R_DMCONTROL_HALTREQ_MASK) {
+                if (dm->unavailable_bm & hartbit) {
+                    trace_riscv_dm_unavailable_hart_control(dm->soc, hartsel,
+                                                            "halt");
+                    ret = CMD_ERR_HALT_RESUME;
+                    /* flag the haltreq as pending while unavailable */
+                    dm->haltreq_bm |= hartbit;
+                } else {
+                    riscv_dm_halt_hart(dm, hartsel);
+                }
+            } else {
+                if (dm->hart->halted) {
+                    /*
+                     * resumereq is explicitly ignored if haltreq is set, by the
+                     * specs
+                     */
+                    if (value & R_DMCONTROL_RESUMEREQ_MASK) {
+                        if (dm->unavailable_bm & hartbit) {
+                            trace_riscv_dm_unavailable_hart_control(dm->soc,
+                                                                    hartsel,
+                                                                    "resume");
+                            ret = CMD_ERR_HALT_RESUME;
+                        } else {
+                            /*
+                             * it also clears the resume ack bit for those harts
+                             */
+                            dm->hart->resumed = false;
+                            riscv_dm_resume_hart(dm, hartsel);
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    dm->regs[A_DMCONTROL] &=
+        ~(R_DMCONTROL_HARTSELLO_MASK | R_DMCONTROL_HARTSELHI_MASK |
+          R_DMCONTROL_NDMRESET_MASK | R_DMCONTROL_DMACTIVE_MASK |
+          R_DMCONTROL_HARTRESET_MASK);
+    value &= R_DMCONTROL_NDMRESET_MASK | R_DMCONTROL_DMACTIVE_MASK |
+             R_DMCONTROL_HARTRESET_MASK;
+    /* HARTSELHI never used, since HARTSELLO already encodes up to 1K harts */
+    dm->regs[A_DMCONTROL] = FIELD_DP32(value, DMCONTROL, HARTSELLO, hartsel);
+
+    return ret;
+}
+
+static CmdErr riscv_dm_exec_command(RISCVDMState *dm, uint32_t value)
+{
+    if (!dm->hart) {
+        /* no hart has been selected for debugging */
+        xtrace_riscv_dm_error(dm->soc, "no hart");
+        return CMD_ERR_OTHER;
+    }
+
+    if (!dm->cfg.data_phyaddr) {
+        /*
+         * CSR-shadowed implementation is not supported
+         * abstract command slots are required
+         */
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NOT_SUPPORTED;
+    }
+
+    if (dm->cmd_busy) {
+        xtrace_riscv_dm_error(dm->soc, "already busy");
+        return CMD_ERR_BUSY;
+    }
+
+    if (!dm->hart->halted) {
+        xtrace_riscv_dm_error(dm->soc, "cannot exec command if not halted");
+        return CMD_ERR_HALT_RESUME;
+    }
+
+    /* "This bit is set as soon as command is written" */
+    riscv_dm_set_busy(dm, true);
+
+    int cmdtype = (int)FIELD_EX32(value, COMMAND, CMDTYPE);
+    CmdErr ret;
+    switch (cmdtype) {
+    case CMD_ACCESS_REGISTER:
+        ret = riscv_dm_access_register(dm, value);
+        break;
+    case CMD_QUICK_ACCESS:
+        ret = riscv_dm_quick_access(dm, value);
+        break;
+    case CMD_ACCESS_MEMORY:
+        ret = riscv_dm_access_memory(dm, value);
+        break;
+    default:
+        ret = CMD_ERR_NOT_SUPPORTED;
+        break;
+    }
+
+    if (ret != CMD_ERR_NONE) {
+        xtrace_riscv_dm_error(dm->soc, "cmd exec failed");
+        /* "and [this bit] is not cleared until that command has completed." */
+        riscv_dm_set_busy(dm, false);
+    }
+
+    return ret;
+}
+
+static CmdErr riscv_dm_command_write(RISCVDMState *dm, uint32_t value)
+{
+    if (dm->cmd_err != CMD_ERR_NONE) {
+        /* if cmderr is non-zero, writes to this register are ignored. */
+        return CMD_ERR_NONE;
+    }
+
+    /* save command as it may be repeated w/ abstractauto command */
+    dm->regs[A_COMMAND] = value;
+
+    /* busy status is asserted in riscv_dm_command_write */
+    return riscv_dm_exec_command(dm, value);
+}
+
+static CmdErr riscv_dm_abstractauto_read(RISCVDMState *dm, uint32_t *value)
+{
+    *value = dm->regs[A_ABSTRACTAUTO];
+
+    /*
+     * this function is only for debug, to be removed since simple read out
+     * does not need a dedicated handler
+     */
+    xtrace_riscv_dm_info(dm->soc, "abstract auto read back", *value);
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_abstractauto_write(RISCVDMState *dm, uint32_t value)
+{
+    if (!dm->cfg.abstractauto) {
+        xtrace_riscv_dm_info(dm->soc, "abstractauto support is disabled",
+                             value);
+        /*
+         * Peer should check the content of ABSTRACTAUTO (which is initialized
+         * and stuck to 0) to discover the feature is not supported.
+         *
+         * It seems OpenOCD does not perform this check and resume anyway.
+         */
+        return CMD_ERR_NONE;
+    }
+
+    if (dm->cmd_busy) {
+        xtrace_riscv_dm_error(dm->soc, "already busy");
+        return CMD_ERR_BUSY;
+    }
+
+    xtrace_riscv_dm_info(dm->soc, "abstractauto attempt", value);
+
+    uint32_t mask = (((1u << dm->cfg.data_count) - 1u)
+                     << R_ABSTRACTAUTO_AUTOEXECDATA_SHIFT) |
+                    (((1u << dm->cfg.progbuf_count) - 1u)
+                     << R_ABSTRACTAUTO_AUTOEXECPROGBUF_SHIFT);
+
+    dm->regs[A_ABSTRACTAUTO] = value & mask;
+
+    if (dm->regs[A_ABSTRACTAUTO] != value) {
+        xtrace_riscv_dm_info(dm->soc, "abstractauto selected", value & mask);
+    }
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_dmstatus_read(RISCVDMState *dm, uint32_t *value)
+{
+    unsigned halted = 0u;
+    unsigned running = 0u;
+    unsigned unavail = 0u;
+    unsigned nonexistent = 0u;
+    unsigned resumeack = 0u;
+    unsigned havereset = 0u;
+
+    unsigned hcount = dm->hart_count;
+    /*
+     * "3.4 Hart States
+     *  Every hart that can be selected is in exactly one of the following four
+     *  DM states: non-existent, unavailable, running, or halted."
+     */
+    unsigned hix = 0u;
+    uint64_t mask = 1u;
+    for (; hix < hcount; hix++, mask <<= 1u) {
+        RISCVDMHartState *hart = &dm->harts[hix];
+        CPUState *cs;
+        g_assert(hart->cpu);
+        cs = CPU(hart->cpu);
+        if (dm->nonexistent_bm & mask) {
+            nonexistent += 1;
+            trace_riscv_dm_status(dm->soc, cs->cpu_index, "nonexistent");
+            continue;
+        }
+        /*
+         * The hart may have been started since last poll. There is no way
+         * for the hart to inform the DM in this case, so rely on polling
+         * for now.
+         */
+        if (cs->disabled) {
+            hart->resumed = false;
+            hart->halted = false;
+            dm->unavailable_bm |= mask;
+            dm->nonexistent_bm &= ~mask;
+            unavail += 1;
+            trace_riscv_dm_status(dm->soc, cs->cpu_index, "unavailable");
+            continue;
+        }
+        if (dm->unavailable_bm & mask) {
+            trace_riscv_dm_status(dm->soc, cs->cpu_index, "became available");
+            /* clear the unavailability flag and resume w/ "regular" states */
+            dm->unavailable_bm &= ~mask;
+
+            /*
+             * If a pending haltreq exists for this hart, enter debug mode.
+             *
+             * @todo: This is a workaround for the fact that the current
+             * implementation does not conform to the debug specification. See
+             * e.g. section C.1.4: "When a hart comes out of reset and haltreq
+             * is set, the hart will immediately enter Debug Mode". To support
+             * this the CPU would need to query the DM when it begins executing
+             * instructions, and hence would need a reference to the DM, which
+             * is not ideal.
+             *
+             * For now, we can support most real use cases by exploiting the
+             * fact that reasonable SW will usually send a haltreq and then
+             * repeatedly poll `dmstatus` to see the hart(s) halt. Hence, we
+             * latch haltreqs for unresponsive cores and halt any hart that is
+             * polled as newly available/responsive on a `dmstatus` read.
+             */
+            if (dm->haltreq_bm & mask) {
+                riscv_dm_halt_hart(dm, hix);
+            }
+        }
+        if (hart->resumed) {
+            resumeack += 1;
+            trace_riscv_dm_status(dm->soc, cs->cpu_index, "resumed");
+        }
+        if (hart->have_reset) {
+            trace_riscv_dm_status(dm->soc, cs->cpu_index, "have reset");
+            havereset += 1;
+        }
+        if (hart->halted) {
+            trace_riscv_dm_status(dm->soc, cs->cpu_index, "halted");
+            halted += 1;
+        } else {
+            trace_riscv_dm_status(dm->soc, cs->cpu_index, "running");
+            running += 1;
+        }
+        mask <<= 1u;
+        hix++;
+
+#ifdef TRACE_CPU_STATES
+        RISCVDMStateCache current = {
+            .cpu = {
+                .ix = cs->cpu_index,
+                .halted = cs->halted,
+                .stopped = cs->stopped,
+                .running = cs->running,
+            },
+            .dm = {
+                .halted = halted,
+                .running = running,
+                .unavail = unavail,
+                .nonexistent = nonexistent,
+                .resumeack = resumeack,
+                .havereset = havereset,
+            },
+        };
+        /* NOLINTNEXTLINE */
+        if (memcmp(&current, &hart->dbgcache, sizeof(RISCVDMStateCache))) {
+            qemu_log("%s: %s [%u/%u] [H:%u S:%u R:%u] "
+                     "DM [h:%u r:%u u:%u x:%u a:%u z:%u]\n",
+                     __func__, dm->soc, hart->hartid, hcount, cs->halted,
+                     cs->stopped, cs->running, halted, running, unavail,
+                     nonexistent, resumeack, havereset);
+            hart->dbgcache = current;
+        }
+#endif /* #ifdef TRACE_CPU_STATES */
+    }
+
+    uint32_t val = dm->regs[A_DMSTATUS];
+    val = FIELD_DP32(val, DMSTATUS, ANYHALTED, (halted ? 1 : 0));
+    val = FIELD_DP32(val, DMSTATUS, ANYRUNNING, (running ? 1 : 0));
+    val = FIELD_DP32(val, DMSTATUS, ANYUNAVAIL, (unavail ? 1 : 0));
+    val = FIELD_DP32(val, DMSTATUS, ANYNONEXISTENT, (nonexistent ? 1 : 0));
+    val = FIELD_DP32(val, DMSTATUS, ANYRESUMEACK, (resumeack ? 1 : 0));
+    val = FIELD_DP32(val, DMSTATUS, ANYHAVERESET, (havereset ? 1 : 0));
+    val = FIELD_DP32(val, DMSTATUS, ALLHALTED, (halted == hcount ? 1 : 0));
+    val = FIELD_DP32(val, DMSTATUS, ALLRUNNING, (running == hcount ? 1 : 0));
+    val = FIELD_DP32(val, DMSTATUS, ALLUNAVAIL, (unavail == hcount ? 1 : 0));
+    val = FIELD_DP32(val, DMSTATUS, ALLNONEXISTENT,
+                     (nonexistent == hcount ? 1 : 0));
+    val =
+        FIELD_DP32(val, DMSTATUS, ALLRESUMEACK, (resumeack == hcount ? 1 : 0));
+    val =
+        FIELD_DP32(val, DMSTATUS, ALLHAVERESET, (havereset == hcount ? 1 : 0));
+
+    if (val != dm->regs[A_DMSTATUS]) {
+        /* @todo update for multiple harts */
+        RISCVCPU *cpu = dm->harts[0].cpu;
+        g_assert(cpu);
+        CPUState *cs = CPU(cpu);
+        trace_riscv_dm_dmstatus_read(dm->soc, val, unavail, halted, cs->halted,
+                                     running, cs->running, resumeack,
+                                     cs->stopped, (uint32_t)cpu->env.pc);
+    }
+
+    *value = dm->regs[A_DMSTATUS] = val;
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_sbcs_write(RISCVDMState *dm, uint32_t value)
+{
+    /* mask out the preset, R/O bits */
+    value &= SBCS_WRITE_MASK;
+
+    /* clear error bits (if flagged as W1C) */
+    value &= ~(value & (R_SBCS_SBERROR_MASK | R_SBCS_SBBUSYERROR_MASK));
+
+    dm->regs[A_SBCS] &= ~SBCS_WRITE_MASK;
+    dm->regs[A_SBCS] |= value;
+
+    if (trace_event_get_state(TRACE_RISCV_DM_SBCS_WRITE)) {
+        bool err = (bool)(value & R_SBCS_SBERROR_MASK);
+        bool rdondata = (bool)(value & R_SBCS_SBREADONDATA_MASK);
+        bool autoinc = (bool)(value & R_SBCS_SBAUTOINCREMENT_MASK);
+        bool rdonaddr = (bool)(value & R_SBCS_SBREADONADDR_MASK);
+        bool busyerr = (bool)(value & R_SBCS_SBBUSYERROR_MASK);
+        unsigned access = 1u << FIELD_EX32(value, SBCS, SBACCESS);
+        trace_riscv_dm_sbcs_write(dm->soc, err, busyerr, access, rdonaddr,
+                                  rdondata, autoinc);
+    }
+
+    return CMD_ERR_NONE;
+}
+
+static uint32_t riscv_dm_sysbus_get_byte_count(RISCVDMState *dm)
+{
+    uint32_t size = 1u << FIELD_EX32(dm->regs[A_SBCS], SBCS, SBACCESS);
+    /* LSBs of A_SBCS define supported sizes as a bitmap */
+    if (!(dm->regs[A_SBCS] & size)) {
+        dm->regs[A_SBCS] =
+            FIELD_DP32(dm->regs[A_SBCS], SBCS, SBERROR, SYSBUS_ASIZE);
+        xtrace_riscv_dm_error(dm->soc, "asize");
+        return 0;
+    }
+    return size;
+}
+
+static void riscv_dm_sysbus_set_busy(RISCVDMState *dm, bool busy)
+{
+    dm->regs[A_SBCS] =
+        FIELD_DP32(dm->regs[A_SBCS], SBCS, SBBUSY, (uint32_t)busy);
+}
+
+static void riscv_dm_sysbus_increment_address(RISCVDMState *dm)
+{
+    uint32_t size;
+    if (!(size = riscv_dm_sysbus_get_byte_count(dm))) {
+        /* invalid size case has already been handled by the caller */
+        return;
+    }
+
+    uint32_t old = dm->regs[A_SBADDRESS0];
+    dm->regs[A_SBADDRESS0] += size;
+    if (old > dm->regs[A_SBADDRESS0] &&
+        dm->hart->cpu->env.misa_mxl > MXL_RV32) {
+        dm->regs[A_SBADDRESS1] += 1u;
+    }
+}
+
+static CmdErr riscv_dm_sysbus_read(RISCVDMState *dm)
+{
+    uint32_t size;
+    if (!(size = riscv_dm_sysbus_get_byte_count(dm))) {
+        /*
+         * note: the spec is fuzzy about how sysbus errors should be managed:
+         * should cmderr always be flagged, or is sberror enough? TBC..
+         */
+        return CMD_ERR_NONE;
+    }
+
+    riscv_dm_sysbus_set_busy(dm, true);
+
+    CmdErr ret = CMD_ERR_NONE;
+    MemTxResult res;
+    hwaddr address = (hwaddr)dm->regs[A_SBADDRESS0];
+    if (dm->hart->cpu->env.misa_mxl > MXL_RV32) {
+        address |= ((hwaddr)dm->regs[A_SBADDRESS1]) << 32u;
+    }
+
+    if (address & (size - 1u)) {
+        dm->regs[A_SBCS] =
+            FIELD_DP32(dm->regs[A_SBCS], SBCS, SBERROR, SYSBUS_BADALIGN);
+        xtrace_riscv_dm_error(dm->soc, "align");
+        ret = CMD_ERR_BUS;
+        goto end;
+    }
+
+    /*
+     * if the width of the read access is less than the width of sbdata, the
+     * contents of the remaining high bits may take on any value
+     */
+    uint64_t val64 = 0; /* however 0 is easier for debugging */
+    res = address_space_rw(dm->as, address, dm->mta_sba, &val64, size, false);
+    trace_riscv_dm_sysbus_data_read(dm->soc, address, size, val64, res);
+    if (res != MEMTX_OK) {
+        dm->regs[A_SBCS] =
+            FIELD_DP32(dm->regs[A_SBCS], SBCS, SBERROR, SYSBUS_BADADDR);
+        xtrace_riscv_dm_error(dm->soc, "memtx");
+        ret = CMD_ERR_BUS;
+        goto end;
+    }
+    dm->sbdata = val64;
+end:
+    riscv_dm_sysbus_set_busy(dm, false);
+
+    return ret;
+}
+
+static CmdErr riscv_dm_sbaddress0_write(RISCVDMState *dm, uint32_t value)
+{
+    if (!dm->cfg.sysbus_access) {
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NONE;
+    }
+
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBERROR)) {
+        xtrace_riscv_dm_error(dm->soc, "sberror");
+        return CMD_ERR_NONE;
+    }
+
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBBUSY)) {
+        FIELD_DP32(dm->regs[A_SBCS], SBCS, SBBUSYERROR, 1u);
+        xtrace_riscv_dm_error(dm->soc, "sbbusy");
+        return CMD_ERR_NONE;
+    }
+
+    dm->regs[A_SBADDRESS0] = value;
+    trace_riscv_dm_sbaddr_write(dm->soc, 0, value);
+
+    /*
+     * "When 1, every write to sbaddress0 automatically triggers a system bus
+     *  read at the new address."
+     */
+    if (!FIELD_EX32(dm->regs[A_SBCS], SBCS, SBREADONADDR)) {
+        return CMD_ERR_NONE;
+    }
+
+    CmdErr ret;
+
+    ret = riscv_dm_sysbus_read(dm);
+    /*
+     * "If the read succeeded and sbautoincrement is set,
+     * increment sbaddress."
+     */
+    if ((ret == CMD_ERR_NONE) &&
+        FIELD_EX32(dm->regs[A_SBCS], SBCS, SBAUTOINCREMENT)) {
+        riscv_dm_sysbus_increment_address(dm);
+    }
+
+    return ret;
+}
+
+static CmdErr riscv_dm_sbaddress1_write(RISCVDMState *dm, uint32_t value)
+{
+    if ((!dm->cfg.sysbus_access) || (dm->hart->cpu->env.misa_mxl < MXL_RV64)) {
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NONE;
+    }
+
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBERROR)) {
+        xtrace_riscv_dm_error(dm->soc, "sberror");
+        return CMD_ERR_NONE;
+    }
+
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBBUSY)) {
+        FIELD_DP32(dm->regs[A_SBCS], SBCS, SBBUSYERROR, 1u);
+        xtrace_riscv_dm_error(dm->soc, "sbbusy");
+        return CMD_ERR_NONE;
+    }
+
+    dm->regs[A_SBADDRESS1] = value;
+    trace_riscv_dm_sbaddr_write(dm->soc, 1, value);
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_sbdata0_read(RISCVDMState *dm, uint32_t *value)
+{
+    if (!dm->cfg.sysbus_access) {
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        *value = 0;
+        return CMD_ERR_NONE;
+    }
+
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBERROR) ||
+        FIELD_EX32(dm->regs[A_SBCS], SBCS, SBBUSYERROR)) {
+        xtrace_riscv_dm_error(dm->soc, "sberror");
+        return CMD_ERR_NONE;
+    }
+
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBBUSY)) {
+        FIELD_DP32(dm->regs[A_SBCS], SBCS, SBBUSYERROR, 1u);
+        xtrace_riscv_dm_error(dm->soc, "sbbusy");
+        return CMD_ERR_NONE;
+    }
+
+    /*
+     * "Reads from this register start the following:
+     *  1. Return the data.
+     * i.e. the actual content has been read from the previous call, hence the
+     * sbdata cache
+     */
+    *value = dm->regs[A_SBDATA0] = (uint32_t)dm->sbdata;
+    trace_riscv_dm_sbdata_read(dm->soc, 0, *value);
+
+    CmdErr ret = CMD_ERR_NONE;
+
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBREADONDATA)) {
+        ret = riscv_dm_sysbus_read(dm);
+    }
+
+    /*
+     * "When 1, sbaddress is incremented by the access size (in bytes) selected
+     *  in sbaccess after every system bus access."
+     */
+    if ((ret == CMD_ERR_NONE) &&
+        FIELD_EX32(dm->regs[A_SBCS], SBCS, SBAUTOINCREMENT)) {
+        riscv_dm_sysbus_increment_address(dm);
+    }
+
+    return ret;
+}
+
+static CmdErr riscv_dm_sbdata0_write(RISCVDMState *dm, uint32_t value)
+{
+    if (!dm->cfg.sysbus_access) {
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NONE;
+    }
+
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBERROR) ||
+        FIELD_EX32(dm->regs[A_SBCS], SBCS, SBBUSYERROR)) {
+        xtrace_riscv_dm_error(dm->soc, "sberror");
+        return CMD_ERR_NONE;
+    }
+
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBBUSY)) {
+        FIELD_DP32(dm->regs[A_SBCS], SBCS, SBBUSYERROR, 1u);
+        xtrace_riscv_dm_error(dm->soc, "sbbusy");
+        return CMD_ERR_NONE;
+    }
+
+    uint32_t size;
+    if (!(size = riscv_dm_sysbus_get_byte_count(dm))) {
+        return CMD_ERR_BUS;
+    }
+
+    CmdErr ret = CMD_ERR_NONE;
+
+    riscv_dm_sysbus_set_busy(dm, true);
+    MemTxResult res;
+    hwaddr address = (hwaddr)dm->regs[A_SBADDRESS0];
+    if (dm->hart->cpu->env.misa_mxl > MXL_RV32) {
+        address |= ((hwaddr)dm->regs[A_SBADDRESS1]) << 32u;
+    }
+    if (address & (size - 1u)) {
+        dm->regs[A_SBCS] =
+            FIELD_DP32(dm->regs[A_SBCS], SBCS, SBERROR, SYSBUS_BADALIGN);
+        xtrace_riscv_dm_error(dm->soc, "asize");
+        goto end;
+    }
+    dm->regs[A_SBDATA0] = value;
+    /*
+     * If the width of the read access is less than the width of sbdata, the
+     * contents of the remaining high bits may take on any value
+     */
+    uint64_t val64;
+    val64 = (uint64_t)dm->regs[A_SBDATA0];
+    if (size > sizeof(uint32_t)) {
+        val64 = ((uint64_t)dm->regs[A_SBDATA1]) << 32u;
+    }
+    res = address_space_rw(dm->as, address, dm->mta_sba, &val64, size, true);
+    trace_riscv_dm_sysbus_data_write(dm->soc, address, size, val64, res);
+    if (res != MEMTX_OK) {
+        dm->regs[A_SBCS] =
+            FIELD_DP32(dm->regs[A_SBCS], SBCS, SBERROR, SYSBUS_BADADDR);
+        xtrace_riscv_dm_error(dm->soc, "memtx");
+        ret = CMD_ERR_BUS;
+    }
+end:
+    riscv_dm_sysbus_set_busy(dm, false);
+
+    if ((ret == CMD_ERR_NONE) &&
+        FIELD_EX32(dm->regs[A_SBCS], SBCS, SBAUTOINCREMENT)) {
+        riscv_dm_sysbus_increment_address(dm);
+    }
+
+    return ret;
+}
+
+static CmdErr riscv_dm_sbdata1_read(RISCVDMState *dm, uint32_t *value)
+{
+    if ((!dm->cfg.sysbus_access) || (dm->hart->cpu->env.misa_mxl < MXL_RV64)) {
+        *value = 0;
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NONE;
+    }
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBBUSY)) {
+        FIELD_DP32(dm->regs[A_SBCS], SBCS, SBBUSYERROR, 1u);
+        xtrace_riscv_dm_error(dm->soc, "sbbusy");
+        return CMD_ERR_NONE;
+    }
+
+    *value = dm->regs[A_SBDATA1] = (uint32_t)(dm->sbdata >> 32u);
+    trace_riscv_dm_sbdata_read(dm->soc, 1, *value);
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_sbdata1_write(RISCVDMState *dm, uint32_t value)
+{
+    if ((!dm->cfg.sysbus_access) || (dm->hart->cpu->env.misa_mxl < MXL_RV64)) {
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NONE;
+    }
+    if (FIELD_EX32(dm->regs[A_SBCS], SBCS, SBBUSY)) {
+        FIELD_DP32(dm->regs[A_SBCS], SBCS, SBBUSYERROR, 1u);
+        xtrace_riscv_dm_error(dm->soc, "sbbusy");
+        return CMD_ERR_NONE;
+    }
+
+    dm->regs[A_SBDATA1] = value;
+    trace_riscv_dm_sbdata_write(dm->soc, 1, value);
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_hartinfo_read(RISCVDMState *dm, uint32_t *value)
+{
+    uint32_t val;
+
+    /* note that CSR-shadowing mode is not supported (data access == 0) */
+    val = FIELD_DP32(0, HARTINFO, DATAADDR, dm->cfg.data_phyaddr);
+    val = FIELD_DP32(val, HARTINFO, DATASIZE, dm->cfg.data_count);
+    val = FIELD_DP32(val, HARTINFO, DATAACCESS, dm->cfg.data_phyaddr != 0u);
+    val = FIELD_DP32(val, HARTINFO, NSCRATCH, dm->cfg.nscratch);
+
+    *value = dm->regs[A_HARTINFO] = val;
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_abstractcs_read(RISCVDMState *dm, uint32_t *value)
+{
+    uint32_t val;
+
+    val = FIELD_DP32(0, ABSTRACTCS, DATACOUNT, dm->cfg.data_count);
+    val = FIELD_DP32(val, ABSTRACTCS, PROGBUFSIZE, dm->cfg.progbuf_count);
+    val = FIELD_DP32(val, ABSTRACTCS, BUSY, (uint32_t)dm->cmd_busy);
+    val = FIELD_DP32(val, ABSTRACTCS, CMDERR, (uint32_t)dm->cmd_err);
+
+    *value = dm->regs[A_ABSTRACTCS] = val;
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_abstractcs_write(RISCVDMState *dm, uint32_t value)
+{
+    if (dm->cmd_busy) {
+        xtrace_riscv_dm_error(dm->soc, "already busy");
+        return CMD_ERR_BUSY;
+    }
+
+    /*
+     * The bits in this field remain set until they are cleared by writing 1 to
+     * them -> it is not clear whether any bit clears all cmderr bits or if
+     * the error code may be changed when only some of them are cleared out...
+     */
+    uint32_t cmderr_mask = (value & R_ABSTRACTCS_CMDERR_MASK);
+    value &= ~cmderr_mask;
+
+    dm->regs[A_ABSTRACTCS] = value;
+    dm->cmd_err &= ~(cmderr_mask >> R_ABSTRACTCS_CMDERR_SHIFT);
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_haltsum0_read(RISCVDMState *dm, uint32_t *value)
+{
+    unsigned hix = 0;
+    unsigned halted_bm = 0;
+
+    while (hix < dm->hart_count) {
+        if (dm->harts[hix].halted) {
+            halted_bm = 1u << hix;
+        }
+    }
+
+    *value = dm->regs[A_HALTSUM0] = halted_bm;
+    return CMD_ERR_NONE;
+}
+
+/* this function contains code retrieved from PUL dm_mem.sv file */
+static CmdErr riscv_dm_access_register(RISCVDMState *dm, uint32_t value)
+{
+    /*
+     * for now, only LE-RISC-V and LE-hosts are supported,
+     * RV128 are not supp.
+     */
+    RISCVCPU *cpu = dm->hart->cpu;
+    CPURISCVState *env = &cpu->env;
+
+    if (!dm->cfg.progbuf_phyaddr ||
+        dm->cfg.abstractcmd_count < RISCVDM_ABSTRACTDATA_SLOTS) {
+        /* abstract command slots and progbuf address are required */
+        xtrace_riscv_dm_error(dm->soc, "no support");
+        return CMD_ERR_NOT_SUPPORTED;
+    }
+
+    unsigned regno = (unsigned)FIELD_EX32(value, COMMAND, REG_REGNO);
+    bool write = (bool)FIELD_EX32(value, COMMAND, REG_WRITE);
+    bool transfer = (bool)FIELD_EX32(value, COMMAND, REG_TRANSFER);
+    bool postexec = (bool)FIELD_EX32(value, COMMAND, REG_POSTEXEC);
+    bool aarpostinc = (bool)FIELD_EX32(value, COMMAND, REG_AARPOSTINCREMENT);
+    unsigned aarsize = (unsigned)FIELD_EX32(value, COMMAND, REG_AARSIZE);
+    unsigned maxarr = env->misa_mxl + 1u;
+
+    if (transfer) {
+        if (aarsize > maxarr) {
+            /*
+             * If aarsize specifies a size larger than the register’s actual
+             * size, then the access must fail.
+             */
+            trace_riscv_dm_aarsize_error(dm->soc, aarsize);
+            return CMD_ERR_NOT_SUPPORTED;
+        }
+    }
+
+    uint32_t abscmd[RISCVDM_ABSTRACTDATA_SLOTS];
+    memset(abscmd, 0u, sizeof(abscmd)); /* fill up the buf with illegal insns */
+
+    /*
+     * if ac_ar.transfer is not set then we can take a shortcut to the program
+     * buffer, load debug module base address into a0, this is shared among all
+     * commands
+     */
+    abscmd[1u] = (dm->cfg.nscratch > 1u) ? riscv_dm_insn_auipc(GPR_A0, 0) :
+                                           riscv_dm_insn_nop();
+    /* clr lowest 12b -> DM base offset */
+    abscmd[2u] = (dm->cfg.nscratch > 1u) ?
+                     riscv_dm_insn_srli(GPR_A0, GPR_A0, 12u) :
+                     riscv_dm_insn_nop();
+    abscmd[3u] = (dm->cfg.nscratch > 1u) ?
+                     riscv_dm_insn_slli(GPR_A0, GPR_A0, 12u) :
+                     riscv_dm_insn_nop();
+    abscmd[4u] = riscv_dm_insn_nop();
+    abscmd[5u] = riscv_dm_insn_nop();
+    abscmd[6u] = riscv_dm_insn_nop();
+    abscmd[7u] = riscv_dm_insn_nop();
+    abscmd[8u] = (dm->cfg.nscratch > 1u) ?
+                     riscv_dm_insn_csrr(CSR_DSCRATCH1, GPR_A0) :
+                     riscv_dm_insn_nop();
+    abscmd[9u] = riscv_dm_insn_ebreak();
+
+    bool unsupported = false;
+    /*
+     * Depending on whether we are at the zero page or not we either use `x0` or
+     * `x10/a0`
+     */
+    uint32_t regaddr = dm->cfg.dm_phyaddr == 0u ? GPR_ZERO : GPR_A0;
+
+    if ((aarsize <= maxarr) && transfer) {
+        if (write) {
+            /* store a0 in dscratch1 */
+            abscmd[0u] = (dm->cfg.nscratch > 1u) ?
+                             riscv_dm_insn_csrw(CSR_DSCRATCH1, GPR_A0) :
+                             riscv_dm_insn_nop();
+            /* this range is reserved */
+            if (regno >= 0xc000) {
+                abscmd[0u] = riscv_dm_insn_ebreak(); /* leave asap */
+                unsupported = true;
+                /*
+                 * A0 access needs to be handled separately, as we use A0 to
+                 * load the DM address offset need to access DSCRATCH1 in this
+                 * case
+                 */
+            } else if ((dm->cfg.nscratch > 1u) && (regno == 0x1000u + GPR_A0)) {
+                xtrace_reg(dm->soc, "write GPR", regno, 0x1000u);
+                /* store s0 in dscratch */
+                abscmd[4u] = riscv_dm_insn_csrw(CSR_DSCRATCH0, GPR_S0);
+                /* load from data register */
+                abscmd[5u] = riscv_dm_insn_load(aarsize, GPR_S0, regaddr,
+                                                dm->cfg.data_phyaddr);
+                /* and store it in the corresponding CSR */
+                abscmd[6u] = riscv_dm_insn_csrw(CSR_DSCRATCH1, GPR_S0);
+                /* restore s0 again from dscratch */
+                abscmd[7u] = riscv_dm_insn_csrr(CSR_DSCRATCH0, GPR_S0);
+                /* GPR/FPR access */
+            } else if (regno & 0x1000u) {
+                /*
+                 * determine whether we want to access the floating point
+                 * register or not
+                 */
+                if (regno & 0x20u) {
+                    xtrace_reg(dm->soc, "write FPR", regno, 0x1020u);
+                    abscmd[4u] =
+                        riscv_dm_insn_float_load(aarsize, riscv_dm_rm(regno),
+                                                 regaddr, dm->cfg.data_phyaddr);
+                } else {
+                    xtrace_reg(dm->soc, "write GPR", regno, 0x1000u);
+                    abscmd[4u] =
+                        riscv_dm_insn_load(aarsize, riscv_dm_rm(regno), regaddr,
+                                           dm->cfg.data_phyaddr);
+                }
+                /* CSR access */
+            } else {
+                /* data register to CSR */
+                xtrace_reg(dm->soc, "write CSR", regno, 0u);
+                /* store s0 in dscratch */
+                abscmd[4u] = riscv_dm_insn_csrw(CSR_DSCRATCH0, GPR_S0);
+                /* load from data register */
+                abscmd[5u] = riscv_dm_insn_load(aarsize, GPR_S0, regaddr,
+                                                dm->cfg.data_phyaddr);
+                /* and store it in the corresponding CSR */
+                abscmd[6u] = riscv_dm_insn_csrw(riscv_dm_csr(regno), GPR_S0);
+                /* restore s0 again from dscratch */
+                abscmd[7u] = riscv_dm_insn_csrr(CSR_DSCRATCH0, GPR_S0);
+            }
+        } else { /* read */
+
+            /* store a0 in dscratch1 */
+            abscmd[0u] = (dm->cfg.nscratch > 1u) ?
+                             riscv_dm_insn_csrw(CSR_DSCRATCH1, regaddr) :
+                             riscv_dm_insn_nop();
+            /* this range is reserved */
+            if (regno >= 0xc000) {
+                abscmd[0u] = riscv_dm_insn_ebreak(); /* leave asap */
+                unsupported = true;
+                /* A0 access needs to be handled separately, as we use A0 to
+                 * load the DM address offset need to access DSCRATCH1 in this
+                 * case
+                 */
+            } else if ((dm->cfg.nscratch > 1u) && (regno == 0x1000u + GPR_A0)) {
+                xtrace_reg(dm->soc, "read GPR", regno, 0x1000u);
+                /* store s0 in dscratch */
+                abscmd[4u] = riscv_dm_insn_csrw(CSR_DSCRATCH0, GPR_S0);
+                /* read value from CSR into s0 */
+                abscmd[5u] = riscv_dm_insn_csrr(CSR_DSCRATCH1, GPR_S0);
+                /* and store s0 into data section */
+                abscmd[6u] = riscv_dm_insn_store(aarsize, GPR_S0, regaddr,
+                                                 dm->cfg.data_phyaddr);
+                /* restore s0 again from dscratch */
+                abscmd[7u] = riscv_dm_insn_csrr(CSR_DSCRATCH0, GPR_S0);
+                /* GPR/FPR access */
+            } else if (regno & 0x1000u) {
+                /*
+                 * determine whether we want to access the floating point
+                 * register or not
+                 */
+                if (regno & 0x20u) {
+                    xtrace_reg(dm->soc, "read FPR", regno, 0x1020u);
+                    abscmd[4u] =
+                        riscv_dm_insn_float_store(aarsize, riscv_dm_rm(regno),
+                                                  regaddr,
+                                                  dm->cfg.data_phyaddr);
+                } else {
+                    xtrace_reg(dm->soc, "read GPR", regno, 0x1000u);
+                    abscmd[4u] =
+                        riscv_dm_insn_store(aarsize, riscv_dm_rm(regno),
+                                            regaddr, dm->cfg.data_phyaddr);
+                }
+                /* CSR access */
+            } else {
+                /* CSR register to data */
+                xtrace_reg(dm->soc, "read CSR", regno, 0u);
+                /* store s0 in dscratch */
+                abscmd[4u] = riscv_dm_insn_csrw(CSR_DSCRATCH0, GPR_S0);
+                /* read value from CSR into s0 */
+                abscmd[5u] = riscv_dm_insn_csrr(riscv_dm_csr(regno), GPR_S0);
+                /* and store s0 into data section */
+                abscmd[6u] = riscv_dm_insn_store(aarsize, GPR_S0, regaddr,
+                                                 dm->cfg.data_phyaddr);
+                /* restore s0 again from dscratch */
+                abscmd[7u] = riscv_dm_insn_csrr(CSR_DSCRATCH0, GPR_S0);
+            }
+        }
+    } else if ((aarsize > maxarr) || aarpostinc) {
+        /*
+         * this should happend when e.g. aarsize > maxaar
+         * Openocd will try to do an access with aarsize=64 bits
+         * first before falling back to 32 bits.
+         */
+        abscmd[0u] = riscv_dm_insn_ebreak(); /* leave asap */
+        unsupported = true;
+    }
+    if (postexec && !unsupported) {
+        /* issue a nop, we will automatically run into the program buffer */
+        abscmd[9u] = riscv_dm_insn_nop();
+    }
+
+    if (unsupported) {
+        xtrace_riscv_dm_error(dm->soc, "unsupported abstract command");
+    }
+
+    /* copy the abstract command opcode into executable memory */
+    hwaddr abscmd_addr = dm->cfg.progbuf_phyaddr - sizeof(abscmd);
+
+    if (MEMTX_OK != address_space_rw(dm->as, abscmd_addr, dm->mta_dm,
+                                     &abscmd[0], sizeof(abscmd), true)) {
+        xtrace_riscv_dm_error(dm->soc, "write to abtract commands to mem");
+        return CMD_ERR_BUS;
+    }
+
+    for (unsigned ix = 0; ix < RISCVDM_ABSTRACTDATA_SLOTS; ix++) {
+        trace_riscv_dm_abstract_cmd(dm->soc,
+                                    abscmd_addr + ix * sizeof(uint32_t),
+                                    abscmd[ix]);
+    }
+
+    /* generate the "whereto" instruction */
+    uint32_t offset;
+    if (!transfer && postexec) {
+        offset = dm->cfg.progbuf_phyaddr - dm->cfg.whereto_phyaddr;
+    } else {
+        offset = abscmd_addr - dm->cfg.whereto_phyaddr;
+    }
+    uint32_t whereto = riscv_dm_insn_jal(GPR_ZERO, offset);
+
+    CmdErr res;
+    if ((res = riscv_dm_write_whereto(dm, whereto))) {
+        return res;
+    };
+
+    /* now kick off execution */
+    unsigned hartsel = (unsigned)(dm->hart - &dm->harts[0]);
+    CPUState *cs = CPU(dm->hart->cpu);
+    trace_riscv_dm_change_hart(dm->soc, "GO", hartsel, cs->halted, cs->running,
+                               cs->stopped, dm->hart->resumed);
+    dm->to_go_bm |= 1u << hartsel;
+    res = riscv_dm_update_flags(dm, hartsel, true, R_FLAGS_FLAG_GO_MASK);
+    if (res != CMD_ERR_NONE) {
+        xtrace_riscv_dm_error(dm->soc, "cannot go");
+        dm->to_go_bm &= ~(1u << hartsel);
+        return res;
+    }
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_access_memory(RISCVDMState *dm, uint32_t value)
+{
+    /*
+     * Arg Width | arg0/ret val |    arg1  |  arg2     |
+     * ----------+--------------+----------+-----------+
+     *        32 | data0        | data1    | data2     |
+     *        64 | data0..1     | data2..3 | data4..5  |
+     *       128 | data0..3     | data4..7 | data8..11 |
+     * The Argument Width of the Access Memory abstract command is determined by
+     * DXLEN, and not by aamsize.
+     *   - arg0 is the data
+     *   - arg1 is the address
+     */
+    RISCVCPU *cpu = dm->hart->cpu;
+    CPURISCVState *env = &cpu->env;
+
+    bool write = (bool)FIELD_EX32(value, COMMAND, MEM_WRITE);
+    bool aampostinc = (bool)FIELD_EX32(value, COMMAND, MEM_AAMPOSTINCREMENT);
+    unsigned aamsize = (unsigned)FIELD_EX32(value, COMMAND, REG_AAMSIZE);
+    bool virt = (bool)FIELD_EX32(value, COMMAND, MEM_AAMVIRTUAL);
+    hwaddr size = 1u << aamsize;
+
+    if (aamsize > env->misa_mxl + 1u) {
+        xtrace_riscv_dm_error(dm->soc, "ammsize");
+        return CMD_ERR_NOT_SUPPORTED;
+    }
+
+    unsigned argwidth = env->misa_mxl; /* in 32-bit word count */
+    unsigned datawcount = aamsize > 2u ? 2u : 1u;
+    /* zero-init is only useful to help w/ debug on RV32 */
+    hwaddr val = 0u;
+    hwaddr addr = 0u;
+    CmdErr res;
+    if ((res = riscv_dm_read_absdata(dm, argwidth, argwidth, &addr))) {
+        xtrace_riscv_dm_error(dm->soc, "read mem address (arg1)");
+        return res;
+    }
+    if (virt) {
+        hwaddr phyaddr;
+        phyaddr = riscv_cpu_get_phys_page_debug(CPU(cpu), addr);
+        if (phyaddr == -1) {
+            xtrace_riscv_dm_error(dm->soc, "virtual mem");
+            return CMD_ERR_BUS;
+        }
+        addr = phyaddr;
+    }
+    if (write) {
+        /* read value from arg0 */
+        if ((res = riscv_dm_read_absdata(dm, 0, datawcount, &val))) {
+            xtrace_riscv_dm_error(dm->soc, "read mem data (arg0)");
+            return res;
+        }
+        /* store value into main memory */
+        if (MEMTX_OK !=
+            address_space_rw(dm->as, addr, dm->mta_sba, &val, size, true)) {
+            xtrace_riscv_dm_error(dm->soc, "write to mem");
+            return CMD_ERR_BUS;
+        }
+    } else {
+        /* read value from main memory */
+        if (MEMTX_OK !=
+            address_space_rw(dm->as, addr, dm->mta_sba, &val, size, false)) {
+            xtrace_riscv_dm_error(dm->soc, "read from mem");
+            return CMD_ERR_BUS;
+        }
+        /* write value to arg0 */
+        if ((res = riscv_dm_write_absdata(dm, 0, datawcount, val))) {
+            xtrace_riscv_dm_error(dm->soc, "write mem data (arg0)");
+            return res;
+        }
+    }
+
+    if (aampostinc) {
+        addr += argwidth << 2u; /* convert to bytes */
+        if (riscv_dm_write_absdata(dm, argwidth, argwidth, addr)) {
+            xtrace_riscv_dm_error(dm->soc, "address postinc");
+        }
+    }
+
+    riscv_dm_set_busy(dm, false);
+
+    return CMD_ERR_NONE;
+}
+
+static CmdErr riscv_dm_quick_access(RISCVDMState *dm, uint32_t value)
+{
+    (void)dm;
+    (void)value;
+
+    return CMD_ERR_NOT_SUPPORTED;
+}
+
+/*
+ * Debugger implementation
+ */
+
+static void riscv_dm_ensure_running(RISCVDMState *dm)
+{
+    /*
+     * Hang on: "halted" has many different meanings, depending on the context.
+     *
+     * There are -at least- three indicators that a hart is not running:
+     *   1. CPU may be halted: for example, it enters a WFI: `CPUState.halted`
+     *   2. CPU may be stopped: `CPUState.stopped`, which differs from
+     *      `CPUState.stop`
+     *   3. VM may be not running: global VM state `current_run_state` !=
+     *      `RUN_STATE_RUNNING`, which is common to all vCPUs.
+     *
+     * Debug module adds just another "halted" state which means the CPU is ...
+     * actively running the park loop of the Debug ROM. This is the only state
+     * in this file that is considered as the "halted" state of a hart.
+     *
+     * As the debug module needs the vCPU to be actively running to execute
+     * Debug ROM code, ensure that the VM is running and that the vCPU is
+     * running whenever the remote debugger requests to "halt" (run the park
+     * loop) or "resume" (run the guest code).
+     */
+
+    if (runstate_needs_reset()) {
+        xtrace_riscv_dm_error(dm->soc, "cannot change VM now");
+        return;
+    }
+
+    RISCVCPU *cpu = dm->hart->cpu;
+    CPUState *cs = CPU(cpu);
+
+    cpu_synchronize_state(cs);
+
+    if (!runstate_is_running()) {
+        /*
+         * the VM may be stopped
+         * (for example, at startup, waiting for debugger initial request)
+         */
+        xtrace_riscv_dm_info(dm->soc, "(re)starting the VM", 0);
+        vm_prepare_start(false);
+        vm_start();
+    }
+
+    if (cs->stopped && !cs->disabled) {
+        cpu_resume(cs);
+    }
+}
+
+
+static void riscv_dm_halt_hart(RISCVDMState *dm, unsigned hartsel)
+{
+    RISCVCPU *cpu = dm->harts[hartsel].cpu;
+    CPUState *cs = CPU(cpu);
+
+    trace_riscv_dm_change_hart(dm->soc, "HALT", hartsel, cs->halted,
+                               cs->running, cs->stopped, dm->hart->resumed);
+
+    /* Note: NMI are not yet supported */
+    cpu_exit(cs);
+    dm->haltreq_bm &= ~(1u << hartsel);
+    /* not sure if the real HW clear this flag on halt */
+    dm->hart->resumed = false;
+    riscv_dm_set_cs(dm, true);
+    riscv_cpu_store_debug_cause(cs, DCSR_CAUSE_HALTREQ);
+    cpu_interrupt(cs, CPU_INTERRUPT_DEBUG);
+    /* vCPU should always be "running" - halt mode runs the park loop */
+    riscv_dm_ensure_running(dm);
+}
+
+static void riscv_dm_resume_hart(RISCVDMState *dm, unsigned hartsel)
+{
+    RISCVCPU *cpu = dm->harts[hartsel].cpu;
+    CPUState *cs = CPU(cpu);
+
+    trace_riscv_dm_change_hart(dm->soc, "RESUME", hartsel, cs->halted,
+                               cs->running, cs->stopped, dm->hart->resumed);
+
+    /* generate "whereto" opcode */
+    uint32_t offset =
+        dm->cfg.rom_phyaddr + dm->cfg.resume_offset - dm->cfg.whereto_phyaddr;
+    uint32_t whereto = riscv_dm_insn_jal(GPR_ZERO, offset);
+    if (MEMTX_OK !=
+        address_space_rw(dm->as, dm->cfg.whereto_phyaddr, dm->mta_dm, &whereto,
+                         sizeof(whereto), true)) {
+        xtrace_riscv_dm_error(dm->soc, "write whereto to mem");
+        return;
+    }
+
+    CPURISCVState *env = &cpu->env;
+    bool sstep = (bool)FIELD_EX32(env->dcsr, DCSR, STEP);
+
+    if (sstep) {
+        /*
+         * it is not possible to single-step on an ebreak instruction
+         * disable single stepping on such an error condition
+         * note that the debugger is in charge of updating DPC on the next
+         * instruction whenever an ebreak instruction is reached.
+         */
+        uint32_t insn = cpu_ldl_code(env, env->dpc);
+        if ((insn == riscv_dm_insn_ebreak()) ||
+            (((uint16_t)insn) == riscv_dm_insn_c_ebreak())) {
+            /* cannot single-step an ebreak/c.break instruction */
+            xtrace_riscv_dm_error(dm->soc, "clear single-step on ebreak");
+            env->dcsr = FIELD_DP32(env->dcsr, DCSR, STEP, 0);
+        }
+    }
+
+    if (riscv_dm_update_flags(dm, hartsel, true, R_FLAGS_FLAG_RESUME_MASK)) {
+        xtrace_riscv_dm_error(dm->soc, "cannot resume");
+    }
+
+    cpu_exit(cs);
+    cpu_reset_interrupt(cs, CPU_INTERRUPT_DEBUG);
+
+    const char *cause = riscv_dmi_get_debug_cause_name(cpu);
+    trace_riscv_dm_resume_hart(dm->soc, sstep, cause);
+
+    riscv_dm_ensure_running(dm);
+}
+
+static int riscv_dm_discover_cpus(RISCVDMState *dm)
+{
+    unsigned hartix = 0;
+    CPUState *cs;
+    /* NOLINTNEXTLINE */
+    CPU_FOREACH(cs) {
+        /* skips CPUs/harts that are not associated to this DM */
+        bool skip = true;
+        for (unsigned ix = 0; ix < dm->hart_count; ix++) {
+            if (cs->cpu_index == dm->cpu_idx[ix]) {
+                skip = false;
+                break;
+            }
+        }
+        if (skip) {
+            continue;
+        }
+        if (hartix >= dm->hart_count) {
+            error_setg(&error_fatal, "Incoherent hart count");
+        }
+        RISCVDMHartState *hart = &dm->harts[hartix];
+        RISCVCPU *cpu = RISCV_CPU(cs);
+        if (!hart->cpu) {
+            hart->cpu = cpu;
+        } else {
+            /* associated CPU should be invariant across resets */
+            g_assert(hart->cpu == cpu);
+        }
+        hart->hartid = hart->cpu->env.mhartid;
+        hart->unlock_reset = !cs->disabled;
+        if (!dm->as) {
+            /* address space is unknown till first hart is realized */
+            dm->as = cs->as;
+        } else if (dm->as != cs->as) {
+            /* for now, all harts should share the same address space */
+            error_setg(&error_fatal, "Incoherent address spaces");
+        }
+        hartix++;
+    }
+
+    return hartix ? 0 : -1;
+}
+
+static const Property riscv_dm_properties[] = {
+    DEFINE_PROP_LINK("dtm", RISCVDMState, dtm, TYPE_RISCV_DTM, RISCVDTMState *),
+    DEFINE_PROP_ARRAY("hart", RISCVDMState, hart_count, cpu_idx,
+                      qdev_prop_uint32, uint32_t),
+    DEFINE_PROP_UINT32("dmi_addr", RISCVDMState, cfg.dmi_addr, 0),
+    DEFINE_PROP_UINT32("dmi_next", RISCVDMState, cfg.dmi_next, 0),
+    DEFINE_PROP_UINT32("nscratch", RISCVDMState, cfg.nscratch, 1u),
+    DEFINE_PROP_UINT32("progbuf_count", RISCVDMState, cfg.progbuf_count, 0),
+    DEFINE_PROP_UINT32("data_count", RISCVDMState, cfg.data_count, 2u),
+    DEFINE_PROP_UINT32("abstractcmd_count", RISCVDMState, cfg.abstractcmd_count,
+                       0),
+    DEFINE_PROP_UINT64("dm_phyaddr", RISCVDMState, cfg.dm_phyaddr, 0),
+    DEFINE_PROP_UINT64("rom_phyaddr", RISCVDMState, cfg.rom_phyaddr, 0),
+    DEFINE_PROP_UINT64("whereto_phyaddr", RISCVDMState, cfg.whereto_phyaddr, 0),
+    DEFINE_PROP_UINT64("data_phyaddr", RISCVDMState, cfg.data_phyaddr, 0),
+    DEFINE_PROP_UINT64("progbuf_phyaddr", RISCVDMState, cfg.progbuf_phyaddr, 0),
+    DEFINE_PROP_UINT16("resume_offset", RISCVDMState, cfg.resume_offset, 0),
+    DEFINE_PROP_BOOL("sysbus_access", RISCVDMState, cfg.sysbus_access, true),
+    /* beware that OpenOCD (RISC-V 2024/04) assumes this is always supported */
+    DEFINE_PROP_BOOL("abstractauto", RISCVDMState, cfg.abstractauto, true),
+    DEFINE_PROP_UINT64("mta_dm", RISCVDMState, cfg.mta_dm, RISCVDM_DEFAULT_MTA),
+    DEFINE_PROP_UINT64("mta_sba", RISCVDMState, cfg.mta_sba,
+                       RISCVDM_DEFAULT_MTA),
+    DEFINE_PROP_BOOL("enable", RISCVDMState, cfg.enable, true),
+};
+
+static void riscv_dm_reset_enter(Object *obj, ResetType type)
+{
+    RISCVDMClass *c = RISCV_DM_GET_CLASS(obj);
+    RISCVDMState *dm = RISCV_DM(obj);
+
+    trace_riscv_dm_reset(dm->soc, "enter");
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    g_assert(dm->dtm != NULL);
+    RISCVDTMClass *dtmc = RISCV_DTM_GET_CLASS(OBJECT(dm->dtm));
+    dm->dtm_ok =
+        (*dtmc->register_dm)(DEVICE(dm->dtm), RISCV_DEBUG_DEVICE(obj),
+                             dm->cfg.dmi_addr, DM_REG_COUNT, dm->cfg.enable);
+
+    for (unsigned ix = 0; ix < DM_REG_COUNT; ix++) {
+        if (ix == A_DMCONTROL) {
+            dm->regs[ix] = RISCVDM_DMS[ix].value & ~R_DMCONTROL_DMACTIVE_MASK;
+            continue;
+        }
+        if (ix == A_NEXTDM) {
+            continue;
+        }
+        dm->regs[ix] = RISCVDM_DMS[ix].value;
+    }
+
+    /* Hart statuses are updated on reset_exit */
+    dm->nonexistent_bm = 0;
+    dm->unavailable_bm = 0;
+    dm->haltreq_bm = 0;
+    dm->reset_bm = 0;
+    dm->address = 0;
+    dm->to_go_bm = 0;
+    for (unsigned ix = 0; ix < dm->hart_count; ix++) {
+        RISCVDMHartState *hart = &dm->harts[ix];
+        /*
+         * preserve CPU reference, as DM may be queried while it is maintained
+         * for current status. Hart association never changes anyway.
+         */
+        RISCVCPU *cpu = hart->cpu;
+        memset(hart, 0, sizeof(RISCVDMHartState));
+        hart->cpu = cpu;
+    }
+}
+
+static void riscv_dm_reset_exit(Object *obj, ResetType type)
+{
+    RISCVDMClass *c = RISCV_DM_GET_CLASS(obj);
+    RISCVDMState *dm = RISCV_DM(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    trace_riscv_dm_reset(dm->soc, "exit");
+
+    /* generate hart association */
+    if (riscv_dm_discover_cpus(dm)) {
+        error_setg(&error_fatal, "Cannot identify harts");
+    }
+
+    riscv_dm_set_busy(dm, false);
+
+    bool is_running = runstate_is_running();
+
+    for (unsigned ix = 0; ix < dm->hart_count; ix++) {
+        RISCVDMHartState *hart = &dm->harts[ix];
+        RISCVCPU *cpu = hart->cpu;
+        if (!cpu) {
+            continue;
+        }
+
+        CPURISCVState *env = &cpu->env;
+        if (!env) {
+            continue;
+        }
+
+        /*
+         * inform the hart a remote debugger/debugger module is
+         * available, as it changes how debug exceptions and trigger CSRs
+         * behave
+         */
+        env->debug_dm = dm->dtm_ok;
+
+        /* External debug support exists */
+        env->dcsr = FIELD_DP32(env->dcsr, DCSR, XDEBUGVER, 4u);
+        /* No support for MPRV */
+        env->dcsr = FIELD_DP32(env->dcsr, DCSR, MPRVEN, 0u);
+        /* Initial value */
+        env->dcsr = FIELD_DP32(env->dcsr, DCSR, STOPTIME, 0u);
+        env->dcsr = FIELD_DP32(env->dcsr, DCSR, STOPCOUNT, 0u);
+
+        CPUState *cs = CPU(cpu);
+        if (cs->halted) {
+            if (cs->disabled) {
+                dm->unavailable_bm |= 1u << ix;
+                trace_riscv_dm_unavailable(dm->soc, cs->cpu_index);
+                /* a hart cannot be halted and unavailable at once */
+                hart->halted = false;
+            } else {
+                /* hart not explicitly halted, ready to run in parked mode */
+                hart->halted = false;
+            }
+        }
+
+        /*
+         * fix DCSR at VM initialization:
+         * 1. if the VM is started as soon as QEMU is started, do nothing
+         * 2. if the VM is idled when QEMU is started, flag all harts as
+         *    "halt-on-reset" as the debugger requires a reason for the
+         *    harts being initially stopped
+         */
+        if (is_running) {
+            /* called from vm_state change, running */
+            if (riscv_dmi_get_debug_cause(cpu) == DCSR_CAUSE_RESETHALTREQ) {
+                env->dcsr = FIELD_DP32(env->dcsr, DCSR, CAUSE, DCSR_CAUSE_NONE);
+            }
+        } else {
+            /* called from DMI reset */
+            if (riscv_dmi_get_debug_cause(cpu) == DCSR_CAUSE_NONE) {
+                env->dcsr =
+                    FIELD_DP32(env->dcsr, DCSR, CAUSE, DCSR_CAUSE_RESETHALTREQ);
+            }
+        }
+
+        xtrace_riscv_dm_info(dm->soc, "cause", riscv_dmi_get_debug_cause(cpu));
+    }
+
+    /* TODO: should we clear progbug, absdata, ...? */
+
+    /* consider all harts for this DM share the same capabilities */
+    CPURISCVState *env = &dm->harts[0u].cpu->env;
+
+    uint32_t value = 0u;
+    if (dm->cfg.sysbus_access && env) {
+        value = FIELD_DP32(value, SBCS, SBVERSION, RISCV_DEBUG_SB_VERSION);
+        value = FIELD_DP32(value, SBCS, SBASIZE, 1u << (4u + env->misa_mxl));
+        value =
+            FIELD_DP32(value, SBCS, SBACCESS64, (uint32_t)(env->misa_mxl > 1u));
+        value = FIELD_DP32(value, SBCS, SBACCESS32, 1u);
+        value = FIELD_DP32(value, SBCS, SBACCESS16, 1u);
+        value = FIELD_DP32(value, SBCS, SBACCESS8, 1u);
+    }
+
+    dm->regs[A_SBCS] = value;
+
+    /* set dmactive once ready */
+    dm->regs[A_DMCONTROL] |= R_DMCONTROL_DMACTIVE_MASK;
+}
+
+static void riscv_dm_realize(DeviceState *dev, Error **errp)
+{
+    RISCVDMState *dm = RISCV_DM(dev);
+
+    MachineState *ms = MACHINE(qdev_get_machine());
+    unsigned max_cpus = ms->smp.max_cpus;
+    g_assert((dm->hart_count > 0) && (dm->hart_count <= max_cpus));
+    dm->harts = g_new0(RISCVDMHartState, dm->hart_count);
+    dm->regs = g_new0(uint32_t, DM_REG_COUNT);
+    dm->as = NULL;
+
+    if (dm->cfg.data_count > R_ABSTRACTAUTO_AUTOEXECDATA_LENGTH) {
+        error_setg(errp, "Invalid data count property");
+        return;
+    }
+    if (dm->cfg.progbuf_count > R_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH) {
+        error_setg(errp, "Invalid progbuf count property");
+        return;
+    }
+
+    qdev_init_gpio_in_named(dev, &riscv_dm_acknowledge, RISCV_DM_ACK_LINES,
+                            ACK_COUNT);
+
+    dm->soc = object_get_canonical_path_component(OBJECT(dev)->parent);
+    dm->unavailable_bm = (1u << dm->hart_count) - 1u;
+    dm->regs[A_NEXTDM] = dm->cfg.dmi_next;
+
+    dm->mta_dm = ((RISCVDMMemAttrs){ .value = dm->cfg.mta_dm }).attrs;
+    dm->mta_sba = ((RISCVDMMemAttrs){ .value = dm->cfg.mta_sba }).attrs;
+}
+
+static void riscv_dm_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &riscv_dm_realize;
+    device_class_set_props(dc, riscv_dm_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    RISCVDMClass *cc = RISCV_DM_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &riscv_dm_reset_enter, NULL,
+                                       &riscv_dm_reset_exit,
+                                       &cc->parent_phases);
+
+    RISCVDebugDeviceClass *dmc = RISCV_DEBUG_DEVICE_CLASS(klass);
+    dmc->write_rq = &riscv_dm_write_rq;
+    dmc->read_rq = &riscv_dm_read_rq;
+    dmc->read_value = &riscv_dm_read_value;
+    dmc->set_next_dm = &riscv_dm_set_next_dm;
+
+    /*
+     * unfortunately, MemTxtAttrs is a bitfield and there is no built-time way
+     * to define nor check its contents vs. an integral value. Run a quick
+     * sanity check at runtime.
+     */
+    RISCVDMMemAttrs mta = { .attrs = MEMTXATTRS_UNSPECIFIED };
+    g_assert(mta.value == RISCVDM_DEFAULT_MTA);
+}
+
+static const TypeInfo riscv_dm_info = {
+    .name = TYPE_RISCV_DM,
+    .parent = TYPE_RISCV_DEBUG_DEVICE,
+    .instance_size = sizeof(RISCVDMState),
+    .class_size = sizeof(RISCVDMClass),
+    .class_init = &riscv_dm_class_init,
+};
+
+static void riscv_dm_register_types(void)
+{
+    type_register_static(&riscv_dm_info);
+}
+
+type_init(riscv_dm_register_types);
diff --git a/hw/riscv/dtm.c b/hw/riscv/dtm.c
new file mode 100644
index 0000000000000..2259869a4aa78
--- /dev/null
+++ b/hw/riscv/dtm.c
@@ -0,0 +1,590 @@
+/*
+ * QEMU Debug Transport Module
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Generated code for absract commands has been extracted from the PULP Debug
+ * module whose file (dm_mem.sv) contains the following copyright. This piece of
+ * code is self contained within the `riscv_dtm_dm_access_register` function:
+ *
+ *   Copyright and related rights are licensed under the Solderpad Hardware
+ *   License, Version 0.51 (the “License”); you may not use this file except in
+ *   compliance with the License. You may obtain a copy of the License at
+ *   http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ *   or agreed to in writing, software, hardware and materials distributed under
+ *   this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+ *   CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ *   specific language governing permissions and limitations under the License.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/compiler.h"
+#include "qemu/log.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "hw/jtag/tap_ctrl.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/debug.h"
+#include "hw/riscv/dtm.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+/* clang-format off */
+
+/* Debug Module Interface and Control */
+REG32(DTMCS, 0x10u)
+    FIELD(DTMCS, VERSION, 0u, 4u)
+    FIELD(DTMCS, ABITS, 4u, 6u)
+    FIELD(DTMCS, DMISTAT, 10u, 2u)
+    FIELD(DTMCS, IDLE, 12u, 3u)
+    FIELD(DTMCS, DMIRESET, 16u, 1u)
+    FIELD(DTMCS, DMIHARDRESET, 17u, 1u)
+REG64(DMI, 0x11u)
+    FIELD(DMI, OP, 0u, 2u)
+    FIELD(DMI, DATA, 2u, 32u)
+    FIELD(DMI, ADDRESS, 34u, 64u-34u) /* real width is a runtime property */
+
+/* clang-format on */
+
+#define xtrace_riscv_dtm_error(_msg_) \
+    trace_riscv_dtm_error(__func__, __LINE__, _msg_)
+#define xtrace_riscv_dtm_info(_msg_, _val_) \
+    trace_riscv_dtm_info(__func__, __LINE__, _msg_, _val_)
+
+/*
+ * DMI register operations
+ * see RISC-V debug spec secttion 6.1.5 Debug Module Interface Access
+ */
+typedef enum {
+    DMI_IGNORE,
+    DMI_READ,
+    DMI_WRITE,
+    DMI_RESERVED,
+} RISCVDMIOperation;
+
+typedef QLIST_HEAD(, RISCVDebugModule) RISCVDebugModuleList;
+
+typedef struct RISCVDebugModule {
+    QLIST_ENTRY(RISCVDebugModule) entry;
+    RISCVDebugDeviceState *dev;
+    RISCVDebugDeviceClass *dc;
+    char *path;
+    uint32_t base;
+    uint32_t size;
+    bool enabled;
+} RISCVDebugModule;
+
+/** Debug Module Interface */
+struct RISCVDTMState {
+    DeviceState parent;
+
+    RISCVDebugModuleList dms;
+    RISCVDebugModule *last_dm; /* last selected DM */
+
+    uint32_t address; /* last updated address */
+    RISCVDebugResult dmistat; /* Operation result */
+    bool cmd_busy; /* A command is being executed */
+
+    /* properties */
+    DeviceState *tap_ctrl;
+    unsigned abits; /* address bit count */
+};
+
+static RISCVDebugModule *riscv_dtm_get_dm(RISCVDTMState *s, uint32_t addr);
+static void riscv_dtm_sort_dms(RISCVDTMState *s);
+static void riscv_dtm_activate_dms(RISCVDTMState *s);
+
+static void riscv_dtm_tap_dtmcs_capture(TapDataHandler *tdh);
+static void riscv_dtm_tap_dtmcs_update(TapDataHandler *tdh);
+static void riscv_dtm_tap_dmi_capture(TapDataHandler *tdh);
+static void riscv_dtm_tap_dmi_update(TapDataHandler *tdh);
+
+#define RISCV_DEBUG_DMI_VERSION 1u /* RISC-V Debug spec 0.13.x & 1.0 */
+#define RISCVDMI_DTMCS_IR       0x10u
+#define RISCVDMI_DMI_IR         0x11u
+
+static const TapDataHandler RISCVDMI_DTMCS = {
+    .name = "dtmcs",
+    .length = 32u,
+    .value = RISCV_DEBUG_DMI_VERSION, /* abits updated at runtime */
+    .capture = &riscv_dtm_tap_dtmcs_capture,
+    .update = &riscv_dtm_tap_dtmcs_update,
+};
+
+static const TapDataHandler RISCVDMI_DMI = {
+    .name = "dmi",
+    /* data, op; abits updated at runtime */
+    .length = R_DMI_OP_LENGTH + R_DMI_DATA_LENGTH,
+    .capture = &riscv_dtm_tap_dmi_capture,
+    .update = &riscv_dtm_tap_dmi_update,
+};
+
+#define MAKE_RUNSTATE_ENTRY(_ent_) [RUN_STATE_##_ent_] = stringify(_ent_)
+static const char *RISCVDMI_RUNSTATE_NAMES[] = {
+    /* clang-format off */
+    MAKE_RUNSTATE_ENTRY(DEBUG),
+    MAKE_RUNSTATE_ENTRY(INMIGRATE),
+    MAKE_RUNSTATE_ENTRY(INTERNAL_ERROR),
+    MAKE_RUNSTATE_ENTRY(IO_ERROR),
+    MAKE_RUNSTATE_ENTRY(PAUSED),
+    MAKE_RUNSTATE_ENTRY(POSTMIGRATE),
+    MAKE_RUNSTATE_ENTRY(PRELAUNCH),
+    MAKE_RUNSTATE_ENTRY(FINISH_MIGRATE),
+    MAKE_RUNSTATE_ENTRY(RESTORE_VM),
+    MAKE_RUNSTATE_ENTRY(RUNNING),
+    MAKE_RUNSTATE_ENTRY(SAVE_VM),
+    MAKE_RUNSTATE_ENTRY(SHUTDOWN),
+    MAKE_RUNSTATE_ENTRY(SUSPENDED),
+    MAKE_RUNSTATE_ENTRY(WATCHDOG),
+    MAKE_RUNSTATE_ENTRY(GUEST_PANICKED),
+    MAKE_RUNSTATE_ENTRY(COLO),
+    /* clang-format on */
+};
+#undef MAKE_RUNSTATE_ENTRY
+#define RUNSTATE_NAME(_reg_) \
+    ((((_reg_) <= ARRAY_SIZE(RISCVDMI_RUNSTATE_NAMES)) && \
+      RISCVDMI_RUNSTATE_NAMES[_reg_]) ? \
+         RISCVDMI_RUNSTATE_NAMES[_reg_] : \
+         "?")
+
+/* -------------------------------------------------------------------------- */
+/* DTM API */
+/* -------------------------------------------------------------------------- */
+
+static bool riscv_dtm_register_dm(DeviceState *dev,
+                                  RISCVDebugDeviceState *dbgdev,
+                                  hwaddr base_addr, hwaddr size, bool enable)
+{
+    RISCVDTMState *s = RISCV_DTM(dev);
+
+    g_assert(dev->realized);
+
+    if ((base_addr + size - 1u) > (1u << s->abits)) {
+        error_setg(&error_fatal,
+                   "DM address range cannot be encoded in %u address bits",
+                   s->abits);
+    }
+
+    if (!s->tap_ctrl) {
+        xtrace_riscv_dtm_info("TAP controller not available", 0);
+        return false;
+    }
+
+    TapCtrlIfClass *tapcls = TAP_CTRL_IF_GET_CLASS(s->tap_ctrl);
+    TapCtrlIf *tap = TAP_CTRL_IF(s->tap_ctrl);
+
+    /* may fail if TAP controller is not active */
+    bool tap_ok = tapcls->is_enabled(tap);
+
+    RISCVDebugModule *node;
+    unsigned count = 0;
+    QLIST_FOREACH(node, &s->dms, entry) {
+        count += 1u;
+        if ((node->dev == dbgdev) && (node->base == base_addr) &&
+            (node->size == size)) {
+            /* already registered */
+            return tap_ok;
+        }
+        if (base_addr > (node->base + node->size - 1u)) {
+            continue;
+        }
+        if ((base_addr + size - 1u) < node->base) {
+            continue;
+        }
+
+        error_setg(&error_fatal, "Debug Module overlap\n");
+    }
+
+    object_ref(OBJECT(dbgdev));
+
+    RISCVDebugModule *dm = g_new(RISCVDebugModule, 1u);
+    dm->dev = dbgdev;
+    dm->dc = RISCV_DEBUG_DEVICE_GET_CLASS(OBJECT(dbgdev));
+    dm->base = base_addr;
+    dm->size = size;
+    dm->enabled = enable;
+    dm->path =
+        g_strdup_printf("%s/%s",
+                        object_get_canonical_path_component(
+                            OBJECT(dbgdev)->parent),
+                        object_get_canonical_path_component(OBJECT(dbgdev)));
+
+    QLIST_INSERT_HEAD(&s->dms, dm, entry);
+    s->last_dm = dm;
+
+    trace_riscv_dtm_register_dm(dm->path, count, base_addr,
+                                base_addr + size - 1u, enable, tap_ok);
+
+    riscv_dtm_sort_dms(s);
+    riscv_dtm_activate_dms(s);
+
+    return tap_ok;
+}
+
+static void riscv_dtm_enable_dm(DeviceState *dev, RISCVDebugDeviceState *dbgdev,
+                                bool enable)
+{
+    RISCVDTMState *s = RISCV_DTM(dev);
+
+    RISCVDebugModule *node;
+    bool update = false;
+    QLIST_FOREACH(node, &s->dms, entry) {
+        if (node->dev == dbgdev) {
+            update = node->enabled != enable;
+            node->enabled = enable;
+            trace_riscv_dtm_enable_dm(object_get_canonical_path_component(
+                                          OBJECT(dbgdev)),
+                                      enable, update);
+            break;
+        }
+    }
+
+    if (update) {
+        riscv_dtm_activate_dms(s);
+    }
+}
+
+/* -------------------------------------------------------------------------- */
+/* DTMCS/DMI implementation */
+/* -------------------------------------------------------------------------- */
+
+static void riscv_dtm_tap_dtmcs_capture(TapDataHandler *tdh)
+{
+    RISCVDTMState *s = tdh->opaque;
+
+    tdh->value = (s->abits << 4u) | (RISCV_DEBUG_DMI_VERSION << 0u) |
+                 ((uint64_t)s->dmistat << 10u); /* see DMI op result */
+}
+
+static void riscv_dtm_tap_dtmcs_update(TapDataHandler *tdh)
+{
+    RISCVDTMState *s = tdh->opaque;
+    if (tdh->value & (1u << 16u)) {
+        /* dmireset */
+        trace_riscv_dtm_dtmcs_reset();
+        s->dmistat = RISCV_DEBUG_NOERR;
+    }
+    if (tdh->value & (1u << 17u)) {
+        /* dmi hardreset */
+        qemu_log_mask(LOG_UNIMP, "%s: DMI hard reset\n", __func__);
+    }
+}
+
+static void riscv_dtm_tap_dmi_capture(TapDataHandler *tdh)
+{
+    RISCVDTMState *s = tdh->opaque;
+
+    uint32_t addr = s->address;
+    uint32_t value = 0;
+
+    if (s->dmistat == RISCV_DEBUG_NOERR) {
+        unsigned op = (unsigned)(tdh->value & 0b11);
+        if (op == DMI_READ) {
+            RISCVDebugModule *dm = riscv_dtm_get_dm(s, addr);
+            if (!dm) {
+                s->dmistat = RISCV_DEBUG_FAILED;
+                value = 0;
+                qemu_log_mask(LOG_UNIMP, "%s: Unknown DM address 0x%x\n",
+                              __func__, addr);
+            } else {
+                trace_riscv_dtm_tap_dmi_capture(addr);
+                value = dm->dc->read_value(dm->dev);
+            }
+        }
+    }
+
+    /*
+     * In Capture-DR, the DTM updates data with the result from [the previous
+     * update] operation, updating op if the current op isn’t sticky.
+     */
+    tdh->value = (((uint64_t)addr) << (32u + 2u)) | (((uint64_t)value) << 2u) |
+                 ((uint64_t)(s->dmistat & 0b11));
+}
+
+static void riscv_dtm_tap_dmi_update(TapDataHandler *tdh)
+{
+    RISCVDTMState *s = tdh->opaque;
+
+    uint32_t value;
+    uint32_t addr =
+        (uint32_t)extract64(tdh->value, R_DMI_ADDRESS_SHIFT, (int)s->abits);
+    unsigned op = (unsigned)(tdh->value & 0b11);
+
+    if (op == DMI_IGNORE) {
+        /*
+         * Don’t send anything over the DMI during Update-DR. This operation
+         * should never result in a busy or error response. The address and data
+         * reported in the following Capture-DR are undefined.
+         */
+        return;
+    }
+
+    /* store address for next read back */
+    s->address = addr;
+
+    RISCVDebugModule *dm = riscv_dtm_get_dm(s, addr);
+    if (!dm) {
+        s->dmistat = RISCV_DEBUG_FAILED;
+        qemu_log_mask(LOG_UNIMP, "%s: Unknown DM address 0x%x, op %u\n",
+                      __func__, addr, op);
+        return;
+    }
+
+    /*
+     * In Update-DR, the DTM starts the operation specified in op unless the
+     * current status reported in op is sticky.
+     */
+    switch (op) {
+    case DMI_IGNORE: /* NOP */
+        g_assert_not_reached();
+        return;
+    case DMI_READ:
+        trace_riscv_dtm_tap_dmi_update(addr, "read");
+        s->dmistat = dm->dc->read_rq(dm->dev, addr - dm->base);
+        break;
+    case DMI_WRITE:
+        trace_riscv_dtm_tap_dmi_update(addr, "write");
+        value = (uint32_t)FIELD_EX64(tdh->value, DMI, DATA);
+        s->dmistat = dm->dc->write_rq(dm->dev, addr - dm->base, value);
+        break;
+    case DMI_RESERVED:
+    default:
+        s->dmistat = RISCV_DEBUG_FAILED;
+        qemu_log_mask(LOG_UNIMP, "%s: Unknown operation %u\n", __func__, op);
+    }
+}
+
+static void riscv_dtm_register_tap_handlers(RISCVDTMState *s)
+{
+    if (!s->tap_ctrl) {
+        return;
+    }
+
+    TapCtrlIfClass *tapcls = TAP_CTRL_IF_GET_CLASS(s->tap_ctrl);
+    TapCtrlIf *tap = TAP_CTRL_IF(s->tap_ctrl);
+
+    /*
+     * copy the template to update the opaque value
+     * no lifetime issue as the data handler is copied by the TAP controller
+     */
+    TapDataHandler tdh;
+
+    memcpy(&tdh, &RISCVDMI_DTMCS, sizeof(TapDataHandler));
+    tdh.value |= s->abits << 4u; /* add address bit count */
+    tdh.opaque = s;
+    if (tapcls->register_instruction(tap, RISCVDMI_DTMCS_IR, &tdh)) {
+        xtrace_riscv_dtm_error("cannot register DMTCS");
+        return;
+    }
+
+    memcpy(&tdh, &RISCVDMI_DMI, sizeof(TapDataHandler));
+    tdh.length += s->abits; /* add address bit count */
+    tdh.opaque = s;
+    /* the data handler is copied by the TAP controller */
+    if (tapcls->register_instruction(tap, RISCVDMI_DMI_IR, &tdh)) {
+        xtrace_riscv_dtm_error("cannot register DMI");
+        return;
+    }
+}
+
+static RISCVDebugModule *riscv_dtm_get_dm(RISCVDTMState *s, uint32_t addr)
+{
+    RISCVDebugModule *dm = s->last_dm;
+
+    if (dm && (addr >= dm->base) && (addr < dm->base + dm->size)) {
+        return dm;
+    }
+
+    QLIST_FOREACH(dm, &s->dms, entry) {
+        if ((addr >= dm->base) && (addr < dm->base + dm->size)) {
+            s->last_dm = dm;
+            return dm;
+        }
+    }
+
+    s->last_dm = NULL;
+    return NULL;
+}
+
+static void riscv_dtm_vm_state_change(void *opaque, bool running,
+                                      RunState state)
+{
+    (void)opaque;
+    (void)running;
+    trace_riscv_dtm_vm_state_change(RUNSTATE_NAME(state), state);
+}
+
+static int riscv_dtm_order_dm(const void *pdm1, const void *pdm2)
+{
+    return ((int)(*(RISCVDebugModule **)pdm1)->base) -
+           ((int)(*(RISCVDebugModule **)pdm2)->base);
+}
+
+static void riscv_dtm_sort_dms(RISCVDTMState *s)
+{
+    RISCVDebugModule *dm;
+
+    /* iterate once to get the count of managed DMs */
+    unsigned count = 0;
+    QLIST_FOREACH(dm, &s->dms, entry) {
+        count += 1;
+    }
+
+    /* create an array of sortable DM references */
+    RISCVDebugModule **dma = g_new(RISCVDebugModule *, count);
+    RISCVDebugModule **cdm = dma;
+    QLIST_FOREACH(dm, &s->dms, entry) {
+        *cdm++ = dm;
+    }
+
+    /* sort DM reference by increasing base address */
+    qsort(dma, count, sizeof(RISCVDebugModule *), &riscv_dtm_order_dm);
+
+    /* create a new list of ordered, managed DMs */
+    RISCVDebugModuleList sorted;
+    QLIST_INIT(&sorted);
+    RISCVDebugModule *cur = QLIST_FIRST(&sorted);
+    for (unsigned ix = 0; ix < count; ix++) {
+        QLIST_REMOVE(dma[ix], entry);
+        if (!cur) {
+            QLIST_INSERT_HEAD(&sorted, dma[ix], entry);
+        } else {
+            QLIST_INSERT_AFTER(cur, dma[ix], entry);
+        }
+        cur = dma[ix];
+    }
+    /* replace current list head with the new ordered one */
+    s->dms = sorted;
+
+    g_free(dma);
+}
+
+static void riscv_dtm_update_next_dm(RISCVDebugModule *dm,
+                                     const RISCVDebugModule *next_dm)
+{
+    if (dm->dc->set_next_dm) {
+        uint32_t next_addr = next_dm ? next_dm->base : 0u;
+        trace_riscv_dtm_set_next_dm(dm->path, dm->base,
+                                    next_dm ? next_dm->path : "end", next_addr);
+        (*dm->dc->set_next_dm)(dm->dev, next_addr);
+    }
+}
+
+static void riscv_dtm_activate_dms(RISCVDTMState *s)
+{
+    RISCVDebugModule *dm;
+    RISCVDebugModule *prev_dm = NULL;
+    QLIST_FOREACH(dm, &s->dms, entry) {
+        /*
+         * devices that do not implement set_next_dm are not part of the next_dm
+         * chain and therefore ignored
+         */
+        if (dm->enabled && dm->dc->set_next_dm) {
+            /* do not bother updating a disabled DM */
+            if (prev_dm && prev_dm->enabled) {
+                riscv_dtm_update_next_dm(prev_dm, dm);
+            }
+            prev_dm = dm;
+        }
+    }
+
+    if (prev_dm) {
+        riscv_dtm_update_next_dm(prev_dm, NULL);
+    }
+}
+
+static const Property riscv_dtm_properties[] = {
+    DEFINE_PROP_UINT32("abits", RISCVDTMState, abits, 0x7u),
+    DEFINE_PROP_LINK("tap-ctrl", RISCVDTMState, tap_ctrl, TYPE_DEVICE,
+                     DeviceState *),
+};
+
+static void riscv_dtm_reset_enter(Object *obj, ResetType type)
+{
+    RISCVDTMClass *c = RISCV_DTM_GET_CLASS(obj);
+    RISCVDTMState *s = RISCV_DTM(obj);
+
+    if (c->parent_phases.enter) {
+        c->parent_phases.enter(obj, type);
+    }
+
+    s->address = 0;
+    s->last_dm = NULL;
+}
+
+static void riscv_dtm_realize(DeviceState *dev, Error **errp)
+{
+    RISCVDTMState *s = RISCV_DTM(dev);
+
+    if (s->abits < 7u || s->abits > 30u) {
+        error_setg(errp, "Invalid address bit count");
+        return;
+    }
+
+    riscv_dtm_register_tap_handlers(s);
+}
+
+static void riscv_dtm_init(Object *obj)
+{
+    RISCVDTMState *s = RISCV_DTM(obj);
+
+    qemu_add_vm_change_state_handler(&riscv_dtm_vm_state_change, s);
+
+    QLIST_INIT(&s->dms);
+}
+
+static void riscv_dtm_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    (void)data;
+
+    dc->realize = &riscv_dtm_realize;
+    device_class_set_props(dc, riscv_dtm_properties);
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    RISCVDTMClass *tc = RISCV_DTM_CLASS(klass);
+    resettable_class_set_parent_phases(rc, &riscv_dtm_reset_enter, NULL, NULL,
+                                       &tc->parent_phases);
+
+    RISCVDTMClass *dmc = RISCV_DTM_CLASS(klass);
+    dmc->register_dm = &riscv_dtm_register_dm;
+    dmc->enable_dm = &riscv_dtm_enable_dm;
+}
+
+static const TypeInfo riscv_dtm_info = {
+    .name = TYPE_RISCV_DTM,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(RISCVDTMState),
+    .instance_init = &riscv_dtm_init,
+    .class_size = sizeof(RISCVDTMClass),
+    .class_init = &riscv_dtm_class_init,
+};
+
+static void riscv_dtm_register_types(void)
+{
+    type_register_static(&riscv_dtm_info);
+}
+
+type_init(riscv_dtm_register_types);
diff --git a/hw/riscv/ibex_clock_src.c b/hw/riscv/ibex_clock_src.c
new file mode 100644
index 0000000000000..92ef0fc7ea7c5
--- /dev/null
+++ b/hw/riscv/ibex_clock_src.c
@@ -0,0 +1,42 @@
+/*
+ * QEMU Ibex Clock Source interface
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/riscv/ibex_clock_src.h"
+
+static const TypeInfo ibex_clock_src_info = {
+    .name = TYPE_IBEX_CLOCK_SRC_IF,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(IbexClockSrcIfClass),
+};
+
+static void ibex_clock_src_register_types(void)
+{
+    type_register_static(&ibex_clock_src_info);
+}
+
+type_init(ibex_clock_src_register_types);
diff --git a/hw/riscv/ibex_common.c b/hw/riscv/ibex_common.c
new file mode 100644
index 0000000000000..c41f7854ddde8
--- /dev/null
+++ b/hw/riscv/ibex_common.c
@@ -0,0 +1,883 @@
+/*
+ * QEMU RISC-V Helpers for LowRISC Ibex Demo System & OpenTitan EarlGrey
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#ifdef CONFIG_POSIX
+#include <dlfcn.h>
+#endif
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qom/object.h"
+#include "chardev/chardev-internal.h"
+/* NOLINTBEGIN(misc-header-include-cycle) */
+#include "cpu.h"
+/* NOLINTEND(misc-header-include-cycle) */
+#include "disas/disas.h"
+#include "elf.h"
+#include "exec/hwaddr.h"
+#include "hw/boards.h"
+#include "hw/core/rust_demangle.h"
+#include "hw/loader.h"
+#include "hw/misc/unimp.h"
+#include "hw/qdev-core.h"
+#include "hw/qdev-properties.h"
+#include "hw/riscv/ibex_clock_src.h"
+#include "hw/riscv/ibex_common.h"
+#include "monitor/monitor.h"
+#include "system/runstate.h"
+#include "trace.h"
+
+static void rust_demangle_fn(const char *st_name, int st_info,
+                             uint64_t st_value, uint64_t st_size);
+
+void ibex_mmio_map_device(SysBusDevice *dev, MemoryRegion *mr, unsigned nr,
+                          hwaddr addr, int priority)
+{
+    g_assert(nr < dev->num_mmio);
+    g_assert(dev->mmio[nr].addr == (hwaddr)-1);
+    dev->mmio[nr].addr = addr;
+    if (priority) {
+        memory_region_add_subregion_overlap(mr, addr, dev->mmio[nr].memory,
+                                            priority);
+    } else {
+        memory_region_add_subregion(mr, addr, dev->mmio[nr].memory);
+    }
+}
+
+DeviceState **ibex_create_devices(const IbexDeviceDef *defs, unsigned count,
+                                  DeviceState *parent)
+{
+    DeviceState **devices = g_new0(DeviceState *, count);
+    GHashTable *chtable =
+        g_hash_table_new_full(g_str_hash, g_str_equal, NULL, g_free);
+    const char *pname = object_get_typename(OBJECT(parent));
+
+    for (unsigned idx = 0; idx < count; idx++) {
+        const IbexDeviceDef *def = &defs[idx];
+        if (!def->type) {
+            devices[idx] = NULL;
+            continue;
+        }
+        devices[idx] = qdev_new(def->type);
+
+        const char *tname;
+        if (!strcmp(def->type, TYPE_UNIMPLEMENTED_DEVICE)) {
+            tname = def->name ? def->name : TYPE_UNIMPLEMENTED_DEVICE;
+        } else {
+            tname = def->type;
+        }
+
+        char *name;
+        if (!IBEX_HAS_INSTANCE_NUM(def)) {
+            gpointer sibling = g_hash_table_lookup(chtable, (gpointer)tname);
+            unsigned *chcount;
+            if (!sibling) {
+                chcount = g_new(unsigned, 1u);
+                *chcount = 0;
+                g_hash_table_insert(chtable, (gpointer)tname,
+                                    (gpointer)chcount);
+            } else {
+                chcount = (unsigned *)sibling;
+                *chcount = (*chcount) + 1u;
+            }
+            name = g_strdup_printf("%s.%u", tname, *chcount);
+        } else {
+            name = g_strdup_printf("%s[%u]", tname, IBEX_GET_INSTANCE_NUM(def));
+        }
+        trace_ibex_create_device(pname, name);
+        object_property_add_child(OBJECT(parent), name, OBJECT(devices[idx]));
+        g_free(name);
+    }
+    g_hash_table_destroy(chtable);
+    return devices;
+}
+
+void ibex_link_remote_devices(DeviceState **devices, const IbexDeviceDef *defs,
+                              unsigned count, DeviceState ***remotes)
+{
+    /* Link devices */
+    DeviceState ***targets = remotes ?: &devices;
+    for (unsigned idx = 0; idx < count; idx++) {
+        DeviceState *dev = devices[idx];
+        if (!dev) {
+            continue;
+        }
+        const IbexDeviceLinkDef *link = defs[idx].link;
+        if (link) {
+            while (link->propname) {
+                unsigned rix = IBEX_DEVLINK_REMOTE(link->index);
+                unsigned dix = IBEX_DEVLINK_DEVICE(link->index);
+                if (rix && !remotes) {
+                    /*
+                     * if no remote devices are specified, only local links
+                     * can be performed, skip any remote definition.
+                     */
+                    link++;
+                    continue;
+                }
+                if (!rix && remotes) {
+                    /*
+                     * if remote devices are specified, only remote links
+                     * should be performed, skip any local definition.
+                     */
+                    link++;
+                    continue;
+                }
+                DeviceState **tdevices = targets[rix];
+                g_assert(tdevices);
+                DeviceState *target = tdevices[dix];
+                g_assert(target);
+                object_property_set_link(OBJECT(dev), link->propname,
+                                         OBJECT(target), &error_fatal);
+                g_autofree char *plink;
+                plink = object_property_get_str(OBJECT(dev), link->propname,
+                                                &error_fatal);
+                if (!plink || *plink == '\0') {
+                    /*
+                     * unfortunately, if an object is not parented, it is not
+                     * possible to create a link (its canonical being NULL), but
+                     * the `object_property_set_link` silently fails. Read back
+                     * the property to ensure it has been really set.
+                     */
+                    error_setg(&error_fatal, "cannot create %s link",
+                               link->propname);
+                }
+                link++;
+            }
+        }
+    }
+}
+
+void ibex_apply_device_props(Object *obj, const IbexDevicePropDef *prop)
+{
+    if (prop) {
+        while (prop->propname) {
+            switch (prop->type) {
+            case IBEX_PROP_TYPE_BOOL:
+                object_property_set_bool(obj, prop->propname, prop->b,
+                                         &error_fatal);
+                break;
+            case IBEX_PROP_TYPE_INT:
+                object_property_set_int(obj, prop->propname, prop->i,
+                                        &error_fatal);
+                break;
+            case IBEX_PROP_TYPE_UINT:
+                object_property_set_uint(obj, prop->propname, prop->u,
+                                         &error_fatal);
+                break;
+            case IBEX_PROP_TYPE_STR:
+                object_property_set_str(obj, prop->propname, prop->s,
+                                        &error_fatal);
+                break;
+            default:
+                g_assert_not_reached();
+                break;
+            }
+            prop++;
+        }
+    }
+}
+
+void ibex_define_device_props(DeviceState **devices, const IbexDeviceDef *defs,
+                              unsigned count)
+{
+    for (unsigned idx = 0; idx < count; idx++) {
+        DeviceState *dev = devices[idx];
+        if (!dev) {
+            continue;
+        }
+        ibex_apply_device_props(OBJECT(dev), defs[idx].prop);
+    }
+}
+
+void ibex_realize_system_devices(DeviceState **devices,
+                                 const IbexDeviceDef *defs, unsigned count)
+{
+    BusState *bus = sysbus_get_default();
+
+    ibex_realize_devices(devices, bus, defs, count);
+
+    MemoryRegion *mrs[] = { get_system_memory(), NULL, NULL, NULL };
+
+    ibex_map_devices(devices, mrs, defs, count);
+}
+
+void ibex_realize_devices(DeviceState **devices, BusState *bus,
+                          const IbexDeviceDef *defs, unsigned count)
+{
+    /* Realize devices */
+    for (unsigned idx = 0; idx < count; idx++) {
+        DeviceState *dev = devices[idx];
+        if (!dev) {
+            continue;
+        }
+        const IbexDeviceDef *def = &defs[idx];
+
+        if (def->cfg) {
+            def->cfg(dev, def, DEVICE(OBJECT(dev)->parent));
+        }
+
+        if (def->memmap) {
+            SysBusDevice *busdev =
+                (SysBusDevice *)object_dynamic_cast(OBJECT(dev),
+                                                    TYPE_SYS_BUS_DEVICE);
+            if (!busdev) {
+                /* non-sysbus devices are not supported for now */
+                g_assert_not_reached();
+            }
+
+            qdev_realize_and_unref(DEVICE(busdev), bus, &error_fatal);
+        } else {
+            /* device is not connected to a bus */
+            qdev_realize_and_unref(dev, NULL, &error_fatal);
+        }
+    }
+}
+
+void ibex_map_devices_mask_offset(DeviceState **devices, MemoryRegion **mrs,
+                                  const IbexDeviceDef *defs, unsigned count,
+                                  uint32_t region_mask, uint32_t offset)
+{
+    for (unsigned idx = 0; idx < count; idx++) {
+        DeviceState *dev = devices[idx];
+        if (!dev) {
+            continue;
+        }
+        const IbexDeviceDef *def = &defs[idx];
+
+        if (def->memmap) {
+            SysBusDevice *busdev =
+                (SysBusDevice *)object_dynamic_cast(OBJECT(dev),
+                                                    TYPE_SYS_BUS_DEVICE);
+            if (busdev) {
+                const IbexMemMapEntry *memmap = def->memmap;
+                unsigned mem = 0;
+                while (!IBEX_MEMMAP_IS_LAST(memmap)) {
+                    unsigned region = IBEX_MEMMAP_GET_REGIDX(memmap->base);
+                    if (region_mask & (1u << region)) {
+                        MemoryRegion *mr = mrs[region];
+                        if (mr) {
+                            ibex_mmio_map_device(busdev, mr, mem,
+                                                 IBEX_MEMMAP_GET_ADDRESS(
+                                                     memmap->base) +
+                                                     offset,
+                                                 memmap->priority);
+                        }
+                    }
+                    mem++;
+                    memmap++;
+                }
+            }
+        }
+    }
+}
+
+void ibex_map_devices_ext_mask_offset(
+    DeviceState *dev, MemoryRegion **mrs, const IbexDeviceMapDef *defs,
+    unsigned count, uint32_t region_mask, uint32_t offset)
+{
+    for (unsigned ix = 0; ix < count; ix++) {
+        const IbexDeviceMapDef *def = &defs[ix];
+        g_assert(def->type);
+        g_assert(def->memmap);
+
+        if (!IBEX_HAS_INSTANCE_NUM(def)) {
+            error_setg(&error_fatal, "Device %s @ %u instance is not known",
+                       def->type, ix);
+            return;
+        }
+
+        char *name =
+            g_strdup_printf("%s[%u]", def->type, IBEX_GET_INSTANCE_NUM(def));
+        Object *child;
+        child = object_property_get_link(OBJECT(dev), name, &error_fatal);
+        SysBusDevice *sdev;
+        sdev = OBJECT_CHECK(SysBusDevice, child, TYPE_SYS_BUS_DEVICE);
+        g_free(name);
+
+        const IbexMemMapEntry *memmap = def->memmap;
+        unsigned mem = 0;
+        while (!IBEX_MEMMAP_IS_LAST(memmap)) {
+            if (!IBEX_MEMMAP_IGNORE(memmap)) {
+                unsigned region = IBEX_MEMMAP_GET_REGIDX(memmap->base);
+                if (region_mask & (1u << region)) {
+                    MemoryRegion *mr = mrs[region];
+                    if (mr) {
+                        ibex_mmio_map_device(sdev, mr, mem,
+                                             IBEX_MEMMAP_GET_ADDRESS(
+                                                 memmap->base) +
+                                                 offset,
+                                             memmap->priority);
+                    }
+                }
+            }
+            mem++;
+            memmap++;
+        }
+    }
+}
+
+void ibex_connect_devices(DeviceState **devices, const IbexDeviceDef *defs,
+                          unsigned count)
+{
+    /* Connect GPIOs (in particular, IRQs) */
+    for (unsigned idx = 0; idx < count; idx++) {
+        DeviceState *dev = devices[idx];
+        if (!dev) {
+            continue;
+        }
+        const IbexDeviceDef *def = &defs[idx];
+
+        if (def->gpio) {
+            const IbexGpioConnDef *conn = def->gpio;
+            while (conn->out.num >= 0 && conn->in.num >= 0) {
+                if (conn->in.index >= 0) {
+                    unsigned in_ix = IBEX_GPIO_GET_IDX(conn->in.index);
+                    g_assert(devices[in_ix]);
+                    qemu_irq in_gpio =
+                        qdev_get_gpio_in_named(devices[in_ix], conn->in.name,
+                                               conn->in.num);
+                    if (!in_gpio) {
+                        error_setg(&error_fatal, "no such GPIO '%s.%s[%d]'\n",
+                                   object_get_typename(OBJECT(devices[in_ix])),
+                                   conn->in.name, conn->in.num);
+                    }
+                    qdev_connect_gpio_out_named(dev, conn->out.name,
+                                                conn->out.num, in_gpio);
+                }
+                conn++;
+            }
+        }
+    }
+}
+
+void ibex_clock_devices(DeviceState **devices, const IbexDeviceDef *defs,
+                        unsigned count)
+{
+    IbexClockSrcIfClass *ic = NULL;
+    IbexClockSrcIf *is = NULL;
+    int ii = -1;
+
+    for (unsigned idx = 0; idx < count; idx++) {
+        DeviceState *dev = devices[idx];
+        if (!dev) {
+            continue;
+        }
+        const IbexClockConnDef *clock = defs[idx].clock;
+        if (!clock) {
+            continue;
+        }
+
+        while (clock->out.name && clock->in.name) {
+            if (clock->out.index != ii) {
+                /* new clock source */
+                DeviceState *cs = devices[clock->out.index];
+                ic = IBEX_CLOCK_SRC_IF_GET_CLASS(cs);
+                is = IBEX_CLOCK_SRC_IF(cs);
+                ii = clock->out.index;
+            }
+
+            qemu_irq clk_irq =
+                qdev_get_gpio_in_named(dev, clock->in.name, clock->in.num);
+            if (!clk_irq) {
+                error_setg(&error_fatal, "no such clock '%s.%s[%d]'\n",
+                           object_get_typename(OBJECT(dev)), clock->in.name,
+                           clock->in.num);
+            }
+
+            g_assert(ic && ic->get_clock_source);
+            const char *out_name =
+                ic->get_clock_source(is, clock->out.name, dev, &error_fatal);
+            qdev_connect_gpio_out_named(dev, out_name, 0, clk_irq);
+            clock++;
+        }
+    }
+}
+
+/* List of exported GPIOs */
+typedef QLIST_HEAD(, NamedGPIOList) IbexXGPIOList;
+
+static NamedGPIOList *ibex_xgpio_list(IbexXGPIOList *xgpios, const char *name)
+{
+    /*
+     * qdev_get_named_gpio_list is not a public API.
+     * Use a clone implementation to manage a list of GPIOs
+     */
+    NamedGPIOList *ngl;
+
+    QLIST_FOREACH(ngl, xgpios, node) {
+        /* NULL is a valid and matchable name. */
+        if (g_strcmp0(name, ngl->name) == 0) {
+            return ngl;
+        }
+    }
+
+    ngl = g_malloc0(sizeof(*ngl));
+    ngl->name = g_strdup(name);
+    QLIST_INSERT_HEAD(xgpios, ngl, node);
+    return ngl;
+}
+
+void ibex_export_gpios(DeviceState **devices, DeviceState *parent,
+                       const IbexDeviceDef *defs, unsigned count)
+{
+    /*
+     * Use IbexXGPIOList as a circomvoluted way to obtain IRQ information that
+     * may not be exposed through public APIs.
+     */
+    IbexXGPIOList pgpios = { 0 };
+
+    for (unsigned idx = 0; idx < count; idx++) {
+        DeviceState *dev = devices[idx];
+        if (!dev) {
+            continue;
+        }
+        const IbexDeviceDef *def = &defs[idx];
+
+        if (def->gpio_export) {
+            const IbexGpioExportDef *export;
+
+            /* loop once to compute how the number of GPIO for each GPIO list */
+            export = def->gpio_export;
+            while (export->device.num >= 0 && export->parent.num >= 0) {
+                const char *pname = export->parent.name;
+                NamedGPIOList *pngl = ibex_xgpio_list(&pgpios, pname);
+
+                pngl->num_in = MAX(pngl->num_in, export->parent.num);
+
+                export ++;
+            }
+
+            NamedGPIOList *ngl, *ntmp;
+            QLIST_FOREACH_SAFE(ngl, &pgpios, node, ntmp) {
+                NamedGPIOList *pngl;
+                QLIST_FOREACH(pngl, &parent->gpios, node) {
+                    if (!g_strcmp0(ngl->name, pngl->name)) {
+                        qemu_log("%s: duplicate GPIO export list %s for %s\n",
+                                 __func__, ngl->name,
+                                 object_get_typename(OBJECT(parent)));
+                        g_assert_not_reached();
+                    }
+                }
+                /* num_in is the max index, i.e. n-1 */
+                ngl->num_in += 1u;
+                ngl->in = g_new(qemu_irq, ngl->num_in);
+                QLIST_REMOVE(ngl, node);
+                QLIST_INSERT_HEAD(&parent->gpios, ngl, node);
+            }
+
+            /*
+             * Now the count of IRQ slots per IRQ name is known.
+             * Allocate the required slots to store IRQs
+             * Create alias from parent to devices
+             * Shallow copy device IRQ into parent's slots, as we do not want
+             * to alter the device IRQ list.
+             */
+            export = def->gpio_export;
+            ngl = NULL;
+            while (export->device.num >= 0 && export->parent.num >= 0) {
+                const char *defname = "unnamed-gpio-in";
+                const char *dname = export->device.name;
+                const char *dm = dname ? dname : defname;
+                char *dpname =
+                    g_strdup_printf("%s[%d]", dm, export->device.num);
+                const char *pname = export->parent.name;
+                const char *pm = pname ? pname : defname;
+                char *ppname =
+                    g_strdup_printf("%s[%d]", pm, export->parent.num);
+                qemu_irq devirq;
+                devirq = qdev_get_gpio_in_named(dev, export->device.name,
+                                                export->device.num);
+                if (!ngl || g_strcmp0(ngl->name, pname)) {
+                    ngl = NULL;
+                    NamedGPIOList *pngl;
+                    QLIST_FOREACH(pngl, &parent->gpios, node) {
+                        if (!g_strcmp0(pngl->name, pname)) {
+                            ngl = pngl;
+                            break;
+                        }
+                    }
+                }
+
+                assert(ngl && ngl->in);
+                ngl->in[export->parent.num] = devirq;
+                (void)object_ref(OBJECT(devirq));
+                object_property_add_alias(OBJECT(parent), ppname, OBJECT(dev),
+                                          dpname);
+                g_free(ppname);
+                g_free(dpname);
+                export ++;
+            }
+        }
+    }
+}
+
+void ibex_connect_soc_devices(DeviceState **soc_devices, DeviceState **devices,
+                              const IbexDeviceDef *defs, unsigned count)
+{
+    for (unsigned ix = 0; ix < count; ix++) {
+        DeviceState *dev = devices[ix];
+        if (!dev) {
+            continue;
+        }
+        const IbexDeviceDef *def = &defs[ix];
+        if (!def->type || !def->gpio) {
+            continue;
+        }
+
+        const IbexGpioConnDef *conn = def->gpio;
+        while (conn->out.num >= 0 && conn->in.num >= 0) {
+            if (conn->in.index < 0) {
+                unsigned grp = IBEX_GPIO_GET_GRP(conn->in.num);
+                if (!(grp < count)) {
+                    g_assert_not_reached();
+                }
+                DeviceState *socdev = soc_devices[grp];
+                unsigned in_ix = IBEX_GPIO_GET_IDX(conn->in.num);
+                qemu_irq in_gpio =
+                    qdev_get_gpio_in_named(socdev, conn->in.name, (int)in_ix);
+                if (!in_gpio) {
+                    error_setg(
+                        &error_fatal,
+                        "cannot connect %s.%s[%d], no such IRQ '%s.%s[%d]'\n",
+                        object_get_typename(OBJECT(dev)), conn->out.name,
+                        conn->out.num, object_get_typename(OBJECT(socdev)),
+                        conn->in.name, in_ix);
+                }
+                qdev_connect_gpio_out_named(dev, conn->out.name, conn->out.num,
+                                            in_gpio);
+            }
+            conn++;
+        }
+    }
+}
+
+void ibex_identify_devices(DeviceState **devices, const char *id_prop,
+                           const char *id_value, bool id_prepend,
+                           unsigned count)
+{
+    for (unsigned ix = 0; ix < count; ix++) {
+        DeviceState *dev = devices[ix];
+        if (!dev) {
+            continue;
+        }
+        Object *obj = OBJECT(dev);
+        /* check if the device defines an identifcation string property */
+        char *value = object_property_get_str(obj, id_prop, NULL);
+        if (!value) {
+            continue;
+        }
+
+        bool is_set = (bool)strcmp(value, "");
+        if (is_set && !id_prepend) {
+            /* do not override already defined property */
+            g_free(value);
+            continue;
+        }
+
+        bool res;
+        if (is_set && id_prepend) {
+            char *pvalue = g_strconcat(id_value, ".", value, NULL);
+            res = object_property_set_str(obj, id_prop, pvalue, NULL);
+            g_free(pvalue);
+        } else {
+            res = object_property_set_str(obj, id_prop, id_value, NULL);
+        }
+        g_free(value);
+        if (!res) {
+            error_report("%s: cannot apply identifier to %s\n", __func__,
+                         object_get_typename(obj));
+        }
+    }
+}
+
+void ibex_configure_devices_with_id(DeviceState **devices, BusState *bus,
+                                    const char *id_prop, const char *id_value,
+                                    bool id_prepend, const IbexDeviceDef *defs,
+                                    unsigned count)
+{
+    ibex_link_devices(devices, defs, count);
+    ibex_define_device_props(devices, defs, count);
+    if (id_prop && id_value) {
+        ibex_identify_devices(devices, id_prop, id_value, id_prepend, count);
+    }
+    ibex_realize_devices(devices, bus, defs, count);
+    ibex_clock_devices(devices, defs, count);
+    ibex_connect_devices(devices, defs, count);
+}
+
+void ibex_configure_devices(DeviceState **devices, BusState *bus,
+                            const IbexDeviceDef *defs, unsigned count)
+{
+    ibex_configure_devices_with_id(devices, bus, NULL, NULL, false, defs,
+                                   count);
+}
+
+typedef struct {
+    Object *child;
+    const char *typename;
+    unsigned instance;
+} IbexChildMatch;
+
+static int ibex_match_device(Object *child, void *opaque)
+{
+    IbexChildMatch *match = opaque;
+
+    if (!object_dynamic_cast(child, match->typename)) {
+        return 0;
+    }
+    if (match->instance) {
+        match->instance -= 1;
+        return 0;
+    }
+
+    match->child = child;
+    return 1;
+}
+
+DeviceState *ibex_get_child_device(DeviceState *s, const char *typename,
+                                   unsigned instance)
+{
+    IbexChildMatch match = {
+        .child = NULL,
+        .typename = typename,
+        .instance = instance,
+    };
+
+    if (!object_child_foreach(OBJECT(s), &ibex_match_device, &match)) {
+        return NULL;
+    }
+
+    if (!object_dynamic_cast(match.child, TYPE_DEVICE)) {
+        return NULL;
+    }
+
+    return DEVICE(match.child);
+}
+
+typedef struct {
+    Chardev *chr;
+    const char *label;
+} IbexChrMatch;
+
+static int ibex_match_chardev(Object *child, void *opaque)
+{
+    IbexChrMatch *match = opaque;
+    Chardev *chr = CHARDEV(child);
+
+    if (strcmp(match->label, chr->label) != 0) {
+        return 0;
+    }
+
+    match->chr = chr;
+    return 1;
+}
+
+Chardev *ibex_get_chardev_by_id(const char *chrid)
+{
+    IbexChrMatch match = {
+        .chr = NULL,
+        .label = chrid,
+    };
+
+    /* "chardev-internal.h" inclusion is required for get_chardevs_root() */
+    if (!object_child_foreach(get_chardevs_root(), &ibex_match_chardev,
+                              &match)) {
+        return NULL;
+    }
+
+    return match.chr;
+}
+
+void ibex_unimp_configure(DeviceState *dev, const IbexDeviceDef *def,
+                          DeviceState *parent)
+{
+    (void)parent;
+
+    if (def->name) {
+        qdev_prop_set_string(dev, "name", def->name);
+    }
+    g_assert(def->memmap != NULL);
+}
+
+uint32_t ibex_load_kernel(CPUState *cpu)
+{
+    MachineState *ms = MACHINE(qdev_get_machine());
+
+    uint64_t kernel_entry;
+    /* load kernel if provided */
+    if (ms->kernel_filename) {
+        AddressSpace *as = NULL;
+        if (!cpu) {
+            CPUState *cs;
+            /* NOLINTNEXTLINE */
+            CPU_FOREACH(cs) {
+                if (cs->as) {
+                    as = cs->as;
+                    break;
+                }
+            }
+        } else {
+            as = cpu->as;
+        }
+        g_assert(as);
+        if (load_elf_ram_sym(ms->kernel_filename, NULL, NULL, NULL,
+                             &kernel_entry, NULL, NULL, NULL, 0, EM_RISCV, 1, 0,
+                             as, true, &rust_demangle_fn) <= 0) {
+            error_report("Cannot load ELF kernel %s", ms->kernel_filename);
+            qemu_system_shutdown_request_with_code(SHUTDOWN_CAUSE_HOST_ERROR,
+                                                   EXIT_FAILURE);
+        }
+
+        if (((uint32_t)kernel_entry & 0xFFu) != 0x80u) {
+            qemu_log("%s: invalid kernel entry address 0x%08x\n", __func__,
+                     (uint32_t)kernel_entry);
+        }
+
+        kernel_entry &= ~0xFFull;
+        Error *errp = NULL;
+        bool no_set_pc =
+            object_property_get_bool(OBJECT(ms), "ignore-elf-entry", &errp);
+        if (!no_set_pc) {
+            if (!cpu) {
+                CPUState *cs;
+                /* NOLINTNEXTLINE */
+                CPU_FOREACH(cs) {
+                    RISCV_CPU(cs)->env.resetvec = kernel_entry | 0x80ull;
+                    RISCV_CPU(cs)->cfg.mtvec = kernel_entry | 0b1ull;
+                }
+            } else {
+                RISCV_CPU(cpu)->env.resetvec = kernel_entry | 0x80ull;
+                RISCV_CPU(cpu)->cfg.mtvec = kernel_entry | 0b1ull;
+            }
+        }
+    } else {
+        kernel_entry = UINT64_MAX;
+    }
+
+    return (uint32_t)kernel_entry;
+}
+
+const char *ibex_common_get_func_name_by_addr(void *fn)
+{
+#ifdef CONFIG_POSIX
+    Dl_info info;
+    if (dladdr(fn, &info)) {
+        return info.dli_sname;
+    }
+#endif
+
+    return NULL;
+}
+
+uint32_t ibex_get_current_pc(void)
+{
+    CPUState *cs = current_cpu;
+
+    return cs && cs->cc->get_pc ? (uint32_t)cs->cc->get_pc(cs) : 0u;
+}
+
+int ibex_get_current_cpu(void)
+{
+    CPUState *cs = current_cpu;
+
+    return cs ? cs->cpu_index : -1;
+}
+
+/* x0 is replaced with PC */
+static const char ibex_ireg_names[32u][4u] = {
+    "pc", "ra", "sp", "gp", "tp",  "t0",  "t1", "t2", "s0", "s1", "a0",
+    "a1", "a2", "a3", "a4", "a5",  "a6",  "a7", "s2", "s3", "s4", "s5",
+    "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
+};
+
+void ibex_log_vcpu_registers(uint64_t regbm)
+{
+    CPURISCVState *env = &RISCV_CPU(current_cpu)->env;
+    qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n....\n");
+    if (regbm & 0x1u) {
+        qemu_log_mask(CPU_LOG_TB_IN_ASM, "%4s: 0x" TARGET_FMT_lx "\n",
+                      ibex_ireg_names[0], env->pc);
+    }
+    for (unsigned gix = 1u; gix < 32u; gix++) {
+        uint64_t mask = 1u << gix;
+        if (regbm & mask) {
+            qemu_log_mask(CPU_LOG_TB_IN_ASM, "%4s: 0x" TARGET_FMT_lx "\n",
+                          ibex_ireg_names[gix], env->gpr[gix]);
+        }
+    }
+}
+
+static void rust_demangle_fn(const char *st_name, int st_info,
+                             uint64_t st_value, uint64_t st_size)
+{
+    (void)st_info;
+    (void)st_value;
+
+    if (!st_size) {
+        return;
+    }
+
+    rust_demangle_replace((char *)st_name);
+}
+
+/*
+ * Note: this is not specific to Ibex, and might apply to any vCPU.
+ */
+static void hmp_info_ibex(Monitor *mon, const QDict *qdict)
+{
+    CPUState *cpu;
+    (void)qdict;
+
+    /* NOLINTNEXTLINE */
+    CPU_FOREACH(cpu) {
+        vaddr pc;
+        const char *symbol;
+        const char *cpu_state;
+        if (cpu->cc->get_pc) {
+            pc = cpu->cc->get_pc(cpu);
+            symbol = lookup_symbol(pc);
+        } else {
+            pc = -1;
+            symbol = "?";
+        }
+        if (cpu->halted && cpu->disabled) {
+            cpu_state = " [HD]";
+        } else if (cpu->halted) {
+            cpu_state = " [H]";
+        } else if (cpu->disabled) {
+            cpu_state = " [D]";
+        } else {
+            cpu_state = "";
+        }
+        monitor_printf(mon, "* CPU #%d%s: 0x%" PRIx64 " in '%s'\n",
+                       cpu->cpu_index, cpu_state, (uint64_t)pc, symbol);
+    }
+}
+
+static void ibex_register_types(void)
+{
+    monitor_register_hmp("ibex", true, &hmp_info_ibex);
+}
+
+type_init(ibex_register_types);
diff --git a/hw/riscv/ibex_gpio.c b/hw/riscv/ibex_gpio.c
new file mode 100644
index 0000000000000..869b28d45db05
--- /dev/null
+++ b/hw/riscv/ibex_gpio.c
@@ -0,0 +1,169 @@
+/*
+ * QEMU Ibex GPIOs
+ *
+ * Copyright (c) 2024 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qapi/qmp/qerror.h"
+#include "qapi/visitor.h"
+#include "hw/riscv/ibex_gpio.h"
+#include "trace.h"
+
+ibex_gpio ibex_gpio_combine(const ibex_gpio *levels, unsigned count)
+{
+    bool oweak = true;
+    bool odefined = false;
+    bool olevel = false;
+
+    while (count--) {
+        ibex_gpio ilevel = *levels++;
+        ibex_gpio_assert(ilevel);
+        if (ibex_gpio_is_hiz(ilevel)) {
+            continue;
+        }
+
+        bool weak = ibex_gpio_is_weak(ilevel);
+        bool level = ibex_gpio_level(ilevel);
+
+        if (!odefined) {
+            olevel = level;
+            oweak = weak;
+            odefined = true;
+            continue;
+        }
+
+        if (oweak) {
+            if (!weak) {
+                /* strong signal always overrides weak */
+                olevel = level;
+                oweak = weak;
+            } else if (level != olevel) {
+                qemu_log("%s: level conflict between weak signals\n", __func__);
+            }
+        } else if (!weak && (level != olevel)) {
+            qemu_log("%s: level conflict between strong signals\n", __func__);
+        }
+    }
+
+    if (!odefined) {
+        return IBEX_GPIO_INIT;
+    }
+
+    return oweak ? IBEX_GPIO_FROM_WEAK_SIG(olevel) :
+                   IBEX_GPIO_FROM_ACTIVE_SIG(olevel);
+}
+
+bool ibex_gpio_parse_level(const char *name, const char *value, ibex_gpio *obj,
+                           Error **errp)
+{
+    if (g_str_equal(value, "on") || g_str_equal(value, "hi") ||
+        g_str_equal(value, "1") || g_str_equal(value, "high")) {
+        *obj = IBEX_GPIO_HIGH;
+        return true;
+    }
+
+    if (g_str_equal(value, "off") || g_str_equal(value, "lo") ||
+        g_str_equal(value, "0") || g_str_equal(value, "low")) {
+        *obj = IBEX_GPIO_LOW;
+        return true;
+    }
+
+    if (g_str_equal(value, "pu") || g_str_equal(value, "pullup")) {
+        *obj = IBEX_GPIO_PULL_UP;
+        return true;
+    }
+
+    if (g_str_equal(value, "pd") || g_str_equal(value, "pulldown")) {
+        *obj = IBEX_GPIO_PULL_DOWN;
+        return true;
+    }
+
+    if (g_str_equal(value, "hiz") || g_str_equal(value, "z")) {
+        *obj = IBEX_GPIO_HIZ;
+        return true;
+    }
+
+    error_setg(errp, QERR_INVALID_PARAMETER_VALUE, name,
+               "'high' or 'low' or 'pu' or 'pd' or 'hiz'");
+    return false;
+}
+
+typedef struct {
+    ibex_gpio *value;
+} GpioLevelProperty;
+
+static void ibex_gpio_property_get(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
+{
+    (void)obj;
+    GpioLevelProperty *prop = opaque;
+    char *value;
+
+    g_assert(prop->value);
+    ibex_gpio val = *prop->value;
+    if (!ibex_gpio_check(val)) {
+        error_setg(errp, "Invalid IbexGPIO");
+        return;
+    }
+    if (ibex_gpio_is_hiz(val)) {
+        value = g_strdup("hiz");
+    } else if (ibex_gpio_is_weak(val)) {
+        value = g_strdup(ibex_gpio_level(val) ? "pu" : "pd");
+    } else {
+        value = g_strdup(ibex_gpio_level(val) ? "high" : "low");
+    }
+
+    visit_type_str(v, name, &value, errp);
+    g_free(value);
+}
+
+static void ibex_gpio_property_set(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
+{
+    (void)obj;
+    GpioLevelProperty *prop = opaque;
+    char *value;
+
+    if (!visit_type_str(v, name, &value, errp)) {
+        return;
+    }
+
+    ibex_gpio_parse_level(name, value, prop->value, errp);
+    g_free(value);
+}
+
+static void
+ibex_gpio_property_release_data(Object *obj, const char *name, void *opaque)
+{
+    (void)obj;
+    (void)name;
+    g_free(opaque);
+}
+
+ObjectProperty *
+object_property_add_ibex_gpio(Object *obj, const char *name, ibex_gpio *value)
+{
+    GpioLevelProperty *prop = g_new0(GpioLevelProperty, 1u);
+    prop->value = value;
+
+    return object_property_add(obj, name, "string", &ibex_gpio_property_get,
+                               &ibex_gpio_property_set,
+                               &ibex_gpio_property_release_data, prop);
+}
diff --git a/hw/riscv/ibexdemo.c b/hw/riscv/ibexdemo.c
new file mode 100644
index 0000000000000..1d16e622448c2
--- /dev/null
+++ b/hw/riscv/ibexdemo.c
@@ -0,0 +1,541 @@
+/*
+ * QEMU RISC-V Board Compatible with Ibex Demo System FPGA platform
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Notes: GPIO output, SIMCTRL, SPI, TIMER, UART and ST7735 devices are
+ *        supported. PWM is only a dummy device, GPIO inputs are not supported.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "chardev/chardev-internal.h"
+#include "cpu.h"
+#include "hw/boards.h"
+#include "hw/display/st7735.h"
+#include "hw/ibexdemo/ibexdemo_gpio.h"
+#include "hw/ibexdemo/ibexdemo_simctrl.h"
+#include "hw/ibexdemo/ibexdemo_spi.h"
+#include "hw/ibexdemo/ibexdemo_timer.h"
+#include "hw/ibexdemo/ibexdemo_uart.h"
+#include "hw/jtag/tap_ctrl.h"
+#include "hw/jtag/tap_ctrl_rbb.h"
+#include "hw/misc/pulp_rv_dm.h"
+#include "hw/misc/unimp.h"
+#include "hw/qdev-properties.h"
+#include "hw/riscv/dm.h"
+#include "hw/riscv/dtm.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ibexdemo.h"
+#include "hw/ssi/ssi.h"
+#include "qobject/qlist.h"
+#include "system/address-spaces.h"
+#include "system/system.h"
+
+/* ------------------------------------------------------------------------ */
+/* Forward Declarations */
+/* ------------------------------------------------------------------------ */
+
+static void ibexdemo_soc_dm_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ibexdemo_soc_gpio_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ibexdemo_soc_hart_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ibexdemo_soc_tap_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ibexdemo_soc_uart_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+
+/* ------------------------------------------------------------------------ */
+/* Constants */
+/* ------------------------------------------------------------------------ */
+
+/* clang-format off */
+static const uint32_t IBEXDEMO_BOOT[] = {
+    /* Exception vectors */
+    0x0840006fu, 0x0800006fu, 0x07c0006fu, 0x0780006fu, 0x0740006fu,
+    0x0700006fu, 0x06c0006fu, 0x0680006fu, 0x0640006fu, 0x0600006fu,
+    0x05c0006fu, 0x0580006fu, 0x0540006fu, 0x0500006fu, 0x04c0006fu,
+    0x0480006fu, 0x0440006fu, 0x0400006fu, 0x03c0006fu, 0x0380006fu,
+    0x0340006fu, 0x0300006fu, 0x02c0006fu, 0x0280006fu, 0x0240006fu,
+    0x0200006fu, 0x01c0006fu, 0x0180006fu, 0x0140006fu, 0x0100006fu,
+    0x00c0006fu, 0x0080006fu,
+    /* reset vector */
+    0x0040006fu,
+    /* blank_loop */
+    0x10500073u, /* wfi */
+    0x0000bff5u, /* j blank_loop */
+};
+/* clang-format on */
+
+enum IbexDemoSocDevice {
+    IBEXDEMO_SOC_DEV_DM,
+    IBEXDEMO_SOC_DEV_DTM,
+    IBEXDEMO_SOC_DEV_GPIO,
+    IBEXDEMO_SOC_DEV_HART,
+    IBEXDEMO_SOC_DEV_PWM,
+    IBEXDEMO_SOC_DEV_RV_DM,
+    IBEXDEMO_SOC_DEV_SIM_CTRL,
+    IBEXDEMO_SOC_DEV_SPI,
+    IBEXDEMO_SOC_DEV_TAP_CTRL,
+    IBEXDEMO_SOC_DEV_TIMER,
+    IBEXDEMO_SOC_DEV_UART,
+};
+
+enum IbexDemoBoardDevice {
+    IBEXDEMO_BOARD_DEV_SOC,
+    IBEXDEMO_BOARD_DEV_DISPLAY,
+    _IBEXDEMO_BOARD_DEV_COUNT
+};
+
+#define IBEXDEMO_SOC_DEVLINK(_pname_, _target_) \
+    IBEX_DEVLINK(_pname_, IBEXDEMO_SOC_DEV_##_target_)
+
+/*
+ * Ibex Demo System RV DM
+ * see https://github.com/lowRISC/part-number-registry/blob/main/jtag_partno.md
+ */
+#define IBEXDEMO_TAP_IDCODE IBEX_JTAG_IDCODE(256, 1, 0)
+
+#define PULP_DM_BASE   0x00010000u
+#define SRAM_MAIN_BASE 0x100000u
+#define SRAM_MAIN_SIZE 0x10000u
+
+#define NUM_PWM_MODULES 12u
+#define PWM_SIZE        (NUM_PWM_MODULES * 8u)
+
+#define IBEXDEMO_DM_CONNECTION(_dst_dev_, _num_) \
+    { \
+        .out = { \
+            .name = PULP_RV_DM_ACK_OUT_LINES, \
+            .num = (_num_), \
+        }, \
+        .in = { \
+            .name = RISCV_DM_ACK_LINES, \
+            .index = (_dst_dev_), \
+            .num = (_num_), \
+        } \
+    }
+
+static const IbexDeviceDef ibexdemo_soc_devices[] = {
+    /* clang-format off */
+    [IBEXDEMO_SOC_DEV_HART] = {
+        .type = TYPE_RISCV_CPU_LOWRISC_IBEXDEMO,
+        .cfg = &ibexdemo_soc_hart_configure,
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("mtvec", 0x00100001u),
+            IBEX_DEV_UINT_PROP("dmhaltvec", PULP_DM_BASE +
+                PULP_RV_DM_ROM_BASE + PULP_RV_DM_HALT_OFFSET),
+            IBEX_DEV_UINT_PROP("dmexcpvec", PULP_DM_BASE +
+                PULP_RV_DM_ROM_BASE + PULP_RV_DM_EXCEPTION_OFFSET)
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_TAP_CTRL] = {
+        .type = TYPE_TAP_CTRL_RBB,
+        .cfg = &ibexdemo_soc_tap_ctrl_configure,
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("ir_length", IBEX_TAP_IR_LENGTH),
+            IBEX_DEV_UINT_PROP("idcode", IBEXDEMO_TAP_IDCODE)
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_DTM] = {
+        .type = TYPE_RISCV_DTM,
+        .link = IBEXDEVICELINKDEFS(
+            IBEXDEMO_SOC_DEVLINK("tap-ctrl", TAP_CTRL)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("abits", 7u)
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_DM] = {
+        .type = TYPE_RISCV_DM,
+        .cfg = &ibexdemo_soc_dm_configure,
+        .link = IBEXDEVICELINKDEFS(
+            IBEXDEMO_SOC_DEVLINK("dtm", DTM)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("nscratch", PULP_RV_DM_NSCRATCH_COUNT),
+            IBEX_DEV_UINT_PROP("progbuf_count",
+                PULP_RV_DM_PROGRAM_BUFFER_COUNT),
+            IBEX_DEV_UINT_PROP("data_count", PULP_RV_DM_DATA_COUNT),
+            IBEX_DEV_UINT_PROP("abstractcmd_count",
+                PULP_RV_DM_ABSTRACTCMD_COUNT),
+            IBEX_DEV_UINT_PROP("dm_phyaddr", PULP_DM_BASE),
+            IBEX_DEV_UINT_PROP("rom_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_ROM_BASE),
+            IBEX_DEV_UINT_PROP("whereto_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_WHERETO_OFFSET),
+            IBEX_DEV_UINT_PROP("data_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_DATAADDR_OFFSET),
+            IBEX_DEV_UINT_PROP("progbuf_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_PROGRAM_BUFFER_OFFSET),
+            IBEX_DEV_UINT_PROP("resume_offset", PULP_RV_DM_RESUME_OFFSET),
+            IBEX_DEV_BOOL_PROP("sysbus_access", true),
+            IBEX_DEV_BOOL_PROP("abstractauto", false)
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_RV_DM] = {
+        .type = TYPE_PULP_RV_DM,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x00000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            IBEXDEMO_DM_CONNECTION(IBEXDEMO_SOC_DEV_DM, 0),
+            IBEXDEMO_DM_CONNECTION(IBEXDEMO_SOC_DEV_DM, 1),
+            IBEXDEMO_DM_CONNECTION(IBEXDEMO_SOC_DEV_DM, 2),
+            IBEXDEMO_DM_CONNECTION(IBEXDEMO_SOC_DEV_DM, 3)
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_SIM_CTRL] = {
+        .type = TYPE_IBEXDEMO_SIMCTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x00020000u }
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_GPIO] = {
+        .type = TYPE_IBEXDEMO_GPIO,
+        .cfg = &ibexdemo_soc_gpio_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x80000000u }
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_UART] = {
+        .type = TYPE_IBEXDEMO_UART,
+        .cfg = &ibexdemo_soc_uart_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x80001000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            IBEX_GPIO_SYSBUS_IRQ(0, IBEXDEMO_SOC_DEV_HART, 16)
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_TIMER] = {
+        .type = TYPE_IBEXDEMO_TIMER,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x80002000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            IBEX_GPIO_SYSBUS_IRQ(0, IBEXDEMO_SOC_DEV_HART, IRQ_M_TIMER)
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_PWM] = {
+        .type = TYPE_UNIMPLEMENTED_DEVICE,
+        .name = "ibexdemo-pwm",
+        .cfg = &ibex_unimp_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x80003000u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("size", PWM_SIZE)
+        ),
+    },
+    [IBEXDEMO_SOC_DEV_SPI] = {
+        .type = TYPE_IBEXDEMO_SPI,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x80004000u }
+        ),
+    },
+    /* clang-format on */
+};
+
+/* ------------------------------------------------------------------------ */
+/* Type definitions */
+/* ------------------------------------------------------------------------ */
+
+struct IbexDemoSoCState {
+    SysBusDevice parent_obj;
+
+    DeviceState **devices;
+
+    /* properties */
+    uint32_t resetvec;
+};
+
+struct IbexDemoBoardState {
+    DeviceState parent_obj;
+
+    DeviceState **devices;
+};
+
+struct IbexDemoMachineState {
+    MachineState parent_obj;
+
+    char *rv_exts;
+};
+
+/* ------------------------------------------------------------------------ */
+/* Device Configuration */
+/* ------------------------------------------------------------------------ */
+
+static void ibexdemo_soc_dm_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)def;
+    (void)parent;
+
+    QList *hart = qlist_new();
+    qlist_append_int(hart, 0);
+    qdev_prop_set_array(dev, "hart", hart);
+
+    RISCVDMMemAttrs pulp_attrs = {
+        .attrs = {
+            .requester_id = PULP_RV_DM_REQUESTER_ID,
+        },
+    };
+    qdev_prop_set_uint64(dev, "mta_dm", pulp_attrs.value);
+}
+
+
+static void ibexdemo_soc_gpio_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)def;
+    (void)parent;
+    qdev_prop_set_uint32(dev, "in_count", IBEXDEMO_GPIO_IN_MAX);
+    qdev_prop_set_uint32(dev, "out_count", IBEXDEMO_GPIO_OUT_MAX);
+}
+
+static void ibexdemo_soc_hart_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)def;
+    (void)parent;
+    IbexDemoSoCState *s = RISCV_IBEXDEMO_SOC(parent);
+
+    qdev_prop_set_uint64(dev, "resetvec", s->resetvec);
+}
+
+static void ibexdemo_soc_tap_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)parent;
+    (void)def;
+
+    Chardev *chr;
+
+    chr = ibex_get_chardev_by_id("taprbb");
+    if (chr) {
+        qdev_prop_set_chr(dev, "chardev", chr);
+    }
+}
+
+static void ibexdemo_soc_uart_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)parent;
+    qdev_prop_set_chr(dev, "chardev", serial_hd(def->instance));
+}
+
+/* ------------------------------------------------------------------------ */
+/* SoC */
+/* ------------------------------------------------------------------------ */
+
+static void ibexdemo_soc_load_boot(void)
+{
+    /* do not use rom_add_blob_fixed_as as absolute address is not yet known */
+    MachineState *ms = MACHINE(qdev_get_machine());
+    void *ram = memory_region_get_ram_ptr(ms->ram);
+    if (!ram) {
+        error_setg(&error_fatal, "no main RAM");
+        /* linter cannot detect error_fatal prevents from returning */
+        abort();
+    }
+    memcpy(ram, IBEXDEMO_BOOT, sizeof(IBEXDEMO_BOOT));
+}
+
+static void ibexdemo_soc_reset(DeviceState *dev)
+{
+    IbexDemoSoCState *s = RISCV_IBEXDEMO_SOC(dev);
+
+    device_cold_reset(s->devices[IBEXDEMO_SOC_DEV_DTM]);
+    device_cold_reset(s->devices[IBEXDEMO_SOC_DEV_DM]);
+
+    cpu_reset(CPU(s->devices[IBEXDEMO_SOC_DEV_HART]));
+}
+
+static void ibexdemo_soc_realize(DeviceState *dev, Error **errp)
+{
+    (void)errp;
+
+    IbexDemoSoCState *s = RISCV_IBEXDEMO_SOC(dev);
+
+    MachineState *ms = MACHINE(qdev_get_machine());
+    MemoryRegion *sys_mem = get_system_memory();
+    memory_region_add_subregion(sys_mem, SRAM_MAIN_BASE, ms->ram);
+
+    ibex_link_devices(s->devices, ibexdemo_soc_devices,
+                      ARRAY_SIZE(ibexdemo_soc_devices));
+    ibex_define_device_props(s->devices, ibexdemo_soc_devices,
+                             ARRAY_SIZE(ibexdemo_soc_devices));
+    ibex_realize_system_devices(s->devices, ibexdemo_soc_devices,
+                                ARRAY_SIZE(ibexdemo_soc_devices));
+    ibex_clock_devices(s->devices, ibexdemo_soc_devices,
+                       ARRAY_SIZE(ibexdemo_soc_devices));
+    ibex_connect_devices(s->devices, ibexdemo_soc_devices,
+                         ARRAY_SIZE(ibexdemo_soc_devices));
+
+    ibexdemo_soc_load_boot();
+
+    /* load application if provided */
+    ibex_load_kernel(NULL);
+}
+
+static void ibexdemo_soc_init(Object *obj)
+{
+    IbexDemoSoCState *s = RISCV_IBEXDEMO_SOC(obj);
+
+    s->devices =
+        ibex_create_devices(ibexdemo_soc_devices,
+                            ARRAY_SIZE(ibexdemo_soc_devices), DEVICE(s));
+}
+
+static const Property ibexdemo_soc_props[] = {
+    DEFINE_PROP_UINT32("resetvec", IbexDemoSoCState, resetvec, 0x00100080u),
+};
+
+static void ibexdemo_soc_class_init(ObjectClass *oc, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    (void)data;
+
+    device_class_set_props(dc, ibexdemo_soc_props);
+    device_class_set_legacy_reset(dc, &ibexdemo_soc_reset);
+    dc->realize = &ibexdemo_soc_realize;
+    dc->user_creatable = false;
+}
+
+static const TypeInfo ibexdemo_soc_type_info = {
+    .name = TYPE_RISCV_IBEXDEMO_SOC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IbexDemoSoCState),
+    .instance_init = &ibexdemo_soc_init,
+    .class_init = &ibexdemo_soc_class_init,
+};
+
+static void ibexdemo_soc_register_types(void)
+{
+    type_register_static(&ibexdemo_soc_type_info);
+}
+
+type_init(ibexdemo_soc_register_types);
+
+/* ------------------------------------------------------------------------ */
+/* Board */
+/* ------------------------------------------------------------------------ */
+
+static void ibexdemo_board_realize(DeviceState *dev, Error **errp)
+{
+    IbexDemoBoardState *board = RISCV_IBEXDEMO_BOARD(dev);
+    (void)errp;
+
+    IbexDemoSoCState *soc =
+        RISCV_IBEXDEMO_SOC(board->devices[IBEXDEMO_BOARD_DEV_SOC]);
+
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(soc), &error_fatal);
+
+    BusState *spibus =
+        qdev_get_child_bus(DEVICE(soc->devices[IBEXDEMO_SOC_DEV_SPI]), "spi0");
+    g_assert(spibus);
+
+    board->devices[IBEXDEMO_BOARD_DEV_DISPLAY] =
+        DEVICE(ST7735(ssi_create_peripheral(SSI_BUS(spibus), TYPE_ST7735)));
+
+    qemu_irq cs, dc, rst;
+
+    dev = board->devices[IBEXDEMO_BOARD_DEV_DISPLAY];
+    cs = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
+    dc = qdev_get_gpio_in_named(dev, ST7735_IO_LINES, ST7735_IO_D_C);
+    rst = qdev_get_gpio_in_named(dev, ST7735_IO_LINES, ST7735_IO_RESET);
+
+    dev = soc->devices[IBEXDEMO_SOC_DEV_GPIO];
+    qdev_connect_gpio_out_named(dev, IBEXDEMO_GPIO_OUT_LINES, 0, cs);
+    qdev_connect_gpio_out_named(dev, IBEXDEMO_GPIO_OUT_LINES, 1, rst);
+    qdev_connect_gpio_out_named(dev, IBEXDEMO_GPIO_OUT_LINES, 2, dc);
+}
+
+static void ibexdemo_board_instance_init(Object *obj)
+{
+    IbexDemoBoardState *s = RISCV_IBEXDEMO_BOARD(obj);
+
+    s->devices = g_new0(DeviceState *, _IBEXDEMO_BOARD_DEV_COUNT);
+    s->devices[IBEXDEMO_BOARD_DEV_SOC] = qdev_new(TYPE_RISCV_IBEXDEMO_SOC);
+
+    object_property_add_child(obj, "soc",
+                              OBJECT(s->devices[IBEXDEMO_BOARD_DEV_SOC]));
+}
+
+static void ibexdemo_board_class_init(ObjectClass *oc, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    (void)data;
+
+    dc->realize = &ibexdemo_board_realize;
+}
+
+static const TypeInfo ibexdemo_board_type_info = {
+    .name = TYPE_RISCV_IBEXDEMO_BOARD,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(IbexDemoBoardState),
+    .instance_init = &ibexdemo_board_instance_init,
+    .class_init = &ibexdemo_board_class_init,
+};
+
+static void ibexdemo_board_register_types(void)
+{
+    type_register_static(&ibexdemo_board_type_info);
+}
+
+type_init(ibexdemo_board_register_types);
+
+/* ------------------------------------------------------------------------ */
+/* Machine */
+/* ------------------------------------------------------------------------ */
+
+static void ibexdemo_machine_init(MachineState *state)
+{
+    DeviceState *dev = qdev_new(TYPE_RISCV_IBEXDEMO_BOARD);
+
+    object_property_add_child(OBJECT(state), "board", OBJECT(dev));
+
+    qdev_realize(dev, NULL, &error_fatal);
+}
+
+static void ibexdemo_machine_class_init(ObjectClass *oc, const void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    (void)data;
+
+    mc->desc = "RISC-V Board compatible with IbexDemo";
+    mc->init = ibexdemo_machine_init;
+    mc->max_cpus = 1u;
+    mc->default_cpu_type = ibexdemo_soc_devices[IBEXDEMO_SOC_DEV_HART].type;
+    mc->default_ram_id = "ibexdemo.ram";
+    mc->default_ram_size = SRAM_MAIN_SIZE;
+}
+
+static const TypeInfo ibexdemo_machine_type_info = {
+    .name = TYPE_RISCV_IBEXDEMO_MACHINE,
+    .parent = TYPE_MACHINE,
+    .instance_size = sizeof(IbexDemoMachineState),
+    .class_init = &ibexdemo_machine_class_init,
+};
+
+static void ibexdemo_machine_register_types(void)
+{
+    type_register_static(&ibexdemo_machine_type_info);
+}
+
+type_init(ibexdemo_machine_register_types);
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 2a8d5b136cc40..9b59949b50560 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -2,7 +2,13 @@ riscv_ss = ss.source_set()
 riscv_ss.add(files('boot.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
 riscv_ss.add(files('riscv_hart.c'))
+riscv_ss.add(when: 'CONFIG_IBEXDEMO', if_true: files('ibexdemo.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
+riscv_ss.add(when: 'CONFIG_IBEX_CLOCK_SRC', if_true: files('ibex_clock_src.c'))
+riscv_ss.add(when: 'CONFIG_IBEX_COMMON', if_true: files('ibex_common.c'))
+riscv_ss.add(when: 'CONFIG_IBEX_GPIO', if_true: files('ibex_gpio.c'))
+riscv_ss.add(when: 'CONFIG_OT_DARJEELING', if_true: files('ot_darjeeling.c'))
+riscv_ss.add(when: 'CONFIG_OT_EARLGREY', if_true: files('ot_earlgrey.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
@@ -14,5 +20,8 @@ riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(
 	'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-hpm.c'))
 riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
 riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan_kmh.c'))
+riscv_ss.add(when: 'CONFIG_RISCV_DEBUG', if_true: files('debug.c'))
+riscv_ss.add(when: 'CONFIG_RISCV_DM', if_true: files('dm.c'))
+riscv_ss.add(when: 'CONFIG_RISCV_DTM', if_true: files('dtm.c'))
 
 hw_arch += {'riscv': riscv_ss}
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index a17f62cd082dd..9fcdd73daf82a 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -287,7 +287,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
         MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
         MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
-        memmap[MICROCHIP_PFSOC_PLIC].size);
+        memmap[MICROCHIP_PFSOC_PLIC].size,
+        false);
     g_free(plic_hart_config);
 
     /* DMA */
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index d369a8a7dcd18..f5f8ce0a51ff9 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -119,7 +119,7 @@ static void opentitan_machine_class_init(ObjectClass *oc, const void *data)
     mc->desc = "RISC-V Board compatible with OpenTitan";
     mc->init = opentitan_machine_init;
     mc->max_cpus = 1;
-    mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
+    mc->default_cpu_type = TYPE_RISCV_CPU_LOWRISC_IBEX;
     mc->default_ram_id = "riscv.lowrisc.ibex.ram";
     mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
 }
@@ -152,13 +152,17 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     MemoryRegion *sys_mem = get_system_memory();
     int i;
 
-    object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
-                            &error_abort);
-    object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
-                            &error_abort);
-    object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
-                            &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
+    Object *cpu = OBJECT(&s->cpus.harts[0]);
+    object_property_set_int(cpu, "resetvec", s->resetvec,
+                            &error_fatal);
+    object_property_set_bool(cpu, "m", true, &error_fatal);
+    object_property_set_bool(cpu, "pmp", true, &error_fatal);
+    object_property_set_bool(cpu, "zba", true, &error_fatal);
+    object_property_set_bool(cpu, "zbb", true, &error_fatal);
+    object_property_set_bool(cpu, "zbc", true, &error_fatal);
+    object_property_set_bool(cpu, "zbs", true, &error_fatal);
+    object_property_set_bool(cpu, "smepmp", true, &error_fatal);
+    qdev_realize(DEVICE(&s->cpus), NULL, &error_fatal);
 
     /* Boot ROM */
     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
@@ -194,10 +198,10 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
 
     for (i = 0; i < ms->smp.cpus; i++) {
-        CPUState *cpu = qemu_get_cpu(i);
+        CPUState *cpu_state = qemu_get_cpu(i);
 
         qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
-                              qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
+                              qdev_get_gpio_in(DEVICE(cpu_state), IRQ_M_EXT));
     }
 
     /* UART */
diff --git a/hw/riscv/ot_darjeeling.c b/hw/riscv/ot_darjeeling.c
new file mode 100644
index 0000000000000..1a3e5692f4319
--- /dev/null
+++ b/hw/riscv/ot_darjeeling.c
@@ -0,0 +1,2170 @@
+/*
+ * QEMU RISC-V Board Compatible with OpenTitan Darjeeling platform
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Based on 0fc384d8a6
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/core/split-irq.h"
+#include "hw/intc/sifive_plic.h"
+#include "hw/jtag/tap_ctrl.h"
+#include "hw/jtag/tap_ctrl_rbb.h"
+#include "hw/loader.h"
+#include "hw/misc/pulp_rv_dm.h"
+#include "hw/opentitan/ot_address_space.h"
+#include "hw/opentitan/ot_aes.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_aon_timer.h"
+#include "hw/opentitan/ot_ast_dj.h"
+#include "hw/opentitan/ot_clkmgr.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_csrng.h"
+#include "hw/opentitan/ot_dev_proxy.h"
+#include "hw/opentitan/ot_dm_tl.h"
+#include "hw/opentitan/ot_dma.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_entropy_src.h"
+#include "hw/opentitan/ot_gpio_dj.h"
+#include "hw/opentitan/ot_hmac.h"
+#include "hw/opentitan/ot_i2c.h"
+#include "hw/opentitan/ot_ibex_wrapper.h"
+#include "hw/opentitan/ot_keymgr_dpe.h"
+#include "hw/opentitan/ot_kmac.h"
+#include "hw/opentitan/ot_lc_ctrl.h"
+#include "hw/opentitan/ot_mbx.h"
+#include "hw/opentitan/ot_otbn.h"
+#include "hw/opentitan/ot_otp_dj.h"
+#include "hw/opentitan/ot_otp_if.h"
+#include "hw/opentitan/ot_otp_ot_be.h"
+#include "hw/opentitan/ot_pinmux_dj.h"
+#include "hw/opentitan/ot_plic_ext.h"
+#include "hw/opentitan/ot_pwrmgr.h"
+#include "hw/opentitan/ot_rom_ctrl.h"
+#include "hw/opentitan/ot_rstmgr.h"
+#include "hw/opentitan/ot_soc_dbg_ctrl.h"
+#include "hw/opentitan/ot_soc_proxy.h"
+#include "hw/opentitan/ot_spi_device.h"
+#include "hw/opentitan/ot_spi_host.h"
+#include "hw/opentitan/ot_sram_ctrl.h"
+#include "hw/opentitan/ot_timer.h"
+#include "hw/opentitan/ot_uart.h"
+#include "hw/opentitan/ot_unimp.h"
+#include "hw/opentitan/ot_vmapper.h"
+#include "hw/qdev-properties.h"
+#include "hw/riscv/dm.h"
+#include "hw/riscv/dtm.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ot_darjeeling.h"
+#include "hw/ssi/ssi.h"
+#include "qobject/qlist.h"
+#include "system/address-spaces.h"
+#include "system/blockdev.h"
+#include "system/hw_accel.h"
+#include "system/reset.h"
+#include "system/system.h"
+
+/* ------------------------------------------------------------------------ */
+/* Forward Declarations */
+/* ------------------------------------------------------------------------ */
+static void ot_dj_soc_ast_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                    DeviceState *parent);
+static void ot_dj_soc_dm_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                   DeviceState *parent);
+static void ot_dj_soc_hart_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                     DeviceState *parent);
+static void ot_dj_soc_otp_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ot_dj_soc_tap_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ot_dj_soc_spi_device_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ot_dj_soc_uart_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                     DeviceState *parent);
+
+/* ------------------------------------------------------------------------ */
+/* Constants */
+/* ------------------------------------------------------------------------ */
+
+enum OtDjMemoryRegion {
+    OT_DJ_DEFAULT_MEMORY_REGION,
+    OT_DJ_CTN_MEMORY_REGION,
+    OT_DJ_DEBUG_MEMORY_REGION,
+};
+
+enum OtDjSocDevice {
+    OT_DJ_SOC_DEV_AC_RANGE_CHECK,
+    OT_DJ_SOC_DEV_AES,
+    OT_DJ_SOC_DEV_ALERT_HANDLER,
+    OT_DJ_SOC_DEV_AON_TIMER,
+    OT_DJ_SOC_DEV_AST,
+    OT_DJ_SOC_DEV_CLKMGR,
+    OT_DJ_SOC_DEV_CSRNG,
+    OT_DJ_SOC_DEV_DM_MBX,
+    OT_DJ_SOC_DEV_DM_LC_CTRL,
+    OT_DJ_SOC_DEV_DM,
+    OT_DJ_SOC_DEV_DMA,
+    OT_DJ_SOC_DEV_DTM,
+    OT_DJ_SOC_DEV_EDN0,
+    OT_DJ_SOC_DEV_EDN1,
+    OT_DJ_SOC_DEV_ENTROPY_SRC,
+    OT_DJ_SOC_DEV_GPIO,
+    OT_DJ_SOC_DEV_HART,
+    OT_DJ_SOC_DEV_HMAC,
+    OT_DJ_SOC_DEV_I2C0,
+    OT_DJ_SOC_DEV_IBEX_WRAPPER,
+    OT_DJ_SOC_DEV_KEYMGR_DPE,
+    OT_DJ_SOC_DEV_KMAC,
+    OT_DJ_SOC_DEV_LC_CTRL,
+    OT_DJ_SOC_DEV_MBX0,
+    OT_DJ_SOC_DEV_MBX1,
+    OT_DJ_SOC_DEV_MBX2,
+    OT_DJ_SOC_DEV_MBX3,
+    OT_DJ_SOC_DEV_MBX4,
+    OT_DJ_SOC_DEV_MBX5,
+    OT_DJ_SOC_DEV_MBX6,
+    OT_DJ_SOC_DEV_MBX_JTAG,
+    OT_DJ_SOC_DEV_MBX_PCIE0,
+    OT_DJ_SOC_DEV_MBX_PCIE1,
+    OT_DJ_SOC_DEV_OTBN,
+    OT_DJ_SOC_DEV_OTP_BACKEND,
+    OT_DJ_SOC_DEV_OTP_CTRL,
+    OT_DJ_SOC_DEV_PINMUX,
+    OT_DJ_SOC_DEV_PLIC,
+    OT_DJ_SOC_DEV_PLIC_EXT,
+    OT_DJ_SOC_DEV_PWRMGR,
+    OT_DJ_SOC_DEV_RACL_CTRL,
+    OT_DJ_SOC_DEV_ROM_CTRL0,
+    OT_DJ_SOC_DEV_ROM_CTRL1,
+    OT_DJ_SOC_DEV_RSTMGR,
+    OT_DJ_SOC_DEV_RV_DM,
+    OT_DJ_SOC_DEV_SOC_DBG_CTRL,
+    OT_DJ_SOC_DEV_SOC_PROXY,
+    OT_DJ_SOC_DEV_SPI_DEVICE,
+    OT_DJ_SOC_DEV_SPI_HOST0,
+    OT_DJ_SOC_DEV_SRAM_CTRL_MAIN,
+    OT_DJ_SOC_DEV_SRAM_CTRL_MBOX,
+    OT_DJ_SOC_DEV_SRAM_CTRL_RET,
+    OT_DJ_SOC_DEV_TAP_CTRL,
+    OT_DJ_SOC_DEV_TIMER,
+    OT_DJ_SOC_DEV_UART0,
+    OT_DJ_SOC_DEV_VMAPPER,
+    /* IRQ splitters, i.e. 1-to-N signal dispatchers */
+    OT_DJ_SOC_SPLITTER_LC_HW_DEBUG,
+    OT_DJ_SOC_SPLITTER_LC_ESCALATE,
+};
+
+enum OtDjResetRequest {
+    OT_DJ_RESET_AON_TIMER,
+    OT_DJ_RESET_SOC_PROXY,
+    OT_DJ_RESET_COUNT,
+};
+
+enum OtDjResetWakeup {
+    OT_DJ_WAKEUP_PINMUX_AON_PIN,
+    OT_DJ_WAKEUP_PINMUX_AON_USB,
+    OT_DJ_WAKEUP_AON_TIMER_AON,
+    OT_DJ_WAKEUP_SENSOR_CTRL,
+    OT_DJ_WAKEUP_SOC_PROXY_INTERNAL,
+    OT_DJ_WAKEUP_SOC_PROXY_EXTERNAL,
+    OT_DJ_WAKEUP_COUNT,
+};
+
+enum OtDjPinmuxDio {
+    DIO_SPI_HOST0_SD0, /* 0 */
+    DIO_SPI_HOST0_SD1, /* 1 */
+    DIO_SPI_HOST0_SD2, /* 2 */
+    DIO_SPI_HOST0_SD3, /* 3 */
+    DIO_SPI_DEVICE_SD0, /* 4 */
+    DIO_SPI_DEVICE_SD1, /* 5 */
+    DIO_SPI_DEVICE_SD2, /* 6 */
+    DIO_SPI_DEVICE_SD3, /* 7 */
+    DIO_I2C0_SCL, /* 8 */
+    DIO_I2C0_SDA, /* 9 */
+    DIO_GPIO_GPIO0, /* 10 */
+    DIO_GPIO_GPIO1, /* 11 */
+    DIO_GPIO_GPIO2, /* 12 */
+    DIO_GPIO_GPIO3, /* 13 */
+    DIO_GPIO_GPIO4, /* 14 */
+    DIO_GPIO_GPIO5, /* 15 */
+    DIO_GPIO_GPIO6, /* 16 */
+    DIO_GPIO_GPIO7, /* 17 */
+    DIO_GPIO_GPIO8, /* 18 */
+    DIO_GPIO_GPIO9, /* 19 */
+    DIO_GPIO_GPIO10, /* 20 */
+    DIO_GPIO_GPIO11, /* 21 */
+    DIO_GPIO_GPIO12, /* 22 */
+    DIO_GPIO_GPIO13, /* 23 */
+    DIO_GPIO_GPIO14, /* 24 */
+    DIO_GPIO_GPIO15, /* 25 */
+    DIO_GPIO_GPIO16, /* 26 */
+    DIO_GPIO_GPIO17, /* 27 */
+    DIO_GPIO_GPIO18, /* 28 */
+    DIO_GPIO_GPIO19, /* 29 */
+    DIO_GPIO_GPIO20, /* 30 */
+    DIO_GPIO_GPIO21, /* 31 */
+    DIO_GPIO_GPIO22, /* 32 */
+    DIO_GPIO_GPIO23, /* 33 */
+    DIO_GPIO_GPIO24, /* 34 */
+    DIO_GPIO_GPIO25, /* 35 */
+    DIO_GPIO_GPIO26, /* 36 */
+    DIO_GPIO_GPIO27, /* 37 */
+    DIO_GPIO_GPIO28, /* 38 */
+    DIO_GPIO_GPIO29, /* 39 */
+    DIO_GPIO_GPIO30, /* 40 */
+    DIO_GPIO_GPIO31, /* 41 */
+    DIO_SPI_DEVICE_SCK, /* 42 */
+    DIO_SPI_DEVICE_CSB, /* 43 */
+    DIO_SPI_DEVICE_TPM_CSB, /* 44 */
+    DIO_UART0_RX, /* 45 */
+    DIO_SOC_PROXY_SOC_GPI0, /* 46 */
+    DIO_SOC_PROXY_SOC_GPI1, /* 47 */
+    DIO_SOC_PROXY_SOC_GPI2, /* 48 */
+    DIO_SOC_PROXY_SOC_GPI3, /* 49 */
+    DIO_SOC_PROXY_SOC_GPI4, /* 50 */
+    DIO_SOC_PROXY_SOC_GPI5, /* 51 */
+    DIO_SOC_PROXY_SOC_GPI6, /* 52 */
+    DIO_SOC_PROXY_SOC_GPI7, /* 53 */
+    DIO_SOC_PROXY_SOC_GPI8, /* 54 */
+    DIO_SOC_PROXY_SOC_GPI9, /* 55 */
+    DIO_SOC_PROXY_SOC_GPI10, /* 56 */
+    DIO_SOC_PROXY_SOC_GPI11, /* 57 */
+    DIO_SPI_HOST0_SCK, /* 58 */
+    DIO_SPI_HOST0_CSB, /* 59 */
+    DIO_UART0_TX, /* 60 */
+    DIO_SOC_PROXY_SOC_GPO0, /* 61 */
+    DIO_SOC_PROXY_SOC_GPO1, /* 62 */
+    DIO_SOC_PROXY_SOC_GPO2, /* 63 */
+    DIO_SOC_PROXY_SOC_GPO3, /* 64 */
+    DIO_SOC_PROXY_SOC_GPO4, /* 65 */
+    DIO_SOC_PROXY_SOC_GPO5, /* 66 */
+    DIO_SOC_PROXY_SOC_GPO6, /* 67 */
+    DIO_SOC_PROXY_SOC_GPO7, /* 68 */
+    DIO_SOC_PROXY_SOC_GPO8, /* 69 */
+    DIO_SOC_PROXY_SOC_GPO9, /* 70 */
+    DIO_SOC_PROXY_SOC_GPO10, /* 71 */
+    DIO_SOC_PROXY_SOC_GPO11, /* 72 */
+    DIO_COUNT, /* 73 */
+};
+
+enum OtDjPinmuxMioIn {
+    MIO_IN_SOC_PROXY_SOC_GPI12, /* 0 */
+    MIO_IN_SOC_PROXY_SOC_GPI13, /* 1 */
+    MIO_IN_SOC_PROXY_SOC_GPI14, /* 2 */
+    MIO_IN_SOC_PROXY_SOC_GPI15, /* 3 */
+    MIO_IN_COUNT, /* 4 */
+};
+
+enum OtDjPinmuxMioOut {
+    MIO_OUT_SOC_PROXY_SOC_GPO12, /* 0 */
+    MIO_OUT_SOC_PROXY_SOC_GPO13, /* 1 */
+    MIO_OUT_SOC_PROXY_SOC_GPO14, /* 2 */
+    MIO_OUT_SOC_PROXY_SOC_GPO15, /* 3 */
+    MIO_OUT_OTP_MACRO_TEST0, /* 4 */
+    MIO_OUT_COUNT, /* 5 */
+};
+
+enum OtDjBoardDevice {
+    OT_DJ_BOARD_DEV_SOC,
+    OT_DJ_BOARD_DEV_FLASH,
+    OT_DJ_BOARD_DEV_DEV_PROXY,
+    OT_DJ_BOARD_DEV_COUNT,
+};
+
+#define OT_DJ_PRIVATE_REGION_OFFSET 0x00000000u
+#define OT_DJ_PRIVATE_REGION_SIZE   (1u << 30u)
+
+#define OT_DJ_IBEX_WRAPPER_NUM_REGIONS 32u
+
+/* CTN address space */
+#define OT_DJ_CTN_REGION_OFFSET 0x40000000u
+#define OT_DJ_CTN_REGION_SIZE   (1u << 30u)
+
+/* CTN RAM (1MB) */
+#define OT_DJ_CTN_RAM_ADDR 0x01000000u
+#define OT_DJ_CTN_RAM_SIZE (2u << 20u)
+
+/* DEBUG address space */
+#define OT_DJ_DEBUG_RV_DM_ADDR    0x0u
+#define OT_DJ_DEBUG_MBX_JTAG_ADDR 0x2200u
+#define OT_DJ_DEBUG_LC_CTRL_ADDR  0x3000u
+#define OT_DJ_DEBUG_LC_CTRL_SIZE  0x400u
+#define OT_DJ_DBG_XBAR_SIZE       0x4000u
+
+static const uint8_t ot_dj_pmp_cfgs[] = {
+    /* clang-format off */
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(1, IBEX_PMP_MODE_NAPOT, 1, 0, 1), /* rgn 2  [ROM: LRX] */
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(1, IBEX_PMP_MODE_TOR, 0, 1, 1), /* rgn 11 [MMIO: LRW] */
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(1, IBEX_PMP_MODE_NAPOT, 1, 1, 1), /* rgn 13 [DV_ROM: LRWX] */
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0)
+    /* clang-format on */
+};
+
+static const uint32_t ot_dj_pmp_addrs[] = {
+    /* clang-format off */
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x000083fc), /* rgn 2 [ROM: base=0x0000_8000 sz (2KiB)] */
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x21100000), /* rgn 10 [MMIO: lo=0x2110_0000] */
+    IBEX_PMP_ADDR(0x30601000), /* rgn 11 [MMIO: hi=0x3060_1000] */
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x000407fc), /* rgn 13 [DV_ROM: base=0x0004_0000 sz (4KiB)] */
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000)
+    /* clang-format on */
+};
+
+#define OT_DJ_MSECCFG IBEX_MSECCFG(1, 1, 0)
+
+#define OT_DJ_SOC_RST_REQ TYPE_RISCV_OT_DJ_SOC "-reset"
+
+#define OT_DJ_SOC_GPIO(_irq_, _target_, _num_) \
+    IBEX_GPIO(_irq_, OT_DJ_SOC_DEV_##_target_, _num_)
+
+#define OT_DJ_SOC_GPIO_SYSBUS_IRQ(_irq_, _target_, _num_) \
+    IBEX_GPIO_SYSBUS_IRQ(_irq_, OT_DJ_SOC_DEV_##_target_, _num_)
+
+#define OT_DJ_SOC_GPIO_ALERT(_snum_, _tnum_) \
+    OT_DJ_SOC_SIGNAL(OT_DEVICE_ALERT, _snum_, ALERT_HANDLER, OT_DEVICE_ALERT, \
+                     _tnum_)
+
+#define OT_DJ_SOC_GPIO_ESCALATE(_snum_, _tgt_, _tnum_) \
+    OT_DJ_SOC_SIGNAL(OT_ALERT_ESCALATE, _snum_, _tgt_, OT_ALERT_ESCALATE, \
+                     _tnum_)
+
+#define OT_DJ_SOC_DEVLINK(_pname_, _target_) \
+    IBEX_DEVLINK(_pname_, OT_DJ_SOC_DEV_##_target_)
+
+/* Device named signal to device named signal */
+#define OT_DJ_SOC_SIGNAL(_sname_, _snum_, _tgt_, _tname_, _tnum_) \
+    { \
+        .out = { \
+            .name = (_sname_), \
+            .num = (_snum_), \
+        }, \
+        .in = { \
+            .name = (_tname_), \
+            .index = (OT_DJ_SOC_DEV_ ## _tgt_), \
+            .num = (_tnum_), \
+        } \
+    }
+
+/* Device named signal to splitter input */
+#define OT_DJ_SOC_D2S(_sname_, _snum_, _tgt_) \
+    { \
+        .out = { \
+            .name = (_sname_), \
+            .num = (_snum_), \
+        }, \
+        .in = { \
+            .index = (OT_DJ_SOC_SPLITTER_ ## _tgt_), \
+        } \
+    }
+
+/* Splitter output to device named signal */
+#define OT_DJ_SOC_S2D(_snum_, _tgt_, _tname_, _tnum_) \
+    { \
+        .out = { \
+            .num = (_snum_), \
+        }, \
+        .in = { \
+            .name = (_tname_), \
+            .index = (OT_DJ_SOC_DEV_ ## _tgt_), \
+            .num = (_tnum_), \
+        } \
+    }
+
+/* Request link */
+#define OT_DJ_SOC_REQ(_req_, _tgt_) \
+    OT_DJ_SOC_SIGNAL(_req_##_REQ, 0, _tgt_, _req_##_REQ, 0)
+
+/* Response link */
+#define OT_DJ_SOC_RSP(_rsp_, _tgt_) \
+    OT_DJ_SOC_SIGNAL(_rsp_##_RSP, 0, _tgt_, _rsp_##_RSP, 0)
+
+#define OT_DJ_SOC_DEV_MBX(_ix_, _addr_, _asname_, _irq_, _alert_) \
+    .type = TYPE_OT_MBX, .instance = IBEX_MAKE_INSTANCE_NUM(_ix_), \
+    .memmap = MEMMAPENTRIES({ .base = (_addr_) }), \
+    .gpio = IBEXGPIOCONNDEFS(OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, (_irq_)), \
+                             OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, (_irq_) + 1u), \
+                             OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, (_irq_) + 2u), \
+                             OT_DJ_SOC_GPIO_ALERT(0, (_alert_)), \
+                             OT_DJ_SOC_GPIO_ALERT(1, (_alert_) + 1)), \
+    .prop = IBEXDEVICEPROPDEFS(IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, \
+                                                    stringify(_ix_)), \
+                               IBEX_DEV_STRING_PROP("ram_as_name", _asname_))
+
+#define OT_DJ_SOC_DEV_MBX_DUAL(_ix_, _addr_, _asname_, _irq_, _alert_, \
+                               _xaddr_) \
+    .type = TYPE_OT_MBX, .instance = IBEX_MAKE_INSTANCE_NUM(_ix_), \
+    .memmap = MEMMAPENTRIES({ .base = (_addr_) }, { .base = (_xaddr_) }), \
+    .gpio = IBEXGPIOCONNDEFS(OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, (_irq_)), \
+                             OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, (_irq_) + 1u), \
+                             OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, (_irq_) + 2u), \
+                             OT_DJ_SOC_GPIO_ALERT(0, (_alert_)), \
+                             OT_DJ_SOC_GPIO_ALERT(1, (_alert_) + 1)), \
+    .prop = IBEXDEVICEPROPDEFS(IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, \
+                                                    stringify(_ix_)), \
+                               IBEX_DEV_STRING_PROP("ram_as_name", _asname_))
+
+#define OT_DJ_PINMUX_LINK(_type_, _name_, _tgt_, _num_) \
+    OT_DJ_SOC_SIGNAL(OT_PINMUX_##_type_, _type_##_##_name_, _tgt_, \
+                     OT_PINMUX_PAD, (_num_))
+
+#define OT_DJ_SOC_CLOCK_CONN(_src_, _src_type_, _src_name_, _in_name_, \
+                             _in_num_) \
+    IBEX_CLOCK_CONN((OT_DJ_SOC_DEV_##_src_), _src_type_, _src_name_, \
+                    _in_name_, _in_num_)
+
+#define OT_DJ_SOC_CLOCK(_src_, _src_type_, _src_name_) \
+    OT_DJ_SOC_CLOCK_CONN(_src_, _src_type_, _src_name_, "clock", 0)
+
+#define OT_DJ_XPORT_MEMORY(_addr_) \
+    IBEX_MEMMAP_MAKE_REG((_addr_), OT_DJ_CTN_MEMORY_REGION)
+
+#define DEBUG_MEMORY(_addr_) \
+    IBEX_MEMMAP_MAKE_REG((_addr_), OT_DJ_DEBUG_MEMORY_REGION)
+
+#define OT_DJ_DEBUG_TL_TO_DMI(_val_) ((_val_) / sizeof(uint32_t))
+
+#define OT_DJ_DEBUG_LC_CTRL_DMI_ADDR \
+    OT_DJ_DEBUG_TL_TO_DMI(OT_DJ_DEBUG_LC_CTRL_ADDR)
+#define OT_DJ_DEBUG_LC_CTRL_DMI_SIZE \
+    OT_DJ_DEBUG_TL_TO_DMI(OT_DJ_DEBUG_LC_CTRL_SIZE)
+#define OT_DJ_DEBUG_MBX_JTAG_DMI_ADDR \
+    OT_DJ_DEBUG_TL_TO_DMI(OT_DJ_DEBUG_MBX_JTAG_ADDR)
+#define OT_DJ_DEBUG_MBX_JTAG_DMI_SIZE (OT_MBX_SYS_APERTURE / sizeof(uint32_t))
+
+#define OT_DJ_SOC_DM_CONNECTION(_dst_dev_, _num_) \
+    { \
+        .out = { \
+            .name = PULP_RV_DM_ACK_OUT_LINES, \
+            .num = (_num_), \
+        }, \
+        .in = { \
+            .name = RISCV_DM_ACK_LINES, \
+            .index = (_dst_dev_), \
+            .num = (_num_), \
+        } \
+    }
+
+/*
+ * Darjeeling RV DM
+ * see https://github.com/lowRISC/part-number-registry/blob/main/jtag_partno.md
+ */
+#define DARJEELING_TAP_IDCODE IBEX_JTAG_IDCODE(1, 1, 0)
+
+#define PULP_DM_BASE 0x00040000u
+
+/*
+ * MMIO/interrupt mapping as per:
+ * lowRISC/opentitan: hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h
+ * and
+ * lowRISC/opentitan: hw/top_darjeeling/sw/autogen/top_darjeeling.h
+ */
+static const IbexDeviceDef ot_dj_soc_devices[] = {
+    /* clang-format off */
+    [OT_DJ_SOC_DEV_HART] = {
+        .type = TYPE_RISCV_CPU_LOWRISC_OPENTITAN,
+        .cfg = &ot_dj_soc_hart_configure,
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("resetvec", 0x8080u),
+            IBEX_DEV_UINT_PROP("mtvec", 0x8001u),
+            IBEX_DEV_UINT_PROP("dmhaltvec", PULP_DM_BASE +
+                PULP_RV_DM_ROM_BASE + PULP_RV_DM_HALT_OFFSET),
+            IBEX_DEV_UINT_PROP("dmexcpvec", PULP_DM_BASE +
+                PULP_RV_DM_ROM_BASE + PULP_RV_DM_EXCEPTION_OFFSET),
+            IBEX_DEV_BOOL_PROP("start-powered-off", true)
+        ),
+    },
+    [OT_DJ_SOC_DEV_TAP_CTRL] = {
+        .type = TYPE_TAP_CTRL_RBB,
+        .cfg = &ot_dj_soc_tap_ctrl_configure,
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("ir_length", IBEX_TAP_IR_LENGTH),
+            IBEX_DEV_UINT_PROP("idcode", DARJEELING_TAP_IDCODE)
+        ),
+    },
+    [OT_DJ_SOC_DEV_DTM] = {
+        .type = TYPE_RISCV_DTM,
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("tap-ctrl", TAP_CTRL)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("abits", 12u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_DM] = {
+        .type = TYPE_RISCV_DM,
+        .cfg = &ot_dj_soc_dm_configure,
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("dtm", DTM)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("dmi_addr", OT_DJ_DEBUG_RV_DM_ADDR),
+            IBEX_DEV_UINT_PROP("dmi_next", 0u), /* last in chain */
+            IBEX_DEV_UINT_PROP("nscratch", PULP_RV_DM_NSCRATCH_COUNT),
+            IBEX_DEV_UINT_PROP("progbuf_count",
+                PULP_RV_DM_PROGRAM_BUFFER_COUNT),
+            IBEX_DEV_UINT_PROP("data_count", PULP_RV_DM_DATA_COUNT),
+            IBEX_DEV_UINT_PROP("abstractcmd_count",
+                PULP_RV_DM_ABSTRACTCMD_COUNT),
+            IBEX_DEV_UINT_PROP("dm_phyaddr", PULP_DM_BASE),
+            IBEX_DEV_UINT_PROP("rom_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_ROM_BASE),
+            IBEX_DEV_UINT_PROP("whereto_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_WHERETO_OFFSET),
+            IBEX_DEV_UINT_PROP("data_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_DATAADDR_OFFSET),
+            IBEX_DEV_UINT_PROP("progbuf_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_PROGRAM_BUFFER_OFFSET),
+            IBEX_DEV_UINT_PROP("resume_offset", PULP_RV_DM_RESUME_OFFSET),
+            IBEX_DEV_BOOL_PROP("sysbus_access", true),
+            IBEX_DEV_BOOL_PROP("abstractauto", true)
+        ),
+    },
+    [OT_DJ_SOC_DEV_DM_MBX] = {
+        .type = TYPE_OT_DM_TL,
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("dtm", DTM),
+            OT_DJ_SOC_DEVLINK("tl_dev", MBX_JTAG)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("dmi_addr", OT_DJ_DEBUG_MBX_JTAG_DMI_ADDR),
+            IBEX_DEV_UINT_PROP("dmi_size", OT_DJ_DEBUG_MBX_JTAG_DMI_SIZE),
+            IBEX_DEV_UINT_PROP("tl_addr", OT_DJ_DEBUG_MBX_JTAG_ADDR),
+            IBEX_DEV_STRING_PROP("tl_as_name", "ot-dbg")
+        )
+    },
+    [OT_DJ_SOC_DEV_DM_LC_CTRL] = {
+        .type = TYPE_OT_DM_TL,
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("dtm", DTM),
+            OT_DJ_SOC_DEVLINK("tl_dev", LC_CTRL)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("dmi_addr", OT_DJ_DEBUG_LC_CTRL_DMI_ADDR),
+            IBEX_DEV_UINT_PROP("dmi_size", OT_DJ_DEBUG_LC_CTRL_DMI_SIZE),
+            IBEX_DEV_UINT_PROP("tl_addr", OT_DJ_DEBUG_LC_CTRL_ADDR),
+            IBEX_DEV_STRING_PROP("tl_as_name", "ot-dbg")
+        )
+    },
+    [OT_DJ_SOC_DEV_RACL_CTRL] = {
+        .type = TYPE_OT_UNIMP,
+        .cfg = &ibex_unimp_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x1461f00u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "racl"),
+            IBEX_DEV_UINT_PROP("size", 0x100u),
+            IBEX_DEV_UINT_PROP("irq-count", 1u),
+            IBEX_DEV_UINT_PROP("alert-count", 2u),
+            IBEX_DEV_BOOL_PROP("warn-once", true)
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 162),
+            OT_DJ_SOC_GPIO_ALERT(0, 97),
+            OT_DJ_SOC_GPIO_ALERT(1, 98)
+        ),
+    },
+    [OT_DJ_SOC_DEV_AC_RANGE_CHECK] = {
+        .type = TYPE_OT_UNIMP,
+        .cfg = &ibex_unimp_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x1464000u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "acr"),
+            IBEX_DEV_UINT_PROP("size", 0x400u),
+            IBEX_DEV_UINT_PROP("irq-count", 1u),
+            IBEX_DEV_UINT_PROP("alert-count", 2u),
+            IBEX_DEV_BOOL_PROP("warn-once", true)
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 163),
+            OT_DJ_SOC_GPIO_ALERT(0, 99),
+            OT_DJ_SOC_GPIO_ALERT(1, 100)
+        ),
+    },
+    [OT_DJ_SOC_DEV_AES] = {
+        .type = TYPE_OT_AES,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x21100000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 53),
+            OT_DJ_SOC_GPIO_ALERT(1, 54)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR),
+            OT_DJ_SOC_DEVLINK("edn", EDN0)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "trans.aes"),
+            IBEX_DEV_UINT_PROP("edn-ep", 5u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_HMAC] = {
+        .type = TYPE_OT_HMAC,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x21110000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 109),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 110),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 111),
+            OT_DJ_SOC_GPIO_ALERT(0, 55)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "trans.hmac")
+        ),
+    },
+    [OT_DJ_SOC_DEV_KMAC] = {
+        .type = TYPE_OT_KMAC,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x21120000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 112),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 113),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 114),
+            OT_DJ_SOC_GPIO_ALERT(0, 56),
+            OT_DJ_SOC_GPIO_ALERT(1, 57)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR),
+            OT_DJ_SOC_DEVLINK("edn", EDN0)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "trans.kmac"),
+            IBEX_DEV_UINT_PROP("edn-ep", 3u),
+            IBEX_DEV_UINT_PROP("num-app", 4u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_OTBN] = {
+        .type = TYPE_OT_OTBN,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x21130000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 115),
+            OT_DJ_SOC_GPIO_ALERT(0, 58),
+            OT_DJ_SOC_GPIO_ALERT(1, 59)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR),
+            OT_DJ_SOC_DEVLINK("edn-u", EDN0),
+            OT_DJ_SOC_DEVLINK("edn-r", EDN1)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "trans.otbn"),
+            IBEX_DEV_UINT_PROP("edn-u-ep", 6u),
+            IBEX_DEV_UINT_PROP("edn-r-ep", 0u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_KEYMGR_DPE] = {
+        .type = TYPE_OT_KEYMGR_DPE,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x21140000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 116),
+            OT_DJ_SOC_GPIO_ALERT(0, 60),
+            OT_DJ_SOC_GPIO_ALERT(1, 61)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("aes", AES),
+            OT_DJ_SOC_DEVLINK("edn", EDN0),
+            OT_DJ_SOC_DEVLINK("kmac", KMAC),
+            OT_DJ_SOC_DEVLINK("otbn", OTBN),
+            OT_DJ_SOC_DEVLINK("lc-ctrl", LC_CTRL),
+            OT_DJ_SOC_DEVLINK("otp-ctrl", OTP_CTRL),
+            OT_DJ_SOC_DEVLINK("rom0", ROM_CTRL0),
+            OT_DJ_SOC_DEVLINK("rom1", ROM_CTRL1)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("edn-ep", 0u),
+            IBEX_DEV_UINT_PROP("kmac-app", 0u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_CSRNG] = {
+        .type = TYPE_OT_CSRNG,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x21150000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 117),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 118),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 119),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 120),
+            OT_DJ_SOC_GPIO_ALERT(0, 62),
+            OT_DJ_SOC_GPIO_ALERT(1, 63)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("entropy-src", ENTROPY_SRC),
+            OT_DJ_SOC_DEVLINK("otp-ctrl", OTP_CTRL)
+        ),
+    },
+    [OT_DJ_SOC_DEV_ENTROPY_SRC] = {
+        .type = TYPE_OT_ENTROPY_SRC,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x21160000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 121),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 122),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 123),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 124),
+            OT_DJ_SOC_GPIO_ALERT(0, 64),
+            OT_DJ_SOC_GPIO_ALERT(1, 65)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+         OT_DJ_SOC_DEVLINK("noise-src", AST)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("version", 3)
+        ),
+    },
+    [OT_DJ_SOC_DEV_EDN0] = {
+        .type = TYPE_OT_EDN,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x21170000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 125),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 126),
+            OT_DJ_SOC_GPIO_ALERT(0, 66),
+            OT_DJ_SOC_GPIO_ALERT(1, 67)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("csrng", CSRNG)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("csrng-app", 0)
+        ),
+    },
+    [OT_DJ_SOC_DEV_EDN1] = {
+        .type = TYPE_OT_EDN,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x21180000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 127),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 128),
+            OT_DJ_SOC_GPIO_ALERT(0, 68),
+            OT_DJ_SOC_GPIO_ALERT(1, 69)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("csrng", CSRNG)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("csrng-app", 1u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_SRAM_CTRL_MAIN] = {
+        .type = TYPE_OT_SRAM_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x211c0000u },
+            { .base = 0x10000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 70)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("otp-ctrl", OTP_CTRL),
+            OT_DJ_SOC_DEVLINK("vmapper", VMAPPER)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("size", 0x10000u),
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "ram"),
+            IBEX_DEV_BOOL_PROP("ifetch", true)
+        ),
+    },
+    [OT_DJ_SOC_DEV_SRAM_CTRL_MBOX] = {
+        .type = TYPE_OT_SRAM_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x211d0000u },
+            { .base = 0x11000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 71)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("otp-ctrl", OTP_CTRL),
+            OT_DJ_SOC_DEVLINK("vmapper", VMAPPER)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("size", 0x1000u),
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "mbx"),
+            IBEX_DEV_BOOL_PROP("ifetch", false)
+        ),
+    },
+    [OT_DJ_SOC_DEV_ROM_CTRL0] = {
+        .type = TYPE_OT_ROM_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x211e0000u },
+            { .base = 0x00008000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 72),
+            OT_DJ_SOC_SIGNAL(OT_ROM_CTRL_GOOD, 0, PWRMGR,
+                             OT_PWRMGR_ROM_GOOD, 0),
+            OT_DJ_SOC_SIGNAL(OT_ROM_CTRL_DONE, 0, PWRMGR,
+                             OT_PWRMGR_ROM_DONE, 0)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("kmac", KMAC)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "rom0"),
+            IBEX_DEV_UINT_PROP("size", 0x8000u),
+            IBEX_DEV_UINT_PROP("kmac-app", 2u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_ROM_CTRL1] = {
+        .type = TYPE_OT_ROM_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x211e1000u },
+            { .base = 0x00020000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 73),
+            OT_DJ_SOC_SIGNAL(OT_ROM_CTRL_GOOD, 0, PWRMGR,
+                             OT_PWRMGR_ROM_GOOD, 1),
+            OT_DJ_SOC_SIGNAL(OT_ROM_CTRL_DONE, 0, PWRMGR,
+                             OT_PWRMGR_ROM_DONE, 1)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("kmac", KMAC)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "rom1"),
+            IBEX_DEV_UINT_PROP("size", 0x10000u),
+            IBEX_DEV_UINT_PROP("kmac-app", 3u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_IBEX_WRAPPER] = {
+        .type = TYPE_OT_IBEX_WRAPPER,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x211f0000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 101),
+            OT_DJ_SOC_GPIO_ALERT(1, 102),
+            OT_DJ_SOC_GPIO_ALERT(2, 103),
+            OT_DJ_SOC_GPIO_ALERT(3, 104)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("edn", EDN0),
+            OT_DJ_SOC_DEVLINK("vmapper", VMAPPER)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("edn-ep", 7u),
+            IBEX_DEV_UINT_PROP("num-regions", OT_DJ_IBEX_WRAPPER_NUM_REGIONS)
+        ),
+    },
+    [OT_DJ_SOC_DEV_RV_DM] = {
+        .type = TYPE_PULP_RV_DM,
+        .memmap = MEMMAPENTRIES(
+            { .base = PULP_DM_BASE },
+            { .base = 0x21200000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_DM_CONNECTION(OT_DJ_SOC_DEV_DM, 0),
+            OT_DJ_SOC_DM_CONNECTION(OT_DJ_SOC_DEV_DM, 1),
+            OT_DJ_SOC_DM_CONNECTION(OT_DJ_SOC_DEV_DM, 2),
+            OT_DJ_SOC_DM_CONNECTION(OT_DJ_SOC_DEV_DM, 3),
+            OT_DJ_SOC_GPIO_ALERT(0, 51)
+        ),
+    },
+    [OT_DJ_SOC_DEV_MBX0] = {
+        OT_DJ_SOC_DEV_MBX(0, 0x22000000u, "ot-mbx.sram", 132, 75),
+    },
+    [OT_DJ_SOC_DEV_MBX1] = {
+        OT_DJ_SOC_DEV_MBX(1, 0x22000100u, "ot-mbx.sram", 135, 77),
+    },
+    [OT_DJ_SOC_DEV_MBX2] = {
+        OT_DJ_SOC_DEV_MBX(2, 0x22000200u, "ot-mbx.sram", 138, 79),
+    },
+    [OT_DJ_SOC_DEV_MBX3] = {
+        OT_DJ_SOC_DEV_MBX(3, 0x22000300u, "ot-mbx.sram", 141, 81),
+    },
+    [OT_DJ_SOC_DEV_MBX4] = {
+        OT_DJ_SOC_DEV_MBX(4, 0x22000400u, "ot-mbx.sram", 144, 83),
+    },
+    [OT_DJ_SOC_DEV_MBX5] = {
+        OT_DJ_SOC_DEV_MBX(5, 0x22000500u, "ot-mbx.sram", 147, 85),
+    },
+    [OT_DJ_SOC_DEV_MBX6] = {
+        OT_DJ_SOC_DEV_MBX(6, 0x22000600u, "ot-mbx.sram", 150, 87),
+    },
+    [OT_DJ_SOC_DEV_MBX_JTAG] = {
+        OT_DJ_SOC_DEV_MBX_DUAL(7, 0x22000800u, "ot-mbx.sram", 153, 89,
+                               DEBUG_MEMORY(OT_DJ_DEBUG_MBX_JTAG_ADDR)),
+    },
+    [OT_DJ_SOC_DEV_DMA] = {
+        .type = TYPE_OT_DMA,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x22010000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 129),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 130),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 131),
+            OT_DJ_SOC_GPIO_ALERT(0, 74)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("ot_as_name", "ot-dma"),
+            IBEX_DEV_STRING_PROP("ctn_as_name", "ctn-dma")
+        )
+    },
+    [OT_DJ_SOC_DEV_SOC_PROXY] = {
+        .type = TYPE_OT_SOC_PROXY,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x22030000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 77),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 78),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 79),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 80),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 81),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 82),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 83),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 84),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 85),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(9, PLIC, 86),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(10, PLIC, 87),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(11, PLIC, 88),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(12, PLIC, 89),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(13, PLIC, 90),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(14, PLIC, 91),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(15, PLIC, 92),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(16, PLIC, 93),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(17, PLIC, 94),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(18, PLIC, 95),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(19, PLIC, 96),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(20, PLIC, 97),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(21, PLIC, 98),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(22, PLIC, 99),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(23, PLIC, 100),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(24, PLIC, 101),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(25, PLIC, 102),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(26, PLIC, 103),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(27, PLIC, 104),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(28, PLIC, 105),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(29, PLIC, 106),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(30, PLIC, 107),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(31, PLIC, 108),
+            OT_DJ_SOC_GPIO_ALERT(0, 21),
+            OT_DJ_SOC_GPIO_ALERT(1, 22),
+            OT_DJ_SOC_GPIO_ALERT(2, 23),
+            OT_DJ_SOC_GPIO_ALERT(3, 24),
+            OT_DJ_SOC_GPIO_ALERT(4, 25),
+            OT_DJ_SOC_GPIO_ALERT(5, 26),
+            OT_DJ_SOC_GPIO_ALERT(6, 27),
+            OT_DJ_SOC_GPIO_ALERT(7, 28),
+            OT_DJ_SOC_GPIO_ALERT(8, 29),
+            OT_DJ_SOC_GPIO_ALERT(9, 30),
+            OT_DJ_SOC_GPIO_ALERT(10, 31),
+            OT_DJ_SOC_GPIO_ALERT(11, 32),
+            OT_DJ_SOC_GPIO_ALERT(12, 33),
+            OT_DJ_SOC_GPIO_ALERT(13, 34),
+            OT_DJ_SOC_GPIO_ALERT(14, 35),
+            OT_DJ_SOC_GPIO_ALERT(15, 36),
+            OT_DJ_SOC_GPIO_ALERT(16, 37),
+            OT_DJ_SOC_GPIO_ALERT(17, 38),
+            OT_DJ_SOC_GPIO_ALERT(18, 39),
+            OT_DJ_SOC_GPIO_ALERT(19, 40),
+            OT_DJ_SOC_GPIO_ALERT(20, 41),
+            OT_DJ_SOC_GPIO_ALERT(21, 42),
+            OT_DJ_SOC_GPIO_ALERT(22, 43),
+            OT_DJ_SOC_GPIO_ALERT(23, 44),
+            OT_DJ_SOC_GPIO_ALERT(24, 45),
+            OT_DJ_SOC_GPIO_ALERT(25, 46),
+            OT_DJ_SOC_GPIO_ALERT(26, 47),
+            OT_DJ_SOC_GPIO_ALERT(27, 48),
+            OT_DJ_SOC_GPIO_ALERT(28, 49)
+        ),
+    },
+    [OT_DJ_SOC_DEV_MBX_PCIE0] = {
+        OT_DJ_SOC_DEV_MBX(8, 0x22040000u, "ot-mbx.sram", 156, 91),
+    },
+    [OT_DJ_SOC_DEV_MBX_PCIE1] = {
+        OT_DJ_SOC_DEV_MBX(9, 0x22040100u, "ot-mbx.sram", 159, 93),
+    },
+    [OT_DJ_SOC_DEV_PLIC] = {
+        .type = TYPE_SIFIVE_PLIC,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x28000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO(1, HART, IRQ_M_EXT)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("hart-config", "M"),
+            IBEX_DEV_UINT_PROP("hartid-base", 0u),
+            /* note: should always be max_irq + 1 */
+            IBEX_DEV_UINT_PROP("num-sources", 164u),
+            IBEX_DEV_UINT_PROP("num-priorities", 3u),
+            IBEX_DEV_UINT_PROP("priority-base", 0x0u),
+            IBEX_DEV_UINT_PROP("pending-base", 0x1000u),
+            IBEX_DEV_UINT_PROP("enable-base", 0x2000u),
+            IBEX_DEV_UINT_PROP("enable-stride", 32u),
+            IBEX_DEV_UINT_PROP("context-base", 0x200000u),
+            IBEX_DEV_UINT_PROP("context-stride", 8u),
+            IBEX_DEV_UINT_PROP("aperture-size", 0x4000000u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_PLIC_EXT] = {
+        .type = TYPE_OT_PLIC_EXT,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x2c000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO(0, HART, IRQ_M_SOFT),
+            OT_DJ_SOC_GPIO_ALERT(0, 52)
+        ),
+    },
+    [OT_DJ_SOC_DEV_GPIO] = {
+        .type = TYPE_OT_GPIO_DJ,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 10),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 11),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 12),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 13),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 14),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 15),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 16),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 17),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 18),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(9, PLIC, 19),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(10, PLIC, 20),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(11, PLIC, 21),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(12, PLIC, 22),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(13, PLIC, 23),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(14, PLIC, 24),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(15, PLIC, 25),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(16, PLIC, 26),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(17, PLIC, 27),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(18, PLIC, 28),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(19, PLIC, 29),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(20, PLIC, 30),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(21, PLIC, 31),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(22, PLIC, 32),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(23, PLIC, 33),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(24, PLIC, 34),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(25, PLIC, 35),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(26, PLIC, 36),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(27, PLIC, 37),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(28, PLIC, 38),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(29, PLIC, 39),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(30, PLIC, 40),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(31, PLIC, 41),
+            OT_DJ_SOC_GPIO_ALERT(0, 1)
+        ),
+    },
+    [OT_DJ_SOC_DEV_UART0] = {
+        .type = TYPE_OT_UART,
+        .cfg = &ot_dj_soc_uart_configure,
+        .instance = IBEX_MAKE_INSTANCE_NUM(0),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30010000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 1),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 2),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 3),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 4),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 5),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 6),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 7),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 8),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 9),
+            OT_DJ_SOC_GPIO_ALERT(0, 0)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4")
+        ),
+    },
+    [OT_DJ_SOC_DEV_I2C0] = {
+        .type = TYPE_OT_I2C,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30080000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 50),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 51),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 52),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 53),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 54),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 55),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 56),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 57),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 58),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(9, PLIC, 59),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(10, PLIC, 60),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(11, PLIC, 61),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(12, PLIC, 62),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(13, PLIC, 63),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(14, PLIC, 64),
+            OT_DJ_SOC_GPIO_ALERT(0, 3)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4")
+        ),
+    },
+    [OT_DJ_SOC_DEV_TIMER] = {
+        .type = TYPE_OT_TIMER,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30100000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO(0, HART, IRQ_M_TIMER),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 65),
+            OT_DJ_SOC_GPIO_ALERT(0, 4)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "timers.io_div4")
+        ),
+    },
+    [OT_DJ_SOC_DEV_OTP_CTRL] = {
+        .type = TYPE_OT_OTP_DJ,
+        .cfg = &ot_dj_soc_otp_ctrl_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30130000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 66),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 67),
+            OT_DJ_SOC_GPIO_ALERT(0, 5),
+            OT_DJ_SOC_GPIO_ALERT(1, 6),
+            OT_DJ_SOC_GPIO_ALERT(2, 7),
+            OT_DJ_SOC_GPIO_ALERT(3, 8),
+            OT_DJ_SOC_GPIO_ALERT(4, 9),
+            OT_DJ_SOC_RSP(OT_PWRMGR_OTP, PWRMGR)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("edn", EDN0),
+            OT_DJ_SOC_DEVLINK("backend", OTP_BACKEND)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("edn-ep", 1u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_OTP_BACKEND] = {
+        .type = TYPE_OT_OTP_OT_BE,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30140000u }
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("parent", OTP_CTRL)
+        ),
+    },
+    [OT_DJ_SOC_DEV_LC_CTRL] = {
+        .type = TYPE_OT_LC_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30150000u },
+            { .base = DEBUG_MEMORY(OT_DJ_DEBUG_LC_CTRL_ADDR) }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 10),
+            OT_DJ_SOC_GPIO_ALERT(1, 11),
+            OT_DJ_SOC_GPIO_ALERT(2, 12),
+            OT_DJ_SOC_D2S(OT_LC_BROADCAST, OT_LC_HW_DEBUG_EN, LC_HW_DEBUG),
+            OT_DJ_SOC_D2S(OT_LC_BROADCAST, OT_LC_ESCALATE_EN, LC_ESCALATE),
+            OT_DJ_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_CPU_EN, IBEX_WRAPPER,
+                             OT_IBEX_WRAPPER_CPU_EN, OT_IBEX_LC_CTRL_CPU_EN),
+            OT_DJ_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_CHECK_BYP_EN, OTP_CTRL,
+                             OT_LC_BROADCAST, OT_OTP_LC_CHECK_BYP_EN),
+            OT_DJ_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_KEYMGR_EN, KEYMGR_DPE,
+                             OT_KEYMGR_DPE_ENABLE, 0),
+            OT_DJ_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_CREATOR_SEED_SW_RW_EN,
+                             OTP_CTRL, OT_LC_BROADCAST,
+                             OT_OTP_LC_CREATOR_SEED_SW_RW_EN),
+            OT_DJ_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_OWNER_SEED_SW_RW_EN,
+                             OTP_CTRL, OT_LC_BROADCAST,
+                             OT_OTP_LC_OWNER_SEED_SW_RW_EN),
+            OT_DJ_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_SEED_HW_RD_EN,
+                             OTP_CTRL, OT_LC_BROADCAST,
+                             OT_OTP_LC_SEED_HW_RD_EN),
+            OT_DJ_SOC_RSP(OT_PWRMGR_LC, PWRMGR)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("otp-ctrl", OTP_CTRL),
+            OT_DJ_SOC_DEVLINK("kmac", KMAC)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("silicon_creator_id", 0x4002u),
+            IBEX_DEV_UINT_PROP("product_id", 0x4000u),
+            IBEX_DEV_UINT_PROP("revision_id", 0x1u),
+            IBEX_DEV_UINT_PROP("kmac-app", 1u),
+            IBEX_DEV_BOOL_PROP("volatile_raw_unlock", true),
+            IBEX_DEV_BOOL_PROP("decode_soc_dbg", true)
+        )
+    },
+    [OT_DJ_SOC_DEV_ALERT_HANDLER] = {
+        .type = TYPE_OT_ALERT,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30160000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 68),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 69),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 70),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 71),
+            OT_DJ_SOC_GPIO_ESCALATE(0, IBEX_WRAPPER, 0),
+            OT_DJ_SOC_GPIO_ESCALATE(1, LC_CTRL, 0),
+            OT_DJ_SOC_GPIO_ESCALATE(2, LC_CTRL, 1),
+            OT_DJ_SOC_GPIO_ESCALATE(3, PWRMGR, 0)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR),
+            OT_DJ_SOC_DEVLINK("edn", EDN0)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("n_alerts", 105u),
+            IBEX_DEV_UINT_PROP("n_classes", 4u),
+            IBEX_DEV_UINT_PROP("n_lpg", 18u),
+            IBEX_DEV_UINT_PROP("edn-ep", 4u),
+            IBEX_DEV_STRING_PROP("clock-name", "secure.io_div4"),
+            IBEX_DEV_STRING_PROP("clock-name-edn", "secure.main")
+        ),
+    },
+    [OT_DJ_SOC_DEV_SOC_DBG_CTRL] = {
+        .type = TYPE_OT_SOC_DBG_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30170000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 95),
+            OT_DJ_SOC_GPIO_ALERT(1, 96)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("lc-ctrl", LC_CTRL)
+        ),
+    },
+    [OT_DJ_SOC_DEV_SPI_HOST0] = {
+        .type = TYPE_OT_SPI_HOST,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30300000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 72),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 73),
+            OT_DJ_SOC_GPIO_ALERT(0, 13)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "spi0"),
+            IBEX_DEV_UINT_PROP("bus-num", 0),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4"),
+            IBEX_DEV_UINT_PROP("version", 3u)
+        ),
+    },
+    [OT_DJ_SOC_DEV_SPI_DEVICE] = {
+        .type = TYPE_OT_SPI_DEVICE,
+        .cfg = &ot_dj_soc_spi_device_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30310000u }
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("spi-host", SPI_HOST0)
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 42),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 43),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 44),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 45),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 46),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 47),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 48),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 49),
+            OT_DJ_SOC_GPIO_ALERT(0, 2),
+            OT_DJ_SOC_SIGNAL(OT_SPI_DEVICE_PASSTHROUGH_EN, 0, SPI_HOST0,
+                OT_SPI_HOST_PASSTHROUGH_EN, 0),
+            OT_DJ_SOC_SIGNAL(OT_SPI_DEVICE_PASSTHROUGH_CS, 0, SPI_HOST0,
+                OT_SPI_HOST_PASSTHROUGH_CS, 0)
+        ),
+    },
+    [OT_DJ_SOC_DEV_PWRMGR] = {
+        .type = TYPE_OT_PWRMGR,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30400000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 74),
+            OT_DJ_SOC_GPIO_ALERT(0, 14),
+            OT_DJ_SOC_REQ(OT_PWRMGR_OTP, OTP_CTRL),
+            OT_DJ_SOC_REQ(OT_PWRMGR_LC, LC_CTRL),
+            OT_DJ_SOC_SIGNAL(OT_PWRMGR_CPU_EN, 0, IBEX_WRAPPER,
+                             OT_IBEX_WRAPPER_CPU_EN, OT_IBEX_PWRMGR_CPU_EN),
+            OT_DJ_SOC_SIGNAL(OT_PWRMGR_STRAP, 0, GPIO,
+                             OT_GPIO_STRAP_EN, 0),
+            OT_DJ_SOC_SIGNAL(OT_PWRMGR_RST_REQ, 0, RSTMGR,
+                             OT_RSTMGR_RST_REQ, 0)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-ctrl", AST)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clocks", "main,io"),
+            IBEX_DEV_UINT_PROP("num-rom", 2u),
+            IBEX_DEV_UINT_PROP("version", OT_PWRMGR_VERSION_DJ)
+        ),
+    },
+    [OT_DJ_SOC_DEV_RSTMGR] = {
+        .type = TYPE_OT_RSTMGR,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30410000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 15),
+            OT_DJ_SOC_GPIO_ALERT(1, 16),
+            OT_DJ_SOC_SIGNAL(OT_RSTMGR_SW_RST, 0, PWRMGR,
+                             OT_PWRMGR_SW_RST, 0)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("version", OT_RSTMGR_VERSION_DJ)
+        ),
+    },
+    [OT_DJ_SOC_DEV_CLKMGR] = {
+        .type = TYPE_OT_CLKMGR,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30420000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 17),
+            OT_DJ_SOC_GPIO_ALERT(1, 18)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", AST)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("version", OT_CLKMGR_VERSION_DJ)
+        ),
+    },
+    [OT_DJ_SOC_DEV_PINMUX] = {
+        .type = TYPE_OT_PINMUX_DJ,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30460000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO0, GPIO, 0),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO1, GPIO, 1),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO2, GPIO, 2),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO3, GPIO, 3),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO4, GPIO, 4),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO5, GPIO, 5),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO6, GPIO, 6),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO7, GPIO, 7),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO8, GPIO, 8),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO9, GPIO, 9),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO10, GPIO, 10),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO11, GPIO, 11),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO12, GPIO, 12),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO13, GPIO, 13),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO14, GPIO, 14),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO15, GPIO, 15),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO16, GPIO, 16),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO17, GPIO, 17),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO18, GPIO, 18),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO19, GPIO, 19),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO20, GPIO, 20),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO21, GPIO, 21),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO22, GPIO, 22),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO23, GPIO, 23),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO24, GPIO, 24),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO25, GPIO, 25),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO26, GPIO, 26),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO27, GPIO, 27),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO28, GPIO, 28),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO29, GPIO, 29),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO30, GPIO, 30),
+            OT_DJ_PINMUX_LINK(DIO, GPIO_GPIO31, GPIO, 31),
+            OT_DJ_SOC_GPIO_ALERT(0, 19)
+        ),
+    },
+    [OT_DJ_SOC_DEV_AON_TIMER] = {
+        .type = TYPE_OT_AON_TIMER,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30470000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 75),
+            OT_DJ_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 76),
+            OT_DJ_SOC_GPIO_ALERT(0, 20),
+            OT_DJ_SOC_SIGNAL(OT_AON_TIMER_WKUP, 0, PWRMGR,
+                             OT_PWRMGR_WKUP, OT_PWRMGR_WAKEUP_AON_TIMER),
+            OT_DJ_SOC_SIGNAL(OT_AON_TIMER_BITE, 0, PWRMGR,
+                             OT_PWRMGR_RST, OT_DJ_RESET_AON_TIMER)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "timers.io_div4"),
+            IBEX_DEV_STRING_PROP("clock-name-aon", "timers.aon")
+        ),
+    },
+    [OT_DJ_SOC_DEV_AST] = {
+        .type = TYPE_OT_AST_DJ,
+        .cfg = &ot_dj_soc_ast_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30480000u }
+        ),
+    },
+    [OT_DJ_SOC_DEV_SRAM_CTRL_RET] = {
+        .type = TYPE_OT_SRAM_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x30500000u },
+            { .base = 0x30600000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_GPIO_ALERT(0, 50)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_DJ_SOC_DEVLINK("otp-ctrl", OTP_CTRL),
+            OT_DJ_SOC_DEVLINK("vmapper", VMAPPER)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("size", 0x1000u),
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "ret"),
+            IBEX_DEV_BOOL_PROP("ifetch", false)
+        ),
+    },
+    [OT_DJ_SOC_DEV_VMAPPER] = {
+        .type = TYPE_OT_VMAPPER,
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "soc"),
+            IBEX_DEV_UINT_PROP("trans_count", OT_DJ_IBEX_WRAPPER_NUM_REGIONS)
+        ),
+    },
+    /* IRQ splitters */
+    [OT_DJ_SOC_SPLITTER_LC_HW_DEBUG] = {
+        .type = TYPE_SPLIT_IRQ,
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_S2D(0, SRAM_CTRL_MAIN, OT_SRAM_CTRL_HW_DEBUG_EN, 0),
+            OT_DJ_SOC_S2D(1, SRAM_CTRL_MBOX, OT_SRAM_CTRL_HW_DEBUG_EN, 0),
+            OT_DJ_SOC_S2D(2, SRAM_CTRL_RET, OT_SRAM_CTRL_HW_DEBUG_EN, 0)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("num-lines", 3u) /* @todo: to be changed */
+        )
+    },
+    [OT_DJ_SOC_SPLITTER_LC_ESCALATE] = {
+        .type = TYPE_SPLIT_IRQ,
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_DJ_SOC_S2D(0, OTP_CTRL, OT_LC_BROADCAST,
+                                  OT_OTP_LC_ESCALATE_EN)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("num-lines", 1u) /* @todo to be changed */
+        )
+    }
+    /* clang-format on */
+};
+
+/* ------------------------------------------------------------------------ */
+/* Type definitions */
+/* ------------------------------------------------------------------------ */
+
+/* Temporary storage for reset iteration */
+typedef struct {
+    OtDjSoCState *soc;
+    ResettableChildCallback cb; /* the callback to call for each child */
+    void *opaque; /* opaque data for the callback */
+    ResetType type; /* type of reset */
+} OtDjSocChildReset;
+
+struct OtDjSoCClass {
+    DeviceClass parent_class;
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
+struct OtDjSoCState {
+    SysBusDevice parent_obj;
+
+    BusState *ot_bus; /* private OpenTitan bus */
+
+    DeviceState **devices;
+};
+
+struct OtDjBoardState {
+    DeviceState parent_obj;
+
+    DeviceState **devices;
+};
+
+struct OtDjMachineState {
+    MachineState parent_obj;
+
+    ResettableState reset;
+
+    bool no_epmp_cfg;
+    bool ignore_elf_entry;
+    bool verilator;
+};
+
+/* ------------------------------------------------------------------------ */
+/* Device Configuration */
+/* ------------------------------------------------------------------------ */
+
+static void ot_dj_soc_ast_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                    DeviceState *parent)
+{
+    (void)def;
+    (void)parent;
+
+    bool verilator_mode =
+        object_property_get_bool(qdev_get_machine(), "verilator", NULL);
+    const char *clock_cfg;
+    if (!verilator_mode) {
+        /* Defaults for Darjeeling HW */
+        clock_cfg = "main:1000000000,io:1000000000,aon:62500000";
+    } else {
+        /* From verilator model */
+        clock_cfg = "main:500000,io:500000,aon:125000";
+    }
+
+    qdev_prop_set_string(dev, "topclocks", clock_cfg);
+}
+
+static void ot_dj_soc_dm_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                   DeviceState *parent)
+{
+    (void)def;
+    (void)parent;
+
+    QList *hart = qlist_new();
+    qlist_append_int(hart, 0);
+    qdev_prop_set_array(dev, "hart", hart);
+
+    RISCVDMMemAttrs pulp_attrs = {
+        .attrs = {
+            .requester_id = PULP_RV_DM_REQUESTER_ID,
+        },
+    };
+    qdev_prop_set_uint64(dev, "mta_dm", pulp_attrs.value);
+}
+
+static void ot_dj_soc_hart_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                     DeviceState *parent)
+{
+    OtDjMachineState *ms = RISCV_OT_DJ_MACHINE(qdev_get_machine());
+    QList *pmp_cfg, *pmp_addr;
+    (void)def;
+    (void)parent;
+
+    if (ms->no_epmp_cfg) {
+        /* skip default PMP config */
+        return;
+    }
+
+    pmp_cfg = qlist_new();
+    for (unsigned ix = 0; ix < ARRAY_SIZE(ot_dj_pmp_cfgs); ix++) {
+        qlist_append_int(pmp_cfg, ot_dj_pmp_cfgs[ix]);
+    }
+    qdev_prop_set_array(dev, "pmp_cfg", pmp_cfg);
+
+    pmp_addr = qlist_new();
+    for (unsigned ix = 0; ix < ARRAY_SIZE(ot_dj_pmp_addrs); ix++) {
+        qlist_append_int(pmp_addr, ot_dj_pmp_addrs[ix]);
+    }
+    qdev_prop_set_array(dev, "pmp_addr", pmp_addr);
+
+    qdev_prop_set_uint64(dev, "mseccfg", (uint64_t)OT_DJ_MSECCFG);
+}
+
+static void ot_dj_soc_otp_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
+    (void)def;
+    (void)parent;
+    if (dinfo) {
+        qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo),
+                                &error_fatal);
+    }
+}
+
+static void ot_dj_soc_tap_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)parent;
+    (void)def;
+
+    Chardev *chr;
+
+    chr = ibex_get_chardev_by_id("taprbb");
+    if (chr) {
+        qdev_prop_set_chr(dev, "chardev", chr);
+    }
+}
+
+static void ot_dj_soc_spi_device_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)parent;
+    (void)def;
+
+    Chardev *chr;
+
+    chr = ibex_get_chardev_by_id("spidev");
+    if (chr) {
+        qdev_prop_set_chr(dev, "chardev", chr);
+    }
+}
+
+static void ot_dj_soc_uart_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                     DeviceState *parent)
+{
+    (void)def;
+    (void)parent;
+    qdev_prop_set_chr(dev, "chardev", serial_hd(IBEX_GET_INSTANCE_NUM(def)));
+}
+
+/* ------------------------------------------------------------------------ */
+/* SoC */
+/* ------------------------------------------------------------------------ */
+
+static int ot_dj_soc_reset_child(Object *child, void *opaque)
+{
+    OtDjSocChildReset *cr = opaque;
+
+    if (object_dynamic_cast(child, TYPE_SYS_BUS_DEVICE)) {
+        /*
+         * sysbus devices being connected to the OT bus, and the bus performing
+         * its own children traversal to perform reset, skip this kind of
+         * devices to avoid resetting each of them twice
+         */
+        return 0;
+    }
+
+    if (object_dynamic_cast(child, TYPE_RESETTABLE_INTERFACE)) {
+        cr->cb(child, cr->opaque, cr->type);
+    }
+
+    /* resume with next child */
+    return 0;
+}
+
+static void ot_dj_soc_reset_child_foreach(
+    Object *obj, ResettableChildCallback cb, void *opaque, ResetType type)
+{
+    OtDjSoCState *s = RISCV_OT_DJ_SOC(obj);
+
+    OtDjSocChildReset r = {
+        .soc = s,
+        .cb = cb,
+        .opaque = opaque,
+        .type = type,
+    };
+
+    /* execute reset stage for each child */
+    object_child_foreach(obj, &ot_dj_soc_reset_child, &r);
+}
+
+static void ot_dj_soc_hw_reset(void *opaque, int irq, int level)
+{
+    OtDjSoCState *s = opaque;
+
+    g_assert(irq == 0);
+
+    if (level) {
+        resettable_reset(OBJECT(s), RESET_TYPE_COLD);
+    }
+}
+
+static void ot_dj_soc_reset_hold(Object *obj, ResetType type)
+{
+    OtDjSoCClass *c = RISCV_OT_DJ_SOC_GET_CLASS(obj);
+    OtDjSoCState *s = RISCV_OT_DJ_SOC(obj);
+
+    if (c->parent_phases.hold) {
+        c->parent_phases.hold(obj, type);
+    }
+
+    /*
+     * This function is called after all children have been reset_hold,
+     * before any child has been reset_exit.
+     *
+     * Power-On-Reset: leave hart disabled on reset
+     * PowerManager takes care of managing Ibex reset when ready
+     */
+    CPUState *cs = CPU(s->devices[OT_DJ_SOC_DEV_HART]);
+    cs->disabled = true;
+}
+
+static void ot_dj_soc_reset_exit(Object *obj, ResetType type)
+{
+    OtDjSoCClass *c = RISCV_OT_DJ_SOC_GET_CLASS(obj);
+    OtDjSoCState *s = RISCV_OT_DJ_SOC(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    rom_load();
+
+    /* Kick off ROM checks and boot */
+    object_property_set_bool(OBJECT(s->devices[OT_DJ_SOC_DEV_ROM_CTRL0]),
+                             "load", true, &error_fatal);
+    object_property_set_bool(OBJECT(s->devices[OT_DJ_SOC_DEV_ROM_CTRL1]),
+                             "load", true, &error_fatal);
+}
+
+static void ot_dj_soc_realize(DeviceState *dev, Error **errp)
+{
+    OtDjSoCState *s = RISCV_OT_DJ_SOC(dev);
+    (void)errp;
+
+    CPUState *cpu = CPU(s->devices[OT_DJ_SOC_DEV_HART]);
+    cpu->memory = get_system_memory();
+    cpu->cpu_index = 0;
+
+    /* Create the private bus on which all OpenTitan IPs are connected */
+    s->ot_bus = BUS(object_new(TYPE_SYSTEM_BUS));
+    qbus_init(s->ot_bus, sizeof(*s->ot_bus), TYPE_SYSTEM_BUS, DEVICE(s),
+              "ot.bus");
+
+    /* Link, define properties and realize devices, then connect GPIOs */
+    ot_common_configure_devices_with_id(s->devices, s->ot_bus, "soc", false,
+                                        ot_dj_soc_devices,
+                                        ARRAY_SIZE(ot_dj_soc_devices));
+
+    Object *oas;
+
+    oas = object_property_get_link(OBJECT(s)->parent, "ctn.as", errp);
+    g_assert(oas);
+    AddressSpace *ctn_as = ot_address_space_get(OT_ADDRESS_SPACE(oas));
+
+    MemoryRegion *dbg_mr = g_new0(MemoryRegion, 1u);
+    memory_region_init(dbg_mr, OBJECT(dev), "dbg.xbar", OT_DJ_DBG_XBAR_SIZE);
+
+    MemoryRegion *mrs[IBEX_MEMMAP_REGIDX_COUNT] = {
+        [OT_DJ_DEFAULT_MEMORY_REGION] = cpu->memory,
+        [OT_DJ_CTN_MEMORY_REGION] = ctn_as->root,
+        [OT_DJ_DEBUG_MEMORY_REGION] = dbg_mr,
+    };
+    ibex_map_devices_mask(s->devices, mrs, ot_dj_soc_devices,
+                          ARRAY_SIZE(ot_dj_soc_devices),
+                          IBEX_MEMMAP_MAKE_REG_MASK(
+                              OT_DJ_DEFAULT_MEMORY_REGION) |
+                              IBEX_MEMMAP_MAKE_REG_MASK(
+                                  OT_DJ_DEBUG_MEMORY_REGION));
+
+    MemoryRegion *mbx_sram_root_mr = g_new0(MemoryRegion, 1u);
+    memory_region_init(mbx_sram_root_mr, OBJECT(s), "mbx.sram",
+                       OT_DJ_PRIVATE_REGION_SIZE);
+    AddressSpace *mbx_sram_as = g_new0(AddressSpace, 1u);
+    address_space_init(mbx_sram_as, mbx_sram_root_mr, "mbx.sram.as");
+    Object *mbx_sram_oas = object_new(TYPE_OT_ADDRESS_SPACE);
+    object_property_add_child(OBJECT(dev), "ot-mbx.sram", mbx_sram_oas);
+    ot_address_space_set(OT_ADDRESS_SPACE(mbx_sram_oas), mbx_sram_as);
+    SysBusDevice *sram_dev =
+        SYS_BUS_DEVICE(s->devices[OT_DJ_SOC_DEV_SRAM_CTRL_MBOX]);
+    /* first MMIO maps to register, second MMIO maps to SRAM */
+    MemoryRegion *mbx_sram_mr = sysbus_mmio_get_region(sram_dev, 1);
+    MemoryRegion *mbx_sram_alias_mr = g_new0(MemoryRegion, 1u);
+    memory_region_init_alias(mbx_sram_alias_mr, OBJECT(s), "mbx.sram",
+                             mbx_sram_mr, 0u, int128_getlo(mbx_sram_mr->size));
+    memory_region_add_subregion(mbx_sram_root_mr, mbx_sram_mr->addr,
+                                mbx_sram_alias_mr);
+
+    AddressSpace *dbg_as = g_new0(AddressSpace, 1u);
+    address_space_init(dbg_as, dbg_mr, "dbg.as");
+
+    oas = object_new(TYPE_OT_ADDRESS_SPACE);
+    object_property_add_child(OBJECT(dev), "ot-dbg", oas);
+    ot_address_space_set(OT_ADDRESS_SPACE(oas), dbg_as);
+
+
+    oas = object_new(TYPE_OT_ADDRESS_SPACE);
+    object_property_add_child(OBJECT(dev), "ot-dma", oas);
+    ot_address_space_set(OT_ADDRESS_SPACE(oas), cpu->as);
+
+    /*
+     * create a new root region to map the CTN for the DMA, viewed as an
+     * elevated region, which means the address range below the elevated CTN
+     * range is kept empty
+     */
+    MemoryRegion *ctn_dma_mr = g_new0(MemoryRegion, 1u);
+    memory_region_init(ctn_dma_mr, OBJECT(dev), "ctn.dma",
+                       OT_DJ_CTN_REGION_OFFSET + OT_DJ_CTN_REGION_SIZE);
+
+    /* create an AS view for this new root region */
+    AddressSpace *ctn_dma_as = g_new0(AddressSpace, 1u);
+    address_space_init(ctn_dma_as, ctn_dma_mr, "ctn.dma.as");
+
+    /* create and map an alias to the CTN MR into the elevated region */
+    MemoryRegion *ctn_amr = g_new0(MemoryRegion, 1u);
+    memory_region_init_alias(ctn_amr, OBJECT(dev), "ctn.dma.alias",
+                             ctn_as->root, 0u, (uint64_t)OT_DJ_CTN_REGION_SIZE);
+    memory_region_add_subregion(ctn_dma_mr, (hwaddr)OT_DJ_CTN_REGION_OFFSET,
+                                ctn_amr);
+
+    oas = object_new(TYPE_OT_ADDRESS_SPACE);
+    object_property_add_child(OBJECT(dev), "ctn-dma", oas);
+    ot_address_space_set(OT_ADDRESS_SPACE(oas), ctn_dma_as);
+
+    qdev_connect_gpio_out_named(DEVICE(s->devices[OT_DJ_SOC_DEV_RSTMGR]),
+                                OT_RSTMGR_SOC_RST, 0,
+                                qdev_get_gpio_in_named(DEVICE(s),
+                                                       OT_DJ_SOC_RST_REQ, 0));
+
+    ot_common_check_rom_configuration();
+
+    /* load kernel if provided */
+    ibex_load_kernel(cpu);
+}
+
+static void ot_dj_soc_init(Object *obj)
+{
+    OtDjSoCState *s = RISCV_OT_DJ_SOC(obj);
+
+    s->devices = ibex_create_devices(ot_dj_soc_devices,
+                                     ARRAY_SIZE(ot_dj_soc_devices), DEVICE(s));
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_dj_soc_hw_reset, OT_DJ_SOC_RST_REQ,
+                            1);
+}
+
+static void ot_dj_soc_class_init(ObjectClass *oc, const void *data)
+{
+    OtDjSoCClass *sc = RISCV_OT_DJ_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    ResettableClass *rc = RESETTABLE_CLASS(dc);
+    (void)data;
+
+    resettable_class_set_parent_phases(rc, NULL, &ot_dj_soc_reset_hold,
+                                       &ot_dj_soc_reset_exit,
+                                       &sc->parent_phases);
+    rc->child_foreach = &ot_dj_soc_reset_child_foreach;
+    dc->realize = &ot_dj_soc_realize;
+    dc->user_creatable = false;
+}
+
+static const TypeInfo ot_dj_soc_type_info = {
+    .name = TYPE_RISCV_OT_DJ_SOC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtDjSoCState),
+    .instance_init = &ot_dj_soc_init,
+    .class_init = &ot_dj_soc_class_init,
+    .class_size = sizeof(OtDjSoCClass),
+};
+
+static void ot_dj_soc_register_types(void)
+{
+    type_register_static(&ot_dj_soc_type_info);
+}
+
+type_init(ot_dj_soc_register_types);
+
+/* ------------------------------------------------------------------------ */
+/* Board */
+/* ------------------------------------------------------------------------ */
+
+static void ot_dj_board_child_foreach(Object *obj, ResettableChildCallback cb,
+                                      void *opaque, ResetType type)
+{
+    OtDjBoardState *s = RISCV_OT_DJ_BOARD(obj);
+
+    for (unsigned ix = 0; ix < OT_DJ_BOARD_DEV_COUNT; ix++) {
+        cb(OBJECT(s->devices[ix]), opaque, type);
+    }
+}
+
+static void ot_dj_board_realize(DeviceState *dev, Error **errp)
+{
+    OtDjBoardState *board = RISCV_OT_DJ_BOARD(dev);
+
+    DeviceState *soc = board->devices[OT_DJ_BOARD_DEV_SOC];
+    object_property_add_child(OBJECT(board), "soc", OBJECT(soc));
+
+    /* CTN memory region */
+    MemoryRegion *ctn_mr = g_new0(MemoryRegion, 1u);
+    memory_region_init(ctn_mr, OBJECT(dev), "ctn.xbar",
+                       (uint64_t)OT_DJ_CTN_REGION_SIZE);
+
+    /* CTN address space */
+    AddressSpace *ctn_as = g_new0(AddressSpace, 1);
+    address_space_init(ctn_as, ctn_mr, "ctn.as");
+    Object *oas = object_new(TYPE_OT_ADDRESS_SPACE);
+    object_property_add_child(OBJECT(dev), ctn_as->name, oas);
+    ot_address_space_set(OT_ADDRESS_SPACE(oas), ctn_as);
+
+    OtDjSoCState *s = RISCV_OT_DJ_SOC(soc);
+
+    BusState *bus = sysbus_get_default();
+    qdev_realize_and_unref(soc, bus, &error_fatal);
+
+    /* CTN RAM */
+    MemoryRegion *ctn_ram = g_new0(MemoryRegion, 1u);
+    memory_region_init_ram_nomigrate(ctn_ram, OBJECT(s), "ctn.ram",
+                                     OT_DJ_CTN_RAM_SIZE, errp);
+    memory_region_add_subregion(ctn_mr, OT_DJ_CTN_RAM_ADDR, ctn_ram);
+
+    /* CTN aliased memory in CPU address space */
+    MemoryRegion *ctn_alias_mr = g_new0(MemoryRegion, 1u);
+    memory_region_init_alias(ctn_alias_mr, OBJECT(dev), "ctn.alias", ctn_mr, 0u,
+                             (uint64_t)OT_DJ_CTN_REGION_SIZE);
+    memory_region_add_subregion(get_system_memory(),
+                                (hwaddr)OT_DJ_CTN_REGION_OFFSET, ctn_alias_mr);
+
+    DeviceState *spihost = s->devices[OT_DJ_SOC_DEV_SPI_HOST0];
+    DeviceState *flash = board->devices[OT_DJ_BOARD_DEV_FLASH];
+    BusState *spibus = qdev_get_child_bus(spihost, "spi0");
+    g_assert(spibus);
+
+    DriveInfo *dinfo = drive_get(IF_MTD, 0, 0);
+    if (dinfo) {
+        qdev_prop_set_drive_err(DEVICE(flash), "drive",
+                                blk_by_legacy_dinfo(dinfo), &error_fatal);
+    }
+    object_property_add_child(OBJECT(board), "dataflash", OBJECT(flash));
+    ssi_realize_and_unref(flash, SSI_BUS(spibus), errp);
+
+    qemu_irq cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
+    qdev_connect_gpio_out_named(spihost, SSI_GPIO_CS, 0, cs);
+
+    DeviceState *devproxy = board->devices[OT_DJ_BOARD_DEV_DEV_PROXY];
+    object_property_add_child(OBJECT(board), "devproxy", OBJECT(devproxy));
+    qdev_realize_and_unref(devproxy, NULL, errp);
+}
+
+static void ot_dj_board_init(Object *obj)
+{
+    OtDjBoardState *s = RISCV_OT_DJ_BOARD(obj);
+
+    s->devices = g_new0(DeviceState *, OT_DJ_BOARD_DEV_COUNT);
+    s->devices[OT_DJ_BOARD_DEV_SOC] = qdev_new(TYPE_RISCV_OT_DJ_SOC);
+    s->devices[OT_DJ_BOARD_DEV_FLASH] = qdev_new("is25wp128");
+    s->devices[OT_DJ_BOARD_DEV_DEV_PROXY] = qdev_new(TYPE_OT_DEV_PROXY);
+}
+
+static void ot_dj_board_class_init(ObjectClass *oc, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    (void)data;
+
+    dc->realize = &ot_dj_board_realize;
+
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
+    rc->child_foreach = &ot_dj_board_child_foreach;
+}
+
+static const TypeInfo ot_dj_board_type_info = {
+    .name = TYPE_RISCV_OT_DJ_BOARD,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(OtDjBoardState),
+    .instance_init = &ot_dj_board_init,
+    .class_init = &ot_dj_board_class_init,
+};
+
+static void ot_dj_board_register_types(void)
+{
+    type_register_static(&ot_dj_board_type_info);
+}
+
+type_init(ot_dj_board_register_types);
+
+/* ------------------------------------------------------------------------ */
+/* Machine */
+/* ------------------------------------------------------------------------ */
+
+static bool ot_dj_machine_get_no_epmp_cfg(Object *obj, Error **errp)
+{
+    OtDjMachineState *s = RISCV_OT_DJ_MACHINE(obj);
+    (void)errp;
+
+    return s->no_epmp_cfg;
+}
+
+static void ot_dj_machine_set_no_epmp_cfg(Object *obj, bool value, Error **errp)
+{
+    OtDjMachineState *s = RISCV_OT_DJ_MACHINE(obj);
+    (void)errp;
+
+    s->no_epmp_cfg = value;
+}
+
+static bool ot_dj_machine_get_ignore_elf_entry(Object *obj, Error **errp)
+{
+    OtDjMachineState *s = RISCV_OT_DJ_MACHINE(obj);
+    (void)errp;
+
+    return s->ignore_elf_entry;
+}
+
+static void
+ot_dj_machine_set_ignore_elf_entry(Object *obj, bool value, Error **errp)
+{
+    OtDjMachineState *s = RISCV_OT_DJ_MACHINE(obj);
+    (void)errp;
+
+    s->ignore_elf_entry = value;
+}
+
+static bool ot_dj_machine_get_verilator(Object *obj, Error **errp)
+{
+    OtDjMachineState *s = RISCV_OT_DJ_MACHINE(obj);
+    (void)errp;
+
+    return s->verilator;
+}
+
+static void ot_dj_machine_set_verilator(Object *obj, bool value, Error **errp)
+{
+    OtDjMachineState *s = RISCV_OT_DJ_MACHINE(obj);
+    (void)errp;
+
+    s->verilator = value;
+}
+
+static ResettableState *ot_dj_machine_get_reset_state(Object *obj)
+{
+    OtDjMachineState *s = RISCV_OT_DJ_MACHINE(obj);
+
+    return &s->reset;
+}
+
+static void ot_dj_machine_child_foreach(Object *obj, ResettableChildCallback cb,
+                                        void *opaque, ResetType type)
+{
+    Object *board = object_property_get_link(obj, "board", &error_fatal);
+
+    cb(board, opaque, type);
+}
+
+static void ot_dj_machine_reset(MachineState *ms, ResetType reason)
+{
+    OtDjMachineState *s = RISCV_OT_DJ_MACHINE(ms);
+
+    g_assert(reason == RESET_TYPE_COLD);
+
+    resettable_reset(OBJECT(s), reason);
+}
+
+static void ot_dj_machine_instance_init(Object *obj)
+{
+    OtDjMachineState *s = RISCV_OT_DJ_MACHINE(obj);
+
+    s->no_epmp_cfg = false;
+    object_property_add_bool(obj, "no-epmp-cfg", &ot_dj_machine_get_no_epmp_cfg,
+                             &ot_dj_machine_set_no_epmp_cfg);
+    object_property_set_description(obj, "no-epmp-cfg",
+                                    "Skip default ePMP configuration");
+    object_property_add_bool(obj, "ignore-elf-entry",
+                             &ot_dj_machine_get_ignore_elf_entry,
+                             &ot_dj_machine_set_ignore_elf_entry);
+    object_property_set_description(obj, "ignore-elf-entry",
+                                    "Do not set vCPU PC with ELF entry point");
+    object_property_add_bool(obj, "verilator", &ot_dj_machine_get_verilator,
+                             &ot_dj_machine_set_verilator);
+    object_property_set_description(obj, "verilator", "Use Verilator clocks");
+}
+
+static void ot_dj_machine_init(MachineState *state)
+{
+    DeviceState *dev = qdev_new(TYPE_RISCV_OT_DJ_BOARD);
+
+    object_property_add_child(OBJECT(state), "board", OBJECT(dev));
+
+    qdev_realize(dev, NULL, &error_fatal);
+}
+
+static void ot_dj_machine_class_init(ObjectClass *oc, const void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    (void)data;
+
+    mc->desc = "RISC-V Board compatible with OpenTitan Darjeeling platform";
+    mc->init = &ot_dj_machine_init;
+    mc->reset = &ot_dj_machine_reset;
+    mc->max_cpus = 1u;
+    mc->default_cpus = 1u;
+
+    /*
+     * Implement the resettable interface to ensure the proper initialization
+     * sequence.
+     */
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+    rc->get_state = &ot_dj_machine_get_reset_state;
+    rc->child_foreach = &ot_dj_machine_child_foreach;
+}
+
+static const TypeInfo ot_dj_machine_type_info = {
+    .name = TYPE_RISCV_OT_DJ_MACHINE,
+    .parent = TYPE_MACHINE,
+    .instance_size = sizeof(OtDjMachineState),
+    .instance_init = &ot_dj_machine_instance_init,
+    .class_init = &ot_dj_machine_class_init,
+    .interfaces = (InterfaceInfo[]){ { TYPE_RESETTABLE_INTERFACE }, {} },
+};
+
+static void ot_dj_machine_register_types(void)
+{
+    type_register_static(&ot_dj_machine_type_info);
+}
+
+type_init(ot_dj_machine_register_types);
diff --git a/hw/riscv/ot_earlgrey.c b/hw/riscv/ot_earlgrey.c
new file mode 100644
index 0000000000000..36034aae9161b
--- /dev/null
+++ b/hw/riscv/ot_earlgrey.c
@@ -0,0 +1,2199 @@
+/*
+ * QEMU RISC-V Board Compatible with OpenTitan EarlGrey FPGA platform
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Copyright (c) 2024-2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * This implementation is based on OpenTitan RTL version:
+ *  <lowRISC/opentitan@caa3bd0a14ddebbf60760490f7c917901482c8fd>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/typedefs.h"
+#include "qapi/error.h"
+#include "qom/object.h"
+#include "hw/block/flash.h"
+#include "hw/boards.h"
+#include "hw/core/split-irq.h"
+#include "hw/intc/sifive_plic.h"
+#include "hw/jtag/tap_ctrl.h"
+#include "hw/jtag/tap_ctrl_rbb.h"
+#include "hw/misc/pulp_rv_dm.h"
+#include "hw/opentitan/ot_address_space.h"
+#include "hw/opentitan/ot_aes.h"
+#include "hw/opentitan/ot_alert.h"
+#include "hw/opentitan/ot_aon_timer.h"
+#include "hw/opentitan/ot_ast_eg.h"
+#include "hw/opentitan/ot_clkmgr.h"
+#include "hw/opentitan/ot_common.h"
+#include "hw/opentitan/ot_csrng.h"
+#include "hw/opentitan/ot_dm_tl.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_eg_pad_ring.h"
+#include "hw/opentitan/ot_entropy_src.h"
+#include "hw/opentitan/ot_flash.h"
+#include "hw/opentitan/ot_gpio_eg.h"
+#include "hw/opentitan/ot_hmac.h"
+#include "hw/opentitan/ot_i2c.h"
+#include "hw/opentitan/ot_ibex_wrapper.h"
+#include "hw/opentitan/ot_keymgr.h"
+#include "hw/opentitan/ot_kmac.h"
+#include "hw/opentitan/ot_lc_ctrl.h"
+#include "hw/opentitan/ot_otbn.h"
+#include "hw/opentitan/ot_otp_eg.h"
+#include "hw/opentitan/ot_otp_if.h"
+#include "hw/opentitan/ot_otp_ot_be.h"
+#include "hw/opentitan/ot_pinmux_eg.h"
+#include "hw/opentitan/ot_plic_ext.h"
+#include "hw/opentitan/ot_pwrmgr.h"
+#include "hw/opentitan/ot_rom_ctrl.h"
+#include "hw/opentitan/ot_rstmgr.h"
+#include "hw/opentitan/ot_sensor_eg.h"
+#include "hw/opentitan/ot_spi_device.h"
+#include "hw/opentitan/ot_spi_host.h"
+#include "hw/opentitan/ot_sram_ctrl.h"
+#include "hw/opentitan/ot_timer.h"
+#include "hw/opentitan/ot_uart.h"
+#include "hw/opentitan/ot_unimp.h"
+#include "hw/opentitan/ot_usbdev.h"
+#include "hw/opentitan/ot_vmapper.h"
+#include "hw/qdev-properties.h"
+#include "hw/riscv/dm.h"
+#include "hw/riscv/dtm.h"
+#include "hw/riscv/ibex_common.h"
+#include "hw/riscv/ot_earlgrey.h"
+#include "hw/ssi/ssi.h"
+#include "qobject/qlist.h"
+#include "system/address-spaces.h"
+#include "system/blockdev.h"
+#include "system/hw_accel.h"
+#include "system/reset.h"
+#include "system/system.h"
+
+/* ------------------------------------------------------------------------ */
+/* Forward Declarations */
+/* ------------------------------------------------------------------------ */
+
+static void ot_eg_soc_ast_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                    DeviceState *parent);
+static void ot_eg_soc_dm_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                   DeviceState *parent);
+static void ot_eg_soc_flash_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ot_eg_soc_hart_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                     DeviceState *parent);
+static void ot_eg_soc_otp_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ot_eg_soc_tap_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ot_eg_soc_lc_ctrl_tap_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ot_eg_soc_spi_device_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+static void ot_eg_soc_uart_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                     DeviceState *parent);
+static void ot_eg_soc_usbdev_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
+
+/* ------------------------------------------------------------------------ */
+/* Constants */
+/* ------------------------------------------------------------------------ */
+
+enum OtEgMemoryRegion {
+    OT_EG_DEFAULT_MEMORY_REGION,
+    OT_EG_LC_CTRL_TAP_MEMORY_REGION,
+};
+
+#define LC_CTRL_TAP_MEMORY(_addr_) \
+    IBEX_MEMMAP_MAKE_REG((_addr_), OT_EG_LC_CTRL_TAP_MEMORY_REGION)
+
+enum OtEGSocDevice {
+    OT_EG_SOC_DEV_ADC_CTRL,
+    OT_EG_SOC_DEV_AES,
+    OT_EG_SOC_DEV_ALERT_HANDLER,
+    OT_EG_SOC_DEV_AON_TIMER,
+    OT_EG_SOC_DEV_AST,
+    OT_EG_SOC_DEV_CLKMGR,
+    OT_EG_SOC_DEV_CSRNG,
+    OT_EG_SOC_DEV_DM,
+    OT_EG_SOC_DEV_DTM,
+    OT_EG_SOC_DEV_LC_CTRL_DTM,
+    OT_EG_SOC_DEV_EDN0,
+    OT_EG_SOC_DEV_EDN1,
+    OT_EG_SOC_DEV_ENTROPY_SRC,
+    OT_EG_SOC_DEV_FLASH_CTRL,
+    OT_EG_SOC_DEV_GPIO,
+    OT_EG_SOC_DEV_HART,
+    OT_EG_SOC_DEV_HMAC,
+    OT_EG_SOC_DEV_I2C0,
+    OT_EG_SOC_DEV_I2C1,
+    OT_EG_SOC_DEV_I2C2,
+    OT_EG_SOC_DEV_IBEX_WRAPPER,
+    OT_EG_SOC_DEV_KEYMGR,
+    OT_EG_SOC_DEV_KMAC,
+    OT_EG_SOC_DEV_LC_CTRL,
+    OT_EG_SOC_DEV_OTBN,
+    OT_EG_SOC_DEV_OTP_CTRL,
+    OT_EG_SOC_DEV_OTP_BACKEND,
+    OT_EG_SOC_DEV_PAD_RING,
+    OT_EG_SOC_DEV_PATTGEN,
+    OT_EG_SOC_DEV_PINMUX,
+    OT_EG_SOC_DEV_PLIC,
+    OT_EG_SOC_DEV_PLIC_EXT,
+    OT_EG_SOC_DEV_PWM,
+    OT_EG_SOC_DEV_PWRMGR,
+    OT_EG_SOC_DEV_SRAM_RET_CTRL,
+    OT_EG_SOC_DEV_ROM_CTRL,
+    OT_EG_SOC_DEV_RSTMGR,
+    OT_EG_SOC_DEV_RV_DM,
+    OT_EG_SOC_DEV_DM_LC_CTRL,
+    OT_EG_SOC_DEV_SENSOR_CTRL,
+    OT_EG_SOC_DEV_SPI_DEVICE,
+    OT_EG_SOC_DEV_SPI_HOST0,
+    OT_EG_SOC_DEV_SPI_HOST1,
+    OT_EG_SOC_DEV_SRAM_MAIN_CTRL,
+    OT_EG_SOC_DEV_SYSRST_CTRL,
+    OT_EG_SOC_DEV_TAP_CTRL,
+    OT_EG_SOC_DEV_LC_CTRL_TAP_CTRL,
+    OT_EG_SOC_DEV_TIMER,
+    OT_EG_SOC_DEV_UART0,
+    OT_EG_SOC_DEV_UART1,
+    OT_EG_SOC_DEV_UART2,
+    OT_EG_SOC_DEV_UART3,
+    OT_EG_SOC_DEV_USBDEV,
+    OT_EG_SOC_DEV_VMAPPER,
+    /* IRQ splitters, i.e. 1-to-N signal dispatchers */
+    OT_EG_SOC_SPLITTER_LC_HW_DEBUG,
+    OT_EG_SOC_SPLITTER_LC_ESCALATE,
+    OT_EG_SOC_SPLITTER_LC_SEED_HW_RD,
+    OT_EG_SOC_SPLITTER_LC_CREATOR_SEED_SW_RW,
+};
+
+enum OtEgResetRequest {
+    OT_EG_RESET_SYSRST_CTRL,
+    OT_EG_RESET_AON_TIMER,
+    OT_EG_RESET_SENSOR_CTRL,
+    OT_EG_RESET_COUNT
+};
+
+/* Data flash buses */
+enum OtEgMtdBus {
+    OT_EG_MTD_SPI0,
+    OT_EG_MTD_SPI1,
+    OT_EG_MTD_SPI_COUNT,
+    OT_EG_MTD_EFLASH = OT_EG_MTD_SPI_COUNT,
+};
+
+/* "Parallel" flash buses */
+enum OtEgPflashBus {
+    OT_EG_PFLASH_OTP,
+};
+
+enum OtEGBoardDevice {
+    OT_EG_BOARD_DEV_SOC,
+    OT_EG_BOARD_DEV_FLASH0,
+    OT_EG_BOARD_DEV_FLASH1,
+    OT_EG_BOARD_DEV_COUNT,
+};
+
+/*
+ * <opentitan>/hw/ip/lc_ctrl/rtl/lc_ctrl.sv instantiates a DMI module (with
+ * abits=7) and a DMI to TL-UL adapter. Together, they create a private bus,
+ * exposing the LC Ctrl registers over JTAG <-> DTM <-> DMI <-> TL-UL. On the
+ * DMI side we have the address space [0 .. 2^7); those addresses are mapped to
+ * words on the TL-UL side, addressing [0 .. 2^7*4) bytes, and accessing the LC
+ * Ctrl registers at the appropriate (documented) offset.
+ */
+#define OT_EG_LC_CTRL_TAP_DMI_ABITS 7u
+#define OT_EG_LC_CTRL_TAP_DMI_ADDR  0x0u
+#define OT_EG_LC_CTRL_TAP_DMI_SIZE  (1u << OT_EG_LC_CTRL_TAP_DMI_ABITS)
+#define OT_EG_LC_CTRL_TAP_TL_ADDR   0x0u
+#define OT_EG_LC_CTRL_TAP_TL_SIZE   ((1u << OT_EG_LC_CTRL_TAP_DMI_ABITS) * 4u)
+
+#define OT_EG_LC_CTRL_TAP      "ot-lc_ctrl-tap"
+#define OT_EG_LC_CTRL_TAP_XBAR OT_EG_LC_CTRL_TAP ".xbar"
+#define OT_EG_LC_CTRL_TAP_AS   OT_EG_LC_CTRL_TAP ".as"
+
+#define OT_EG_IBEX_WRAPPER_NUM_REGIONS 2u
+
+static const uint8_t ot_eg_pmp_cfgs[] = {
+    /* clang-format off */
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(1, IBEX_PMP_MODE_NAPOT, 1, 0, 1), /* rgn 2  [ROM: LRX] */
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(1, IBEX_PMP_MODE_TOR, 0, 1, 1), /* rgn 11 [MMIO: LRW] */
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(1, IBEX_PMP_MODE_NAPOT, 1, 1, 1), /* rgn 13 [DV_ROM: LRWX] */
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0),
+    IBEX_PMP_CFG(0, IBEX_PMP_MODE_OFF, 0, 0, 0)
+    /* clang-format on */
+};
+
+static const uint32_t ot_eg_pmp_addrs[] = {
+    /* clang-format off */
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x000083fc), /* rgn 2 [ROM: base=0x0000_8000 sz (2KiB)] */
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x40000000), /* rgn 10 [MMIO: lo=0x4000_0000] */
+    IBEX_PMP_ADDR(0x42010000), /* rgn 11 [MMIO: hi=0x4201_0000] */
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x000107fc), /* rgn 13 [DV_ROM: base=0x0001_0000 sz (4KiB)] */
+    IBEX_PMP_ADDR(0x00000000),
+    IBEX_PMP_ADDR(0x00000000)
+    /* clang-format on */
+};
+
+#define OT_EG_MSECCFG IBEX_MSECCFG(1, 1, 0)
+
+#define OT_EG_SOC_RST_REQ TYPE_RISCV_OT_EG_SOC "-reset"
+
+#define OT_EG_SOC_GPIO(_irq_, _target_, _num_) \
+    IBEX_GPIO(_irq_, OT_EG_SOC_DEV_##_target_, _num_)
+
+#define OT_EG_SOC_GPIO_SYSBUS_IRQ(_irq_, _target_, _num_) \
+    IBEX_GPIO_SYSBUS_IRQ(_irq_, OT_EG_SOC_DEV_##_target_, _num_)
+
+#define OT_EG_SOC_GPIO_ALERT(_snum_, _tnum_) \
+    OT_EG_SOC_SIGNAL(OT_DEVICE_ALERT, _snum_, ALERT_HANDLER, OT_DEVICE_ALERT, \
+                     _tnum_)
+
+#define OT_EG_SOC_GPIO_ESCALATE(_snum_, _tgt_, _tnum_) \
+    OT_EG_SOC_SIGNAL(OT_ALERT_ESCALATE, _snum_, _tgt_, OT_ALERT_ESCALATE, \
+                     _tnum_)
+
+#define OT_EG_SOC_DEVLINK(_pname_, _target_) \
+    IBEX_DEVLINK(_pname_, OT_EG_SOC_DEV_##_target_)
+
+/* Device named signal to device named signal */
+#define OT_EG_SOC_SIGNAL(_sname_, _snum_, _tgt_, _tname_, _tnum_) \
+    { \
+        .out = { \
+            .name = (_sname_), \
+            .num = (_snum_), \
+        }, \
+        .in = { \
+            .name = (_tname_), \
+            .index = (OT_EG_SOC_DEV_ ## _tgt_), \
+            .num = (_tnum_), \
+        } \
+    }
+
+/* Device named signal to splitter input */
+#define OT_EG_SOC_D2S(_sname_, _snum_, _tgt_) \
+    { \
+        .out = { \
+            .name = (_sname_), \
+            .num = (_snum_), \
+        }, \
+        .in = { \
+            .index = (OT_EG_SOC_SPLITTER_ ## _tgt_), \
+        } \
+    }
+
+/* Splitter output to device named signal */
+#define OT_EG_SOC_S2D(_snum_, _tgt_, _tname_, _tnum_) \
+    { \
+        .out = { \
+            .num = (_snum_), \
+        }, \
+        .in = { \
+            .name = (_tname_), \
+            .index = (OT_EG_SOC_DEV_ ## _tgt_), \
+            .num = (_tnum_), \
+        } \
+    }
+
+/* Request link */
+#define OT_EG_SOC_REQ(_req_, _tgt_) \
+    OT_EG_SOC_SIGNAL(_req_##_REQ, 0, _tgt_, _req_##_REQ, 0)
+
+/* Response link */
+#define OT_EG_SOC_RSP(_rsp_, _tgt_) \
+    OT_EG_SOC_SIGNAL(_rsp_##_RSP, 0, _tgt_, _rsp_##_RSP, 0)
+
+#define OT_EG_SOC_DM_CONNECTION(_dst_dev_, _num_) \
+    { \
+        .out = { \
+            .name = PULP_RV_DM_ACK_OUT_LINES, \
+            .num = (_num_), \
+        }, \
+        .in = { \
+            .name = RISCV_DM_ACK_LINES, \
+            .index = (_dst_dev_), \
+            .num = (_num_), \
+        } \
+    }
+
+/*
+ * Earlgrey 1.0.0 TAPs
+ * See https://github.com/lowRISC/part-number-registry/blob/main/jtag_partno.md
+ */
+#define EG_RV_DM_TAP_IDCODE    IBEX_JTAG_IDCODE(0, 1, 1)
+#define EG_LC_CTRL_TAP_IDCODE  IBEX_JTAG_IDCODE(0, 2, 1)
+#define EG_COMBINED_TAP_IDCODE IBEX_JTAG_IDCODE(0, 3, 1)
+
+#define PULP_DM_BASE   0x00010000u
+#define SRAM_MAIN_SIZE 0x20000u
+
+/*
+ * MMIO/interrupt mapping as per:
+ * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
+ * and
+ * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey.h
+ */
+static const IbexDeviceDef ot_eg_soc_devices[] = {
+    /* clang-format off */
+    [OT_EG_SOC_DEV_HART] = {
+        .type = TYPE_RISCV_CPU_LOWRISC_OPENTITAN,
+        .cfg = &ot_eg_soc_hart_configure,
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("resetvec", 0x8080u),
+            IBEX_DEV_UINT_PROP("mtvec", 0x8001u),
+            IBEX_DEV_UINT_PROP("dmhaltvec", PULP_DM_BASE +
+                PULP_RV_DM_ROM_BASE + PULP_RV_DM_HALT_OFFSET),
+            IBEX_DEV_UINT_PROP("dmexcpvec", PULP_DM_BASE +
+                PULP_RV_DM_ROM_BASE + PULP_RV_DM_EXCEPTION_OFFSET),
+            IBEX_DEV_BOOL_PROP("start-powered-off", true)
+        ),
+    },
+    [OT_EG_SOC_DEV_TAP_CTRL] = {
+        .type = TYPE_TAP_CTRL_RBB,
+        .cfg = &ot_eg_soc_tap_ctrl_configure,
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("ir_length", IBEX_TAP_IR_LENGTH),
+            IBEX_DEV_UINT_PROP("idcode", EG_RV_DM_TAP_IDCODE)
+        ),
+    },
+    [OT_EG_SOC_DEV_LC_CTRL_TAP_CTRL] = {
+        .type = TYPE_TAP_CTRL_RBB,
+        .cfg = &ot_eg_soc_lc_ctrl_tap_ctrl_configure,
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("ir_length", IBEX_TAP_IR_LENGTH),
+            IBEX_DEV_UINT_PROP("idcode", EG_LC_CTRL_TAP_IDCODE)
+        ),
+    },
+    [OT_EG_SOC_DEV_DTM] = {
+        .type = TYPE_RISCV_DTM,
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("tap-ctrl", TAP_CTRL)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("abits", 7u)
+        ),
+    },
+    [OT_EG_SOC_DEV_LC_CTRL_DTM] = {
+        .type = TYPE_RISCV_DTM,
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("tap-ctrl", LC_CTRL_TAP_CTRL)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("abits", OT_EG_LC_CTRL_TAP_DMI_ABITS)
+        ),
+    },
+    [OT_EG_SOC_DEV_DM] = {
+        .type = TYPE_RISCV_DM,
+        .cfg = &ot_eg_soc_dm_configure,
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("dtm", DTM)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("nscratch", PULP_RV_DM_NSCRATCH_COUNT),
+            IBEX_DEV_UINT_PROP("progbuf_count",
+                PULP_RV_DM_PROGRAM_BUFFER_COUNT),
+            IBEX_DEV_UINT_PROP("data_count", PULP_RV_DM_DATA_COUNT),
+            IBEX_DEV_UINT_PROP("abstractcmd_count",
+                PULP_RV_DM_ABSTRACTCMD_COUNT),
+            IBEX_DEV_UINT_PROP("dm_phyaddr", PULP_DM_BASE),
+            IBEX_DEV_UINT_PROP("rom_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_ROM_BASE),
+            IBEX_DEV_UINT_PROP("whereto_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_WHERETO_OFFSET),
+            IBEX_DEV_UINT_PROP("data_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_DATAADDR_OFFSET),
+            IBEX_DEV_UINT_PROP("progbuf_phyaddr",
+                PULP_DM_BASE + PULP_RV_DM_PROGRAM_BUFFER_OFFSET),
+            IBEX_DEV_UINT_PROP("resume_offset", PULP_RV_DM_RESUME_OFFSET),
+            IBEX_DEV_BOOL_PROP("sysbus_access", true),
+            IBEX_DEV_BOOL_PROP("abstractauto", true)
+        ),
+    },
+    [OT_EG_SOC_DEV_UART0] = {
+        .type = TYPE_OT_UART,
+        .cfg = &ot_eg_soc_uart_configure,
+        .instance = IBEX_MAKE_INSTANCE_NUM(0),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 1),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 2),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 3),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 4),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 5),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 6),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 7),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 8),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 9),
+            OT_EG_SOC_GPIO_ALERT(0, 0)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "u0"),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4")
+        ),
+    },
+    [OT_EG_SOC_DEV_UART1] = {
+        .type = TYPE_OT_UART,
+        .cfg = &ot_eg_soc_uart_configure,
+        .instance = IBEX_MAKE_INSTANCE_NUM(1),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40010000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 10),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 11),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 12),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 13),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 14),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 15),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 16),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 17),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 18),
+            OT_EG_SOC_GPIO_ALERT(0, 1)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "u1"),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4")
+        ),
+    },
+    [OT_EG_SOC_DEV_UART2] = {
+        .type = TYPE_OT_UART,
+        .cfg = &ot_eg_soc_uart_configure,
+        .instance = IBEX_MAKE_INSTANCE_NUM(2),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40020000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 19),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 20),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 21),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 22),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 23),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 24),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 25),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 26),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 27),
+            OT_EG_SOC_GPIO_ALERT(0, 2)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "u2"),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4")
+        ),
+    },
+    [OT_EG_SOC_DEV_UART3] = {
+        .type = TYPE_OT_UART,
+        .cfg = &ot_eg_soc_uart_configure,
+        .instance = IBEX_MAKE_INSTANCE_NUM(3),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40030000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 28),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 29),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 30),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 31),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 32),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 33),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 34),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 35),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 36),
+            OT_EG_SOC_GPIO_ALERT(0, 3)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "u3"),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4")
+        ),
+    },
+    [OT_EG_SOC_DEV_GPIO] = {
+        .type = TYPE_OT_GPIO_EG,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40040000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 37),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 38),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 39),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 40),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 41),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 42),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 43),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 44),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 45),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(9, PLIC, 46),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(10, PLIC, 47),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(11, PLIC, 48),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(12, PLIC, 49),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(13, PLIC, 50),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(14, PLIC, 51),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(15, PLIC, 52),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(16, PLIC, 53),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(17, PLIC, 54),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(18, PLIC, 55),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(19, PLIC, 56),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(20, PLIC, 57),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(21, PLIC, 58),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(22, PLIC, 59),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(23, PLIC, 60),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(24, PLIC, 61),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(25, PLIC, 62),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(26, PLIC, 63),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(27, PLIC, 64),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(28, PLIC, 65),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(29, PLIC, 66),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(30, PLIC, 67),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(31, PLIC, 68),
+            OT_EG_SOC_GPIO_ALERT(0, 4)
+        )
+    },
+    [OT_EG_SOC_DEV_SPI_DEVICE] = {
+        .type = TYPE_OT_SPI_DEVICE,
+        .cfg = &ot_eg_soc_spi_device_configure,
+        .instance = IBEX_MAKE_INSTANCE_NUM(0),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40050000u }
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("spi-host", SPI_HOST0)
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 69),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 70),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 71),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 72),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 73),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 74),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 75),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 76),
+            OT_EG_SOC_GPIO_ALERT(0, 5),
+            OT_EG_SOC_SIGNAL(OT_SPI_DEVICE_PASSTHROUGH_EN, 0, SPI_HOST0,
+                OT_SPI_HOST_PASSTHROUGH_EN, 0),
+            OT_EG_SOC_SIGNAL(OT_SPI_DEVICE_PASSTHROUGH_CS, 0, SPI_HOST0,
+                OT_SPI_HOST_PASSTHROUGH_CS, 0)
+        ),
+    },
+    [OT_EG_SOC_DEV_I2C0] = {
+        .type = TYPE_OT_I2C,
+        .instance = IBEX_MAKE_INSTANCE_NUM(0),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40080000u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "i2c0"),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4")
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 77),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 78),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 79),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 80),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 81),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 82),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 83),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 84),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 85),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(9, PLIC, 86),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(10, PLIC, 87),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(11, PLIC, 88),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(12, PLIC, 89),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(13, PLIC, 90),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(14, PLIC, 91),
+            OT_EG_SOC_GPIO_ALERT(0, 6)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        )
+    },
+    [OT_EG_SOC_DEV_I2C1] = {
+        .type = TYPE_OT_I2C,
+        .instance = IBEX_MAKE_INSTANCE_NUM(1),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40090000u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "i2c1"),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4")
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 92),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 93),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 94),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 95),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 96),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 97),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 98),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 99),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 100),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(9, PLIC, 101),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(10, PLIC, 102),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(11, PLIC, 103),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(12, PLIC, 104),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(13, PLIC, 105),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(14, PLIC, 106),
+            OT_EG_SOC_GPIO_ALERT(0, 7)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        )
+    },
+    [OT_EG_SOC_DEV_I2C2] = {
+        .type = TYPE_OT_I2C,
+        .instance = IBEX_MAKE_INSTANCE_NUM(2),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x400a0000u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "i2c2"),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4")
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 107),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 108),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 109),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 110),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 111),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 112),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 113),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 114),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 115),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(9, PLIC, 116),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(10, PLIC, 117),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(11, PLIC, 118),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(12, PLIC, 119),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(13, PLIC, 120),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(14, PLIC, 121),
+            OT_EG_SOC_GPIO_ALERT(0, 8)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        )
+    },
+    [OT_EG_SOC_DEV_PAD_RING] = {
+        .type = TYPE_OT_EG_PAD_RING,
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_SIGNAL(OT_EG_PAD_RING_POR_REQ, 0, RSTMGR,
+                             OT_RSTMGR_RST_REQ, 0)
+        ),
+    },
+    [OT_EG_SOC_DEV_PATTGEN] = {
+        .type = TYPE_OT_UNIMP,
+        .cfg = &ibex_unimp_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x400e0000u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "pattgen"),
+            IBEX_DEV_UINT_PROP("size", 0x40u),
+            IBEX_DEV_UINT_PROP("irq-count", 2u),
+            IBEX_DEV_UINT_PROP("alert-count", 1u),
+            IBEX_DEV_BOOL_PROP("warn-once", true)
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 9)
+        )
+    },
+    [OT_EG_SOC_DEV_TIMER] = {
+        .type = TYPE_OT_TIMER,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40100000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO(0, HART, IRQ_M_TIMER),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 124),
+            OT_EG_SOC_GPIO_ALERT(0, 10)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "timers.io_div4")
+        ),
+    },
+    [OT_EG_SOC_DEV_OTP_CTRL] = {
+        .type = TYPE_OT_OTP_EG,
+        .cfg = &ot_eg_soc_otp_ctrl_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40130000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 125),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 126),
+            OT_EG_SOC_GPIO_ALERT(0, 11),
+            OT_EG_SOC_GPIO_ALERT(1, 12),
+            OT_EG_SOC_GPIO_ALERT(2, 13),
+            OT_EG_SOC_GPIO_ALERT(3, 14),
+            OT_EG_SOC_GPIO_ALERT(4, 15),
+            OT_EG_SOC_RSP(OT_PWRMGR_OTP, PWRMGR)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("edn", EDN0),
+            OT_EG_SOC_DEVLINK("backend", OTP_BACKEND)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("edn-ep", 1u)
+        ),
+    },
+    [OT_EG_SOC_DEV_OTP_BACKEND] = {
+        .type = TYPE_OT_OTP_OT_BE,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40132000u }
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("parent", OTP_CTRL)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("write_ns", 25000u), /* 25 us */
+            IBEX_DEV_UINT_PROP("read_ns", 5000u) /* 5 us */
+        )
+    },
+    [OT_EG_SOC_DEV_LC_CTRL] = {
+        .type = TYPE_OT_LC_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40140000u },
+            { .base = LC_CTRL_TAP_MEMORY(OT_EG_LC_CTRL_TAP_TL_ADDR) }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_RSP(OT_PWRMGR_LC, PWRMGR),
+            OT_EG_SOC_GPIO_ALERT(0, 16),
+            OT_EG_SOC_GPIO_ALERT(1, 17),
+            OT_EG_SOC_GPIO_ALERT(2, 18),
+            /*
+             * @todo: check for missing life cycle broadcast signal connections
+             * and add them when the required supporting HW is available.
+             */
+            /* Splitters for signals that go to many blocks. */
+            OT_EG_SOC_D2S(OT_LC_BROADCAST, OT_LC_HW_DEBUG_EN, LC_HW_DEBUG),
+            OT_EG_SOC_D2S(OT_LC_BROADCAST, OT_LC_ESCALATE_EN, LC_ESCALATE),
+            OT_EG_SOC_D2S(OT_LC_BROADCAST, OT_LC_SEED_HW_RD_EN, LC_SEED_HW_RD),
+            OT_EG_SOC_D2S(OT_LC_BROADCAST, OT_LC_CREATOR_SEED_SW_RW_EN,
+                          LC_CREATOR_SEED_SW_RW),
+            /* Signals to ibex_wrapper */
+            OT_EG_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_CPU_EN, IBEX_WRAPPER,
+                             OT_IBEX_WRAPPER_CPU_EN, OT_IBEX_LC_CTRL_CPU_EN),
+            /* Signals to keymgr */
+            OT_EG_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_KEYMGR_EN, KEYMGR,
+                             OT_KEYMGR_ENABLE, 0),
+            /* Signals to flash_ctrl */
+            OT_EG_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_OWNER_SEED_SW_RW_EN,
+                             FLASH_CTRL, OT_LC_BROADCAST,
+                             OT_FLASH_LC_OWNER_SEED_SW_RW_EN),
+            OT_EG_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_SEED_HW_RD_EN, FLASH_CTRL,
+                             OT_LC_BROADCAST, OT_FLASH_LC_SEED_HW_RD_EN),
+            OT_EG_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_ISO_PART_SW_RD_EN,
+                             FLASH_CTRL, OT_LC_BROADCAST,
+                             OT_FLASH_LC_ISO_PART_SW_RD_EN),
+            OT_EG_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_ISO_PART_SW_WR_EN,
+                             FLASH_CTRL, OT_LC_BROADCAST,
+                             OT_FLASH_LC_ISO_PART_SW_WR_EN),
+            OT_EG_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_NVM_DEBUG_EN, FLASH_CTRL,
+                             OT_LC_BROADCAST, OT_FLASH_LC_NVM_DEBUG_EN),
+            /* Signals to OTP */
+            OT_EG_SOC_SIGNAL(OT_LC_BROADCAST, OT_LC_CHECK_BYP_EN, OTP_CTRL,
+                             OT_LC_BROADCAST, OT_OTP_LC_CHECK_BYP_EN)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("otp-ctrl", OTP_CTRL),
+            OT_EG_SOC_DEVLINK("kmac", KMAC)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("silicon_creator_id", 0x4001u),
+            IBEX_DEV_UINT_PROP("product_id", 0x0002u),
+            IBEX_DEV_UINT_PROP("revision_id", 0x1u),
+            IBEX_DEV_BOOL_PROP("volatile_raw_unlock", true),
+            IBEX_DEV_UINT_PROP("kmac-app", 1u)
+        )
+    },
+    [OT_EG_SOC_DEV_ALERT_HANDLER] = {
+        .type = TYPE_OT_ALERT,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40150000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 127),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 128),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 129),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 130),
+            OT_EG_SOC_GPIO_ESCALATE(0, IBEX_WRAPPER, 0),
+            OT_EG_SOC_GPIO_ESCALATE(1, LC_CTRL, 0),
+            OT_EG_SOC_GPIO_ESCALATE(1, LC_CTRL, 1),
+            OT_EG_SOC_GPIO_ESCALATE(3, PWRMGR, 0)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR),
+            OT_EG_SOC_DEVLINK("edn", EDN0)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("n_alerts", 65u),
+            IBEX_DEV_UINT_PROP("n_classes", 4u),
+            IBEX_DEV_UINT_PROP("n_lpg", 22u),
+            IBEX_DEV_UINT_PROP("edn-ep", 4u),
+            IBEX_DEV_STRING_PROP("clock-name", "secure.io_div4"),
+            IBEX_DEV_STRING_PROP("clock-name-edn", "secure.main")
+        ),
+    },
+    [OT_EG_SOC_DEV_SPI_HOST0] = {
+        .type = TYPE_OT_SPI_HOST,
+        .instance = IBEX_MAKE_INSTANCE_NUM(0),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40300000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 131),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 132),
+            OT_EG_SOC_GPIO_ALERT(0, 19)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "spi0"),
+            IBEX_DEV_UINT_PROP("bus-num", 0),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4"),
+            IBEX_DEV_UINT_PROP("version", 2u)
+        ),
+    },
+    [OT_EG_SOC_DEV_SPI_HOST1] = {
+        .type = TYPE_OT_SPI_HOST,
+        .instance = IBEX_MAKE_INSTANCE_NUM(1),
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40310000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 133),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 134),
+            OT_EG_SOC_GPIO_ALERT(0, 20)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "spi1"),
+            IBEX_DEV_UINT_PROP("bus-num", 1),
+            IBEX_DEV_STRING_PROP("clock-name", "peri.io_div4"),
+            IBEX_DEV_UINT_PROP("version", 2u)
+        ),
+    },
+    [OT_EG_SOC_DEV_USBDEV] = {
+        .type = TYPE_OT_USBDEV,
+        .cfg = &ot_eg_soc_usbdev_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40320000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 135),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 136),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 137),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 138),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 139),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 140),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(6, PLIC, 141),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(7, PLIC, 142),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(8, PLIC, 143),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(9, PLIC, 144),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(10, PLIC, 145),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(11, PLIC, 146),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(12, PLIC, 147),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(13, PLIC, 148),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(14, PLIC, 149),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(15, PLIC, 150),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(16, PLIC, 151),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(17, PLIC, 152),
+            OT_EG_SOC_GPIO_ALERT(0, 21)
+            /* The VBUS sense pin is handled by a chardev */
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "usbdev"),
+            IBEX_DEV_STRING_PROP("clock-name", "usb"),
+            IBEX_DEV_STRING_PROP("clock-name-aon", "aon")
+        ),
+    },
+    [OT_EG_SOC_DEV_PWRMGR] = {
+        .type = TYPE_OT_PWRMGR,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40400000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 153),
+            OT_EG_SOC_GPIO_ALERT(0, 22),
+            OT_EG_SOC_REQ(OT_PWRMGR_OTP, OTP_CTRL),
+            OT_EG_SOC_REQ(OT_PWRMGR_LC, LC_CTRL),
+            OT_EG_SOC_SIGNAL(OT_PWRMGR_CPU_EN, 0, IBEX_WRAPPER,
+                             OT_IBEX_WRAPPER_CPU_EN,
+                             OT_IBEX_PWRMGR_CPU_EN),
+            /* todo: add pwmgr GPIO strap when Earlgrey GPIO is updated */
+            OT_EG_SOC_SIGNAL(OT_PWRMGR_RST_REQ, 0, RSTMGR,
+                             OT_RSTMGR_RST_REQ, 0)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-ctrl", AST)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clocks", "main,io,usb"),
+            IBEX_DEV_UINT_PROP("num-rom", 1u),
+            IBEX_DEV_UINT_PROP("version", OT_PWRMGR_VERSION_EG_1_0_0)
+        ),
+    },
+    [OT_EG_SOC_DEV_RSTMGR] = {
+        .type = TYPE_OT_RSTMGR,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40410000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_SIGNAL(OT_RSTMGR_SW_RST, 0, PWRMGR, \
+                                   OT_PWRMGR_SW_RST, 0),
+            OT_EG_SOC_GPIO_ALERT(0, 23),
+            OT_EG_SOC_GPIO_ALERT(1, 24)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("version", OT_RSTMGR_VERSION_EG_1_0_0)
+        ),
+    },
+    [OT_EG_SOC_DEV_CLKMGR] = {
+        .type = TYPE_OT_CLKMGR,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40420000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 25),
+            OT_EG_SOC_GPIO_ALERT(1, 26)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", AST)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("version", OT_CLKMGR_VERSION_EG_1_0_0)
+        ),
+    },
+    [OT_EG_SOC_DEV_SYSRST_CTRL] = {
+        .type = TYPE_OT_UNIMP,
+        .cfg = &ibex_unimp_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40430000u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "sysrst_ctrl"),
+            IBEX_DEV_UINT_PROP("size", 0x100u),
+            IBEX_DEV_UINT_PROP("irq-count", 1u),
+            IBEX_DEV_UINT_PROP("alert-count", 1u),
+            IBEX_DEV_BOOL_PROP("warn-once", true)
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 27)
+        )
+    },
+    [OT_EG_SOC_DEV_ADC_CTRL] = {
+        .type = TYPE_OT_UNIMP,
+        .cfg = &ibex_unimp_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40440000u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "adc_ctrl"),
+            IBEX_DEV_UINT_PROP("size", 0x80u),
+            IBEX_DEV_UINT_PROP("irq-count", 1u),
+            IBEX_DEV_UINT_PROP("alert-count", 1u),
+            IBEX_DEV_BOOL_PROP("warn-once", true)
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 28)
+        )
+    },
+    [OT_EG_SOC_DEV_PWM] = {
+        .type = TYPE_OT_UNIMP,
+        .cfg = &ibex_unimp_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40450000u }
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "pwm"),
+            IBEX_DEV_UINT_PROP("size", 0x80u),
+            IBEX_DEV_UINT_PROP("alert-count", 1u),
+            IBEX_DEV_BOOL_PROP("warn-once", true)
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 29)
+        )
+    },
+    [OT_EG_SOC_DEV_PINMUX] = {
+        .type = TYPE_OT_PINMUX_EG,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40460000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 30)
+        )
+    },
+    [OT_EG_SOC_DEV_AON_TIMER] = {
+        .type = TYPE_OT_AON_TIMER,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40470000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 156),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 157),
+            OT_EG_SOC_SIGNAL(OT_AON_TIMER_WKUP, 0, PWRMGR, \
+                             OT_PWRMGR_WKUP, OT_PWRMGR_WAKEUP_AON_TIMER),
+            OT_EG_SOC_SIGNAL(OT_AON_TIMER_BITE, 0, PWRMGR, \
+                             OT_PWRMGR_RST, OT_EG_RESET_AON_TIMER),
+            OT_EG_SOC_GPIO_ALERT(0, 31)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "timers.io_div4"),
+            IBEX_DEV_STRING_PROP("clock-name-aon", "timers.aon")
+        ),
+    },
+    [OT_EG_SOC_DEV_AST] = {
+        .type = TYPE_OT_AST_EG,
+        .cfg = &ot_eg_soc_ast_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40480000u }
+        ),
+    },
+    [OT_EG_SOC_DEV_SENSOR_CTRL] = {
+        .type = TYPE_OT_SENSOR_EG,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40490000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 32),
+            OT_EG_SOC_GPIO_ALERT(1, 33)
+        ),
+    },
+    [OT_EG_SOC_DEV_SRAM_RET_CTRL] = {
+        .type = TYPE_OT_SRAM_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x40500000u },
+            { .base = 0x40600000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 34)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("otp-ctrl", OTP_CTRL),
+            OT_EG_SOC_DEVLINK("vmapper", VMAPPER)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("size", 0x1000u),
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "ret"),
+            IBEX_DEV_BOOL_PROP("ifetch", false)
+        ),
+    },
+    [OT_EG_SOC_DEV_FLASH_CTRL] = {
+        .type = TYPE_OT_FLASH,
+        .cfg = &ot_eg_soc_flash_ctrl_configure,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41000000u },
+            { .base = 0x41008000u },
+            { .base = 0x20000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 160),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 161),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 162),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 163),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(4, PLIC, 164),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(5, PLIC, 165),
+            OT_EG_SOC_GPIO_ALERT(0, 35),
+            OT_EG_SOC_GPIO_ALERT(1, 36),
+            OT_EG_SOC_GPIO_ALERT(2, 37),
+            OT_EG_SOC_GPIO_ALERT(3, 38),
+            OT_EG_SOC_GPIO_ALERT(4, 39)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("vmapper", VMAPPER)
+        ),
+    },
+    [OT_EG_SOC_DEV_AES] = {
+        .type = TYPE_OT_AES,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41100000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 42),
+            OT_EG_SOC_GPIO_ALERT(1, 43)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR),
+            OT_EG_SOC_DEVLINK("edn", EDN0)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "trans.aes"),
+            IBEX_DEV_UINT_PROP("edn-ep", 5u)
+        ),
+    },
+    [OT_EG_SOC_DEV_HMAC] = {
+        .type = TYPE_OT_HMAC,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41110000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 166),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 167),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 168),
+            OT_EG_SOC_GPIO_ALERT(0, 44)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "trans.hmac")
+        ),
+    },
+    [OT_EG_SOC_DEV_KMAC] = {
+        .type = TYPE_OT_KMAC,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41120000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 169),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 170),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 171),
+            OT_EG_SOC_GPIO_ALERT(0, 45),
+            OT_EG_SOC_GPIO_ALERT(1, 46)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR),
+            OT_EG_SOC_DEVLINK("edn", EDN0)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "trans.kmac"),
+            IBEX_DEV_UINT_PROP("edn-ep", 3u),
+            IBEX_DEV_UINT_PROP("num-app", 3u)
+        ),
+    },
+    [OT_EG_SOC_DEV_OTBN] = {
+        .type = TYPE_OT_OTBN,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41130000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 172),
+            OT_EG_SOC_GPIO_ALERT(0, 47),
+            OT_EG_SOC_GPIO_ALERT(1, 48)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("clock-src", CLKMGR),
+            OT_EG_SOC_DEVLINK("edn-u", EDN0),
+            OT_EG_SOC_DEVLINK("edn-r", EDN1)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("clock-name", "trans.otbn"),
+            IBEX_DEV_UINT_PROP("edn-u-ep", 6u),
+            IBEX_DEV_UINT_PROP("edn-r-ep", 0u)
+        ),
+    },
+    [OT_EG_SOC_DEV_KEYMGR] = {
+        .type = TYPE_OT_KEYMGR,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41140000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 173),
+            OT_EG_SOC_GPIO_ALERT(0, 49),
+            OT_EG_SOC_GPIO_ALERT(1, 50)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("aes", AES),
+            OT_EG_SOC_DEVLINK("edn", EDN0),
+            OT_EG_SOC_DEVLINK("flash_ctrl", FLASH_CTRL),
+            OT_EG_SOC_DEVLINK("kmac", KMAC),
+            OT_EG_SOC_DEVLINK("lc-ctrl", LC_CTRL),
+            OT_EG_SOC_DEVLINK("otbn", OTBN),
+            OT_EG_SOC_DEVLINK("otp-ctrl", OTP_CTRL),
+            OT_EG_SOC_DEVLINK("rom_ctrl", ROM_CTRL)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("edn-ep", 0u),
+            IBEX_DEV_UINT_PROP("kmac-app", 0u)
+        ),
+    },
+    [OT_EG_SOC_DEV_CSRNG] = {
+        .type = TYPE_OT_CSRNG,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41150000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 174),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 175),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 176),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 177),
+            OT_EG_SOC_GPIO_ALERT(0, 51),
+            OT_EG_SOC_GPIO_ALERT(1, 52)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("entropy-src", ENTROPY_SRC),
+            OT_EG_SOC_DEVLINK("otp-ctrl", OTP_CTRL)
+        ),
+    },
+    [OT_EG_SOC_DEV_ENTROPY_SRC] = {
+        .type = TYPE_OT_ENTROPY_SRC,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41160000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 178),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 179),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(2, PLIC, 180),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(3, PLIC, 181),
+            OT_EG_SOC_GPIO_ALERT(0, 53),
+            OT_EG_SOC_GPIO_ALERT(1, 54)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("noise-src", AST)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("version", 2)
+        ),
+    },
+    [OT_EG_SOC_DEV_EDN0] = {
+        .type = TYPE_OT_EDN,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41170000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 182),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 183),
+            OT_EG_SOC_GPIO_ALERT(0, 55),
+            OT_EG_SOC_GPIO_ALERT(1, 56)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("csrng", CSRNG)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("csrng-app", 0u)
+        ),
+    },
+    [OT_EG_SOC_DEV_EDN1] = {
+        .type = TYPE_OT_EDN,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x41180000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(0, PLIC, 184),
+            OT_EG_SOC_GPIO_SYSBUS_IRQ(1, PLIC, 185),
+            OT_EG_SOC_GPIO_ALERT(0, 57),
+            OT_EG_SOC_GPIO_ALERT(1, 58)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("csrng", CSRNG)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("csrng-app", 1u)
+        ),
+    },
+    [OT_EG_SOC_DEV_SRAM_MAIN_CTRL] = {
+        .type = TYPE_OT_SRAM_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x411c0000u },
+            { .base = 0x10000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 59)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("otp-ctrl", OTP_CTRL),
+            OT_EG_SOC_DEVLINK("vmapper", VMAPPER)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("size", SRAM_MAIN_SIZE),
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "ram"),
+            IBEX_DEV_BOOL_PROP("ifetch", true)
+        ),
+    },
+    [OT_EG_SOC_DEV_ROM_CTRL] = {
+        .type = TYPE_OT_ROM_CTRL,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x411e0000u },
+            { .base = 0x00008000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_SIGNAL(OT_ROM_CTRL_GOOD, 0, PWRMGR, \
+                                   OT_PWRMGR_ROM_GOOD, 0),
+            OT_EG_SOC_SIGNAL(OT_ROM_CTRL_DONE, 0, PWRMGR, \
+                                   OT_PWRMGR_ROM_DONE, 0),
+            OT_EG_SOC_GPIO_ALERT(0, 60)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("kmac", KMAC)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "rom"),
+            IBEX_DEV_UINT_PROP("size", 0x8000u),
+            IBEX_DEV_UINT_PROP("kmac-app", 2u)
+        ),
+    },
+    [OT_EG_SOC_DEV_IBEX_WRAPPER] = {
+        .type = TYPE_OT_IBEX_WRAPPER,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x411f0000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO_ALERT(0, 61),
+            OT_EG_SOC_GPIO_ALERT(1, 62),
+            OT_EG_SOC_GPIO_ALERT(2, 63),
+            OT_EG_SOC_GPIO_ALERT(3, 64)
+        ),
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("edn", EDN0),
+            OT_EG_SOC_DEVLINK("vmapper", VMAPPER)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("edn-ep", 7u),
+            IBEX_DEV_UINT_PROP("num-regions", OT_EG_IBEX_WRAPPER_NUM_REGIONS)
+        ),
+    },
+    [OT_EG_SOC_DEV_RV_DM] = {
+        .type = TYPE_PULP_RV_DM,
+        .memmap = MEMMAPENTRIES(
+            { .base = PULP_DM_BASE },
+            { .base = 0x41200000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 0),
+            OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 1),
+            OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 2),
+            OT_EG_SOC_DM_CONNECTION(OT_EG_SOC_DEV_DM, 3),
+            OT_EG_SOC_GPIO_ALERT(0, 40)
+        ),
+    },
+    [OT_EG_SOC_DEV_DM_LC_CTRL] = {
+        .type = TYPE_OT_DM_TL,
+        .link = IBEXDEVICELINKDEFS(
+            OT_EG_SOC_DEVLINK("dtm", LC_CTRL_DTM),
+            OT_EG_SOC_DEVLINK("tl_dev", LC_CTRL)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("dmi_addr", OT_EG_LC_CTRL_TAP_DMI_ADDR),
+            IBEX_DEV_UINT_PROP("dmi_size", OT_EG_LC_CTRL_TAP_DMI_SIZE),
+            IBEX_DEV_UINT_PROP("tl_addr", OT_EG_LC_CTRL_TAP_TL_ADDR),
+            IBEX_DEV_STRING_PROP("tl_as_name", OT_EG_LC_CTRL_TAP_AS)
+        )
+    },
+    [OT_EG_SOC_DEV_PLIC] = {
+        .type = TYPE_SIFIVE_PLIC,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x48000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO(1, HART, IRQ_M_EXT)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP("hart-config", "M"),
+            IBEX_DEV_UINT_PROP("hartid-base", 0u),
+            /* note: should always be max_irq + 1 */
+            IBEX_DEV_UINT_PROP("num-sources", 186u),
+            IBEX_DEV_UINT_PROP("num-priorities", 3u),
+            IBEX_DEV_UINT_PROP("priority-base", 0x0u),
+            IBEX_DEV_UINT_PROP("pending-base", 0x1000u),
+            IBEX_DEV_UINT_PROP("enable-base", 0x2000u),
+            IBEX_DEV_UINT_PROP("enable-stride", 32u),
+            IBEX_DEV_UINT_PROP("context-base", 0x200000u),
+            IBEX_DEV_UINT_PROP("context-stride", 8u),
+            IBEX_DEV_UINT_PROP("aperture-size", 0x4000000u)
+        ),
+    },
+    [OT_EG_SOC_DEV_PLIC_EXT] = {
+        .type = TYPE_OT_PLIC_EXT,
+        .memmap = MEMMAPENTRIES(
+            { .base = 0x4c000000u }
+        ),
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_GPIO(0, HART, IRQ_M_SOFT),
+            OT_EG_SOC_GPIO_ALERT(0, 41)
+        ),
+    },
+    [OT_EG_SOC_DEV_VMAPPER] = {
+        .type = TYPE_OT_VMAPPER,
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_STRING_PROP(OT_COMMON_DEV_ID, "soc"),
+            IBEX_DEV_UINT_PROP("trans_count", OT_EG_IBEX_WRAPPER_NUM_REGIONS)
+        ),
+    },
+    /* IRQ splitters */
+    [OT_EG_SOC_SPLITTER_LC_HW_DEBUG] = {
+        .type = TYPE_SPLIT_IRQ,
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_S2D(0, SRAM_MAIN_CTRL, OT_SRAM_CTRL_HW_DEBUG_EN, 0),
+            OT_EG_SOC_S2D(1, SRAM_RET_CTRL, OT_SRAM_CTRL_HW_DEBUG_EN, 0)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("num-lines", 2u) /* @todo to be changed */
+        )
+    },
+    [OT_EG_SOC_SPLITTER_LC_ESCALATE] = {
+        .type = TYPE_SPLIT_IRQ,
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_S2D(0, OTP_CTRL, OT_LC_BROADCAST,
+                          OT_OTP_LC_ESCALATE_EN),
+            OT_EG_SOC_S2D(1, FLASH_CTRL, OT_LC_BROADCAST,
+                          OT_FLASH_LC_ESCALATE_EN)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("num-lines", 2u) /* @todo to be changed */
+        )
+    },
+    [OT_EG_SOC_SPLITTER_LC_SEED_HW_RD] = {
+        .type = TYPE_SPLIT_IRQ,
+        .gpio = IBEXGPIOCONNDEFS(
+          OT_EG_SOC_S2D(0, OTP_CTRL, OT_LC_BROADCAST,
+                        OT_OTP_LC_SEED_HW_RD_EN),
+          OT_EG_SOC_S2D(1, FLASH_CTRL, OT_LC_BROADCAST,
+                        OT_FLASH_LC_SEED_HW_RD_EN)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("num-lines", 2u)
+        )
+    },
+    [OT_EG_SOC_SPLITTER_LC_CREATOR_SEED_SW_RW] = {
+        .type = TYPE_SPLIT_IRQ,
+        .gpio = IBEXGPIOCONNDEFS(
+            OT_EG_SOC_S2D(0, OTP_CTRL, OT_LC_BROADCAST,
+                          OT_OTP_LC_CREATOR_SEED_SW_RW_EN),
+            OT_EG_SOC_S2D(1, FLASH_CTRL, OT_LC_BROADCAST,
+                          OT_FLASH_LC_CREATOR_SEED_SW_RW_EN)
+        ),
+        .prop = IBEXDEVICEPROPDEFS(
+            IBEX_DEV_UINT_PROP("num-lines", 2u)
+        )
+    },
+    /* clang-format on */
+};
+
+/* ------------------------------------------------------------------------ */
+/* Type definitions */
+/* ------------------------------------------------------------------------ */
+
+/* Temporary storage for reset iteration */
+typedef struct {
+    OtEGSoCState *soc;
+    ResettableChildCallback cb; /* the callback to call for each child */
+    void *opaque; /* opaque data for the callback */
+    ResetType type; /* type of reset */
+} OtEgSocChildReset;
+
+struct OtEGSoCClass {
+    DeviceClass parent_class;
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
+struct OtEGSoCState {
+    SysBusDevice parent_obj;
+
+    BusState *ot_bus; /* private OpenTitan bus */
+
+    DeviceState **devices;
+};
+
+struct OtEGBoardState {
+    DeviceState parent_obj;
+
+    DeviceState **devices;
+
+    /* optional SPI data flash (type of device) */
+    char *spiflash[OT_EG_MTD_SPI_COUNT];
+};
+
+struct OtEGMachineState {
+    MachineState parent_obj;
+
+    ResettableState reset;
+
+    bool no_epmp_cfg;
+    bool ignore_elf_entry;
+    bool verilator;
+};
+
+struct OtEGMachineClass {
+    MachineClass parent_class;
+    ResettablePhases parent_phases;
+};
+
+/* ------------------------------------------------------------------------ */
+/* Device Configuration */
+/* ------------------------------------------------------------------------ */
+
+static void ot_eg_soc_ast_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                    DeviceState *parent)
+{
+    (void)def;
+    (void)parent;
+
+    bool verilator_mode =
+        object_property_get_bool(qdev_get_machine(), "verilator", NULL);
+    const char *clock_cfg;
+    if (!verilator_mode) {
+        /* EarlGrey/CW310 */
+        clock_cfg = "main:24000000,io:24000000,usb:48000000,aon:250000";
+    } else {
+        clock_cfg = "main:500000,io:500000,usb:500000,aon:125000";
+    }
+
+    qdev_prop_set_string(dev, "topclocks", clock_cfg);
+}
+
+static void ot_eg_soc_dm_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                   DeviceState *parent)
+{
+    (void)def;
+    (void)parent;
+
+    QList *hart = qlist_new();
+    qlist_append_int(hart, 0);
+    qdev_prop_set_array(dev, "hart", hart);
+
+    RISCVDMMemAttrs pulp_attrs = {
+        .attrs = {
+            .requester_id = PULP_RV_DM_REQUESTER_ID,
+        },
+    };
+    qdev_prop_set_uint64(dev, "mta_dm", pulp_attrs.value);
+}
+
+static void ot_eg_soc_flash_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    DriveInfo *dinfo = drive_get(IF_MTD, OT_EG_MTD_EFLASH, 0);
+    (void)def;
+    (void)parent;
+
+    if (dinfo) {
+        qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo),
+                                &error_fatal);
+    }
+}
+
+static void ot_eg_soc_hart_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                     DeviceState *parent)
+{
+    OtEGMachineState *ms = RISCV_OT_EG_MACHINE(qdev_get_machine());
+    QList *pmp_cfg, *pmp_addr;
+    (void)def;
+    (void)parent;
+
+    if (ms->no_epmp_cfg) {
+        /* skip default PMP config */
+        return;
+    }
+
+    pmp_cfg = qlist_new();
+    for (unsigned ix = 0; ix < ARRAY_SIZE(ot_eg_pmp_cfgs); ix++) {
+        qlist_append_int(pmp_cfg, ot_eg_pmp_cfgs[ix]);
+    }
+    qdev_prop_set_array(dev, "pmp_cfg", pmp_cfg);
+
+    pmp_addr = qlist_new();
+    for (unsigned ix = 0; ix < ARRAY_SIZE(ot_eg_pmp_addrs); ix++) {
+        qlist_append_int(pmp_addr, ot_eg_pmp_addrs[ix]);
+    }
+    qdev_prop_set_array(dev, "pmp_addr", pmp_addr);
+
+    qdev_prop_set_uint64(dev, "mseccfg", (uint64_t)OT_EG_MSECCFG);
+}
+
+static void ot_eg_soc_otp_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    DriveInfo *dinfo = drive_get(IF_PFLASH, OT_EG_PFLASH_OTP, 0);
+    (void)def;
+    (void)parent;
+
+    if (dinfo) {
+        qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo),
+                                &error_fatal);
+    }
+}
+
+static void ot_eg_soc_tap_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)parent;
+    (void)def;
+
+    Chardev *chr;
+
+    chr = ibex_get_chardev_by_id("taprbb");
+    if (chr) {
+        qdev_prop_set_chr(dev, "chardev", chr);
+    }
+}
+
+static void ot_eg_soc_lc_ctrl_tap_ctrl_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)parent;
+    (void)def;
+
+    Chardev *chr;
+
+    chr = ibex_get_chardev_by_id("taprbb-lc-ctrl");
+    if (chr) {
+        qdev_prop_set_chr(dev, "chardev", chr);
+    }
+}
+
+static void ot_eg_soc_spi_device_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)parent;
+    (void)def;
+
+    Chardev *chr;
+
+    chr = ibex_get_chardev_by_id("spidev");
+    if (chr) {
+        qdev_prop_set_chr(dev, "chardev", chr);
+    }
+}
+
+static void ot_eg_soc_uart_configure(DeviceState *dev, const IbexDeviceDef *def,
+                                     DeviceState *parent)
+{
+    (void)def;
+    (void)parent;
+    qdev_prop_set_chr(dev, "chardev", serial_hd(IBEX_GET_INSTANCE_NUM(def)));
+}
+
+static void ot_eg_soc_usbdev_configure(
+    DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
+{
+    (void)parent;
+    (void)def;
+
+    Chardev *chr;
+
+    chr = ibex_get_chardev_by_id("usbdev-cmd");
+    if (chr) {
+        qdev_prop_set_chr(dev, "chardev-cmd", chr);
+    }
+    chr = ibex_get_chardev_by_id("usbdev-host");
+    if (chr) {
+        qdev_prop_set_chr(dev, "chardev-usb", chr);
+    }
+}
+
+/* ------------------------------------------------------------------------ */
+/* SoC */
+/* ------------------------------------------------------------------------ */
+
+static int ot_eg_soc_reset_child(Object *child, void *opaque)
+{
+    OtEgSocChildReset *cr = opaque;
+
+    if (object_dynamic_cast(child, TYPE_SYS_BUS_DEVICE)) {
+        /*
+         * sysbus devices being connected to the OT bus, and the bus performing
+         * its own children traversal to perform reset, skip this kind of
+         * devices to avoid resetting each of them twice
+         */
+        return 0;
+    }
+
+    if (object_dynamic_cast(child, TYPE_RESETTABLE_INTERFACE)) {
+        cr->cb(child, cr->opaque, cr->type);
+    }
+
+    /* resume with next child */
+    return 0;
+}
+
+static void ot_eg_soc_reset_child_foreach(
+    Object *obj, ResettableChildCallback cb, void *opaque, ResetType type)
+{
+    OtEGSoCState *s = RISCV_OT_EG_SOC(obj);
+
+    OtEgSocChildReset r = {
+        .soc = s,
+        .cb = cb,
+        .opaque = opaque,
+        .type = type,
+    };
+
+    /* execute reset stage for each child */
+    object_child_foreach(obj, &ot_eg_soc_reset_child, &r);
+}
+
+static void ot_eg_soc_hw_reset(void *opaque, int irq, int level)
+{
+    OtEGSoCState *s = opaque;
+
+    g_assert(irq == 0);
+
+    if (level) {
+        resettable_reset(OBJECT(s), RESET_TYPE_COLD);
+    }
+}
+
+static void ot_eg_soc_reset_hold(Object *obj, ResetType type)
+{
+    OtEGSoCClass *c = RISCV_OT_EG_SOC_GET_CLASS(obj);
+    OtEGSoCState *s = RISCV_OT_EG_SOC(obj);
+
+    if (c->parent_phases.hold) {
+        c->parent_phases.hold(obj, type);
+    }
+
+    /*
+     * This function is called after all children have been reset_hold,
+     * before any child has been reset_exit.
+     *
+     * Power-On-Reset: leave hart disabled on reset
+     * PowerManager takes care of managing Ibex reset when ready
+     */
+    CPUState *cs = CPU(s->devices[OT_EG_SOC_DEV_HART]);
+    cs->disabled = true;
+}
+
+static void ot_eg_soc_reset_exit(Object *obj, ResetType type)
+{
+    OtEGSoCClass *c = RISCV_OT_EG_SOC_GET_CLASS(obj);
+    OtEGSoCState *s = RISCV_OT_EG_SOC(obj);
+
+    if (c->parent_phases.exit) {
+        c->parent_phases.exit(obj, type);
+    }
+
+    /* Kick off ROM check and boot */
+    object_property_set_bool(OBJECT(s->devices[OT_EG_SOC_DEV_ROM_CTRL]), "load",
+                             true, &error_fatal);
+}
+
+static void ot_eg_soc_realize(DeviceState *dev, Error **errp)
+{
+    OtEGSoCState *s = RISCV_OT_EG_SOC(dev);
+    (void)errp;
+
+    CPUState *cpu = CPU(s->devices[OT_EG_SOC_DEV_HART]);
+    cpu->memory = get_system_memory();
+    cpu->cpu_index = 0;
+
+    /* Create the private bus on which all OpenTitan IPs are connected */
+    s->ot_bus = BUS(object_new(TYPE_SYSTEM_BUS));
+    qbus_init(s->ot_bus, sizeof(*s->ot_bus), TYPE_SYSTEM_BUS, DEVICE(s),
+              "ot.bus");
+
+    /* Link, define properties and realize devices, then connect GPIOs */
+    ot_common_configure_devices_with_id(s->devices, s->ot_bus, "soc", false,
+                                        ot_eg_soc_devices,
+                                        ARRAY_SIZE(ot_eg_soc_devices));
+
+    MemoryRegion *lc_ctrl_tap_mr = g_new0(MemoryRegion, 1u);
+    memory_region_init(lc_ctrl_tap_mr, OBJECT(dev), OT_EG_LC_CTRL_TAP_XBAR,
+                       OT_EG_LC_CTRL_TAP_TL_SIZE);
+
+    MemoryRegion *mrs[IBEX_MEMMAP_REGIDX_COUNT] = {
+        [OT_EG_DEFAULT_MEMORY_REGION] = get_system_memory(),
+        [OT_EG_LC_CTRL_TAP_MEMORY_REGION] = lc_ctrl_tap_mr,
+    };
+    ibex_map_devices_mask(s->devices, mrs, ot_eg_soc_devices,
+                          ARRAY_SIZE(ot_eg_soc_devices),
+                          IBEX_MEMMAP_MAKE_REG_MASK(
+                              OT_EG_DEFAULT_MEMORY_REGION) |
+                              IBEX_MEMMAP_MAKE_REG_MASK(
+                                  OT_EG_LC_CTRL_TAP_MEMORY_REGION));
+    Object *oas;
+    AddressSpace *as = g_new0(AddressSpace, 1u);
+    address_space_init(as, lc_ctrl_tap_mr, OT_EG_LC_CTRL_TAP_AS);
+    oas = object_new(TYPE_OT_ADDRESS_SPACE);
+    object_property_add_child(OBJECT(dev), as->name, oas);
+    ot_address_space_set(OT_ADDRESS_SPACE(oas), as);
+
+    qdev_connect_gpio_out_named(DEVICE(s->devices[OT_EG_SOC_DEV_RSTMGR]),
+                                OT_RSTMGR_SOC_RST, 0,
+                                qdev_get_gpio_in_named(DEVICE(s),
+                                                       OT_EG_SOC_RST_REQ, 0));
+
+    ot_common_check_rom_configuration();
+
+    /* load kernel if provided */
+    ibex_load_kernel(cpu);
+}
+
+static void ot_eg_soc_init(Object *obj)
+{
+    OtEGSoCState *s = RISCV_OT_EG_SOC(obj);
+
+    s->devices = ibex_create_devices(ot_eg_soc_devices,
+                                     ARRAY_SIZE(ot_eg_soc_devices), DEVICE(s));
+
+    qdev_init_gpio_in_named(DEVICE(obj), &ot_eg_soc_hw_reset, OT_EG_SOC_RST_REQ,
+                            1);
+}
+
+static void ot_eg_soc_class_init(ObjectClass *oc, const void *data)
+{
+    OtEGSoCClass *sc = RISCV_OT_EG_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    ResettableClass *rc = RESETTABLE_CLASS(dc);
+    (void)data;
+
+    resettable_class_set_parent_phases(rc, NULL, &ot_eg_soc_reset_hold,
+                                       &ot_eg_soc_reset_exit,
+                                       &sc->parent_phases);
+    rc->child_foreach = &ot_eg_soc_reset_child_foreach;
+    dc->realize = &ot_eg_soc_realize;
+    dc->user_creatable = false;
+}
+
+static const TypeInfo ot_eg_soc_type_info = {
+    .name = TYPE_RISCV_OT_EG_SOC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OtEGSoCState),
+    .instance_init = &ot_eg_soc_init,
+    .class_init = &ot_eg_soc_class_init,
+    .class_size = sizeof(OtEGSoCClass),
+};
+
+static void ot_eg_soc_register_types(void)
+{
+    type_register_static(&ot_eg_soc_type_info);
+}
+
+type_init(ot_eg_soc_register_types);
+
+/* ------------------------------------------------------------------------ */
+/* Board */
+/* ------------------------------------------------------------------------ */
+
+static void ot_eg_board_set_spiflash0(Object *obj, const char *value,
+                                      Error **errp)
+{
+    OtEGBoardState *board = RISCV_OT_EG_BOARD(obj);
+    (void)errp;
+
+    g_free(board->spiflash[OT_EG_MTD_SPI0]);
+    board->spiflash[OT_EG_MTD_SPI0] = g_strdup(value);
+}
+
+static void ot_eg_board_set_spiflash1(Object *obj, const char *value,
+                                      Error **errp)
+{
+    OtEGBoardState *board = RISCV_OT_EG_BOARD(obj);
+    (void)errp;
+
+    g_free(board->spiflash[OT_EG_MTD_SPI1]);
+    board->spiflash[OT_EG_MTD_SPI1] = g_strdup(value);
+}
+
+static void ot_eg_board_child_foreach(Object *obj, ResettableChildCallback cb,
+                                      void *opaque, ResetType type)
+{
+    OtEGBoardState *s = RISCV_OT_EG_BOARD(obj);
+
+    for (unsigned ix = 0; ix < OT_EG_BOARD_DEV_COUNT; ix++) {
+        /* flash devices are optional */
+        if (s->devices[ix]) {
+            cb(OBJECT(s->devices[ix]), opaque, type);
+        }
+    }
+}
+
+static void ot_eg_board_realize(DeviceState *dev, Error **errp)
+{
+    OtEGBoardState *board = RISCV_OT_EG_BOARD(dev);
+
+    DeviceState *soc = board->devices[OT_EG_BOARD_DEV_SOC];
+    object_property_add_child(OBJECT(board), "soc", OBJECT(soc));
+
+    BusState *bus = sysbus_get_default();
+    qdev_realize_and_unref(soc, bus, &error_fatal);
+
+    for (unsigned fix = 0; fix < OT_EG_MTD_SPI_COUNT; fix++) {
+        const char *flash_type = board->spiflash[OT_EG_MTD_SPI0 + fix];
+        /*
+         * skip this flash slot if no device type has been defined on the QEMU
+         * command line
+         */
+        if (!flash_type) {
+            continue;
+        }
+
+        /* qdev_new aborts if the specified device is not supported */
+        DeviceState *flash = qdev_new(flash_type);
+
+        if (!object_dynamic_cast(OBJECT(flash), TYPE_M25P80)) {
+            error_setg(errp, "%s is not a SPI dataflash device", flash_type);
+        }
+
+        /*
+         * retrieve the SPI host controller bus. Although each SPI host only
+         * has one SPI bus, each bus name in QEMU needs to be unique. The SPI
+         * host controller uses its bus-num property as a suffix for naming its
+         * bus
+         */
+        DeviceState *spihost =
+            RISCV_OT_EG_SOC(soc)->devices[OT_EG_SOC_DEV_SPI_HOST0 + fix];
+        char *busname = g_strdup_printf("spi%u", fix);
+        BusState *spibus = qdev_get_child_bus(spihost, busname);
+        g_assert(spibus);
+
+        /*
+         * if a "drive" property for this bus/unit pair is defined on the QEMU
+         * command line, assigned it to the flash device
+         */
+        DriveInfo *dinfo = drive_get(IF_MTD, (int)fix, 0);
+        if (dinfo) {
+            qdev_prop_set_drive_err(DEVICE(flash), "drive",
+                                    blk_by_legacy_dinfo(dinfo), &error_fatal);
+        }
+
+        /* the flash device is a child of the board */
+        char *flashname = g_strdup_printf("dataflash%u", fix);
+        object_property_add_child(OBJECT(board), flashname, OBJECT(flash));
+        /* connect it as a peripheral of the SPI host controller bus */
+        ssi_realize_and_unref(flash, SSI_BUS(spibus), errp);
+
+        board->devices[OT_EG_BOARD_DEV_FLASH0 + fix] = flash;
+
+        /*
+         * finally, connect the first CS line of the SPI controller to control
+         * to select this SPI flash device
+         */
+        qemu_irq cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
+        qdev_connect_gpio_out_named(spihost, SSI_GPIO_CS, 0, cs);
+
+        g_free(flashname);
+        g_free(busname);
+    }
+}
+
+static void ot_eg_board_init(Object *obj)
+{
+    object_property_add_str(obj, "spiflash0", NULL, &ot_eg_board_set_spiflash0);
+    object_property_set_description(obj, "spiflash0",
+                                    "SPI dataflash on SPI0 bus");
+    object_property_add_str(obj, "spiflash1", NULL, &ot_eg_board_set_spiflash1);
+    object_property_set_description(obj, "spiflash1",
+                                    "SPI dataflash on SPI1 bus");
+
+    OtEGBoardState *s = RISCV_OT_EG_BOARD(obj);
+
+    s->devices = g_new0(DeviceState *, OT_EG_BOARD_DEV_COUNT);
+    s->devices[OT_EG_BOARD_DEV_SOC] = qdev_new(TYPE_RISCV_OT_EG_SOC);
+}
+
+static void ot_eg_board_class_init(ObjectClass *oc, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    (void)data;
+
+    dc->realize = &ot_eg_board_realize;
+
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
+    rc->child_foreach = &ot_eg_board_child_foreach;
+}
+
+static const TypeInfo ot_eg_board_type_info = {
+    .name = TYPE_RISCV_OT_EG_BOARD,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(OtEGBoardState),
+    .instance_init = &ot_eg_board_init,
+    .class_init = &ot_eg_board_class_init,
+};
+
+static void ot_eg_board_register_types(void)
+{
+    type_register_static(&ot_eg_board_type_info);
+}
+
+type_init(ot_eg_board_register_types);
+
+/* ------------------------------------------------------------------------ */
+/* Machine */
+/* ------------------------------------------------------------------------ */
+
+static bool ot_eg_machine_get_no_epmp_cfg(Object *obj, Error **errp)
+{
+    OtEGMachineState *s = RISCV_OT_EG_MACHINE(obj);
+    (void)errp;
+
+    return s->no_epmp_cfg;
+}
+
+static void ot_eg_machine_set_no_epmp_cfg(Object *obj, bool value, Error **errp)
+{
+    OtEGMachineState *s = RISCV_OT_EG_MACHINE(obj);
+    (void)errp;
+
+    s->no_epmp_cfg = value;
+}
+
+static bool ot_eg_machine_get_ignore_elf_entry(Object *obj, Error **errp)
+{
+    OtEGMachineState *s = RISCV_OT_EG_MACHINE(obj);
+    (void)errp;
+
+    return s->ignore_elf_entry;
+}
+
+static void
+ot_eg_machine_set_ignore_elf_entry(Object *obj, bool value, Error **errp)
+{
+    OtEGMachineState *s = RISCV_OT_EG_MACHINE(obj);
+    (void)errp;
+
+    s->ignore_elf_entry = value;
+}
+
+static bool ot_eg_machine_get_verilator(Object *obj, Error **errp)
+{
+    OtEGMachineState *s = RISCV_OT_EG_MACHINE(obj);
+    (void)errp;
+
+    return s->verilator;
+}
+
+static void ot_eg_machine_set_verilator(Object *obj, bool value, Error **errp)
+{
+    OtEGMachineState *s = RISCV_OT_EG_MACHINE(obj);
+    (void)errp;
+
+    s->verilator = value;
+}
+
+static ResettableState *ot_eg_machine_get_reset_state(Object *obj)
+{
+    OtEGMachineState *s = RISCV_OT_EG_MACHINE(obj);
+
+    return &s->reset;
+}
+
+static void ot_eg_machine_child_foreach(Object *obj, ResettableChildCallback cb,
+                                        void *opaque, ResetType type)
+{
+    Object *board = object_property_get_link(obj, "board", &error_fatal);
+
+    cb(board, opaque, type);
+}
+
+static void ot_eg_machine_reset(MachineState *ms, ResetType reason)
+{
+    OtEGMachineState *s = RISCV_OT_EG_MACHINE(ms);
+
+    g_assert(reason == RESET_TYPE_COLD);
+
+    resettable_reset(OBJECT(s), reason);
+}
+
+static void ot_eg_machine_instance_init(Object *obj)
+{
+    OtEGMachineState *s = RISCV_OT_EG_MACHINE(obj);
+
+    s->no_epmp_cfg = false;
+    object_property_add_bool(obj, "no-epmp-cfg", &ot_eg_machine_get_no_epmp_cfg,
+                             &ot_eg_machine_set_no_epmp_cfg);
+    object_property_set_description(obj, "no-epmp-cfg",
+                                    "Skip default ePMP configuration");
+    object_property_add_bool(obj, "ignore-elf-entry",
+                             &ot_eg_machine_get_ignore_elf_entry,
+                             &ot_eg_machine_set_ignore_elf_entry);
+    object_property_set_description(obj, "ignore-elf-entry",
+                                    "Do not set vCPU PC with ELF entry point");
+    object_property_add_bool(obj, "verilator", &ot_eg_machine_get_verilator,
+                             &ot_eg_machine_set_verilator);
+    object_property_set_description(obj, "verilator", "Use Verilator clocks");
+}
+
+static void ot_eg_machine_init(MachineState *state)
+{
+    DeviceState *dev = qdev_new(TYPE_RISCV_OT_EG_BOARD);
+
+    object_property_add_child(OBJECT(state), "board", OBJECT(dev));
+
+    qdev_realize(dev, NULL, &error_fatal);
+}
+
+static void ot_eg_machine_class_init(ObjectClass *oc, const void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    (void)data;
+
+    mc->desc = "RISC-V Board compatible with OpenTitan EarlGrey FPGA platform";
+    mc->init = ot_eg_machine_init;
+    mc->reset = &ot_eg_machine_reset;
+    mc->max_cpus = 1u;
+    mc->default_cpus = 1u;
+
+    /*
+     * Implement the resettable interface to ensure the proper initialization
+     * sequence.
+     */
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+    rc->get_state = &ot_eg_machine_get_reset_state;
+    rc->child_foreach = &ot_eg_machine_child_foreach;
+}
+
+static const TypeInfo ot_eg_machine_type_info = {
+    .name = TYPE_RISCV_OT_EG_MACHINE,
+    .parent = TYPE_MACHINE,
+    .instance_size = sizeof(OtEGMachineState),
+    .instance_init = &ot_eg_machine_instance_init,
+    .class_init = &ot_eg_machine_class_init,
+    .interfaces = (InterfaceInfo[]){ { TYPE_RESETTABLE_INTERFACE }, {} },
+};
+
+static void ot_eg_machine_register_types(void)
+{
+    type_register_static(&ot_eg_machine_type_info);
+}
+
+type_init(ot_eg_machine_register_types);
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 3e7f4411727d6..0a3550c41b0b4 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -118,7 +118,8 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
         SHAKTI_C_PLIC_ENABLE_STRIDE,
         SHAKTI_C_PLIC_CONTEXT_BASE,
         SHAKTI_C_PLIC_CONTEXT_STRIDE,
-        shakti_c_memmap[SHAKTI_C_PLIC].size);
+        shakti_c_memmap[SHAKTI_C_PLIC].size,
+        false);
 
     riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
         0, 1, false);
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 7baed1958e05d..fe09da15fe9f8 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -219,7 +219,8 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_E_PLIC_ENABLE_STRIDE,
         SIFIVE_E_PLIC_CONTEXT_BASE,
         SIFIVE_E_PLIC_CONTEXT_STRIDE,
-        memmap[SIFIVE_E_DEV_PLIC].size);
+        memmap[SIFIVE_E_DEV_PLIC].size,
+        false);
     riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
         0, ms->smp.cpus, false);
     riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index a7492aa27a46c..7de4dbe6077a8 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -842,7 +842,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_U_PLIC_ENABLE_STRIDE,
         SIFIVE_U_PLIC_CONTEXT_BASE,
         SIFIVE_U_PLIC_CONTEXT_STRIDE,
-        memmap[SIFIVE_U_DEV_PLIC].size);
+        memmap[SIFIVE_U_DEV_PLIC].size,
+        false);
     g_free(plic_hart_config);
     sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
index b50b14a65422c..2ae2269cf3d05 100644
--- a/hw/riscv/trace-events
+++ b/hw/riscv/trace-events
@@ -24,3 +24,49 @@ riscv_iommu_hpm_incr_ctr(uint64_t cntr_val) "cntr_val 0x%"PRIx64
 riscv_iommu_hpm_iocntinh_cy(bool prev_cy_inh) "prev_cy_inh %d"
 riscv_iommu_hpm_cycle_write(uint32_t ovf, uint64_t val) "ovf 0x%x val 0x%"PRIx64
 riscv_iommu_hpm_evt_write(uint32_t ctr_idx, uint32_t ovf, uint64_t val) "ctr_idx 0x%x ovf 0x%x val 0x%"PRIx64
+
+# dm.c
+
+riscv_dm_aarsize_error(const char *soc, unsigned aarsize) "%s: aarsize %u not supported"
+riscv_dm_absdata(const char *soc, const char *op, unsigned woffset, unsigned wcount, uint64_t value, uint32_t res) "%s: %s: @ %u[%u] = 0x%08" PRIx64 ": res %u"
+riscv_dm_abstract_cmd(const char *soc, uint32_t addr, uint32_t inst) "%s: [%x]: %08x"
+riscv_dm_access_register(const char *soc, const char *msg, const char *regname, uint32_t value) "%s: %s: %s (%x)"
+riscv_dm_busy(const char *soc, bool busy) "%s: busy: %u"
+riscv_dm_change_hart(const char *soc, const char *msg, unsigned hart, bool cpuhalted, bool cpurunning, bool cpustopped, bool resack) "%s: [%s] hart#%u h:%u r:%u s:%u A:%u"
+riscv_dm_cs(const char *soc, bool enable) "%s: debug_cs: %u"
+riscv_dm_dmstatus_read(const char *soc, uint32_t val, bool unavail, bool halted, bool cpuhalted, bool running, bool cpurunning, bool resack, bool cpustopped, uint32_t pc) "%s: 0x%08x U:%u H:%u(%u) R:%u(%u) A:%u S:%u @ %08x"
+riscv_dm_error(const char *soc, const char *func, int line, const char *msg) "%s: %s:%d %s"
+riscv_dm_halted(const char *soc, unsigned hart, uint64_t pc, const char *cause) "%s hart #%u halted @ 0x%08" PRIx64 " as %s"
+riscv_dm_hart_reset(const char *soc, unsigned cpuid, unsigned hartid, const char *msg) "%s {%u}: hartid:%u: %s"
+riscv_dm_hart_state(const char *soc, unsigned hartsel, const char *msg) "%s: hart #%u %s"
+riscv_dm_info(const char *soc, const char *func, int line, const char *msg, uint32_t val) "%s: %s:%d %s 0x%08x"
+riscv_dm_progbuf(const char *soc, const char *op, unsigned woffset, uint64_t value, uint32_t res) "%s: %s: @ %u = 0x%08" PRIx64 ": res %u"
+riscv_dm_reg_capture(const char *soc, const char *name, uint64_t addr, uint32_t value) "%s: %s @ %02" PRIx64 " = 0x%08x"
+riscv_dm_reg_update(const char *soc, const char *name, uint32_t addr, uint32_t value, const char * op, int ret) "%s: %s @ %02x = 0x%08x, %s res %d"
+riscv_dm_reset(const char *soc, const char *msg) "%s: %s"
+riscv_dm_resume_hart(const char *soc, bool sstep, const char *cause) "%s: single-step: %u, cause %s"
+riscv_dm_sbcs_write(const char *soc, bool err, bool busyerr, unsigned access, bool rdonaddr, bool rdondata, bool autoinc) "%s: err#:%u busy#:%u %uB rdonaddr:%u rdondata: %u autoinc:%u"
+riscv_dm_sbaddr_write(const char *soc, unsigned slot, uint32_t address) "%s: @[%u] 0x%08x"
+riscv_dm_sbdata_read(const char *soc, unsigned slot, uint32_t data) "%s: @[%u] 0x%08x"
+riscv_dm_sbdata_write(const char *soc, unsigned slot, uint32_t data) "%s: @[%u] 0x%08x"
+riscv_dm_status(const char *soc, int cpuid, const char *status) "%s {%d}: %s"
+riscv_dm_sysbus_data_read(const char *soc, uint64_t address, unsigned size, uint64_t val64, unsigned res) "%s: 0x%08" PRIx64 "[+%u] <- %08" PRIx64 ": res %u"
+riscv_dm_sysbus_data_write(const char *soc, uint64_t address, unsigned size, uint64_t val64, unsigned res) "%s: 0x%08" PRIx64 "[+%u] -> %08" PRIx64 ": res %u"
+riscv_dm_unavailable(const char *soc, int cpuid) "%s {%d}"
+riscv_dm_unavailable_hart_control(const char *soc, unsigned hartsel, const char *action) "%s: #%u cannot %s as unavailable"
+
+# dtm.c
+
+riscv_dtm_dtmcs_reset(void) ""
+riscv_dtm_enable_dm(const char *cls, bool enable, bool update) "%s: en:%u upd:%u"
+riscv_dtm_error(const char *func, int line, const char *msg) "%s:%d %s"
+riscv_dtm_info(const char *func, int line, const char *msg, uint32_t val) "%s:%d %s 0x%08x"
+riscv_dtm_register_dm(const char *cls, unsigned count, uint64_t first, uint64_t last, bool enabled, bool ok) "%s: #%u 0x%" PRIx64 "..0x%" PRIx64 ": enabled:%u tap:%u"
+riscv_dtm_set_next_dm(const char *fromcls, uint32_t fromaddr, const char *tocls, uint32_t toaddr) "%s @ 0x%x next_dm %s @ 0x%x"
+riscv_dtm_tap_dmi_capture(uint32_t addr) "0x%x"
+riscv_dtm_tap_dmi_update(uint32_t addr, const char *dir) "0x%x %s"
+riscv_dtm_vm_state_change(const char *name, unsigned state) "VM state: %s[%u]"
+
+# ibex_common.c
+
+ibex_create_device(const char *pname, const char *name) "%s.%s"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 17909206c7ef8..4ad9c3feeaf37 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1299,7 +1299,8 @@ static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
              VIRT_PLIC_ENABLE_BASE, VIRT_PLIC_ENABLE_STRIDE,
              VIRT_PLIC_CONTEXT_BASE,
              VIRT_PLIC_CONTEXT_STRIDE,
-             memmap[VIRT_PLIC].size);
+             memmap[VIRT_PLIC].size,
+             false);
 }
 
 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
diff --git a/hw/ssi/Kconfig b/hw/ssi/Kconfig
index 1bd56463c1e0c..bd193700edc14 100644
--- a/hw/ssi/Kconfig
+++ b/hw/ssi/Kconfig
@@ -21,6 +21,10 @@ config STM32F2XX_SPI
     bool
     select SSI
 
+config IBEX_SPI_HOST
+    bool
+    select SSI
+
 config BCM2835_SPI
     bool
     select SSI
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
index 6afb1ea200121..a3ba319280d6d 100644
--- a/hw/ssi/meson.build
+++ b/hw/ssi/meson.build
@@ -10,6 +10,6 @@ system_ss.add(when: 'CONFIG_XILINX_SPI', if_true: files('xilinx_spi.c'))
 system_ss.add(when: 'CONFIG_XILINX_SPIPS', if_true: files('xilinx_spips.c'))
 system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-ospi.c'))
 system_ss.add(when: 'CONFIG_IMX', if_true: files('imx_spi.c'))
-system_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_spi_host.c'))
+system_ss.add(when: 'CONFIG_IBEX_SPI_HOST', if_true: files('ibex_spi_host.c'))
 system_ss.add(when: 'CONFIG_BCM2835_SPI', if_true: files('bcm2835_spi.c'))
 system_ss.add(when: 'CONFIG_PNV_SPI', if_true: files('pnv_spi.c'))
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
index d0de640fe6428..5462977885919 100644
--- a/hw/ssi/ssi.c
+++ b/hw/ssi/ssi.c
@@ -24,9 +24,6 @@ struct SSIBus {
     BusState parent_obj;
 };
 
-#define TYPE_SSI_BUS "SSI"
-OBJECT_DECLARE_SIMPLE_TYPE(SSIBus, SSI_BUS)
-
 DeviceState *ssi_get_cs(SSIBus *bus, uint8_t cs_index)
 {
     BusState *b = BUS(bus);
diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig
index b3d823ce2c394..2fdefd0d1fcfd 100644
--- a/hw/timer/Kconfig
+++ b/hw/timer/Kconfig
@@ -65,3 +65,6 @@ config STELLARIS_GPTM
 
 config AVR_TIMER16
     bool
+
+config IBEX_TIMER
+    bool
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index c7320ef30fabe..431f37a9852c7 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -31,27 +31,26 @@
 #include "hw/timer/ibex_timer.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
-#include "target/riscv/cpu.h"
+#include "hw/registerfields.h"
 #include "migration/vmstate.h"
 
 REG32(ALERT_TEST, 0x00)
     FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
 REG32(CTRL, 0x04)
     FIELD(CTRL, ACTIVE, 0, 1)
-REG32(CFG0, 0x100)
-    FIELD(CFG0, PRESCALE, 0, 12)
-    FIELD(CFG0, STEP, 16, 8)
-REG32(LOWER0, 0x104)
-REG32(UPPER0, 0x108)
-REG32(COMPARE_LOWER0, 0x10C)
-REG32(COMPARE_UPPER0, 0x110)
-REG32(INTR_ENABLE, 0x114)
+REG32(INTR_ENABLE, 0x100)
     FIELD(INTR_ENABLE, IE_0, 0, 1)
-REG32(INTR_STATE, 0x118)
+REG32(INTR_STATE, 0x104)
     FIELD(INTR_STATE, IS_0, 0, 1)
-REG32(INTR_TEST, 0x11C)
+REG32(INTR_TEST, 0x108)
     FIELD(INTR_TEST, T_0, 0, 1)
-
+REG32(CFG0, 0x10c)
+    FIELD(CFG0, PRESCALE, 0, 12)
+    FIELD(CFG0, STEP, 16, 8)
+REG32(LOWER0, 0x110)
+REG32(UPPER0, 0x114)
+REG32(COMPARE_LOWER0, 0x118)
+REG32(COMPARE_UPPER0, 0x11c)
 static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
 {
     return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
diff --git a/hw/timer/meson.build b/hw/timer/meson.build
index 178321c029c8d..ebf46f641b40d 100644
--- a/hw/timer/meson.build
+++ b/hw/timer/meson.build
@@ -30,7 +30,7 @@ system_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c'))
 system_ss.add(when: 'CONFIG_STELLARIS_GPTM', if_true: files('stellaris-gptm.c'))
 system_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c'))
 system_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c'))
-specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c'))
+specific_ss.add(when: 'CONFIG_IBEX_TIMER', if_true: files('ibex_timer.c'))
 system_ss.add(when: 'CONFIG_SIFIVE_PWM', if_true: files('sifive_pwm.c'))
 
 specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c'))
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
index 3b50ecfb5409d..e8a68ae57a17f 100644
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -453,6 +453,7 @@ int print_insn_riscv128         (bfd_vma, disassemble_info*);
 int print_insn_rx(bfd_vma, disassemble_info *);
 int print_insn_hexagon(bfd_vma, disassemble_info *);
 int print_insn_loongarch(bfd_vma, disassemble_info *);
+const char *get_riscv_debug_reg_name(int regno);
 
 #ifdef CONFIG_CAPSTONE
 bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size);
diff --git a/include/exec/poison.h b/include/exec/poison.h
index a779adbb7a6cb..693d9b214aed9 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -25,6 +25,9 @@
 #pragma GCC poison TARGET_PPC
 #pragma GCC poison TARGET_PPC64
 #pragma GCC poison TARGET_ABI32
+#pragma GCC poison TARGET_RISCV
+#pragma GCC poison TARGET_RISCV32
+#pragma GCC poison TARGET_RISCV64
 #pragma GCC poison TARGET_RX
 #pragma GCC poison TARGET_S390X
 #pragma GCC poison TARGET_SH4
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 9615051774d75..3e249ec350127 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -167,6 +167,8 @@ struct CPUClass {
     int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
     vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
+    bool (*debug_request)(CPUState *cpu);
+    void (*debug_enable_singlestep)(CPUState *cpu, vaddr addr);
 
     const char *gdb_core_xml_file;
     const char * (*gdb_arch_name)(CPUState *cpu);
@@ -499,6 +501,8 @@ struct CPUState {
 
     /* Should CPU start in powered-off state? */
     bool start_powered_off;
+    /* Is CPU currently currently disabled? */
+    bool disabled;
 
     bool unplug;
     bool crash_occurred;
diff --git a/include/hw/core/rust_demangle.h b/include/hw/core/rust_demangle.h
new file mode 100644
index 0000000000000..8aa759907ea0b
--- /dev/null
+++ b/include/hw/core/rust_demangle.h
@@ -0,0 +1,58 @@
+/* Demangler for the Rust programming language
+   Copyright (C) 2016-2019 Free Software Foundation, Inc.
+   Written by David Tolnay (dtolnay@gmail.com).
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+In addition to the permissions in the GNU Library General Public
+License, the Free Software Foundation gives you unlimited permission
+to link the compiled version of this file into combinations with other
+programs, and to distribute those combinations without any restriction
+coming from the use of this file.  (The Library Public License
+restrictions do apply in other respects; for example, they cover
+modification of the file, and distribution when not linked into a
+combined executable.)
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB.
+If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef QEMU_RUST_DEMANGLE_H
+#define QEMU_RUST_DEMANGLE_H
+
+#define DMGL_NO_OPTS     0
+#define DMGL_PARAMS      (1 << 0)
+#define DMGL_ANSI        (1 << 1)
+#define DMGL_JAVA        (1 << 2)
+#define DMGL_VERBOSE     (1 << 3)
+#define DMGL_TYPES       (1 << 4)
+#define DMGL_RET_POSTFIX (1 << 5)
+#define DMGL_RET_DROP    (1 << 6)
+#define DMGL_AUTO        (1 << 8)
+#define DMGL_GNU_V3      (1 << 14)
+#define DMGL_GNAT        (1 << 15)
+#define DMGL_DLANG       (1 << 16)
+#define DMGL_RUST        (1 << 17)
+#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT|DMGL_DLANG|DMGL_RUST)
+#define DMGL_NO_RECURSE_LIMIT (1 << 18)
+#define DEMANGLE_RECURSION_LIMIT 2048
+
+/* Callback typedef for allocation-less demangler interfaces. */
+typedef void (*demangle_callbackref)(const char *, size_t, void *);
+
+int rust_demangle_callback(const char *mangled, int options,
+                          demangle_callbackref callback, void *opaque);
+
+char * rust_demangle(const char *mangled, int options);
+void rust_demangle_replace(char *mangled);
+
+#endif // QEMU_RUST_DEMANGLE_H
diff --git a/include/hw/display/st7735.h b/include/hw/display/st7735.h
new file mode 100644
index 0000000000000..9ed02a4550e6e
--- /dev/null
+++ b/include/hw/display/st7735.h
@@ -0,0 +1,45 @@
+/*
+ * QEMU Sitronix ST7735 controller device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_DISPLAY_ST7735_H
+#define HW_DISPLAY_ST7735_H
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+#include "exec/hwaddr.h"
+
+#define TYPE_ST7735 "st7735"
+OBJECT_DECLARE_SIMPLE_TYPE(St7735State, ST7735)
+
+#define ST7735_IO_LINES TYPE_ST7735 ".io"
+
+enum {
+    ST7735_IO_RESET,
+    ST7735_IO_D_C,
+    ST7735_IO_COUNT,
+};
+
+void st7735_configure(DeviceState *dev, hwaddr addr);
+
+#endif /* HW_DISPLAY_ST7735_H */
diff --git a/include/hw/elf_ops.h.inc b/include/hw/elf_ops.h.inc
index 9c35d1b9da6c3..bf758ac27ec0a 100644
--- a/include/hw/elf_ops.h.inc
+++ b/include/hw/elf_ops.h.inc
@@ -321,7 +321,7 @@ static ssize_t glue(load_elf, SZ)(const char *name, int fd,
                                   uint32_t *pflags, int elf_machine,
                                   int clear_lsb, int data_swab,
                                   AddressSpace *as, bool load_rom,
-                                  symbol_fn_t sym_cb)
+                                  symbol_fn_t sym_cb, bool skip_nosz)
 {
     struct elfhdr ehdr;
     struct elf_phdr *phdr = NULL, *ph;
@@ -560,7 +560,7 @@ static ssize_t glue(load_elf, SZ)(const char *name, int fd,
                      * We need to zero'ify the space that is not copied
                      * from file
                      */
-                    if (file_size < mem_size) {
+                    if (file_size < mem_size && !skip_nosz) {
                         res = address_space_set(as ? as : &address_space_memory,
                                                 addr + file_size, 0,
                                                 mem_size - file_size,
@@ -625,3 +625,68 @@ static ssize_t glue(load_elf, SZ)(const char *name, int fd,
     g_free(phdr);
     return ret;
 }
+
+static int glue(load_elf_symbols, SZ)(const char *name, int fd, int must_swab,
+                                      int elf_machine, int clear_lsb)
+{
+    struct elfhdr ehdr;
+    int ret = ELF_LOAD_FAILED;
+
+    if (read(fd, &ehdr, sizeof(ehdr)) != sizeof(ehdr)) {
+        goto fail;
+    }
+    if (must_swab) {
+        glue(bswap_ehdr, SZ)(&ehdr);
+    }
+
+    if (elf_machine <= EM_NONE) {
+        /* The caller didn't specify an ARCH, we can figure it out */
+        elf_machine = ehdr.e_machine;
+    }
+
+    switch (elf_machine) {
+        case EM_PPC64:
+            if (ehdr.e_machine != EM_PPC64) {
+                if (ehdr.e_machine != EM_PPC) {
+                    ret = ELF_LOAD_WRONG_ARCH;
+                    goto fail;
+                }
+            }
+            break;
+        case EM_X86_64:
+            if (ehdr.e_machine != EM_X86_64) {
+                if (ehdr.e_machine != EM_386) {
+                    ret = ELF_LOAD_WRONG_ARCH;
+                    goto fail;
+                }
+            }
+            break;
+        case EM_MICROBLAZE:
+            if (ehdr.e_machine != EM_MICROBLAZE) {
+                if (ehdr.e_machine != EM_MICROBLAZE_OLD) {
+                    ret = ELF_LOAD_WRONG_ARCH;
+                    goto fail;
+                }
+            }
+            break;
+        case EM_MIPS:
+        case EM_NANOMIPS:
+            if ((ehdr.e_machine != EM_MIPS) &&
+                (ehdr.e_machine != EM_NANOMIPS)) {
+                ret = ELF_LOAD_WRONG_ARCH;
+                goto fail;
+            }
+            break;
+        default:
+            if (elf_machine != ehdr.e_machine) {
+                ret = ELF_LOAD_WRONG_ARCH;
+                goto fail;
+            }
+    }
+
+    glue(load_symbols, SZ)(&ehdr, fd, must_swab, clear_lsb, NULL);
+    ret = 0;
+
+fail:
+    return ret;
+}
diff --git a/include/hw/ibexdemo/ibexdemo_gpio.h b/include/hw/ibexdemo/ibexdemo_gpio.h
new file mode 100644
index 0000000000000..2d25bafae535d
--- /dev/null
+++ b/include/hw/ibexdemo/ibexdemo_gpio.h
@@ -0,0 +1,41 @@
+/*
+ * QEMU lowRISC Ibex Demo SPI host device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_GPIO_IBEXDEMO_GPIO_H
+#define HW_GPIO_IBEXDEMO_GPIO_H
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+#include "exec/hwaddr.h"
+
+#define TYPE_IBEXDEMO_GPIO "ibexdemo-gpio"
+OBJECT_DECLARE_SIMPLE_TYPE(IbexDemoGPIOState, IBEXDEMO_GPIO)
+
+#define IBEXDEMO_GPIO_IN_MAX  8u
+#define IBEXDEMO_GPIO_OUT_MAX 16u
+
+#define IBEXDEMO_GPIO_IN_LINES  TYPE_IBEXDEMO_GPIO ".in"
+#define IBEXDEMO_GPIO_OUT_LINES TYPE_IBEXDEMO_GPIO ".out"
+
+#endif /* HW_GPIO_IBEXDEMO_GPIO_H */
diff --git a/include/hw/ibexdemo/ibexdemo_simctrl.h b/include/hw/ibexdemo/ibexdemo_simctrl.h
new file mode 100644
index 0000000000000..a80f363b78671
--- /dev/null
+++ b/include/hw/ibexdemo/ibexdemo_simctrl.h
@@ -0,0 +1,35 @@
+/*
+ * QEMU lowRISC Ibex Demo Sim Control device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MISC_IBEXDEMO_SIMCTRL_H
+#define HW_MISC_IBEXDEMO_SIMCTRL_H
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+#include "exec/hwaddr.h"
+
+#define TYPE_IBEXDEMO_SIMCTRL "ibexdemo-simctrl"
+OBJECT_DECLARE_SIMPLE_TYPE(IbexDemoSimCtrlState, IBEXDEMO_SIMCTRL)
+
+#endif /* HW_MISC_IBEXDEMO_SIMCTRL_H */
diff --git a/include/hw/ibexdemo/ibexdemo_spi.h b/include/hw/ibexdemo/ibexdemo_spi.h
new file mode 100644
index 0000000000000..3a675f95b7efb
--- /dev/null
+++ b/include/hw/ibexdemo/ibexdemo_spi.h
@@ -0,0 +1,35 @@
+/*
+ * QEMU lowRISC Ibex Demo SPI host device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_SSI_IBEXDEMO_SPI_H
+#define HW_SSI_IBEXDEMO_SPI_H
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+#include "exec/hwaddr.h"
+
+#define TYPE_IBEXDEMO_SPI "ibexdemo-spi"
+OBJECT_DECLARE_SIMPLE_TYPE(IbexDemoSPIState, IBEXDEMO_SPI)
+
+#endif /* HW_SSI_IBEXDEMO_SPI_H */
diff --git a/include/hw/ibexdemo/ibexdemo_timer.h b/include/hw/ibexdemo/ibexdemo_timer.h
new file mode 100644
index 0000000000000..9101a55f1c7f0
--- /dev/null
+++ b/include/hw/ibexdemo/ibexdemo_timer.h
@@ -0,0 +1,34 @@
+/*
+ * QEMU lowRISC Ibex Demo Timer device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_TIMER_IBEXDEMO_TIMER_H
+#define HW_TIMER_IBEXDEMO_TIMER_H
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+
+#define TYPE_IBEXDEMO_TIMER "ibexdemo-timer"
+OBJECT_DECLARE_SIMPLE_TYPE(IbexDemoTimerState, IBEXDEMO_TIMER)
+
+#endif /* HW_TIMER_IBEXDEMO_TIMER_H */
diff --git a/include/hw/ibexdemo/ibexdemo_uart.h b/include/hw/ibexdemo/ibexdemo_uart.h
new file mode 100644
index 0000000000000..efd3839e1cea0
--- /dev/null
+++ b/include/hw/ibexdemo/ibexdemo_uart.h
@@ -0,0 +1,35 @@
+/*
+ * QEMU lowRISC Ibex Demo UART device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_CHAR_IBEXDEMO_UART_H
+#define HW_CHAR_IBEXDEMO_UART_H
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+#include "exec/hwaddr.h"
+
+#define TYPE_IBEXDEMO_UART "ibexdemo-uart"
+OBJECT_DECLARE_SIMPLE_TYPE(IbexDemoUARTState, IBEXDEMO_UART)
+
+#endif /* HW_CHAR_IBEXDEMO_UART_H */
diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h
index d3f45ec248167..f59a8a9fc8936 100644
--- a/include/hw/intc/sifive_plic.h
+++ b/include/hw/intc/sifive_plic.h
@@ -58,6 +58,7 @@ struct SiFivePLICState {
     uint32_t *pending;
     uint32_t *claimed;
     uint32_t *enable;
+    uint32_t *level;
 
     /* config */
     char *hart_config;
@@ -71,6 +72,7 @@ struct SiFivePLICState {
     uint32_t context_base;
     uint32_t context_stride;
     uint32_t aperture_size;
+    bool edge_triggered;
 
     qemu_irq *m_external_irqs;
     qemu_irq *s_external_irqs;
@@ -82,6 +84,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     uint32_t num_priorities, uint32_t priority_base,
     uint32_t pending_base, uint32_t enable_base,
     uint32_t enable_stride, uint32_t context_base,
-    uint32_t context_stride, uint32_t aperture_size);
+    uint32_t context_stride, uint32_t aperture_size,
+    bool edge_triggered);
 
 #endif
diff --git a/include/hw/jtag/tap_ctrl.h b/include/hw/jtag/tap_ctrl.h
new file mode 100644
index 0000000000000..4f40f9f2dab13
--- /dev/null
+++ b/include/hw/jtag/tap_ctrl.h
@@ -0,0 +1,92 @@
+/*
+ * QEMU JTAG TAP controller
+ *
+ * Copyright (c) 2022-2024 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_JTAG_TAP_CTRL_H
+#define HW_JTAG_TAP_CTRL_H
+
+#include "qom/object.h"
+
+struct _TapDataHandler;
+typedef struct _TapDataHandler TapDataHandler;
+
+struct _TapDataHandler {
+    const char *name; /**< Name */
+    size_t length; /**< Data register length */
+    uint64_t value; /**< Capture/Update value */
+    void *opaque; /**< Arbitrary data */
+    void (*capture)(TapDataHandler *tdh);
+    void (*update)(TapDataHandler *tdh);
+};
+
+/*
+ * Create TAP IDCODE
+ *
+ * @_mfid_ Manufacturer ID
+ * @_pnum_ Part number
+ * @_ver_  Version
+ */
+#define JTAG_IDCODE(_mfid_, _pnum_, _ver_) \
+    ((((_ver_) & 0xfu) << 28u) | (((_pnum_) & 0xffffu) << 12u) | \
+     (((_mfid_) & 0x7ffu) << 1u) | 0b1)
+
+/*
+ * Create JEDEC Manufacturer ID
+ *
+ * @_tbl_ JEDEC table
+ * @_id_ Entry in JEDEC table
+ */
+#define JEDEC_MANUFACTURER_ID(_tbl_, _id_) \
+    (((((_tbl_) - 1u) & 0xfu) << 7u) | ((_id_) & 0x7fu))
+
+#define TYPE_TAP_CTRL_IF "tap-ctrl-interface"
+typedef struct TapCtrlIfClass TapCtrlIfClass;
+DECLARE_CLASS_CHECKERS(TapCtrlIfClass, TAP_CTRL_IF, TYPE_TAP_CTRL_IF)
+#define TAP_CTRL_IF(_obj_) INTERFACE_CHECK(TapCtrlIf, (_obj_), TYPE_TAP_CTRL_IF)
+
+typedef struct TapCtrlIf TapCtrlIf;
+
+struct TapCtrlIfClass {
+    InterfaceClass parent_class;
+
+    /**
+     * Report whether TAP controller is enabled.
+     *
+     * @return @c true if the TAP can be used.
+     */
+    bool (*is_enabled)(TapCtrlIf *dev);
+
+    /*
+     * Register instruction support on the TAP controller
+     *
+     * @code instruction code for which to register the handler
+     * @tdh TAP data handler to register
+     * @return non-zero on error
+     */
+    int (*register_instruction)(TapCtrlIf *dev, unsigned code,
+                                const TapDataHandler *tdh);
+};
+
+#endif // HW_JTAG_TAP_CTRL_H
diff --git a/include/hw/jtag/tap_ctrl_rbb.h b/include/hw/jtag/tap_ctrl_rbb.h
new file mode 100644
index 0000000000000..a08caaa4f0b3d
--- /dev/null
+++ b/include/hw/jtag/tap_ctrl_rbb.h
@@ -0,0 +1,35 @@
+/*
+ * QEMU JTAG TAP controller for the OpenOCD/Spike Remote BigBang protocol
+ *
+ * Copyright (c) 2024 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_JTAG_TAP_CTRL_RBB_H
+#define HW_JTAG_TAP_CTRL_RBB_H
+
+#include "qom/object.h"
+
+#define TYPE_TAP_CTRL_RBB "tap-ctrl-rbb"
+OBJECT_DECLARE_SIMPLE_TYPE(TapCtrlRbbState, TAP_CTRL_RBB)
+
+#endif /* HW_JTAG_TAP_CTRL_RBB_H */
diff --git a/include/hw/loader.h b/include/hw/loader.h
index d035e72748a98..9dea108b8a495 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -133,6 +133,8 @@ const char *load_elf_strerror(ssize_t error);
  *      is used if nothing is supplied here.
  * @load_rom : Load ELF binary as ROM
  * @sym_cb: Callback function for symbol table entries
+ * @skip_nosz: whether to initialize section area not stored in ELF file such as
+ *             NOBITS sections.
  *
  * Load an ELF file's contents to the emulated system's address space.
  * Clients may optionally specify a callback to perform address
@@ -148,6 +150,19 @@ const char *load_elf_strerror(ssize_t error);
 typedef void (*symbol_fn_t)(const char *st_name, int st_info,
                             uint64_t st_value, uint64_t st_size);
 
+ssize_t load_elf_ram_sym_nosz(const char *filename,
+                              uint64_t (*elf_note_fn)(void *, void *, bool),
+                              uint64_t (*translate_fn)(void *, uint64_t),
+                              void *translate_opaque, uint64_t *pentry,
+                              uint64_t *lowaddr, uint64_t *highaddr,
+                              uint32_t *pflags, int big_endian, int elf_machine,
+                              int clear_lsb, int data_swab,
+                              AddressSpace *as, bool load_rom,
+                              symbol_fn_t sym_cb, bool skip_nosz);
+
+/** load_elf_ram_sym:
+ * Same as load_elf_ram_sym_nosz(), with skip_nosz disabled
+ */
 ssize_t load_elf_ram_sym(const char *filename,
                          uint64_t (*elf_note_fn)(void *, void *, bool),
                          uint64_t (*translate_fn)(void *, uint64_t),
@@ -191,6 +206,9 @@ ssize_t load_elf(const char *filename,
  */
 void load_elf_hdr(const char *filename, void *hdr, bool *is64, Error **errp);
 
+int load_elf_sym(const char *filename, int big_endian, int elf_machine,
+                 int clear_lsb);
+
 ssize_t load_aout(const char *filename, hwaddr addr, int max_sz,
                   bool big_endian, hwaddr target_page_size);
 
@@ -359,4 +377,9 @@ typedef struct RomGap {
  */
 RomGap rom_find_largest_gap_between(hwaddr base, size_t size);
 
+/**
+ * rom_load: Load all registered ROMs
+ */
+void rom_load(void);
+
 #endif
diff --git a/include/hw/misc/pulp_rv_dm.h b/include/hw/misc/pulp_rv_dm.h
new file mode 100644
index 0000000000000..c833efba4502f
--- /dev/null
+++ b/include/hw/misc/pulp_rv_dm.h
@@ -0,0 +1,70 @@
+/*
+ * QEMU OpenTitan Debug Module device
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_PULP_RV_DM_H
+#define HW_PULP_RV_DM_H
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+
+#define TYPE_PULP_RV_DM "pulp-rv-dm"
+OBJECT_DECLARE_SIMPLE_TYPE(PulpRVDMState, PULP_RV_DM)
+
+#define PULP_RV_DM_ACK_OUT_LINES TYPE_PULP_RV_DM ".ack-out"
+
+/* Configuration */
+#define PULP_RV_DM_NSCRATCH_COUNT        2u
+#define PULP_RV_DM_DATA_COUNT            2u
+#define PULP_RV_DM_PROGRAM_BUFFER_COUNT  8u
+#define PULP_RV_DM_ABSTRACTCMD_COUNT     10u
+#define PULP_RV_DM_FLAGS_COUNT           1u
+#define PULP_RV_DM_WHERETO_OFFSET        0x300u
+#define PULP_RV_DM_PROGRAM_BUFFER_OFFSET 0x360u
+#define PULP_RV_DM_DATAADDR_OFFSET       0x380u
+
+/* ROM entry points */
+#define PULP_RV_DM_HALT_OFFSET      0x0000
+#define PULP_RV_DM_RESUME_OFFSET    0x0004
+#define PULP_RV_DM_EXCEPTION_OFFSET 0x0008
+
+/* Memory regions */
+#define PULP_RV_DM_REGS_BASE 0x0u
+#define PULP_RV_DM_REGS_SIZE sizeof(uint32_t)
+#define PULP_RV_DM_MEM_BASE  0x100u
+#define PULP_RV_DM_MEM_SIZE  0x700u
+#define PULP_RV_DM_ROM_BASE  0x800u
+#define PULP_RV_DM_ROM_SIZE  0x800u
+
+/*
+ * Special MemTxAttrs requester identifier so that debug module can identified
+ * a debugger-initiated request (vs. a regular hart-initiated request).
+ */
+/* Not sure how to define this at system level */
+#define PULP_RV_DM_REQUESTER_ID UINT16_MAX
+
+#endif /* HW_PULP_RV_DM_H */
diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
index 518d627dc5dc8..61710239b0e77 100644
--- a/include/hw/misc/unimp.h
+++ b/include/hw/misc/unimp.h
@@ -23,6 +23,9 @@ struct UnimplementedDeviceState {
     unsigned offset_fmt_width;
     char *name;
     uint64_t size;
+    bool warn_once;
+    bool r_warned;
+    bool w_warned;
 };
 
 /**
diff --git a/include/hw/opentitan/ot_address_space.h b/include/hw/opentitan/ot_address_space.h
new file mode 100644
index 0000000000000..518ecd757c20c
--- /dev/null
+++ b/include/hw/opentitan/ot_address_space.h
@@ -0,0 +1,44 @@
+/*
+ * QEMU OpenTitan Address Space container
+ *
+ * Copyright (c) 2023-2024 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * AddressSpace instances are not Object, i.e. cannot be used with the QOM APIs.
+ * OtAddressSpaceState acts as an AddressSpace container so an address space
+ * can be stored and retrieved as another QOM object. It does not provide any
+ * other service.
+ */
+
+#ifndef HW_OPENTITAN_OT_ADDRESS_SPACE_H
+#define HW_OPENTITAN_OT_ADDRESS_SPACE_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_ADDRESS_SPACE "ot-address_space"
+OBJECT_DECLARE_SIMPLE_TYPE(OtAddressSpaceState, OT_ADDRESS_SPACE)
+
+AddressSpace *ot_address_space_get(OtAddressSpaceState *s);
+void ot_address_space_set(OtAddressSpaceState *s, AddressSpace *as);
+
+#endif /* HW_OPENTITAN_OT_ADDRESS_SPACE_H */
diff --git a/include/hw/opentitan/ot_aes.h b/include/hw/opentitan/ot_aes.h
new file mode 100644
index 0000000000000..dc69ad5041cb3
--- /dev/null
+++ b/include/hw/opentitan/ot_aes.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU OpenTitan AES device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_AES_H
+#define HW_OPENTITAN_OT_AES_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_AES "ot-aes"
+OBJECT_DECLARE_TYPE(OtAESState, OtAESClass, OT_AES)
+
+#define OT_AES_KEY_SIZE (256u / 8u)
+
+#endif /* HW_OPENTITAN_OT_AES_H */
diff --git a/include/hw/opentitan/ot_alert.h b/include/hw/opentitan/ot_alert.h
new file mode 100644
index 0000000000000..c45d4af70da9c
--- /dev/null
+++ b/include/hw/opentitan/ot_alert.h
@@ -0,0 +1,41 @@
+/*
+ * QEMU OpenTitan Alert handler device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_ALERT_H
+#define HW_OPENTITAN_OT_ALERT_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+#define TYPE_OT_ALERT "ot-alert"
+OBJECT_DECLARE_TYPE(OtAlertState, OtAlertClass, OT_ALERT)
+
+#define OT_DEVICE_ALERT   TYPE_OT_ALERT "-sig"
+#define OT_ALERT_ESCALATE TYPE_OT_ALERT "-esc"
+
+#endif /* HW_OPENTITAN_OT_ALERT_H */
diff --git a/include/hw/opentitan/ot_aon_timer.h b/include/hw/opentitan/ot_aon_timer.h
new file mode 100644
index 0000000000000..7dea47b6133ec
--- /dev/null
+++ b/include/hw/opentitan/ot_aon_timer.h
@@ -0,0 +1,40 @@
+/*
+ * QEMU OpenTitan AON Timer device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_AON_TIMER_H
+#define HW_OPENTITAN_OT_AON_TIMER_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_AON_TIMER "ot-aon_timer"
+OBJECT_DECLARE_TYPE(OtAonTimerState, OtAonTimerClass, OT_AON_TIMER)
+
+#define OT_AON_TIMER_WKUP TYPE_OT_AON_TIMER "-wkup"
+#define OT_AON_TIMER_BARK TYPE_OT_AON_TIMER "-bark"
+#define OT_AON_TIMER_BITE TYPE_OT_AON_TIMER "-bite"
+
+#endif /* HW_OPENTITAN_OT_AON_TIMER_H */
diff --git a/include/hw/opentitan/ot_ast_dj.h b/include/hw/opentitan/ot_ast_dj.h
new file mode 100644
index 0000000000000..cecda3ac17073
--- /dev/null
+++ b/include/hw/opentitan/ot_ast_dj.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan Darjeeling Analog Sensor Top device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_AST_DJ_H
+#define HW_OPENTITAN_OT_AST_DJ_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_AST_DJ "ot-ast-dj"
+OBJECT_DECLARE_TYPE(OtASTDjState, OtASTDjClass, OT_AST_DJ)
+
+#endif /* HW_OPENTITAN_OT_AST_DJ_H */
diff --git a/include/hw/opentitan/ot_ast_eg.h b/include/hw/opentitan/ot_ast_eg.h
new file mode 100644
index 0000000000000..fc55015c84f82
--- /dev/null
+++ b/include/hw/opentitan/ot_ast_eg.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan EarlGrey Analog Sensor Top device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_AST_EG_H
+#define HW_OPENTITAN_OT_AST_EG_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_AST_EG "ot-ast-eg"
+OBJECT_DECLARE_TYPE(OtASTEgState, OtASTEgClass, OT_AST_EG)
+
+#endif /* HW_OPENTITAN_OT_AST_EG_H */
diff --git a/include/hw/opentitan/ot_clkmgr.h b/include/hw/opentitan/ot_clkmgr.h
new file mode 100644
index 0000000000000..058c2ba490b9d
--- /dev/null
+++ b/include/hw/opentitan/ot_clkmgr.h
@@ -0,0 +1,59 @@
+/*
+ * QEMU OpenTitan Clock manager device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_CLKMGR_H
+#define HW_OPENTITAN_OT_CLKMGR_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_CLKMGR "ot-clkmgr"
+OBJECT_DECLARE_TYPE(OtClkMgrState, OtClkMgrClass, OT_CLKMGR)
+
+/* Supported ClockManager versions */
+typedef enum {
+    OT_CLKMGR_VERSION_EG_1_0_0,
+    OT_CLKMGR_VERSION_DJ,
+    OT_CLKMGR_VERSION_COUNT,
+} OtClkMgrVersion;
+
+#define OT_CLOCK_HINT_PREFIX "ot-clock-hint-"
+
+#define OT_CLKMGR_CLOCK_INPUT TYPE_OT_CLKMGR "-clock-in"
+
+/* deprecated definitions */
+typedef enum {
+    OT_CLKMGR_HINT_AES,
+    OT_CLKMGR_HINT_HMAC,
+    OT_CLKMGR_HINT_KMAC,
+    OT_CLKMGR_HINT_OTBN,
+    OT_CLKMGR_HINT_COUNT
+} OtClkMgrHintSource;
+
+#define OT_CLKMGR_HINT  TYPE_OT_CLKMGR "-hint"
+#define OT_CLOCK_ACTIVE "ot-clock-active"
+
+#endif /* HW_OPENTITAN_OT_CLKMGR_H */
diff --git a/include/hw/opentitan/ot_clock_ctrl.h b/include/hw/opentitan/ot_clock_ctrl.h
new file mode 100644
index 0000000000000..d59066790feed
--- /dev/null
+++ b/include/hw/opentitan/ot_clock_ctrl.h
@@ -0,0 +1,71 @@
+/*
+ * QEMU OpenTitan Clock controller interface
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_CLOCK_CTRL_H
+#define HW_OPENTITAN_OT_CLOCK_CTRL_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_CLOCK_CTRL_IF "ot-clock_ctrl_if"
+typedef struct OtClockCtrlIfClass OtClockCtrlIfClass;
+DECLARE_CLASS_CHECKERS(OtClockCtrlIfClass, OT_CLOCK_CTRL_IF,
+                       TYPE_OT_CLOCK_CTRL_IF)
+#define OT_CLOCK_CTRL_IF(_obj_) \
+    INTERFACE_CHECK(OtClockCtrlIf, (_obj_), TYPE_OT_CLOCK_CTRL_IF)
+
+typedef struct OtClockCtrlIf OtClockCtrlIf;
+
+struct OtClockCtrlIfClass {
+    InterfaceClass parent_class;
+
+    /*
+     * Enable or disable a clock source.
+     *
+     * @clk the clock source
+     * @enable whether to enable or disable the clock source
+     */
+    void (*clock_enable)(OtClockCtrlIf *dev, const char *clkname, bool enable);
+
+    /*
+     * Select the external clock.
+     *
+     * @enable whether to enable or disable the external clock.
+     */
+    void (*clock_ext_freq_select)(OtClockCtrlIf *dev, bool enable);
+};
+
+/*
+ * Output clock (OT_CLOCK_CTRL_COUNT) lines
+ *
+ * IRQ signal carries the current clock value in Hz, as an unsigned value
+ * encoded in the `int` type, _i.e._ up to 4GHz.
+ */
+#define OT_CLOCK_CTRL_CLOCK_OUTPUT TYPE_OT_CLOCK_CTRL_IF "-clock-out"
+
+#define OT_CLOCK_CTRL_CLOCK_INPUT TYPE_OT_CLOCK_CTRL_IF "-clock-in"
+
+#endif /* HW_OPENTITAN_OT_CLOCK_CTRL_H */
diff --git a/include/hw/opentitan/ot_common.h b/include/hw/opentitan/ot_common.h
new file mode 100644
index 0000000000000..46977467c8655
--- /dev/null
+++ b/include/hw/opentitan/ot_common.h
@@ -0,0 +1,406 @@
+/*
+ * QEMU RISC-V Helpers for OpenTitan EarlGrey
+ *
+ * Copyright (c) 2023-2024 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_OPENTITAN_OT_COMMON_H
+#define HW_OPENTITAN_OT_COMMON_H
+
+#include "chardev/char.h"
+#include "hw/core/cpu.h"
+#include "hw/riscv/ibex_common.h"
+#include "system/memory.h"
+
+/* ------------------------------------------------------------------------ */
+/* Timer */
+/* ------------------------------------------------------------------------ */
+
+/* QEMU virtual timer to use for OpenTitan devices */
+#define OT_VIRTUAL_CLOCK QEMU_CLOCK_VIRTUAL
+
+/* ------------------------------------------------------------------------ */
+/* TL-UL Bus Characteristics */
+/* ------------------------------------------------------------------------ */
+
+#define OT_TL_UL_D_WIDTH_BITS  32u
+#define OT_TL_UL_D_WIDTH_BYTES ((OT_TL_UL_D_WIDTH_BITS) / 8u)
+
+/* ------------------------------------------------------------------------ */
+/* Register Span Definitions */
+/* ------------------------------------------------------------------------ */
+
+#define OT_REG_NAME_IDX(_n_, _i_) (R_##_n_##_##_i_)
+#define OT_REG_COUNT(_n_, _l_) \
+    (OT_REG_NAME_IDX(_n_, _l_) - OT_REG_NAME_IDX(_n_, 0) + 1u)
+#define OT_REG_SPAN(_n_, _l_) (OT_REG_COUNT(_n_, _l_) * sizeof(uint32_t))
+
+/* ------------------------------------------------------------------------ */
+/* Multi-bit boolean values */
+/* ------------------------------------------------------------------------ */
+
+#define OT_MULTIBITBOOL4_TRUE  0x6u
+#define OT_MULTIBITBOOL4_FALSE 0x9u
+#define OT_MULTIBITBOOL4_WIDTH 4u
+#define OT_MULTIBITBOOL4_MASK  ((1u << OT_MULTIBITBOOL4_WIDTH) - 1u)
+
+#define OT_MULTIBITBOOL8_TRUE  0x96u
+#define OT_MULTIBITBOOL8_FALSE 0x69u
+#define OT_MULTIBITBOOL8_WIDTH 8u
+#define OT_MULTIBITBOOL8_MASK  ((1u << OT_MULTIBITBOOL8_WIDTH) - 1u)
+
+#define OT_MULTIBITBOOL12_TRUE  0x696u
+#define OT_MULTIBITBOOL12_FALSE 0x969u
+#define OT_MULTIBITBOOL12_WIDTH 12u
+#define OT_MULTIBITBOOL12_MASK  ((1u << OT_MULTIBITBOOL12_WIDTH) - 1u)
+
+#define OT_MULTIBITBOOL16_TRUE  0x9696u
+#define OT_MULTIBITBOOL16_FALSE 0x6969u
+#define OT_MULTIBITBOOL16_WIDTH 16u
+#define OT_MULTIBITBOOL16_MASK  ((1u << OT_MULTIBITBOOL16_WIDTH) - 1u)
+
+#define OT_MULTIBITBOOL_LC4_TRUE  0xau
+#define OT_MULTIBITBOOL_LC4_FALSE 0x5u
+#define OT_MULTIBITBOOL_LC4_WIDTH 4u
+#define OT_MULTIBITBOOL_LC4_MASK  ((1u << OT_MULTIBITBOOL_LC4_WIDTH) - 1u)
+
+typedef uint8_t ot_mb4_t;
+typedef uint8_t ot_mb8_t;
+typedef uint16_t ot_mb12_t;
+typedef uint16_t ot_mb16_t;
+typedef uint8_t ot_mb_lc4_t;
+
+/*
+ * Performs a logical OR operation between two multibit values.
+ * This treats "act" as logical 1, and all other values are treated as 0.
+ * Truth table:
+ *
+ *  A    | B    | OUT
+ * ------+------+-----
+ *  !act | !act | !act
+ *  act  | !act | act
+ *  !act | act  | act
+ *  act  | act  | act
+ */
+static inline uint32_t
+ot_multibitbool_or(uint32_t a, uint32_t b, uint32_t act, uint32_t size)
+{
+    uint32_t mask = (1u << size) - 1u;
+    return (((a | b) & act) | ((a & b) & ~act)) & mask;
+}
+
+/*
+ * Performs a logical AND operation between two multibit values.
+ * This treats "act" as logical 1, and all other values are treated as 0.
+ * Truth table:
+ *
+ *  A    | B    | OUT
+ * ------+------+-----
+ *  !act | !act | !act
+ *  act  | !act | !act
+ *  !act | act  | !act
+ *  act  | act  | act
+ */
+static inline uint32_t
+ot_multibitbool_and(uint32_t a, uint32_t b, uint32_t act, uint32_t size)
+{
+    uint32_t mask = (1u << size) - 1u;
+    return (((a & b) & act) | ((a | b) & ~act)) & mask;
+}
+
+/*
+ * Performs a logical OR operation between two multibit values.
+ * This treats "True" as logical 1, and all other values are
+ * treated as 0.
+ */
+static inline uint32_t
+ot_multibitbool_or_hi(uint32_t a, uint32_t b, uint32_t size)
+{
+    return ot_multibitbool_or(a, b, OT_MULTIBITBOOL16_TRUE, size);
+}
+
+/*
+ * Performs a logical AND operation between two multibit values.
+ * This treats "True" as logical 1, and all other values are
+ * treated as 0.
+ */
+static inline uint32_t
+ot_multibitbool_and_hi(uint32_t a, uint32_t b, uint32_t size)
+{
+    return ot_multibitbool_and(a, b, OT_MULTIBITBOOL16_TRUE, size);
+}
+
+/*
+ * Performs a logical OR operation between two multibit values.
+ * This treats "False" as logical 1, and all other values are
+ * treated as 0.
+ */
+static inline uint32_t
+ot_multibitbool_or_lo(uint32_t a, uint32_t b, uint32_t size)
+{
+    return ot_multibitbool_or(a, b, OT_MULTIBITBOOL16_FALSE, size);
+}
+
+/*
+ * Performs a logical AND operation between two multibit values.
+ * This treats "False" as logical 1, and all other values are
+ * treated as 0.
+ */
+static inline uint32_t
+ot_multibitbool_and_lo(uint32_t a, uint32_t b, uint32_t size)
+{
+    return ot_multibitbool_and(a, b, OT_MULTIBITBOOL16_FALSE, size);
+}
+
+/*
+ * Computes the new multibit register value when writing to a W1S register
+ * field.
+ */
+static inline uint32_t
+ot_multibitbool_w1s_write(uint32_t old, uint32_t val, uint32_t size)
+{
+    return ot_multibitbool_or_hi(old, val, size);
+}
+
+/*
+ * Computes the new multibit register value when writing to a W1C register
+ * field.
+ */
+static inline uint32_t
+ot_multibitbool_w1c_write(uint32_t old, uint32_t val, uint32_t size)
+{
+    return ot_multibitbool_and_hi(old, ~val, size);
+}
+
+/*
+ * Computes the new multibit register value when writing to a W0C register
+ * field.
+ */
+static inline uint32_t
+ot_multibitbool_w0c_write(uint32_t old, uint32_t val, uint32_t size)
+{
+    return ot_multibitbool_and_hi(old, val, size);
+}
+
+/* ------------------------------------------------------------------------ */
+/* Extended memory transactions (MemTxAttrs can be tained with .role attr)  */
+/* ------------------------------------------------------------------------ */
+
+#if defined(MEMTXATTRS_HAS_ROLE) && (MEMTXATTRS_HAS_ROLE != 0)
+#define MEMTXATTRS_WITH_ROLE(_r_) \
+    (MemTxAttrs) \
+    { \
+        .role = (_r_) \
+    }
+#define MEMTXATTRS_GET_ROLE(_a_) ((_a_).unspecified ? 0xfu : (_a_).role);
+#else
+#define MEMTXATTRS_WITH_ROLE(_r_) MEMTXATTRS_UNSPECIFIED
+#define MEMTXATTRS_GET_ROLE(_a_)  ((_a_).unspecified ? 0xfu : 0x0)
+#endif
+
+/* ------------------------------------------------------------------------ */
+/* Shadow Registers */
+/* ------------------------------------------------------------------------ */
+
+/*
+ * Shadow register, concept documented at:
+ * https://docs.opentitan.org/doc/rm/register_tool/#shadow-registers
+ */
+typedef struct OtShadowReg {
+    /* committed register value */
+    uint32_t committed;
+    /* staged register value */
+    uint32_t staged;
+    /* true if 'staged' holds a value */
+    bool staged_p;
+} OtShadowReg;
+
+enum {
+    OT_SHADOW_REG_ERROR = -1,
+    OT_SHADOW_REG_COMMITTED = 0,
+    OT_SHADOW_REG_STAGED = 1,
+};
+
+/**
+ * Initialize a shadow register with a committed value and no staged value
+ */
+static inline void ot_shadow_reg_init(OtShadowReg *sreg, uint32_t value)
+{
+    sreg->committed = value;
+    sreg->staged_p = false;
+}
+
+/**
+ * Write a new value to a shadow register.
+ * If no value was previously staged, the new value is only staged for next
+ * write and the function returns OT_SHADOW_REG_STAGED.
+ * If a value was previously staged and the new value is different, the function
+ * returns OT_SHADOW_REG_ERROR and the new value is ignored. Otherwise the value
+ * is committed, the staged value is discarded and the function returns
+ * OT_SHADOW_REG_COMMITTED.
+ */
+static inline int ot_shadow_reg_write(OtShadowReg *sreg, uint32_t value)
+{
+    if (sreg->staged_p) {
+        if (value != sreg->staged) {
+            /* second write is different, return error status */
+            return OT_SHADOW_REG_ERROR;
+        }
+        sreg->committed = value;
+        sreg->staged_p = false;
+        return OT_SHADOW_REG_COMMITTED;
+    } else {
+        sreg->staged = value;
+        sreg->staged_p = true;
+        return OT_SHADOW_REG_STAGED;
+    }
+}
+
+/**
+ * Return the current committed register value
+ */
+static inline uint32_t ot_shadow_reg_peek(const OtShadowReg *sreg)
+{
+    return sreg->committed;
+}
+
+/**
+ * Discard the staged value and return the current committed register value
+ */
+static inline uint32_t ot_shadow_reg_read(OtShadowReg *sreg)
+{
+    sreg->staged_p = false;
+    return sreg->committed;
+}
+
+/* ------------------------------------------------------------------------ */
+/* Memory and Devices */
+/* ------------------------------------------------------------------------ */
+
+/**
+ * Get the closest CPU for a device, if any.
+ * @return the CPU if found or NULL
+ */
+CPUState *ot_common_get_local_cpu(DeviceState *s);
+
+/**
+ * Verify that command-line ROM image definitions are compatible with the
+ * current machine; emit warning message if they are not.
+ *
+ * @return the count of ROM controllers with no assigned ROM image
+ */
+unsigned ot_common_check_rom_configuration(void);
+
+/**
+ * Get the local address space for a device, if any.
+ * The local address space if the address space the OT CPU uses to access this
+ * device on its local bus.
+ *
+ * @s the device for each to find the local address space
+ * @return the AddressSpace if found or NULL
+ */
+AddressSpace *ot_common_get_local_address_space(DeviceState *s);
+
+/* ------------------------------------------------------------------------ */
+/* CharDev utilities */
+/* ------------------------------------------------------------------------ */
+
+/**
+ * Configure a (PTY) char backend to ignore status lines.
+ *
+ * @chr the character backend to configure.
+ */
+void ot_common_ignore_chr_status_lines(CharFrontend *chr);
+
+/* ------------------------------------------------------------------------ */
+/* String utilities */
+/* ------------------------------------------------------------------------ */
+
+int ot_common_string_ends_with(const char *str, const char *suffix);
+
+int ot_common_parse_hexa_str(uint8_t *out, const char *xstr, size_t olen,
+                             bool reverse, bool exact);
+
+/*
+ * Generate a uppercase hex-string representation of a buffer.
+ *
+ * @buf input byte buffer
+ * @size size of the buffer
+ * @order true to print the buffer in reverse order
+ * @hexstr output hex string buffer
+ * @hexstr_size max size of the output hex string buffer
+ *
+ * @return the hex string representation of the buffer
+ */
+const char *ot_common_uhexdump(const uint8_t *buf, size_t size, bool order,
+                               char *hexstr, size_t hexstr_size);
+
+/*
+ * Generate a lowercase hex-string representation of a buffer.
+ *
+ * @buf input byte buffer
+ * @size size of the buffer
+ * @order true to print the buffer in reverse order
+ * @hexstr output hex string buffer
+ * @hexstr_size max size of the output hex string buffer
+ *
+ * @return the hex string representation of the buffer
+ */
+const char *ot_common_lhexdump(const uint8_t *buf, size_t size, bool order,
+                               char *hexstr, size_t hexstr_size);
+
+/* ------------------------------------------------------------------------ */
+/* Configuration utilities */
+/* ------------------------------------------------------------------------ */
+
+#define OT_COMMON_DEV_ID "ot_id"
+
+void ot_common_configure_devices_with_id(
+    DeviceState **devices, BusState *bus, const char *id_value, bool id_prepend,
+    const IbexDeviceDef *defs, size_t count);
+
+void ot_common_configure_device_opts(DeviceState **devices, unsigned count);
+
+/* ------------------------------------------------------------------------ */
+/* OBJECT macros */
+/* ------------------------------------------------------------------------ */
+
+/*
+ * OBJECT_DEFINE_TYPE_EXTENDED with explicit class name
+ */
+#define OT_OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, ModuleClassName, \
+                                       module_obj_name, MODULE_OBJ_NAME, \
+                                       PARENT_MODULE_OBJ_NAME, ABSTRACT, ...) \
+    DO_OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, module_obj_name, \
+                                   MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, \
+                                   ABSTRACT, sizeof(ModuleClassName), \
+                                   __VA_ARGS__)
+
+/*
+ * OBJECT_DEFINE_ABSTRACT_TYPE with explicit class name
+ */
+#define OT_OBJECT_DEFINE_ABSTRACT_TYPE(ModuleObjName, ModuleClassName, \
+                                       module_obj_name, MODULE_OBJ_NAME, \
+                                       PARENT_MODULE_OBJ_NAME) \
+    OT_OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, ModuleClassName, \
+                                   module_obj_name, MODULE_OBJ_NAME, \
+                                   PARENT_MODULE_OBJ_NAME, true, { NULL })
+
+#endif /* HW_OPENTITAN_OT_COMMON_H */
diff --git a/include/hw/opentitan/ot_csrng.h b/include/hw/opentitan/ot_csrng.h
new file mode 100644
index 0000000000000..cd5cc5d1c9728
--- /dev/null
+++ b/include/hw/opentitan/ot_csrng.h
@@ -0,0 +1,132 @@
+/*
+ * QEMU OpenTitan Cryptographically Secure Random Number Generator
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_CSRNG_H
+#define HW_OPENTITAN_OT_CSRNG_H
+
+#include "qom/object.h"
+#include "hw/registerfields.h"
+
+#define TYPE_OT_CSRNG "ot-csrng"
+OBJECT_DECLARE_TYPE(OtCSRNGState, OtCSRNGClass, OT_CSRNG)
+
+#define OT_CSRNG_HW_APP_MAX 2u
+
+#define OT_CSRNG_PACKET_SIZE_BITS 128u
+#define OT_CSRNG_SEED_SIZE_BITS   384u
+
+#define OT_CSRNG_PACKET_WORD_COUNT \
+    ((unsigned)(OT_CSRNG_PACKET_SIZE_BITS / (8u * sizeof(uint32_t))))
+#define OT_CSRNG_CMD_WORD_COUNT  1u
+#define OT_CSRNG_SEED_BYTE_COUNT (OT_CSRNG_SEED_SIZE_BITS / 8u)
+#define OT_CSRNG_SEED_WORD_COUNT (OT_CSRNG_SEED_BYTE_COUNT / sizeof(uint32_t))
+#define OT_CSRNG_CMD_WORD_MAX \
+    (OT_CSRNG_CMD_WORD_COUNT + OT_CSRNG_SEED_WORD_COUNT)
+
+typedef enum {
+    OT_CSRNG_CMD_NONE = 0,
+    OT_CSRNG_CMD_INSTANTIATE = 1,
+    OT_CSRNG_CMD_RESEED = 2,
+    OT_CSRNG_CMD_GENERATE = 3,
+    OT_CSRNG_CMD_UPDATE = 4,
+    OT_CSRNG_CMD_UNINSTANTIATE = 5,
+} OtCSRNGCmd;
+
+typedef enum {
+    CSRNG_STATUS_SUCCESS,
+    CSRNG_STATUS_INVALID_ACMD,
+    CSRNG_STATUS_INVALID_GEN_CMD,
+    CSRNG_STATUS_INVALID_CMD_SEQ,
+    CSRNG_STATUS_RESEED_CNT_EXCEEDED,
+    CSRNG_STATUS_COUNT,
+} OtCSRNGCmdStatus;
+
+/* clang-format off */
+REG32(OT_CSNRG_CMD, 0)
+    FIELD(OT_CSNRG_CMD, ACMD, 0u, 4u)
+    FIELD(OT_CSNRG_CMD, CLEN, 4u, 4u)
+    FIELD(OT_CSNRG_CMD, FLAG0, 8u, 4u)
+    FIELD(OT_CSNRG_CMD, GLEN, 12u, 12u)
+/* clang-format on */
+
+/*
+ * Function called by the CSRNS instance once one entropy packet is available.
+ * Once all requested entropy packets have been sent, the req_sts IRQ is
+ * signalled.
+ *
+ * @opaque the opaque pointer as registered with the ot_csrng_connect_endpoint
+ *         function. This is usually the requester device instance.
+ * @app_id the HW application identifier of the requester
+ * @bits the buffer that contains entropy bits
+ * @fips   whether the entropy adhere to NIST requirements (simulated only,
+ *         current implementation does not support FIPS requirements)
+ */
+typedef void (*OtCsrngGenbitFiller)(void *opaque, const uint32_t *bits,
+                                    bool fips);
+
+/**
+ * Connect or disconnect a HW application to the CSRNG device.
+ *
+ * @s the CSRNG device
+ * @app_id the HW application unique identifier
+ * @req_sts the IRQ to signal once a command is completed. The IRQ level signal
+ *          the completion status of the command: 0 indicates a sucessful
+ *          completion, non-zero a failed one. Ignored if filler_fn is NULL.
+ * @filler_fn the filler function to call with one or more entropy packet, when
+ *            a generate command is called. If filler_fn is NULL, the HW
+ *            application is disconnected.
+ * @opaque a opaque pointer to forward to the filler_fn function
+ * @return an IRQ line that signals whether the HW application is ready to
+ *         receive entropy, i.e. genbits_ready
+ */
+typedef qemu_irq (*OtCsnrgConnectHwApp)(
+    OtCSRNGState *s, unsigned app_id, qemu_irq req_sts,
+    OtCsrngGenbitFiller filler_fn, void *opaque);
+
+/**
+ * Push a new command.
+ *
+ * @s the CSRNG device
+ * @app_id the HW application unique identifier, as provided with the connect
+ *         command
+ * @word a command or payload chunk
+ * @return CSRNG_STATUS_SUCCESS on success. If failure, the req_sts is not
+ *         signalled for this command.
+ */
+typedef OtCSRNGCmdStatus (*OtCsrngPushCommand)(OtCSRNGState *s, unsigned app_id,
+                                               uint32_t word);
+
+struct OtCSRNGClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    OtCsnrgConnectHwApp connect_hw_app;
+    OtCsrngPushCommand push_command;
+};
+
+#endif /* HW_OPENTITAN_OT_CSRNG_H */
diff --git a/include/hw/opentitan/ot_dev_proxy.h b/include/hw/opentitan/ot_dev_proxy.h
new file mode 100644
index 0000000000000..90b55a840df96
--- /dev/null
+++ b/include/hw/opentitan/ot_dev_proxy.h
@@ -0,0 +1,39 @@
+/*
+ * QEMU OpenTitan Device Proxy
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_DEV_PROXY_H
+#define HW_OPENTITAN_OT_DEV_PROXY_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_DEV_PROXY "ot-dev_proxy"
+OBJECT_DECLARE_TYPE(OtDevProxyState, OtDevProxyClass, OT_DEV_PROXY)
+
+#define TYPE_OT_DEV_PROXY_WATCHER "ot-dev_proxy_watcher"
+OBJECT_DECLARE_SIMPLE_TYPE(OtDevProxyWatcherState, OT_DEV_PROXY_WATCHER)
+
+#endif /* HW_OPENTITAN_OT_DEV_PROXY_H */
diff --git a/include/hw/opentitan/ot_dm_tl.h b/include/hw/opentitan/ot_dm_tl.h
new file mode 100644
index 0000000000000..46c104d56e012
--- /dev/null
+++ b/include/hw/opentitan/ot_dm_tl.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan Debug Module to TileLink bridge
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_DM_TL_H
+#define HW_OPENTITAN_OT_DM_TL_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_DM_TL "ot-dm_tl"
+OBJECT_DECLARE_TYPE(OtDMTLState, OtDMTLClass, OT_DM_TL)
+
+#endif /* HW_OPENTITAN_OT_DM_TL_H */
diff --git a/include/hw/opentitan/ot_dma.h b/include/hw/opentitan/ot_dma.h
new file mode 100644
index 0000000000000..ac5afc92a8d54
--- /dev/null
+++ b/include/hw/opentitan/ot_dma.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan DMA device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_DMA_H
+#define HW_OPENTITAN_OT_DMA_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_DMA "ot-dma"
+OBJECT_DECLARE_TYPE(OtDMAState, OtDMAClass, OT_DMA)
+
+#endif /* HW_OPENTITAN_OT_DMA_H */
diff --git a/include/hw/opentitan/ot_edn.h b/include/hw/opentitan/ot_edn.h
new file mode 100644
index 0000000000000..888deee4b2007
--- /dev/null
+++ b/include/hw/opentitan/ot_edn.h
@@ -0,0 +1,72 @@
+/*
+ * QEMU OpenTitan Entropy Distribution Network device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_EDN_H
+#define HW_OPENTITAN_OT_EDN_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_EDN "ot-edn"
+OBJECT_DECLARE_TYPE(OtEDNState, OtEDNClass, OT_EDN)
+
+/*
+ * Function called by the EDN instance whenever entropy has been requested
+ * and an entropy packet is available for the requester endpoint.
+ *
+ * @opaque the opaque pointer as registered with the ot_end_connect_endpoint
+ *         function. This is usually the requester device instance.
+ * @bits the entropy bits
+ * @fips   whether the entropy adhere to NIST requirements (simulated only,
+ *         current implementation does not support FIPS requirements)
+ */
+typedef void (*ot_edn_push_entropy_fn)(void *opaque, uint32_t bits, bool fips);
+
+/**
+ * Connect a device endpoint to the EDN device.
+ *
+ * @s the EDN device
+ * @ep_id the endpoint unique identifier for the EDN instance.
+ * @fn the function to call when an entropy packet is available for the
+ *      requester.
+ * @opaque a opaque pointer to forward to the entropy function
+ */
+void ot_edn_connect_endpoint(OtEDNState *s, unsigned ep_id,
+                             ot_edn_push_entropy_fn fn, void *opaque);
+
+/**
+ * Request a new entropy packet.
+ *
+ * @s the EDN device
+ * @ep_id the endpoint unique identifier for the EDN instance.
+ * @return 0 on success, -1 otherwise. If non-zero, the entropy function is not
+ *         called for this request.
+ */
+int ot_edn_request_entropy(OtEDNState *s, unsigned ep_id);
+
+
+#endif /* HW_OPENTITAN_OT_EDN_H */
diff --git a/include/hw/opentitan/ot_eg_pad_ring.h b/include/hw/opentitan/ot_eg_pad_ring.h
new file mode 100644
index 0000000000000..73ba85d321fd0
--- /dev/null
+++ b/include/hw/opentitan/ot_eg_pad_ring.h
@@ -0,0 +1,74 @@
+/*
+ * QEMU OpenTitan Earlgrey Pad Ring Device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_EG_PAD_RING_H
+#define HW_OPENTITAN_OT_EG_PAD_RING_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_EG_PAD_RING "ot-eg-pad-ring"
+OBJECT_DECLARE_TYPE(OtEgPadRingState, OtEgPadRingClass, OT_EG_PAD_RING)
+
+/* Pad output signals */
+#define OT_EG_PAD_RING_PAD_EGRESS TYPE_OT_EG_PAD_RING "-egress"
+
+/* Separate output signal to map the PoR GPIO to the correct reset request */
+#define OT_EG_PAD_RING_POR_REQ TYPE_OT_EG_PAD_RING "-por-req"
+
+/* Exposed I/O on external pads */
+typedef enum {
+    /*
+     * USB (N & P), SPI Host & SPI Device (Csb, Sck, Sd0-3) currently go direct
+     * through their respective CharDevs. Their DIOs are thus excluded unless
+     * it is determined they are needed/useful for emulating their devices.
+     *
+     * @todo: IOR8/IOR9 are used by the System Reset Controller (not currently
+     * emulated) as outputs for the `ec_rst_l` & `flash_wp_l` signals. These
+     * should be added here if it is determined they should be emulated.
+     *
+     * Flash testing and voltage signal pads (flash_test_mode{0,1} and
+     * flash_test_volt) are not needed for emulation. The same is true of the
+     * OTP external voltage pad.
+     *
+     * @todo: There are also 47 MIO pads that should be added here:
+     *  - IOR0-7 and IOR10-13,
+     *  - IOC0-12,
+     *  - IOB0-12, and
+     *  - IOA0-8.
+     * These pads should be connected to Earlgrey's Pinmux, and then the GPIO
+     * CharDev logic should be updated/moved so that the host talks to GPIO
+     * via the Pad Ring (going through Pinmux) instead of bypassing Pinmux to
+     * talk to GPIO directly. When this is done, because the pad states will
+     * not be reset, the work-around in Earlgrey's GPIO to retain values
+     * across reset (see commit c232d98) should be removed also.
+     */
+    OT_EG_PAD_RING_PAD_POR_N, /* Power-on-Reset (negated) */
+    OT_EG_PAD_RING_PAD_COUNT,
+} OtEgPadRingPad;
+
+#endif /* HW_OPENTITAN_OT_EG_PAD_RING_H */
diff --git a/include/hw/opentitan/ot_entropy_src.h b/include/hw/opentitan/ot_entropy_src.h
new file mode 100644
index 0000000000000..85971db981c12
--- /dev/null
+++ b/include/hw/opentitan/ot_entropy_src.h
@@ -0,0 +1,65 @@
+/*
+ * QEMU OpenTitan Entropy Source device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_ENTROPY_SRC_H
+#define HW_OPENTITAN_OT_ENTROPY_SRC_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_ENTROPY_SRC "ot-entropy_src"
+OBJECT_DECLARE_TYPE(OtEntropySrcState, OtEntropySrcClass, OT_ENTROPY_SRC)
+
+#define OT_ENTROPY_SRC_PACKET_SIZE_BITS 384u
+
+#define OT_ENTROPY_SRC_BYTE_COUNT (OT_ENTROPY_SRC_PACKET_SIZE_BITS / 8u)
+#define OT_ENTROPY_SRC_WORD_COUNT (OT_ENTROPY_SRC_BYTE_COUNT / sizeof(uint32_t))
+#define OT_ENTROPY_SRC_DWORD_COUNT \
+    (OT_ENTROPY_SRC_BYTE_COUNT / sizeof(uint64_t))
+
+struct OtEntropySrcClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    /*
+     * Fill up a buffer with random values
+     *
+     * @ess the entropy source instance
+     * @random the buffer to fill in with random data
+     * @fips on success, updated to @true if random data are FIPS-compliant
+     * @return 0 on success,
+     *         >=1 if the random source is still initializing or not enough
+     *           entropy is available to fill the output buffer;
+     *           if >1, indicates a hint on how many ns to wait before retrying,
+     *         -1 if the random source is not available, i.e. if the module is
+     *          not enabled or if the selected route is not the HW one,
+     */
+    int (*get_entropy)(OtEntropySrcState *ess,
+                       uint64_t random[OT_ENTROPY_SRC_DWORD_COUNT], bool *fips);
+};
+
+#endif /* HW_OPENTITAN_OT_ENTROPY_SRC_H */
diff --git a/include/hw/opentitan/ot_fifo32.h b/include/hw/opentitan/ot_fifo32.h
new file mode 100644
index 0000000000000..917b22a08cc0b
--- /dev/null
+++ b/include/hw/opentitan/ot_fifo32.h
@@ -0,0 +1,125 @@
+/*
+ * QEMU OpenTitan 32-bit FIFO helper
+ *
+ * Copyright (c) 2023 Rivos, Inc.
+ * Based on fifo8.h
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_FIFO32_H
+#define HW_OPENTITAN_OT_FIFO32_H
+
+typedef struct {
+    uint32_t *data;
+    uint32_t capacity;
+    uint32_t head;
+    uint32_t num;
+} OtFifo32;
+
+static inline void ot_fifo32_create(OtFifo32 *fifo, uint32_t capacity)
+{
+    fifo->data = g_new(uint32_t, capacity);
+    fifo->capacity = capacity;
+    fifo->head = 0u;
+    fifo->num = 0u;
+}
+
+static inline void ot_fifo32_push(OtFifo32 *fifo, uint32_t data)
+{
+    g_assert(fifo->num < fifo->capacity);
+
+    fifo->data[(fifo->head + fifo->num) % fifo->capacity] = data;
+    fifo->num++;
+}
+
+static inline uint32_t ot_fifo32_pop(OtFifo32 *fifo)
+{
+    g_assert(fifo->num > 0);
+
+    uint32_t ret = fifo->data[fifo->head];
+
+    fifo->head++;
+    fifo->head %= fifo->capacity;
+    fifo->num--;
+
+    return ret;
+}
+
+static inline uint32_t ot_fifo32_peek(const OtFifo32 *fifo)
+{
+    g_assert(fifo->num > 0);
+
+    uint32_t ret = fifo->data[fifo->head];
+
+    return ret;
+}
+
+static inline const uint32_t *
+ot_fifo32_pop_buf(OtFifo32 *fifo, uint32_t max, uint32_t *num)
+{
+    uint32_t *ret;
+
+    g_assert(max > 0 && max <= fifo->num);
+    *num = MIN(fifo->capacity - fifo->head, max);
+    ret = &fifo->data[fifo->head];
+    fifo->head += *num;
+    fifo->head %= fifo->capacity;
+    fifo->num -= *num;
+    return ret;
+}
+
+static inline const uint32_t *
+ot_fifo32_peek_buf(const OtFifo32 *fifo, uint32_t max, uint32_t *num)
+{
+    uint32_t *ret;
+
+    g_assert(max > 0 && max <= fifo->num);
+    *num = MIN(fifo->capacity - fifo->head, max);
+    ret = &fifo->data[fifo->head];
+    return ret;
+}
+
+static inline void ot_fifo32_reset(OtFifo32 *fifo)
+{
+    fifo->num = 0u;
+    fifo->head = 0u;
+}
+
+static inline bool ot_fifo32_is_empty(const OtFifo32 *fifo)
+{
+    return (fifo->num == 0u);
+}
+
+static inline bool ot_fifo32_is_full(const OtFifo32 *fifo)
+{
+    return (fifo->num == fifo->capacity);
+}
+
+static inline uint32_t ot_fifo32_num_free(const OtFifo32 *fifo)
+{
+    return fifo->capacity - fifo->num;
+}
+
+static inline uint32_t ot_fifo32_num_used(const OtFifo32 *fifo)
+{
+    return fifo->num;
+}
+
+#endif /* HW_OPENTITAN_OT_FIFO32_H */
diff --git a/include/hw/opentitan/ot_flash.h b/include/hw/opentitan/ot_flash.h
new file mode 100644
index 0000000000000..dac02939c81d7
--- /dev/null
+++ b/include/hw/opentitan/ot_flash.h
@@ -0,0 +1,84 @@
+/*
+ * QEMU OpenTitan Flash controller device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_FLASH_H
+#define HW_OPENTITAN_OT_FLASH_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_FLASH "ot-flash"
+OBJECT_DECLARE_TYPE(OtFlashState, OtFlashClass, OT_FLASH)
+
+/* Input signals from the lc_ctrl */
+typedef enum {
+    /* "Indication ... that software is allowed to read/write CREATOR_SEED" */
+    OT_FLASH_LC_CREATOR_SEED_SW_RW_EN,
+    /* "Indication ... that software is allowed to read/write OWNER_SEED" */
+    OT_FLASH_LC_OWNER_SEED_SW_RW_EN,
+    /* "Indication ... that hardware is allowed to read {CREATOR,OWNER}_SEED" */
+    OT_FLASH_LC_SEED_HW_RD_EN,
+    /* "Indication ... that software is allowed to read the isolated part" */
+    OT_FLASH_LC_ISO_PART_SW_RD_EN,
+    /* "Indication ... that software is allowed to write the isolated part" */
+    OT_FLASH_LC_ISO_PART_SW_WR_EN,
+    /* "Escalation indication" - move FSMs into the error state */
+    OT_FLASH_LC_ESCALATE_EN,
+    /* "Indication ... that non-volatile memory debug is allowed" */
+    OT_FLASH_LC_NVM_DEBUG_EN,
+    OT_FLASH_LC_BROADCAST_COUNT,
+} OtFlashLcBroadcastType;
+
+typedef enum {
+    FLASH_KEYMGR_SECRET_CREATOR_SEED,
+    FLASH_KEYMGR_SECRET_OWNER_SEED,
+    FLASH_KEYMGR_SECRET_COUNT
+} OtFlashKeyMgrSecretType;
+
+#define OT_FLASH_KEYMGR_SECRET_BYTES 32u /* 256 bits */
+
+typedef struct {
+    uint8_t secret[OT_FLASH_KEYMGR_SECRET_BYTES]; /* seed data */
+    bool valid; /* whether the seed data is valid */
+} OtFlashKeyMgrSecret;
+
+struct OtFlashClass {
+    DeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    /*
+     * Retrieve Key Manager secret (seed) from flash.
+     *
+     * @s the flash device
+     * @type the type of secret to retrieve
+     * @secret the key manager secret record to update
+     */
+    void (*get_keymgr_secret)(const OtFlashState *s,
+                              OtFlashKeyMgrSecretType type,
+                              OtFlashKeyMgrSecret *secret);
+};
+
+#endif /* HW_OPENTITAN_OT_FLASH_H */
diff --git a/include/hw/opentitan/ot_gpio.h b/include/hw/opentitan/ot_gpio.h
new file mode 100644
index 0000000000000..3ee375e9d103f
--- /dev/null
+++ b/include/hw/opentitan/ot_gpio.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU OpenTitan GPIO device
+ *
+ * Copyright (c) 2023-2024 Rivos, Inc.
+ *
+ * Author(s):
+ *  Samuel Ortiz <sameo@rivosinc.com>
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_GPIO_H
+#define HW_OPENTITAN_OT_GPIO_H
+
+#define TYPE_OT_GPIO "ot-gpio"
+
+#define OT_GPIO_OUT TYPE_OT_GPIO "-out"
+#define OT_GPIO_IN  TYPE_OT_GPIO "-in"
+
+#endif /* HW_OPENTITAN_OT_GPIO_H */
diff --git a/include/hw/opentitan/ot_gpio_dj.h b/include/hw/opentitan/ot_gpio_dj.h
new file mode 100644
index 0000000000000..e28098d412369
--- /dev/null
+++ b/include/hw/opentitan/ot_gpio_dj.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU OpenTitan Darjeeling GPIO device
+ *
+ * Copyright (c) 2023-2024 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_GPIO_DJ_H
+#define HW_OPENTITAN_OT_GPIO_DJ_H
+
+#include "hw/opentitan/ot_gpio.h"
+
+#define TYPE_OT_GPIO_DJ "ot-gpio-dj"
+OBJECT_DECLARE_TYPE(OtGpioDjState, OtGpioDjClass, OT_GPIO_DJ)
+
+#define OT_GPIO_STRAP_EN TYPE_OT_GPIO "-strap-en"
+
+#endif /* HW_OPENTITAN_OT_GPIO_DJ_H */
diff --git a/include/hw/opentitan/ot_gpio_eg.h b/include/hw/opentitan/ot_gpio_eg.h
new file mode 100644
index 0000000000000..782839fd7e85a
--- /dev/null
+++ b/include/hw/opentitan/ot_gpio_eg.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan EarlGrey GPIO device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_GPIO_EG_H
+#define HW_OPENTITAN_OT_GPIO_EG_H
+
+#include "hw/opentitan/ot_gpio.h"
+
+#define TYPE_OT_GPIO_EG "ot-gpio-eg"
+OBJECT_DECLARE_TYPE(OtGpioEgState, OtGpioEgClass, OT_GPIO_EG)
+
+#endif /* HW_OPENTITAN_OT_GPIO_EG_H */
diff --git a/include/hw/opentitan/ot_hmac.h b/include/hw/opentitan/ot_hmac.h
new file mode 100644
index 0000000000000..a3da4c6b45dd0
--- /dev/null
+++ b/include/hw/opentitan/ot_hmac.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan HMAC device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_HMAC_H
+#define HW_OPENTITAN_OT_HMAC_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_HMAC "ot-hmac"
+OBJECT_DECLARE_TYPE(OtHMACState, OtHMACClass, OT_HMAC)
+
+#endif /* HW_OPENTITAN_OT_HMAC_H */
diff --git a/include/hw/opentitan/ot_i2c.h b/include/hw/opentitan/ot_i2c.h
new file mode 100644
index 0000000000000..eb4d299310c08
--- /dev/null
+++ b/include/hw/opentitan/ot_i2c.h
@@ -0,0 +1,42 @@
+/*
+ * QEMU OpenTitan I2C device
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Duncan Laurie <duncan@rivosinc.com>
+ *  Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_I2C_H
+#define HW_OPENTITAN_OT_I2C_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+#define TYPE_OT_I2C "ot-i2c"
+OBJECT_DECLARE_TYPE(OtI2CState, OtI2CClass, OT_I2C)
+
+#define TYPE_OT_I2C_TARGET TYPE_OT_I2C "-target"
+OBJECT_DECLARE_SIMPLE_TYPE(OtI2CTarget, OT_I2C_TARGET)
+
+#endif /* HW_OPENTITAN_OT_I2C_H */
diff --git a/include/hw/opentitan/ot_i2c_host_proxy.h b/include/hw/opentitan/ot_i2c_host_proxy.h
new file mode 100644
index 0000000000000..6cf5ad09508a7
--- /dev/null
+++ b/include/hw/opentitan/ot_i2c_host_proxy.h
@@ -0,0 +1,36 @@
+/*
+ * I2C Host Proxy Device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_I2C_HOST_PROXY_H
+#define HW_OPENTITAN_OT_I2C_HOST_PROXY_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_I2C_HOST_PROXY "ot-i2c_host_proxy"
+OBJECT_DECLARE_TYPE(OtI2CHostProxyState, OtI2CHostProxyClass, OT_I2C_HOST_PROXY)
+
+#endif /* HW_OPENTITAN_OT_I2C_HOST_PROXY_H */
diff --git a/include/hw/opentitan/ot_ibex_wrapper.h b/include/hw/opentitan/ot_ibex_wrapper.h
new file mode 100644
index 0000000000000..67adb0685f848
--- /dev/null
+++ b/include/hw/opentitan/ot_ibex_wrapper.h
@@ -0,0 +1,48 @@
+/*
+ * QEMU OpenTitan Ibex Wrapper device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_IBEX_WRAPPER_H
+#define HW_OPENTITAN_OT_IBEX_WRAPPER_H
+
+#include "qom/object.h"
+#include "hw/resettable.h"
+#include "hw/sysbus.h"
+
+#define TYPE_OT_IBEX_WRAPPER "ot-ibex_wrapper"
+OBJECT_DECLARE_TYPE(OtIbexWrapperState, OtIbexWrapperClass, OT_IBEX_WRAPPER)
+
+#define OT_IBEX_WRAPPER_CPU_EN TYPE_OT_IBEX_WRAPPER "-cpu-en"
+
+typedef enum {
+    OT_IBEX_LC_CTRL_CPU_EN,
+    OT_IBEX_PWRMGR_CPU_EN,
+    OT_IBEX_CPU_EN_COUNT
+} OtIbexWrapperCpuEnable;
+
+#endif /* HW_OPENTITAN_OT_IBEX_WRAPPER_H */
diff --git a/include/hw/opentitan/ot_key_sink.h b/include/hw/opentitan/ot_key_sink.h
new file mode 100644
index 0000000000000..f0b3da48668a7
--- /dev/null
+++ b/include/hw/opentitan/ot_key_sink.h
@@ -0,0 +1,58 @@
+/*
+ * QEMU OpenTitan Key Sink interface
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_KEY_SINK_H
+#define HW_OPENTITAN_OT_KEY_SINK_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_KEY_SINK_IF "ot-key_sink_if"
+typedef struct OtKeySinkIfClass OtKeySinkIfClass;
+DECLARE_CLASS_CHECKERS(OtKeySinkIfClass, OT_KEY_SINK_IF, TYPE_OT_KEY_SINK_IF)
+#define OT_KEY_SINK_IF(_obj_) \
+    INTERFACE_CHECK(OtKeySinkIf, (_obj_), TYPE_OT_KEY_SINK_IF)
+
+typedef struct OtKeySinkIf OtKeySinkIf;
+
+struct OtKeySinkIfClass {
+    InterfaceClass parent_class;
+
+    /*
+     * Push key material to a key sink.
+     *
+     * Key is split in two shares, such as: key = share0 ^ share1
+     *
+     * @share0 first key share, may be NULL
+     * @share1 second key share, may be NULL
+     * @key_len the length of the key shares in bytes, may be 0
+     * @valid whether the key is valid or not
+     */
+    void (*push_key)(OtKeySinkIf *ifd, const uint8_t *share0,
+                     const uint8_t *share1, size_t key_len, bool valid);
+};
+
+#endif /* HW_OPENTITAN_OT_KEY_SINK_H */
diff --git a/include/hw/opentitan/ot_keymgr.h b/include/hw/opentitan/ot_keymgr.h
new file mode 100644
index 0000000000000..6ac454df0886b
--- /dev/null
+++ b/include/hw/opentitan/ot_keymgr.h
@@ -0,0 +1,40 @@
+/*
+ * QEMU OpenTitan Key Manager device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_KEYMGR_H
+#define HW_OPENTITAN_OT_KEYMGR_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_KEYMGR "ot-keymgr"
+OBJECT_DECLARE_TYPE(OtKeyMgrState, OtKeyMgrClass, OT_KEYMGR)
+
+/* Input signal to enable the key manager (from lifecycle controller) */
+#define OT_KEYMGR_ENABLE TYPE_OT_KEYMGR "-enable"
+
+#endif /* HW_OPENTITAN_OT_KEYMGR_H */
diff --git a/include/hw/opentitan/ot_keymgr_dpe.h b/include/hw/opentitan/ot_keymgr_dpe.h
new file mode 100644
index 0000000000000..ac7376c01f61b
--- /dev/null
+++ b/include/hw/opentitan/ot_keymgr_dpe.h
@@ -0,0 +1,40 @@
+/*
+ * QEMU OpenTitan Key Manager DPE device
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Samuel Ortiz <sameo@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_KEYMGR_DPE_H
+#define HW_OPENTITAN_OT_KEYMGR_DPE_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_KEYMGR_DPE "ot-keymgr_dpe"
+OBJECT_DECLARE_TYPE(OtKeyMgrDpeState, OtKeyMgrDpeClass, OT_KEYMGR_DPE)
+
+/* Input signal to enable the key manager (from lifecycle controller) */
+#define OT_KEYMGR_DPE_ENABLE TYPE_OT_KEYMGR_DPE "-enable"
+
+#endif /* HW_OPENTITAN_OT_KEYMGR_DPE_H */
diff --git a/include/hw/opentitan/ot_kmac.h b/include/hw/opentitan/ot_kmac.h
new file mode 100644
index 0000000000000..f120173b7239a
--- /dev/null
+++ b/include/hw/opentitan/ot_kmac.h
@@ -0,0 +1,130 @@
+/*
+ * QEMU OpenTitan KMAC device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * For details check the documentation here:
+ *    https://opentitan.org/book/hw/ip/kmac
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_KMAC_H
+#define HW_OPENTITAN_OT_KMAC_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_KMAC "ot-kmac"
+OBJECT_DECLARE_TYPE(OtKMACState, OtKMACClass, OT_KMAC)
+
+enum OtKMACMode {
+    OT_KMAC_MODE_NONE,
+    OT_KMAC_MODE_SHA3,
+    OT_KMAC_MODE_SHAKE,
+    OT_KMAC_MODE_CSHAKE,
+    OT_KMAC_MODE_KMAC,
+};
+
+/* Max size of cSHAKE prefix function name */
+#define OT_KMAC_PREFIX_FUNCNAME_LEN 32u
+
+/* Max size of cSHAKE prefix custom string */
+#define OT_KMAC_PREFIX_CUSTOMSTR_LEN 32u
+
+typedef struct {
+    uint8_t funcname[OT_KMAC_PREFIX_FUNCNAME_LEN];
+    size_t funcname_len;
+    uint8_t customstr[OT_KMAC_PREFIX_CUSTOMSTR_LEN];
+    size_t customstr_len;
+} OtKMACPrefix;
+
+typedef struct {
+    enum OtKMACMode mode;
+    size_t strength;
+    OtKMACPrefix prefix;
+} OtKMACAppCfg;
+
+#define OT_KMAC_APP_MSG_BYTES    (64u / 8u)
+#define OT_KMAC_APP_DIGEST_BYTES (384u / 8u)
+#define OT_KMAC_KEY_SIZE         (256u / 8u)
+
+typedef struct {
+    uint8_t msg_data[OT_KMAC_APP_MSG_BYTES];
+    size_t msg_len; /* meaningful count of bytes in msg_data */
+    bool last;
+} OtKMACAppReq;
+
+typedef struct {
+    uint8_t digest_share0[OT_KMAC_APP_DIGEST_BYTES];
+    uint8_t digest_share1[OT_KMAC_APP_DIGEST_BYTES];
+    bool done; /* digest_share updated (on last request) */
+} OtKMACAppRsp;
+
+/* KMAC application configuration helper */
+#define OT_KMAC_CONFIG(_mode_, _strength_, _fname_, _cust_) \
+    { \
+        .mode = (OT_KMAC_MODE_##_mode_), .strength = (_strength_), \
+        .prefix = { \
+            .funcname = (_fname_), \
+            .funcname_len = ARRAY_SIZE(_fname_) - 1u, \
+            .customstr = (_cust_), \
+            .customstr_len = ARRAY_SIZE(_cust_) - 1u, \
+        }, \
+    }
+
+/*
+ * Function called by the KMAC instance whenever an application request has been
+ * processed.
+ *
+ * @opaque the opaque pointer as registered with the ot_kmac_connect_app
+ *         function. This is usually the requester device instance.
+ * @rsp the KMAC response.
+ */
+typedef void (*OtKmacResponse)(void *opaque, const OtKMACAppRsp *rsp);
+
+struct OtKMACClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    /*
+     * Connect a application to the KMAC device.
+     *
+     * @app_idx the application index.
+     * @cfg pointer to the KMAC configuration for this application.
+     * @fn the function to call when an request has been processed.
+     * @opaque a opaque pointer to forward to the response function.
+     */
+    void (*connect_app)(OtKMACState *s, unsigned app_idx,
+                        const OtKMACAppCfg *cfg, OtKmacResponse fn,
+                        void *opaque);
+
+    /*
+     * Send a new application request to the KMAC device.
+     *
+     * @app_idx the application index.
+     * @req the KMAC request to process.
+     */
+    void (*app_request)(OtKMACState *s, unsigned app_idx,
+                        const OtKMACAppReq *req);
+};
+
+#endif /* HW_OPENTITAN_OT_KMAC_H */
diff --git a/include/hw/opentitan/ot_lc_ctrl.h b/include/hw/opentitan/ot_lc_ctrl.h
new file mode 100644
index 0000000000000..6b733cd2c67f5
--- /dev/null
+++ b/include/hw/opentitan/ot_lc_ctrl.h
@@ -0,0 +1,96 @@
+/*
+ * QEMU OpenTitan Life Cycle controller device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_LC_CTRL_H
+#define HW_OPENTITAN_OT_LC_CTRL_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+#define TYPE_OT_LC_CTRL "ot-lc_ctrl"
+OBJECT_DECLARE_TYPE(OtLcCtrlState, OtLcCtrlClass, OT_LC_CTRL)
+
+/* input lines */
+#define OT_LC_PWR          TYPE_OT_LC_CTRL "-pwr"
+#define OT_LC_A0_FORCE_RAW TYPE_OT_LC_CTRL "-a0-force-raw"
+
+/* output lines */
+#define OT_LC_BROADCAST TYPE_OT_LC_CTRL "-broadcast"
+#define OT_LC_SOC_DBG   TYPE_OT_LC_CTRL "-soc-dbg"
+
+/* Life cycle broadcast signals (booleans) */
+typedef enum {
+    OT_LC_RAW_TEST_RMA, /* SoC debug control */
+    OT_LC_DFT_EN, /* device for test */
+    OT_LC_NVM_DEBUG_EN, /* for embed. flash, not used in DJ */
+    OT_LC_HW_DEBUG_EN, /* unfortunately highly pervasive */
+    OT_LC_CPU_EN, /* ibex core */
+    OT_LC_KEYMGR_EN, /* key manager */
+    OT_LC_ESCALATE_EN, /* unfortunately highly pervasive */
+    OT_LC_CHECK_BYP_EN, /* OTP: bypass consistency check while updating */
+    OT_LC_CREATOR_SEED_SW_RW_EN, /* for OTP and embed. flash */
+    OT_LC_OWNER_SEED_SW_RW_EN, /* for embed. flash, not used in DJ, but should*/
+    OT_LC_ISO_PART_SW_RD_EN, /* for embed. flash, not used in DJ */
+    OT_LC_ISO_PART_SW_WR_EN, /* for embed. flash, not used in DJ */
+    OT_LC_SEED_HW_RD_EN, /* for OTP and embed. flash */
+    OT_LC_RMA, /* RMA state */
+    OT_LC_BROADCAST_COUNT,
+} OtLcCtrlBroadcast;
+
+#define OT_LC_KEYMGR_DIV_BYTES 16u /* 128 bits */
+
+#define OT_LC_SOC_DBG_STATE_COUNT 3u
+
+typedef struct {
+    uint8_t data[OT_LC_KEYMGR_DIV_BYTES];
+} OtLcCtrlKeyMgrDiv;
+
+struct OtLcCtrlClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    /*
+     * Retrieve key manager diversification value.
+     *
+     * @s the LC controller instance
+     * @div a pointer to a structure that will be filled with the key manager
+     *      diversification data.
+     */
+    void (*get_keymgr_div)(const OtLcCtrlState *s, OtLcCtrlKeyMgrDiv *div);
+
+    /*
+     * Expose SoC debug state value
+     *
+     * @s the LC controller instance
+     * @state the soc debug state index to obtain the code for
+     * @return LC soc debug state value or UINT32_MAX if the value of the state
+     *         is unknown
+     */
+    uint32_t (*get_soc_dbg_state)(const OtLcCtrlState *s, unsigned state);
+};
+
+#endif /* HW_OPENTITAN_OT_LC_CTRL_H */
diff --git a/include/hw/opentitan/ot_mbx.h b/include/hw/opentitan/ot_mbx.h
new file mode 100644
index 0000000000000..fc5fc35e43564
--- /dev/null
+++ b/include/hw/opentitan/ot_mbx.h
@@ -0,0 +1,44 @@
+/*
+ * QEMU OpenTitan Data Object Exchange Mailbox
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_MBX_H
+#define HW_OPENTITAN_OT_MBX_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_MBX "ot-mbx"
+OBJECT_DECLARE_TYPE(OtMbxState, OtMbxClass, OT_MBX)
+
+#define OT_MBX_HOST_REGS_COUNT 17u
+#define OT_MBX_SYS_REGS_COUNT  8u
+
+#define OT_MBX_HOST_APERTURE \
+    ROUND_UP((OT_MBX_HOST_REGS_COUNT * sizeof(uint32_t)), 0x10u)
+#define OT_MBX_SYS_APERTURE \
+    ROUND_UP((OT_MBX_SYS_REGS_COUNT * sizeof(uint32_t)), 0x10u)
+
+#endif /* HW_OPENTITAN_OT_MBX_H */
diff --git a/include/hw/opentitan/ot_noise_src.h b/include/hw/opentitan/ot_noise_src.h
new file mode 100644
index 0000000000000..c88b869110d68
--- /dev/null
+++ b/include/hw/opentitan/ot_noise_src.h
@@ -0,0 +1,61 @@
+/*
+ * QEMU OpenTitan Noise Source interface
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_NOISE_SRC_H
+#define HW_OPENTITAN_OT_NOISE_SRC_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_NOISE_SRC_IF "ot-noise_src_if"
+typedef struct OtNoiseSrcIfClass OtNoiseSrcIfClass;
+DECLARE_CLASS_CHECKERS(OtNoiseSrcIfClass, OT_NOISE_SRC_IF, TYPE_OT_NOISE_SRC_IF)
+#define OT_NOISE_SRC_IF(_obj_) \
+    INTERFACE_CHECK(OtNoiseSrcIf, (_obj_), TYPE_OT_NOISE_SRC_IF)
+
+typedef struct OtNoiseSrcIf OtNoiseSrcIf;
+
+struct OtNoiseSrcIfClass {
+    InterfaceClass parent_class;
+
+    /*
+     * Report the fill rate of this source.
+     *
+     * @return the fill rate, in bytes per second
+     */
+    unsigned (*get_fill_rate)(OtNoiseSrcIf *dev);
+
+    /*
+     * Fill up a buffer with noise data
+     *
+     * @buffer destination buffer
+     * @length number of bytes to fill in
+     */
+    void (*get_noise)(OtNoiseSrcIf *dev, uint8_t *buffer, size_t length);
+};
+
+#endif /* HW_OPENTITAN_OT_NOISE_SRC_H */
diff --git a/include/hw/opentitan/ot_otbn.h b/include/hw/opentitan/ot_otbn.h
new file mode 100644
index 0000000000000..a0e57f2296812
--- /dev/null
+++ b/include/hw/opentitan/ot_otbn.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU OpenTitan Big Number device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_OTBN_H
+#define HW_OPENTITAN_OT_OTBN_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_OTBN "ot-otbn"
+OBJECT_DECLARE_TYPE(OtOTBNState, OtOTBNClass, OT_OTBN)
+
+#define OT_OTBN_KEY_SIZE (384u / 8u)
+
+#endif /* HW_OPENTITAN_OT_OTBN_H */
diff --git a/include/hw/opentitan/ot_otp_be_if.h b/include/hw/opentitan/ot_otp_be_if.h
new file mode 100644
index 0000000000000..c4201c477a6bf
--- /dev/null
+++ b/include/hw/opentitan/ot_otp_be_if.h
@@ -0,0 +1,68 @@
+/*
+ * QEMU OpenTitan OTP backend interface
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_OTP_BE_IF_H
+#define HW_OPENTITAN_OT_OTP_BE_IF_H
+
+#include "qom/object.h"
+#include "memory.h"
+
+#define TYPE_OT_OTP_BE_IF "ot-otp_be_if"
+typedef struct OtOtpBeIfClass OtOtpBeIfClass;
+DECLARE_CLASS_CHECKERS(OtOtpBeIfClass, OT_OTP_BE_IF, TYPE_OT_OTP_BE_IF)
+#define OT_OTP_BE_IF(_obj_) \
+    INTERFACE_CHECK(OtOtpBeIf, (_obj_), TYPE_OT_OTP_BE_IF)
+
+typedef struct OtOtpBeIf OtOtpBeIf;
+
+typedef struct {
+    struct {
+        unsigned read_ns; /* time to read an OTP cell */
+        unsigned write_ns; /* time to write an OTP cell */
+    } timings;
+} OtOtpBeCharacteristics;
+
+struct OtOtpBeIfClass {
+    InterfaceClass parent_class;
+
+    /*
+     * Report whether ECC feature is enabled
+     *
+     * @dev the OTP device this backend belongs to
+     * @return @c true if ECC mode is active, @c false otherwise
+     */
+    bool (*is_ecc_enabled)(OtOtpBeIf *beif);
+
+    /*
+     * Retrieve OTP back end characteristics
+     *
+     * @return the OTP characteristics
+     */
+    const OtOtpBeCharacteristics *(*get_characteristics)(OtOtpBeIf *beif);
+};
+
+#endif /* HW_OPENTITAN_OT_OTP_BE_IF_H */
diff --git a/include/hw/opentitan/ot_otp_dj.h b/include/hw/opentitan/ot_otp_dj.h
new file mode 100644
index 0000000000000..700d364990906
--- /dev/null
+++ b/include/hw/opentitan/ot_otp_dj.h
@@ -0,0 +1,35 @@
+/*
+ * QEMU OpenTitan Darjeeling One Time Programmable (OTP) memory controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_OTP_DJ_H
+#define HW_OPENTITAN_OT_OTP_DJ_H
+
+#define TYPE_OT_OTP_DJ "ot-otp-dj"
+OBJECT_DECLARE_TYPE(OtOTPDjState, OtOTPDjClass, OT_OTP_DJ)
+
+#endif /* HW_OPENTITAN_OT_OTP_DJ_H */
diff --git a/include/hw/opentitan/ot_otp_eg.h b/include/hw/opentitan/ot_otp_eg.h
new file mode 100644
index 0000000000000..9431b4be5d9d6
--- /dev/null
+++ b/include/hw/opentitan/ot_otp_eg.h
@@ -0,0 +1,35 @@
+/*
+ * QEMU OpenTitan EarlGrey One Time Programmable (OTP) memory controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_OTP_EG_H
+#define HW_OPENTITAN_OT_OTP_EG_H
+
+#define TYPE_OT_OTP_EG "ot-otp-eg"
+OBJECT_DECLARE_TYPE(OtOTPEgState, OtOTPEgClass, OT_OTP_EG)
+
+#endif /* HW_OPENTITAN_OT_OTP_EG_H */
diff --git a/include/hw/opentitan/ot_otp_engine.h b/include/hw/opentitan/ot_otp_engine.h
new file mode 100644
index 0000000000000..6bfde4c8d300a
--- /dev/null
+++ b/include/hw/opentitan/ot_otp_engine.h
@@ -0,0 +1,416 @@
+/*
+ * QEMU OpenTitan One Time Programmable (OTP) memory controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Alex Jones <alex.jones@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_OTP_ENGINE_H
+#define HW_OPENTITAN_OT_OTP_ENGINE_H
+
+#include "qemu/timer.h"
+#include "hw/opentitan/ot_edn.h"
+#include "hw/opentitan/ot_otp_be_if.h"
+#include "hw/opentitan/ot_otp_if.h"
+#include "hw/opentitan/ot_otp_impl_if.h"
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_irq.h"
+#include "hw/sysbus.h"
+
+#undef OT_OTP_DEBUG
+
+#define TYPE_OT_OTP_ENGINE "ot-otp_engine"
+OBJECT_DECLARE_TYPE(OtOTPEngineState, OtOTPEngineClass, OT_OTP_ENGINE)
+
+#define OT_OTP_NUM_IRQS         2u
+#define OT_OTP_NUM_ALERTS       5u
+#define OT_OTP_NUM_DAI_WORDS    2u
+#define OT_OTP_NUM_DIGEST_WORDS 2u
+#define OT_OTP_NUM_ZER_WORDS    2u
+
+
+#define LC_TRANSITION_CNT_SIZE 48u
+#define LC_STATE_SIZE          40u
+
+#define OT_OTP_DIGEST_ADDR_MASK (sizeof(uint64_t) - 1u)
+#define OT_OTP_ZER_ADDR_MASK    (sizeof(uint64_t) - 1u)
+
+/* Error code (compliant with ERR_CODE registers) */
+typedef enum {
+    OT_OTP_NO_ERROR,
+    OT_OTP_MACRO_ERROR,
+    OT_OTP_MACRO_ECC_CORR_ERROR, /* This is NOT an error */
+    OT_OTP_MACRO_ECC_UNCORR_ERROR,
+    OT_OTP_MACRO_WRITE_BLANK_ERROR,
+    OT_OTP_ACCESS_ERROR,
+    OT_OTP_CHECK_FAIL_ERROR, /* Digest error */
+    OT_OTP_FSM_STATE_ERROR,
+    OT_OTP_ERROR_COUNT,
+} OtOTPError;
+
+/* States of an unbuffered partition FSM */
+typedef enum {
+    OT_OTP_UNBUF_RESET,
+    OT_OTP_UNBUF_INIT,
+    OT_OTP_UNBUF_INIT_WAIT,
+    OT_OTP_UNBUF_IDLE,
+    OT_OTP_UNBUF_READ,
+    OT_OTP_UNBUF_READ_WAIT,
+    OT_OTP_UNBUF_ERROR,
+} OtOTPUnbufState;
+
+/* States of a buffered partition FSM */
+typedef enum {
+    OT_OTP_BUF_RESET,
+    OT_OTP_BUF_INIT,
+    OT_OTP_BUF_INIT_WAIT,
+    OT_OTP_BUF_INIT_DESCR,
+    OT_OTP_BUF_INIT_DESCR_WAIT,
+    OT_OTP_BUF_IDLE,
+    OT_OTP_BUF_INTEG_SCR,
+    OT_OTP_BUF_INTEG_SCR_WAIT,
+    OT_OTP_BUF_INTEG_DIG_CLR,
+    OT_OTP_BUF_INTEG_DIG,
+    OT_OTP_BUF_INTEG_DIG_PAD,
+    OT_OTP_BUF_INTEG_DIG_FIN,
+    OT_OTP_BUF_INTEG_DIG_WAIT,
+    OT_OTP_BUF_CNSTY_READ,
+    OT_OTP_BUF_CNSTY_READ_WAIT,
+    OT_OTP_BUF_ERROR,
+} OtOTPBufState;
+
+/* Direct Access Interface states */
+typedef enum {
+    OT_OTP_DAI_RESET,
+    OT_OTP_DAI_INIT_OTP,
+    OT_OTP_DAI_INIT_PART,
+    OT_OTP_DAI_IDLE,
+    OT_OTP_DAI_ERROR,
+    OT_OTP_DAI_READ,
+    OT_OTP_DAI_READ_WAIT,
+    OT_OTP_DAI_DESCR,
+    OT_OTP_DAI_DESCR_WAIT,
+    OT_OTP_DAI_WRITE,
+    OT_OTP_DAI_WRITE_WAIT,
+    OT_OTP_DAI_SCR,
+    OT_OTP_DAI_SCR_WAIT,
+    OT_OTP_DAI_DIG_CLR,
+    OT_OTP_DAI_DIG_READ,
+    OT_OTP_DAI_DIG_READ_WAIT,
+    OT_OTP_DAI_DIG,
+    OT_OTP_DAI_DIG_PAD,
+    OT_OTP_DAI_DIG_FIN,
+    OT_OTP_DAI_DIG_WAIT,
+} OtOTPDAIState;
+
+typedef enum {
+    OT_OTP_LCI_RESET,
+    OT_OTP_LCI_IDLE,
+    OT_OTP_LCI_WRITE,
+    OT_OTP_LCI_WRITE_WAIT,
+    OT_OTP_LCI_ERROR,
+} OtOTPLCIState;
+
+typedef enum {
+    OT_OTP_DA_REG_REGWEN,
+    OT_OTP_DA_REG_CMD,
+    OT_OTP_DA_REG_ADDRESS,
+    OT_OTP_DA_REG_WDATA_0,
+    OT_OTP_DA_REG_WDATA_1,
+    OT_OTP_DA_REG_RDATA_0,
+    OT_OTP_DA_REG_RDATA_1,
+} OtOTPDirectAccessRegister;
+
+typedef struct {
+    union {
+        OtOTPBufState b;
+        OtOTPUnbufState u;
+    } state;
+    struct {
+        uint32_t *data; /* size, see OtOTPPartDesc w/o digest data */
+        uint64_t next_digest; /* computed HW digest to store into OTP cell */
+    } buffer; /* only meaningful for buffered partitions */
+    uint64_t digest; /* digest as read from OTP back end at init time */
+    bool locked;
+    bool failed;
+    bool read_lock;
+    bool write_lock;
+    /* OTP scrambling key constant, not constant for deriving other keys */
+    uint8_t *otp_scramble_key; /* may be NULL */
+    uint8_t *inv_default_data; /* may be NULL */
+} OtOTPPartController;
+
+typedef struct OtOTPDAIController {
+    QEMUTimer *delay; /* simulate delayed access completion */
+    QEMUTimer *digest_write; /* write computed digest to OTP cell */
+    OtOTPDAIState state;
+    int partition; /* current partition being worked on or -1 */
+} OtOTPDAIController;
+
+typedef struct {
+    QEMUTimer *prog_delay; /* OTP cell prog delay (use OT_OTP_HW_CLOCK) */
+    OtOTPLCIState state;
+    OtOTPError error;
+    ot_otp_program_ack_fn ack_fn;
+    void *ack_data;
+    uint16_t *data;
+    unsigned hpos; /* current offset in data */
+} OtOTPLCIController;
+
+typedef struct {
+    uint32_t *storage; /* overall buffer for the storage backend */
+    uint32_t *data; /* data buffer (all partitions) */
+    uint32_t *ecc; /* ecc buffer for date */
+    unsigned size; /* overall storage size in bytes */
+    unsigned data_size; /* data buffer size in bytes */
+    unsigned ecc_size; /* ecc buffer size in bytes */
+    unsigned ecc_bit_count; /* count of ECC bit for each data granule */
+    unsigned ecc_granule; /* size of a granule in bytes */
+} OtOTPStorage;
+
+typedef struct {
+    QEMUBH *bh;
+    uint16_t signal; /* each bit tells if signal needs to be handled */
+    uint16_t level; /* level of the matching signal */
+    uint16_t current_level; /* current level of all signals */
+} OtOTPLcBroadcast;
+
+static_assert(OT_OTP_LC_BROADCAST_COUNT < 8 * sizeof(uint16_t),
+              "Invalid OT_OTP_LC_BROADCAST_COUNT");
+
+typedef struct OtOTPKeyGen_ OtOTPKeyGen;
+typedef struct OtOTPScrmblKeyInit_ OtOTPScrmblKeyInit;
+
+typedef struct {
+    uint32_t dai_base; /* offset of DIRECT_ACCESS_REGWEN register */
+    uint32_t err_code_base; /* offset of ERR_CODE_0 register */
+    uint32_t read_lock_base; /* offset of first *_READ_LOCK  */
+} OtOTPRegisterOffset;
+
+struct OtOTPEngineState {
+    SysBusDevice parent_obj;
+
+    QEMUBH *pwr_otp_bh;
+    IbexIRQ irqs[OT_OTP_NUM_IRQS];
+    IbexIRQ alerts[OT_OTP_NUM_ALERTS];
+    IbexIRQ pwc_otp_rsp;
+
+    uint32_t *regs;
+    uint32_t alert_bm;
+
+    OtOTPLcBroadcast lc_broadcast;
+    OtOTPDAIController *dai;
+    OtOTPLCIController *lci;
+    OtOTPPartController *part_ctrls;
+    const OtOTPPartDesc *part_descs;
+    unsigned part_count;
+    unsigned part_lc_num;
+    OtOTPKeyGen *keygen;
+    OtOTPScrmblKeyInit *scrmbl_key_init;
+    OtOtpBeCharacteristics be_chars;
+    OtOTPRegisterOffset reg_offset;
+    uint64_t digest_iv;
+    uint8_t digest_const[16u];
+    uint64_t sram_iv;
+    uint8_t sram_const[16u];
+    /* flash_* are only defined for OtOTPImplIf with has_flash_support set */
+    uint64_t flash_data_iv;
+    uint8_t flash_data_const[16u];
+    uint64_t flash_addr_iv;
+    uint8_t flash_addr_const[16u];
+
+    OtOTPStorage *otp;
+    OtOTPHWCfg *hw_cfg;
+    OtOTPTokens *tokens;
+    char *hexstr;
+
+    char *ot_id;
+    BlockBackend *blk; /* OTP host backend */
+    OtOtpBeIf *otp_backend;
+    OtEDNState *edn;
+    char *scrmbl_key_xstr;
+    char *digest_const_xstr;
+    char *digest_iv_xstr;
+    char *sram_const_xstr;
+    char *sram_iv_xstr;
+    /* flash xstrs are only valid for OtOTPImplIf with has_flash_support set */
+    char *flash_data_iv_xstr;
+    char *flash_data_const_xstr;
+    char *flash_addr_iv_xstr;
+    char *flash_addr_const_xstr;
+    char **otp_scramble_key_xstrs; /* some entries may be NULL */
+    char **inv_default_part_xstrs; /* some entries may be NULL */
+    uint8_t edn_ep;
+    bool fatal_escalate;
+};
+
+struct OtOTPEngineClass {
+    SysBusDeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    /* @todo document all those */
+    void (*update_irqs)(OtOTPEngineState *s);
+    void (*update_alerts)(OtOTPEngineState *s);
+    int (*get_part_from_address)(const OtOTPEngineState *s, hwaddr addr);
+    uint32_t (*get_part_digest_reg)(OtOTPEngineState *s, uint32_t offset);
+    bool (*is_readable)(const OtOTPEngineState *s, unsigned part_ix);
+    void (*set_error)(OtOTPEngineState *s, unsigned part_ix, OtOTPError err);
+    void (*dai_read)(OtOTPEngineState *s);
+    void (*dai_write)(OtOTPEngineState *s);
+    void (*dai_digest)(OtOTPEngineState *s);
+    const OtOTPHWCfg *(*get_hw_cfg)(const OtOTPIf *dev);
+    void (*get_otp_key)(OtOTPIf *dev, OtOTPKeyType type, OtOTPKey *key);
+    bool (*program_req)(OtOTPIf *dev, const uint16_t *lc_tcount,
+                        const uint16_t *lc_state, ot_otp_program_ack_fn ack,
+                        void *opaque);
+};
+
+#ifdef OT_OTP_COMPORTABLE_REGS
+
+/* Comportable registers are identical for all OTP variants */
+REG32(INTR_STATE, 0x00u)
+SHARED_FIELD(INTR_OTP_OPERATION_DONE, 0u, 1u)
+SHARED_FIELD(INTR_OTP_ERROR, 1u, 1u)
+REG32(INTR_ENABLE, 0x04u)
+REG32(INTR_TEST, 0x08u)
+REG32(ALERT_TEST, 0x0cu)
+REG32(OTP_FIRST_IMPL_REG, 0x10u)
+SHARED_FIELD(ALERT_FATAL_MACRO_ERROR, 0u, 1u)
+SHARED_FIELD(ALERT_FATAL_CHECK_ERROR, 1u, 1u)
+SHARED_FIELD(ALERT_FATAL_BUS_INTEG_ERROR, 2u, 1u)
+SHARED_FIELD(ALERT_FATAL_PRIM_OTP_ALERT, 3u, 1u)
+SHARED_FIELD(ALERT_RECOV_PRIM_OTP_ALERT, 4u, 1u)
+
+#define INTR_WMASK (INTR_OTP_OPERATION_DONE_MASK | INTR_OTP_ERROR_MASK)
+
+#define ALERT_WMASK \
+    (ALERT_FATAL_MACRO_ERROR_MASK | ALERT_FATAL_CHECK_ERROR_MASK | \
+     ALERT_FATAL_BUS_INTEG_ERROR_MASK | ALERT_FATAL_PRIM_OTP_ALERT_MASK | \
+     ALERT_RECOV_PRIM_OTP_ALERT_MASK)
+
+#endif /* OT_OTP_COMPORTABLE_REGS */
+
+/* REG32 bitfields common to all new OTP versions */
+FIELD(OT_OTP_DIRECT_ACCESS_CMD, RD, 0u, 1u)
+FIELD(OT_OTP_DIRECT_ACCESS_CMD, WR, 1u, 1u)
+FIELD(OT_OTP_DIRECT_ACCESS_CMD, DIGEST, 2u, 1u)
+/* ZEROIZE has been introduced in OTP v2.10, after Earlgrey v1.0 / OTP v2.0 */
+FIELD(OT_OTP_DIRECT_ACCESS_CMD, ZEROIZE, 3u, 1u)
+
+SHARED_FIELD(OT_OTP_ERR_CODE, 0u, 3u)
+static_assert(OT_OTP_ERR_CODE_MASK >= OT_OTP_ERROR_COUNT - 1u,
+              "Error mask not large enough");
+
+SHARED_FIELD(OT_OTP_READ_LOCK, 0u, 1u)
+
+static inline unsigned
+ot_otp_engine_part_data_offset(const OtOTPEngineState *s, unsigned part_ix)
+{
+    return (unsigned)(s->part_descs[part_ix].offset);
+}
+
+static inline unsigned
+ot_otp_engine_part_data_byte_size(const OtOTPEngineState *s, unsigned part_ix)
+{
+    size_t size = s->part_descs[part_ix].size;
+
+    if (s->part_descs[part_ix].hw_digest || s->part_descs[part_ix].sw_digest) {
+        size -= sizeof(uint32_t) * OT_OTP_NUM_DIGEST_WORDS;
+    }
+
+    if (s->part_descs[part_ix].zeroizable) {
+        size -= sizeof(uint32_t) * OT_OTP_NUM_ZER_WORDS;
+    }
+
+    return (unsigned)size;
+}
+
+static inline bool
+ot_otp_engine_is_buffered(const OtOTPEngineState *s, unsigned part_ix)
+{
+    if (part_ix < s->part_count) {
+        return s->part_descs[part_ix].buffered;
+    }
+
+    return false;
+}
+
+static inline bool
+ot_otp_engine_is_secret(const OtOTPEngineState *s, unsigned part_ix)
+{
+    if (part_ix < s->part_count) {
+        return s->part_descs[part_ix].secret;
+    }
+
+    return false;
+}
+
+static inline bool
+ot_otp_engine_is_backend_ecc_enabled(const OtOTPEngineState *s)
+{
+    OtOtpBeIfClass *bec = OT_OTP_BE_IF_GET_CLASS(s->otp_backend);
+    if (!bec->is_ecc_enabled) {
+        return true;
+    }
+
+    return bec->is_ecc_enabled(s->otp_backend);
+}
+
+static inline bool ot_otp_engine_is_ecc_enabled(const OtOTPEngineState *s)
+{
+    return s->otp->ecc_granule == sizeof(uint16_t) &&
+           ot_otp_engine_is_backend_ecc_enabled(s);
+}
+
+static inline bool
+ot_otp_engine_has_digest(const OtOTPEngineState *s, unsigned part_ix)
+{
+    return s->part_descs[part_ix].hw_digest || s->part_descs[part_ix].sw_digest;
+}
+
+static inline bool ot_otp_engine_is_part_digest_offset(
+    const OtOTPEngineState *s, unsigned part_ix, hwaddr addr)
+{
+    uint16_t offset = s->part_descs[part_ix].digest_offset;
+
+    return (offset != UINT16_MAX) &&
+           ((addr & ~OT_OTP_DIGEST_ADDR_MASK) == offset);
+}
+
+static inline bool ot_otp_engine_is_part_zer_offset(
+    const OtOTPEngineState *s, unsigned part_ix, hwaddr addr)
+{
+    uint16_t offset = s->part_descs[part_ix].zer_offset;
+
+    return (offset != UINT16_MAX) && ((addr & ~OT_OTP_ZER_ADDR_MASK) == offset);
+}
+
+static inline uint32_t ot_otp_engine_dai_is_busy(const OtOTPEngineState *s)
+{
+    return s->dai->state != OT_OTP_DAI_IDLE;
+}
+
+#endif /* HW_OPENTITAN_OT_OTP_ENGINE_H */
diff --git a/include/hw/opentitan/ot_otp_if.h b/include/hw/opentitan/ot_otp_if.h
new file mode 100644
index 0000000000000..237bf4eff877a
--- /dev/null
+++ b/include/hw/opentitan/ot_otp_if.h
@@ -0,0 +1,198 @@
+/*
+ * QEMU OpenTitan One Time Programmable (OTP) memory controller public interface
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_OTP_IF_H
+#define HW_OPENTITAN_OT_OTP_IF_H
+
+#include "qom/object.h"
+#include "hw/opentitan/ot_common.h"
+
+#define TYPE_OT_OTP_IF "ot-otp_if"
+typedef struct OtOTPIfClass OtOTPIfClass;
+typedef struct OtOTPIf OtOTPIf;
+
+DECLARE_CLASS_CHECKERS(OtOTPIfClass, OT_OTP_IF, TYPE_OT_OTP_IF)
+#define OT_OTP_IF(_obj_) INTERFACE_CHECK(OtOTPIf, (_obj_), TYPE_OT_OTP_IF)
+
+/* Input signals from life cycle */
+typedef enum {
+    /* "Enable the TL-UL access port to the proprietary OTP IP." */
+    OT_OTP_LC_DFT_EN,
+    /* "Move all FSMs within OTP into the error state." */
+    OT_OTP_LC_ESCALATE_EN,
+    /* "Bypass consistency checks during life cycle state transitions." */
+    OT_OTP_LC_CHECK_BYP_EN,
+    /* "Enables SW R/W to the KeyMgr material partitions", should be SECRET2 */
+    OT_OTP_LC_CREATOR_SEED_SW_RW_EN,
+    /* see above, should be SECRET3 */
+    OT_OTP_LC_OWNER_SEED_SW_RW_EN,
+    /* "Enable HW R/O to the CREATOR_ROOT_KEY_SHARE{0,1}." */
+    OT_OTP_LC_SEED_HW_RD_EN,
+    OT_OTP_LC_BROADCAST_COUNT,
+} OtOtpLcBroadcast;
+
+#define OT_OTP_HWCFG_DEVICE_ID_BYTES     32u
+#define OT_OTP_HWCFG_MANUF_STATE_BYTES   32u
+#define OT_OTP_HWCFG_SOC_DBG_STATE_BYTES 4u
+
+/*
+ * Hardware configuration (for HW_CFG partitions).
+ *
+ * Digests are not added to this structure since real HW does not use them
+ *
+ * Note that some fields may be meaningless / not initialized depending on the
+ * actual OpenTitan top.
+ */
+typedef struct {
+    uint8_t device_id[OT_OTP_HWCFG_DEVICE_ID_BYTES];
+    uint8_t manuf_state[OT_OTP_HWCFG_MANUF_STATE_BYTES];
+    uint8_t soc_dbg_state[OT_OTP_HWCFG_SOC_DBG_STATE_BYTES];
+    ot_mb8_t en_sram_ifetch_mb8;
+    ot_mb8_t en_csrng_sw_app_read_mb8;
+    ot_mb_lc4_t valid_lc4; /* seems generated but no used on real HW */
+} OtOTPHWCfg;
+
+typedef enum {
+    OT_OTP_TOKEN_TEST_UNLOCK,
+    OT_OTP_TOKEN_TEST_EXIT,
+    OT_OTP_TOKEN_RMA,
+    OT_OTP_TOKEN_COUNT
+} OtOTPToken;
+
+typedef struct {
+    uint64_t lo;
+    uint64_t hi;
+} OtOTPTokenValue;
+
+typedef struct {
+    OtOTPTokenValue values[OT_OTP_TOKEN_COUNT];
+    uint32_t valid_bm; /* OtLcCtrlToken-indexed valid bit flags */
+} OtOTPTokens;
+
+typedef enum {
+    OT_OTP_KEY_FLASH_DATA,
+    OT_OTP_KEY_FLASH_ADDR,
+    OT_OTP_KEY_OTBN,
+    OT_OTP_KEY_SRAM,
+    OT_OTP_KEY_COUNT
+} OtOTPKeyType;
+
+#define OT_OTP_SEED_MAX_SIZE  32u /* 256 bits */
+#define OT_OTP_NONCE_MAX_SIZE 32u /* 256 bits */
+
+typedef struct {
+    uint8_t seed[OT_OTP_SEED_MAX_SIZE];
+    uint8_t nonce[OT_OTP_NONCE_MAX_SIZE];
+    uint8_t seed_size; /* size in bytes */
+    uint8_t nonce_size; /* size in bytes */
+    bool seed_valid; /* whether the seed is valid */
+} OtOTPKey;
+
+typedef enum {
+    OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE0,
+    OT_OTP_KEYMGR_SECRET_CREATOR_ROOT_KEY_SHARE1,
+    OT_OTP_KEYMGR_SECRET_CREATOR_SEED,
+    OT_OTP_KEYMGR_SECRET_OWNER_SEED,
+    OT_OTP_KEYMGR_SECRET_COUNT
+} OtOTPKeyMgrSecretType;
+
+#define OT_OTP_KEYMGR_SECRET_SIZE 32u /* 256 bits (for both keys and seeds) */
+
+typedef struct {
+    uint8_t secret[OT_OTP_KEYMGR_SECRET_SIZE]; /* key/seed data */
+    bool valid; /* whether the key/seed data is valid */
+} OtOTPKeyMgrSecret;
+
+typedef void (*ot_otp_program_ack_fn)(void *opaque, bool ack);
+
+struct OtOTPIfClass {
+    InterfaceClass parent_class;
+
+    /*
+     * Provide OTP lifecycle information.
+     *
+     * @dev the OTP device
+     * @lc_tcount if not NULL, updated with the raw LifeCycle transition count
+     *            buffer.
+     * @lc_state if not NULL, updated with the raw LifeCycle state buffer.
+     * @lc_valid if not NULL, update with the LC valid state (scalar)
+     * @secret_valid if not NULL, update with the LC secret_valid info (scalar)
+     *
+     * @note: lc_valid and secret_valid use OT_MULTIBITBOOL_LC4 encoding
+     */
+    void (*get_lc_info)(const OtOTPIf *dev, uint16_t *lc_state,
+                        uint16_t *lc_tcount, uint8_t *lc_valid,
+                        uint8_t *secret_valid, const OtOTPTokens **tokens);
+
+    /*
+     * Retrieve HW configuration.
+     *
+     * @dev the OTP device
+     * @return the HW config data (never NULL)
+     */
+    const OtOTPHWCfg *(*get_hw_cfg)(const OtOTPIf *dev);
+
+    /*
+     * Retrieve SRAM scrambling key.
+     *
+     * @dev the OTP device
+     * @type the type of the key to retrieve
+     * @key the key record to update
+     */
+    void (*get_otp_key)(OtOTPIf *dev, OtOTPKeyType type, OtOTPKey *key);
+
+    /*
+     * Retrieve Key Manager secret (key or seeds).
+     *
+     * @dev the OTP device
+     * @type the type of secret to retrieve
+     * @secret the key manager secret record to update
+     */
+    void (*get_keymgr_secret)(OtOTPIf *dev, OtOTPKeyMgrSecretType type,
+                              OtOTPKeyMgrSecret *secret);
+
+    /**
+     * Request the OTP to program the state, transition count pair.
+     * OTP only accepts one request at a time. If another program request is
+     * on going, this function returns immediately and never invoke the
+     * callback. Conversely, it should always invoke the callback if the request
+     * is accepted.
+     *
+     * @dev the OTP device
+     * @lc_tcount the raw LifeCycle transition count buffer
+     * @lc_state the raw LifeCycle state buffer
+     * @ack the callback to asynchronously invoke on OTP completion/error
+     * @opaque opaque data to forward to the ot_otp_program_ack_fn function
+     * @return @c true if request is accepted, @c false is rejected.
+     */
+    bool (*program_req)(OtOTPIf *dev, const uint16_t *lc_tcount,
+                        const uint16_t *lc_state, ot_otp_program_ack_fn ack,
+                        void *opaque);
+};
+
+#endif /* HW_OPENTITAN_OT_OTP_IF_H */
diff --git a/include/hw/opentitan/ot_otp_impl_if.h b/include/hw/opentitan/ot_otp_impl_if.h
new file mode 100644
index 0000000000000..bc54b68c8a42c
--- /dev/null
+++ b/include/hw/opentitan/ot_otp_impl_if.h
@@ -0,0 +1,119 @@
+/*
+ * QEMU OpenTitan One Time Programmable (OTP) implementer interface.
+ * An OTP device should implement this API used by the OTP engine.
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_OTP_IMPL_IF_H
+#define HW_OPENTITAN_OT_OTP_IMPL_IF_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_OTP_IMPL_IF "ot-otp_impl_if"
+typedef struct OtOTPImplIfClass OtOTPImplIfClass;
+typedef struct OtOTPImplIf OtOTPImplIf;
+DECLARE_CLASS_CHECKERS(OtOTPImplIfClass, OT_OTP_IMPL_IF, TYPE_OT_OTP_IMPL_IF)
+#define OT_OTP_IMPL_IF(_obj_) \
+    INTERFACE_CHECK(OtOTPImplIf, (_obj_), TYPE_OT_OTP_IMPL_IF)
+
+/* @todo WR and RD locks need to be rewritten (not simple boolean) */
+typedef struct {
+    const char *name;
+    uint16_t size;
+    uint16_t offset;
+    uint16_t digest_offset;
+    uint16_t zer_offset;
+    uint16_t hw_digest:1;
+    uint16_t sw_digest:1;
+    uint16_t secret:1;
+    uint16_t buffered:1;
+    uint16_t write_lock:1;
+    uint16_t read_lock:1;
+    uint16_t read_lock_csr:1;
+    uint16_t integrity:1;
+    uint16_t zeroizable:1;
+    uint16_t iskeymgr_creator:1;
+    uint16_t iskeymgr_owner:1;
+} OtOTPPartDesc;
+
+typedef struct {
+    unsigned partition;
+    unsigned offset; /* byte offset in partition */
+    unsigned size; /* size in bytes */
+} OtOTPKeySeed;
+
+
+/* Supported statuses */
+typedef enum {
+    OT_OTP_STATUS_NONE,
+    OT_OTP_STATUS_DAI, /* Direct Access Interface */
+    OT_OTP_STATUS_LCI, /* Life Cycle Interface */
+    OT_OTP_STATUS_COUNT
+} OtOTPStatus;
+
+struct OtOTPImplIfClass {
+    InterfaceClass parent_class;
+
+    /* Array of part_count partition descriptors */
+    const OtOTPPartDesc *part_descs;
+
+    /* Array of OTP_KEY_COUNT descriptors */
+    const OtOTPKeySeed *key_seeds;
+
+    /* Number of partition */
+    unsigned part_count;
+
+    /* Index of the life cycle partition in part_descs */
+    unsigned part_lc_num;
+
+    /* Number of SRAM KEY requester slots */
+    unsigned sram_key_req_slot_count;
+
+    /* Whether embedded flash support is present */
+    bool has_flash_support;
+
+    /* Whether zeroification feature is supported */
+    bool has_zer_support;
+
+    /*
+     * Update the R_STATUS register.
+     * The OTP concrete device should provide an implementation
+     *
+     * @dev the OTP device
+     * @error the error type to update
+     * @set whether to set or clear the error
+     */
+    void (*update_status_error)(OtOTPImplIf *dev, OtOTPStatus error, bool set);
+
+    /*
+     * Signal that power management has triggered the OTP initialization
+     * sequence. May be left unimplemented (NULL).
+     *
+     * @dev the OTP device
+     */
+    void (*signal_pwr_sequence)(OtOTPImplIf *dev);
+};
+
+#endif /* HW_OPENTITAN_OT_OTP_IMPL_IF_H */
diff --git a/include/hw/opentitan/ot_otp_ot_be.h b/include/hw/opentitan/ot_otp_ot_be.h
new file mode 100644
index 0000000000000..52705b2e97209
--- /dev/null
+++ b/include/hw/opentitan/ot_otp_ot_be.h
@@ -0,0 +1,34 @@
+/*
+ * QEMU OpenTitan OTP backend
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_OTP_OT_BE_H
+#define HW_OPENTITAN_OT_OTP_OT_BE_H
+
+#define TYPE_OT_OTP_OT_BE "ot-otp_ot_be"
+OBJECT_DECLARE_TYPE(OtOtpOtBeState, OtOtpOtBeClass, OT_OTP_OT_BE)
+
+#endif /* HW_OPENTITAN_OT_OTP_OT_BE_H */
diff --git a/include/hw/opentitan/ot_pinmux.h b/include/hw/opentitan/ot_pinmux.h
new file mode 100644
index 0000000000000..48557cc710ea7
--- /dev/null
+++ b/include/hw/opentitan/ot_pinmux.h
@@ -0,0 +1,65 @@
+/*
+ * QEMU OpenTitan PinMux device
+ *
+ * Copyright (c) 2023-2024 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_PINMUX_H
+#define HW_OPENTITAN_OT_PINMUX_H
+
+#include "qom/object.h"
+#include "hw/registerfields.h"
+
+#define TYPE_OT_PINMUX "ot-pinmux"
+
+#define OT_PINMUX_DIO TYPE_OT_PINMUX "-dio"
+#define OT_PINMUX_MIO TYPE_OT_PINMUX "-mio"
+#define OT_PINMUX_PAD TYPE_OT_PINMUX "-pad" /* for devices using pinmux pad */
+
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_INVERT, 0u, 1u)
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_VIRTUAL_OD_EN, 1u, 1u)
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_PULL_EN, 2u, 1u)
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_PULL_SELECT, 3u, 1u)
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_KEEPER_EN, 4u, 1u)
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_SCHMITT_EN, 5u, 1u)
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_OD_EN, 6u, 1u)
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_SLEW_RATE, 16u, 0x2u)
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_DRIVE_STRENGTH, 20u, 4u)
+SHARED_FIELD(OT_PINMUX_PAD_ATTR_FORCE_MODE, 28u, 2u)
+
+typedef enum {
+    OT_PINMUX_PAD_FORCE_IGNORE,
+    OT_PINMUX_PAD_FORCE_LOW,
+    OT_PINMUX_PAD_FORCE_HIGH,
+    OT_PINMUX_PAD_FORCE_HIZ,
+} OtPinmuxPadForceMode;
+
+#define OT_PINMUX_PAD_ATTR_MASK \
+    (OT_PINMUX_PAD_ATTR_INVERT_MASK | OT_PINMUX_PAD_ATTR_VIRTUAL_OD_EN_MASK | \
+     OT_PINMUX_PAD_ATTR_PULL_EN_MASK | OT_PINMUX_PAD_ATTR_PULL_SELECT_MASK | \
+     OT_PINMUX_PAD_ATTR_KEEPER_EN_MASK | OT_PINMUX_PAD_ATTR_SCHMITT_EN_MASK | \
+     OT_PINMUX_PAD_ATTR_OD_EN_MASK | OT_PINMUX_PAD_ATTR_SLEW_RATE_MASK | \
+     OT_PINMUX_PAD_ATTR_DRIVE_STRENGTH_MASK)
+
+#endif /* HW_OPENTITAN_OT_PINMUX_H */
diff --git a/include/hw/opentitan/ot_pinmux_dj.h b/include/hw/opentitan/ot_pinmux_dj.h
new file mode 100644
index 0000000000000..58fc77aa0127a
--- /dev/null
+++ b/include/hw/opentitan/ot_pinmux_dj.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan Darjeeling PinMux device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_PINMUX_DJ_H
+#define HW_OPENTITAN_OT_PINMUX_DJ_H
+
+#include "hw/opentitan/ot_pinmux.h"
+
+#define TYPE_OT_PINMUX_DJ TYPE_OT_PINMUX "-dj"
+OBJECT_DECLARE_TYPE(OtPinmuxDjState, OtPinmuxDjClass, OT_PINMUX_DJ)
+
+#endif /* HW_OPENTITAN_OT_PINMUX_DJ_H */
diff --git a/include/hw/opentitan/ot_pinmux_eg.h b/include/hw/opentitan/ot_pinmux_eg.h
new file mode 100644
index 0000000000000..20122898cfea0
--- /dev/null
+++ b/include/hw/opentitan/ot_pinmux_eg.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan EarlGrey PinMux device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_PINMUX_EG_H
+#define HW_OPENTITAN_OT_PINMUX_EG_H
+
+#include "hw/opentitan/ot_pinmux.h"
+
+#define TYPE_OT_PINMUX_EG TYPE_OT_PINMUX "-eg"
+OBJECT_DECLARE_TYPE(OtPinmuxEgState, OtPinmuxEgClass, OT_PINMUX_EG)
+
+#endif /* HW_OPENTITAN_OT_PINMUX_EG_H */
diff --git a/include/hw/opentitan/ot_plic_ext.h b/include/hw/opentitan/ot_plic_ext.h
new file mode 100644
index 0000000000000..e6c29f692e5fb
--- /dev/null
+++ b/include/hw/opentitan/ot_plic_ext.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan PLIC extension
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_PLIC_EXT_H
+#define HW_OPENTITAN_OT_PLIC_EXT_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_PLIC_EXT "ot-plic_ext"
+OBJECT_DECLARE_TYPE(OtPlicExtState, OtPlicExtClass, OT_PLIC_EXT)
+
+#endif /* HW_OPENTITAN_OT_PLIC_EXT_H */
diff --git a/include/hw/opentitan/ot_present.h b/include/hw/opentitan/ot_present.h
new file mode 100644
index 0000000000000..652c1bc5372c8
--- /dev/null
+++ b/include/hw/opentitan/ot_present.h
@@ -0,0 +1,21 @@
+/*
+ * QEMU OpenTitan Present 128-bit key cipher implementation
+ *
+ * Copyright lowRISC contributors.
+ *
+ * Licensed under the Apache License, Version 2.0, see LICENSE for details.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef HW_OPENTITAN_OT_PRESENT_H
+#define HW_OPENTITAN_OT_PRESENT_H
+
+typedef struct OtPresentState OtPresentState;
+
+OtPresentState *ot_present_new(void);
+void ot_present_init(OtPresentState *ps, const uint8_t *key);
+void ot_present_free(OtPresentState *ps);
+void ot_present_encrypt(const OtPresentState *ps, uint64_t src, uint64_t *dst);
+void ot_present_decrypt(const OtPresentState *ps, uint64_t src, uint64_t *dst);
+
+#endif /* HW_OPENTITAN_OT_PRESENT_H */
diff --git a/include/hw/opentitan/ot_prince.h b/include/hw/opentitan/ot_prince.h
new file mode 100644
index 0000000000000..b9a5d11c82646
--- /dev/null
+++ b/include/hw/opentitan/ot_prince.h
@@ -0,0 +1,16 @@
+/*
+ * QEMU OpenTitan Prince implementation
+ *
+ * Copyright (c) lowRISC contributors.
+ * Licensed under the Apache License, Version 2.0, see LICENSE for details.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef HW_OPENTITAN_OT_PRINCE_H
+#define HW_OPENTITAN_OT_PRINCE_H
+
+uint64_t ot_prince_run(uint64_t data, uint64_t khi, uint64_t klo,
+                       unsigned num_rounds_half);
+
+#endif /* HW_OPENTITAN_OT_PRINCE_H */
diff --git a/include/hw/opentitan/ot_prng.h b/include/hw/opentitan/ot_prng.h
new file mode 100644
index 0000000000000..a1d1d015bd80c
--- /dev/null
+++ b/include/hw/opentitan/ot_prng.h
@@ -0,0 +1,43 @@
+/*
+ * QEMU OpenTitan Pseudo Random Generator
+ *
+ * Copyright (c) 2023 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_PRNG_H
+#define HW_OPENTITAN_OT_PRNG_H
+
+#define TYPE_OT_PRNG "ot-prng"
+
+typedef struct OtPrngState OtPrngState;
+
+OtPrngState *ot_prng_allocate(void);
+void ot_prng_release(OtPrngState *prng);
+uint32_t ot_prng_random_u32(OtPrngState *prng);
+void ot_prng_random_u32_array(OtPrngState *prng, uint32_t *array, size_t count);
+void ot_prng_reseed(OtPrngState *prng, uint32_t seed);
+void ot_prng_reseed_array(OtPrngState *prng, const uint32_t *seed,
+                          size_t length);
+
+#endif /* HW_OPENTITAN_OT_PRNG_H */
diff --git a/include/hw/opentitan/ot_pwrmgr.h b/include/hw/opentitan/ot_pwrmgr.h
new file mode 100644
index 0000000000000..7811874c7e610
--- /dev/null
+++ b/include/hw/opentitan/ot_pwrmgr.h
@@ -0,0 +1,99 @@
+/*
+ * QEMU OpenTitan Power Manager device
+ *
+ * Copyright (c) 2023-2024 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_PWRMGR_H
+#define HW_OPENTITAN_OT_PWRMGR_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_PWRMGR "ot-pwrmgr"
+OBJECT_DECLARE_TYPE(OtPwrMgrState, OtPwrMgrClass, OT_PWRMGR)
+
+/* Supported PowerManager versions */
+typedef enum {
+    OT_PWRMGR_VERSION_EG_1_0_0,
+    OT_PWRMGR_VERSION_DJ,
+    OT_PWRMGR_VERSION_COUNT,
+} OtPwrMgrVersion;
+
+/* Union of PWRMGR_PARAM_*_WKUP_REQ_IDX definitions for all supported tops */
+typedef enum {
+    OT_PWRMGR_WAKEUP_SYSRST,
+    OT_PWRMGR_WAKEUP_ADC_CTRL,
+    OT_PWRMGR_WAKEUP_PINMUX,
+    OT_PWRMGR_WAKEUP_USBDEV,
+    OT_PWRMGR_WAKEUP_AON_TIMER,
+    OT_PWRMGR_WAKEUP_SENSOR,
+    OT_PWRMGR_WAKEUP_COUNT,
+} OtPwrMgrWakeup;
+
+#define OT_PWRMGR_MAX_ROM_CTRL_COUNT 3u
+#define OT_PWRMGR_MAX_ROM_COUNT      (OT_PWRMGR_MAX_ROM_CTRL_COUNT + 1u)
+
+/* Boot status packed as an IRQ */
+typedef union {
+    struct {
+        unsigned main_clk_status:1u; /* in pwr_clk_rsp_t */
+        unsigned io_clk_status:1u; /* in pwr_clk_rsp_t */
+        unsigned otp_done:1u;
+        unsigned lc_done:1u;
+        unsigned cpu_fetch_en:1u;
+        unsigned strap_sampled:1u;
+        unsigned light_reset:1u;
+        /* clang-format off */
+        unsigned rom_done:OT_PWRMGR_MAX_ROM_COUNT;
+        unsigned rom_good:OT_PWRMGR_MAX_ROM_COUNT;
+        unsigned rom_mask:OT_PWRMGR_MAX_ROM_COUNT;
+        /* clang-format on */
+    };
+    int i32;
+} OtPwrMgrBootStatus;
+
+/* output lines */
+#define OT_PWRMGR_LC_REQ      TYPE_OT_PWRMGR "-lc-req"
+#define OT_PWRMGR_OTP_REQ     TYPE_OT_PWRMGR "-otp-req"
+#define OT_PWRMGR_CPU_EN      TYPE_OT_PWRMGR "-cpu-en"
+#define OT_PWRMGR_STRAP       TYPE_OT_PWRMGR "-strap"
+#define OT_PWRMGR_RST_REQ     TYPE_OT_PWRMGR "-reset-req"
+#define OT_PWRMGR_BOOT_STATUS TYPE_OT_PWRMGR "-boot-status"
+
+/* input lines */
+#define OT_PWRMGR_LC_RSP  TYPE_OT_PWRMGR "-lc-rsp"
+#define OT_PWRMGR_OTP_RSP TYPE_OT_PWRMGR "-otp-rsp"
+
+#define OT_PWRMGR_WKUP   TYPE_OT_PWRMGR "-wkup"
+#define OT_PWRMGR_RST    TYPE_OT_PWRMGR "-rst"
+#define OT_PWRMGR_SW_RST TYPE_OT_PWRMGR "-sw-rst"
+
+#define OT_PWRMGR_ROM_GOOD TYPE_OT_PWRMGR "-rom-good"
+#define OT_PWRMGR_ROM_DONE TYPE_OT_PWRMGR "-rom-done"
+
+/* custom extension */
+#define OT_PWRMGR_HOLDON_FETCH TYPE_OT_PWRMGR "-holdon-fetch"
+
+#endif /* HW_OPENTITAN_OT_PWRMGR_H */
diff --git a/include/hw/opentitan/ot_rom_ctrl.h b/include/hw/opentitan/ot_rom_ctrl.h
new file mode 100644
index 0000000000000..c2448c24e733e
--- /dev/null
+++ b/include/hw/opentitan/ot_rom_ctrl.h
@@ -0,0 +1,54 @@
+/*
+ * QEMU OpenTitan ROM controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_ROM_CTRL
+#define HW_OPENTITAN_OT_ROM_CTRL
+
+#include "qom/object.h"
+
+#define TYPE_OT_ROM_CTRL "ot-rom_ctrl"
+OBJECT_DECLARE_TYPE(OtRomCtrlState, OtRomCtrlClass, OT_ROM_CTRL)
+
+#define OT_ROM_CTRL_GOOD TYPE_OT_ROM_CTRL "-good"
+#define OT_ROM_CTRL_DONE TYPE_OT_ROM_CTRL "-done"
+
+#define OT_ROM_DIGEST_BYTES 32u
+
+struct OtRomCtrlClass {
+    DeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    /*
+     * Retrieve ROM digest.
+     *
+     * @digest a pointer to an array that will be filled with the ROM digest
+     */
+    void (*get_rom_digest)(const OtRomCtrlState *s,
+                           uint8_t digest[OT_ROM_DIGEST_BYTES]);
+};
+
+#endif /* HW_OPENTITAN_OT_ROM_CTRL */
diff --git a/include/hw/opentitan/ot_rom_ctrl_img.h b/include/hw/opentitan/ot_rom_ctrl_img.h
new file mode 100644
index 0000000000000..7a2152cefd35f
--- /dev/null
+++ b/include/hw/opentitan/ot_rom_ctrl_img.h
@@ -0,0 +1,53 @@
+/*
+ * QEMU OpenTitan ROM image
+ *
+ * Copyright (c) 2023 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_ROM_CTRL_IMG
+#define HW_OPENTITAN_OT_ROM_CTRL_IMG
+
+#include "qom/object.h"
+
+#define TYPE_OT_ROM_IMG "ot-rom_img"
+OBJECT_DECLARE_SIMPLE_TYPE(OtRomImg, OT_ROM_IMG)
+
+typedef enum {
+    OT_ROM_IMG_FORMAT_NONE, /* invalid image */
+    OT_ROM_IMG_FORMAT_VMEM_PLAIN, /* 32-bit VMEM, no scrambling, no ECC */
+    OT_ROM_IMG_FORMAT_VMEM_SCRAMBLED_ECC, /* 39-bit VMEM, scrambled, ECC */
+    OT_ROM_IMG_FORMAT_HEX_SCRAMBLED_ECC, /* 39-bit raw HEX, scrambled, ECC */
+    OT_ROM_IMG_FORMAT_ELF, /* ELF32 file, no scrambling, no ECC */
+    OT_ROM_IMG_FORMAT_BINARY, /* RAW binary file */
+} OtRomImgFormat;
+
+struct OtRomImg {
+    Object parent_obj;
+    char *filename; /* full file path to the image file */
+    unsigned raw_size; /* size in bytes of the image file */
+    OtRomImgFormat format; /* guessed format of the image file */
+};
+
+#endif /* HW_OPENTITAN_OT_ROM_CTRL_IMG */
diff --git a/include/hw/opentitan/ot_rstmgr.h b/include/hw/opentitan/ot_rstmgr.h
new file mode 100644
index 0000000000000..fcaf9e569ffc0
--- /dev/null
+++ b/include/hw/opentitan/ot_rstmgr.h
@@ -0,0 +1,69 @@
+/*
+ * QEMU OpenTitan Reset Manager device
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_RSTMGR_H
+#define HW_OPENTITAN_OT_RSTMGR_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_RSTMGR "ot-rstmgr"
+OBJECT_DECLARE_TYPE(OtRstMgrState, OtRstMgrClass, OT_RSTMGR)
+
+/* Supported ResetManager versions */
+typedef enum {
+    OT_RSTMGR_VERSION_EG_1_0_0,
+    OT_RSTMGR_VERSION_DJ,
+    OT_RSTMGR_VERSION_COUNT,
+} OtRstMgrVersion;
+
+/* Some reset reasons may not exist on the current platform */
+typedef enum {
+    OT_RSTMGR_RESET_NONE,
+    OT_RSTMGR_RESET_POR,
+    OT_RSTMGR_RESET_LOW_POWER,
+    OT_RSTMGR_RESET_SW,
+    OT_RSTMGR_RESET_SYSCTRL,
+    OT_RSTMGR_RESET_SOC_PROXY,
+    OT_RSTMGR_RESET_AON_TIMER,
+    OT_RSTMGR_RESET_SENSOR,
+    OT_RSTMGR_RESET_PWRMGR,
+    OT_RSTMGR_RESET_ALERT_HANDLER,
+    OT_RSTMGR_RESET_RV_DM,
+    OT_RSTMGR_RESET_COUNT,
+} OtRstMgrResetReq;
+
+#define OT_RSTMGR_RESET_REQUEST(_fast_, _req_) \
+    ((int)((1u << 31u) | (((int)(bool)_fast_) << 8u) | _req_))
+
+/* output lines */
+#define OT_RSTMGR_SOC_RST TYPE_OT_RSTMGR "-soc-reset"
+#define OT_RSTMGR_SW_RST  TYPE_OT_RSTMGR "-sw-reset"
+
+/* input lines */
+#define OT_RSTMGR_RST_REQ TYPE_OT_RSTMGR "-reset-req"
+
+#endif /* HW_OPENTITAN_OT_RSTMGR_H */
diff --git a/include/hw/opentitan/ot_sensor_eg.h b/include/hw/opentitan/ot_sensor_eg.h
new file mode 100644
index 0000000000000..696bbe6071bcd
--- /dev/null
+++ b/include/hw/opentitan/ot_sensor_eg.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan Sensor controller device for EarlGrey
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_SENSOR_EG_H
+#define HW_OPENTITAN_OT_SENSOR_EG_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_SENSOR_EG "ot-sensor-eg"
+OBJECT_DECLARE_TYPE(OtSensorEgState, OtSensorEgClass, OT_SENSOR_EG)
+
+#endif /* HW_OPENTITAN_OT_SENSOR_EG_H */
diff --git a/include/hw/opentitan/ot_soc_dbg_ctrl.h b/include/hw/opentitan/ot_soc_dbg_ctrl.h
new file mode 100644
index 0000000000000..bb45b04a97b86
--- /dev/null
+++ b/include/hw/opentitan/ot_soc_dbg_ctrl.h
@@ -0,0 +1,74 @@
+/*
+ * QEMU OpenTitan SoC Debug Controller
+ *
+ * Copyright (c) 2024-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_SOC_DBG_CTRL_H
+#define HW_OPENTITAN_OT_SOC_DBG_CTRL_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_SOC_DBG_CTRL "ot-soc_dbg_ctrl"
+OBJECT_DECLARE_TYPE(OtSoCDbgCtrlState, OtSoCDbgCtrlClass, OT_SOC_DBG_CTRL)
+
+/* SocDbg controller states */
+typedef enum {
+    OT_SOC_DBG_ST_BLANK,
+    OT_SOC_DBG_ST_PRE_PROD,
+    OT_SOC_DBG_ST_PROD,
+    OT_SOC_DBG_ST_COUNT,
+} OtSoCDbgState;
+
+/* Signal carried over OT_SOC_DBG_DEBUG_POLICY */
+typedef union {
+    struct {
+        /*
+         * Active categories:
+         * b0..b1: unused
+         * b2: CAT2
+         * b3: CAT3
+         * b4: CAT4
+         * b5..b7: unused
+         */
+        uint8_t cat_bm;
+        bool relocked;
+    };
+    int i32;
+} OtSocDbgDebugPolicy;
+
+/* input lines */
+#define OT_SOC_DBG_HALT_CPU_BOOT TYPE_OT_SOC_DBG_CTRL "-halt-cpu-boot"
+#define OT_SOC_DBG_LC_BCAST      TYPE_OT_SOC_DBG_CTRL "-lc-broadcast"
+#define OT_SOC_DBG_STATE         TYPE_OT_SOC_DBG_CTRL "-soc-dbg"
+#define OT_SOC_DBG_BOOT_STATUS   TYPE_OT_SOC_DBG_CTRL "-boot-status"
+
+/* output lines */
+#define OT_SOC_DBG_CONTINUE_CPU_BOOT TYPE_OT_SOC_DBG_CTRL "-continue-cpu-boot"
+#define OT_SOC_DBG_DEBUG_POLICY      TYPE_OT_SOC_DBG_CTRL "-debug-policy"
+
+#define OT_SOC_DBG_DEBUG_POLICY_MASK 0x0fu
+#define OT_SOC_DBG_DEBUG_VALID_MASK  0x80u
+
+#endif /* HW_OPENTITAN_OT_SOC_DBG_CTRL_H */
diff --git a/include/hw/opentitan/ot_soc_proxy.h b/include/hw/opentitan/ot_soc_proxy.h
new file mode 100644
index 0000000000000..99d320cc8c295
--- /dev/null
+++ b/include/hw/opentitan/ot_soc_proxy.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU OpenTitan SocProxy
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_SOC_PROXY_H
+#define HW_OPENTITAN_OT_SOC_PROXY_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_SOC_PROXY "ot-soc_proxy"
+OBJECT_DECLARE_TYPE(OtSoCProxyState, OtSoCProxyClass, OT_SOC_PROXY)
+
+#define OT_SOC_PROXY_REGS_COUNT 4u
+
+#endif /* HW_OPENTITAN_OT_SOC_PROXY_H */
diff --git a/include/hw/opentitan/ot_spi_device.h b/include/hw/opentitan/ot_spi_device.h
new file mode 100644
index 0000000000000..ff4146058b91f
--- /dev/null
+++ b/include/hw/opentitan/ot_spi_device.h
@@ -0,0 +1,42 @@
+/*
+ * QEMU OpenTitan SPI Device controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_SPI_DEVICE_H
+#define HW_OPENTITAN_OT_SPI_DEVICE_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_SPI_DEVICE "ot-spi_device"
+OBJECT_DECLARE_TYPE(OtSPIDeviceState, OtSPIDeviceClass, OT_SPI_DEVICE)
+
+/* IRQ lines to downstream OT SPI Host */
+#define OT_SPI_DEVICE_PASSTHROUGH_EN (TYPE_OT_SPI_DEVICE "-passthrough-en")
+#define OT_SPI_DEVICE_PASSTHROUGH_CS (TYPE_OT_SPI_DEVICE "-passthrough-cs")
+
+#endif /* HW_OPENTITAN_OT_SPI_DEVICE_H */
diff --git a/include/hw/opentitan/ot_spi_host.h b/include/hw/opentitan/ot_spi_host.h
new file mode 100644
index 0000000000000..b71a196cda1c0
--- /dev/null
+++ b/include/hw/opentitan/ot_spi_host.h
@@ -0,0 +1,64 @@
+/*
+ * QEMU OpenTitan SPI Host controller
+ *
+ * Copyright (C) 2022 Western Digital
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Wilfred Mallawa <wilfred.mallawa@wdc.com>
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_SPI_HOST_H
+#define HW_OPENTITAN_OT_SPI_HOST_H
+
+#include "qom/object.h"
+#include "hw/resettable.h"
+#include "hw/sysbus.h"
+
+#define TYPE_OT_SPI_HOST "ot-spi_host"
+OBJECT_DECLARE_TYPE(OtSPIHostState, OtSPIHostClass, OT_SPI_HOST)
+
+/* this class is only required to manage on-hold reset */
+struct OtSPIHostClass {
+    SysBusDeviceClass parent_class;
+
+    /*
+     * Transfer a byte over this downstream SPI Host's SPI bus.
+     * If Passthrough Enable is not asserted, or the SPI Host supports more
+     * than one Chip Select, the transfer does not take place on the bus and a
+     * default value is returned.
+     *
+     * @tx byte to be transferred
+     * @return received byte from SPI bus, or a default value
+     */
+    uint8_t (*ssi_downstream_transfer)(OtSPIHostState *, uint8_t tx);
+
+    ResettablePhases parent_phases;
+};
+
+/* IRQ lines from upstream OT SPI Device */
+#define OT_SPI_HOST_PASSTHROUGH_EN (TYPE_OT_SPI_HOST "-passthrough-en")
+#define OT_SPI_HOST_PASSTHROUGH_CS (TYPE_OT_SPI_HOST "-passthrough-cs")
+
+#endif /* HW_OPENTITAN_OT_SPI_HOST_H */
diff --git a/include/hw/opentitan/ot_sram_ctrl.h b/include/hw/opentitan/ot_sram_ctrl.h
new file mode 100644
index 0000000000000..a502b6e5aeffc
--- /dev/null
+++ b/include/hw/opentitan/ot_sram_ctrl.h
@@ -0,0 +1,39 @@
+/*
+ * QEMU OpenTitan SRAM controller
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_SRAM_CTRL
+#define HW_OPENTITAN_OT_SRAM_CTRL
+
+#include "qom/object.h"
+
+#define TYPE_OT_SRAM_CTRL "ot-sram_ctrl"
+OBJECT_DECLARE_TYPE(OtSramCtrlState, OtSramCtrlClass, OT_SRAM_CTRL)
+
+/* Input HW_DEBUG_EN signal for SRAM ifetch (from lifecycle controller) */
+#define OT_SRAM_CTRL_HW_DEBUG_EN TYPE_OT_SRAM_CTRL "-hw_debug_en"
+
+#endif /* HW_OPENTITAN_OT_SRAM_CTRL */
diff --git a/include/hw/opentitan/ot_timer.h b/include/hw/opentitan/ot_timer.h
new file mode 100644
index 0000000000000..e043c9ba85630
--- /dev/null
+++ b/include/hw/opentitan/ot_timer.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan Timer device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_TIMER_H
+#define HW_OPENTITAN_OT_TIMER_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_TIMER "ot-timer"
+OBJECT_DECLARE_TYPE(OtTimerState, OtTimerClass, OT_TIMER)
+
+#endif /* HW_OPENTITAN_OT_TIMER_H */
diff --git a/include/hw/opentitan/ot_uart.h b/include/hw/opentitan/ot_uart.h
new file mode 100644
index 0000000000000..f334f7b9ce06e
--- /dev/null
+++ b/include/hw/opentitan/ot_uart.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan UART device
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_UART_H
+#define HW_OPENTITAN_OT_UART_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_UART "ot-uart"
+OBJECT_DECLARE_TYPE(OtUARTState, OtUARTClass, OT_UART)
+
+#endif /* HW_OPENTITAN_OT_UART_H */
diff --git a/include/hw/opentitan/ot_unimp.h b/include/hw/opentitan/ot_unimp.h
new file mode 100644
index 0000000000000..64012d4c32cbb
--- /dev/null
+++ b/include/hw/opentitan/ot_unimp.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenTitan unimplemented device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_UNIMP_H
+#define HW_OPENTITAN_OT_UNIMP_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_UNIMP "ot-unimp"
+OBJECT_DECLARE_TYPE(OtUnimpState, OtUnimpClass, OT_UNIMP)
+
+#endif /* HW_OPENTITAN_OT_UNIMP_H */
diff --git a/include/hw/opentitan/ot_usbdev.h b/include/hw/opentitan/ot_usbdev.h
new file mode 100644
index 0000000000000..1b578e83747c8
--- /dev/null
+++ b/include/hw/opentitan/ot_usbdev.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU OpenTitan USBDEV device
+ *
+ * Copyright (c) 2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Amaury Pouly <amaury.pouly@lowrisc.org>
+ *  Douglas Reis <doreis@lowrisc.org>
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#ifndef HW_OPENTITAN_OT_USBDEV_H
+#define HW_OPENTITAN_OT_USBDEV_H
+
+#include "qom/object.h"
+
+#define TYPE_OT_USBDEV "ot-usbdev"
+OBJECT_DECLARE_TYPE(OtUsbdevState, OtUsbdevClass, OT_USBDEV)
+
+#endif /* HW_OPENTITAN_OT_USBDEV_H */
diff --git a/include/hw/opentitan/ot_vmapper.h b/include/hw/opentitan/ot_vmapper.h
new file mode 100644
index 0000000000000..94ac33c4a54e3
--- /dev/null
+++ b/include/hw/opentitan/ot_vmapper.h
@@ -0,0 +1,71 @@
+/*
+ * QEMU OpenTitan virtual mapper device
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_OPENTITAN_OT_VMAPPER_H
+#define HW_OPENTITAN_OT_VMAPPER_H
+
+#include "qom/object.h"
+#include "exec/hwaddr.h"
+#include "system/memory.h"
+
+#define TYPE_OT_VMAPPER "ot-vmapper"
+OBJECT_DECLARE_TYPE(OtVMapperState, OtVMapperClass, OT_VMAPPER)
+
+/*
+ * Configure the address translation for an address range.
+ *
+ * @insn whether the translation is for an instruction.
+ * @slot the execution slot to use for the translation.
+ * @src the first address of the range to match.
+ * @dst the first physical address of the range to translate to.
+ * @size the size (extentof the range to match. If 0, disable the translation
+ *       for the selected slot.
+ */
+typedef void (*OtVMapperTranslate)(OtVMapperState *s, bool insn, unsigned slot,
+                                   hwaddr src, hwaddr dst, size_t size);
+
+/*
+ * Disable the execution of an address range.
+ *
+ * @mr the memory region to manage
+ * @disable whether to disable execution or (re-)enable it
+ */
+typedef void (*OtVMapperDisableExec)(OtVMapperState *s, const MemoryRegion *mr,
+                                     bool disable);
+
+struct OtVMapperClass {
+    DeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    OtVMapperTranslate translate;
+    OtVMapperDisableExec disable_exec;
+
+    OtVMapperState **instances;
+    unsigned num_instances;
+};
+
+#endif /* HW_OPENTITAN_OT_VMAPPER_H */
diff --git a/include/hw/opentitan/otbn/otbnproxy.h b/include/hw/opentitan/otbn/otbnproxy.h
new file mode 100644
index 0000000000000..2d5080b6cf5d2
--- /dev/null
+++ b/include/hw/opentitan/otbn/otbnproxy.h
@@ -0,0 +1,92 @@
+/*
+ * QEMU OpenTitan BigNumber proxy API
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_OPENTITAN_OTBN_PROXY_H
+#define HW_OPENTITAN_OTBN_PROXY_H
+
+#include "qemu/typedefs.h"
+
+/*
+ * The Unsafe Code Guidelines also notably defines that usize and isize are
+ * respectively compatible with uintptr_t and intptr_t defined in C, while rust
+ * does not explicitly guarantee compatibility between usize and size_t
+ */
+
+typedef void *OTBNProxy;
+
+typedef void (*ot_otbn_signal_completion_fn)(void *opaque);
+typedef void (*ot_otbn_fetch_entropy_fn)(void *opaque);
+
+enum OtOTBNCommand {
+    OT_OTBN_CMD_NONE = 0x00,
+    OT_OTBN_CMD_EXECUTE = 0xD8,
+    OT_OTBN_CMD_SEC_WIPE_DMEM = 0xC3,
+    OT_OTBN_CMD_SEC_WIDE_IMEM = 0x1E,
+};
+
+enum OtOTBNStatus {
+    OT_OTBN_STATUS_IDLE = 0x00,
+    OT_OTBN_STATUS_BUSY_EXECUTE = 0x01,
+    OT_OTBN_STATUS_BUSY_SEC_WIPE_DMEM = 0x02,
+    OT_OTBN_STATUS_BUSY_SEC_WIPE_IMEM = 0x03,
+    OT_OTBN_STATUS_BUSY_SEC_WIPE_INT = 0x04,
+    OT_OTBN_STATUS_LOCKED = 0xFF,
+};
+
+enum OtOTBNRandomSource { OT_OTBN_URND, OT_OTBN_RND, OT_OTBN_RND_COUNT };
+
+#define OT_OTBN_IMEM_SIZE (8U << 10U)
+#define OT_OTBN_DMEM_SIZE (3U << 10U)
+
+#define OT_OTBN_RANDOM_BIT_WIDTH 256u
+#define OT_OTBN_RANDOM_WORD_COUNT \
+    ((OT_OTBN_RANDOM_BIT_WIDTH) / (8u * sizeof(uint32_t)))
+
+extern OTBNProxy
+ot_otbn_proxy_new(ot_otbn_fetch_entropy_fn urnd_req_entropy, void *urnd_opaque,
+                  ot_otbn_fetch_entropy_fn rnd_req_entropy, void *rnd_opaque,
+                  ot_otbn_signal_completion_fn signal, void *on_comp_opaque);
+extern void ot_otbn_proxy_start(OTBNProxy proxy, bool test_mode,
+                                const char *logname, bool log_asm);
+extern void ot_otbn_proxy_terminate(OTBNProxy proxy);
+extern bool ot_otbn_proxy_push_entropy(OTBNProxy proxy, uint32_t rndix,
+                                       const uint8_t *seed, uint32_t len,
+                                       bool fips);
+extern bool ot_otbn_proxy_push_key(OTBNProxy proxy, const uint8_t *share0,
+                                   const uint8_t *share1, uint32_t len,
+                                   bool valid);
+extern int ot_otbn_proxy_execute(OTBNProxy proxy, bool dumpstate);
+extern int ot_otbn_proxy_wipe_memory(OTBNProxy proxy, bool doi);
+extern bool ot_otbn_proxy_acknowledge_execution(OTBNProxy proxy);
+extern uint32_t
+ot_otbn_proxy_read_memory(OTBNProxy proxy, bool doi, uint32_t addr);
+extern bool ot_otbn_proxy_write_memory(OTBNProxy proxy, bool doi, uint32_t addr,
+                                       uint32_t val);
+extern enum OtOTBNStatus ot_otbn_proxy_get_status(OTBNProxy proxy);
+extern uint32_t ot_otbn_proxy_get_instruction_count(OTBNProxy proxy);
+extern void
+ot_otbn_proxy_set_instruction_count(OTBNProxy proxy, uint32_t value);
+extern uint32_t ot_otbn_proxy_get_err_bits(OTBNProxy proxy);
+extern void ot_otbn_proxy_set_err_bits(OTBNProxy proxy, uint32_t value);
+extern bool ot_otbn_proxy_get_ctrl(OTBNProxy proxy);
+extern void ot_otbn_proxy_set_ctrl(OTBNProxy proxy, bool value);
+
+#endif /* HW_OPENTITAN_OTBN_PROXY_H */
diff --git a/include/hw/riscv/debug.h b/include/hw/riscv/debug.h
new file mode 100644
index 0000000000000..67925c2bd87c4
--- /dev/null
+++ b/include/hw/riscv/debug.h
@@ -0,0 +1,77 @@
+/*
+ * QEMU RISC-V Debug
+ *
+ * Copyright (c) 2023-2024 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_RISCV_DEBUG_H
+#define HW_RISCV_DEBUG_H
+
+#include "qom/object.h"
+#include "hw/qdev-core.h"
+#include "hw/sysbus.h"
+
+#define RISCV_DEBUG_PREFIX "riscv-debug"
+
+#define TYPE_RISCV_DEBUG_DEVICE RISCV_DEBUG_PREFIX "_device"
+OBJECT_DECLARE_TYPE(RISCVDebugDeviceState, RISCVDebugDeviceClass,
+                    RISCV_DEBUG_DEVICE)
+
+typedef enum RISCVDebugResult {
+    RISCV_DEBUG_NOERR, /* Previous operation completed successfully */
+    RISCV_DEBUG_RSV, /* Reserved value, eq. to FAILED */
+    RISCV_DEBUG_FAILED, /* Previous operation failed */
+    RISCV_DEBUG_BUSY, /* New op. while a DMI request is still in progress */
+} RISCVDebugResult;
+
+/* Debug Module Interface access */
+struct RISCVDebugDeviceClass {
+    DeviceClass parent_class;
+
+    /*
+     * Debugger request to write to address.
+     */
+    RISCVDebugResult (*write_rq)(RISCVDebugDeviceState *dev, uint32_t addr,
+                                 uint32_t value);
+
+    /*
+     * Debugger request to read from address.
+     */
+    RISCVDebugResult (*read_rq)(RISCVDebugDeviceState *dev, uint32_t addr);
+
+    /*
+     * Read back value.
+     */
+    uint32_t (*read_value)(RISCVDebugDeviceState *dev);
+
+    /*
+     * Set next DM address
+     */
+    void (*set_next_dm)(RISCVDebugDeviceState *dev, uint32_t addr);
+};
+
+struct RISCVDebugDeviceState {
+    DeviceState parent_obj;
+};
+
+#endif /* HW_RISCV_DEBUG_H */
diff --git a/include/hw/riscv/dm.h b/include/hw/riscv/dm.h
new file mode 100644
index 0000000000000..845697fff5113
--- /dev/null
+++ b/include/hw/riscv/dm.h
@@ -0,0 +1,62 @@
+/*
+ * QEMU RISC-V Debug Module
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_RISCV_DM_H
+#define HW_RISCV_DM_H
+
+#include "qom/object.h"
+#include "exec/memattrs.h"
+
+#define TYPE_RISCV_DM "riscv-dm"
+OBJECT_DECLARE_TYPE(RISCVDMState, RISCVDMClass, RISCV_DM)
+
+#define RISCV_DM_ACK_LINES TYPE_RISCV_DM ".ack"
+
+/*
+ * Note: these offsets depends on the debug module implementation, so they
+ * should be better defined as yet another configurable properties
+ */
+#define RISCV_DM_HALTED_OFFSET    0x100u
+#define RISCV_DM_GOING_OFFSET     0x104u
+#define RISCV_DM_RESUMING_OFFSET  0x108u
+#define RISCV_DM_EXCEPTION_OFFSET 0x10cu
+#define RISCV_DM_FLAGS_OFFSET     0x400u
+
+enum RISCVDMAckInterface {
+    ACK_HALTED, /* HartID of the hart that has been halted */
+    ACK_GOING, /* A hart has started execution */
+    ACK_RESUMING, /* HardID of the hart that has resumed non-debug op. */
+    ACK_EXCEPTION, /* An exception has occured in debug mode */
+    ACK_COUNT, /* Count of acknownledgement lines */
+};
+
+/* Simple helper to define MemTxAttrs properties as uint64_t values */
+typedef union {
+    MemTxAttrs attrs;
+    uint64_t value;
+} RISCVDMMemAttrs;
+
+#endif /* HW_RISCV_DM_H */
diff --git a/include/hw/riscv/dtm.h b/include/hw/riscv/dtm.h
new file mode 100644
index 0000000000000..35d53e5db356f
--- /dev/null
+++ b/include/hw/riscv/dtm.h
@@ -0,0 +1,66 @@
+/*
+ * QEMU RISC-V Debug Tranport Module
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_RISCV_DTM_H
+#define HW_RISCV_DTM_H
+
+#include "qom/object.h"
+#include "exec/hwaddr.h"
+#include "hw/resettable.h"
+#include "hw/riscv/debug.h"
+
+#define TYPE_RISCV_DTM "riscv.dtm"
+OBJECT_DECLARE_TYPE(RISCVDTMState, RISCVDTMClass, RISCV_DTM)
+
+struct RISCVDTMClass {
+    DeviceClass parent_class;
+    ResettablePhases parent_phases;
+
+    /*
+     * Register a debug module on the Debug Transport Module.
+     * It is valid to register the same module multiple time, as long as
+     * base_addr and size are not modified.
+     *
+     * @dev the DTM instance
+     * @dmif the DM to register
+     * @base_addr the address of the first DM register
+     * @size the count of DM registers
+     * @enable whether the DM should be immediately enabled or not
+     * @return @c true if DTM is enabled, @c false otherwise
+     */
+    bool (*register_dm)(DeviceState *dev, RISCVDebugDeviceState *dbgdev,
+                        hwaddr base_addr, hwaddr size, bool enable);
+
+    /*
+     * Change the activation state of an already registered Debug Module.
+     * When disabled, the Debug Module can no longer be accessed from the DTM,
+     * and is removed from the "next_dm" chain.
+     */
+    void (*enable_dm)(DeviceState *dev, RISCVDebugDeviceState *dbgdev,
+                      bool enable);
+};
+
+#endif /* HW_RISCV_DTM_H */
diff --git a/include/hw/riscv/ibex_clock_src.h b/include/hw/riscv/ibex_clock_src.h
new file mode 100644
index 0000000000000..6c1fbd5cccfce
--- /dev/null
+++ b/include/hw/riscv/ibex_clock_src.h
@@ -0,0 +1,58 @@
+/*
+ * QEMU Ibex Clock Source interface
+ *
+ * Copyright (c) 2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_RISCV_IBEX_CLOCK_SRC_H
+#define HW_RISCV_IBEX_CLOCK_SRC_H
+
+#include "qom/object.h"
+
+#define TYPE_IBEX_CLOCK_SRC_IF "ibex-clock_src_if"
+typedef struct IbexClockSrcIfClass IbexClockSrcIfClass;
+DECLARE_CLASS_CHECKERS(IbexClockSrcIfClass, IBEX_CLOCK_SRC_IF,
+                       TYPE_IBEX_CLOCK_SRC_IF)
+#define IBEX_CLOCK_SRC_IF(_obj_) \
+    INTERFACE_CHECK(IbexClockSrcIf, (_obj_), TYPE_IBEX_CLOCK_SRC_IF)
+
+typedef struct IbexClockSrcIf IbexClockSrcIf;
+
+struct IbexClockSrcIfClass {
+    InterfaceClass parent_class;
+
+    /*
+     * Get a clock source by its type/name, to connect to the specified sink
+     * device. The clock line may already be connected or not.
+     *
+     * @name clock name
+     * @sink the sink device for the clock line
+     * @errp the error to use for reporting an invalid request
+     * @return the name of IRQ line to carry the clock information
+     */
+    const char *(*get_clock_source)(IbexClockSrcIf *ifd, const char *name,
+                                    const DeviceState *sink, Error **errp);
+};
+
+#endif /* HW_RISCV_IBEX_CLOCK_SRC_H */
diff --git a/include/hw/riscv/ibex_common.h b/include/hw/riscv/ibex_common.h
new file mode 100644
index 0000000000000..459f011a244f0
--- /dev/null
+++ b/include/hw/riscv/ibex_common.h
@@ -0,0 +1,637 @@
+/*
+ * QEMU RISC-V Helpers for LowRISC Ibex Demo System & OpenTitan EarlGrey
+ *
+ * Copyright (c) 2022-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_IBEX_COMMON_H
+#define HW_RISCV_IBEX_COMMON_H
+
+#include "qom/object.h"
+#include "exec/hwaddr.h"
+#include "hw/qdev-core.h"
+#include "hw/sysbus.h"
+
+/* ------------------------------------------------------------------------ */
+/* PMP configuration */
+/* ------------------------------------------------------------------------ */
+
+#define IBEX_PMP_CFG(_l_, _a_, _x_, _w_, _r_) \
+    ((uint8_t)(((_l_) << 7u) | ((_a_) << 3u) | ((_x_) << 2u) | ((_w_) << 1u) | \
+               ((_r_))))
+#define IBEX_PMP_ADDR(_a_) ((_a_) >> 2u)
+
+#define IBEX_MSECCFG(_rlb_, _mmwp_, _mml_) \
+    (((_rlb_) << 2u) | ((_mmwp_) << 1u) | ((_mml_)))
+
+
+/* clang-format off */
+
+enum {
+    IBEX_PMP_MODE_OFF,
+    IBEX_PMP_MODE_TOR,
+    IBEX_PMP_MODE_NA4,
+    IBEX_PMP_MODE_NAPOT
+};
+
+/* clang-format on */
+
+/* ------------------------------------------------------------------------ */
+/* JTAG */
+/* ------------------------------------------------------------------------ */
+
+#define IBEX_JTAG_PART_NUM(_part_, _tap_) \
+    ((((_part_) & 0xfffu) << 4u) | ((_tap_) & 0xfu))
+
+#define LOWRISC_JEDEC_MANUFACTURER_ID 0x6fu /* MSB is parity bit, ignored */
+#define LOWRISC_JEDEC_TABLE           13u
+#define IBEX_TAP_IR_LENGTH            5u
+
+#define LOWRISC_JEDEC_MID \
+    JEDEC_MANUFACTURER_ID(LOWRISC_JEDEC_TABLE, LOWRISC_JEDEC_MANUFACTURER_ID)
+#define IBEX_JTAG_IDCODE(_part_, _tap_, _ver_) \
+    JTAG_IDCODE(LOWRISC_JEDEC_MID, IBEX_JTAG_PART_NUM(_part_, _tap_), _ver_)
+
+/* ------------------------------------------------------------------------ */
+/* Devices & GPIOs */
+/* ------------------------------------------------------------------------ */
+
+#define IBEX_MAX_MMIO_ENTRIES 4u
+#define IBEX_MAX_GPIO_ENTRIES 16u
+
+typedef struct IbexDeviceDef IbexDeviceDef;
+
+typedef void (*ibex_dev_cfg_fn)(DeviceState *dev, const IbexDeviceDef *def,
+                                DeviceState *parent);
+
+/*
+ * Structure defining a GPIO connection (in particular, IRQs) from the current
+ * device to a target device
+ */
+typedef struct {
+    /* Source GPIO */
+    struct {
+        /* Name of source GPIO array or NULL for unnamed */
+        const char *name;
+        /* Index of source output GPIO */
+        int num;
+    } out;
+
+    /* Target GPIO */
+    struct {
+        /* Target device index */
+        int index;
+        /* Name of target input GPIO array or NULL for unnamed */
+        const char *name;
+        /* Index of target input GPIO */
+        int num;
+    } in;
+} IbexGpioConnDef;
+
+/*
+ * Structure defining the export of a device GPIO connection to the parent level
+ */
+typedef struct {
+    /* Device GPIO */
+    struct {
+        /* Name of device GPIO array or NULL for unnamed */
+        const char *name;
+        /* Index of device GPIO */
+        int num;
+    } device;
+
+    /* Parent GPIO */
+    struct {
+        /* Name of parent GPIO array or NULL for unnamed */
+        const char *name;
+        /* Index of parent GPIO */
+        int num;
+    } parent;
+} IbexGpioExportDef;
+
+typedef struct {
+    /* Name of the property to assign the linked device to */
+    const char *propname;
+    /* Linked device index */
+    int index;
+} IbexDeviceLinkDef;
+
+typedef struct {
+    /* Clock source */
+    struct {
+        /* Clock source device index */
+        int index;
+        /* Clock name */
+        const char *name;
+    } out;
+    /* Clock sink */
+    struct {
+        /* Name of target input clock */
+        const char *name;
+        /* Index of target input clock */
+        int num;
+    } in;
+} IbexClockConnDef;
+
+/* Type of device property */
+typedef enum {
+    IBEX_PROP_TYPE_BOOL,
+    IBEX_PROP_TYPE_INT,
+    IBEX_PROP_TYPE_UINT,
+    IBEX_PROP_TYPE_STR,
+} IbexPropertyType;
+
+typedef struct {
+    /* Name of the property */
+    const char *propname;
+    /* Type of property */
+    IbexPropertyType type;
+    /* Value */
+    union {
+        bool b;
+        int64_t i;
+        uint64_t u;
+        const char *s;
+    };
+} IbexDevicePropDef;
+
+typedef enum {
+    IBEX_MEM_MAP_ENTRY_FLAG_LAST,
+    IBEX_MEM_MAP_ENTRY_FLAG_SKIP,
+    IBEX_MEM_MAP_ENTRY_FLAG_COUNT
+} IbexMemMapEntryFlags;
+
+typedef struct IbexMemMapEntry {
+    hwaddr base;
+    int8_t priority;
+    uint8_t flags; /* bitfield of IbexMemMapEntryFlags */
+} IbexMemMapEntry;
+
+#define IBEX_MEM_MAP_ENTRY_FLAG(_f_) (1u << (IBEX_MEM_MAP_ENTRY_FLAG_##_f_))
+
+#define IBEX_INSTANCE_FLAG           (1u << 31u)
+#define IBEX_MAKE_INSTANCE_NUM(_ix_) (IBEX_INSTANCE_FLAG | (_ix_))
+#define IBEX_HAS_INSTANCE_NUM(_def_) \
+    ((bool)(((_def_)->instance & IBEX_INSTANCE_FLAG)))
+#define IBEX_GET_INSTANCE_NUM(_def_) \
+    (IBEX_HAS_INSTANCE_NUM(_def_) ? \
+         ((_def_)->instance & ~IBEX_INSTANCE_FLAG) : \
+         UINT32_MAX)
+
+/* Device definition */
+struct IbexDeviceDef {
+    /* Registered type of the device */
+    const char *type;
+    /* Optional name, may be NULL */
+    const char *name;
+    /*
+     * Instance number, default to auto-numbering, using a monotonic incremental
+     * value following the declaration order. Use IBEX_MAKE_INSTANCE_NUM macro
+     * to specify a unique instance of the type, when an instance needs to be
+     * explictly referenced by its instance number.
+     */
+    unsigned instance;
+    /* Optional configuration function */
+    ibex_dev_cfg_fn cfg;
+    /* Array of memory map */
+    const IbexMemMapEntry *memmap;
+    /* Array of GPIO connections */
+    const IbexGpioConnDef *gpio;
+    /* Array of linked devices */
+    const IbexDeviceLinkDef *link;
+    /* Array of properties */
+    const IbexDevicePropDef *prop;
+    /* Array of clock sources */
+    const IbexClockConnDef *clock;
+    /* Array of GPIO export */
+    const IbexGpioExportDef *gpio_export;
+};
+
+/* Additional device mapping for external buses */
+typedef struct {
+    /* Registered type of the device */
+    const char *type;
+    /* Instance number, default to 0 */
+    int instance;
+    /* Array of memory map */
+    const IbexMemMapEntry *memmap;
+} IbexDeviceMapDef;
+
+/*
+ * Special memory address marked to flag a special MemMapEntry.
+ * Flagged MemMapEntry are used to select a memory region while mem mapping
+ * devices. There could be up to 4 different regions.
+ */
+#define IBEX_MEMMAP_REGIDX_COUNT 4u
+#define IBEX_MEMMAP_REGIDX_MASK \
+    ((IBEX_MEMMAP_REGIDX_COUNT) - 1u) /* address are always word-aligned */
+#define IBEX_MEMMAP_MAKE_REG(_addr_, _flag_) \
+    ((_addr_) | (((uint32_t)_flag_) & IBEX_MEMMAP_REGIDX_MASK))
+#define IBEX_MEMMAP_MAKE_REG_MASK(_flag_) (1u << (_flag_))
+#define IBEX_MEMMAP_DEFAULT_REG_MASK      (1u << 0u)
+#define IBEX_MEMMAP_GET_REGIDX(_addr_)    ((_addr_) & IBEX_MEMMAP_REGIDX_MASK)
+#define IBEX_MEMMAP_GET_ADDRESS(_addr_)   ((_addr_) & ~IBEX_MEMMAP_REGIDX_MASK)
+
+#define IBEX_GPIO_GRP_BITS       5u
+#define IBEX_GPIO_GRP_COUNT      (1u << (IBEX_GPIO_GRP_BITS))
+#define IBEX_GPIO_GRP_SHIFT      (32u - IBEX_GPIO_GRP_BITS)
+#define IBEX_GPIO_GRP_MASK       ((IBEX_GPIO_GRP_COUNT) - 1u) << (IBEX_GPIO_GRP_SHIFT)
+#define IBEX_GPIO_IDX_MASK       (~(IBEX_GPIO_GRP_MASK))
+#define IBEX_GPIO_GET_IDX(_idx_) ((_idx_) & IBEX_GPIO_IDX_MASK)
+#define IBEX_GPIO_GET_GRP(_idx_) \
+    (((_idx_) & (IBEX_GPIO_GRP_MASK)) >> IBEX_GPIO_GRP_SHIFT)
+#define IBEX_GPIO_MAKE_GRPIDX(_grp_, _ix_) \
+    (((_grp_) << IBEX_GPIO_GRP_SHIFT) | ((_ix_) & IBEX_GPIO_IDX_MASK))
+
+#define IBEX_DEVLINK_RMT_BITS  8u
+#define IBEX_DEVLINK_RMT_COUNT (1u << (IBEX_DEVLINK_RMT_BITS))
+#define IBEX_DEVLINK_RMT_SHIFT (32u - IBEX_DEVLINK_RMT_BITS)
+#define IBEX_DEVLINK_RMT_MASK \
+    ((IBEX_DEVLINK_RMT_COUNT) - 1u) << (IBEX_DEVLINK_RMT_SHIFT)
+#define IBEX_DEVLINK_IDX_MASK      (~(IBEX_DEVLINK_RMT_MASK))
+#define IBEX_DEVLINK_DEVICE(_idx_) ((_idx_) & IBEX_DEVLINK_IDX_MASK)
+#define IBEX_DEVLINK_REMOTE(_idx_) \
+    (((_idx_) & (IBEX_DEVLINK_RMT_MASK)) >> IBEX_DEVLINK_RMT_SHIFT)
+#define IBEX_DEVLINK_MAKE_RMTDEV(_par_, _ix_) \
+    (((_par_) << IBEX_DEVLINK_RMT_SHIFT) | ((_ix_) & IBEX_DEVLINK_IDX_MASK))
+
+/* MemMapEntry that should be ignored (i.e. skipped, not mapped) */
+#define IBEX_MEMMAP_LAST { .flags = IBEX_MEM_MAP_ENTRY_FLAG(LAST) }
+#define IBEX_MEMMAP_SKIP { .flags = IBEX_MEM_MAP_ENTRY_FLAG(SKIP) }
+#define IBEX_MEMMAP_IS_LAST(_mmap_) \
+    ((bool)((_mmap_)->flags & IBEX_MEM_MAP_ENTRY_FLAG(LAST)))
+#define IBEX_MEMMAP_IGNORE(_mmap_) \
+    ((bool)((_mmap_)->flags & IBEX_MEM_MAP_ENTRY_FLAG(SKIP)))
+
+/*
+ * Create memory map entries, each arg is MemMapEntry definition
+ */
+#define MEMMAPENTRIES(...) \
+    (const IbexMemMapEntry[]) \
+    { \
+        __VA_ARGS__, IBEX_MEMMAP_LAST \
+    }
+
+/*
+ * Create GPIO connection entries, each arg is IbexGpioConnDef definition
+ */
+#define IBEXGPIOCONNDEFS(...) \
+    (const IbexGpioConnDef[]) \
+    { \
+        __VA_ARGS__, \
+        { \
+            .out = { .num = -1 } \
+        } \
+    }
+
+/*
+ * Create device link entries, each arg is IbexDeviceLinkDef definition
+ */
+#define IBEXDEVICELINKDEFS(...) \
+    (const IbexDeviceLinkDef[]) \
+    { \
+        __VA_ARGS__, \
+        { \
+            .propname = NULL \
+        } \
+    }
+
+/*
+ * Create clock connection entries, each arg is IbexClockConnDef definition
+ */
+#define IBEXCLOCKCONNDEFS(...) \
+    (const IbexClockConnDef[]) \
+    { \
+        __VA_ARGS__, \
+        { \
+            .out.name = NULL \
+        } \
+    }
+
+/*
+ * Create device property entries, each arg is IbexDevicePropDef definition
+ */
+#define IBEXDEVICEPROPDEFS(...) \
+    (const IbexDevicePropDef[]) \
+    { \
+        __VA_ARGS__, \
+        { \
+            .propname = NULL \
+        } \
+    }
+
+/*
+ * Create device additional map entries, each arg is IbexDeviceMapDef definition
+ */
+#define IBEXDEVICEMAPDEFS(...) \
+    (const IbexDeviceMapDef[]) \
+    { \
+        __VA_ARGS__, \
+        { \
+            .type = NULL \
+        } \
+    }
+
+/*
+ * Create device gpio export property entries, each arg is IbexGpioExportDef
+ * definition
+ */
+#define IBEXGPIOEXPORTDEFS(...) \
+    (const IbexGpioExportDef[]) \
+    { \
+        __VA_ARGS__, \
+        { \
+            .device = { .num = -1 }, .parent = { .num = -1 }, \
+        } \
+    }
+
+/*
+ * Create a IbexGpioConnDef to connect two unnamed GPIOs
+ */
+#define IBEX_GPIO(_irq_, _in_idx_, _num_) \
+    { \
+        .out = { \
+            .num = (_irq_), \
+        }, \
+        .in = { \
+            .index = (_in_idx_), \
+            .num = (_num_), \
+        } \
+    }
+
+/*
+ * Create a IbexGpioConnDef to connect a SysBus IRQ to an unnamed GPIO
+ */
+#define IBEX_GPIO_SYSBUS_IRQ(_irq_, _in_idx_, _num_) \
+    { \
+        .out = { \
+            .name = SYSBUS_DEVICE_GPIO_IRQ, \
+            .num = (_irq_), \
+        }, \
+        .in = { \
+            .index = (_in_idx_), \
+            .num = (_num_), \
+        } \
+    }
+
+/*
+ * Create a IbexLinkDeviceDef to link one device to another
+ */
+#define IBEX_DEVLINK(_pname_, _idx_) \
+    { \
+        .propname = (_pname_), \
+        .index = (_idx_), \
+    }
+
+/*
+ * Create a IbexClockConnDef to connect a clock output to a clock input
+ */
+#define IBEX_CLOCK_CONN(_out_idx_, _out_type_, _out_name_, _in_name_, \
+                        _in_idx_) \
+    { \
+        .out = { \
+            .index = (_out_idx_), \
+            .type = (_out_type_), \
+            .name = (_out_name_), \
+        }, \
+        .in = { \
+            .name = (_in_name_), \
+            .num = (_in_idx_), \
+        } \
+    }
+
+/*
+ * Create a IbexGpioExportDef to export a GPIO
+ */
+#define IBEX_EXPORT_GPIO(_dname_, _dnum_, _pname_, _pnum_) \
+    { \
+        .device = { \
+            .name = (_dname_), \
+            .num = (_dnum_), \
+        }, \
+        .parent = { \
+            .name = (_pname_), \
+            .num = (_pnum_), \
+        }, \
+    }
+
+/*
+ * Create a IbexGpioExportDef to export a SysBus IRQ
+ */
+#define IBEX_EXPORT_SYSBUS_IRQ(_dnum_, _pname_, _pnum_) \
+    IBEX_EXPORT_GPIO(NULL, _dnum_, _pname_, _pnum_)
+
+/*
+ * Create a boolean device property
+ */
+#define IBEX_DEV_BOOL_PROP(_pname_, _b_) \
+    { \
+        .propname = (_pname_), \
+        .type = IBEX_PROP_TYPE_BOOL, \
+        .b = (_b_), \
+    }
+
+/*
+ * Create a signed integer device property
+ */
+#define IBEX_DEV_INT_PROP(_pname_, _i_) \
+    { \
+        .propname = (_pname_), \
+        .type = IBEX_PROP_TYPE_INT, \
+        .i = (_i_), \
+    }
+
+/*
+ * Create an unsigned integer device property
+ */
+#define IBEX_DEV_UINT_PROP(_pname_, _u_) \
+    { \
+        .propname = (_pname_), \
+        .type = IBEX_PROP_TYPE_UINT, \
+        .u = (_u_), \
+    }
+
+/*
+ * Create a string device property
+ */
+#define IBEX_DEV_STRING_PROP(_pname_, _s_) \
+    { \
+        .propname = (_pname_), \
+        .type = IBEX_PROP_TYPE_STR, \
+        .s = (_s_), \
+    }
+
+void ibex_mmio_map_device(SysBusDevice *dev, MemoryRegion *mr, unsigned nr,
+                          hwaddr addr, int priority);
+DeviceState **ibex_create_devices(const IbexDeviceDef *defs, unsigned count,
+                                  DeviceState *parent);
+#define ibex_link_devices(_devs_, _defs_, _cnt_) \
+    ibex_link_remote_devices(_devs_, _defs_, _cnt_, NULL)
+void ibex_link_remote_devices(DeviceState **devices, const IbexDeviceDef *defs,
+                              unsigned count, DeviceState ***remotes);
+void ibex_apply_device_props(Object *obj, const IbexDevicePropDef *prop);
+void ibex_define_device_props(DeviceState **devices, const IbexDeviceDef *defs,
+                              unsigned count);
+void ibex_realize_system_devices(DeviceState **devices,
+                                 const IbexDeviceDef *defs, unsigned count);
+void ibex_realize_devices(DeviceState **devices, BusState *bus,
+                          const IbexDeviceDef *defs, unsigned count);
+void ibex_clock_devices(DeviceState **devices, const IbexDeviceDef *defs,
+                        unsigned count);
+void ibex_connect_devices(DeviceState **devices, const IbexDeviceDef *defs,
+                          unsigned count);
+#define ibex_map_devices(_devs_, _mrs_, _defs_, _cnt_) \
+    ibex_map_devices_offset(_devs_, _mrs_, _defs_, _cnt_, 0u)
+#define ibex_map_devices_offset(_devs_, _mrs_, _defs_, _cnt_, _off_) \
+    ibex_map_devices_mask_offset(_devs_, _mrs_, _defs_, _cnt_, \
+                                 IBEX_MEMMAP_DEFAULT_REG_MASK, _off_)
+#define ibex_map_devices_mask(_devs_, _mrs_, _defs_, _cnt_, _msk_) \
+    ibex_map_devices_mask_offset(_devs_, _mrs_, _defs_, _cnt_, _msk_, 0u)
+void ibex_map_devices_mask_offset(DeviceState **devices, MemoryRegion **mrs,
+                                  const IbexDeviceDef *defs, unsigned count,
+                                  uint32_t region_mask, uint32_t offset);
+#define ibex_map_devices_ext_mask(_dev_, _mrs_, _defs_, _cnt_, _msk_) \
+    ibex_map_devices_ext_mask_offset(_dev_, _mrs_, _defs_, _cnt_, _msk_, 0u)
+void ibex_map_devices_ext_mask_offset(
+    DeviceState *dev, MemoryRegion **mrs, const IbexDeviceMapDef *defs,
+    unsigned count, uint32_t region_mask, uint32_t offset);
+void ibex_configure_devices(DeviceState **devices, BusState *bus,
+                            const IbexDeviceDef *defs, unsigned count);
+void ibex_identify_devices(DeviceState **devices, const char *id_prop,
+                           const char *id_value, bool id_prepend,
+                           unsigned count);
+void ibex_configure_devices_with_id(DeviceState **devices, BusState *bus,
+                                    const char *id_prop, const char *id_value,
+                                    bool id_prepend, const IbexDeviceDef *defs,
+                                    unsigned count);
+void ibex_export_gpios(DeviceState **devices, DeviceState *parent,
+                       const IbexDeviceDef *defs, unsigned count);
+void ibex_connect_soc_devices(DeviceState **soc_devices, DeviceState **devices,
+                              const IbexDeviceDef *defs, unsigned count);
+DeviceState *ibex_get_child_device(DeviceState *s, const char *typename,
+                                   unsigned instance);
+/*
+ * Utility function to configure unimplemented device.
+ * The Ibex device definition should have one defined memory entry, and an
+ * optional name.
+ */
+void ibex_unimp_configure(DeviceState *dev, const IbexDeviceDef *def,
+                          DeviceState *parent);
+
+/* ------------------------------------------------------------------------ */
+/* CPU */
+/* ------------------------------------------------------------------------ */
+
+/*
+ * Load an ELF application into a CPU address space.
+ *
+ * @cpu the CPU to load the application for; maybe NULL in which case the
+ *      first valid CPU address space is used. Except if the machine defines
+ *      and sets a "ignore-elf-entry" boolean property, the PC of the specified
+ *      vCPU - or all vCPUs if not specified - is assigned the entry point of
+ *      the ELF file.
+ *
+ * @return the Ibex-constrained ELF entry point (or -1 on error)
+ */
+uint32_t ibex_load_kernel(CPUState *cpu);
+
+/*
+ * Helper for device debugging: report the current guest PC, if any.
+ *
+ * If a HW access is performed from another device but the CPU, reported PC
+ * is 0.
+ */
+uint32_t ibex_get_current_pc(void);
+
+/*
+ * Helper for device debugging: report the current guest CPU index, if any.
+ *
+ * If a HW access is performed from another device but the CPU, reported CPU
+ * is -1.
+ */
+int ibex_get_current_cpu(void);
+
+enum {
+    RV_GPR_PC = (1u << 0u),
+    RV_GPR_RA = (1u << 1u),
+    RV_GPR_SP = (1u << 2u),
+    RV_GPR_GP = (1u << 3u),
+    RV_GPR_TP = (1u << 4u),
+    RV_GPR_T0 = (1u << 5u),
+    RV_GPR_T1 = (1u << 6u),
+    RV_GPR_T2 = (1u << 7u),
+    RV_GPR_S0 = (1u << 8u),
+    RV_GPR_S1 = (1u << 9u),
+    RV_GPR_A0 = (1u << 10u),
+    RV_GPR_A1 = (1u << 11u),
+    RV_GPR_A2 = (1u << 12u),
+    RV_GPR_A3 = (1u << 13u),
+    RV_GPR_A4 = (1u << 14u),
+    RV_GPR_A5 = (1u << 15u),
+    RV_GPR_A6 = (1u << 16u),
+    RV_GPR_A7 = (1u << 17u),
+    RV_GPR_S2 = (1u << 18u),
+    RV_GPR_S3 = (1u << 19u),
+    RV_GPR_S4 = (1u << 20u),
+    RV_GPR_S5 = (1u << 21u),
+    RV_GPR_S6 = (1u << 22u),
+    RV_GPR_S7 = (1u << 23u),
+    RV_GPR_S8 = (1u << 24u),
+    RV_GPR_S9 = (1u << 25u),
+    RV_GPR_S10 = (1u << 26u),
+    RV_GPR_S11 = (1u << 27u),
+    RV_GPR_T3 = (1u << 28u),
+    RV_GPR_T4 = (1u << 29u),
+    RV_GPR_T5 = (1u << 30u),
+    RV_GPR_T6 = (1u << 31u),
+};
+
+/*
+ * Log current vCPU registers.
+ *
+ * @regbm is a bitmap of registers to be dumped [x1..t6], pc replace x0
+ */
+void ibex_log_vcpu_registers(uint64_t regbm);
+
+/* ------------------------------------------------------------------------ */
+/* Miscellaneous utilities */
+/* ------------------------------------------------------------------------ */
+
+/*
+ * Find a host function name by its address.
+ *
+ * @fn the address of the function
+ * @return the function name, or NULL if not found or not supported
+ */
+const char *ibex_common_get_func_name_by_addr(void *fn);
+
+/* ------------------------------------------------------------------------ */
+/* CharDev utilities */
+/* ------------------------------------------------------------------------ */
+
+/*
+ * Find a char device by its id, e.g. "-chardev type,id=<id>,...`"
+ *
+ * @chrid the id of the char device
+ * @return the char device if found, @c NULL otherwise.
+ */
+Chardev *ibex_get_chardev_by_id(const char *chrid);
+
+
+#endif /* HW_RISCV_IBEX_COMMON_H */
diff --git a/include/hw/riscv/ibex_gpio.h b/include/hw/riscv/ibex_gpio.h
new file mode 100644
index 0000000000000..866b437fafd39
--- /dev/null
+++ b/include/hw/riscv/ibex_gpio.h
@@ -0,0 +1,111 @@
+/*
+ * QEMU Ibex GPIOs
+ *
+ * Copyright (c) 2024 Rivos, Inc.
+ *
+ * Author(s):
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_IBEX_GPIO_H
+#define HW_RISCV_IBEX_GPIO_H
+
+#include "hw/registerfields.h"
+#include "hw/riscv/ibex_irq.h"
+
+/* GPIO multi-level storage */
+typedef int ibex_gpio;
+
+/* set if GPIO is not Hi-Z */
+SHARED_FIELD(IBEX_GPIO_ACTIVE, 0u, 1u)
+/* GPIO signal level */
+SHARED_FIELD(IBEX_GPIO_LEVEL, 1u, 1u)
+/* GPIO is applying a strong signed (vs. weak pull-up or pull-down) */
+SHARED_FIELD(IBEX_GPIO_STRENGTH, 2u, 1u)
+/* always 0 (reserved for strength extension) */
+SHARED_FIELD(IBEX_GPIO_SBZ, 3u, 5u)
+/* Ibex GPIO 'G' marker (sanity check) */
+SHARED_FIELD(IBEX_GPIO_FLAG, 8u, 8u)
+
+/* default initialization: Hi-Z */
+#define IBEX_GPIO_INIT ('G' << IBEX_GPIO_FLAG_SHIFT)
+#define IBEX_GPIO_HIZ  IBEX_GPIO_INIT
+#define IBEX_GPIO_FROM_ACTIVE_SIG(_lvl_) \
+    (IBEX_GPIO_INIT | IBEX_GPIO_ACTIVE_MASK | IBEX_GPIO_STRENGTH_MASK | \
+     (((int)(bool)(_lvl_)) << IBEX_GPIO_LEVEL_SHIFT))
+#define IBEX_GPIO_FROM_WEAK_SIG(_lvl_) \
+    (IBEX_GPIO_INIT | IBEX_GPIO_ACTIVE_MASK | \
+     (((int)(bool)(_lvl_)) << IBEX_GPIO_LEVEL_SHIFT))
+#define IBEX_GPIO_LOW       IBEX_GPIO_FROM_ACTIVE_SIG(false)
+#define IBEX_GPIO_HIGH      IBEX_GPIO_FROM_ACTIVE_SIG(true)
+#define IBEX_GPIO_PULL_DOWN IBEX_GPIO_FROM_WEAK_SIG(false)
+#define IBEX_GPIO_PULL_UP   IBEX_GPIO_FROM_WEAK_SIG(true)
+
+
+static inline bool ibex_gpio_level(ibex_gpio level)
+{
+    return (bool)(level & IBEX_GPIO_LEVEL_MASK);
+}
+
+static inline bool ibex_gpio_is_hiz(ibex_gpio level)
+{
+    return !(level & IBEX_GPIO_ACTIVE_MASK);
+}
+
+static inline bool ibex_gpio_is_weak(ibex_gpio level)
+{
+    return !(level & IBEX_GPIO_STRENGTH_MASK);
+}
+
+static inline bool ibex_gpio_check(ibex_gpio level)
+{
+    return (level & (IBEX_GPIO_FLAG_MASK | IBEX_GPIO_SBZ_MASK)) ==
+           ('G' << IBEX_GPIO_FLAG_SHIFT);
+}
+
+/*
+ * Debug representation of an Ibex GPIO signal.
+ *
+ * 'X': invalid signal (not a valid Ibex IO)
+ * 'z': Hi-Z
+ * 'H': active high
+ * 'L': active low
+ * 'h': weak high / pull up
+ * 'l': weak low / pull down
+ */
+static inline char ibex_gpio_repr(ibex_gpio level)
+{
+    return ibex_gpio_check(level) ?
+               (!ibex_gpio_is_hiz(level) ?
+                    (ibex_gpio_level(level) ? 'H' : 'L') +
+                        (ibex_gpio_is_weak(level) ? 0x20 : 0) :
+                    'z') :
+               'X';
+}
+
+static inline void ibex_gpio_assert(ibex_gpio level)
+{
+    g_assert(ibex_gpio_check(level));
+}
+
+ibex_gpio ibex_gpio_combine(const ibex_gpio *levels, unsigned count);
+
+bool ibex_gpio_parse_level(const char *name, const char *value, ibex_gpio *obj,
+                           Error **errp);
+
+ObjectProperty *
+object_property_add_ibex_gpio(Object *obj, const char *name, ibex_gpio *value);
+
+#endif /* HW_RISCV_IBEX_GPIO_H */
diff --git a/include/hw/riscv/ibex_irq.h b/include/hw/riscv/ibex_irq.h
new file mode 100644
index 0000000000000..957a88c20338b
--- /dev/null
+++ b/include/hw/riscv/ibex_irq.h
@@ -0,0 +1,103 @@
+/*
+ * QEMU lowRISC Ibex IRQ wrapper
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_RISCV_IBEX_IRQ_H
+#define HW_RISCV_IBEX_IRQ_H
+
+#include "qemu/osdep.h"
+#include "hw/irq.h"
+#include "hw/qdev-core.h"
+#include "hw/sysbus.h"
+
+/** Simple IRQ wrapper to limit propagation of no-change calls */
+typedef struct {
+    qemu_irq irq;
+    int level;
+} IbexIRQ;
+
+static inline bool ibex_irq_is_connected(const IbexIRQ *ibex_irq)
+{
+    return qemu_irq_is_connected(ibex_irq->irq);
+}
+
+static inline int ibex_irq_get_level(const IbexIRQ *ibex_irq)
+{
+    return ibex_irq->level;
+}
+
+static inline bool ibex_irq_set(IbexIRQ *ibex_irq, int level)
+{
+    if (level != ibex_irq->level) {
+        ibex_irq->level = level;
+        qemu_set_irq(ibex_irq->irq, level);
+        return true;
+    }
+
+    return false;
+}
+
+static inline bool ibex_irq_raise(IbexIRQ *irq)
+{
+    return ibex_irq_set(irq, 1);
+}
+
+static inline bool ibex_irq_lower(IbexIRQ *irq)
+{
+    return ibex_irq_set(irq, 0);
+}
+
+static inline void ibex_qdev_init_irq_default(Object *obj, IbexIRQ *irq,
+                                              const char *name, int level)
+{
+    irq->level = level;
+    qdev_init_gpio_out_named(DEVICE(obj), &irq->irq, name, 1);
+}
+
+static inline void ibex_qdev_init_irq(Object *obj, IbexIRQ *irq,
+                                      const char *name)
+{
+    ibex_qdev_init_irq_default(obj, irq, name, 0);
+}
+
+static inline void ibex_qdev_init_irqs_default(
+    Object *obj, IbexIRQ *irqs, const char *name, unsigned count, int level)
+{
+    for (unsigned ix = 0; ix < count; ix++) {
+        ibex_qdev_init_irq_default(obj, &irqs[ix], name, level);
+    }
+}
+
+static inline void ibex_qdev_init_irqs(Object *obj, IbexIRQ *irqs,
+                                       const char *name, unsigned count)
+{
+    ibex_qdev_init_irqs_default(obj, irqs, name, count, 0);
+}
+
+static inline void ibex_sysbus_init_irq(Object *obj, IbexIRQ *irq)
+{
+    irq->level = 0;
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &irq->irq);
+}
+
+#endif /* HW_RISCV_IBEX_IRQ_H */
diff --git a/include/hw/riscv/ibexdemo.h b/include/hw/riscv/ibexdemo.h
new file mode 100644
index 0000000000000..1060e01708f07
--- /dev/null
+++ b/include/hw/riscv/ibexdemo.h
@@ -0,0 +1,33 @@
+/*
+ * QEMU RISC-V Board Compatible with Ibex Demo FPGA platform
+ *
+ * Copyright (c) 2022-2023 Rivos, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_IBEXDEMO_H
+#define HW_RISCV_IBEXDEMO_H
+
+#include "qom/object.h"
+
+#define TYPE_RISCV_IBEXDEMO_MACHINE MACHINE_TYPE_NAME("ibexdemo")
+OBJECT_DECLARE_SIMPLE_TYPE(IbexDemoMachineState, RISCV_IBEXDEMO_MACHINE)
+
+#define TYPE_RISCV_IBEXDEMO_BOARD "riscv.ibexdemo.board"
+OBJECT_DECLARE_SIMPLE_TYPE(IbexDemoBoardState, RISCV_IBEXDEMO_BOARD)
+
+#define TYPE_RISCV_IBEXDEMO_SOC "riscv.ibexdemo.soc"
+OBJECT_DECLARE_SIMPLE_TYPE(IbexDemoSoCState, RISCV_IBEXDEMO_SOC)
+
+#endif /* HW_RISCV_IBEXDEMO_H */
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 609473d07b400..2cbf3b42f0425 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -19,13 +19,13 @@
 #ifndef HW_OPENTITAN_H
 #define HW_OPENTITAN_H
 
-#include "hw/riscv/riscv_hart.h"
 #include "hw/intc/sifive_plic.h"
 #include "hw/char/ibex_uart.h"
 #include "hw/timer/ibex_timer.h"
 #include "hw/ssi/ibex_spi_host.h"
 #include "hw/boards.h"
 #include "qom/object.h"
+#include "include/hw/riscv/riscv_hart.h"
 
 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
 OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
diff --git a/include/hw/riscv/ot_darjeeling.h b/include/hw/riscv/ot_darjeeling.h
new file mode 100644
index 0000000000000..2df919c76ce6a
--- /dev/null
+++ b/include/hw/riscv/ot_darjeeling.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU RISC-V Board Compatible with OpenTitan "integrated" Darjeeling platform
+ *
+ * Copyright (c) 2023-2025 Rivos, Inc.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *  Emmanuel Blot <eblot@rivosinc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_OT_DARJEELING_H
+#define HW_RISCV_OT_DARJEELING_H
+
+#include "qom/object.h"
+
+#define TYPE_RISCV_OT_DJ_MACHINE MACHINE_TYPE_NAME("ot-darjeeling")
+OBJECT_DECLARE_SIMPLE_TYPE(OtDjMachineState, RISCV_OT_DJ_MACHINE)
+
+#define TYPE_RISCV_OT_DJ_BOARD "riscv.ot_darjeeling.board"
+OBJECT_DECLARE_SIMPLE_TYPE(OtDjBoardState, RISCV_OT_DJ_BOARD)
+
+#define TYPE_RISCV_OT_DJ_SOC "riscv.ot_darjeeling.soc"
+OBJECT_DECLARE_TYPE(OtDjSoCState, OtDjSoCClass, RISCV_OT_DJ_SOC)
+
+#endif /* HW_RISCV_OT_DARJEELING_H */
diff --git a/include/hw/riscv/ot_earlgrey.h b/include/hw/riscv/ot_earlgrey.h
new file mode 100644
index 0000000000000..c996ddee1ea65
--- /dev/null
+++ b/include/hw/riscv/ot_earlgrey.h
@@ -0,0 +1,39 @@
+/*
+ * QEMU RISC-V Board Compatible with OpenTitan EarlGrey FPGA platform
+ *
+ * Copyright (c) 2022-2024 Rivos, Inc.
+ * Copyright (c) 2024-2025 lowRISC contributors.
+ *
+ * Author(s):
+ *  Loïc Lefort <loic@rivosinc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RISCV_OT_EARLGREY_H
+#define HW_RISCV_OT_EARLGREY_H
+
+#include "qom/object.h"
+
+#define OT_EARLGREY "ot-earlgrey"
+
+#define TYPE_RISCV_OT_EG_MACHINE MACHINE_TYPE_NAME(OT_EARLGREY)
+OBJECT_DECLARE_SIMPLE_TYPE(OtEGMachineState, RISCV_OT_EG_MACHINE)
+
+#define TYPE_RISCV_OT_EG_BOARD OT_EARLGREY "-board"
+OBJECT_DECLARE_SIMPLE_TYPE(OtEGBoardState, RISCV_OT_EG_BOARD)
+
+#define TYPE_RISCV_OT_EG_SOC OT_EARLGREY "-soc"
+OBJECT_DECLARE_TYPE(OtEGSoCState, OtEGSoCClass, RISCV_OT_EG_SOC)
+
+#endif /* HW_RISCV_OT_EARLGREY_H */
diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index 2ad8033d8f5b7..60e4e2f21889f 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -18,6 +18,9 @@
 
 typedef enum SSICSMode SSICSMode;
 
+#define TYPE_SSI_BUS "SSI"
+OBJECT_DECLARE_SIMPLE_TYPE(SSIBus, SSI_BUS)
+
 #define TYPE_SSI_PERIPHERAL "ssi-peripheral"
 OBJECT_DECLARE_TYPE(SSIPeripheral, SSIPeripheralClass,
                     SSI_PERIPHERAL)
diff --git a/meson.build b/meson.build
index d9293294d8e76..f1a4c504ebc97 100644
--- a/meson.build
+++ b/meson.build
@@ -1,4 +1,4 @@
-project('qemu', ['c'], meson_version: '>=1.5.0',
+project('qemu', ['c', 'rust'], meson_version: '>=1.5.0',
         default_options: ['warning_level=1', 'c_std=gnu11', 'cpp_std=gnu++11', 'b_colorout=auto',
                           'b_staticpic=false', 'stdsplit=false', 'optimization=2', 'b_pie=true'],
         version: files('VERSION'))
@@ -3635,6 +3635,7 @@ if have_system
     'hw/dma',
     'hw/fsi',
     'hw/hyperv',
+    'hw/ibexdemo',
     'hw/i2c',
     'hw/i386',
     'hw/i386/xen',
@@ -3643,6 +3644,7 @@ if have_system
     'hw/input',
     'hw/intc',
     'hw/isa',
+    'hw/jtag',
     'hw/mem',
     'hw/mips',
     'hw/misc',
@@ -3652,11 +3654,12 @@ if have_system
     'hw/nubus',
     'hw/nvme',
     'hw/nvram',
+    'hw/opentitan',
     'hw/pci',
     'hw/pci-host',
     'hw/ppc',
-    'hw/rtc',
     'hw/riscv',
+    'hw/rtc',
     'hw/s390x',
     'hw/scsi',
     'hw/sd',
diff --git a/python/qemu/jtagtools/.flake8 b/python/qemu/jtagtools/.flake8
new file mode 100644
index 0000000000000..15fc7e33eb08a
--- /dev/null
+++ b/python/qemu/jtagtools/.flake8
@@ -0,0 +1,2 @@
+[flake8]
+max-line-length = 80
diff --git a/python/qemu/jtagtools/.pylintrc b/python/qemu/jtagtools/.pylintrc
new file mode 100644
index 0000000000000..7ee6e793e253c
--- /dev/null
+++ b/python/qemu/jtagtools/.pylintrc
@@ -0,0 +1,14 @@
+[MESSAGES CONTROL]
+
+disable=
+    too-few-public-methods,
+    too-many-arguments,
+    too-many-branches,
+    too-many-function-args,
+    too-many-instance-attributes,
+    too-many-lines,
+    too-many-locals,
+    too-many-nested-blocks,
+    too-many-public-methods,
+    too-many-statements,
+    unspecified-encoding
diff --git a/python/qemu/jtagtools/__init__.py b/python/qemu/jtagtools/__init__.py
new file mode 100644
index 0000000000000..ad9e1081ea683
--- /dev/null
+++ b/python/qemu/jtagtools/__init__.py
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Rivos Inc. Emmanuel Blot <eblot@rivosinc.com>
+# Copyright (c) 2024, Emmanuel Blot <emmanuel.blot@free.fr>
+# All rights reserved.
+#
+# SPDX-License-Identifier: Apache2
+
+"""JTAG Tools."""
+__version__ = '0.11.0'
diff --git a/python/qemu/jtagtools/bits/__init__.py b/python/qemu/jtagtools/bits/__init__.py
new file mode 100644
index 0000000000000..c5ccb5b7c39e9
--- /dev/null
+++ b/python/qemu/jtagtools/bits/__init__.py
@@ -0,0 +1,1130 @@
+# Copyright (c) 2024 Rivos Inc. Emmanuel Blot <eblot@rivosinc.com>
+# Copyright (c) 2024 Emmanuel Blot <emmanuel.blot@free.fr>
+# All rights reserved.
+#
+# SPDX-License-Identifier: Apache2
+
+"""Bit sequence helpers for JTAG.
+
+   BitSequence handle bit manipulation for the JTAG tools.
+
+   To run all tests, use:
+       python3 jtagtools/bits/__init__.py [-v]
+
+   To test a single function, install pytest and use:
+       pytest --doctest-modules jtagtools/bits -k <function>
+"""
+
+from typing import Any, Iterable, Union
+
+
+class BitSequenceError(Exception):
+    """Bit sequence error.
+
+       >>> raise BitSequenceError('msg')
+       Traceback (most recent call last):
+       ...
+       BitSequenceError: msg
+    """
+
+
+BitSequenceInitializer = Union['BitSequence', str, int, bytes, bytearray,
+                               Iterable[int], Iterable[bool], None]
+"""Supported types to initialize a BitSequence."""
+
+
+class BitSequence:
+    """Bit sequence.
+
+       Support most of the common bit operations and conversion from and to
+       integral values, as well as sequence of boolean, int and characters.
+
+       Bit sequence objects are iterable.
+
+       :param value:  initial value
+       :param width: count of significant bits in the bit sequence
+
+       >>> BitSequence()
+       []
+       >>> BitSequence([False, True])
+       [0, 1]
+       >>> BitSequence([0, 1, 1])
+       [0, 1, 1]
+       >>> BitSequence(BitSequence([0, 1, 1]), 5)
+       [0, 0, 0, 1, 1]
+       >>> BitSequence('100')
+       [1, 0, 0]
+       >>> BitSequence(b'101')
+       [1, 0, 1]
+       >>> BitSequence(0xC, 4)
+       [1, 1, 0, 0]
+       >>> BitSequence(0xC, 3)
+       Traceback (most recent call last):
+       ...
+       ValueError: Value cannot be stored in specified width
+       >>> BitSequence(BitSequence([1, 1, 0, 0]), 3)
+       Traceback (most recent call last):
+       ...
+       ValueError: Specified width too short
+    """
+
+    NIBBLE_SEP = ''
+    # Optional string separator between each nibble for string representation
+
+    # pylint: disable=protected-access
+
+    def __init__(self, value: BitSequenceInitializer = None,
+                 width: int = 0):
+        """
+        >>> BitSequence()
+        []
+        >>> BitSequence(0, 3)
+        [0, 0, 0]
+        """
+        if value is None:
+            self._int = 0
+            self._width = width
+            return
+        if isinstance(value, BitSequence):
+            if width:
+                if value._width > width:
+                    raise ValueError('Specified width too short')
+                width = max(width, value._width)
+            else:
+                width = value._width
+            self._int, self._width = value._int, width
+            return
+        if isinstance(value, int):
+            if width == 0:
+                raise ValueError('Integer value should have a non-zero width')
+            if value >= 1 << width:
+                raise ValueError('Value cannot be stored in specified width')
+            bseq = self.from_int(value, width)
+            self._int, self._width = bseq._int, bseq._width
+            return
+        if is_iterable(value):
+            bseq = self.from_iterable(value)
+            if width and width != bseq._width:
+                raise ValueError('Specified width does not match input value')
+            self._int, self._width = bseq._int, bseq._width
+            return
+        raise BitSequenceError(f'Cannot initialize from a {type(value)}')
+
+    @classmethod
+    def from_iterable(cls, iterable: Iterable) -> 'BitSequence':
+        """Instanciate a BitSequence from an iterable.
+           Each element of the iterable should represent a single bit.
+
+           See BitSequence.from_bytes to create a BitSequence for a byte
+           stream.
+
+        >>> BitSequence('11000100')
+        [1, 1, 0, 0, 0, 1, 0, 0]
+        >>> BitSequence(b'11000100')
+        [1, 1, 0, 0, 0, 1, 0, 0]
+        >>> BitSequence(b'\\x01\\x01\\x00\\x00\\x00\\x01\\x000')
+        [1, 1, 0, 0, 0, 1, 0, 0]
+        >>> BitSequence([1, 1, 0, 0, 0, 1, 0, 0])
+        [1, 1, 0, 0, 0, 1, 0, 0]
+        """
+        # pylint: disable=duplicate-key
+        smap = {
+            0: 0, 1: 1,  # as int
+            '0': 0, '1': 1,  # as string
+            0x30: 0, 0x31: 1,  # as bytes
+            False: 0, True: 1,  # as bool
+        }
+        value = 0
+        width = 0
+        for bit in iterable:
+            try:
+                value <<= 1
+                value |= smap[bit]
+                width += 1
+            except KeyError as exc:
+                raise ValueError(f"Invalid item value '{bit}' in iterable at "
+                                 f"pos {width}") from exc
+        return BitSequence.from_int(value, width)
+
+    @classmethod
+    def from_int(cls, value: int, width: int) -> 'BitSequence':
+        """Instanciate a BitSequence from an integer value.
+
+        >>> BitSequence(0xC4, 8)
+        [1, 1, 0, 0, 0, 1, 0, 0]
+        >>> BitSequence(-1, 9)
+        [1, 1, 1, 1, 1, 1, 1, 1, 1]
+        """
+        bseq = BitSequence()
+        bseq._int = value & ((1 << width) - 1)
+        bseq._width = width
+        return bseq
+
+    @classmethod
+    def from_bytes(cls, value: Union[bytes, bytearray]) -> 'BitSequence':
+        """Instanciate a BitSequence from a sequence of bytes, one bit for each
+           input byte.
+
+        >>> BitSequence(b'\\x01\\x01\\x00\\x00\\x00\\x01\\x000')
+        [1, 1, 0, 0, 0, 1, 0, 0]
+        """
+        return cls.from_iterable(value)
+
+    @classmethod
+    def from_bytestream(cls, value: Union[bytes, bytearray],
+                        lsbyte: bool = False) -> 'BitSequence':
+        """Instanciate a BitSequence from a sequence of bytes, 8 bits for each
+           input byte.
+
+        >>> BitSequence.from_bytestream(b'\\xca\\xfe')
+        [1, 1, 0, 0, 1, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0]
+        >>> BitSequence.from_bytestream(b'\\xca\\xfe', True)
+        [1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, 1, 0]
+        """
+        bseq = BitSequence(0, 8 * len(value))
+        if lsbyte:
+            for byte in reversed(value):
+                bseq._int <<= 8
+                bseq._int |= byte
+        else:
+            for byte in value:
+                bseq._int <<= 8
+                bseq._int |= byte
+        return bseq
+
+    def __len__(self):
+        """
+        >>> len(BitSequence())
+        0
+        >>> len(BitSequence(0, 1))
+        1
+        >>> len(BitSequence('010'))
+        3
+        """
+        return self._width
+
+    def __bool__(self) -> bool:
+        """Report whether BitSequence is empty or not.
+
+           To fold a single bit sequence into a boolean, see #to_bit
+
+        >>> bool(BitSequence())
+        False
+        >>> bool(BitSequence(0, 1))
+        True
+        >>> bool(BitSequence('010'))
+        True
+        """
+        return bool(self._width)
+
+    def __int__(self) -> int:
+        """Convert BitSequence to an int.
+
+        >>> int(BitSequence())
+        0
+        >>> int(BitSequence(0, 1))
+        0
+        >>> int(BitSequence('010'))
+        2
+        """
+        return self._int
+
+    def __repr__(self) -> str:
+        """
+        >>> repr(BitSequence(0xC4, 8))
+        '[1, 1, 0, 0, 0, 1, 0, 0]'
+        """
+        sseq = ', '.join((f'{b:0d}' for b in self))
+        return f'[{sseq}]'
+
+    def __str__(self) -> str:
+        """
+        >>> str(BitSequence(0xC4, 8))
+        '11000100'
+        >>> BitSequence.NIBBLE_SEP = '.'
+
+        >>> str(BitSequence(0xC4, 8))
+        '1100.0100'
+        >>> str(BitSequence(0x2C4, 10))
+        '10.1100.0100'
+        >>> BitSequence.NIBBLE_SEP = ''
+
+        """
+        bss = f'{self._int:0{self._width}b}'
+        if not self.NIBBLE_SEP:
+            return bss
+        xlen = len(bss) % 4
+        padlen = 4 - xlen
+        if xlen:
+            pad = ' ' * padlen
+            bss = f'{pad}{bss}'
+        nbss = self.NIBBLE_SEP.join((''.join(nb)
+                                     for nb in BitSequence.group(bss, 4)))
+        return nbss[padlen:] if xlen else nbss
+
+    @staticmethod
+    def group(lst, count):
+        """Group a list into consecutive count-tuples. Incomplete tuples are
+           discarded.
+
+           >>> BitSequence.group([0,3,4,10,2,3], 2)
+           [(0, 3), (4, 10), (2, 3)]
+        """
+        return list(zip(*[lst[i::count] for i in range(count)]))
+
+    @property
+    def mask(self) -> int:
+        """Bit mask.
+
+        >>> BitSequence(0xC4, 8).mask
+        255
+        >>> BitSequence().mask
+        0
+        """
+        return (1 << self._width) - 1
+
+    def to_bit(self) -> bool:
+        """Fold the sequence into a single bit, if possible.
+
+        >>> BitSequence([0]).to_bit()
+        False
+        >>> BitSequence([1]).to_bit()
+        True
+        >>> BitSequence([0, 0]).to_bit()
+        Traceback (most recent call last):
+        ...
+        BitSequenceError: BitSequence too large
+        """
+        if self._width != 1:
+            raise BitSequenceError("BitSequence too large")
+        return bool(self._int & 1)
+
+    def to_byte(self, lsb: bool = False) -> int:
+        """Convert the sequence into a single byte value, if possible.
+
+        >>> hex(BitSequence(0xC4, 8).to_byte())
+        '0xc4'
+        >>> hex(BitSequence(0xC4, 8).to_byte(True))
+        '0x23'
+        """
+        if self._width > 8:
+            raise BitSequenceError("Cannot fit into a single byte")
+        if lsb:
+            bseq = BitSequence(self)
+            bseq.reverse()
+        else:
+            bseq = self
+        return bseq._int
+
+    def to_bytes(self) -> bytes:
+        """Return the internal representation as bytes.
+
+        >>> BitSequence(0xC4, 8).to_bytes()
+        b'\\x01\\x01\\x00\\x00\\x00\\x01\\x00\\x00'
+        """
+        return bytes((int(b) for b in self))
+
+    def to_bool_list(self) -> list[bool]:
+        """Convert the sequence into a list of boolean values.
+
+        >>> BitSequence(0xC4, 8).to_bool_list()
+        [True, True, False, False, False, True, False, False]
+        """
+        return list(self)
+
+    def to_bytestream(self, lsbyte: bool = False, lsbit: bool = False)\
+            -> bytes:
+        """Convert the sequence into a sequence of byte values.
+
+        >>> from binascii import hexlify
+
+        >>> hexlify(BitSequence(0xC4A5D0, 24).to_bytestream(False, False))
+        b'c4a5d0'
+        >>> hexlify(BitSequence(0xC4A5D0, 24).to_bytestream(True, False))
+        b'd0a5c4'
+        >>> hexlify(BitSequence(0xC4A5D0, 24).to_bytestream(False, True))
+        b'23a50b'
+        >>> hexlify(BitSequence(0xC4A5D0, 24).to_bytestream(True, True))
+        b'0ba523'
+        >>> hexlify(BitSequence(0xC4A5D01234, 40).to_bytestream(False, False))
+        b'c4a5d01234'
+        >>> hexlify(BitSequence(0x51234, 20).to_bytestream(False, False))
+        b'051234'
+        >>> hexlify(BitSequence(0x51234, 21).to_bytestream(False, False))
+        b'051234'
+        >>> hexlify(BitSequence(0x51234, 21).to_bytestream(True, False))
+        b'341205'
+        >>> hexlify(BitSequence(0x51234, 21).to_bytestream(True, True))
+        b'2c48a0'
+        """
+        out: list[int] = []
+        bseq = BitSequence(self)
+        xbitlen = len(bseq) & 7
+        if xbitlen:
+            bseq.push_left([0] * (8 - xbitlen))
+        if lsbit:
+            bseq.reverse()
+        while bseq._width > 0:
+            out.append(bseq._int & 0xff)
+            bseq._int >>= 8
+            bseq._width -= 8
+        if not lsbit ^ lsbyte:
+            out.reverse()
+        return bytes(out)
+
+    def resize(self, width: int) -> 'BitSequence':
+        """Change the width of the BitSequence.
+           Truncate the stored bits of new width is shorter.
+
+           :return: self
+
+        >>> bs1 = BitSequence(0xC4, 8)
+
+        >>> bs1.resize(10)
+        [0, 0, 1, 1, 0, 0, 0, 1, 0, 0]
+        >>> bs1.resize(5)
+        [0, 0, 1, 0, 0]
+        """
+        if width > self._width:
+            self._int &= (1 << width) - 1
+        self._width = width
+        return self
+
+    def copy(self, reverse=False) -> 'BitSequence':
+        """Duplicate bitsequence.
+
+        >>> bs1 = BitSequence(0xC4, 8)
+
+        >>> bs2 = bs1.copy()
+
+        >>> bs1 == bs2
+        True
+        >>> id(bs1) == id(bs2)
+        False
+        >>> bs1._int = 0
+
+        >>> bs1 == bs2
+        False
+        >>> int(bs1)
+        0
+        >>> int(bs2)
+        196
+        >>> BitSequence(0b11000100, 8).copy(True)
+        [0, 0, 1, 0, 0, 0, 1, 1]
+        """
+        if not reverse:
+            bseq = self.__class__()
+            bseq._int = self._int
+            bseq._width = self._width
+            return bseq
+        return self.__class__.from_iterable(reversed(self))
+
+    def reverse(self) -> 'BitSequence':
+        """In-place reverse.
+
+           :return: self
+
+        >>> BitSequence(0b11000100, 8).reverse()
+        [0, 0, 1, 0, 0, 0, 1, 1]
+        """
+        bseq = self.__class__.from_iterable(reversed(self))
+        assert bseq._width == self._width
+        self._int = bseq._int
+        return self
+
+    def invert(self) -> 'BitSequence':
+        """In-place invert of each sequence value.
+
+           :return: self
+
+        >>> BitSequence(0b11000100, 8).invert()
+        [0, 0, 1, 1, 1, 0, 1, 1]
+        """
+        self._int = ~self._int & self.mask
+        return self
+
+    def push_right(self, *bseq: BitSequenceInitializer) -> 'BitSequence':
+        """Push a bit sequence to the right side.
+
+           :param bseq: the bit sequence to push
+           :return: self
+
+        >>> BitSequence(0b11000100, 8).push_right(0b110, 3)
+        [1, 1, 0, 0, 0, 1, 0, 0, 1, 1, 0]
+        """
+        bseq = BitSequence(*bseq)
+        self._int <<= len(bseq)
+        self._int |= bseq._int
+        self._width += len(bseq)
+        return self
+
+    def push_left(self, *bseq: BitSequenceInitializer) -> 'BitSequence':
+        """Push a bit sequence to the left side.
+
+           :param bseq: the bit sequence to push
+           :return: self
+        >>> BitSequence(0b11000100, 8).push_left(BitSequence(0b110, 3))
+        [1, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0]
+        """
+        bseq = BitSequence(*bseq)
+        self._int = (bseq._int << self._width) | self._int
+        self._width += len(bseq)
+        return self
+
+    def pop_right(self, count: int = 1) -> 'BitSequence':
+        """Pop bits from the right side.
+
+           :param count: how many bits to pop
+           :return: popped bits a a new BitSequence
+
+        >>> bs = BitSequence(0b11000100, 8)
+
+        >>> bs.pop_right(2)
+        [0, 0]
+
+        >>> bs
+        [1, 1, 0, 0, 0, 1]
+        """
+        if count > self._width:
+            raise ValueError('Count too large')
+        if count == 0:
+            return BitSequence()
+        if count < 0:
+            raise ValueError('Negative shift is not defined')
+        bseq = self.__class__.from_int(self._int & ((1 << count) - 1), count)
+        self._int >>= count
+        self._width -= count
+        return bseq
+
+    def pop_left(self, count: int = 1) -> 'BitSequence':
+        """Pop bits from the left side.
+
+           :param count: how many bits to pop
+           :return: popped bits a a new BitSequence
+
+        >>> bs = BitSequence(0b11000100, 8)
+
+        >>> bs.pop_left(2)
+        [1, 1]
+
+        >>> bs
+        [0, 0, 0, 1, 0, 0]
+        """
+        if count > self._width:
+            raise ValueError('Count too large')
+        if count == 0:
+            return BitSequence()
+        if count < 0:
+            raise ValueError('Negative shift is not defined')
+        shift = self._width - count
+        bseq = self.__class__.from_int(self._int >> shift, count)
+        self._int &= (1 << shift) - 1
+        self._width -= count
+        return bseq
+
+    def pop_right_bit(self) -> bool:
+        """Pop a single bit from the right side.
+
+           :return: popped bit
+        >>> bs = BitSequence(0b11000100, 8)
+
+        >>> bs.pop_right_bit()
+        False
+
+        >>> bs
+        [1, 1, 0, 0, 0, 1, 0]
+        """
+        if self._width == 0:
+            raise RuntimeError('Empty bit sequence')
+        bit = bool(self._int & 1)
+        self._int >>= 1
+        self._width -= 1
+        return bit
+
+    def pop_left_bit(self) -> bool:
+        """Pop a single bit from the left side.
+
+           :return: popped bit
+        >>> bs = BitSequence(0b11000100, 8)
+
+        >>> bs.pop_left_bit()
+        True
+
+        >>> bs
+        [1, 0, 0, 0, 1, 0, 0]
+        >>> bs = BitSequence(1, 2048)
+
+        >>> for _ in range(2047): _ = bs.pop_left_bit()
+
+        >>> bs
+        [1]
+        """
+        if self._width == 0:
+            raise RuntimeError('Empty bit sequence')
+        bit = bool(self._int >> (self._width - 1))
+        self._width -= 1
+        self._int &= self.mask
+        return bit
+
+    def rll(self, count: int = 1) -> 'BitSequence':
+        """Rotate Left Logical.
+
+           :return: self
+
+        >>> BitSequence(0b11000100, 8).rll(3)
+        [0, 0, 1, 0, 0, 1, 1, 0]
+        """
+        count %= self._width
+        bseq = self.pop_left(count)
+        self.push_right(bseq)
+        return self
+
+    def rrl(self, count: int = 1) -> 'BitSequence':
+        """Rotate Right Logical.
+
+           :return: self
+
+        >>> BitSequence(0b11000100, 8).rrl(3)
+        [1, 0, 0, 1, 1, 0, 0, 0]
+        """
+        count %= self._width
+        bseq = self.pop_right(count)
+        self.push_left(bseq)
+        return self
+
+    def inc(self, wrap: bool = True) -> 'BitSequence':
+        """Increment the sequence.
+
+        >>> BitSequence(0b11000100, 8).inc()
+        [1, 1, 0, 0, 0, 1, 0, 1]
+        """
+        self._int += 1
+        if not wrap:
+            if self._int >> self._width:
+                self._width += 1
+        else:
+            self._int &= self.mask
+        return self
+
+    def dec(self, wrap: bool = True) -> 'BitSequence':
+        """Decrement the sequence.
+
+        >>> BitSequence(0b11000100, 8).dec()
+        [1, 1, 0, 0, 0, 0, 1, 1]
+        """
+        self._int -= 1
+        if not wrap:
+            if not self._int >> self._width:
+                self._width -= 1
+        else:
+            self._int &= self.mask
+        return self
+
+    def invariant(self) -> bool:
+        """Tells whether all bits of the sequence are of the same value.
+
+           :return: the value
+           :raise ValueError: if the bits are not of the same value
+
+        >>> BitSequence(0b111, 3).invariant()
+        True
+        >>> BitSequence(0b000, 3).invariant()
+        False
+        >>> BitSequence(0b010, 3).invariant()
+        Traceback (most recent call last):
+        ...
+        BitSequenceError: Bits do no match
+        """
+        if self._int == 0:
+            return False
+        if self._int == self.mask:
+            return True
+        raise BitSequenceError('Bits do no match')
+
+    class Iterator:
+        """BitSequence iterator.
+
+           Iterate from left to right (MSB to LSB) if reverse is not set.
+
+           :param bseq: the BitSequence to iterate
+           :param reverse: whether to create a reverse iterator
+
+           >>> for b in BitSequence(): pass
+
+        """
+
+        def __init__(self, bseq: 'BitSequence', reverse: bool = False):
+            """
+            >>> bsit = BitSequence.Iterator(BitSequence())
+
+            >>> is_iterable(bsit)
+            True
+            """
+            self._bseq = bseq
+            self._reverse = reverse
+            self._width = bseq._width
+            self._pos = 0
+
+        def __iter__(self) -> 'BitSequence.Iterator':
+            """
+            >>> bsit = BitSequence.Iterator(BitSequence())
+
+            >>> iter(bsit) == bsit
+            True
+            """
+            return self
+
+        def __next__(self) -> bool:
+            """
+            >>> bsit = BitSequence.Iterator(BitSequence([0]))
+
+            >>> next(bsit)
+            False
+
+            >>> next(bsit)
+            Traceback (most recent call last):
+            ...
+            StopIteration
+            """
+            if self._width != self._bseq._width:
+                raise RuntimeError('BitSequence modified while iterating')
+            if self._pos >= self._bseq._width:
+                raise StopIteration()
+            if self._reverse:
+                bit = bool((self._bseq._int >> self._pos) & 1)
+            else:
+                pos = self._width - self._pos - 1
+                bit = bool((self._bseq._int >> pos) & 1)
+            self._pos += 1
+            return bit
+
+    def __iter__(self) -> 'BitSequence.Iterator':
+        """Iterate from left to right, i.e. MSB to LSB.
+
+           >>> [not b for b in BitSequence(0b11000100, 8)]
+           [False, False, True, True, True, False, True, True]
+        """
+        return self.__class__.Iterator(self)
+
+    def __reversed__(self):
+        """Iterate from right to left, i.e. LSB to MSB.
+
+           >>> [not b for b in reversed(BitSequence(0b11000100, 8))]
+           [True, True, False, True, True, True, False, False]
+        """
+        return self.__class__.Iterator(self, reverse=True)
+
+    def __eq__(self, other: 'BitSequence') -> bool:
+        """
+        >>> bs1 = BitSequence(0b10011, 5)  # 10011
+
+        >>> bs2 = BitSequence(0b11001, 5)  # 11001
+
+        >>> bs3 = bs2.copy().reverse()
+
+        >>> bs1 == bs3
+        True
+        >>> bs1 == bs2
+        False
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError(f'Cannot compare with {type(other)}')
+        return self._cmp(other) == 0
+
+    def __ne__(self, other: 'BitSequence') -> bool:
+        """
+        >>> BitSequence(0b10011, 5) != BitSequence(0b11001, 5)
+        True
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError(f'Cannot compare with {type(other)}')
+        return not self == other
+
+    def __le__(self, other: 'BitSequence') -> bool:
+        """
+        >>> BitSequence(0b10011, 5) <= BitSequence(0b11001, 5)
+        True
+        >>> BitSequence(0b11001, 5) <= BitSequence(0b11001, 5)
+        True
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError(f'Cannot compare with {type(other)}')
+        return self._cmp(other) <= 0
+
+    def __lt__(self, other: 'BitSequence') -> bool:
+        """
+        >>> BitSequence(0b10011, 5) < BitSequence(0b11001, 5)
+        True
+        >>> BitSequence(0b11001, 5) < BitSequence(0b11001, 5)
+        False
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError(f'Cannot compare with {type(other)}')
+        return self._cmp(other) < 0
+
+    def __ge__(self, other: 'BitSequence') -> bool:
+        """
+        >>> BitSequence(0b11001, 5) >= BitSequence(0b10011, 5)
+        True
+        >>> BitSequence(0b11001, 5) >= BitSequence(0b11001, 5)
+        True
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError(f'Cannot compare with {type(other)}')
+        return self._cmp(other) >= 0
+
+    def __gt__(self, other: 'BitSequence') -> bool:
+        """
+        >>> BitSequence(0b11001, 5) > BitSequence(0b10011, 5)
+        True
+        >>> BitSequence(0b11001, 5) > BitSequence(0b11001, 5)
+        False
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError(f'Cannot compare with {type(other)}')
+        return self._cmp(other) > 0
+
+    def _cmp(self, other: 'BitSequence') -> int:
+        # the bit sequence should be of the same length
+        """
+        >>> BitSequence(0b11001, 5)._cmp(BitSequence(0b10011, 5))
+        6
+        >>> BitSequence(0b11001, 5)._cmp(BitSequence(0b11001, 6))
+        -1
+        >>> BitSequence(0b10011, 5)._cmp(BitSequence(0b11001, 5))
+        -6
+        >>> BitSequence(0b11001, 5)._cmp(BitSequence(0b11001, 5))
+        0
+        """
+        wdiff = self._width - other._width
+        if wdiff:
+            return wdiff
+        return self._int - other._int
+
+    def __and__(self, other: 'BitSequence') -> 'BitSequence':
+        """
+        >>> BitSequence(0b10011, 5) & BitSequence(0b11001, 5)
+        [1, 0, 0, 0, 1]
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError('Need a BitSequence to combine')
+        if self._width != other._width:
+            raise ValueError('Sequences must be the same size')
+        value = self._int & other._int
+        return self.__class__.from_int(value, self._width)
+
+    def __or__(self, other: 'BitSequence') -> 'BitSequence':
+        """
+        >>> BitSequence(0b10011, 5) | BitSequence(0b11001, 5)
+        [1, 1, 0, 1, 1]
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError('Need a BitSequence to combine')
+        if self._width != other._width:
+            raise ValueError('Sequences must be the same size')
+        value = self._int | other._int
+        return self.__class__.from_int(value, self._width)
+
+    def __xor__(self, other: 'BitSequence') -> 'BitSequence':
+        """
+        >>> BitSequence(0b10011, 5) ^ BitSequence(0b11001, 5)
+        [0, 1, 0, 1, 0]
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError('Need a BitSequence to combine')
+        if self._width != other._width:
+            raise ValueError('Sequences must be the same size')
+        value = self._int ^ other._int
+        return self.__class__.from_int(value, self._width)
+
+    def __iand__(self, other: 'BitSequence') -> 'BitSequence':
+        """
+        >>> bs = BitSequence(0b10011, 5)
+
+        >>> bs &= BitSequence(0b11001, 5)
+
+        >>> bs
+        [1, 0, 0, 0, 1]
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError('Need a BitSequence to combine')
+        if self._width != other._width:
+            raise ValueError('Sequences must be the same size')
+        self._int &= other._int
+        return self
+
+    def __ior__(self, other: 'BitSequence') -> 'BitSequence':
+        """
+        >>> bs = BitSequence(0b10011, 5)
+
+        >>> bs |= BitSequence(0b11001, 5)
+
+        >>> bs
+        [1, 1, 0, 1, 1]
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError('Need a BitSequence to combine')
+        if self._width != other._width:
+            raise ValueError('Sequences must be the same size')
+        self._int |= other._int
+        return self
+
+    def __ixor__(self, other: 'BitSequence') -> 'BitSequence':
+        """
+        >>> bs = BitSequence(0b10011, 5)
+
+        >>> bs ^= BitSequence(0b11001, 5)
+
+        >>> bs
+        [0, 1, 0, 1, 0]
+        """
+        if not isinstance(other, self.__class__):
+            raise ValueError('Need a BitSequence to combine')
+        if self._width != other._width:
+            raise ValueError('Sequences must be the same size')
+        self._int ^= other._int
+        return self
+
+    def __invert__(self) -> 'BitSequence':
+        """
+        >>> ~BitSequence(0b10011, 5)
+        [0, 1, 1, 0, 0]
+        """
+        value = (~self._int) & self.mask
+        return self.__class__.from_int(value, self._width)
+
+    def __ilshift__(self, count) -> 'BitSequence':
+        """
+        >>> bs = BitSequence(0b10011, 5)
+
+        >>> bs <<= 1
+
+        >>> bs
+        [0, 0, 1, 1, 0]
+        """
+        value = (self._int << count) & self.mask
+        return self.__class__.from_int(value, self._width)
+
+    def __irshift__(self, count) -> 'BitSequence':
+        """
+        >>> bs = BitSequence(0b10011, 5)
+
+        >>> bs >>= 1
+
+        >>> bs
+        [0, 1, 0, 0, 1]
+        """
+        value = (self._int >> count) & self.mask
+        return self.__class__.from_int(value, self._width)
+
+    def __iadd__(self, other) -> 'BitSequence':
+        """
+        >>> bs = BitSequence(0b10011, 5)
+
+        >>> bs += BitSequence([0, 1, 0])
+
+        >>> len(bs)
+        8
+
+        >>> bs
+        [1, 0, 0, 1, 1, 0, 1, 0]
+        """
+        if not isinstance(other, self.__class__):
+            raise TypeError(f"unsupported operand type(s) for +=: "
+                            f"'{self.__class__.__name__}' and "
+                            f"'{other.__class__.__name__}'")
+        self._width += other._width
+        self._int <<= other._width
+        self._int |= other._int
+        return self
+
+    def __getitem__(self, index) -> 'BitSequence':
+        """
+        >>> bs = BitSequence(0b11000100, 8)
+
+        >>> bs[0]
+        [1]
+        >>> bs[1]
+        [1]
+        >>> bs[2]
+        [0]
+        >>> bs[-3]
+        [1]
+        >>> bs[-2]
+        [0]
+        >>> bs[-1]
+        [0]
+        >>> bs[0:5]
+        [1, 1, 0, 0, 0]
+        >>> bs[-4:-1]
+        [0, 1, 0]
+        >>> bs[:-2]
+        [1, 1, 0, 0, 0, 1]
+        >>> bs[::-1]
+        [0, 0, 1, 0, 0, 0, 1, 1]
+        >>> bs[-5::-2]
+        [0, 1]
+        """
+        if isinstance(index, slice):
+            bits: list[int] = []
+            length = self._width
+            start = index.start
+            stop = index.stop
+            step = index.step or 1
+            if start is None:
+                start = 0 if step > 0 else length
+            elif start < 0:
+                start = max(0, length+start)
+            if stop is None:
+                stop = length if step > 0 else 0
+            elif stop < 0:
+                stop = min(length+stop, length)
+            off = -1 if step > 0 else 0
+            for bpos in range(start, stop, step):
+                bits.append((self._int >> (self._width - bpos + off)) & 1)
+            return self.__class__.from_iterable(bits)
+        if not isinstance(index, int):
+            raise TypeError(f'{self.__class__.__name__} indices must be '
+                            f'integers or slices, not {type(index)}')
+        if ~index >= self._width:
+            raise IndexError(f'{self.__class__.__name__} index out of range')
+        if index >= 0:
+            value = (self._int >> (self._width - index - 1)) & 1
+        else:
+            value = (self._int >> (- index - 1)) & 1
+        return self.__class__.from_int(value, 1)
+
+    def __setitem__(self, index, value) -> None:
+        """
+        >>> bs = BitSequence(0b11000100, 8)
+
+        >>> bs[-1] = True
+
+        >>> bs
+        [1, 1, 0, 0, 0, 1, 0, 1]
+        >>> bs[1] = 0
+
+        >>> bs
+        [1, 0, 0, 0, 0, 1, 0, 1]
+        >>> bs[8] = 0
+        Traceback (most recent call last):
+        ...
+        IndexError: BitSequence index out of range
+        >>> bs[2:4] = [1, 1]
+
+        >>> bs
+        [1, 0, 1, 1, 0, 1, 0, 1]
+        >>> bs[7] = False
+
+        >>> bs
+        [1, 0, 1, 1, 0, 1, 0, 0]
+
+        >>> bs[-3:] = [0, 1, 1]
+
+        >>> bs
+        [1, 0, 1, 1, 0, 0, 1, 1]
+
+        >>> bs = BitSequence(0, 8)
+
+        >>> bs[-5::-2] = [1, 1]
+
+        >>> bs
+        [0, 1, 0, 1, 0, 0, 0, 0]
+
+        >>> bs[-5::-2] = [1, 1, 1]
+        Traceback (most recent call last):
+        ...
+        ValueError: Cannot assign sequence of size 3 to ext. slice of size 2
+        """
+        if isinstance(index, slice):
+            if not isinstance(value, BitSequence):
+                if not is_iterable(value):
+                    raise TypeError(f'Cannot set item with {type(value)}')
+                value = self.from_iterable(value)
+            else:
+                value = value.copy()
+            length = self._width
+            start = index.start
+            stop = index.stop
+            step = index.step or 1
+            if start is None:
+                start = 0 if step > 0 else length
+            elif start < 0:
+                start = max(0, length+start)
+            if stop is None:
+                stop = length if step > 0 else 0
+            elif stop < 0:
+                stop = min(length+stop, length)
+            slen = len(range(start, stop, step))
+            vlen = len(value)
+            if slen != len(value):
+                raise ValueError(f'Cannot assign sequence of size {vlen} '
+                                 f'to ext. slice of size {slen}')
+            nint = self._int
+            for bpos in range(start, stop, step):
+                pos = length - 1 - bpos
+                if value.pop_left_bit():
+                    nint |= 1 << pos
+                else:
+                    nint &= ~(1 << pos)
+            if value:
+                raise ValueError('Slice assignment does not support width '
+                                 'extension')
+            self._int = nint
+            return
+        if not isinstance(index, int):
+            raise TypeError(f'{self.__class__.__name__} indices must be '
+                            f'integers or slices, not {type(index)}')
+        if isinstance(value, BitSequence):
+            value = value.tobit()
+        elif isinstance(value, int):
+            if value not in (0, 1):
+                raise ValueError('Invalid value')
+        if index >= 0:
+            bpos = self._width - index - 1
+        else:
+            bpos = - index - 1
+        if not 0 <= bpos < self._width:
+            raise IndexError(f'{self.__class__.__name__} index out of range')
+        if bool(value):
+            self._int |= 1 << bpos
+        else:
+            self._int &= ~(1 << bpos)
+
+
+def is_iterable(obj: Any) -> bool:
+    """Tells whether an instance is iterable or not.
+
+       :param obj: the instance to test
+       :type obj: object
+       :return: True if the object is iterable
+       :rtype: bool
+
+    >>> is_iterable(None)
+    False
+    >>> is_iterable(42)
+    False
+    >>> is_iterable((None,))
+    True
+    >>> is_iterable('abc')
+    True
+    >>> is_iterable([])
+    True
+    >>> is_iterable({})
+    True
+    >>> is_iterable(set())
+    True
+    >>> is_iterable(is_iterable)
+    False
+    """
+    try:
+        iter(obj)
+        return True
+    except TypeError:
+        return False
+
+
+if __name__ == "__main__":
+    # note: tests expect an empty BitSequence.NIBBLE_SEP string
+    import doctest
+    doctest.testmod()
diff --git a/python/qemu/jtagtools/jtag/__init__.py b/python/qemu/jtagtools/jtag/__init__.py
new file mode 100644
index 0000000000000..ee213f2d6884d
--- /dev/null
+++ b/python/qemu/jtagtools/jtag/__init__.py
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Rivos Inc. Emmanuel Blot <eblot@rivosinc.com>
+# Copyright (c) 2010-2024, Emmanuel Blot <emmanuel.blot@free.fr>
+# Copyright (c) 2025 lowRISC contributors.
+# All rights reserved.
+#
+# SPDX-License-Identifier: Apache2
+
+"""JTAG Tools."""
+
+from .controller import JtagController  # noqa: F401
+from .engine import JtagEngine  # noqa: F401
+from .error import JtagError  # noqa: F401
diff --git a/python/qemu/jtagtools/jtag/controller.py b/python/qemu/jtagtools/jtag/controller.py
new file mode 100644
index 0000000000000..799c3695ccba3
--- /dev/null
+++ b/python/qemu/jtagtools/jtag/controller.py
@@ -0,0 +1,73 @@
+# Copyright (c) 2024 Rivos Inc. Emmanuel Blot <eblot@rivosinc.com>
+# Copyright (c) 2010-2024, Emmanuel Blot <emmanuel.blot@free.fr>
+# Copyright (c) 2016, Emmanuel Bouaziz <ebouaziz@free.fr>
+# All rights reserved.
+#
+# SPDX-License-Identifier: Apache2
+
+"""JTAG controller API."""
+
+from ..bits import BitSequence
+
+
+class JtagController:
+    """JTAG master API."""
+
+    INSTRUCTIONS = {'bypass': 0x0, 'idcode': 0x1}
+    """Common instruction register codes."""
+
+    def tap_reset(self, use_trst: bool = False) -> None:
+        """Reset the TAP controller.
+
+           :param use_trst: use TRST HW wire if available
+        """
+        raise NotImplementedError('ABC')
+
+    def system_reset(self) -> None:
+        """Reset the device."""
+
+    def quit(self) -> None:
+        """Terminate session."""
+
+    def scan(self) -> BitSequence:
+        """Flush output buffer and read back the requested BitSequence.
+        """
+        raise NotImplementedError('ABC')
+
+    def write_tms(self, modesel: BitSequence, read_tdo: bool = False) -> None:
+        """Change the TAP controller state.
+
+           :note: modesel content may be consumed, i.e. emptied
+           :note: last TMS bit should be stored and clocked on next write
+                  request
+
+           :param modesel: the bit sequence of TMS bits to clock in
+           :param read_tdo: whether to read back the TDO bit on the first CLK
+                            cycle of the TMS sequence
+        """
+        raise NotImplementedError('ABC')
+
+    def write(self, out: BitSequence) -> None:
+        """Write a sequence of bits to TDI.
+
+           :note: out content may be consumed, i.e. emptied
+           :param out: the bit sequence of TDI bits to clock in
+        """
+        raise NotImplementedError('ABC')
+
+    def read(self, length: int) -> None:
+        """Read out a sequence of bits from TDO.
+
+           :param length: the number of bits to clock out from the remote
+                          device
+        """
+        raise NotImplementedError('ABC')
+
+    def exchange(self, out: BitSequence) -> BitSequence:
+        """Write a sequence to TDI and read out a sequence of the same length
+           from TDO
+
+           :param out: the bit sequence of TDI bits to clock in
+           :return: the bit sequence received from TDO
+        """
+        raise NotImplementedError('ABC')
diff --git a/python/qemu/jtagtools/jtag/engine.py b/python/qemu/jtagtools/jtag/engine.py
new file mode 100644
index 0000000000000..afe43fa5ed4cf
--- /dev/null
+++ b/python/qemu/jtagtools/jtag/engine.py
@@ -0,0 +1,116 @@
+# Copyright (c) 2024 Rivos Inc. Emmanuel Blot <eblot@rivosinc.com>
+# Copyright (c) 2010-2024, Emmanuel Blot <emmanuel.blot@free.fr>
+# Copyright (c) 2016, Emmanuel Bouaziz <ebouaziz@free.fr>
+# All rights reserved.
+#
+# SPDX-License-Identifier: Apache2
+
+"""JTAG engine."""
+
+from logging import getLogger
+
+from ..bits import BitSequence
+from .controller import JtagController
+from .machine import JtagStateMachine
+
+
+class JtagEngine:
+    """High-level JTAG engine."""
+
+    def __init__(self, ctrl: 'JtagController'):
+        self._ctrl = ctrl
+        self._log = getLogger('jtag.eng')
+        self._fsm = JtagStateMachine()
+        self._tr_cache: dict[tuple[str,  # from state
+                                   str],  # to state
+                             BitSequence] = {}  # TMS sequence
+        self._seq = bytearray()
+
+    @property
+    def fsm(self) -> JtagStateMachine:
+        """Return the state machine."""
+        return self._fsm
+
+    @property
+    def controller(self) -> 'JtagController':
+        """Return the JTAG controller."""
+        return self._ctrl
+
+    def reset(self) -> None:
+        """Reset the attached TAP controller."""
+        self._ctrl.tap_reset()
+        self._fsm.reset()
+
+    def get_available_statenames(self):
+        """Return a list of supported state names."""
+        return [str(s) for s in self._fsm.states]
+
+    def scan(self) -> BitSequence:
+        """Perform a JTAG scan, where all buffered TDI bits are sent and
+           incoming TDO bits are returned.
+
+           :return: the received TDO bits.
+        """
+        return self._ctrl.scan()
+
+    def change_state(self, statename, read_tdo: bool = False) -> None:
+        """Advance the TAP controller to the defined state"""
+        transition = (self._fsm.state.name, statename)
+        if transition not in self._tr_cache:
+            # find the state machine path to move to the new instruction
+            path = self._fsm.find_path(statename)
+            self._log.debug('new path: %s',
+                            ', '.join((str(s).upper() for s in path[1:])))
+            # convert the path into an event sequence
+            events = self._fsm.get_events(path)
+            self._tr_cache[transition] = events
+        else:
+            # transition already in cache
+            events = self._tr_cache[transition]
+        # update the remote device tap controller (write TMS consumes the seq)
+        self._ctrl.write_tms(events.copy(), read_tdo)
+        self._log.debug('change state to %s', statename)
+        # update the current state machine's state
+        self._fsm.handle_events(events.copy())
+
+    def go_idle(self) -> None:
+        """Schedule the TAP controller to go to the IDLE state."""
+        self.change_state('run_test_idle')
+
+    def run(self) -> None:
+        """Schedule the TAP controller to go to the IDLE state."""
+        self.change_state('run_test_idle')
+
+    def capture_ir(self) -> None:
+        """Schedule the capture of the current instruction from the TAP
+           controller."""
+        self.change_state('capture_ir')
+
+    def write_ir(self, instruction: BitSequence) -> None:
+        """Schedule an instruction to be sent to the TAP controller."""
+        self.change_state('shift_ir')
+        self._ctrl.write(instruction)
+        self.change_state('update_ir')
+
+    def capture_dr(self) -> None:
+        """Schedule the current data register of the TAP controller to be
+           read."""
+        self.change_state('capture_dr')
+
+    def write_dr(self, data: BitSequence) -> None:
+        """Schedule data to be written to the TAP controller."""
+        self.change_state('shift_dr')
+        self._ctrl.write(data)
+        self.change_state('update_dr')
+
+    def read_dr(self, length: int) -> None:
+        """Schedule data register to be retrieved from the TAP controller."""
+        self.change_state('shift_dr')
+        self._ctrl.read(length-1)
+        self.change_state('update_dr', True)
+
+    def exchange_dr(self, data: BitSequence) -> None:
+        """Schedule data register content exchange."""
+        self.change_state('shift_dr')
+        self._ctrl.exchange(data)
+        self.change_state('update_dr', True)
diff --git a/python/qemu/jtagtools/jtag/error.py b/python/qemu/jtagtools/jtag/error.py
new file mode 100644
index 0000000000000..9c9c0840d7f69
--- /dev/null
+++ b/python/qemu/jtagtools/jtag/error.py
@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Rivos Inc. Emmanuel Blot <eblot@rivosinc.com>
+# Copyright (c) 2010-2024, Emmanuel Blot <emmanuel.blot@free.fr>
+# Copyright (c) 2025 lowRISC contributors.
+# All rights reserved.
+#
+# SPDX-License-Identifier: Apache2
+
+"""JTAG Errors"""
+
+
+class JtagError(Exception):
+    """Generic JTAG error."""
+
+
+class JtagStateError(JtagError):
+    """JTAG state machine error."""
diff --git a/python/qemu/jtagtools/jtag/machine.py b/python/qemu/jtagtools/jtag/machine.py
new file mode 100644
index 0000000000000..ac22eebd49e33
--- /dev/null
+++ b/python/qemu/jtagtools/jtag/machine.py
@@ -0,0 +1,181 @@
+# Copyright (c) 2010-2024, Emmanuel Blot <emmanuel.blot@free.fr>
+# Copyright (c) 2016, Emmanuel Bouaziz <ebouaziz@free.fr>
+# All rights reserved.
+#
+# SPDX-License-Identifier: Apache2
+
+"""JTAG state machine."""
+
+from logging import getLogger
+from typing import Union
+
+from .error import JtagStateError
+from ..bits import BitSequence
+
+
+class JtagState:
+    """Test Access Port controller state.
+
+       :param name: the name of the state
+       :param modes: categories to which the state belongs
+    """
+
+    def __init__(self, name: str, modes: tuple[str, str]):
+        self.name = name
+        self.modes = modes
+        self.exits = [self, self]  # dummy value before initial configuration
+
+    def __str__(self):
+        return self.name
+
+    def __repr__(self):
+        return self.name
+
+    def setx(self, fstate: 'JtagState', tstate: 'JtagState'):
+        """Define the two exit state of a state."""
+        self.exits = [fstate, tstate]
+
+    def getx(self, event) -> 'JtagState':
+        """Retrieve the exit state of the state.
+
+           :param event: evaluated as a boolean value
+           :return: next state
+        """
+        return self.exits[int(bool(event))]
+
+    def is_of(self, mode: str) -> bool:
+        """Report if the state is a member of the specified mode."""
+        return mode in self.modes
+
+
+class JtagStateMachine:
+    """Test Access Port controller state machine."""
+
+    def __init__(self):
+        self._log = getLogger('jtag.fsm')
+        self.states = {}
+        for state, modes in [('test_logic_reset', ('reset', ' idle')),
+                             ('run_test_idle', ('idle',)),
+                             ('select_dr_scan', ('dr',)),
+                             ('capture_dr', ('dr', 'shift', 'capture')),
+                             ('shift_dr', ('dr', 'shift')),
+                             ('exit_1_dr', ('dr', 'update', 'pause')),
+                             ('pause_dr', ('dr', 'pause')),
+                             ('exit_2_dr', ('dr', 'shift', 'udpate')),
+                             ('update_dr', ('dr', 'idle')),
+                             ('select_ir_scan', ('ir',)),
+                             ('capture_ir', ('ir', 'shift', 'capture')),
+                             ('shift_ir', ('ir', 'shift')),
+                             ('exit_1_ir', ('ir', 'udpate', 'pause')),
+                             ('pause_ir', ('ir', 'pause')),
+                             ('exit_2_ir', ('ir', 'shift', 'update')),
+                             ('update_ir', ('ir', 'idle'))]:
+            self.states[state] = JtagState(state, modes)
+        self['test_logic_reset'].setx(self['run_test_idle'],
+                                      self['test_logic_reset'])
+        self['run_test_idle'].setx(self['run_test_idle'],
+                                   self['select_dr_scan'])
+        self['select_dr_scan'].setx(self['capture_dr'],
+                                    self['select_ir_scan'])
+        self['capture_dr'].setx(self['shift_dr'], self['exit_1_dr'])
+        self['shift_dr'].setx(self['shift_dr'], self['exit_1_dr'])
+        self['exit_1_dr'].setx(self['pause_dr'], self['update_dr'])
+        self['pause_dr'].setx(self['pause_dr'], self['exit_2_dr'])
+        self['exit_2_dr'].setx(self['shift_dr'], self['update_dr'])
+        self['update_dr'].setx(self['run_test_idle'],
+                               self['select_dr_scan'])
+        self['select_ir_scan'].setx(self['capture_ir'],
+                                    self['test_logic_reset'])
+        self['capture_ir'].setx(self['shift_ir'], self['exit_1_ir'])
+        self['shift_ir'].setx(self['shift_ir'], self['exit_1_ir'])
+        self['exit_1_ir'].setx(self['pause_ir'], self['update_ir'])
+        self['pause_ir'].setx(self['pause_ir'], self['exit_2_ir'])
+        self['exit_2_ir'].setx(self['shift_ir'], self['update_ir'])
+        self['update_ir'].setx(self['run_test_idle'], self['select_dr_scan'])
+        self._current = self['test_logic_reset']
+        self._tr_cache: dict[tuple[str,  # current state name
+                                   int,  # event length
+                                   int],  # event value
+                             JtagState] = {}  # new state
+
+    def __getitem__(self, name: str) -> JtagState:
+        return self.states[name]
+
+    @property
+    def state(self) -> JtagState:
+        """Return the current state."""
+        return self._current
+
+    def state_of(self, mode: str) -> bool:
+        """Report if the current state is of the specified mode."""
+        return self._current.is_of(mode)
+
+    def reset(self):
+        """Reset the state machine."""
+        self._current = self['test_logic_reset']
+
+    def find_path(self, target: Union[JtagState, str],
+                  source: Union[JtagState, str, None] = None) \
+            -> list[JtagState]:
+        """Find the shortest event sequence to move from source state to
+           target state. If source state is not specified, used the current
+           state.
+
+           :return: the list of states, including source and target states.
+        """
+        if source is None:
+            source = self.state
+        if isinstance(source, str):
+            source = self[source]
+        if isinstance(target, str):
+            target = self[target]
+
+        def next_path(state, target, path):
+            # this test match the target, path is valid
+            if state == target:
+                return path+[state]
+            # candidate paths
+            paths = []
+            for xstate in state.exits:
+                # next state is self (loop around), kill the path
+                if xstate == state:
+                    continue
+                # next state already in upstream (loop back), kill the path
+                if xstate in path:
+                    continue
+                # try the current path
+                npath = next_path(xstate, target, path + [state])
+                # downstream is a valid path, store it
+                if npath:
+                    paths.append(npath)
+            # keep the shortest path
+            return min(((len(path), path) for path in paths),
+                       key=lambda x: x[0])[1] if paths else []
+        return next_path(source, target, [])
+
+    @classmethod
+    def get_events(cls, path):
+        """Build up an event sequence from a state sequence, so that the
+           resulting event sequence allows the JTAG state machine to advance
+           from the first state to the last one of the input sequence"""
+        events = []
+        for sstate, dstate in zip(path[:-1], path[1:]):
+            for epos, xstate in enumerate(sstate.exits):
+                if xstate == dstate:
+                    events.append(epos)
+        if len(events) != len(path) - 1:
+            raise JtagStateError("Invalid path")
+        return BitSequence(events)
+
+    def handle_events(self, events: BitSequence) -> None:
+        """State machine stepping.
+
+           :param events: a sequence of boolean events to advance the FSM.
+        """
+        transit = (self._current.name, len(events), int(events))
+        if transit in self._tr_cache:
+            self._current = self._tr_cache[transit]
+            return
+        for event in events:
+            self._current = self._current.getx(event)
+        self._tr_cache[transit] = self._current
diff --git a/python/qemu/jtagtools/rbb/__init__.py b/python/qemu/jtagtools/rbb/__init__.py
new file mode 100644
index 0000000000000..452dee860cd2f
--- /dev/null
+++ b/python/qemu/jtagtools/rbb/__init__.py
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Rivos Inc. Emmanuel Blot <eblot@rivosinc.com>
+# Copyright (c) 2025 lowRISC contributors.
+# All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+"""JTAG Remote BitBang Controller"""
+
+from .bitbang import JtagBitbangController  # noqa: F401
diff --git a/python/qemu/jtagtools/rbb/bitbang.py b/python/qemu/jtagtools/rbb/bitbang.py
new file mode 100644
index 0000000000000..48d74af014e4c
--- /dev/null
+++ b/python/qemu/jtagtools/rbb/bitbang.py
@@ -0,0 +1,209 @@
+# Copyright (c) 2024 Rivos Inc. Emmanuel Blot <eblot@rivosinc.com>
+# SPDX-License-Identifier: Apache2
+
+"""JTAG controller for OpenOCD/QEMU bitbang protocol.
+
+   Protocol abstract:
+
+                  TCLK TMS TDI
+    b'0' - Write    0   0   0
+    b'1' - Write    0   0   1
+    b'2' - Write    0   1   0
+    b'3' - Write    0   1   1
+    b'4' - Write    1   0   0
+    b'5' - Write    1   0   1
+    b'6' - Write    1   1   0
+    b'7' - Write    1   1   1
+
+                  TRST SRST
+    b'r' - Reset    0   0
+    b's' - Reset    0   1
+    b't' - Reset    1   0
+    b'u' - Reset    1   1
+
+    b'R' - Read request  -> b'0' or b'1'
+    b'Q' - Quit request
+"""
+
+from logging import getLogger
+from socket import socket, SOCK_STREAM, IPPROTO_TCP, TCP_NODELAY
+from time import time as now
+from typing import Optional
+
+from ..bits import BitSequence
+from ..jtag.controller import JtagController
+
+
+class JtagBitbangController(JtagController):
+    """JTAG master for Remote Bitbang connection.
+
+       :param sock: communication socket with remote QEMU JTAG server
+       :param link_log: whether to emit link log messages
+    """
+
+    DEFAULT_PORT = 3335
+    """Default TCP port."""
+
+    RECV_TIMEOUT = 2.0
+    """Maximum allowed time in seconds to receive a response from the JTAG
+       controller.
+    """
+
+    READ = ord('R')
+    """JTAG bitbang code to receive data from TDO."""
+
+    QUIT = ord('Q')
+    """JTAG bitbang code to quit."""
+
+    def __init__(self, sock: socket, link_log: bool = False):
+        self._log = getLogger('jtag.rbb')
+        self._sock = sock
+        self._link_log = link_log
+        self._last: Optional[bool] = None  # Last deferred TDO bit
+        self._outbuf = bytearray()
+        self._inlen = 0
+        self._tck = False
+        self._tms = False
+        self._tdi = False
+        self._trst = False
+        self._srst = False
+        if self._sock.proto == IPPROTO_TCP and self._sock.type == SOCK_STREAM:
+            self._sock.setsockopt(IPPROTO_TCP, TCP_NODELAY, 1)
+        self._sock.settimeout(self.RECV_TIMEOUT)
+
+    def tap_reset(self, use_trst: bool = False) -> None:
+        self._log.info('TAP reset (%s)', 'TRST' if use_trst else 'SW')
+        if use_trst:
+            self._trst = not self._trst
+            self._write(self._reset_code(self._trst, self._srst))
+            self._trst = not self._trst
+            self._write(self._reset_code(self._trst, self._srst))
+        else:
+            self.write_tms(BitSequence('11111'))
+        self.scan()
+
+    def system_reset(self) -> None:
+        self._log.info('System reset')
+        self._write(self._reset_code(self._trst, self._srst))
+        self._srst = not self._srst
+        self._write(self._reset_code(self._trst, self._srst))
+        self._srst = not self._srst
+        self._write(self._reset_code(self._trst, self._srst))
+        self.scan()
+
+    def quit(self) -> None:
+        self._log.info('Quit')
+        self._outbuf.append(self.QUIT)
+        self.scan()
+
+    def scan(self) -> BitSequence:
+        if self._outbuf:
+            if self._link_log:
+                self._log.debug('write %d bytes to TDI', len(self._outbuf))
+            self._sock.send(self._outbuf)
+            self._outbuf.clear()
+        bseq = BitSequence()
+        length = self._inlen
+        self._inlen = 0
+        if length:
+            timeout = now() + self.RECV_TIMEOUT
+            while length:
+                try:
+                    data = self._sock.recv(length)
+                except TimeoutError as exc:
+                    if now() < timeout:
+                        continue
+                    raise TimeoutError('No response from RBB server') from exc
+                length -= len(data)
+                bseq.push_right(data)
+                timeout = now() + self.RECV_TIMEOUT / 2
+            bseq.reverse()
+            if self._link_log:
+                self._log.debug('read TDO [%d] %s', len(bseq), bseq)
+        return bseq
+
+    def write_tms(self, modesel: BitSequence, read_tdo: bool = False) -> None:
+        if not isinstance(modesel, BitSequence):
+            raise ValueError('Expect a BitSequence')
+        # apply the last TDO bit
+        if self._last is not None:
+            self._tdi = self._last
+            self._last = None
+        else:
+            self._tdi = False
+        if self._link_log:
+            self._log.debug('write TMS [%d] %s', len(modesel), modesel)
+        tck = self._tck
+        tdi = self._tdi
+        tms = self._tms
+        read = self.READ
+        code = self._bus_code
+        while modesel:
+            tms = modesel.pop_left_bit()
+            self._outbuf.append(code(tck, tms, tdi))
+            tck = not tck
+            self._outbuf.append(code(tck, tms, tdi))
+            tck = not tck
+            if read_tdo:
+                self._outbuf.append(read)
+                self._inlen += 1
+                read_tdo = False
+        self._tms = tms
+        self._tck = tck
+
+    def write(self, out: BitSequence) -> None:
+        if not isinstance(out, BitSequence):
+            raise ValueError('out is not a BitSequence')
+        if self._last is not None:
+            # TODO: check if this case needs to be handled
+            raise NotImplementedError('Last is lost')
+        self._last = out.pop_left_bit()
+        tms = self._tms
+        tck = self._tck
+        tdi = self._tdi
+        code = self._bus_code
+        while out:
+            tdi = out.pop_right_bit()
+            self._outbuf.append(code(tck, tms, tdi))
+            tck = not tck
+            self._outbuf.append(code(tck, tms, tdi))
+            tck = not tck
+        self._tdi = tdi
+        self._tms = tms
+        self._tck = tck
+
+    def read(self, length: int) -> None:
+        if length == 0:
+            raise ValueError()
+        if self._link_log:
+            self._log.debug('read %d TDO bits, TMS: %d', length, self._tms)
+        tms = self._tms
+        tck = self._tck
+        tdi = self._tdi
+        read = self.READ
+        code = self._bus_code
+        self._inlen += length
+        while length:
+            length -= 1
+            self._outbuf.append(code(tck, tms, tdi))
+            tck = not tck
+            self._outbuf.append(code(tck, tms, tdi))
+            tck = not tck
+            self._outbuf.append(read)
+
+    def exchange(self, out: BitSequence) -> BitSequence:
+        raise NotImplementedError('RBB exchange support not implemented yet')
+
+    @classmethod
+    def _bus_code(cls, tclk: bool, tms: bool, tdi: bool) -> int:
+        return 0x30 + ((int(tclk) << 2) | (int(tms) << 1) | tdi)
+
+    @classmethod
+    def _reset_code(cls, trst: bool, srst: bool) -> int:
+        return ord('r') + ((int(trst) << 1) | srst)
+
+    def _write(self, code: int):
+        if self._link_log:
+            self._log.debug('_write 0x%02x %s (%s)', code, f'{code-0x30:03b}',
+                            chr(code))
+        self._outbuf.append(code)
diff --git a/python/qemu/ot/.flake8 b/python/qemu/ot/.flake8
new file mode 100644
index 0000000000000..15fc7e33eb08a
--- /dev/null
+++ b/python/qemu/ot/.flake8
@@ -0,0 +1,2 @@
+[flake8]
+max-line-length = 80
diff --git a/python/qemu/ot/.pylintrc b/python/qemu/ot/.pylintrc
new file mode 100644
index 0000000000000..a84380cdf78e2
--- /dev/null
+++ b/python/qemu/ot/.pylintrc
@@ -0,0 +1,17 @@
+[MESSAGES CONTROL]
+
+disable=
+    import-error,
+    too-few-public-methods,
+    too-many-arguments,
+    too-many-branches,
+    too-many-function-args,
+    too-many-instance-attributes,
+    too-many-lines,
+    too-many-locals,
+    too-many-nested-blocks,
+    too-many-positional-arguments,
+    too-many-public-methods,
+    too-many-return-statements,
+    too-many-statements,
+    unspecified-encoding
diff --git a/python/qemu/ot/__init__.py b/python/qemu/ot/__init__.py
new file mode 100644
index 0000000000000..dca8c95e274ca
--- /dev/null
+++ b/python/qemu/ot/__init__.py
@@ -0,0 +1,4 @@
+"""OpenTitan modules."""
+
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
diff --git a/python/qemu/ot/bitfield.py b/python/qemu/ot/bitfield.py
new file mode 100644
index 0000000000000..1760d767e58ae
--- /dev/null
+++ b/python/qemu/ot/bitfield.py
@@ -0,0 +1,97 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Simple BitField container.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from typing import Any
+
+from .util.misc import HexInt
+
+
+class BitField:
+    """BitField container
+    """
+
+    def __init__(self, *args, **kwargs):
+        self._bits = {}
+        self._named_bits = {}
+        for bits in args:
+            self._bits.update(bits)
+        for name, bits in kwargs.items():
+            self._named_bits[name] = {}
+            self._named_bits[name].update(bits)
+        self._selector = None
+        sels = {k: v for k, v in self._bits.items() if len(v) > 3 and v[3]}
+        if sels:
+            if len(sels) > 1:
+                raise ValueError(f'Too many selectors: {", ".join(sels)}')
+            name, desc = sels.popitem()
+            enum_ = desc[2]
+            if name != enum_.__name__:
+                raise ValueError(f'Invalid selector name: {enum_.__name__}')
+            self._selector = enum_
+
+    def decode(self, value: int) -> dict[str, Any]:
+        """Decode a value into a dictionary."""
+        bits = dict(self._bits)
+        if self._selector:
+            offset, length, enum_ = self._bits[self._selector.__name__][:3]
+            mask = (1 << length) - 1
+            val = (value >> offset) & mask
+            try:
+                sel = enum_(val).name
+            except ValueError:
+                sel = None
+            if sel:
+                bits.update(self._named_bits[sel])
+        values = {}
+        for name, code in bits.items():
+            offset, length = code[:2]
+            enum = code[2] if len(code) > 2 else None
+            mask = (1 << length) - 1
+            val = (value >> offset) & mask
+            if enum:
+                values[name] = enum(val)
+            else:
+                if length == 1:
+                    values[name] = bool(val)
+                else:
+                    values[name] = HexInt(val)
+        return values
+
+    def encode(self, *init, **values: dict[str, Any]) -> HexInt:
+        """Encode a dictionary into a value."""
+        if init:
+            value = init[0]
+            if len(init) > 1:
+                raise ValueError('Unknown argument')
+        else:
+            value = 0
+        values = dict(values)  # duplicate as entries are removed
+        bits = dict(self._bits)  # duplicate as selector may be folded into
+        if self._selector:
+            selname = self._selector.__name__
+            sel = values.get(selname)
+            if sel:
+                bits.update(self._named_bits[sel])
+        for name, code in bits.items():
+            if name not in values:
+                continue
+            val = values[name]
+            del values[name]
+            offset, length = code[:2]
+            enum = code[2] if len(code) > 2 else None
+            if enum and isinstance(val, str):
+                val = enum[val]
+            if length == 1 and isinstance(val, bool):
+                val = int(val)
+            mask = (1 << length) - 1
+            val &= mask
+            value &= ~(mask << offset)
+            value |= val << offset
+        if values:
+            raise ValueError(f'Unknown field {", ".join(values)}')
+        return HexInt(value)
diff --git a/python/qemu/ot/devproxy.py b/python/qemu/ot/devproxy.py
new file mode 100644
index 0000000000000..4880556b122bc
--- /dev/null
+++ b/python/qemu/ot/devproxy.py
@@ -0,0 +1,1888 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Device proxy for OpenTitan devices and peripherals
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import hexlify, unhexlify
+from collections import deque
+from enum import IntEnum
+from inspect import currentframe
+from logging import getLogger
+from socket import create_connection, socket, SHUT_RDWR
+from struct import calcsize as scalc, pack as spack, unpack as sunpack
+from sys import modules
+from threading import Event, Thread, get_ident
+from time import sleep, time as now
+from typing import Any, Callable, Iterator, NamedTuple, Optional, Union
+
+from .mailbox.doe import DOEHeader
+from .util.mbb import MB4_FALSE, MB4_TRUE
+
+
+try:
+    from serial import Serial, serial_for_url
+except ImportError:
+    Serial = None
+    serial_for_url = None
+
+
+class ProxyCommandError(Exception):
+    """Signal a remote proxy command execution error.
+    """
+    ERRORS = {
+        # No error
+        0: 'PE_NO_ERROR',
+        # Undefined errors
+        1: 'PE_UNKNOWN',
+        # Request errors
+        0x101: 'PE_INVALID_COMMAND_LENGTH',
+        0x102: 'PE_INVALID_COMMAND_CODE',
+        0x103: 'PE_INVALID_REQUEST_ID',
+        0x104: 'PE_INVALID_SPECIFIER_ID',
+        0x105: 'PE_INVALID_DEVICE_ID',
+        0x106: 'PE_INVALID_IRQ',
+        0x107: 'PE_INVALID_REG_ADDRESS',
+        # State error
+        0x201: 'PE_DEVICE_IN_ERROR',
+        # Local error
+        0x401: 'PE_CANNOT_READ_DEVICE',
+        0x402: 'PE_CANNOT_WRITE_DEVICE',
+        0x403: 'PE_TRUNCATED_RESPONSE',
+        0x404: 'PE_INCOMPLETE_WRITE',
+        0x405: 'PE_OOM',
+        # internal error
+        0x801: 'PE_UNSUPPORTED_DEVICE',
+        0x802: 'PE_DUPLICATED_UID'
+    }
+    """Proxy error codes."""
+
+    def __init__(self, errcode: int, msg: Optional[str] = None):
+        err = self.ERRORS.get(errcode, 'PE_UNKNOWN')
+        errmsg = f'{err}: {msg}' if msg else err
+        super().__init__(errcode, errmsg)
+
+    @property
+    def code(self) -> int:
+        """Return the code of the exception."""
+        return self.args[0]
+
+    @classmethod
+    def get_error_code(cls, name: str) -> Optional[int]:
+        """Retrieve the error code from its name
+
+           :param name: error name
+           :return: the matching error code if any
+        """
+        errors = {v: k for k, v in cls.ERRORS.items()}
+        if name not in errors:
+            getLogger('proxy.proxy').error("Unknown error '{name}'")
+            return None
+        return errors[name]
+
+    def __eq__(self, other: 'ProxyCommandError') -> bool:
+        return self.code == other.code
+
+
+class ProxyDeviceError(ProxyCommandError):
+    """Locallly generated ProxyCommandError when remote device reports iself
+       on error.
+    """
+
+    def __init__(self):
+        super().__init__(0x201, 'Device On Error')
+
+
+class MemoryRoot(NamedTuple):
+    """A root memory region.
+    """
+    name: str
+    address: int
+    size: int
+
+
+class InterruptGroup(NamedTuple):
+    """Descriptor of a named group of interrupts.
+       Interrupts follow the meaning of QEMU IRQ: an "asynchronous" wire.
+       They are not only "interrupts" between a device and an interrupt
+       controller.
+    """
+    out: bool  # output or input IRQ group
+    num: int  # group identifier
+    count: int  # number of IRQ lines in the group
+
+
+class MemoryHitEvent(NamedTuple):
+    """Event triggered when a memory watcher has been matched."""
+    address: int
+    value: int
+    write: bool
+    width: int
+    role: int
+
+
+InterruptHandler = Callable[['DeviceProxy', str, int, int, Any], None]
+"""qemu_irq handler (device, group name, channel, value, *args)
+"""
+
+RequestHandler = Callable[[str, bytes, Any], None]
+"""Remote request handler."""
+
+
+MemoryWatcherHandler = Callable[[MemoryHitEvent, Any], None]
+"""Memory Watcher handler."""
+
+
+class DeviceProxy:
+    """Remote device wrapper.
+
+       Expose a generic API to manage a remove QEMU DeviceState (mostly
+       SysBusDeviceState)
+
+       :param proxy: the parent communication proxy
+       :param name: an arbitrary name to identify this device
+       :param devid: unique device identifier for the communication proxy
+       :param base: base address of the device in CPU space
+       :param offset: relative base address for the first register in the remote
+                    device (usually 0)
+       :paran regcount: count of 32-bit registers in the remote device
+    """
+
+    NO_ROLE = 0xf
+    """Disabled role."""
+
+    IRQ_NAME = 'sysbus-irq'
+    """SysBus Interrupt IRQ identifier."""
+
+    ALERT_NAME = 'ot-alert-sig'
+    """OpenTitan Alert IRQ identifier."""
+
+    def __init__(self, proxy: 'ProxyEngine', name: str, devid: int, addr: int,
+                 count: int, offset: int):
+        logname = self.__class__.__name__.lower().replace('proxy', '')
+        self._log = getLogger(f'proxy.{logname}')
+        if offset > 0xffff:
+            raise ValueError(f'Invalid address 0x{offset:02x}')
+        self._proxy = proxy
+        self._name = name
+        self._devid = devid
+        self._addr = addr
+        self._regcount = count
+        self._offset = offset * 4
+        self._end = offset + count * 4
+        self._interrupts: Optional[dict[str, InterruptGroup]] = None
+        self._interrupt_handler: Optional[InterruptHandler] = None
+        self._interrupt_args: list[Any] = []
+        self._new()
+
+    @property
+    def proxy(self) -> 'ProxyEngine':
+        """Return the proxy engine."""
+        return self._proxy
+
+    @property
+    def uid(self) -> int:
+        """Provide the unique device identifier in this environment."""
+        return self._devid
+
+    def __str__(self) -> str:
+        return f'{self.__class__.__name__} ({self._devid})'
+
+    def read_word(self, role: int, addr: int) -> int:
+        """Read a single 32-bit word from the device.
+
+           :param role: the control access role identifier.
+           :param addr: the address (in bytes) of the register to read from
+           :return: the 32-bit value of the device register
+        """
+        if not self._offset <= addr < self._end or addr & 0x3:
+            raise ValueError(f'Invalid address 0x{addr:02x}')
+        request = spack('<HH', addr >> 2, self._make_sel(self._devid, role))
+        response = self._proxy.exchange('RW', request)
+        value, = sunpack('<I', response)
+        return value
+
+    def write_word(self, role: int, addr: int, value: int,
+                   mask: int = 0xffffffff) -> None:
+        """Write a single 32-bit word from the device.
+
+           :param role: the control access role identifier.
+           :param addr: the address (in bytes) of the register to write to
+           :param value: the 32-bit value to write into the register
+           :param mask: an optional mask. Only set bits should be updated.
+                        default to all 32 bits. If the remote device does not
+                        support setters, a read-modify-write sequence should be
+                        used.
+        """
+        if not self._offset <= addr < self._end or addr & 0x3:
+            raise ValueError(f'Invalid address 0x{addr:02x}')
+        request = spack('<HHII', addr >> 2, self._make_sel(self._devid, role),
+                        value, mask)
+        self._proxy.exchange('WW', request)
+
+    def read_buf(self, cmd: str, role: int, addr: int, dwcount: int) -> bytes:
+        """Read a sequence of 32-bit words from the device.
+
+           This function is barely used directly, it is usually called from a
+           high level function that provides the command to use to perform the
+           read operation.
+
+           :param cmd: the command to use (see Protocol documentation)
+           :param role: the control access role identifier.
+           :param addr: the address (in bytes) of the 1st register to read from
+           :param dwcount: the count of 32-bit words to read out
+           :return: the read words as a sequence of bytes (LE encoding)
+        """
+        if not self._offset <= addr < self._end or addr & 0x3:
+            raise ValueError(f'Invalid address 0x{addr:02x}')
+        request = spack('<HHI', addr >> 2, self._make_sel(self._devid, role),
+                        dwcount)
+        response = self._proxy.exchange(cmd, request)
+        return response
+
+    def write_buf(self, cmd: str, role: int, addr: int, buffer: bytes) -> int:
+        """Write a sequence of 32-bit words tp the device.
+
+           This function is barely used directly, it is usually called from a
+           high level function that provides the command to use to perform the
+           write operation.
+
+           :param cmd: the command to use (see Protocol documentation)
+           :param role: the control access role identifier.
+           :param addr: the address (in bytes) of the 1st register to write to
+           :param buffer: the buffer of bytes to write to the device. Note that
+                          if the buffer length is not a multiple of 4 bytes, it
+                          is padded with trailing nul bytes
+           :return: count of written bytes (should be equal to buf length)
+        """
+        if not self._offset <= addr < self._end or addr & 0x3:
+            raise ValueError(f'Invalid address 0x{addr:02x}')
+        if not isinstance(buffer, (bytes, bytearray)):
+            raise ValueError('Invalid buffer type')
+        trailing = len(buffer) & 0x3
+        if trailing:
+            buffer = b''.join((buffer, bytes(4-trailing)))
+        request = b''.join((spack('<HH', addr >> 2,
+                            self._make_sel(self._devid, role)), buffer))
+        response = self._proxy.exchange(cmd, request)
+        respsize = scalc('<I')
+        if len(response) != respsize:
+            raise ProxyCommandError(0x403, f'expected {respsize}, '
+                                           f'received {len(response)}')
+        value, = sunpack('<I', response)
+        return value * 4
+
+    def register_interrupt_handler(self, handler: InterruptHandler, *args) \
+            -> None:
+        """Register a handler to receive notification from the remote peer.
+
+           :param handler: the handler function
+           :param args: any argument to forward to the handler
+        """
+        if self._interrupt_handler:
+            self._log.warning('Overridding previous IRQ handler')
+        self._interrupt_handler = handler
+        self._interrupt_args = args
+
+    def intercept_interrupts(self, group: int, mask: int) -> None:
+        """Request the remote proxy to intercept output interrupt for the device
+
+           Interrupted are reported to the proxy rather than delivered them to
+           their default destination. This means that the default receiver no
+           longer receive the selected interrtupts till they are explicitly
+           release, see #release_interrupts
+
+           It is safe to intercept the same interrupts several time (in which
+           case the remote proxy should ignore the requests for these IRQ
+           channels and intercept the selected ones that were not intercepted)
+
+           :param group: IRQ group identifier
+           :param mask: a bitmask of interrupt (0..31) to intercept.
+        """
+        if not isinstance(group, int) or not 0 <= group <= 0xff:
+            raise ValueError(f'Invalid group value {group}')
+        if not isinstance(mask, int) or not 0 <= mask <= 0xffff_ffff:
+            raise ValueError(f'Invalid interrupt mask {mask}')
+        request = spack('<BxHI', group, self._make_sel(self._devid), mask)
+        self._proxy.exchange('II', request)
+
+    def release_interrupts(self, group: int, mask: int) -> None:
+        """Release previously intercepted IRQ lines
+
+           Interrupted are connected back to their initial destination device.
+
+           :param group: IRQ group identifier
+           :param mask: a bitmask of interrupt (0..31) to release.
+        """
+        if not isinstance(group, int) or not 0 <= group <= 0xff:
+            raise ValueError(f'Invalid group value {group}')
+        if not isinstance(mask, int) or not 0 <= mask <= 0xffff_ffff:
+            raise ValueError(f'Invalid interrupt mask {mask}')
+        request = spack('<BxHI', group, self._make_sel(self._devid), mask)
+        self._proxy.exchange('IR', request)
+
+    def capture_sysbus_irq(self, irq: int, enable: bool) -> None:
+        """Capture or release one or more sysbus interrupts output channels.
+
+           :param irq: the interrupt number to manage
+           :param enable: whether to intercept or release IRQ channels.
+        """
+        self.capture_sysbus_irqs(1 << irq, enable)
+
+    def capture_sysbus_irqs(self, irq_mask: int, enable: bool) -> None:
+        """Capture or release one or more sysbus interrupts output channels.
+
+           :param irq: a bitfield of interrupt channel to manage
+           :param enable: whether to intercept or release IRQ channels.
+        """
+        if self._interrupts is None:
+            self._enumerate_interrupts()
+        try:
+            gnum = self._interrupts[self.IRQ_NAME].num
+        except KeyError as exc:
+            raise ValueError(f'No {self.IRQ_NAME} interruption support for '
+                             f'{self.__class__.__name__}') from exc
+        if enable:
+            self.intercept_interrupts(gnum, irq_mask)
+        else:
+            self.release_interrupts(gnum, irq_mask)
+
+    def enumerate_interrupts(self, out: bool) -> Iterator[InterruptGroup]:
+        """Enumerate supported interrupt lines.
+
+           :param out: True to enumerate output IRQ lines, False for input ones
+           :yield: enumerated tuples that contain the IRQ group name, and the
+                   count of interrupt line in this group.
+        """
+        if self._interrupts is None:
+            self._enumerate_interrupts()
+        for name, group in self._interrupts.items():
+            if group.out == out:
+                yield name, group
+
+    def signal_interrupt(self, group: str, irq: int, level: Union[int, bool]) \
+            -> None:
+        """Set the level of an input interrupt line.
+
+           :param group: the name of the group
+           :param irq: the IRQ line to signal
+           :param level: the new level for this IRQ line
+
+           The group name may be retrieved with the #enumerate_interrupts API.
+        """
+        if self._interrupts is None:
+            self._enumerate_interrupts()
+        if group not in self._interrupts:
+            raise ValueError(f"No such interrupt group '{group}'")
+        grp = self._interrupts[group]
+        if irq >= grp.count:
+            raise ValueError(f"No such interrupt {irq} in '{group}' "
+                             f"(<{grp.count})")
+        level = int(level)
+        if level >= (1 << 32):
+            raise ValueError(f'Invalied interrupt level {level}')
+        request = spack('<HHHHI', grp.num, self._make_sel(self._devid), irq, 0,
+                        level)
+        try:
+            self._proxy.exchange('IS', request)
+        except ProxyCommandError as exc:
+            self._log.fatal('%s', exc)
+            raise
+
+    def notify_interrupt(self, group: int, channel: int, value: int) -> None:
+        """Wired IRQ notification handler."""
+        if not self._interrupt_handler:
+            self._log.warning('Missed IRQ notification')
+            return
+        if self._interrupts is None:
+            self._log.error('IRQ received w/o registration')
+            return
+        for gname, igroup in self._interrupts.items():
+            if igroup.num == group:
+                if channel >= igroup.count:
+                    self._log.error('Interrupt %s out of bound: %d', gname,
+                                    channel)
+                    return
+                self._interrupt_handler(self, gname, channel, value,
+                                        *self._interrupt_args)
+                break
+        else:
+            self._log.error('Unknow interrupt group %d, ignored', igroup)
+
+    @classmethod
+    def _make_sel(cls, device: int, role: int = 0xf) -> int:
+        if not isinstance(device, int) or not 0 <= device <= 0xfff:
+            raise ValueError('Invalid device identifier')
+        if not isinstance(role, int) or not 0 <= role <= 0xf:
+            raise ValueError('Invalid device identifier')
+        return device | (role << 12)
+
+    def _new(self):
+        self._log.debug('Device %s @ 0x%08x: %s',
+                        str(self), self._addr, self._name)
+
+    def _enumerate_interrupts(self) -> None:
+        # lazy initialization interrupt enumeration is rarely used
+        request = spack('<HH', 0, self._make_sel(self._devid))
+        try:
+            irqgroups = self._proxy.exchange('IE', request)
+        except ProxyCommandError as exc:
+            self._log.fatal('%s', exc)
+            raise
+        grpfmt = '<HBB32s'
+        grplen = scalc(grpfmt)
+        if len(irqgroups) % grplen:
+            raise ValueError('Unexpected response length')
+        grpcount = len(irqgroups) // grplen
+        self._log.info('Found %d remote interrupt groups for %s', grpcount,
+                       str(self))
+        self._interrupts = {}
+        while irqgroups:
+            grphdr = irqgroups[0:grplen]
+            irqgroups = irqgroups[grplen:]
+            gcount, gnum, gdir, gname = sunpack(grpfmt, grphdr)
+            grpname = gname.rstrip(b'\x00').decode().lower()
+            if grpname in self._interrupts:
+                self._log.error("Multiple devices w/ identical identifier: "
+                                "'%s'", grpname)
+            else:
+                group = InterruptGroup(bool(gdir & 0x80), gnum, gcount)
+                self._interrupts[grpname] = group
+
+
+class MbxHostProxy(DeviceProxy):
+    """DOE Mailbox Host-side proxy.
+
+       Specialized DeviceProxy that helps communication with a remote DOE HOST
+       mailbox.
+
+       :param args: forwarded as is to the parent, see #DevicePRoxy
+       :param role: optional access role
+    """
+
+    DEVICE_ID = 'mbh'
+
+    REGS = {
+        'INTR_STATE':  0x00,
+        'INTR_ENABLE':  0x04,
+        'INTR_TEST':  0x08,
+        'ALERT_TEST':  0x0c,
+        'CONTROL':  0x10,
+        'STATUS':  0x14,
+        'ADDRESS_RANGE_REGWEN':  0x18,
+        'ADDRESS_RANGE_VALID':  0x1c,
+        'IN_BASE_ADDR':  0x20,
+        'IN_LIMIT_ADDR':  0x24,
+        'IN_WRITE_PTR':  0x28,
+        'OUT_BASE_ADDR':  0x2c,
+        'OUT_LIMIT_ADDR':  0x30,
+        'OUT_READ_PTR':  0x34,
+        'OUT_OBJECT_SIZE':  0x38,
+        'INTR_MSG_ADDR':  0x3c,
+        'INTR_MSG_DATA':  0x40,
+    }
+    """Supported registers."""
+
+    IRQS = {
+        'MSGREADY': 0,
+        'ABORT': 1,
+        'ERROR': 3,
+    }
+    """Supported IRQ channels."""
+
+    def __init__(self, *args, role: Optional[int] = None):
+        super().__init__(*args)
+        self._role = 0xff  # ensure it should be defined through set_role
+        if role is not None:
+            self.set_role(role)
+
+    def set_role(self, role: int):
+        """Set the control access role to read/write remote registers."""
+        if not isinstance(role, int) or role > 0xf:
+            raise ValueError(f'Invalid role {role}')
+        self._log.debug('%d', role)
+        self._role = role
+
+    @property
+    def role(self) -> int:
+        """Provide the current role."""
+        return self._role
+
+    @property
+    def interrupt_state(self) -> int:
+        """Report which interrupts are active.
+
+           :return: interrupt state bitfield
+        """
+        return self.read_word(self._role, self.REGS['INTR_STATE'])
+
+    def enable_interrupts(self, intrs: int) -> None:
+        """Enable interrupts.
+
+           :param intrs: the bitfield of interrupts to enable
+        """
+        self._log.debug('0x%08x', intrs)
+        self.write_word(self._role, self.REGS['INTR_ENABLE'], intrs)
+
+    def clear_interrupts(self, intrs: int) -> None:
+        """Clear interrupts.
+
+           :param intrs: the bitfield of interrupts to clear
+        """
+        self._log.debug('0x%08x', intrs)
+        self.write_word(self._role, self.REGS['INTR_STATE'], intrs)
+
+    def test_interrupts(self, intrs: int) -> None:
+        """Test interrupts.
+
+           :param intrs: the bitfield of interrupts to test
+        """
+        self._log.debug('0x%08x', intrs)
+        self.write_word(self._role, self.REGS['INTR_TEST'], intrs)
+
+    @classmethod
+    def intrnames_to_int(cls, *intrnames) -> int:
+        """Create a interrupt bitfield from interrupt names.
+        """
+        value = 0
+        for intname in intrnames:
+            irq = cls.IRQS.get(intname)
+            if irq is None:
+                raise ValueError(f"Unkwon interrupt '{intname}'")
+            value |= 1 << irq
+        return value
+
+    @classmethod
+    def is_interrupt(cls, intnum: int, intname: str) -> bool:
+        """Tell whether the object ready interrupt is raised.
+
+           :param intrs: the interrupt bitfield
+           :return: True if the object ready interrupt is raised
+        """
+        irqval = cls.IRQS.get(intname)
+        if irqval is None:
+            raise ValueError(f"Unkwon interrupt '{intname}'")
+        return intnum == irqval
+
+    def is_aborted(self) -> bool:
+        """Tell whether the system side has aborted the request.
+
+           :return: true if abort is set
+        """
+        res = (bool)(self.read_word(self._role, self.REGS['CONTROL']) & 0b001)
+        self._log.debug('%d', res)
+        return res
+
+    def is_on_error(self) -> bool:
+        """Tell whether the mailbox has detected an error.
+
+           :return: true if ERROR bit is set
+        """
+        res = (bool)(self.read_word(self._role, self.REGS['CONTROL']) & 0b010)
+        self._log.debug('%d', res)
+        return res
+
+    def is_busy(self) -> bool:
+        """Tell whether the mailbox is busy.
+
+           :return: true if BUSY bit is set
+        """
+        res = (bool)(self.read_word(self._role, self.REGS['STATUS']) & 0b001)
+        self._log.debug('%d', res)
+        return res
+
+    def is_object_ready(self) -> bool:
+        """Tell whether the mailbox contains a response.
+
+           :return: true if OBJECT READY bit is set
+        """
+        res = (bool)(self.read_word(self._role, self.REGS['STATUS']) &
+                     (1 << 31))
+        self._log.debug('%d', res)
+        return res
+
+    def is_sys_interrupt(self) -> bool:
+        """Tell whether the system side interrupt has been raised.
+
+           :return: true if INT bit is set
+        """
+        res = bool(self.read_word(self._role, self.REGS['STATUS']) & 0b010)
+        self._log.debug('%d', res)
+        return res
+
+    def is_sys_interrupt_enabled(self) -> bool:
+        """Tell whether the system side has requested to be signalled with an
+           interrupt.
+
+           :return: true if interrupt mode is enabled
+        """
+        res = (bool)(self.read_word(self._role, self.REGS['STATUS']) & 0b100)
+        self._log.debug('%d', res)
+        return res
+
+    def acknowledge_abort(self) -> None:
+        """Finalize abort handling.
+        """
+        self._log.debug('')
+        self.write_word(self._role, self.REGS['CONTROL'], 0b01, 0b01)
+
+    def set_error(self) -> bool:
+        """Signal the request cannot be handled because of an error
+        """
+        self._log.debug('')
+        self.write_word(self._role, self.REGS['CONTROL'], 0b10, 0b10)
+
+    def lock_address_range(self) -> bool:
+        """Lock address range (base and limit registers).
+        """
+        self._log.debug('')
+        self.write_word(self._role, self.REGS['ADDRESS_RANGE_REGWEN'],
+                        MB4_FALSE)
+
+    def is_locked_address_range(self) -> bool:
+        """Lock address range (base and limit registers).
+        """
+        res = self.read_word(self._role, self.REGS['ADDRESS_RANGE_REGWEN']) \
+            != MB4_TRUE
+        self._log.debug('%d', res)
+        return res
+
+    def validate_address_range(self, valid: bool):
+        """Validate address range (base and limit registers).
+
+           :param valid: whether to validate or invalidate the range
+        """
+        self._log.debug('%d', valid)
+        self.write_word(self._role, self.REGS['ADDRESS_RANGE_VALID'],
+                        int(valid))
+
+    def set_base_address(self, write: bool, address: int) -> None:
+        """Set the 32-bit base address to the mailbox host register.
+
+           The caller is responsible to first check that a value can be written
+           to this register.
+
+           :param write: whether to set the write or read register
+           :param address: the 32-bit address to write
+        """
+        reg = 'IN_BASE_ADDR' if write else 'OUT_BASE_ADDR'
+        self._log.debug('%s: 0x%08x', reg, address)
+        self.write_word(self._role, self.REGS[reg], address)
+
+    def get_base_address(self, write: int) -> int:
+        """Get the 32-bit base address of the mailbox host register.
+
+           :param write: whether to get the write or read register
+           :return: the 32-bit address to write
+        """
+        reg = 'IN_BASE_ADDR' if write else 'OUT_BASE_ADDR'
+        res = self.read_word(self._role, self.REGS[reg])
+        self._log.debug('%s: 0x%08x', reg, res)
+        return res
+
+    def set_limit_address(self, write: bool, address: int) -> None:
+        """Set the 32-bit limit address to the mailbox host register.
+
+           The caller is responsible to first check that a value can be written
+           to this register.
+
+           :param write: whether to set the write or read register
+           :param address: the 32-bit address to write
+        """
+        reg = 'IN_LIMIT_ADDR' if write else 'OUT_LIMIT_ADDR'
+        self._log.debug('%s: 0x%08x', reg, address)
+        self.write_word(self._role, self.REGS[reg], address)
+
+    def get_limit_address(self, write: int) -> int:
+        """Get the 32-bit limit address of the mailbox host register.
+
+           :param write: whether to get the write or read register
+           :return: the 32-bit address to write
+        """
+        reg = 'IN_LIMIT_ADDR' if write else 'OUT_LIMIT_ADDR'
+        res = self.read_word(self._role, self.REGS[reg])
+        self._log.debug('%s: 0x%08x', reg, res)
+        return res
+
+    def get_mem_pointer(self, write: int) -> int:
+        """Get the 32-bit memory address of the mailbox host pointer.
+
+           :param write: whether to get the write or read pointer
+           :return: the 32-bit address to write
+        """
+        reg = 'IN_WRITE_PTR' if write else 'OUT_READ_PTR'
+        res = self.read_word(self._role, self.REGS[reg])
+        self._log.debug('%s: 0x%08x', reg, res)
+        return res
+
+    def get_interrupt_info(self) -> tuple[int, int]:
+        """Return the system-side interrupt information.
+
+           :return: address and data values
+        """
+        data = self.read_buf('RS', self._role, self.REGS['INTR_MSG_ADDR'], 2)
+        vals = sunpack('<II', data)
+        self._log.debug('0x%08x 0x%08x', vals[0], vals[1])
+        return vals
+
+    def set_object_size(self, size: int) -> None:
+        """Set the size (in word count) of the response written in memory.
+
+           :param size: the size in word count
+        """
+        self._log.debug('%d', size)
+        self.write_word(self._role, self.REGS['OUT_OBJECT_SIZE'], size)
+
+
+class MbxSysProxy(DeviceProxy):
+    """DOE Mailbox System-side proxy.
+
+       Specialized DeviceProxy that helps communication with a remote DOE SYS
+       mailbox.
+
+       :param args: forwarded as is to the parent, see #DevicePRoxy
+       :param role: optional access role
+    """
+
+    DEVICE_ID = 'mbs'
+
+    REGS = {
+        'INTR_MSG_ADDR': 0x00,
+        'INTR_MSG_DATA': 0x04,
+        'CONTROL': 0x08,
+        'STATUS': 0x0c,
+        'WRITE_DATA': 0x010,
+        'READ_DATA': 0x014,
+    }
+    """Supported registers."""
+
+    def __init__(self, *args, role: Optional[int] = None):
+        super().__init__(*args)
+        self._role = 0xff  # ensure it should be defined through set_role
+        if role is not None:
+            self.set_role(role)
+
+    def set_role(self, role: int):
+        """Set the control access role to read/write remote registers."""
+        if not isinstance(role, int) or role > 0xf:
+            raise ValueError(f'Invalid role {role}')
+        self._role = role
+        self._log.debug('%d', role)
+
+    def abort(self) -> None:
+        """Abort an outstanding DOE request."""
+        self._log.debug('')
+        self.write_word(self._role, self.REGS['CONTROL'], 0b001, 0b001)
+
+    def go(self) -> None:
+        """Tell the mailbox responder that a request is reading to be processed.
+        """
+        # pylint: disable=invalid-name
+        self._log.debug('')
+        self.write_word(self._role, self.REGS['CONTROL'], 1 << 31, 1 << 31)
+
+    def enable_interrupt(self, enable: bool) -> None:
+        """Tell the DOE mailbox the requester wants to be signalled with an
+           interrupt when the response is available.
+
+           :param enable: whether to activate or deactivate this feature
+        """
+        self._log.debug('%d', enable)
+        self.write_word(self._role, self.REGS['CONTROL'],
+                        0b0010 if enable else 0, 0b0010)
+
+    def get_status(self) -> int:
+        """Retrieve the DOE mailbox status 32-bit register."""
+        res = self.read_word(self._role, self.REGS['STATUS'])
+        self._log.debug('%d', res)
+        return res
+
+    def is_busy(self) -> bool:
+        """Report whether the mailbox is busy, not accepting any request."""
+        res = bool(self.get_status() & 0b0001)
+        self._log.debug('%d', res)
+        return res
+
+    def is_interrupt(self) -> bool:
+        """Report whether the mailbox has signalled the completion of a
+           response.
+        """
+        res = bool(self.get_status() & 0b0010)
+        self._log.debug('%d', res)
+        return res
+
+    def is_on_error(self) -> bool:
+        """Report whether the mailbox is in error."""
+        res = bool(self.get_status() & 0b0100)
+        self._log.debug('%d', res)
+        return res
+
+    def is_object_ready(self) -> bool:
+        """Report whether a request object has been flagged as ready to be
+           handled.
+        """
+        res = bool(self.get_status() & (1 << 31))
+        self._log.debug('%d', res)
+        return res
+
+    def clear_interrupt(self) -> None:
+        """Clear the response completion flag."""
+        self._log.debug('')
+        self.write_word(self._role, self.REGS['STATUS'], 0b0010, 0b0010)
+
+    def write(self, value: int) -> None:
+        """Write a 32-bit word into the mailbox system input register.
+
+           The caller is responsible to first check that a value can be pushed
+           into this register.
+        """
+        self._log.debug('0x%08x', value)
+        self.write_word(self._role, self.REGS['WRITE_DATA'], value)
+
+    def read(self) -> int:
+        """Read a 32-bit word from the mailbox system output register.
+
+           The caller is responsible to first check that a value can be read
+           from this register.
+        """
+        res = self.read_word(self._role, self.REGS['READ_DATA'])
+        self._log.debug('0x%08x', res)
+        return res
+
+    def write_buffer(self, pcie: DOEHeader, buffer: bytes) -> int:
+        """Write a DOE object to the remote mailbox.
+
+           If the buffer length is not a multiple of 4 bytes, it is padded with
+           NUL bytes.
+
+           The length encoded into the pcie header is automatically updated,
+           i.e. the caller is only in charge of filling in the vendor identifier
+           and the object type.
+
+           Be aware that in this mode, the DOE status is not checked, the
+           WRITE_DATA destination register is written blindly. See #write_mbox
+        """
+        trailing = len(buffer) & 0x3
+        if trailing:
+            buffer = b''.join((buffer, bytes(4-trailing)))
+        dwlen = len(buffer)//4 + DOEHeader.DWSIZE
+        pcie.set_dwlength(dwlen)
+        buffer = b''.join((pcie.encode(), buffer))
+        self._log.debug('len %d', len(buffer))
+        return self.write_buf('WS', self._role, self.REGS['WRITE_DATA'], buffer)
+
+    def write_mbox(self, pcie: DOEHeader, buffer: bytes) -> None:
+        """Write a DOE object and tell the remote mailbox the DOE object is
+           complete and ready to be handled.
+
+           The DOE status register is checked before each write to the
+           destination register. Write stops whenever the busy or error bit is
+           set.
+
+           If the buffer length is not a multiple of 4 bytes, it is padded with
+           NUL bytes.
+
+           The length encoded into the pcie header is automatically updated,
+           i.e. the caller is only in charge of filling in the vendor identifier
+           and the object type.
+
+           If the whole buffer is sucessfully written into the DOE mailbox, the
+           GO bit is automatically flagged to signal the mailbox that the DOE
+           object can be handled immediately.
+        """
+        trailing = len(buffer) & 0x3
+        if trailing:
+            buffer = b''.join((buffer, bytes(4-trailing)))
+        dwlen = len(buffer)//4 + DOEHeader.DWSIZE
+        pcie.set_dwlength(dwlen)
+        buffer = b''.join((pcie.encode(), buffer))
+        self._log.debug('len %d', len(buffer))
+        count = self.write_buf('WX', self._role, self.REGS['WRITE_DATA'],
+                               buffer)
+        if count != len(buffer):
+            raise ProxyCommandError(0x402, f'Cannot write full buffer {count}/'
+                                    f'{len(buffer)}')
+
+    def read_mbox(self, dwcount: int) -> tuple[DOEHeader, bytes]:
+        """Read a DOE object from the remote mailbox.
+
+           Each read word is automatically acknowledged on the remote mailbox,
+           and read stops immediately in case of an error.
+
+           :param dwcount: the maximum 32-bit words to read out. The actual DOE
+                           object may be shorter.
+        """
+        buf = self.read_buf('RX', self._role, self.REGS['READ_DATA'],
+                            dwcount+DOEHeader.DWSIZE)
+        pcie = DOEHeader.decode(buf[:DOEHeader.SIZE])
+        self._log.debug('len %d', len(buf)-DOEHeader.SIZE)
+        return pcie, buf[DOEHeader.SIZE:]
+
+    def get_interrupt_info(self) -> tuple[int, int]:
+        """Return the system-side interrupt information.
+
+           :return: address and data values
+        """
+        data = self.read_buf('RS', self._role, self.REGS['INTR_MSG_ADDR'], 2)
+        vals = sunpack('<II', data)
+        self._log.debug('0x%08x 0x%08x', vals[0], vals[1])
+        return vals
+
+    def set_interrupt_addr(self, addr: int) -> None:
+        """Return the system-side interrupt information.
+
+           :param addr: set interrupt address
+        """
+        self._log.debug('0x%08x', addr)
+        self.write_word(self._role, self.REGS['INTR_MSG_ADDR'], addr)
+
+    def set_interrupt_data(self, data: int) -> None:
+        """Return the system-side interrupt information.
+
+           :param addr: set interrupt data
+        """
+        self._log.debug('0x%08x', data)
+        self.write_word(self._role, self.REGS['INTR_MSG_DATA'], data)
+
+
+class SoCProxy(DeviceProxy):
+    """SoC proxy.
+
+       Specialized DeviceProxy that helps managing an SOC PROXY device.
+
+       :param args: forwarded as is to the parent, see #DevicePRoxy
+       :param role: optional access role
+    """
+
+    DEVICE_ID = 'soc'
+
+    REGS = {
+        'INTR_STATE':  0x00,
+        'INTR_ENABLE':  0x04,
+        'INTR_TEST':  0x08,
+        'ALERT_TEST':  0x0c,
+    }
+    """Supported registers."""
+
+    def __init__(self, *args, role: Optional[int] = None):
+        super().__init__(*args)
+        self._role = 0xff  # ensure it should be defined through set_role
+        if role is not None:
+            self.set_role(role)
+
+    def set_role(self, role: int):
+        """Set the control access role to read/write remote registers."""
+        if not isinstance(role, int) or role > 0xf:
+            raise ValueError('Invalid role')
+        self._role = role
+        self._log.debug('%d', role)
+
+    @property
+    def interrupt_state(self) -> int:
+        """Report which interrupts are active.
+
+           :return: interrupt state bitfield
+        """
+        return self.read_word(self._role, self.REGS['INTR_STATE'])
+
+    def enable_interrupts(self, intrs: int) -> None:
+        """Enable interrupts.
+
+           :param intrs: the bitfield of interrupts to enable
+        """
+        self._log.debug('0x%08x', intrs)
+        self.write_word(self._role, self.REGS['INTR_ENABLE'], intrs)
+
+    @property
+    def enabled_interrupts(self) -> int:
+        """Get enabled interrupt channels.
+        """
+        return self.read_word(self._role, self.REGS['INTR_ENABLE'])
+
+    def clear_interrupts(self, intrs: int) -> None:
+        """Clear interrupts.
+
+           :param intrs: the bitfield of interrupts to clear
+        """
+        self._log.debug('0x%08x', intrs)
+        self.write_word(self._role, self.REGS['INTR_STATE'], intrs)
+
+    def test_interrupts(self, intrs: int) -> None:
+        """Test interrupts.
+
+           :param intrs: the bitfield of interrupts to test
+        """
+        self._log.debug('0x%08x', intrs)
+        self.write_word(self._role, self.REGS['INTR_TEST'], intrs)
+
+    def test_alerts(self, alerts: int) -> None:
+        """Test alerts
+
+           :param alerts: the bitfield of interrupts to test
+        """
+        self._log.debug('0x%08x', alerts)
+        self.write_word(self._role, self.REGS['ALERT_TEST'], alerts)
+
+
+class MemProxy(DeviceProxy):
+    """Memory device proxy.
+
+       Specialized DeviceProxy that helps managing random access memory.
+
+       :param args: forwarded as is to the parent, see #DevicePRoxy
+       :param role: optional access role
+    """
+
+    DEVICE_ID = 'm'
+
+    def __init__(self, *args, role: Optional[int] = None):
+        super().__init__(*args)
+        self._role = 0xff  # ensure it should be defined through set_role
+        if role is not None:
+            self.set_role(role)
+
+    def set_role(self, role: int):
+        """Set the control access role to read/write remote registers."""
+        if not isinstance(role, int) or role > 0xf:
+            raise ValueError(f'Invalid role {role}')
+        self._role = role
+
+    @property
+    def base_address(self) -> int:
+        """Return the base address of the memory device, as seen from the
+           local CPU if any, otherwise in the CTN address space.
+        """
+        return self._addr
+
+    @property
+    def size(self) -> int:
+        """Return the size in bytes of the memory device.
+        """
+        return (self._end - self._offset) * 4
+
+    def read(self, address: int, size: int, rel: bool = False) -> bytes:
+        """Read a buffer from memory.
+
+           :param address: the address of the first word to read
+           :param size: the count of word to read
+           :param rel: whether the address is relative or absolute
+        """
+        if self._role > 0xf:
+            raise ValueError(f'Invalid role {self._role}')
+        # if specified address is an absolute address, compute the relative
+        # address within the device
+        addr = (address - self._addr) if not rel else address
+        if not 0 <= addr < self.size:
+            raise ValueError(f'Invalid address 0x{addr:08x}')
+        if size * 4 > self.size:
+            raise ValueError(f'Invalid size {size}')
+        request = spack('<HHII', 0, self._make_sel(self._devid), addr, size)
+        response = self._proxy.exchange('RM', request)
+        return response
+
+    def write(self, address: int, buffer: bytes, rel: bool = False) -> None:
+        """Write a buffer into memory.
+
+           :param address: the address of the first byte to read
+           :param size: the count of bytes to read
+           :param rel: whether the address is relative or absolute
+        """
+        if self._role > 0xf:
+            raise ValueError(f'Invalid role {self._role}')
+        # if specified address is an absolute address, compute the relative
+        # address within the device
+        addr = (address - self._addr) if not rel else address
+        if not 0 <= addr < self.size:
+            raise ValueError(f'Invalid address 0x{address:08x}')
+        trailing = len(buffer) & 0x3
+        if trailing:
+            buffer = b''.join((buffer, bytes(4-trailing)))
+        size = len(buffer)
+        wsize = size // 4
+        if wsize > self.size:
+            raise ValueError('Invalid buffer size {size}')
+        request = b''.join((spack('<HHI', 0, self._make_sel(self._devid),
+                                  addr), buffer))
+        response = self._proxy.exchange('WM', request)
+        respsize = scalc('<I')
+        if len(response) != respsize:
+            raise ProxyCommandError(0x403, f'expected {respsize}, '
+                                           f'received {len(response)}')
+        value, = sunpack('<I', response)
+        if value != wsize:
+            raise ProxyCommandError(0x404, f'expected {wsize}, wrote {value}')
+
+
+class SramMemProxy(MemProxy):
+    """SRAM memory device proxy.
+
+       Specialized MemProxy that helps managing SRAM.
+
+       :param args: forwarded as is to the parent, see #DevicePRoxy
+       :param role: optional access role
+    """
+
+    DEVICE_ID = 'srm'
+
+
+class SramCtrlProxy(DeviceProxy):
+    """SRAM controller device proxy.
+
+       Specialized DeviceProxy that help managing SRAM controllers.
+
+       :param args: forwarded as is to the parent, see #DevicePRoxy
+       :param role: optional access role
+    """
+
+    DEVICE_ID = 'src'
+
+    REGS = {
+        'ALERT_TEST': 0x0,
+        'STATUS': 0x4,
+        'EXEC_REGWEN': 0x8,
+        'EXEC': 0xc,
+        'CTRL_REGWEN': 0x10,
+        'CTRL': 0x14,
+        'SCR_KEY_ROTATED': 0x1c,
+    }
+    """Supported registers."""
+
+    def __init__(self, *args, role: Optional[int] = None):
+        super().__init__(*args)
+        self._role = 0xff  # ensure it should be defined through set_role
+        if role is not None:
+            self.set_role(role)
+
+    def set_role(self, role: int):
+        """Set the control access role to read/write remote registers."""
+        if not isinstance(role, int) or role > 0xf:
+            raise ValueError('Invalid role')
+        self._role = role
+        self._log.debug('%d', role)
+
+    def is_init_done(self) -> bool:
+        """Report whether initialization is complete."""
+        return bool(self.read_word(self._role, self.REGS['STATUS']) & (1 << 5))
+
+    def is_scr_key_seed_valid(self) -> bool:
+        """Report whether scrambing key seed is valid."""
+        return bool(self.read_word(self._role, self.REGS['STATUS']) & (1 << 4))
+
+    def is_scr_key_valid(self) -> bool:
+        """Report whether scrambing key is valid."""
+        return bool(self.read_word(self._role, self.REGS['STATUS']) & (1 << 3))
+
+    def initialize(self, renew_src_key: bool) -> None:
+        """Intialize SRAM content."""
+        ctrl = 0b10
+        if renew_src_key:
+            ctrl |= 0b01
+        self.write_word(self._role, self.REGS['CTRL'], ctrl)
+
+
+class ProxyEngine:
+    """Tool to access and remotely drive devices and memories.
+    """
+
+    VERSION = (0, 15)
+    """Protocol version."""
+
+    TIMEOUT = 2.0
+    """Default allowed timeout to complete an exchange with the remote target.
+    """
+
+    POLL_TIMEOUT = 0.05
+    """Maximum time to wait on a blocking operation.
+    """
+
+    POLL_RECOVER_DELAY = 0.1
+    """Time to wait on a recovery operation.
+    """
+
+    EXIT_DELAY = 0.1
+    """Time to wait before resuming once the termination command is sent.
+    """
+
+    BAUDRATE = 115200
+    """Default baudrate for serial line communication."""
+
+    HEADER = '<2sHI'
+    """Proxy header."""
+
+    HEADER_SIZE = scalc(HEADER)
+    """Proxy header size."""
+
+    NOTIFICATIONS = {
+        'W': 'wired_irq',
+        'R': 'mr_hit',
+    }
+    """Notification dispatch map."""
+
+    LOG_CHANNELS = (
+        'tb_out_asm',
+        'tb_in_asm',
+        'tb_op',
+        'tb_op_opt',
+        'int',
+        'exec',
+        'pcall',
+        'tb_cpu',
+        'reset',
+        'unimp',
+        'guest_error',
+        'mmu',
+        'tb_nochain',
+        'page',
+        'trace',
+        'tb_op_ind',
+        'tb_fpu',
+        'plugin',
+        'strace',
+        'per_thread',
+        'tb_vpu',
+        'tb_op_plugin',
+    )
+    """Supported QEMU log channels."""
+
+    class LogOp(IntEnum):
+        """Log operations."""
+        READ = 0
+        ADD = 1
+        REMOVE = 2
+        SET = 3
+
+    LogOnce: set[str] = set()
+    # whether initial log of remote device capabilities has been done
+
+    def __init__(self):
+        self._log = getLogger('proxy.proxy')
+        self._socket: Optional[socket] = None
+        self._port: Optional[Serial] = None
+        self._resume = False
+        self._receiver: Optional[Thread] = None
+        self._notifier: Optional[Thread] = None
+        self._requ_q = deque()
+        self._resp_q = deque()
+        self._requ_event = Event()
+        self._resp_event = Event()
+        self._rx_uid = 0
+        self._tx_uid = 0
+        self._devices: dict[str, int] = {}
+        self._mroots: dict[int, MemoryRoot] = {}
+        self._request_handler: Optional[RequestHandler] = None
+        self._request_args: list[Any] = []
+        self._watchers: dict[int, tuple[MemoryWatcherHandler, Any]] = {}
+        self._proxies = self._discover_proxies()
+
+    def connect(self, host: str, port: int) -> None:
+        """Open a TCP connection to the remote host.
+
+           @param host the host name
+           @paran port the TCP port
+        """
+        if self._socket or self._port:
+            raise RuntimeError('Cannot open multiple comm port at once')
+        try:
+            self._socket = create_connection((host, port), timeout=self.TIMEOUT)
+        except OSError:
+            self._log.fatal('Cannot connect to %s:%d', host, port)
+            raise
+        self._socket.settimeout(self.POLL_TIMEOUT)
+        self._kick_off()
+
+    def open(self, url: str) -> None:
+        """Open a PySerial communication port with the remote device.
+
+           :param url: a pyserial-supported port URL
+        """
+        if self._socket or self._port:
+            raise RuntimeError('Cannot open multiple comm port at once')
+        self._port = serial_for_url(url, timeout=self.POLL_TIMEOUT,
+                                    baudrate=self.BAUDRATE)
+        self._kick_off()
+
+    def close(self) -> None:
+        """Close the connection with the remote device."""
+        self._resume = False
+        self._log.debug('Closing connection')
+        if self._socket:
+            self._socket.shutdown(SHUT_RDWR)
+            self._socket.close()
+            self._socket = None
+        if self._port:
+            self._port.close()
+            self._port = None
+
+    @property
+    def socket(self) -> Optional[socket]:
+        """Get the current socket to connect to the VM, if any."""
+        return self._socket
+
+    def quit(self, code: int) -> None:
+        """Tell the remote target to exit the application.
+        """
+        payload = spack('<i', code)
+        self.exchange('QT', payload)
+        sleep(self.EXIT_DELAY)
+        self.close()
+
+    def resume(self) -> None:
+        """Resume execution.
+        """
+        self.exchange('CX')
+
+    def discover_devices(self) -> None:
+        """Enumerate and store supported remote devices.
+        """
+        try:
+            devices = self.exchange('ED')
+        except ProxyCommandError as exc:
+            self._log.fatal('%s', exc)
+            raise
+        devfmt = '<HHII16s'
+        devlen = scalc(devfmt)
+        if len(devices) % devlen:
+            raise ValueError('Unexpected response length')
+        devcount = len(devices) // devlen
+        fname = currentframe().f_code.co_name
+        if fname not in self.LogOnce:
+            self.LogOnce.add(fname)
+            self._log.info('Found %d remote devices', devcount)
+        self._devices.clear()
+        while devices:
+            devhdr = devices[0:devlen]
+            devices = devices[devlen:]
+            doff, dnum, daddr, dcount, dname = sunpack(devfmt, devhdr)
+            try:
+                devname = dname.rstrip(b'\x00').decode().lower()
+            except UnicodeDecodeError as exc:
+                self._log.critical('Malformed device name (%s): %s',
+                                   str(exc), hexlify(dname).decode())
+                continue
+            if devname in self._devices:
+                self._log.error("Multiple devices w/ identical identifier: "
+                                "'%s'", devname)
+                continue
+            dnum &= 0xfff
+            kind = devname.split('/', 1)[0]
+            class_ = self._proxies.get(kind, DeviceProxy)
+            self._devices[devname] = \
+                class_(self, devname, dnum, daddr, dcount, doff)
+
+    def discover_memory_spaces(self) -> None:
+        """Enumerate and store memory spaces.
+        """
+        try:
+            mregions = self.exchange('ES')
+        except ProxyCommandError as exc:
+            self._log.fatal('%s', exc)
+            raise
+        mrfmt = '<xxxBII32s'
+        mrlen = scalc(mrfmt)
+        if len(mregions) % mrlen:
+            raise ValueError('Unexpected response length')
+        mrcount = len(mregions) // mrlen
+        fname = currentframe().f_code.co_name
+        if fname not in self.LogOnce:
+            self.LogOnce.add(fname)
+            self._log.info('Found %d remote memory root regions', mrcount)
+        self._mroots.clear()
+        while mregions:
+            mrhdr = mregions[0:mrlen]
+            mregions = mregions[mrlen:]
+            mspc, address, size, mname = sunpack(mrfmt, mrhdr)
+            mrname = mname.rstrip(b'\x00').decode().lower()
+            if mspc in self._mroots:
+                self._log.error("Multiple memory regions w/ identical "
+                                "identifier: '%s' @ %d", mrname, mspc)
+                continue
+            self._mroots[mspc] = MemoryRoot(mrname, address, size)
+
+    def enumerate_devices(self) -> Iterator[str]:
+        """Provide an iterator on discovered devices.
+        """
+        yield from self._devices
+
+    def enumerate_memory_spaces(self) -> Iterator[int]:
+        """Provide an iterator on discovered memory spaces.
+        """
+        yield from self._mroots
+
+    def get_device_by_name(self, name: str) -> Optional[DeviceProxy]:
+        """Retrieve a device proxy from its name."""
+        return self._devices.get(name.lower())
+
+    def get_device_by_uid(self, uid: int) -> Optional[DeviceProxy]:
+        """Retrieve a device proxy from its uid."""
+        for dev in self._devices.values():
+            if dev.uid == uid:
+                return dev
+        return None
+
+    def get_region_by_name(self, name: str, approx: bool = False) \
+            -> Optional[MemoryRoot]:
+        """Retrieve a memory root region from its name.
+
+           :param name: the name og the region (or a part of its name)
+           :param approx: whether to look for a partial name
+        """
+        candidates = []
+        name = name.lower()
+        for region in self._mroots.values():
+            lrname = region.name.lower()
+            if lrname == name:
+                return region
+            if approx and lrname.find(name) >= 0:
+                candidates.append(region)
+        if len(candidates) == 1:
+            return candidates[0]
+        return None
+
+    def get_region_by_uid(self, uid: int) -> Optional[DeviceProxy]:
+        """Retrieve a memory root region from its uid."""
+        return self._mroots.get(uid)
+
+    def intercept_mmio_access(self, root: Optional[MemoryRoot], address: int,
+                              size: int, read: bool, write: bool,
+                              handler: MemoryWatcherHandler, *args, **kwargs) \
+            -> None:
+        """Request the remote proxy to intercept memory/IO access to a specified
+           region.
+
+           :param root: the root of the memory region to intercept, maybe None
+                        if a single memory root region exist
+           :param address: the adress of the first byte to intercept
+           :param size: the size of the region to intercept
+           :param read: whether to intercept read access
+           :param write: whether to intercept write access
+           :param kwargs:
+              * 'stop': whether to stop auto-discard intercepter after the
+                        specified count of access. Use 0 to disable auto-discard
+              * 'prority': priority of the intercepter
+        """
+        if not read and not write:
+            raise ValueError('Read or/and Write should be specified')
+        priority = kwargs.pop('priority', 1)
+        stop = kwargs.pop('stop', 0)
+        if kwargs:
+            raise ValueError(f'Unknown arguements: {", ".join(kwargs)}')
+        if not isinstance(priority, int) or not priority or priority > 0x3f:
+            raise ValueError('Invalid priority')
+        if not isinstance(stop, int) or stop > 0x3f:
+            raise ValueError('Invalid stop value')
+        if root is None:
+            if len(self._mroots) != 1:
+                raise ValueError('Root region should be specified')
+            rid = 0
+        else:
+            for rid, mroot in self._mroots.items():
+                if mroot == root:
+                    break
+            else:
+                raise ValueError('Unkown memory region')
+        header = 0
+        if read:
+            header |= 0b01
+        if write:
+            header |= 0b10
+        header |= priority << 2
+        header |= stop << 10
+        header |= rid << 24
+        request = spack('<III', header, address, size)
+        response = self.exchange('MI', request)
+        if len(response) != scalc('<xxH'):
+            raise ProxyCommandError(0x403)
+        region, = sunpack('<xxH', response)
+        region &= 0x3f
+        if region in self._watchers:
+            raise ProxyCommandError(0x802)
+        self._watchers[region] = (handler, *args)
+
+    def register_request_handler(self, handler: RequestHandler, *args) -> None:
+        """Register a handler to receive requests from the remote peer.
+
+           :param handler: the handler function
+           :param args: any argument to forward to the handler
+        """
+        self._request_handler = handler
+        self._request_args = args
+
+    def change_log_mask(self, logop: 'ProxyEngine.LogOp', mask: int) -> int:
+        """Change the QEMU log mask.
+
+           :param op: the log modification operation
+           :param mask: the log mask to apply
+           :return: the previous log mask
+        """
+        if not 0 <= logop <= 3:
+            raise ValueError('Invalid log operation')
+        if not 0 <= mask < (1 << 30):
+            raise ValueError('Invalid log mask')
+        req = spack('<I', (logop << 30) | mask)
+        try:
+            resp = self.exchange('HL', req)
+        except ProxyCommandError as exc:
+            self._log.fatal('%s', exc)
+            raise
+        logfmt = '<I'
+        loglen = scalc(logfmt)
+        if len(resp) != loglen:
+            raise ValueError('Unexpected response length')
+        return sunpack(logfmt, resp)[0]
+
+    def add_log_sources(self, *sources) -> tuple[int, list[str]]:
+        """Add new log sources.
+
+           :param sources: should be one or more from LOG_CHANNELS
+           :return the previous sources
+        """
+        mask = self._convert_log_to_mask(*sources)
+        oldmask = self.change_log_mask(self.LogOp.ADD, mask)
+        return oldmask, self._convert_mask_to_log(oldmask)
+
+    def remove_log_sources(self, *sources) -> tuple[int, list[str]]:
+        """Remove new log sources.
+
+           :param sources: should be one or more from LOG_CHANNELS
+           :return the previous sources
+        """
+        mask = self._convert_log_to_mask(*sources)
+        oldmask = self.change_log_mask(self.LogOp.REMOVE, mask)
+        return oldmask, self._convert_mask_to_log(oldmask)
+
+    def set_log_sources(self, *sources) -> tuple[int, list[str]]:
+        """Set log sources.
+
+           :param sources: should be one or more from LOG_CHANNELS
+           :return the previous sources
+        """
+        mask = self._convert_log_to_mask(*sources)
+        oldmask = self.change_log_mask(self.LogOp.SET, mask)
+        return oldmask, self._convert_mask_to_log(oldmask)
+
+    def exchange(self, command: str, payload: Optional[bytes] = None) -> bytes:
+        """Execute a communication trip with the remote target.
+
+           @param command the command to execute, as a single char
+           @param payload optional payload to the command
+           @return the target's response
+        """
+        if get_ident() in (self._receiver.ident, self._notifier.ident):
+            raise RuntimeError('Cannot exchange using internal threads')
+        try:
+            self._resp_event.clear()
+            self._send(command, payload or b'')
+            timeout = self.TIMEOUT + now()
+            while not self._resp_q:
+                if not self._resume:
+                    raise RuntimeError('Aborted')
+                if now() > timeout:
+                    self._log.error('Timeout on command completion')
+                    self._resume = False
+                    raise TimeoutError('No reply from peer')
+                if self._resp_event.wait(self.POLL_TIMEOUT):
+                    break
+            rcmd, payload = self._resp_q.popleft()
+            if rcmd != command.lower():
+                if rcmd != 'xx':
+                    raise ValueError(f"Unexpected command response '{rcmd}'")
+                errfmt = '<I'
+                errsize = scalc(errfmt)
+                if len(payload) < errsize:
+                    raise ProxyCommandError(1,
+                                            'Rejected command w/ unknown error')
+                errcode, = sunpack(errfmt, payload[:errsize])
+                errdesc = payload[errsize:].rstrip(b'\x00').decode()
+                raise ProxyCommandError(errcode, errdesc)
+            return payload
+        except Exception:
+            self._resume = False
+            raise
+
+    def _send(self, command: str, data: bytes):
+        """Send a command to the remote target.
+
+           @param command the command to execute, as a dual char string
+           @param data the command payload
+        """
+        if len(command) != 2 or not isinstance(command, str):
+            raise ValueError('Invalid command')
+        self._tx_uid += 1
+        uid = (0 << 31) | (self._tx_uid & ~(1 << 31))
+        self._log.debug('TX cmd:%s, len:%d, uid:%d', command, len(data), uid)
+        request = spack(self.HEADER, bytes(reversed(command.encode())),
+                        len(data), uid)
+        request = b''.join((request, data))
+        try:
+            if self._port:
+                self._port.write(request)
+            elif self._socket:
+                self._socket.send(request)
+        except OSError:
+            self._log.error("Cannot send command '%s'", command)
+            self._resume = False
+
+    def _receive(self):
+        """Worker thread that handle data reception.
+        """
+        buffer = bytearray()
+        cmd = ''
+        length = 0
+        uid = 0
+        resp = False
+        while self._resume:
+            try:
+                if self._port:
+                    data = self._port.read(128)
+                    if data:
+                        buffer.extend(data)
+                elif self._socket:
+                    try:
+                        data = self._socket.recv(128)
+                        buffer.extend(data)
+                    except TimeoutError:
+                        pass
+                else:
+                    raise RuntimeError('No communication channel')
+                if not buffer:
+                    continue
+                if not length:
+                    if len(buffer) < self.HEADER_SIZE:
+                        continue
+                    bcmd, length, uid = sunpack(self.HEADER,
+                                                buffer[:self.HEADER_SIZE])
+                    resp = not bool(uid >> 31)
+                    uid = uid & ~(1 << 31)
+                    cmd = bytes(reversed(bcmd)).decode()
+                    self._log.debug('RX cmd:%s, len:%d, uid:%d, resp:%d',
+                                    cmd, length, uid, resp)
+                    buffer = buffer[self.HEADER_SIZE:]
+                if len(buffer) < length:
+                    continue
+                packet = bytes(buffer[:length])
+                self._log.debug('RX payload:%s%s', self.to_str(packet)[:80],
+                                '...' if len(packet) > 80 else '')
+                buffer = buffer[length:]
+                if resp:
+                    if self._tx_uid != uid:
+                        raise ValueError('Unexpected TX tracking')
+                    queue = self._resp_q
+                else:
+                    if self._rx_uid != uid:
+                        raise ValueError('Unexpected RX tracking')
+                    self._rx_uid += 1
+                    queue = self._requ_q
+                queue.append((cmd, packet))
+                cmd = ''
+                length = 0
+                uid = 0
+                resp = False
+            # pylint: disable=broad-except
+            except Exception as exc:
+                # connection shutdown may have been requested
+                if self._resume:
+                    self._log.fatal('Exception: %s', exc)
+                    self._resume = False
+                break
+
+    def _notify(self) -> None:
+        """Worker thread that handles notifications and remote requests.
+        """
+        while self._resume:
+            try:
+                if not self._requ_q:
+                    if not self._requ_event.wait(self.POLL_TIMEOUT):
+                        continue
+                    self._requ_event.clear()
+                rcmd, payload = self._requ_q.popleft()
+                notify = rcmd.startswith('^')
+                if notify:
+                    try:
+                        handler = self.NOTIFICATIONS[rcmd[1:]]
+                    except KeyError:
+                        self._log.error('Unknown notification type: %s',
+                                        rcmd[1:])
+                        continue
+                    dispatcher = getattr(self, f'_dispatch_{handler}', None)
+                    if not dispatcher:
+                        self._log.error('Unsupported notification: %s', handler)
+                        continue
+                    # pylint: disable=not-callable
+                    dispatcher(payload)
+                else:
+                    if not self._request_handler:
+                        self._log.warning('Missed request %s', rcmd)
+                        continue
+                    self._request_handler(rcmd, payload, *self._request_args)
+
+            # pylint: disable=broad-except
+            except Exception as exc:
+                self._log.fatal('Exception: %s', exc)
+                break
+
+    def _dispatch_wired_irq(self, payload: bytes) -> None:
+        wifmt = '<xxHHBxI'
+        wisize = scalc(wifmt)
+        if len(payload) != wisize:
+            self._log.error('Unexpected W notification length')
+            return
+        devid, channel, group, value = sunpack(wifmt, payload[:wisize])
+        devid &= 0xfff
+        device = self.get_device_by_uid(devid)
+        try:
+            device.notify_interrupt(group, channel, value)
+        except Exception as exc:
+            self._log.critical('Exception in notify_interrupt: %s', exc)
+            raise
+
+    def _dispatch_mr_hit(self, payload: bytes) -> None:
+        rifmt = '<BxHII'
+        risize = scalc(rifmt)
+        if len(payload) != risize:
+            self._log.error('Unexpected R notification length')
+            return
+        info, reg, addr, val = sunpack(rifmt, payload[:risize])
+        write = bool(info & 0b10)
+        width = info >> 4
+        wid = reg & 0x3f
+        role = reg >> 12
+        mhevent = MemoryHitEvent(addr, val, write, width, role)
+        try:
+            handler, args = self._watchers[wid]
+        except KeyError:
+            self._log.error('Memory Hit on unknown watcher: %d', wid)
+            return
+        try:
+            handler(mhevent, *args)
+        except Exception as exc:
+            self._log.critical('Exception in Memory Hit hit handler: %s', exc)
+            raise
+
+    def _kick_off(self) -> None:
+        """Start engine.
+        """
+        self._receiver = Thread(target=self._receive, name='receiver',
+                                daemon=True)
+        self._notifier = Thread(target=self._notify, name='notifier',
+                                daemon=True)
+        self._resume = True
+        self._receiver.start()
+        self._notifier.start()
+        self._handshake()
+
+    def _handshake(self):
+        """Execute a handshake with the remote target, in order to check the
+           communication link.
+        """
+        try:
+            payload = self.exchange('HS')
+        except ProxyCommandError as exc:
+            self._log.fatal('%s', exc)
+            raise
+        hshdrfmt = '<BBH'
+        hshdrlen = scalc(hshdrfmt)
+        if len(payload) < hshdrlen:
+            raise ValueError('Unexpected response length')
+        vmin, vmaj, _ = sunpack(hshdrfmt, payload[:hshdrlen])
+        fname = currentframe().f_code.co_name
+        if fname not in self.LogOnce:
+            self.LogOnce.add(fname)
+            self._log.info('Local version %d.%d, remote version %d.%d',
+                           self.VERSION[0], self.VERSION[1], vmaj, vmin)
+        if vmaj != self.VERSION[0]:
+            raise ValueError('Unsuppported version: {vmaj}.{vmin}')
+        if vmin < self.VERSION[1]:
+            raise ValueError('Unsuppported version: {vmaj}.{vmin}')
+
+    @classmethod
+    def _discover_proxies(cls) -> dict[str, DeviceProxy]:
+        """Create a map of device proxies.
+        """
+        proxymap = {}
+        for cname in dir(modules[__name__]):
+            if not cname.endswith('Proxy'):
+                continue
+            class_ = getattr(modules[__name__], cname)
+            if isinstance(class_, DeviceProxy):
+                continue
+            devid = getattr(class_, 'DEVICE_ID', None)
+            if not devid or not isinstance(devid, str):
+                continue
+            proxymap[devid] = class_
+        return proxymap
+
+    @classmethod
+    def _convert_log_to_mask(cls, *srcs) -> int:
+        channels = {l: i for i, l in enumerate(cls.LOG_CHANNELS)}
+        try:
+            mask = sum(1 << channels[s.lower()] for s in srcs)
+        except KeyError as exc:
+            raise ValueError("Unknown log channel {exc}") from exc
+        return mask
+
+    @classmethod
+    def _convert_mask_to_log(cls, logmask: int) -> list[str]:
+        srcs = []
+        pos = 0
+        while logmask:
+            mask = 1 << pos
+            if logmask & mask:
+                srcs.append(cls.LOG_CHANNELS[pos])
+                logmask &= ~mask
+            pos += 1
+        return srcs
+
+    @classmethod
+    def to_str(cls, data: Union[bytes, bytearray]) -> str:
+        """Convert a byte sequence into an hexadecimal string.
+
+           @param data the bytes to convert
+           @return the bytes encoded as a hexadecimal string
+        """
+        return hexlify(data).decode()
+
+    @classmethod
+    def to_bytes(cls, data: str) -> bytes:
+        """Convert an hexadecimal string into a byte sequence
+
+           @param data the hexadecimal string to convert
+           @return the decoded bytes
+        """
+        return unhexlify(data)
+
+
+def _main():
+    # pylint: disable=unknown-option-value
+    # pylint: disable=possibly-used-before-assignment
+    debug = False
+    try:
+        desc = modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc} simple test.')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        proxy = ProxyEngine()
+        proxy.connect('localhost', 8003)
+        proxy.discover_devices()
+        proxy.discover_memory_spaces()
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'\nError: {exc}', file=stderr)
+        if debug:
+            print(format_exc(chain=False), file=stderr)
+        sysexit(1)
+    except KeyboardInterrupt:
+        sysexit(2)
+
+
+if __name__ == '__main__':
+    # pylint: disable=ungrouped-imports
+    from argparse import ArgumentParser
+    from sys import exit as sysexit, stderr
+    from traceback import format_exc
+    _main()
diff --git a/python/qemu/ot/dm/__init__.py b/python/qemu/ot/dm/__init__.py
new file mode 100644
index 0000000000000..04979ed7b3437
--- /dev/null
+++ b/python/qemu/ot/dm/__init__.py
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""RISC-V Debug Module tools.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from .dm import DebugModule  # noqa: F401
diff --git a/python/qemu/ot/dm/dm.py b/python/qemu/ot/dm/dm.py
new file mode 100644
index 0000000000000..b99723e7e225f
--- /dev/null
+++ b/python/qemu/ot/dm/dm.py
@@ -0,0 +1,585 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""RISC-V Debug Module tools.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from enum import IntEnum
+from io import SEEK_END
+from logging import getLogger
+from time import sleep, time as now
+from typing import Any, BinaryIO, Optional, Union
+
+from .regs import CSRS, GPRS
+from ..bitfield import BitField
+from ..dtm import DebugTransportModule
+
+
+class DebugModule:
+    """RISC-V Debug Module.
+
+       Only support a single hart for now
+    """
+
+    # pylint: disable=attribute-defined-outside-init
+
+    DM_VERSION = (0, 13, 2)
+    """Supported version."""
+
+    REGISTERS = {
+        'data0': 0x04,
+        'data1': 0x05,
+        'data2': 0x06,
+        'data3': 0x07,
+        'data4': 0x08,
+        'data5': 0x09,
+        'data6': 0x0a,
+        'data7': 0x0b,
+        'data8': 0x0c,
+        'data9': 0x0d,
+        'data10': 0x0e,
+        'data11': 0x0f,
+        'dmcontrol': 0x10,
+        'dmstatus': 0x11,
+        'hartinfo': 0x12,
+        'abstractcs': 0x16,
+        'command': 0x17,
+        'abstractauto': 0x18,
+        'nextdm': 0x1d,
+        'progbuf0': 0x20,
+        'progbuf1': 0x21,
+        'progbuf2': 0x22,
+        'progbuf3': 0x23,
+        'progbuf4': 0x24,
+        'progbuf5': 0x25,
+        'progbuf6': 0x26,
+        'progbuf7': 0x27,
+        'progbuf8': 0x28,
+        'progbuf9': 0x29,
+        'progbuf10': 0x2a,
+        'progbuf11': 0x2b,
+        'progbuf12': 0x2c,
+        'progbuf13': 0x2d,
+        'progbuf14': 0x2e,
+        'progbuf15': 0x2f,
+        'sbcs': 0x38,
+        'sbaddress0': 0x39,
+        'sbaddress1': 0x3a,
+        'sbdata0': 0x3c,
+        'sbdata1': 0x3d,
+        'haltsum0': 0x40,
+    }
+    """Supported registers"""
+
+    CMDERR = IntEnum('cmderr',
+                     ['none', 'busy', 'notsup', 'exc', 'halt', 'bus', 'rsv',
+                      'other'], start=0)
+    """Command error."""
+
+    VERSION = IntEnum('version', ['nodebug', 'v0.11', 'v0.13', 'v1.0'], start=0)
+    """DMSTATUS version."""
+
+    SBERROR = IntEnum('sberror', ['none', 'timeout', 'badaddr', 'badalign',
+                                  'badsize', 'rsv5', 'rsv6', 'other'], start=0)
+    """SBCS sberror."""
+
+    SBVERSION = IntEnum('sbversion', ['legacy', 'v1.0'], start=0)
+    """SBCS sbversion."""
+
+    BITFIELDS = {
+        'DMCONTROL': BitField({
+            'dmactive': (0, 1),
+            'ndmreset': (1, 1),
+            'clrresethaltreq': (2, 1),
+            'setresethaltreq': (3, 1),
+            'hartselhi': (6, 10),
+            'hartsello': (16, 10),
+            'hasel': (26, 1),
+            'ackhavereset': (28, 1),
+            'hartreset': (29, 1),
+            'resumereq': (30, 1),
+            'haltreq': (31, 1)}),
+        'DMSTATUS': BitField({
+            'version': (0, 4, VERSION),
+            'confstrptrvalid': (4, 1),
+            'hasresethaltreq': (5, 1),
+            'authbusy': (6, 1),
+            'authenticated': (7, 1),
+            'anyhalted': (8, 1),
+            'allhalted': (9, 1),
+            'anyrunning': (10, 1),
+            'allrunning': (11, 1),
+            'anyunavail': (12, 1),
+            'allunavail': (13, 1),
+            'anynonexistent': (14, 1),
+            'allnonexistent': (15, 1),
+            'anyresumeack': (16, 1),
+            'allresumeack': (17, 1),
+            'anyhavereset': (18, 1),
+            'allhavereset': (19, 1),
+            'impebreak': (22, 1)}),
+        'HARTINFO': BitField({
+            'dataaddr': (0, 12),
+            'datasize': (12, 4),
+            'dataaccess': (16, 1),
+            'nscratch': (20, 4)}),
+        'ABSTRACTCS': BitField({
+            'datacount': (0, 4),
+            'cmderr': (8, 3, CMDERR),
+            'busy': (12, 1),
+            'progbufsize': (24, 5)}),
+        'COMMAND': BitField({
+            'control': (0, 24),
+            'cmdtype': (24, 8, IntEnum('cmdtype', ['reg', 'quick', 'mem'],
+                                       start=0), True),
+            'write': (16, 1),
+            }, reg={
+            'regno': (0, 16),
+            'transfer': (17, 1),
+            'postexec': (18, 1),
+            'aarpostincrement': (19, 1),
+            'aarsize': (20, 3, IntEnum('aarsize',
+                                       ['b8', 'b16', 'b32', 'b64', 'b128'],
+                                       start=0)),
+            }, mem={
+            'aampostincrement': (19, 1),
+            'aamsize': (20, 3),
+            'aamvirtual': (23, 1)}),
+        'ABSTRACTAUTO': BitField({
+            'autoexecdata': (0, 12),
+            'autoexecprogbuf': (16, 16)}),
+        'SBCS': BitField({
+            'sbaccess8': (0, 1),
+            'sbaccess16': (1, 1),
+            'sbaccess32': (2, 1),
+            'sbaccess64': (3, 1),
+            'sbaccess128': (4, 1),
+            'sbasize': (5, 7),
+            'sberror': (12, 3, SBERROR),
+            'sbreadondata': (15, 1),
+            'sbautoincrement': (16, 1),
+            'sbaccess': (17, 3),
+            'sbreadonaddr': (20, 1),
+            'sbbusy': (21, 1),
+            'sbbusyerror': (22, 1),
+            'sbversion': (29, 3, SBVERSION)
+        })
+    }
+
+    def __init__(self, dtm: DebugTransportModule, address: int):
+        self._log = getLogger('dtm.rvdm')
+        self._dtm = dtm
+        self._dmi = dtm['dmi']
+        self._address = address
+        self._hart: int = 0  # currently selected hart
+        self._cache: dict[str, int] = {}
+
+    def restart_system(self) -> None:
+        """Restart the remote machine."""
+        self._dtm.engine.controller.system_reset()
+
+    @classmethod
+    def decode(cls, name: str, value: int) -> dict[str, Any]:
+        """Decode a bitfield register."""
+        bitfield = cls.BITFIELDS.get(f'{name.upper()}')
+        if not bitfield:
+            raise ValueError('Cannot decode {name} register')
+        return bitfield.decode(value)
+
+    def initialize(self) -> None:
+        """Initialize the debug module."""
+        self._log.debug('Initialize')
+        btf = self.BITFIELDS['DMCONTROL']
+        self.dmcontrol = 0
+        enable = btf.encode(dmactive=True)
+        self.dmcontrol = enable
+        allharts = btf.encode(dmactive=True, hartsello=-1, hartselhi=-1,
+                              hasel=True)
+        self.dmcontrol = allharts
+        self._hart = 0
+        select = btf.encode(dmactive=True, hasel=False, hartsello=self._hart)
+        self.dmcontrol = select
+        dmcontrol = btf.decode(self.dmcontrol)
+        assert dmcontrol['dmactive'], "Debug Module not active"
+        btf = self.BITFIELDS['DMSTATUS']
+        version = btf.decode(self.dmstatus)['version']
+        if version == self.VERSION['v0.11']:
+            raise RuntimeError(f'Detected incompatible DM version {version!r}')
+        if version != self.VERSION['v0.13']:
+            self._log.warning('Detected incompatible DM version %r', version)
+
+    @property
+    def status(self) -> dict[str, int]:
+        """Report debug module status."""
+        btf = self.BITFIELDS['DMSTATUS']
+        # TODO would need to check if another hart needs to be selected first
+        return btf.decode(self.dmstatus)
+
+    @property
+    def hart_info(self) -> dict[str, int]:
+        """Report current hart information."""
+        btf = self.BITFIELDS['HARTINFO']
+        # TODO would need to check if another hart needs to be selected first
+        return btf.decode(self.hartinfo)
+
+    @property
+    def system_bus_info(self) -> dict[str, int]:
+        """Report system bus capabilities."""
+        btf = self.BITFIELDS['SBCS']
+        return btf.decode(self.sbcs)
+
+    @property
+    def is_available(self) -> bool:
+        """Report whether the currently selected hart is available."""
+        btf = self.BITFIELDS['DMSTATUS']
+        val = self.dmstatus
+        status = btf.decode(val)
+        return not status['anyunavail']
+
+    @property
+    def is_halted(self) -> bool:
+        """Report whether the currently selected hart is halted."""
+        btf = self.BITFIELDS['DMSTATUS']
+        val = self.dmstatus
+        status = btf.decode(val)
+        return status['allhalted']
+
+    def halt(self, hart: int = 0) -> None:
+        """Halt execution the selected hart."""
+        btf = self.BITFIELDS['DMCONTROL']
+        halt = btf.encode(dmactive=True, haltreq=True,
+                          hasel=False, hartsello=hart)
+        self.dmcontrol = halt
+        self._hart = hart
+        timeout = now() + 1.0
+        btf = self.BITFIELDS['DMSTATUS']
+        while now() < timeout:
+            val = self.dmstatus
+            status = btf.decode(val)
+            if status['allhalted']:
+                self._log.info('Hart %d halted', hart)
+                break
+            sleep(0.001)
+        else:
+            status = ', '.join((f'{k}: {v}' for k, v in status.items()))
+            self._log.error('Status: %s', status)
+            raise TimeoutError(f'Cannot halt hart {self._hart}')
+
+    def resume(self, hart: int = 0) -> None:
+        """Resume execution of the selected hart."""
+        btf = self.BITFIELDS['DMCONTROL']
+        resume = btf.encode(dmactive=True, resumereq=True,
+                            hasel=False, hartsello=hart)
+        self.dmcontrol = resume
+        self._hart = hart
+        timeout = now() + 1.0
+        btf = self.BITFIELDS['DMSTATUS']
+        while now() < timeout:
+            val = self.dmstatus
+            status = btf.decode(val)
+            if status['anyresumeack']:
+                self._log.info('Hart %d resumed', hart)
+                break
+            sleep(0.001)
+        else:
+            self._log.error('Status %s', status)
+            raise TimeoutError(f'Cannot resume hart {self._hart}')
+
+    def read_csr(self, reg: Union[str, int]) -> int:
+        """Read the value of a CSR."""
+        ireg = self._get_register_index(reg)
+        btf = self.BITFIELDS['COMMAND']
+        command = btf.encode(cmdtype='reg', regno=ireg, aarsize='b32',
+                             write=False, transfer=True)
+        self.command = command
+        try:
+            self._wait_abtract_command()
+        except (RuntimeError, TimeoutError, ValueError) as exc:
+            raise exc.__class__(f'{exc} while reading register {reg}') from exc
+        value = self.data0
+        self._log.info('read %s = %08x', reg, value)
+        return value
+
+    def write_csr(self, reg: Union[str, int], value: int) -> None:
+        """Write a value to a CSR."""
+        ireg = self._get_register_index(reg)
+        btf = self.BITFIELDS['COMMAND']
+        self.data0 = value
+        command = btf.encode(cmdtype='reg', regno=ireg, aarsize='b32',
+                             write=True, transfer=True)
+        self.command = command
+        try:
+            self._wait_abtract_command()
+        except (RuntimeError, TimeoutError, ValueError) as exc:
+            raise exc.__class__(f'{exc} while writing register {reg}') from exc
+        self._log.info('write %s = %08x', reg, value)
+        return value
+
+    def memory_copy(self, mfp: BinaryIO, mop: str, addr: int,
+                    size: Optional[int], no_check: bool = False) -> None:
+        """Handle memory operations.
+
+           Only support 32-bit transfers (address and size should be aligned)
+           for now.
+
+           :param mfp: I/O stream to read data from or write data to, depending
+                       on the selected operation
+           :param mop: the operation to perform (read, write)
+           :param addr: start address
+           :param size: count of bytes to read or write
+           :param no_check: assume remote peer always accepts incoming data:
+                            SBCS status is not checked during transfer if this
+                            option is set.
+        """
+        read = mop == 'read'
+        write = mop == 'write'
+        if not (read or write):
+            raise ValueError(f'Unsupported memcopy operation {mop}')
+        if addr & 0x3 != 0:
+            raise ValueError('Invalid address')
+        if (size and size & 0x3 != 0) or (read and not size):
+            raise ValueError('Invalid size')
+        start = now()
+        btf = self.BITFIELDS['SBCS']
+        val = self._wait_sb_idle(check=True)
+        val = btf.encode(val,
+                         sbreadonaddr=read,
+                         sbreadondata=read,
+                         sbautoincrement=True,
+                         sbaccess=2)  # 32-bit access
+        self.sbcs = val
+        # trigger first read (sbreadonaddr) in read mode
+        self.sbaddress0 = addr
+        if read:
+            to_go = size
+            # pylint: disable=access-member-before-definition
+            while to_go > 0:
+                self._log.debug('reading mem from 0x%08x', addr)
+                if not no_check:
+                    self._wait_sb_idle()
+                # trigger next read (sbreadondata), inc addr (sbautoincrement)
+                data = self.sbdata0
+                mfp.write(data.to_bytes(4, 'little'))
+                to_go -= 4
+                addr += 4
+        elif write:
+            if not size:
+                # mfp needs to be seekable
+                pos = mfp.tell()
+                mfp.seek(0, SEEK_END)
+                end = mfp.tell()
+                size = (end - pos) & ~0x3
+                mfp.seek(pos)
+            to_go = size
+            while to_go > 0:
+                buf = mfp.read(4)
+                self._log.debug('writing mem to 0x%08x %d', addr, len(buf))
+                assert len(buf) == 4
+                data = int.from_bytes(buf, 'little')
+                # inc addr (sbautoincrement)
+                self.sbdata0 = data
+                if not no_check:
+                    self._wait_sb_idle()
+                to_go -= 4
+                addr += 4
+        if no_check:
+            self._wait_sb_idle(check=True)
+        lap = now() - start
+        rate = size / (lap * 1024)
+        if size > 1024:
+            self._log.info('copied %d KB @ %.1f KB/s', size//1024, rate)
+        else:
+            self._log.info('copied %d bytes @ %.1f KB/s', size, rate)
+
+    def read32(self, addr: int) -> int:
+        """Read a single word from memory."""
+        if addr & 0x3 != 0:
+            raise ValueError('Invalid address')
+        btf = self.BITFIELDS['SBCS']
+        val = self._wait_sb_idle(check=True)
+        val = btf.encode(val,
+                         sbreadonaddr=True,
+                         sbreadondata=False,
+                         sbautoincrement=False,
+                         sbaccess=2)  # 32-bit access
+        self.sbcs = val
+        # trigger first read (sbreadonaddr) in read mode
+        self._log.debug('reading mem from 0x%08x', addr)
+        self.sbaddress0 = addr
+        self._wait_sb_idle()
+        value = self.sbdata0
+        return value
+
+    def write32(self, addr: int, value: int) -> None:
+        """Write a single word to memory."""
+        if addr & 0x3 != 0:
+            raise ValueError('Invalid address')
+        btf = self.BITFIELDS['SBCS']
+        val = self._wait_sb_idle(check=True)
+        val = btf.encode(val,
+                         sbreadonaddr=False,
+                         sbreadondata=False,
+                         sbautoincrement=False,
+                         sbaccess=2)  # 32-bit access
+        self.sbcs = val
+        self._log.debug('writing mem to 0x%08x', addr)
+        self.sbaddress0 = addr
+        self.sbdata0 = value
+        self._wait_sb_idle()
+
+    def read64(self, addr: int) -> int:
+        """Read two words from memory."""
+        if addr & 0x3 != 0:
+            raise ValueError('Invalid address')
+        btf = self.BITFIELDS['SBCS']
+        val = self._wait_sb_idle(check=True)
+        val = btf.encode(val,
+                         sbreadonaddr=True,
+                         sbreadondata=False,
+                         sbautoincrement=False,
+                         sbaccess=2)  # 32-bit access
+        self.sbcs = val
+        self._log.debug('reading mem from 0x%08x', addr)
+        self.sbaddress0 = addr
+        self._wait_sb_idle()
+        value = self.sbdata0
+        self.sbaddress0 = addr + 4
+        self._wait_sb_idle()
+        value |= self.sbdata0 << 32
+        return value
+
+    def write64(self, addr: int, value: int) -> None:
+        """Write two words to memory."""
+        if addr & 0x3 != 0:
+            raise ValueError('Invalid address')
+        btf = self.BITFIELDS['SBCS']
+        val = self._wait_sb_idle(check=True)
+        val = btf.encode(val,
+                         sbreadonaddr=False,
+                         sbreadondata=False,
+                         sbautoincrement=True,
+                         sbaccess=2)  # 32-bit access
+        self.sbcs = val
+        self._log.debug('writing mem to 0x%08x', addr)
+        self.sbaddress0 = addr
+        self.sbdata0 = value & 0xffff_ffff
+        self._wait_sb_idle()
+        value >>= 32
+        self.sbdata0 = value & 0xffff_ffff
+        self._wait_sb_idle()
+
+    def set_pc(self, addr: int) -> None:
+        """Set the next Program Counter address."""
+        if not self.is_halted:
+            raise RuntimeError('Cannot update PC while running')
+        self.write_csr('dpc', addr)
+
+    def __getattr__(self, name) -> int:
+        name = name.lower()
+        regaddr = self.REGISTERS.get(name, None)
+        if regaddr is None:
+            raise AttributeError('No such attribute {name}')
+        return self._read_reg(regaddr)
+
+    def __setattr__(self, name, value):
+        name = name.lower()
+        regaddr = self.REGISTERS.get(name, None)
+        if regaddr is not None:
+            self._write_reg(regaddr, value)
+        else:
+            super().__setattr__(name, value)
+
+    def _write_reg(self, reg: int, value: int) -> None:
+        if not isinstance(value, int):
+            raise TypeError(f'Invalid type {type(value)}')
+        if value >= (1 << 32):
+            raise ValueError('Invalid value')
+        self._log.debug('write %02x: 0x%08x', reg, value)
+        self._dmi.write(self._address + reg, value)
+        self._cache[reg] = value
+
+    def _read_reg(self, reg: str) -> int:
+        self._log.debug('read %02x', reg)
+        value = self._dmi.read(self._address + reg)
+        self._cache[reg] = value
+        self._log.debug('read 0x%08x', value)
+        return value
+
+    def _get_register_index(self, reg: Union[str, int]) -> int:
+        if isinstance(reg, str):
+            # Not supported: FPR, Vector, etc.
+            ireg = CSRS.get(reg.lower())
+            if ireg is None:
+                ireg = GPRS.get(reg.lower())
+                if ireg is None:
+                    raise ValueError(f"No such CSR '{reg}'")
+                ireg += 0x1000
+            return ireg
+        return reg
+
+    def _wait_abtract_command(self) -> None:
+        """Wait for the completion of an abstract command."""
+        timeout = now() + 1.0
+        btf = self.BITFIELDS['ABSTRACTCS']
+        exc = None
+        error = 0
+        while now() < timeout:
+            # pylint: disable=access-member-before-definition
+            val = self.abstractcs
+            cmd = btf.decode(val)
+            error = cmd['cmderr']
+            if error != self.CMDERR.none:
+                exc = RuntimeError(f'DM in error: {error!r}')
+                break
+            if not cmd['busy']:
+                break
+            sleep(0.001)
+        else:
+            # need a recovery feature, see hung command handling in spec.
+            raise TimeoutError()
+        if exc:
+            clear_err = btf.encode(cmderr=error)
+            self.abstractcs = clear_err
+            raise exc
+
+    def _wait_sb_idle(self, check: bool = False) -> int:
+        """Wait for the completion of a system bus access.
+
+           :param check: whether to check the access is supported
+        """
+        btf = self.BITFIELDS['SBCS']
+        timeout = now() + 1.0
+        while now() < timeout:
+            # pylint: disable=access-member-before-definition
+            val = self.sbcs
+            sbcs = btf.decode(val)
+            if check:
+                # check supported version
+                assert sbcs['sbversion'] == self.SBVERSION['v1.0']
+                # check System Bus access is supported
+                assert sbcs['sbasize'] != 0
+                # for now, only use 32-bit access
+                assert sbcs['sbaccess32']
+                check = False
+            error = sbcs['sberror']
+            if sbcs['sberror'] != self.SBERROR['none']:
+                # clear the error
+                val = btf.encode(val, sberror=True)
+                self.sbcs = val
+                # then raise the error
+                self._log.error('sbcs 0x%08x %s', val, btf.decode(val))
+                raise RuntimeError(f'SBCS in error {error!r}')
+            if sbcs['sbbusyerror']:
+                # clear the error
+                val = btf.encode(val, sbbusyerror=True)
+                self.sbcs = val
+                # then raise the error
+                self._log.error('sbcs 0x%08x %s', val, btf.decode(val))
+                raise RuntimeError('SBCS in busy error')
+            if not sbcs['sbbusy']:
+                return val
+            sleep(0.001)
+        # need a recovery feature, see hung command handling in spec.
+        raise TimeoutError('System Bus stalled')
diff --git a/python/qemu/ot/dm/otp.py b/python/qemu/ot/dm/otp.py
new file mode 100644
index 0000000000000..e2fe3a0cefd45
--- /dev/null
+++ b/python/qemu/ot/dm/otp.py
@@ -0,0 +1,354 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""One-Time Programmable controller.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import unhexlify
+from enum import IntEnum
+from logging import getLogger
+from time import sleep, time as now
+from typing import Optional, Union
+
+from .dm import DebugModule
+from ..bitfield import BitField
+from ..otp import OtpMap, OtpPartition
+from ..util.misc import HexInt
+
+# pylint: disable=missing-function-docstring
+
+
+class OTPException(Exception):
+    """Base exception."""
+
+
+class OTPBusyError(OTPException):
+    """OTP controller is busy."""
+
+
+class OTPError(OTPException):
+    """OTP controller error."""
+
+    def __init__(self, err_code: 'OTPController.ERR_CODE'):
+        super().__init__(f'{err_code!r}')
+        self.err_code = err_code
+
+
+class OTPController:
+    """
+       Only support Darjeeling variant of the controller
+       Only support the Direct Access Interface for now
+    """
+
+    TOKENS = [
+        'invalid',
+        'zero',
+        'raw_unlock',
+        'test_unlock',
+        'test_exit',
+        'rma',
+    ]
+
+    REGISTERS = {
+        'status': 0x10,
+        'err_code': 0x14,
+        'regwen': 0x74,
+        'cmd': 0x78,
+        'address': 0x7c,
+        'wdata_0': 0x80,
+        'wdata_1': 0x84,
+        'rdata_0': 0x88,
+        'rdata_1': 0x8c,
+    }
+    """Darjeeling registers"""
+
+    ERR_CODE = IntEnum('err_code',
+                       ['none', 'macro', 'macro_ecc_corr', 'macro_ecc_uncorr',
+                        'macro_write_blank', 'access', 'check_fail',
+                        'fsm_state'], start=0)
+
+    ERROR_COUNT = 24
+
+    BITFIELDS = {
+        'STATUS': BitField({
+            'vendor_test_error': (0, 1),
+            'creator_sw_cfg_error': (1, 1),
+            'owner_sw_cfg_error': (2, 1),
+            'ownership_slot_state_error': (3, 1),
+            'rot_creator_auth_error': (4, 1),
+            'rot_owner_auth_slot0_error': (5, 1),
+            'rot_owner_auth_slot1_error': (6, 1),
+            'plat_integ_auth_slot0_error': (7, 1),
+            'plat_integ_auth_slot1_error': (8, 1),
+            'plat_owner_auth_slot0_error': (9, 1),
+            'plat_owner_auth_slot1_error': (10, 1),
+            'plat_owner_auth_slot2_error': (11, 1),
+            'plat_owner_auth_slot3_error': (12, 1),
+            'ext_nvm_error': (13, 1),
+            'rom_patch_error': (14, 1),
+            'hw_cfg0_error': (15, 1),
+            'hw_cfg1_error': (16, 1),
+            'secret0_error': (17, 1),
+            'secret1_error': (18, 1),
+            'secret2_error': (19, 1),
+            'secret3_error': (20, 1),
+            'life_cycle_error': (21, 1),
+            'dai_error': (22, 1),
+            'lci_error': (23, 1),
+            'timeout_error': (24, 1),
+            'lfsr_fsm_error': (25, 1),
+            'scrambling_fsm_error': (26, 1),
+            'key_deriv_fsm_error': (27, 1),
+            'bus_integ_error': (28, 1),
+            'dai_idle': (29, 1),
+            'check_pending': (30, 1),
+        }),
+        'REGWEN': BitField({
+            'en': (0, 1),
+        }),
+        'CMD': BitField({
+            'rd': (0, 1),
+            'wr': (1, 1),
+            'digest': (2, 1)
+        }),
+        'ADDRESS': BitField({
+            'address': (0, 14),
+        }),
+        'ERR_CODE': BitField({
+            'err_code': (0, 3, ERR_CODE),
+        })
+    }
+
+    def __init__(self, dbgmod: DebugModule, base: int):
+        self._log = getLogger('dtm.otp')
+        self._dm = dbgmod
+        self._base = base
+        self._max_addr = self.BITFIELDS['ADDRESS'].encode(address=-1)
+        self._map: Optional[OtpMap] = None
+        self._partitions: dict[str, OtpPartition] = {}
+        self._item_offsets: dict[str,  # partition name
+                                 dict[str,  # item name
+                                      tuple[int,  # offset
+                                            int]]] = {}  # size
+
+    def set_map(self, otpmap: 'OtpMap'):
+        self._map = otpmap
+        self._partitions = {p.name: p for p in self._map.enumerate_partitions()}
+        self._fill_item_offsets()
+
+    def get_hw_partition_digest(self, partname: str) -> int:
+        if not self._map:
+            raise RuntimeError('Partition map not loaded')
+        try:
+            part = self._partitions[partname.upper()]
+        except KeyError as exc:
+            raise ValueError(f"No such partition '{partname}'") from exc
+        if not part.hw_digest:
+            raise ValueError(f"No HW digest in partition '{partname}'")
+        self._dai_prepare(part.digest_offset)
+        self._dai_execute_command('read')
+        digest = self._dai_read64()
+        self._log.info('%s HW digest %016x', partname, digest)
+        return digest
+
+    def get_hw_partition_digests(self) -> dict[str, int]:
+        digests: dict[str, int] = {}
+        for name, part in self._partitions.items():
+            if not part.hw_digest:
+                continue
+            digests[name] = self.get_hw_partition_digest(name)
+        return digests
+
+    @classmethod
+    def is_wide_granule(cls, partition: OtpPartition, offset: int) -> bool:
+        return partition.secret or (partition.digest_offset == offset & ~0b111)
+
+    def read_partition_item(self, partname: str, itemname: str) \
+            -> Union[int, bytes]:
+        pname = partname.upper()
+        try:
+            part = self._partitions[pname]
+            items = self._item_offsets[pname]
+        except KeyError as exc:
+            raise ValueError(f"No such partition '{partname}'") from exc
+        try:
+            ioffset, size = items[itemname.upper()]
+        except KeyError as exc:
+            raise ValueError(f"No such item '{itemname}' in partition "
+                             f"'{partname}'") from exc
+        if size == 4:
+            self._dai_execute_read(part.offset + ioffset)
+            return self._dai_read32()
+        wide_granule = self.is_wide_granule(part, ioffset)
+        if wide_granule and size == 8:
+            self._dai_execute_read(part.offset + ioffset)
+            return self._dai_read64()
+        buffer = bytearray()
+        pos = 0
+        while size > 0:
+            self._dai_execute_read(part.offset + ioffset + pos)
+            if wide_granule and size >= 8:
+                val = self._dai_read64()
+                buffer.extend(val.to_bytes(8, 'little'))
+                pos += 8
+                size -= 8
+                continue
+            if size >= 4:
+                val = self._dai_read32()
+                buffer.extend(val.to_bytes(4, 'little'))
+                pos += 4
+                size -= 4
+                continue
+            raise RuntimeError('Invalid item size')
+        return bytes(buffer)
+
+    def write_partition_item(self, partname: str, itemname: str,
+                             value: Union[int, bytes, bytearray, str]) -> None:
+        pname = partname.upper()
+        try:
+            part = self._partitions[pname]
+            items = self._item_offsets[pname]
+        except KeyError as exc:
+            raise ValueError(f"No such partition '{partname}'") from exc
+        try:
+            ioffset, size = items[itemname.upper()]
+        except KeyError as exc:
+            raise ValueError(f"No such item '{itemname}' in partition "
+                             f"'{partname}'") from exc
+        if isinstance(value, int):
+            if size not in (4, 8):
+                raise ValueError(f'{itemname} expects a {size}-byte long value')
+        elif size in (4, 8):
+            value = HexInt.parse(value)
+        else:
+            if isinstance(value, str):
+                try:
+                    value = unhexlify(value)
+                except ValueError as exc:
+                    raise ValueError(f'Invalid hexa string: {exc}') from exc
+            if isinstance(value, (bytes, bytearray)):
+                vlen = len(value)
+                if size != vlen:
+                    raise ValueError(f'{itemname} expects a {size}-byte long '
+                                     f'value, value is {vlen}-byte long')
+            else:
+                raise TypeError(f'Invalid value type for {itemname}')
+        if size == 4:
+            self._dai_prepare(part.offset + ioffset)
+            self._dai_write32(value)
+            self._dai_execute_write()
+            return
+        wide_granule = self.is_wide_granule(part, ioffset)
+        if wide_granule and size == 8:
+            self._dai_prepare(part.offset + ioffset)
+            self._dai_write64(value)
+            self._dai_execute_write()
+            return
+        pos = 0
+        while size > 0:
+            self._dai_prepare(part.offset + ioffset + pos)
+            if wide_granule and size >= 8:
+                val = int.from_bytes(value[pos:pos+8], 'little')
+                self._dai_write64(val)
+                self._dai_execute_write()
+                pos += 8
+                size -= 8
+                continue
+            if size >= 4:
+                val = int.from_bytes(value[pos:pos+4], 'little')
+                self._dai_write32(val)
+                self._dai_execute_write()
+                pos += 4
+                size -= 4
+                continue
+            raise RuntimeError('Invalid item size')
+
+    def _dai_execute_read(self, offset: int) -> int:
+        self._dai_prepare(offset)
+        self._dai_execute_command('read')
+        self._dai_wait_completion()
+
+    def _dai_execute_write(self) -> int:
+        self._dai_execute_command('write')
+        self._dai_wait_completion()
+
+    def _dai_prepare(self, offset: int) -> int:
+        self._expect_dai_idle()
+        assert not self._is_dai_busy(), "DAI busy"
+        self._dai_set_address(offset)
+
+    def _dai_wait_completion(self):
+        self._expect_dai_idle()
+        assert not self._is_dai_busy(), "DAI busy"
+        dai_error = self._get_dai_error()
+        if dai_error != self.ERR_CODE.none:
+            raise OTPError(dai_error)
+        if not self._is_dai_regwen():
+            raise OTPBusyError()
+
+    def _dai_execute_command(self, command: str) -> None:
+        if not self._is_dai_regwen():
+            raise OTPBusyError()
+        try:
+            cmd = {'read': 'rd', 'write': 'wr', 'digest': 'digest'}[command]
+        except KeyError as exc:
+            raise ValueError(f'Unsupported command {command}') from exc
+        cmdargs = {cmd: True}
+        val = self.BITFIELDS['CMD'].encode(**cmdargs)
+        self._dm.write32(self._base + self.REGISTERS['cmd'], val)
+
+    def _dai_set_address(self, address: int) -> None:
+        if address > self._max_addr:
+            raise ValueError(f'Invalid OTP address {address}')
+        if not self._is_dai_regwen():
+            raise OTPBusyError()
+        self._dm.write32(self._base + self.REGISTERS['address'], address)
+
+    def _dai_read32(self) -> int:
+        return self._dm.read32(self._base + self.REGISTERS['rdata_0'])
+
+    def _dai_read64(self) -> int:
+        return self._dm.read64(self._base + self.REGISTERS['rdata_0'])
+
+    def _dai_write32(self, val: int) -> None:
+        self._dm.write32(self._base + self.REGISTERS['wdata_0'], val)
+
+    def _dai_write64(self, val: int) -> None:
+        self._dm.write64(self._base + self.REGISTERS['wdata_0'], val)
+
+    def _is_dai_regwen(self) -> bool:
+        val = self._dm.read32(self._base + self.REGISTERS['regwen'])
+        return self.BITFIELDS['REGWEN'].decode(val)['en']
+
+    def _is_dai_busy(self) -> bool:
+        val = self._dm.read32(self._base + self.REGISTERS['status'])
+        return not self.BITFIELDS['STATUS'].decode(val)['dai_idle']
+
+    def _get_dai_error(self) -> 'OTPController.ERR_CODE':
+        return self._get_error_code(self.ERROR_COUNT-2)
+
+    def _get_error_code(self, slot: int) -> 'OTPController.ERR_CODE':
+        if slot >= self.ERROR_COUNT:
+            raise ValueError(f'Invalid slot {slot}')
+        val = self._dm.read32(self._base + self.REGISTERS['err_code'] +
+                              4 * slot)
+        return self.BITFIELDS['ERR_CODE'].decode(val)['err_code']
+
+    def _expect_dai_idle(self, timeout: float = 0.5):
+        timeout += now()
+        while now() < timeout:
+            if self._is_dai_regwen():
+                return
+            sleep(0.05)
+        raise TimeoutError('DAI stalled')
+
+    def _fill_item_offsets(self) -> None:
+        for pname, part in self._partitions.items():
+            items = self._item_offsets[pname] = {}
+            offset = 0
+            for iname, item in part.items.items():
+                size = item['size']
+                items[iname] = offset, size
+                offset += size
diff --git a/python/qemu/ot/dm/regs.py b/python/qemu/ot/dm/regs.py
new file mode 100644
index 0000000000000..608eb4718aa9e
--- /dev/null
+++ b/python/qemu/ot/dm/regs.py
@@ -0,0 +1,442 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""RISC-V CSRs
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+GPRS = {
+    'x0': 0x00,
+    'x1': 0x01,
+    'x2': 0x02,
+    'x3': 0x03,
+    'x4': 0x04,
+    'x5': 0x05,
+    'x6': 0x06,
+    'x7': 0x07,
+    'x8': 0x08,
+    'x9': 0x09,
+    'x10': 0x0a,
+    'x11': 0x0b,
+    'x12': 0x0c,
+    'x13': 0x0d,
+    'x14': 0x0e,
+    'x15': 0x0f,
+    'x16': 0x10,
+    'x17': 0x11,
+    'x18': 0x12,
+    'x19': 0x13,
+    'x20': 0x14,
+    'x21': 0x15,
+    'x22': 0x16,
+    'x23': 0x17,
+    'x24': 0x18,
+    'x25': 0x19,
+    'x26': 0x1a,
+    'x27': 0x1b,
+    'x28': 0x1c,
+    'x29': 0x1d,
+    'x30': 0x1e,
+    'x31': 0x1f,
+    'zero': 0x00,
+    'ra': 0x01,
+    'sp': 0x02,
+    'gp': 0x03,
+    'tp': 0x04,
+    't0': 0x05,
+    't1': 0x06,
+    't2': 0x07,
+    's0': 0x08,
+    'fp': 0x08,
+    's1': 0x09,
+    'a0': 0x0a,
+    'a1': 0x0b,
+    'a2': 0x0c,
+    'a3': 0x0d,
+    'a4': 0x0e,
+    'a5': 0x0f,
+    'a6': 0x10,
+    'a7': 0x11,
+    's2': 0x12,
+    's3': 0x13,
+    's4': 0x14,
+    's5': 0x15,
+    's6': 0x16,
+    's7': 0x17,
+    's8': 0x18,
+    's9': 0x19,
+    's10': 0x1a,
+    's11': 0x1b,
+    't3': 0x1c,
+    't4': 0x1d,
+    't5': 0x1e,
+    't6': 0x1f,
+}
+
+CSRS = {
+    'ustatus': 0x000,
+    'uie': 0x004,
+    'utvec': 0x005,
+    'uscratch': 0x040,
+    'uepc': 0x041,
+    'ucause': 0x042,
+    'utval': 0x043,
+    'uip': 0x044,
+    'fflags': 0x001,
+    'frm': 0x002,
+    'fcsr': 0x003,
+    'vstart': 0x008,
+    'vxsat': 0x009,
+    'vxrm': 0x00a,
+    'vcsr': 0x00f,
+    'vl': 0xc20,
+    'vtype': 0xc21,
+    'vlenb': 0xc22,
+    'cycle': 0xc00,
+    'time': 0xc01,
+    'instret': 0xc02,
+    'hpmcounter3': 0xc03,
+    'hpmcounter4': 0xc04,
+    'hpmcounter5': 0xc05,
+    'hpmcounter6': 0xc06,
+    'hpmcounter7': 0xc07,
+    'hpmcounter8': 0xc08,
+    'hpmcounter9': 0xc09,
+    'hpmcounter10': 0xc0a,
+    'hpmcounter11': 0xc0b,
+    'hpmcounter12': 0xc0c,
+    'hpmcounter13': 0xc0d,
+    'hpmcounter14': 0xc0e,
+    'hpmcounter15': 0xc0f,
+    'hpmcounter16': 0xc10,
+    'hpmcounter17': 0xc11,
+    'hpmcounter18': 0xc12,
+    'hpmcounter19': 0xc13,
+    'hpmcounter20': 0xc14,
+    'hpmcounter21': 0xc15,
+    'hpmcounter22': 0xc16,
+    'hpmcounter23': 0xc17,
+    'hpmcounter24': 0xc18,
+    'hpmcounter25': 0xc19,
+    'hpmcounter26': 0xc1a,
+    'hpmcounter27': 0xc1b,
+    'hpmcounter28': 0xc1c,
+    'hpmcounter29': 0xc1d,
+    'hpmcounter30': 0xc1e,
+    'hpmcounter31': 0xc1f,
+    'cycleh': 0xc80,
+    'timeh': 0xc81,
+    'instreth': 0xc82,
+    'hpmcounter3h': 0xc83,
+    'hpmcounter4h': 0xc84,
+    'hpmcounter5h': 0xc85,
+    'hpmcounter6h': 0xc86,
+    'hpmcounter7h': 0xc87,
+    'hpmcounter8h': 0xc88,
+    'hpmcounter9h': 0xc89,
+    'hpmcounter10h': 0xc8a,
+    'hpmcounter11h': 0xc8b,
+    'hpmcounter12h': 0xc8c,
+    'hpmcounter13h': 0xc8d,
+    'hpmcounter14h': 0xc8e,
+    'hpmcounter15h': 0xc8f,
+    'hpmcounter16h': 0xc90,
+    'hpmcounter17h': 0xc91,
+    'hpmcounter18h': 0xc92,
+    'hpmcounter19h': 0xc93,
+    'hpmcounter20h': 0xc94,
+    'hpmcounter21h': 0xc95,
+    'hpmcounter22h': 0xc96,
+    'hpmcounter23h': 0xc97,
+    'hpmcounter24h': 0xc98,
+    'hpmcounter25h': 0xc99,
+    'hpmcounter26h': 0xc9a,
+    'hpmcounter27h': 0xc9b,
+    'hpmcounter28h': 0xc9c,
+    'hpmcounter29h': 0xc9d,
+    'hpmcounter30h': 0xc9e,
+    'hpmcounter31h': 0xc9f,
+    'mcycle': 0xb00,
+    'minstret': 0xb02,
+    'mcycleh': 0xb80,
+    'minstreth': 0xb82,
+    'mvendorid': 0xf11,
+    'marchid': 0xf12,
+    'mimpid': 0xf13,
+    'mhartid': 0xf14,
+    'mconfigptr': 0xf15,
+    'mstatus': 0x300,
+    'misa': 0x301,
+    'medeleg': 0x302,
+    'mideleg': 0x303,
+    'mie': 0x304,
+    'mtvec': 0x305,
+    'mcounteren': 0x306,
+    'mstatush': 0x310,
+    'mscratch': 0x340,
+    'mepc': 0x341,
+    'mcause': 0x342,
+    'mtval': 0x343,
+    'mip': 0x344,
+    'miselect': 0x350,
+    'mireg': 0x351,
+    'mtopei': 0x35c,
+    'mtopi': 0xfb0,
+    'mvien': 0x308,
+    'mvip': 0x309,
+    'midelegh': 0x313,
+    'mieh': 0x314,
+    'mvienh': 0x318,
+    'mviph': 0x319,
+    'miph': 0x354,
+    'sstatus': 0x100,
+    'sie': 0x104,
+    'stvec': 0x105,
+    'scounteren': 0x106,
+    'senvcfg': 0x10a,
+    'sstateen0': 0x10c,
+    'sstateen1': 0x10d,
+    'sstateen2': 0x10e,
+    'sstateen3': 0x10f,
+    'sscratch': 0x140,
+    'sepc': 0x141,
+    'scause': 0x142,
+    'stval': 0x143,
+    'sip': 0x144,
+    'stimecmp': 0x14d,
+    'stimecmph': 0x15d,
+    'sptbr': 0x180,
+    'satp': 0x180,
+    'siselect': 0x150,
+    'sireg': 0x151,
+    'stopei': 0x15c,
+    'stopi': 0xdb0,
+    'sieh': 0x114,
+    'siph': 0x154,
+    'hstatus': 0x600,
+    'hedeleg': 0x602,
+    'hideleg': 0x603,
+    'hie': 0x604,
+    'hcounteren': 0x606,
+    'hgeie': 0x607,
+    'htval': 0x643,
+    'hvip': 0x645,
+    'hip': 0x644,
+    'htinst': 0x64a,
+    'hgeip': 0xe12,
+    'hgatp': 0x680,
+    'htimedelta': 0x605,
+    'htimedeltah': 0x615,
+    'henvcfg': 0x60a,
+    'henvcfgh': 0x61a,
+    'hstateen0': 0x60c,
+    'hstateen0h': 0x61c,
+    'hstateen1': 0x60d,
+    'hstateen1h': 0x61d,
+    'hstateen2': 0x60e,
+    'hstateen2h': 0x61e,
+    'hstateen3': 0x60f,
+    'hstateen3h': 0x61f,
+    'vsstatus': 0x200,
+    'vsie': 0x204,
+    'vstvec': 0x205,
+    'vsscratch': 0x240,
+    'vsepc': 0x241,
+    'vscause': 0x242,
+    'vstval': 0x243,
+    'vsip': 0x244,
+    'vsatp': 0x280,
+    'vstimecmp': 0x24d,
+    'vstimecmph': 0x25d,
+    'mtinst': 0x34a,
+    'mtval2': 0x34b,
+    'hvien': 0x608,
+    'hvictl': 0x609,
+    'hviprio1': 0x646,
+    'hviprio2': 0x647,
+    'vsiselect': 0x250,
+    'vsireg': 0x251,
+    'vstopei': 0x25c,
+    'vstopi': 0xeb0,
+    'hidelegh': 0x613,
+    'hvienh': 0x618,
+    'hviph': 0x655,
+    'hviprio1h': 0x656,
+    'hviprio2h': 0x657,
+    'vsieh': 0x214,
+    'vsiph': 0x254,
+    'menvcfg': 0x30a,
+    'menvcfgh': 0x31a,
+    'mstateen0': 0x30c,
+    'mstateen0h': 0x31c,
+    'mstateen1': 0x30d,
+    'mstateen1h': 0x31d,
+    'mstateen2': 0x30e,
+    'mstateen2h': 0x31e,
+    'mstateen3': 0x30f,
+    'mstateen3h': 0x31f,
+    'mseccfg': 0x747,
+    'mseccfgh': 0x757,
+    'pmpcfg0': 0x3a0,
+    'pmpcfg1': 0x3a1,
+    'pmpcfg2': 0x3a2,
+    'pmpcfg3': 0x3a3,
+    'pmpaddr0': 0x3b0,
+    'pmpaddr1': 0x3b1,
+    'pmpaddr2': 0x3b2,
+    'pmpaddr3': 0x3b3,
+    'pmpaddr4': 0x3b4,
+    'pmpaddr5': 0x3b5,
+    'pmpaddr6': 0x3b6,
+    'pmpaddr7': 0x3b7,
+    'pmpaddr8': 0x3b8,
+    'pmpaddr9': 0x3b9,
+    'pmpaddr10': 0x3ba,
+    'pmpaddr11': 0x3bb,
+    'pmpaddr12': 0x3bc,
+    'pmpaddr13': 0x3bd,
+    'pmpaddr14': 0x3be,
+    'pmpaddr15': 0x3bf,
+    'tselect': 0x7a0,
+    'tdata1': 0x7a1,
+    'tdata2': 0x7a2,
+    'tdata3': 0x7a3,
+    'tinfo': 0x7a4,
+    'dcsr': 0x7b0,
+    'dpc': 0x7b1,
+    'dscratch0': 0x7b2,
+    'dscratch1': 0x7b3,
+    'mhpmcounter3': 0xb03,
+    'mhpmcounter4': 0xb04,
+    'mhpmcounter5': 0xb05,
+    'mhpmcounter6': 0xb06,
+    'mhpmcounter7': 0xb07,
+    'mhpmcounter8': 0xb08,
+    'mhpmcounter9': 0xb09,
+    'mhpmcounter10': 0xb0a,
+    'mhpmcounter11': 0xb0b,
+    'mhpmcounter12': 0xb0c,
+    'mhpmcounter13': 0xb0d,
+    'mhpmcounter14': 0xb0e,
+    'mhpmcounter15': 0xb0f,
+    'mhpmcounter16': 0xb10,
+    'mhpmcounter17': 0xb11,
+    'mhpmcounter18': 0xb12,
+    'mhpmcounter19': 0xb13,
+    'mhpmcounter20': 0xb14,
+    'mhpmcounter21': 0xb15,
+    'mhpmcounter22': 0xb16,
+    'mhpmcounter23': 0xb17,
+    'mhpmcounter24': 0xb18,
+    'mhpmcounter25': 0xb19,
+    'mhpmcounter26': 0xb1a,
+    'mhpmcounter27': 0xb1b,
+    'mhpmcounter28': 0xb1c,
+    'mhpmcounter29': 0xb1d,
+    'mhpmcounter30': 0xb1e,
+    'mhpmcounter31': 0xb1f,
+    'mcountinhibit': 0x320,
+    'mhpmevent3': 0x323,
+    'mhpmevent4': 0x324,
+    'mhpmevent5': 0x325,
+    'mhpmevent6': 0x326,
+    'mhpmevent7': 0x327,
+    'mhpmevent8': 0x328,
+    'mhpmevent9': 0x329,
+    'mhpmevent10': 0x32a,
+    'mhpmevent11': 0x32b,
+    'mhpmevent12': 0x32c,
+    'mhpmevent13': 0x32d,
+    'mhpmevent14': 0x32e,
+    'mhpmevent15': 0x32f,
+    'mhpmevent16': 0x330,
+    'mhpmevent17': 0x331,
+    'mhpmevent18': 0x332,
+    'mhpmevent19': 0x333,
+    'mhpmevent20': 0x334,
+    'mhpmevent21': 0x335,
+    'mhpmevent22': 0x336,
+    'mhpmevent23': 0x337,
+    'mhpmevent24': 0x338,
+    'mhpmevent25': 0x339,
+    'mhpmevent26': 0x33a,
+    'mhpmevent27': 0x33b,
+    'mhpmevent28': 0x33c,
+    'mhpmevent29': 0x33d,
+    'mhpmevent30': 0x33e,
+    'mhpmevent31': 0x33f,
+    'mhpmevent3h': 0x723,
+    'mhpmevent4h': 0x724,
+    'mhpmevent5h': 0x725,
+    'mhpmevent6h': 0x726,
+    'mhpmevent7h': 0x727,
+    'mhpmevent8h': 0x728,
+    'mhpmevent9h': 0x729,
+    'mhpmevent10h': 0x72a,
+    'mhpmevent11h': 0x72b,
+    'mhpmevent12h': 0x72c,
+    'mhpmevent13h': 0x72d,
+    'mhpmevent14h': 0x72e,
+    'mhpmevent15h': 0x72f,
+    'mhpmevent16h': 0x730,
+    'mhpmevent17h': 0x731,
+    'mhpmevent18h': 0x732,
+    'mhpmevent19h': 0x733,
+    'mhpmevent20h': 0x734,
+    'mhpmevent21h': 0x735,
+    'mhpmevent22h': 0x736,
+    'mhpmevent23h': 0x737,
+    'mhpmevent24h': 0x738,
+    'mhpmevent25h': 0x739,
+    'mhpmevent26h': 0x73a,
+    'mhpmevent27h': 0x73b,
+    'mhpmevent28h': 0x73c,
+    'mhpmevent29h': 0x73d,
+    'mhpmevent30h': 0x73e,
+    'mhpmevent31h': 0x73f,
+    'mhpmcounter3h': 0xb83,
+    'mhpmcounter4h': 0xb84,
+    'mhpmcounter5h': 0xb85,
+    'mhpmcounter6h': 0xb86,
+    'mhpmcounter7h': 0xb87,
+    'mhpmcounter8h': 0xb88,
+    'mhpmcounter9h': 0xb89,
+    'mhpmcounter10h': 0xb8a,
+    'mhpmcounter11h': 0xb8b,
+    'mhpmcounter12h': 0xb8c,
+    'mhpmcounter13h': 0xb8d,
+    'mhpmcounter14h': 0xb8e,
+    'mhpmcounter15h': 0xb8f,
+    'mhpmcounter16h': 0xb90,
+    'mhpmcounter17h': 0xb91,
+    'mhpmcounter18h': 0xb92,
+    'mhpmcounter19h': 0xb93,
+    'mhpmcounter20h': 0xb94,
+    'mhpmcounter21h': 0xb95,
+    'mhpmcounter22h': 0xb96,
+    'mhpmcounter23h': 0xb97,
+    'mhpmcounter24h': 0xb98,
+    'mhpmcounter25h': 0xb99,
+    'mhpmcounter26h': 0xb9a,
+    'mhpmcounter27h': 0xb9b,
+    'mhpmcounter28h': 0xb9c,
+    'mhpmcounter29h': 0xb9d,
+    'mhpmcounter30h': 0xb9e,
+    'mhpmcounter31h': 0xb9f,
+    'umte': 0x4c0,
+    'upmmask': 0x4c1,
+    'upmbase': 0x4c2,
+    'mmte': 0x3c0,
+    'mpmmask': 0x3c1,
+    'mpmbase': 0x3c2,
+    'smte': 0x1c0,
+    'spmmask': 0x1c1,
+    'spmbase': 0x1c2,
+    'vsmte': 0x2c0,
+    'vspmmask': 0x2c1,
+    'vspmbase': 0x2c2,
+    'scountovf': 0xda0,
+    'seed': 0x015,
+    'jvt': 0x017,
+}
diff --git a/python/qemu/ot/dtm/__init__.py b/python/qemu/ot/dtm/__init__.py
new file mode 100644
index 0000000000000..6c8c430b5c2ee
--- /dev/null
+++ b/python/qemu/ot/dtm/__init__.py
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Debug Module tools.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from .dtm import DebugTransportModule  # noqa: F401
diff --git a/python/qemu/ot/dtm/dtm.py b/python/qemu/ot/dtm/dtm.py
new file mode 100644
index 0000000000000..06cae9be3681e
--- /dev/null
+++ b/python/qemu/ot/dtm/dtm.py
@@ -0,0 +1,325 @@
+# Copyright (c) 2024 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Debug Module tools.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+
+from logging import getLogger
+from sys import modules
+from typing import Optional
+
+from jtagtools.bits import BitSequence
+from jtagtools.jtag import JtagEngine
+
+
+class DMIError(RuntimeError):
+    """DMI Error."""
+
+
+class DMIBusyError(DMIError):
+    """Last operation still in progress."""
+
+    def __init__(self):
+        super().__init__('DMI is busy')
+
+
+class DMIFailedError(DMIError):
+    """Last operation has failed."""
+
+    def __init__(self):
+        super().__init__('DMI execution failed')
+
+
+class DTMRegister:
+    """Abstract base class for DTM registers."""
+
+    def __init__(self, dtm: 'DebugTransportModule'):
+        name = self.__class__.__name__
+        if (not hasattr(self.__class__, 'ADDRESS') or
+                not isinstance(getattr(self, 'ADDRESS'), int)):
+            raise NotImplementedError(f'Unknown/invalid register address for '
+                                      f'{self.__class__.__name__}')
+        self._dtm = dtm
+        self._log = getLogger(f'dtm.{name.lower()}')
+
+    @property
+    def address(self) -> int:
+        """Return the register address."""
+        # pylint: disable=no-member
+        return self.ADDRESS
+
+    def _read(self, length: int) -> BitSequence:
+        """Read the current register value."""
+        self._log.debug('read %d bits', length)
+        return self._dtm.read(self.address, length)
+
+    def _write(self, bseq: BitSequence):
+        """Read the current register value."""
+        self._log.debug('write %s', bseq)
+        return self._dtm.write(self.address, bseq)
+
+    def _read_word(self) -> int:
+        """Read the current register value as a 32-bit value."""
+        self._log.debug('read_word')
+        return self._dtm.read_word(self.address)
+
+    def _write_word(self, value: int):
+        """Read the current register value as a 32-bit value."""
+        self._log.debug('write_word %x', value)
+        return self._dtm.write_word(self.address, value)
+
+
+class DTMCS(DTMRegister):
+    """DTM Control and Status register."""
+
+    ADDRESS = 0x10
+
+    @property
+    def idle(self) -> int:
+        """Minimum number of cycles a debugger should spend in Run-Test/Idle
+           after every DMI scan (hint only)
+        """
+        hint = (self._read_word() >> 12) & 0b111
+        self._log.debug('idle: %d', hint)
+        return hint
+
+    @property
+    def dmistat(self) -> int:
+        """Return DMI status
+
+           0: No error.
+           1: Reserved. Interpret the same as 2 (see DMI register)
+           2: An operation failed (resulted in DMI operation of type 2).
+           3: An operation was attempted while a DMI access was still in
+              progress (resulted in DMI operation of type 3).
+        """
+        dmistat = (self._read_word() >> 10) & 0b11
+        self._log.debug('dmistat: %d', dmistat)
+        return dmistat
+
+    @property
+    def abits(self) -> int:
+        """The bit size of address in DMI."""
+        abits = (self._read_word() >> 4) & 0b111111
+        self._log.debug('abits: %d', abits)
+        return abits
+
+    @property
+    def version(self) -> int:
+        """Version of the supported DMI specification (raw code)."""
+        version = self._read_word() & 0b1111
+        self._log.debug('version: %d', version)
+        return version
+
+    @property
+    def dmi_version(self) -> tuple[int, int]:
+        """Version of the supported DMI specification."""
+        try:
+            tversion = {0: (0, 11), 1: (0, 13)}[self.version]
+        except KeyError:
+            tversion = (0, 0)
+        self._log.debug('version: %d.%d', *tversion)
+        return tversion
+
+    def check(self) -> None:
+        """Raise a DMI Error if any.
+        """
+        self._log.debug('check')
+        dmistat = self.dmistat
+        err = self._dtm.build_error(dmistat)
+        if err:
+            self._dtm.set_sticky(err)
+            raise err
+
+    def dmireset(self) -> None:
+        """Clears the sticky error state and allows the DTM to retry or complete
+           the previous transaction.
+        """
+        self._log.debug('dmi reset')
+        self._write_word(1 << 16)
+        self._dtm.clear_sticky()
+
+    def dmihardreset(self) -> None:
+        """Causes the DTM to forget about any outstanding DMI transactions.
+        """
+        self._log.debug('dmi hard reset')
+        self._write_word(1 << 17)
+        self._dtm.clear_sticky()
+
+
+class DMI(DTMRegister):
+    """Debug Module Interface Access."""
+
+    ADDRESS = 0x11
+
+    OPS = {'nop': 0, 'read': 1, 'write': 2}
+
+    def __init__(self, *args, **kwargs):
+        super().__init__(*args, **kwargs)
+        self._abits = 0
+
+    @property
+    def length(self) -> int:
+        """Return the register length in bits."""
+        return self._abits + 32 + 2
+
+    def write(self, address: int, value: int) -> None:
+        """Write a 32-bit value to the specified address
+        """
+        self._log.debug('dmi 0x%x 0x%08x', address, value)
+        dmi = self._build_dmi(address)
+        value &= 0xffff_ffff
+        dmi |= value << 2
+        dmi |= self.OPS['write']
+        wbseq = BitSequence(dmi, self.length)
+        self._write(wbseq)
+        rbseq = self._read(self.length)
+        res = int(rbseq) & 0b11
+        err = self._dtm.build_error(res)
+        if err:
+            self._log.error('op res %d -> %s', res, err)
+            self._dtm.set_sticky(err)
+            raise err
+
+    def read(self, address: int) -> int:
+        """Read a 32-bit value from the specified address
+        """
+        self._log.debug('read @ 0x%x', address)
+        dmi = self._build_dmi(address)
+        dmi |= self.OPS['read']
+        wbseq = BitSequence(dmi, self.length)
+        self._write(wbseq)
+        rbseq = self._read(self.length)
+        value = int(rbseq)
+        res = value & 0b11
+        err = self._dtm.build_error(res)
+        if err:
+            self._log.error('op res %d -> %s', res, err)
+            self._dtm.set_sticky(err)
+            raise err
+        value >>= 2
+        value &= 0xffff_ffff
+        self._log.debug('read: 0x%08x', value)
+        return value
+
+    def _build_dmi(self, address: int) -> int:
+        self._check_error()
+        if not self._abits:
+            self._abits = self._dtm.abits()
+            if self._abits < 1:
+                raise DMIError('Invalid reported address bits')
+            self._log.debug('DMI width: %d bits', self._abits)
+        if address >= (1 << self._abits):
+            raise ValueError(f'Address 0x{address:x} too large, '
+                             f'max 0x{(1 << self._abits) - 1:x}')
+        return address << (32 + 2)
+
+    def _check_error(self) -> None:
+        self._dtm.check_sticky()
+
+
+class DebugTransportModule:
+    """Debug Transport Modules provide access to the DM over JTAG.
+
+       :param engine: JTAG engine
+       :param ir_length: the length in bits of the IR register
+    """
+
+    def __init__(self, engine: JtagEngine, ir_length: int):
+        self._engine = engine
+        self._ir_length = ir_length
+        self._log = getLogger('dtm')
+        self._regs = self._load_registers()
+        self._sticky: Optional[DMIError] = None
+
+    def __getitem__(self, name: str) -> DTMRegister:
+        try:
+            return self._regs[name]
+        except KeyError as exc:
+            raise ValueError(f"No such DTM reg '{name}'") from exc
+
+    @property
+    def engine(self) -> JtagEngine:
+        """Provide the associated engine."""
+        return self._engine
+
+    @classmethod
+    def build_error(cls, code: int) -> Optional[DMIError]:
+        """Build a DMIError from an error code."""
+        if code in (1, 2):
+            return DMIFailedError()
+        if code == 3:
+            return DMIBusyError()
+        if code == 0:
+            return None
+        raise ValueError(f'Invalid DTM error code: {code}')
+
+    def read(self, address: int, length: int) -> BitSequence:
+        """Read a bit sequence value."""
+        self._log.debug("read addr: 0x%x len: %d", address, length)
+        self._engine.write_ir(BitSequence(address, self._ir_length))
+        self._engine.read_dr(length)
+        return self._engine.scan()
+
+    def write(self, address: int, bseq: BitSequence) -> None:
+        """Write a bit sequence value."""
+        self._log.debug("write addr: 0x%x len: %d", address, len(bseq))
+        self._engine.write_ir(BitSequence(address, self._ir_length))
+        self._engine.write_dr(bseq)
+        self._engine.scan()
+
+    def read_word(self, address: int) -> int:
+        """Read a 32-bit value."""
+        return int(self.read(address, 32))
+
+    def write_word(self, address: int, value: int) -> int:
+        """Write a 32-bit value."""
+        self.write(address, BitSequence(value, 32))
+
+    def set_sticky(self, error: DMIError):
+        """Set sticky error.
+           @warning Internal API, should not be called but from the DMI
+                    register.
+        """
+        self._sticky = error
+
+    def clear_sticky(self) -> None:
+        """Clear sticky error.
+           @warning Internal API, should not be called but from the DMI
+                    register.
+        """
+        self._sticky = None
+
+    def check_sticky(self) -> None:
+        """Raise a DMIError if a sticky error has been recorded.
+        """
+        if self._sticky:
+            raise self._sticky
+
+    def abits(self) -> int:
+        """Report the bit size of address in DMI."""
+        try:
+            dtmcs = self['dtmcs']
+        except KeyError as exc:
+            raise DMIError('Missing DTMCS register') from exc
+        return dtmcs.abits
+
+    def _load_registers(self) -> dict[str, DTMRegister]:
+        module = modules[__name__]
+        regs = {}
+        for name in dir(module):
+            class_ = getattr(module, name)
+            if not isinstance(class_, type):
+                continue
+            if not issubclass(class_, DTMRegister) or class_ is DTMRegister:
+                continue
+            address = getattr(class_, 'ADDRESS', None)
+            if not address or not isinstance(address, int):
+                continue
+            self._log.debug('Instanciate %s', name)
+            regs[name.lower()] = class_(self)
+        return regs
diff --git a/python/qemu/ot/eflash/__init__.py b/python/qemu/ot/eflash/__init__.py
new file mode 100644
index 0000000000000..02c60c55c001c
--- /dev/null
+++ b/python/qemu/ot/eflash/__init__.py
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Embedded Flash tools."""
diff --git a/python/qemu/ot/eflash/gen.py b/python/qemu/ot/eflash/gen.py
new file mode 100644
index 0000000000000..dcb0a9411e383
--- /dev/null
+++ b/python/qemu/ot/eflash/gen.py
@@ -0,0 +1,594 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Create/update OpenTitan backend flash file.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import hexlify
+from hashlib import sha256
+from itertools import repeat
+from logging import getLogger
+from os import SEEK_END, SEEK_SET, stat
+from os.path import abspath, basename, exists, isfile
+from struct import calcsize as scalc, pack as spack, unpack as sunpack
+from typing import Any, BinaryIO, NamedTuple, Optional, Union
+import re
+
+# pylint: disable=missing-function-docstring
+
+from ot.util.elf import ElfBlob
+
+
+class BootLocation(NamedTuple):
+    """Boot location entry (always in two first pages of first info part)
+    """
+    bank: int
+    page: int
+    seq: int
+
+
+class RuntimeDescriptor(NamedTuple):
+    """Description of an executable binary.
+    """
+    code_start: int
+    code_end: int
+    size: int
+    entry_point: int
+
+
+class FlashGen:
+    """Generate a flash image file.
+
+       :param bl_offset: offset of the BL0 storage within the data partition.
+                         if forced to 0, do not reserve any space for BL0, i.e.
+                         dedicated all storage space to ROM_EXT section.
+       :discard_elf_check: whether to ignore mismatching binary/ELF files.
+       :accept_invalid: accept invalid input files (fully ignore content)
+       :discard_time_check: whether to ignore mismatching time between binary
+                         and ELF files.
+    """
+
+    NUM_BANKS = 2
+    PAGES_PER_BANK = 256
+    NUM_REGIONS = 8
+    INFOS = [10, 1, 2]
+    WORDS_PER_PAGE = 256
+    BYTES_PER_WORD = 8
+    BYTES_PER_PAGE = 2048
+    BYTES_PER_BANK = 524288
+    CHIP_ROM_EXT_SIZE_MAX = 0x10000
+
+    HEADER_FORMAT = {
+        'magic': '4s',  # "vFSH"
+        'hlength': 'I',  # count of header bytes after this point
+        'version': 'I',  # version of the header
+        'bank': 'B',  # count of bank
+        'info': 'B',  # count of info partitions per bank
+        'page': 'H',  # count of pages per bank
+        'psize': 'I',  # page size in bytes
+        'ipp': '12s',  # count of pages for each info partition (up to 12 parts)
+    }
+
+    BOOT_HEADER_FORMAT = {
+        'sha': '32s',  # SHA-256 digest of boot data
+        'valid': 'Q',  # Invalidate a previously entry
+        'identifier': 'I',  # Boot data identifier (i.e. magic)
+        'counter': 'I',  # used to determine the newest entry
+        'min_ver_rom_ext': 'I',  # Minimum required security version for ROM_EXT
+        'min_ver_bl0': 'I',  # Minimum required security version for BL0
+        'padding': 'Q',  # Padding to make the size of header a power of 2
+    }
+
+    MANIFEST_FORMAT = {
+        # SigverifyRsaBuffer
+        'signature': '384s',  # 96u32
+        # ManifestUsageConstraints
+        'selector_bits': 'I',
+        'device_id': '32s',  # 8u32
+        'manuf_state_creator': 'I',
+        'manuf_state_owner': 'I',
+        'life_cycle_state': 'I',
+        # SigverifyRsaBuffer
+        'modulus': '384s',
+        'address_translation': 'I',
+        'identifier': '4s',
+        # ManifestVersion
+        'manifest_version_minor': 'H',
+        'manifest_version_major': 'H',
+        'signed_region_end': 'I',
+        'length': 'I',
+        'version_major': 'I',
+        'version_minor': 'I',
+        'security_version': 'I',
+        # Timestamp
+        'timestamp': '8s',  # cannot use 'Q', no longer aligned on 64-bit type
+        # KeymgrBindingValue
+        'binding_value': '32s',  # 8u32
+        'max_key_version': 'I',
+        'code_start': 'I',
+        'code_end': 'I',
+        'entry_point': 'I',
+        # ManifestExtTable
+        'entries': '120s'  # 15*(2u32)
+    }
+
+    MANIFEST_SIZE = 1024
+    MANIFEST_VERSION_MINOR1 = 0x6c47
+    MANIFEST_VERSION_MAJOR1 = 0x71c3
+    # Allow v2 manifests, the only difference is that signatures are ECDSA.
+    MANIFEST_VERSION_MAJOR2 = 0x0002
+    MANIFEST_EXT_TABLE_COUNT = 15
+
+    MANIFEST_TRUE = 0x739  # 'true' value for address_translation field
+    MANIFEST_FALSE = 0x1d4  # 'false' value for address_translation field
+
+    IDENTIFIERS = {
+        None: b'\x00\x00\x00\x00',
+        'rom_ext': b'OTRE',
+        'bl0': b'OTB0',
+    }
+
+    DEBUG_TRAILER_FORMAT = {
+        'otre0': '256s',  # optional path to the rom_ext filename in bank A
+        'otb00': '256s',  # optional path to the bl0 filename in bank A
+        'otre1': '256s',  # optional path to the rom_ext filename in bank B
+        'otb01': '256s',  # optional path to the bl0 filename in bank B
+    }
+
+    BOOT_IDENTIFIER = 0x41444f42
+    BOOT_INVALID = 0
+    BOOT_VALID = (1 << 64) - 1
+    BOOT_BANK = 1
+    BOOT_PARTS = 2
+
+    def __init__(self, bl_offset: Optional[int] = None,
+                 discard_elf_check: bool = False,
+                 accept_invalid: bool = False,
+                 discard_time_check: bool = False):
+        self._log = getLogger('flashgen')
+        self._check_manifest_size()
+        self._bl_offset = bl_offset if bl_offset is not None \
+            else self.CHIP_ROM_EXT_SIZE_MAX
+        self._accept_invalid = accept_invalid
+        self._check_elf = not (discard_elf_check or self._accept_invalid)
+        self._check_time = not discard_time_check and self._check_elf
+        hfmt = ''.join(self.HEADER_FORMAT.values())
+        header_size = scalc(hfmt)
+        assert header_size == 32
+        self._header_size = header_size
+        bhfmt = ''.join(self.BOOT_HEADER_FORMAT.values())
+        self._boot_header_size = scalc(bhfmt)
+        tfmt = ''.join(self.DEBUG_TRAILER_FORMAT.values())
+        trailer_size = scalc(tfmt)
+        self._image_size = ((self.BYTES_PER_BANK + self.info_part_size()) *
+                            self.NUM_BANKS + self._header_size + trailer_size)
+        self._ffp: Optional[BinaryIO] = None
+
+    def open(self, path: str) -> None:
+        """Prepare flash content into a QEMU RAW stream.
+        """
+        mode = 'r+b' if exists(path) else 'w+b'
+        # cannot use a context manager here
+        # pylint: disable=consider-using-with
+        self._ffp = open(path, mode)
+        self._ffp.seek(0, SEEK_END)
+        vsize = self._ffp.tell()
+        if vsize < self._image_size:
+            if vsize and mode.startswith('r'):
+                self._log.info('File image too short, expanding')
+            else:
+                self._log.info('Creating new image file')
+            header = self._build_header()
+            self._write(0, header)
+            vsize += len(header)
+            self._write(len(header),
+                        bytes(repeat(0xff, self._image_size-vsize)))
+        self._ffp.seek(0)
+        if vsize > self._image_size:
+            self._log.info('File image too long, truncating')
+            self._ffp.truncate(self._image_size)
+
+    def close(self):
+        if self._ffp:
+            pos = self._ffp.seek(0, SEEK_END)
+            self._ffp.close()
+            self._ffp = None
+            if pos != self._image_size:
+                self._log.error('Invalid image size (%d bytes)', pos)
+
+    @property
+    def logger(self):
+        return self._log
+
+    @classmethod
+    def info_part_size(cls) -> int:
+        return sum(cls.INFOS) * cls.BYTES_PER_PAGE
+
+    def read_boot_info(self) -> dict[BootLocation,
+                                     dict[str, Union[int, bytes]]]:
+        size = self._boot_header_size
+        fmt = ''.join(self.BOOT_HEADER_FORMAT.values())
+        boot_entries = {}
+        boot_bank = 1
+        for page in range(self.BOOT_PARTS):
+            base = page * self.BYTES_PER_PAGE
+            for offset in range(0, self.BYTES_PER_PAGE, size):
+                bdata = self.read_info_partition(boot_bank, base+offset, size)
+                if len(bdata) != size:
+                    raise ValueError(f'Cannot read header: {len(bdata)} '
+                                     f'bytes @ page {page} offset '
+                                     f'{base+offset}')
+                values = sunpack(f'<{fmt}', bdata)
+                boot = dict(zip(self.BOOT_HEADER_FORMAT, values))
+                if boot['identifier'] != self.BOOT_IDENTIFIER:
+                    continue
+                if boot['valid'] != self.BOOT_VALID:
+                    continue
+                boot_entries[BootLocation(boot_bank, page, offset//size)] = boot
+            offset += size
+        return boot_entries
+
+    def read_info_partition(self, bank: int, offset: int, size: int) -> bytes:
+        offset += (self._header_size + self.NUM_BANKS * self.BYTES_PER_BANK +
+                   bank * self.info_part_size())
+        pos = self._ffp.tell()
+        self._ffp.seek(offset)
+        data = self._ffp.read(size)
+        self._ffp.seek(pos)
+        return data
+
+    def store_rom_ext(self, bank: int, dfp: BinaryIO,
+                      elfpath: Optional[str] = None,
+                      no_header: bool = False) -> None:
+        if not 0 <= bank < self.NUM_BANKS:
+            raise ValueError(f'Invalid bank {bank}')
+        data = dfp.read()
+        if len(data) > self.BYTES_PER_BANK:
+            raise ValueError('Data too large')
+        bindesc = self._check_rom_ext(data) if not no_header else None
+        boot_entries = self.read_boot_info()
+        if not boot_entries:
+            next_loc = BootLocation(self.BOOT_BANK, 0, 0)
+            next_count = 5
+            self._log.info('No pre-existing BootLocation')
+        else:
+            sorted_locs = sorted(boot_entries,
+                                 key=lambda e: boot_entries[e]['counter'])
+            mr_loc = sorted_locs[-1]
+            self._log.info('Last boot location %s', mr_loc)
+            mr_entry = boot_entries[mr_loc]
+            mr_bank = mr_loc.bank
+            next_op_bank = mr_bank
+            op_locs = [loc for loc in sorted_locs if loc.bank == next_op_bank]
+            if op_locs:
+                last_op_loc = op_locs[-1]
+                next_op_seq = last_op_loc.seq + 1
+                next_op_page = last_op_loc.page
+            else:
+                next_op_seq = 0
+                next_op_page = 0
+            if next_op_seq >= self.BYTES_PER_PAGE/self._boot_header_size:
+                next_op_page += 1
+                next_op_seq = 0
+            if next_op_page >= self.BOOT_PARTS:
+                # erase the flash?
+                raise ValueError('No more room to store boot location')
+            next_loc = BootLocation(next_op_bank, next_op_page, next_op_seq)
+            next_count = mr_entry['counter'] + 1
+        self._write(self._header_size + bank * self.BYTES_PER_BANK, data)
+        boot_header = self._build_boot_header(next_count)
+        offset = self._get_boot_location_offset(next_loc)
+        self._write(offset, boot_header)
+        info_offset = (offset - self.NUM_BANKS * self.BYTES_PER_BANK -
+                       self._header_size)
+        self._log.info('New %s stored @ abs:0x%06x / rel:0x%06x',
+                       next_loc, offset, info_offset)
+        field_offset, field_data = self._build_field(self.BOOT_HEADER_FORMAT,
+                                                     'valid', self.BOOT_INVALID)
+        for loc, entry in boot_entries.items():
+            if loc.bank != next_op_bank:
+                continue
+            if entry['valid'] != self.BOOT_INVALID:
+                offset = self._get_boot_location_offset(loc)
+                offset += field_offset
+                self._write(offset, field_data)
+        ename = f'otre{bank}'
+        if bindesc:
+            if not elfpath:
+                elfpath = self._get_elf_filename(dfp.name)
+        elif elfpath and not no_header:
+            self._log.warning('Discarding ELF as input binary file is invalid')
+            elfpath = None
+        if elfpath and isfile(dfp.name) and not no_header:
+            elftime = stat(elfpath).st_mtime
+            bintime = stat(dfp.name).st_mtime
+            if bintime < elftime:
+                msg = 'Application binary file is older than ELF file'
+                if self._check_time:
+                    raise RuntimeError(msg)
+                self._log.warning(msg)
+            be_match = self._compare_bin_elf(bindesc, elfpath)
+            if not be_match:
+                if be_match is None:
+                    msg = 'Cannot verify ELF file (pyelftools not installed)'
+                else:
+                    msg = 'Application ELF file does not match binary file'
+                if self._check_elf:
+                    raise RuntimeError(msg)
+                self._log.warning(msg)
+        self._store_debug_info(ename, elfpath)
+
+    def store_bootloader(self, bank: int, dfp: BinaryIO,
+                         elfpath: Optional[str] = None,
+                         no_header: bool = False) -> None:
+        if self._bl_offset == 0:
+            raise ValueError('Bootloader cannot be used')
+        if not 0 <= bank < self.NUM_BANKS:
+            raise ValueError(f'Invalid bank {bank}')
+        data = dfp.read()
+        if len(data) > self.BYTES_PER_BANK:
+            raise ValueError('Data too large')
+        bindesc = self._check_bootloader(data) if not no_header else None
+        self._write(self._header_size + self._bl_offset, data)
+        ename = f'otb0{bank}'
+        if bindesc:
+            if not elfpath:
+                elfpath = self._get_elf_filename(dfp.name)
+        elif elfpath and not no_header:
+            self._log.warning('Discarding ELF as input binary file is invalid')
+            elfpath = None
+        if elfpath and not no_header:
+            elftime = stat(elfpath).st_mtime
+            bintime = stat(dfp.name).st_mtime
+            if bintime < elftime:
+                msg = 'Boot binary file is older than ELF file'
+                if self._check_time:
+                    raise RuntimeError(msg)
+                self._log.warning(msg)
+            be_match = self._compare_bin_elf(bindesc, elfpath)
+            if not be_match:
+                if be_match is None:
+                    msg = 'Cannot verify ELF file (pyelftools not installed)'
+                else:
+                    msg = 'Boot ELF file does not match binary file'
+                if self._check_elf:
+                    raise RuntimeError(msg)
+                self._log.warning(msg)
+        self._store_debug_info(ename, elfpath)
+
+    def store_ot_files(self, otdescs: list[str]) -> None:
+        for otdesc in otdescs:
+            # @TODO: add back support for ELFs for convenience debug symbols
+            # when the flash debug trailer format is changed to support
+            # arbitrary numbers (and locations) of ELFs, which is also
+            # needed due to mutable flash.
+            parts = otdesc.split('@', 1)
+            if len(parts) < 2:
+                raise ValueError('Missing address in OT descriptor')
+            bin_filename = parts[0]
+            if not isfile(bin_filename):
+                raise ValueError(f'No such file {bin_filename}')
+            try:
+                address = int(parts[1], 16)
+            except ValueError as exc:
+                raise ValueError('Invalid address in OT descriptor') from exc
+            max_offset = self.NUM_BANKS * self.BYTES_PER_BANK
+            if not 0 <= address < max_offset:
+                raise ValueError(f'Invalid address 0x{address:x} for bin '
+                                 f'{basename(bin_filename)}')
+            with open(bin_filename, 'rb') as bfp:
+                data = bfp.read()
+            address_end = address + len(data)
+            if not 0 <= address_end <= max_offset:
+                raise ValueError(f'Binary {basename(bin_filename)} at '
+                                 f'0x{address:x}:0x{address_end:x} does not '
+                                 f'fit in flash size 0x{max_offset:x}')
+            self._write(self._header_size + address, data)
+
+    def _compare_bin_elf(self, bindesc: RuntimeDescriptor, elfpath: str) \
+            -> Optional[bool]:
+        if ElfBlob.ELF_ERROR:
+            return None
+        with open(elfpath, 'rb') as efp:
+            elfdesc = self._load_elf_info(efp)
+        if not elfdesc:
+            return False
+        binep = bindesc.entry_point & (self.CHIP_ROM_EXT_SIZE_MAX - 1)
+        elfep = elfdesc.entry_point & (self.CHIP_ROM_EXT_SIZE_MAX - 1)
+        if binep != elfep:
+            self._log.warning('Cannot compare bin vs. elf files')
+            return False
+        offset = elfdesc.entry_point - bindesc.entry_point
+        self._log.debug('ELF base offset 0x%08x', offset)
+        relfdesc = RuntimeDescriptor(elfdesc.code_start - offset,
+                                     elfdesc.code_end - offset,
+                                     elfdesc.size,
+                                     elfdesc.entry_point - offset)
+        match = bindesc == relfdesc
+        logfunc = self._log.debug if match else self._log.warning
+        logfunc('start bin %08x / elf %08x',
+                bindesc.code_start, relfdesc.code_start)
+        logfunc('end   bin %08x / elf %08x',
+                bindesc.code_end, relfdesc.code_end)
+        logfunc('size  bin %08x / elf %08x',
+                bindesc.size, relfdesc.size)
+        logfunc('entry bin %08x / elf %08x',
+                bindesc.entry_point, relfdesc.entry_point)
+        return match
+
+    def _write(self, offset: Optional[int], data: bytes) -> None:
+        pos = self._ffp.tell()
+        if offset is None:
+            offset = pos
+        if offset + len(data) > self._image_size:
+            raise ValueError(f'Invalid offset {offset}+{len(data)}, '
+                             f'max {self._image_size}')
+        self._ffp.seek(offset, SEEK_SET)
+        self._ffp.write(data)
+        self._ffp.seek(pos, SEEK_SET)
+
+    def _get_info_part_offset(self, part: int, info: int) -> int:
+        offset = self._header_size + self.NUM_BANKS * self.BYTES_PER_BANK
+        partition = 0
+        while partition < part:
+            offset += self.INFOS[partition]*self.BYTES_PER_PAGE
+            partition += 1
+        offset += info * self.BYTES_PER_PAGE
+        return offset
+
+    def _get_boot_location_offset(self, loc: BootLocation) -> int:
+        return (loc.bank * self.info_part_size() +
+                self._get_info_part_offset(0, 0) +
+                loc.page * self.BYTES_PER_PAGE +
+                loc.seq * self._boot_header_size)
+
+    def _build_field(self, fmtdict: dict[str, Any], field: str, value: Any) \
+            -> tuple[int, bytes]:
+        offset = 0
+        for name, fmt in fmtdict.items():
+            if name == field:
+                return offset, spack(f'<{fmt}', value)
+            offset += scalc(fmt)
+        raise ValueError(f'No such field: {field}')
+
+    def _build_header(self) -> bytes:
+        # hlength is the length of header minus the two first items (T, L)
+        hfmt = self.HEADER_FORMAT
+        fhfmt = ''.join(hfmt.values())
+        shfmt = ''.join(hfmt[k] for k in list(hfmt)[:2])
+        hlen = scalc(fhfmt) - scalc(shfmt)
+        ipp = bytearray(self.INFOS)
+        ipp.extend([0] * (12 - len(ipp)))
+        values = {
+            'magic': b'vFSH', 'hlength': hlen, 'version': 1,
+            'bank': self.NUM_BANKS, 'info': len(self.INFOS),
+            'page': self.PAGES_PER_BANK, 'psize': self.BYTES_PER_PAGE,
+            'ipp': bytes(ipp)
+        }
+        args = [values[k] for k in hfmt]
+        header = spack(f'<{fhfmt}', *args)
+        return header
+
+    def _build_boot_header(self, counter) -> bytes:
+        min_sec_ver_rom_ext = 0
+        min_sec_ver_bl0 = 0
+        padding = 0
+        fmts = list(self.BOOT_HEADER_FORMAT.values())
+        sha_fmt, pld_fmt = fmts[0], ''.join(fmts[1:])
+        payload = spack(f'<{pld_fmt}', self.BOOT_VALID, self.BOOT_IDENTIFIER,
+                        counter, min_sec_ver_rom_ext, min_sec_ver_bl0, padding)
+        sha = spack(sha_fmt, sha256(payload).digest())
+        header = b''.join((sha, payload))
+        return header
+
+    def _get_elf_filename(self, filename: str) -> str:
+        pathname = abspath(filename)
+        radix = re.sub(r'.[a-z_]+_0.signed.bin$', '', pathname)
+        elfname = f'{radix}.elf'
+        if not exists(elfname):
+            self._log.warning('No ELF debug info found')
+            return ''
+        self._log.info('Using ELF %s for %s',
+                       basename(elfname), basename(filename))
+        return elfname
+
+    def _load_elf_info(self, efp: BinaryIO) \
+            -> Optional[RuntimeDescriptor]:
+        if ElfBlob.ELF_ERROR:
+            # ELF tools are not available
+            self._log.warning('ELF file cannot be verified')
+            return None
+        elf = ElfBlob()
+        elf.load(efp)
+        if elf.address_size != 32:
+            raise ValueError('Spefified ELF file {} is not an ELF32 file')
+        elfstart, elfend = elf.code_span
+        return RuntimeDescriptor(elfstart, elfend, elf.size, elf.entry_point)
+
+    def _store_debug_info(self, entryname: str, filename: Optional[str]) \
+            -> None:
+        fnp = filename.encode('utf8') if filename else b''
+        lfnp = len(fnp)
+        tfmt = ''.join(self.DEBUG_TRAILER_FORMAT.values())
+        trailer_size = scalc(tfmt)
+        trailer_offset = self._image_size - trailer_size
+        for name, fmt in self.DEBUG_TRAILER_FORMAT.items():
+            lfmt = scalc(fmt)
+            if name != entryname:
+                trailer_offset += lfmt
+                continue
+            if lfnp < lfmt:
+                fnp = b''.join((fnp, bytes(lfmt-lfnp)))
+            elif lfnp > lfmt:
+                self._log.warning('ELF pathname too long to store')
+                return
+            fnp = spack(fmt, fnp)  # useless, used as sanity check
+            self._write(trailer_offset, fnp)
+            break
+        else:
+            self._log.warning('Unable to find a matching debug entry: %s',
+                              entryname)
+
+    def _check_rom_ext(self, data: bytes) -> Optional[RuntimeDescriptor]:
+        max_size = self._bl_offset or self.BYTES_PER_BANK
+        try:
+            return self._check_manifest(data, 'rom_ext', max_size)
+        except ValueError:
+            if self._accept_invalid:
+                return None
+            raise
+
+    def _check_bootloader(self, data: bytes) -> Optional[RuntimeDescriptor]:
+        assert self._bl_offset
+        max_size = self.BYTES_PER_BANK - self._bl_offset
+        try:
+            return self._check_manifest(data, 'bl0', max_size)
+        except ValueError:
+            if self._accept_invalid:
+                return None
+            raise
+
+    def _check_manifest(self, data: bytes, kind: str, max_size: int) \
+            -> RuntimeDescriptor:
+        if len(data) > max_size:
+            raise ValueError(f'{kind} too large')
+        mfmt = ''.join(self.MANIFEST_FORMAT.values())
+        slen = scalc(mfmt)
+        if len(data) <= slen:
+            raise ValueError(f'{kind} too short')
+        manifest = dict(zip(self.MANIFEST_FORMAT,
+                            sunpack(f'<{mfmt}', data[:slen])))
+        self._log_manifest(manifest)
+        if (manifest['manifest_version_major'] not in
+                (self.MANIFEST_VERSION_MAJOR1, self.MANIFEST_VERSION_MAJOR2)
+            or manifest['manifest_version_minor'] !=
+                self.MANIFEST_VERSION_MINOR1):
+            raise ValueError('Unsupported manifest version')
+        self._log.info('%s code start 0x%05x, end 0x%05x, exec 0x%05x',
+                       kind, manifest['code_start'], manifest['code_end'],
+                       manifest['entry_point'])
+        if manifest['identifier'] != self.IDENTIFIERS[kind]:
+            if manifest['identifier'] != self.IDENTIFIERS[None]:
+                manifest_str = hexlify(manifest["identifier"]).decode().upper()
+                raise ValueError(f'Specified file is not a {kind} file: '
+                                 f'{manifest_str}')
+            self._log.warning('Empty %s manifest, cannot verify', kind)
+        return RuntimeDescriptor(manifest['code_start'], manifest['code_end'],
+                                 manifest['length'], manifest['entry_point'])
+
+    @classmethod
+    def _check_manifest_size(cls):
+        slen = scalc(''.join(cls.MANIFEST_FORMAT.values()))
+        assert cls.MANIFEST_SIZE == slen, 'Invalid Manifest size'
+
+    def _log_manifest(self, manifest):
+        for item, value in manifest.items():
+            if isinstance(value, int):
+                self._log.debug('%s: 0x%08x', item, value)
+            elif isinstance(value, bytes):
+                self._log.debug('%s: (%d) %s', item, len(value),
+                                hexlify(value).decode())
+            else:
+                self._log.debug('%s: (%d) %s', item, len(value), value)
diff --git a/python/qemu/ot/gpio/__init__.py b/python/qemu/ot/gpio/__init__.py
new file mode 100644
index 0000000000000..cc1567184041d
--- /dev/null
+++ b/python/qemu/ot/gpio/__init__.py
@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Rivos, Inc.
+# All rights reserved.
+
+"""GPIO utilities.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
diff --git a/python/qemu/ot/gpio/device.py b/python/qemu/ot/gpio/device.py
new file mode 100644
index 0000000000000..6793531671a70
--- /dev/null
+++ b/python/qemu/ot/gpio/device.py
@@ -0,0 +1,262 @@
+# Copyright (c) 2024 Rivos, Inc.
+# All rights reserved.
+
+"""GPIO device tiny simulator.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from logging import getLogger
+from socket import create_server, socket, SHUT_RDWR
+from time import sleep
+from typing import Optional, TextIO
+import re
+
+
+# pylint: disable-msg=missing-function-docstring,missing-class-docstring
+
+class GpioChecker:
+
+    CHK_RE = r'^\s*(\d+)?\s*([@]):([0-9a-fA-F]{8})$'
+    """Handler either log file or `uniq -c` post-processed file."""
+
+    def __init__(self):
+        self._log = getLogger('gpio.check')
+        self._seq = []
+
+    def load(self, lfp: TextIO) -> None:
+        commands = ''.join(GpioDevice.INPUT_CMD_MAP.keys())
+        chk_re = self.CHK_RE.replace('@', commands)
+        error = 0
+        for lno, line in enumerate(lfp, start=1):
+            line = line.strip()
+            cmo = re.match(chk_re, line)
+            if not cmo:
+                self._log.error('Unknown check line @ %d: %s', lno, line)
+                error += 1
+                continue
+            repeat, command, value = cmo.groups()
+            irepeat = int(repeat) if repeat else 1
+            ivalue = int(value, 16)
+            while irepeat:
+                self._seq.append((command, ivalue))
+                irepeat -= 1
+        if error:
+            raise RuntimeError('Cannot use checker file {lfp.name}')
+
+    class Iterator:
+
+        def __init__(self, parent: 'GpioChecker'):
+            self._log = getLogger('gpio.dev.it')
+            self._iter = enumerate(parent._seq)
+            self._len = len(parent._seq)
+            self._pos = 0
+
+        def __iter__(self):
+            return self
+
+        def __next__(self) -> tuple[str, int]:
+            self._pos, value = next(self._iter)
+            return value
+
+        @property
+        def last(self) -> bool:
+            self._log.debug("pos: %d len: %d", self._pos, self._len)
+            return self._pos + 1 >= self._len
+
+    def __iter__(self) -> Iterator:
+        return self.Iterator(self)
+
+
+class GpioDevice:
+
+    INPUT_CMD_MAP = {
+        'C': 'clear',
+        'D': 'direction',
+        'O': 'output',
+        'P': 'pull',
+        'Q': 'query',
+        'Y': 'ynput',
+        'Z': 'hi_z',
+    }
+
+    OUTPUT_CMD_MAP = {
+        'input': 'I',
+        'mask': 'M',
+        'repeat': 'R',
+    }
+
+    def __init__(self):
+        self._log = getLogger('gpio.dev')
+        self._socket = None
+        self._checker: Optional[TextIO] = None
+        self._resume = False
+        self._oe = 0  # output enable (1: out, 0: in)
+        self._out = 0  # output value (from peer)
+        self._hiz = 0xffff_ffff  # high-Z
+        self._wpud = 0  # weak pull (1: up 0: down)
+        self._inact = 0xffff_ffff  # input activated
+        self._in = 0  # input value (to peer)
+        self._yn = 0  # mirror input value handled by QEMU
+        self._error_count = 0
+        self._record = []
+
+    def load(self, lfp: TextIO) -> None:
+        self._checker = GpioChecker()
+        self._checker.load(lfp)
+
+    def save(self, sfp: TextIO) -> None:
+        for cmd, value in self._record:
+            print(f'{cmd}:{value:08x}', end='\r\n', file=sfp)
+        sfp.close()
+
+    def run(self, port: int, single_run: bool, fatal: bool,
+            end: Optional[int]) -> bool:
+        self._socket = create_server(('localhost', port), reuse_port=True)
+        fail = False
+        self._socket.listen(0)
+        while True:
+            resume = True
+            peer, addr = self._socket.accept()
+            with peer:
+                self._log.info('Connection from %s:%d', *addr)
+                # rewind on each connection
+                it_cmd = iter(self._checker) if self._checker else None
+                self._error_count = 0
+                buf = bytearray()
+                while resume:
+                    if end is not None:
+                        if it_cmd and it_cmd.last:
+                            self._terminate(peer, end)
+                            resume = False
+                            break
+                    data = peer.recv(1024)
+                    if not data:
+                        break
+                    buf.extend(data)
+                    try:
+                        buf = self._process(peer, it_cmd, buf)
+                    except ValueError:
+                        fail = True
+                        resume = False
+                        break
+            try:
+                self._log.info('Disconnect from %s:%d', *addr)
+                peer.close()
+                peer.shutdown(SHUT_RDWR)
+            except OSError:
+                pass
+            if single_run:
+                break
+            if fail and fatal:
+                break
+        try:
+            self._socket.close()
+            self._socket.shutdown(SHUT_RDWR)
+        except OSError:
+            pass
+        self._socket = None
+        return not fail
+
+    def _process(self, peer: socket, it_cmd: Optional[GpioChecker.Iterator],
+                 buf: bytearray) -> bytearray:
+        while True:
+            eol = buf.find(b'\n')
+            if eol < 0:
+                return buf
+            line, buf = buf[:eol], buf[eol+1:]
+            line = line.strip()
+            sline = line.decode('utf8')
+            self._log.debug('in %s', sline)
+            resp = self._inject(sline, it_cmd)
+            if resp is not None:
+                for oline in resp.split('\n'):
+                    if oline:
+                        self._log.info('send %s', oline.strip())
+                out = resp.encode('utf8')
+                peer.send(out)
+
+    def _terminate(self, peer: socket, end: int) -> None:
+        resp = self._build_reply(mask=~end, input=end)
+        for oline in resp.split('\n'):
+            if oline:
+                self._log.info('send %s', oline.strip())
+        out = resp.encode('utf8')
+        peer.send(out)
+        sleep(0.1)
+
+    def _inject(self, line: str, it_cmd: Optional[GpioChecker.Iterator]) -> \
+            Optional[str]:
+        try:
+            cmd, value = line.split(':', 1)
+        except ValueError:
+            self._log.error('Unsupported line: %s', line)
+            return None
+        try:
+            word = int(value, 16)
+        except ValueError:
+            self._log.error('Unsupported value: %s', value)
+            return None
+        try:
+            command = self.INPUT_CMD_MAP[cmd]
+        except KeyError:
+            self._log.error('Unsupported command: %s', cmd)
+            return None
+        handler = getattr(self, f'_inject_{command}', None)
+        if handler is None:
+            self._log.warning('Unimplemented handler for %s', command)
+            return None
+        self._log.info('recv %s: 0x%08x', command, word)
+        self._record.append((cmd, word))
+        # pylint: disable=not-callable
+        out = handler(word)
+        if it_cmd:
+            try:
+                refcmd, refword = next(it_cmd)
+            except StopIteration as exc:
+                self._log.warning('End of checker')
+                raise ValueError('Unexpected command') from exc
+            self._log.debug('ck %c:%08x', refcmd, refword)
+            if cmd != refcmd:
+                self._log.error('Received command %s differs from expected %s',
+                                cmd, refcmd)
+                raise ValueError('Command mismatch')
+            if word != refword:
+                self._log.error('Received word 0x%08x differs from expected '
+                                '0x%08x', word, refword)
+                raise ValueError('Value mismatch')
+        return out
+
+    def _inject_clear(self, _) -> None:
+        self._oe = 0
+        self._out = 0
+        self._hiz = 0xfffffff
+        self._wpud = 0
+        self._inact = 0
+        self._in = 0
+
+    def _inject_output(self, value) -> None:
+        self._out = value
+
+    def _inject_direction(self, value) -> None:
+        self._oe = value
+
+    def _inject_pull(self, value) -> None:
+        self._wpud = value
+
+    def _inject_query(self, _) -> str:
+        return self._build_reply(mask=self._inact, input=self._in)
+
+    def _inject_hi_z(self, value) -> None:
+        self._hiz = value
+
+    def _inject_ynput(self, value) -> None:
+        self._yn = value
+
+    @classmethod
+    def _build_reply(cls, **kwargs) -> str:
+        lines = []
+        for cmd, value in kwargs.items():
+            value &= (1 << 32) - 1
+            lines.append(f'{cls.OUTPUT_CMD_MAP[cmd]}:{value:08x}\r\n')
+        return ''.join(lines)
diff --git a/python/qemu/ot/gpio/proxy.py b/python/qemu/ot/gpio/proxy.py
new file mode 100644
index 0000000000000..a69b38015158d
--- /dev/null
+++ b/python/qemu/ot/gpio/proxy.py
@@ -0,0 +1,212 @@
+# Copyright (c) 2024 Rivos, Inc.
+# All rights reserved.
+
+"""GPIO proxy.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from enum import IntEnum
+from logging import getLogger
+from select import POLLIN, poll as spoll
+from socket import (IPPROTO_TCP, TCP_NODELAY, SHUT_RDWR, socket)
+from time import time as now
+from typing import Optional
+
+
+class GpioProxy:
+    """Simple GPIO proxy using the QEMU OT GPIO protocol."""
+
+    DEFAULT_PORT = 8007
+    """Default GPIO TCP port."""
+
+    INPUT_CMD_MAP = {
+        'C': 'clear',
+        'D': 'direction',
+        'O': 'output',
+        'P': 'pull',
+        'Q': 'query',
+        'Y': 'ynput',
+        'Z': 'hi_z',
+    }
+
+    OUTPUT_CMD_MAP = {
+        'input': 'I',
+        'mask': 'M',
+        'repeat': 'R',
+    }
+
+    TIMEOUT = 1.0
+    """Default allowed timeout to complete an exchange with the remote target.
+    """
+
+    POLL_TIMEOUT = 0.05
+    """Maximum time to wait on a blocking operation.
+    """
+
+    def __init__(self, sock: socket):
+        self._log = getLogger('gpio.proxy')
+        self._socket = sock
+        self._socket.settimeout(None)
+        self._socket.setsockopt(IPPROTO_TCP, TCP_NODELAY, 1)
+        self._out: Optional[int] = None
+        self._last_out: Optional[int] = None
+        self._yn: Optional[int] = None
+        self._last_yn: Optional[int] = None
+        self._in = 0
+        self._dir = 0
+        self._pull = 0
+        self._hiz = 0
+        self._buf: bytearray()
+        self._timestamps: dict[str, float] = {}
+
+    def quit(self) -> None:
+        """Close the communication socket."""
+        if self._socket:
+            self._socket.shutdown(SHUT_RDWR)
+            self._socket.close()
+            self._socket = None
+
+    def sync(self) -> None:
+        """Request current status from QEMU."""
+        self._receive()
+        self._write('repeat', 0)
+
+    def gpio_out(self, force: bool = False) -> int:
+        """Retrieve the output value of the 32-bit GPIO lines."""
+        self._receive()
+        if self._out is None or force:
+            self._write('R', 0)
+            start = now()
+            timeout = start + self.TIMEOUT
+            while now() < timeout:
+                update = self._timestamps.get('output', 0.0)
+                if update > start:
+                    break
+            else:
+                raise TimeoutError('No answer from remote')
+        return self._out
+
+    def get_updated_out(self, gpio_def: type[IntEnum]) -> dict[IntEnum, bool]:
+        """Get GPIO changes since last call."""
+        out = self.gpio_out()
+        if self._last_out is None:
+            changes = ~0
+        else:
+            changes = self._last_out ^ out
+        if not changes:
+            return {}
+        gpio_changes = {}
+        for gpio in gpio_def:
+            bit = gpio.value
+            if changes & (1 << bit):
+                gpio_changes[gpio.name] = bool((out >> bit) & 1)
+        self._last_out = out
+        return gpio_changes
+
+    def gpio_mirrored_in(self, force: bool = False) -> int:
+        """Retrieve the mirrored values of the 32-bit GPIO lines."""
+        self._receive()
+        if self._yn is None or force:
+            self._write('R', 0)
+            start = now()
+            timeout = start + self.TIMEOUT
+            while now() < timeout:
+                update = self._timestamps.get('ynput', 0.0)
+                if update > start:
+                    break
+            else:
+                raise TimeoutError('No answer from remote')
+        return self._yn
+
+    def get_updated_mirrored_in(self, gpio_def: type[IntEnum]) -> \
+            dict[IntEnum, bool]:
+        """Get GPIO input changes since last call."""
+        m_in = self.gpio_mirrored_in()
+        if self._last_yn is None:
+            changes = ~0
+        else:
+            changes = self._last_yn ^ m_in
+        if not changes:
+            return {}
+        gpio_changes = {}
+        for gpio in gpio_def:
+            bit = gpio.value
+            if changes & (1 << bit):
+                gpio_changes[gpio.name] = bool((m_in >> bit) & 1)
+        self._last_yn = m_in
+        return gpio_changes
+
+    def _write(self, command: str, value: int) -> None:
+        if not isinstance(command, str):
+            raise ValueError("Invalid command {command}'")
+        if len(command) > 1:
+            command = self.OUTPUT_CMD_MAP.get(command.lower())
+        if command not in self.OUTPUT_CMD_MAP.values():
+            raise ValueError("Invalid command {command}'")
+        if not 0 <= value < (1 << 32):
+            raise ValueError("Invalid value: 0x{value:08x}")
+        req = f'{command}:{value:08x}\r\n'.encode()
+        self._log.debug('TX %s', req.decode().rstrip())
+        self._socket.send(req)
+
+    def _receive(self) -> None:
+        buf = bytearray()
+        poller = spoll()
+        poller.register(self._socket, POLLIN)
+        for _ in poller.poll(self.POLL_TIMEOUT):
+            data = self._socket.recv(1024)
+            buf.extend(data)
+        while buf:
+            pos = buf.find(b'\n')
+            if pos < 0:
+                break
+            chunk, buf = buf[:pos], buf[pos+1:]
+            if pos != 11:
+                self._log.error("Find truncated GPIO packet: '%s'", chunk)
+                continue
+            tchunk = chunk.strip().decode()
+            cmd, sep, tval = tchunk[0], tchunk[1], tchunk[2:]
+            if cmd not in self.INPUT_CMD_MAP:
+                self._log.error("Unknown received command: {%s}", cmd)
+                continue
+            if sep != ':':
+                self._log.error("Unknown received separator: {%s}", sep)
+                continue
+            command = self.INPUT_CMD_MAP[cmd]
+            rcvfn = getattr(self, f'_receive_{command}', None)
+            if not rcvfn or not callable(rcvfn):
+                raise RuntimeError(f"Invalid/missing handler for '{command}'")
+            value = int(tval, 16)
+            if not 0 <= value < (1 << 32):
+                raise ValueError(f"Invalid value: 0x{value:08x}")
+            self._log.debug('RX %s %08x', command.rstrip(), value)
+            # pylint: disable=not-callable
+            rcvfn(value)
+            self._timestamps[command] = now()
+
+    def _receive_clear(self, _: int) -> None:
+        self._in = 0
+        self._yn = None
+        self._last_yn = None
+        self._dir = 0
+        self._pull = 0
+        self._hiz = 0
+
+    def _receive_direction(self, value: int) -> None:
+        self._dir = value
+
+    def _receive_ynput(self, value: int) -> None:
+        self._yn = value
+
+    def _receive_output(self, value: int) -> None:
+        self._out = value
+
+    def _receive_pull(self, value: int) -> None:
+        self._pull = value
+
+    def _receive_query(self, _: int) -> None:
+        self._write('input', self._in)
+
+    def _receive_hi_z(self, value: int) -> None:
+        self._hiz = value
diff --git a/python/qemu/ot/km/__init__.py b/python/qemu/ot/km/__init__.py
new file mode 100644
index 0000000000000..28bf2ac2c3547
--- /dev/null
+++ b/python/qemu/ot/km/__init__.py
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""KeyManager tools."""
+
+from .dpe import KeyManagerDpe  # noqa: F401
diff --git a/python/qemu/ot/km/dpe.py b/python/qemu/ot/km/dpe.py
new file mode 100644
index 0000000000000..23e4f097dab53
--- /dev/null
+++ b/python/qemu/ot/km/dpe.py
@@ -0,0 +1,408 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU OT tool to generate Key Manager DPE keys.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import Namespace
+from binascii import unhexlify
+from configparser import RawConfigParser
+from io import BufferedReader
+from logging import getLogger
+from os.path import dirname, join as joinpath, normpath
+from textwrap import fill
+from typing import BinaryIO, Optional, TextIO
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ..otp import OtpImage, OtpLifecycleExtension, OtpMap
+from ..rom.image import ROMImage
+from ..util.arg import ArgError
+
+# ruff: noqa: E402
+_CRYPTO_EXC: Optional[Exception] = None
+try:
+    from Crypto.Hash import KMAC256
+except ModuleNotFoundError:
+    try:
+        # see pip3 install -r requirements.txt
+        from Cryptodome.Hash import KMAC256
+    except ModuleNotFoundError as exc:
+        _CRYPTO_EXC = exc
+
+
+class KeyManagerDpe:
+    """Key Manager DPE.
+    """
+
+    SLOT_COUNT = 4
+    ADVANCE_DATA_WIDTH = 208
+    GENERATE_DATA_WIDTH = 100
+    SW_BINDINGS_WIDTH = 32  # 256 bits
+    SALT_WIDTH = 32  # 256 bits
+    KMAC_LEN = 48  # 384 bits
+
+    OUTPUTS = ('HW', 'SW')
+    TARGETS = ('AES', 'KMAC', 'OTBN', 'NONE')
+
+    def __init__(self, otp_img: OtpImage, rom_count: int):
+        if _CRYPTO_EXC:
+            raise _CRYPTO_EXC
+        self._log = getLogger('keymgr')
+        self._otp_img = otp_img
+        self._roms = [ROMImage(x) for x in range(rom_count)]
+        self._config = RawConfigParser()
+        self._step: int = 0
+        self._command: str = ''
+        self._slots: list[bytes] = [b'' for _ in range(self.SLOT_COUNT)]
+        self._lc_ctrl_km_divs: dict[str, bytes] = {}
+        self._seeds: dict[str, bytes] = {}
+
+    @classmethod
+    def from_args(cls, args: Namespace) -> 'KeyManagerDpe':
+        """Generate a key based on the provided arguments
+
+           :param args: ArgumentPaser argument
+           :return KeyManagerDpe: KeyManagerDpe instance
+        """
+        swbindings = []
+        if not args.swbindings:
+            raise ArgError('Missing SW bindings for advance')
+        for sval in reversed(args.swbindings):
+            if len(sval) & 1:
+                sval = f'0{sval}'
+            try:
+                val = unhexlify(sval)
+            except ValueError as exc:
+                raise ArgError(f'Invalid SW binding: {sval}: {exc}') from exc
+            if len(val) > cls.SW_BINDINGS_WIDTH:
+                raise ArgError('Invalid SW bindings length')
+            swbindings.append(val)
+        # first step needs no bindings
+        swbindings.append(None)
+
+        ssalt = args.salt
+        if len(ssalt) & 1:
+            ssalt = f'0{ssalt}'
+        try:
+            salt = unhexlify(ssalt)
+        except ValueError as exc:
+            raise ArgError(f'Invalid SW binding: {ssalt}: {exc}') from exc
+
+        salt_len = len(salt)
+        if salt_len > cls.SALT_WIDTH:
+            raise ArgError('Invalid salt length')
+
+        if not 0 <= args.key_version < 1 << 32:
+            raise ArgError('Invalid key version value')
+
+        kmd = cls.create(args.otp_map, args.ecc, args.vmem, args.raw,
+                         args.lifecycle, args.config, args.rom, args.rom_size)
+
+        # if swbindings is not empty, use advance mode
+        while swbindings:
+            swb = swbindings.pop()
+            kmd.advance(0, 0, swb)
+
+        res = kmd.generate(0, args.target, args.gen_out, salt, args.key_version)
+
+        if args.rust_const:
+            const_name = args.rust_const.upper()
+            res_array = ', '.join((f'0x{v:02x}' for v in res))
+            res_array = fill(res_array, width=100,
+                             initial_indent='    ', subsequent_indent='    ')
+            outstr = (f'const {const_name}: [u8; {len(res)}] = '
+                      f'[\n{res_array}\n];')
+        else:
+            outstr = kmd.hexstr(res)
+
+        if args.output:
+            mode = 'at' if args.rust_const else 'wt'
+            with open(args.output, mode) as ofp:
+                print(outstr, file=ofp)
+        else:
+            print(outstr)
+
+        return kmd
+
+    @classmethod
+    def create(cls, otpmap: BinaryIO, ecc: int, vmem: Optional[BinaryIO],
+               raw: Optional[BinaryIO], lifecycle: TextIO, config: TextIO,
+               roms: list[ROMImage], rom_sizes: list[int]) -> 'KeyManagerDpe':
+        """Create a KeyManagerDpe instance from dependencies."""
+        otp_map = OtpMap()
+        otp_map.load(otpmap)
+        otpmap.close()
+
+        otp_img = OtpImage(ecc)
+        if vmem:
+            otp_img.load_vmem(vmem, 'otp')
+            vmem.close()
+        elif raw:
+            otp_img.load_raw(raw)
+            raw.close()
+        otp_img.dispatch(otp_map)
+
+        lcext = OtpLifecycleExtension()
+        lcext.load(lifecycle)
+        otp_img.load_lifecycle(lcext)
+        lifecycle.close()
+
+        kmd = cls(otp_img, len(roms))
+
+        kmd.load_config(config)
+        config.close()
+
+        if len(rom_sizes) < len(roms):
+            rom_sizes.extend([None] * (len(roms) - len(rom_sizes)))
+        for rom, (rfp, rom_size) in enumerate(zip(roms, rom_sizes)):
+            kmd.load_rom(rom, rfp, rom_size)
+            rfp.close()
+
+        return kmd
+
+    def load_config(self, config_file: TextIO) -> None:
+        """Load QEMU 'readconfig' file.
+
+           :param config_file: the config file text stream
+        """
+        self._config.read_file(config_file)
+        loaded: set[str] = set()
+        for section in self._config.sections():
+            prefix = 'ot_device '
+            if not section.startswith(prefix):
+                continue
+            devname = section.removeprefix(prefix).strip(' "')
+            devdescs = devname.split('.')
+            devtype = devdescs[0]
+            if devtype == 'ot-lc_ctrl' and devtype not in loaded:
+                loaded.add(devtype)
+                for opt in 'invalid production test_unlocked dev rma'.split():
+                    sval = self._config.get(section, opt)
+                    if not sval:
+                        raise ValueError(f'Unable to load {opt} LC KM div')
+                    sval = sval.strip('"')
+                    val = unhexlify(sval)
+                    # TODO: check why we need to reverse the div
+                    val = bytes(reversed(val))
+                    self._lc_ctrl_km_divs[opt] = val
+                continue
+            if devtype == 'ot-keymgr_dpe' and devtype not in loaded:
+                loaded.add(devtype)
+                for opt in self._config.options(section):
+                    sval = self._config.get(section, opt).strip('"')
+                    seed_name = opt.replace('_seed', '')
+                    val = unhexlify(sval)
+                    # TODO: check why we need to reverse the seeds
+                    val = bytes(reversed(val))
+                    self._seeds[seed_name] = val
+                continue
+            if devtype == 'ot-rom_ctrl':
+                devinst = devdescs[-1]
+                devload = f'{devtype}.{devinst}'
+                if devload in loaded:
+                    continue
+                loaded.add(devload)
+                prefix = 'rom'
+                if not devinst.startswith(prefix):
+                    raise ValueError(f'Invalid ROM instance name: {devinst}')
+                devidx = int(devinst.removeprefix(prefix))
+                try:
+                    rom_img = self._roms[devidx]
+                except IndexError:
+                    self._log.warning('No ROM image loaded for device %s',
+                                      devinst)
+                    continue
+                for opt in self._config.options(section):
+                    val = self._config.get(section, opt).strip('"')
+                    setattr(rom_img, opt, unhexlify(val))
+                continue
+
+    def load_rom(self, rom_idx: int, rfp: BufferedReader,
+                 size: Optional[int] = None) -> None:
+        """Load QEMU 'readconfig' file.
+
+           :param rom_idx: the ROM index
+           :param rfp: the ROM data stream
+           :param size: the size of the ROM image
+        """
+        rom_img = self._roms[rom_idx]
+        rom_img.load(rfp, size)
+
+    def initialize(self, dst: int):
+        """Initialize the KeyManager DPE statemachine.
+
+           :param dst: the destination slot index
+        """
+        return self.advance(0, dst)
+
+    def advance(self, src: int, dst: int, swbindings: Optional[bytes] = None):
+        """Advance the KeyManager DPE statemachine to the next step.
+
+           :param src: the source slot index
+           :param dst: the destination slot index
+           :param swbindings: the software bindings for the current step
+        """
+        assert 0 <= src < self.SLOT_COUNT, f'Invalid source slot {src}'
+        assert 0 <= dst < self.SLOT_COUNT, f'Invalid destination slot {dst}'
+        try:
+            advfn = getattr(self, f'_advance_{self._step}')
+        except AttributeError:
+            self._log.error('Unknown advance step %s', self._step)
+            raise
+        exp_swbindings = self._step not in (0,)
+        if exp_swbindings:
+            if swbindings is None:
+                raise ValueError(f'Missing SW bindings for step {self._step}')
+            swb_len = len(swbindings)
+            if swb_len < self.SW_BINDINGS_WIDTH:
+                swbindings = b''.join((swbindings,
+                                       bytes(self.SW_BINDINGS_WIDTH - swb_len)))
+        if not exp_swbindings and swbindings is not None:
+            raise ValueError(f'Unexpected SW bindings for step {self._step}')
+        self._log.debug('Advance #%d', self._step)
+        self._slots[dst] = advfn(src, swbindings)
+        if self._step < 3:
+            self._step += 1
+        return self._slots[dst]
+
+    def generate(self, src: int, target: str, output: Optional[str],
+                 salt: bytes, key_version: int) -> bytes:
+        """Generate an output key.
+
+           :param src: the source slot index
+           :param target: the target device for the key.
+           :param output: the type of output key to generate.
+           :param salt: the salt to use for the key generation.
+           :param key_version: the version of the key to generate.
+           :return: the generated key.
+        """
+        assert 0 <= src < self.SLOT_COUNT, f'Invalid source slot {src}'
+        if not output:
+            output = 'SW' if target == 'NONE' else 'HW'
+        outmap = {'SW': 'soft', 'HW': 'hard'}
+        output_seed = self._seeds[f'{outmap[output]}_output']
+        self._log.debug('Output Key Seed: %s', self.bnstr(output_seed))
+        dest = 'NONE' if target == 'SW' else target
+        dest_seed = self._seeds[dest.lower()]
+        self._log.debug('Destination Seed: %s', self.bnstr(dest_seed))
+        salt_len = len(salt)
+        if salt_len < self.SALT_WIDTH:
+            salt = b''.join((salt, bytes(self.SALT_WIDTH - salt_len)))
+        self._log.debug('Salt: %s', self.bnstr(salt))
+        key_ver = key_version.to_bytes(4, 'little')
+        self._log.debug('Key Version: %s', self.bnstr(key_ver))
+        buf_parts = [
+            output_seed,
+            dest_seed,
+            salt,
+            key_ver,
+        ]
+        resp = self._kmac_generate(src, buf_parts)
+        return resp
+
+    @classmethod
+    def bnstr(cls, data: bytes) -> str:
+        """Convert a byte array to a big-endian hex string."""
+        return bytes(reversed(data)).hex()
+
+    @classmethod
+    def hexstr(cls, data: bytes) -> str:
+        """Convert a byte array to a hex string."""
+        return data.hex()
+
+    def _advance_0(self, *_) -> bytes:
+        share0 = self._otp_img.get_field('SECRET2', 'CREATOR_ROOT_KEY_SHARE0')
+        share1 = self._otp_img.get_field('SECRET2', 'CREATOR_ROOT_KEY_SHARE1')
+        self._log.debug('Creator Root Key share 0: %s', self.bnstr(share0))
+        self._log.debug('Creator Root Key share 1: %s', self.bnstr(share1))
+        return bytes((s0 ^ s1 for s0, s1 in zip(share0, share1)))
+
+    def _advance_1(self, src: int, swbindings: bytes) -> bytes:
+        if len(self._roms) < 2:
+            raise ValueError('Missing ROM')
+        creator_seed = self._otp_img.get_field('SECRET2', 'CREATOR_SEED')
+        self._log.debug('Creator Seed: %s', self.bnstr(creator_seed))
+        rom0_digest = self._roms[0].digest
+        rom1_digest = self._roms[1].digest
+        self._log.debug('ROM0 digest: %s', self.bnstr(rom0_digest))
+        self._log.debug('ROM1 digest: %s', self.bnstr(rom1_digest))
+        lc_div = self._get_lc_div()
+        lc_ctrl_km_div = self._lc_ctrl_km_divs[lc_div]
+        self._log.debug('KeyManager div: %s', self.hexstr(lc_ctrl_km_div))
+        device_id = self._otp_img.get_field('HW_CFG0', 'DEVICE_ID')
+        self._log.debug('Device ID: %s', self.bnstr(device_id))
+        revision_seed = self._seeds['revision']
+        self._log.debug('Revision Seed: %s', self.bnstr(revision_seed))
+        self._log.debug('Software Binding: %s', self.hexstr(swbindings))
+        buf_parts = [
+            creator_seed,
+            self._roms[0].digest,
+            self._roms[1].digest,
+            lc_ctrl_km_div,
+            device_id,
+            revision_seed,
+            swbindings
+        ]
+        resp = self._kmac_advance(src, buf_parts)
+        return resp
+
+    def _advance_2(self, src: int, swbindings: bytes):
+        owner_seed = self._otp_img.get_field('SECRET3', 'OWNER_SEED')
+        self._log.debug('Owner Seed: %s', self.bnstr(owner_seed))
+        self._log.debug('Software Binding: %s', self.hexstr(swbindings))
+        buf_parts = [
+            owner_seed,
+            swbindings
+        ]
+        resp = self._kmac_advance(src, buf_parts)
+        return resp
+
+    def _advance_3(self, src: int, swbindings: bytes):
+        self._log.debug('Software Binding: %s', self.hexstr(swbindings))
+        resp = self._kmac_advance(src, [swbindings])
+        return resp
+
+    def _kmac_advance(self, src: int, buffers: list[bytes]) -> bytes:
+        return self._kmac(src, buffers, self.ADVANCE_DATA_WIDTH)
+
+    def _kmac_generate(self, src: int, buffers: list[bytes]) -> bytes:
+        return self._kmac(src, buffers, self.GENERATE_DATA_WIDTH)
+
+    def _kmac(self, src: int, buffers: list[bytes], data_width: int) -> bytes:
+        buffer = bytearray()
+        for buf in buffers:
+            buffer.extend(buf)
+        buflen = len(buffer)
+        assert buflen <= data_width, \
+            f'Invalid data width: {buflen}'
+        if buflen < data_width:
+            buffer.extend(bytes(data_width - buflen))
+        kmac_key = self._slots[src][:32]
+        self._log.debug('KMAC key: %s (%d)',
+                        self.bnstr(kmac_key), len(kmac_key))
+        kmac = KMAC256.new(key=kmac_key, mac_len=self.KMAC_LEN)
+        kmac.update(buffer)
+        resp = kmac.digest()
+        self._log.info('KMAC resp: %s (%d)', self.bnstr(resp), len(resp))
+        return resp
+
+    def _get_lc_div(self):
+        lc_part = self._otp_img.get_partition('LIFE_CYCLE')
+        lc_state = lc_part.decode_field('LC_STATE')
+        self._log.debug('LC state: %s', lc_state)
+        if lc_state.startswith('TESTUNLOCKED'):
+            return 'test_dev_rma'
+        if lc_state in ('DEV', 'RMA'):
+            return 'test_dev_rma'
+        if lc_state.startswith('PROD'):
+            return 'production'
+        return 'invalid'
diff --git a/python/qemu/ot/km/engine.py b/python/qemu/ot/km/engine.py
new file mode 100644
index 0000000000000..472aaedbc3c34
--- /dev/null
+++ b/python/qemu/ot/km/engine.py
@@ -0,0 +1,361 @@
+# Copyright (c) 2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU OT tool to verify Key Manager DPE test execution
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import unhexlify
+from collections.abc import Iterator
+from configparser import ConfigParser, NoOptionError
+from logging import getLogger
+from typing import BinaryIO, NamedTuple, Optional, TextIO, Union
+
+import re
+import sys
+
+from .dpe import KeyManagerDpe
+from ..util.misc import to_bool, HexInt
+
+# ruff: noqa: E402
+_CRYPTO_EXC: Optional[Exception] = None
+try:
+    from Crypto.Cipher import AES
+    from Crypto.Hash import KMAC256
+except ModuleNotFoundError:
+    try:
+        # see pip3 install -r requirements.txt
+        from Cryptodome.Cipher import AES
+        from Cryptodome.Hash import KMAC256
+    except ModuleNotFoundError as exc:
+        _CRYPTO_EXC = exc
+
+
+KeyManagerDpeStep = NamedTuple
+"""Key Manager DPE test step."""
+
+
+class KeyManagerDpeStepInitialize(KeyManagerDpeStep):
+    """Key Manager DPE test initialization step."""
+
+    dst: int
+    """Destination slot."""
+
+
+class KeyManagerDpeStepErase(KeyManagerDpeStep):
+    """Key Manager DPE test erase step."""
+
+    dst: int
+    """Destination slot."""
+
+
+class KeyManagerDpeStepAdvance(KeyManagerDpeStep):
+    """Key Manager DPE test advance step."""
+
+    src: int
+    """Source slot."""
+
+    dst: int
+    """Destination slot."""
+
+    max_key_version: int
+    """Maximum key version."""
+
+    binding: bytes
+    """Software bindings."""
+
+    allow_child: bool
+    """Whether this context allows derivation of further children."""
+
+    exportable: bool
+    """Whether the key for the target slot is exportable."""
+
+    reatin_parent: bool
+    """Whether further advance operations force erasure of the slot."""
+
+
+class KeyManagerDpeStepGenerate(KeyManagerDpeStep):
+    """Key Manager DPE test generate step"""
+
+    src: int
+    """Source slot."""
+
+    dst: str
+    """Destination device."""
+
+    output: Optional[str]
+    """Type of output."""
+
+    key_version: int
+    """Key version."""
+
+    salt: bytes
+    """Salt."""
+
+
+class KeyManagerDpeEngine:
+    """
+    Key Manager DPE test executer
+    """
+
+    ANSI_CRE = re.compile(r'(\x9B|\x1B\[)[0-?]*[ -\/]*[@-~]')
+    """Filter out ANSI escape sequences from input stream (colors, etc.)."""
+
+    LOG_CRE = re.compile(r'^(?:.*\s)?T>\s(.*)$')
+    """Lines of interest in the log file."""
+
+    def __init__(self, kmd: KeyManagerDpe):
+        self._log = getLogger('keymgr.eng')
+        self._kmd = kmd
+        self._steps: dict[str, KeyManagerDpeStep] = []
+        self._exp_results: dict[str, bytes] = {}
+
+    def execute(self, ifp: TextIO) -> None:
+        """Verify Key Manager DPE test execution
+
+           :param ifp: ini-style sequence definition stream
+        """
+        seq = ConfigParser()
+        seq.read_file(ifp)
+        self._steps = self._build_steps_from_seq(seq)
+        self._exp_results = self._execute_steps()
+
+    def verify(self, lfp: BinaryIO) -> None:
+        """Verify Key Manager DPE test execution
+
+           :param lfp: bianry log stream
+        """
+        exec_log = self._filter_log(lfp)
+        self._steps, results = self._build_steps_from_log(exec_log)
+        if not self._steps:
+            raise ValueError('No step found in log')
+        self._exp_results = self._execute_steps()
+        error_count = self._verify_results(results)
+        if error_count:
+            raise ValueError(f'{error_count} errors found')
+
+    def _filter_log(self, lfp: BinaryIO) -> Iterator[KeyManagerDpeStep]:
+        """Filter log stream
+
+           :param lfp: log stream
+        """
+        for line in lfp:
+            line = self.ANSI_CRE.sub('', line.decode(errors='ignore')).strip()
+            lmo = self.LOG_CRE.match(line)
+            if not lmo:
+                continue
+            yield lmo.group(1)
+
+    @classmethod
+    def _parse_bytes(cls, value: str) -> bytes:
+        """Parse bytes from string
+
+           :param value: string representation of bytes
+           :return: the parsed bytes
+        """
+        value = value.strip('"')
+        if value.startswith('[') and value.endswith(']'):
+            value = value[1:-1]
+            if len(value) & 1:
+                value = f'0{value}'
+            return unhexlify(value)
+        if value.startswith('0x'):
+            ivalue = int(value, 16)
+            return ivalue.to_bytes((ivalue.bit_length() + 7) // 8, 'big')
+        raise ValueError(f'invalid bytes: {value}')
+
+    def _build_steps_from_seq(self, seq: ConfigParser) -> \
+            dict[str, KeyManagerDpeStep]:
+        module = sys.modules[__name__]
+        steps: dict[str, KeyManagerDpeStep] = {}
+        for step in seq.sections():
+            if step in steps:
+                raise ValueError(f'Duplicate step: {step}')
+            mode = seq.get(step, 'mode')
+            try:
+                step_cls = getattr(module, f'KeyManagerDpeStep{mode.title()}')
+            except AttributeError as exc:
+                raise ValueError(f'Unknown mode: {mode}') from exc
+            attrs = []
+            for name, type_ in step_cls.__annotations__.items():
+                if type_ is bool:
+                    val = seq.getboolean(step, name, fallback=True)
+                elif type_ is int:
+                    val = seq.getint(step, name, fallback=None)
+                    if val is None:
+                        if name == 'max_key_version':
+                            val = (1 << 32) - 1
+                        else:
+                            raise ValueError(f'Step {step} is missing {name}')
+                elif type_ is str:
+                    val = seq.get(step, name, fallback=None)
+                    if val is None:
+                        raise ValueError(f'Step {step} is missing {name}')
+                elif type_ is Optional[str]:
+                    val = seq.get(step, name, fallback=None)
+                elif type_ is bytes:
+                    try:
+                        val = self._parse_bytes(seq.get(step, name))
+                    except (KeyError, NoOptionError) as exc:
+                        raise ValueError(f'Step {step} is missing attribute '
+                                         f"'{name}'") from exc
+                    except (AttributeError, ValueError) as exc:
+                        raise ValueError(f'Step {step}, invalid bytes for '
+                                         f'{name}: {exc}') from exc
+                else:
+                    raise ValueError(f'Step {step}, invalid type for {name}: '
+                                     f'{type_}')
+                if not isinstance(val, type_):
+                    raise TypeError(f'Step {step}, invalid type for {name}: '
+                                    f'{type(val)}, expected {type_}')
+                self._log.debug("Step %s: attr '%s': type '%s', val= %s",
+                                step, name, type_.__name__, val)
+                attrs.append(val)
+            kmd_step = step_cls(*attrs)
+            steps[step] = kmd_step
+        return steps
+
+    def _build_steps_from_log(self, itlog: Iterator[str]) -> \
+            tuple[dict[str, KeyManagerDpeStep], dict[str, bytes]]:
+        module = sys.modules[__name__]
+        steps: dict[str, KeyManagerDpeStep] = {}
+        results: dict[str, bytes] = {}
+        for step, values, result in self._enumerate_steps_from_log(itlog):
+            self._log.info('Parsing %s log', step)
+            if step in steps:
+                raise ValueError(f'Duplicate step: {step}')
+            try:
+                mode = values['mode']
+                step_cls = getattr(module, f'KeyManagerDpeStep{mode.title()}')
+            except KeyError as exc:
+                raise ValueError('Missing mode in result') from exc
+            except AttributeError as exc:
+                raise ValueError(f'Unknown mode: {mode}') from exc
+            attrs = []
+            for name, type_ in step_cls.__annotations__.items():
+                if type_ is bool:
+                    val = to_bool(values.get(name, True), permissive=False)
+                elif type_ is int:
+                    val = values.get(name, None)
+                    if val is None:
+                        if name == 'max_key_version':
+                            val = (1 << 32) - 1
+                        else:
+                            raise ValueError(f'Step {step} is missing {name}')
+                    else:
+                        val = HexInt.parse(val)
+                elif type_ is str:
+                    val = values.get(name, None)
+                    if val is None:
+                        raise ValueError(f'Step {step} is missing {name}')
+                elif type_ is Optional[str]:
+                    val = values.get(name, None)
+                elif type_ is bytes:
+                    try:
+                        val = self._parse_bytes(values[name])
+                    except (KeyError, ValueError) as exc:
+                        raise ValueError(f'Step {step}, invalid bytes for '
+                                         f'{name}: {exc}') from exc
+                else:
+                    raise ValueError(f'Step {step}, invalid type for {name}: '
+                                     f'{type_}')
+                if not isinstance(val, type_):
+                    raise TypeError(f'Step {step}, invalid type for {name}: '
+                                    f'{type(val)}, expected {type_}')
+                attrs.append(val)
+            kmd_step = step_cls(*attrs)
+            steps[step] = kmd_step
+            if result:
+                try:
+                    results[step] = val = self._parse_bytes(result)
+                except ValueError as exc:
+                    raise ValueError(f'Step {step}, '
+                                     f'invalid result bytes: {exc}') from exc
+            elif mode == 'generate':
+                raise RuntimeError(f'Step {step}, no result bytes provided')
+        return steps, results
+
+    def _enumerate_steps_from_log(self, itlog: Iterator[str]) -> \
+            Iterator[tuple[str, dict[str, Union[str, int, bytes, bool]],
+                           Optional[bytes]]]:
+        step = None
+        values: dict[str, Union[str, int, bytes, bool]] = {}
+        result: Optional[bytes] = None
+        for line in itlog:
+            smo = re.match(r'^\[(step_\d+)\]$', line)
+            if smo:
+                if step:
+                    yield step, values, result
+                    step = None
+                    values = {}
+                    result = None
+                step = smo.group(1)
+                continue
+            if not step:
+                raise ValueError('Parsing error')
+            attr, val = [x.strip() for x in line.split('=')]
+            if attr == 'output':
+                result = val
+            else:
+                values[attr] = val
+        if step:
+            yield step, values, result
+
+    def _execute_steps(self) -> dict[str, bytes]:
+        results: dict[str, bytes] = {}
+        prefix = 'KeyManagerDpeStep'
+        for name, step in self._steps.items():
+            self._log.info('Executing %s (%s: %s)', name,
+                           step.__class__.__name__.removeprefix(prefix),
+                           step.dst)
+            if isinstance(step, KeyManagerDpeStepInitialize):
+                res = self._kmd.initialize(step.dst)
+            elif isinstance(step, KeyManagerDpeStepErase):
+                res = self._kmd.erase(step.dst)
+            elif isinstance(step, KeyManagerDpeStepAdvance):
+                res = self._kmd.advance(step.src, step.dst, step.binding)
+            elif isinstance(step, KeyManagerDpeStepGenerate):
+                res = self._kmd.generate(step.src, step.dst, step.output,
+                                         step.salt, step.key_version)
+                res = self._retrieve_output(step.dst, res)
+                results[name] = res
+            else:
+                raise ValueError(f'Unknown step type: '
+                                 f'{step.__class__.__name__}')
+            self._log.debug('Result: %s', res.hex())
+        return results
+
+    def _verify_results(self, results: dict[str, bytes]) -> int:
+        error = 0
+        for name, step in self._steps.items():
+            if not isinstance(step, KeyManagerDpeStepGenerate):
+                continue
+            self._log.info('Verifying result for %s', name)
+            exp_result = self._exp_results[name]
+            result = results[name]
+            if result != exp_result:
+                self._log.error('Key mismatch for %s, %s != %s',
+                                name, result.hex(), exp_result.hex())
+                error += 1
+                continue
+            self._log.info('Key verified for %s, %s', name, result.hex())
+        return error
+
+    def _retrieve_output(self, output: str, key_: bytes) -> bytes:
+        if _CRYPTO_EXC:
+            raise _CRYPTO_EXC
+        output = output.lower()
+        self._log.debug('retrieve output %s', output)
+        if output == 'aes':
+            assert len(key_) >= 32, 'AES Key must be at least 32 bytes long'
+            aes = AES.new(key_[:32], AES.MODE_ECB)
+            return aes.encrypt(bytes(16))
+        if output == 'kmac':
+            kmac = KMAC256.new(key=key_[:32], mac_len=256//8)
+            kmac.update(bytes(4))
+            return kmac.digest()
+        if output == 'otbn':
+            return key_
+        raise ValueError(f'Invalid output type: {output}')
diff --git a/python/qemu/ot/lc_ctrl/__init__.py b/python/qemu/ot/lc_ctrl/__init__.py
new file mode 100644
index 0000000000000..bdcf1b69c330c
--- /dev/null
+++ b/python/qemu/ot/lc_ctrl/__init__.py
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""LifeCycle tools."""
+
+
+class LifeCycleError(RuntimeError):
+    """Life Cycle Error"""
diff --git a/python/qemu/ot/lc_ctrl/const.py b/python/qemu/ot/lc_ctrl/const.py
new file mode 100644
index 0000000000000..404bef8c3c986
--- /dev/null
+++ b/python/qemu/ot/lc_ctrl/const.py
@@ -0,0 +1,84 @@
+# Copyright (c) 2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Lifecycle helpers.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from copy import deepcopy
+from logging import getLogger
+from typing import TextIO
+
+from ot.otp.lifecycle import OtpLifecycle
+
+
+class LcCtrlConstants:
+    """Life Cycle constant manager.
+    """
+
+    def __init__(self):
+        self._log = getLogger('lc.const')
+        self._states: dict[str, tuple[str, str]] = {}
+        self._tokens: dict[str, str] = {}
+        self._diversifiers: dict[str, str] = {}
+
+    def load_sv(self, svp: TextIO) -> None:
+        """Decode LC information from a System Verilog file.
+
+           :param svp: System Verilog stream with OTP definitions.
+        """
+        lcext = OtpLifecycle()
+        lcext.load(svp)
+        states = lcext.get_configuration('LC_STATE')
+        if not states:
+            raise ValueError('Cannot obtain LifeCycle states')
+        for raw in {s for s in states if int(s, 16) == 0}:
+            del states[raw]
+        ostates = list(states)
+        self._states['lc_state'] = ostates[0], ostates[-1]
+        self._log.info("States first: '%s', last '%s'",
+                       states[ostates[0]], states[ostates[-1]])
+        trans = lcext.get_configuration('LC_TRANSITION_CNT')
+        if not trans:
+            raise ValueError('Cannot obtain LifeCycle transitions')
+        for raw in {s for s in trans if int(s, 16) == 0}:
+            del trans[raw]
+        otrans = list(trans)
+        self._states['lc_trscnt'] = otrans[0], otrans[-1]
+        self._log.info('Transitions first: %d, last %d',
+                       int(trans[otrans[0]]),
+                       int(trans[otrans[1]]))
+        self._tokens.update(lcext.get_tokens(False, False))
+        soc_dbg = lcext.get_configuration('SOC_DBG')
+        if soc_dbg:
+            for raw in {s for s in soc_dbg if int(s, 16) == 0}:
+                del soc_dbg[raw]
+            osoc = list(soc_dbg)
+            self._states['soc_dbg'] = osoc[0], osoc[-1]
+            self._log.info("Socdbg first: '%s', last '%s'",
+                           soc_dbg[osoc[0]], soc_dbg[osoc[-1]])
+        ownership = lcext.get_configuration('OWNERSHIP')
+        if ownership:
+            for raw in {s for s in ownership if int(s, 16) == 0}:
+                del ownership[raw]
+            osoc = list(ownership)
+            self._states['ownership'] = osoc[0], osoc[-1]
+            self._log.info("Ownership first: '%s', last '%s'",
+                           ownership[osoc[0]], ownership[osoc[1]])
+
+    @property
+    def states(self) -> dict[str, tuple[str, str]]:
+        """Return initial and final values for all known states.
+
+           :return: a state name indexed map with first and last states
+                    hex string values.
+        """
+        return deepcopy(self._states)
+
+    @property
+    def tokens(self) -> dict[str, str]:
+        """Return LC token values.
+        """
+        return deepcopy(self._tokens)
diff --git a/python/qemu/ot/lc_ctrl/lcdmi.py b/python/qemu/ot/lc_ctrl/lcdmi.py
new file mode 100644
index 0000000000000..b878d279b4276
--- /dev/null
+++ b/python/qemu/ot/lc_ctrl/lcdmi.py
@@ -0,0 +1,348 @@
+# Copyright (c) 2024 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""LifeCycle DMI.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import Error as BinasciiError, hexlify, unhexlify
+from logging import getLogger
+from struct import pack as spack, unpack as sunpack
+from typing import NamedTuple, Union
+
+from . import LifeCycleError
+from ..dtm import DebugTransportModule
+from ..util.mbb import MB8_TRUE, MB8_FALSE, MB8_MASK
+
+
+class HardwareRevision(NamedTuple):
+    """OpenTitan Hardware Revision."""
+    silicon_creator: int
+    product_id: int
+    revision_id: int
+
+
+class LifeCycleController:
+    """LifeCycle Controller over DMI."""
+
+    STATUS = """
+        initialized
+        ready
+        ext_clock_switched
+        transition_successful
+        transition_count_error
+        transition_error
+        token_error
+        flash_rma_error
+        otp_error
+        state_error
+        bus_integ_error
+        otp_partition_error
+    """.split()
+    """Status bits."""
+
+    STATES = """
+        RAW
+        TEST_UNLOCKED0
+        TEST_LOCKED0
+        TEST_UNLOCKED1
+        TEST_LOCKED1
+        TEST_UNLOCKED2
+        TEST_LOCKED2
+        TEST_UNLOCKED3
+        TEST_LOCKED3
+        TEST_UNLOCKED4
+        TEST_LOCKED4
+        TEST_UNLOCKED5
+        TEST_LOCKED5
+        TEST_UNLOCKED6
+        TEST_LOCKED6
+        TEST_UNLOCKED7
+        DEV
+        PROD
+        PROD_END
+        RMA
+        SCRAP
+    """.split()
+
+    REGS = {
+        'alert_test': 0, 'status': 1, 'claim_transition_if_regwen': 2,
+        'claim_transition_if': 3, 'transition_regwen': 4, 'transition_cmd': 5,
+        'transition_ctrl': 6, 'transition_token': 7, 'transition_target': 11,
+        'otp_vendor_test_ctrl': 12, 'otp_vendor_test_status': 13,
+        'lc_state': 14, 'lc_transition_cnt': 15, 'lc_id_state': 16,
+        'hw_revision': 17, 'device_id': 19, 'manuf_state': 27}
+    """Registers."""
+
+    ALERTS = 'prog_error state_error bus_integ_error'.split()
+    """Alerts."""
+
+    DEFAULT_DMI_ADDRESS = 0xc00
+    """Default DMI address of the controller."""
+
+    TOKEN_FORMAT = '<4I'
+
+    def __init__(self, dtm: DebugTransportModule, address: int):
+        self._log = getLogger('dtm.lcctrl')
+        self._dtm = dtm
+        self._dmi = dtm['dmi']
+        self._address = address
+        self._hw_rev_widths = (16, 16, 8)
+
+    def restart_system(self) -> None:
+        """Restart the remote machine."""
+        self._dtm.engine.controller.system_reset()
+
+    def set_alert_test(self, alert: str) -> None:
+        """Test alert."""
+        try:
+            alix = self.ALERTS.index(alert.lower())
+        except IndexError as exc:
+            raise ValueError(f'No such alert {alert}') from exc
+        self._write_reg('alert_test', 1 << alix)
+
+    @property
+    def status(self) -> dict[str, bool]:
+        """Retrieve the current status."""
+        value = self._read_reg('status')
+        status = {self.STATUS[b]: bool(value & (1 << b))
+                  for b in range(len(self.STATUS))}
+        return status
+
+    @property
+    def dtm(self) -> DebugTransportModule:
+        """Return the DTM"""
+        return self._dtm
+
+    def disable_claim_transition_if_regwen(self):
+        """Disable claim transition interface."""
+        self._write_reg('claim_transition_if_regwen', 0)
+
+    def claim_transition_if(self, claim: bool) -> bool:
+        """Clain transition interface.
+
+           :return: True of the interface has been successfully claimed for DMI.
+        """
+        reg = 'claim_transition_if'
+        self._log.debug('%s interface', 'Claim' if claim else 'Release')
+        if claim:
+            self._write_reg(reg, MB8_TRUE)
+            val = self._read_reg(reg) & MB8_MASK
+            success = val == MB8_TRUE
+            return success
+        self._write_reg(reg, MB8_FALSE)
+        val = self._read_reg(reg) & MB8_MASK
+        if val == MB8_TRUE:
+            raise LifeCycleError('Cannot release LC interface')
+        return val == MB8_FALSE
+
+    @property
+    def transition_regwen(self) -> bool:
+        """Tells whether transition registers can be written."""
+        regwen = bool(self._read_reg('transition_regwen') & 0x1)
+        self._log.debug('Transition regwen: %s', regwen)
+        return regwen
+
+    def transition_start(self) -> str:
+        """Start the transition operation."""
+        self._log.debug('Start transition')
+        self._write_reg('transition_cmd', 0b1)
+
+    @property
+    def volatile_raw_unlock(self) -> bool:
+        """Report whether volatile unlock is enabled."""
+        reg = 'transition_ctrl'
+        vru = bool(self._read_reg(reg) & 0b10)
+        return vru
+
+    @volatile_raw_unlock.setter
+    def volatile_raw_unlock(self, enable: bool) -> None:
+        """Enable or disable volatile unlock."""
+        reg = 'transition_ctrl'
+        value = self._read_reg(reg)
+        if enable:
+            value |= 0b10
+        else:
+            value &= ~0b10
+        self._write_reg(reg, value)
+
+    @property
+    def ext_clock_en(self) -> bool:
+        """Report whether external clock is selected."""
+        reg = 'transition_ctrl'
+        value = self._read_reg(reg)
+        value |= 0b1
+        self._write_reg(reg, value)
+
+    @ext_clock_en.setter
+    def ext_clock_en(self) -> None:
+        """Select external clock source."""
+
+    @property
+    def transition_token(self) -> bytes:
+        """Report current transition token."""
+        tokens = (self._read_reg('transition_token', pos) for pos in range(4))
+        token = spack(self.TOKEN_FORMAT, *tokens)
+        self._log.debug('Transition token: %s', hexlify(token).decode())
+        return token
+
+    @transition_token.setter
+    def transition_token(self,
+                         token: Union[bytes, bytearray, str, None]) -> None:
+        """Define the transition token as a 16-byte token.
+
+           :param token: if None, use an empty zeroed token,
+                         if provided as a string, it should be an hexadecimal
+                         value of 32 characters, otherwise it should be a
+                         16-byte sequence.
+        """
+        if isinstance(token, str):
+            try:
+                token = unhexlify(token)
+            except BinasciiError as exc:
+                raise ValueError('Invalid token string: {exc}') from exc
+        elif token is None:
+            token = bytes(16)
+        elif not isinstance(token, (bytes, bytearray)):
+            raise ValueError('Invalid token type')
+        if len(token) != 16:
+            raise ValueError('Invalid token length')
+        token = bytes(reversed(token))
+        for tix, tok in enumerate(sunpack('<4I', token)):
+            self._log.debug('Write token[%d] 0x%08x', tix, tok)
+            self._write_reg('transition_token', tok, tix)
+
+    @property
+    def transition_target(self) -> tuple[str, int]:
+        """Read back the transition target."""
+        target = self._read_reg('transition_target')
+        starget = self._decode_state(target)
+        self._log.debug('Transition target: %s', starget)
+        return starget, target
+
+    @transition_target.setter
+    def transition_target(self, target: Union[str, int]) -> None:
+        """Define the transition token as a 16-byte token."""
+        if isinstance(target, str):
+            itarget = self._encode_state(target)
+        elif isinstance(target, int):
+            if target < (1 << 5):
+                itarget = self._expand_state(target)
+            else:
+                itarget = target
+            self._check_state(itarget)
+        else:
+            raise ValueError('Invalid target type')
+        self._log.debug('Set transition target: 0x%08x', itarget)
+        self._write_reg('transition_target', itarget)
+
+    def otp_vendor_test_ctrl(self) -> int:
+        """Provide the OTP vendor test control as a 32-bit value."""
+        return self._read_reg('otp_vendor_test_ctrl')
+
+    def otp_vendor_test_status(self) -> int:
+        """Provide the OTP vendor test status as a 32-bit value."""
+        return self._read_reg('otp_vendor_test_status')
+
+    @property
+    def lc_state(self) -> Union[str, int]:
+        """Report the current state."""
+        istate = self._read_reg('lc_state')
+        tix = self._check_state(istate)
+        return self.STATES[tix], istate
+
+    @property
+    def lc_transition_count(self) -> int:
+        """Report the current transition count."""
+        return self._read_reg('lc_transition_cnt') & 0x1f
+
+    @property
+    def lc_id_state(self) -> str:
+        """Report the current ID state."""
+        value = self._read_reg('lc_id_state')
+        idmap = {0: 'blank', 0x55555555: 'personalized', 0xaaaaaaaa: 'invalid'}
+        try:
+            return idmap[value]
+        except KeyError as exc:
+            raise LifeCycleError(f'Unknown ID state 0x{value:08x}') from exc
+
+    @property
+    def hw_revision(self) -> HardwareRevision:
+        """Report the HW revision."""
+        hw0 = self._read_reg('hw_revision', 0)
+        hw1 = self._read_reg('hw_revision', 1)
+        widths = self._hw_rev_widths
+        creator = hw0 >> widths[1] & ((1 << widths[0]) - 1)
+        product = hw0 & ((1 << widths[1]) - 1)
+        revision = hw1 & ((1 << widths[2]) - 1)
+        return HardwareRevision(creator, product, revision)
+
+    @property
+    def device_identifier(self) -> bytes:
+        """Report the device identifier as a 32-byte value."""
+        devids = (self._read_reg('device_id', pos) for pos in range(8))
+        devid = spack(self.TOKEN_FORMAT, *devids)
+        self._log.debug('Transition token: %s', hexlify(devid).decode())
+        return devid
+
+    @property
+    def manufacturer_state(self) -> bytes:
+        """Report the manufacturer state as a 32-byte value."""
+        devids = (self._read_reg('manuf_state', pos) for pos in range(8))
+        devid = spack(self.TOKEN_FORMAT, *devids)
+        self._log.debug('Transition token: %s', hexlify(devid).decode())
+        return devid
+
+    @classmethod
+    def _decode_state(cls, state: int) -> str:
+        tgix = cls._check_state(state)
+        return cls.STATES[tgix]
+
+    @classmethod
+    def _encode_state(cls, state: str) -> int:
+        try:
+            tgix = cls.STATES.index(state.upper())
+        except IndexError as exc:
+            raise ValueError(f"Unknwon state '{state}'") from exc
+        return cls._expand_state(tgix)
+
+    @classmethod
+    def _check_state(cls, state: int) -> int:
+        base = cls._base_state(state)
+        if cls._expand_state(state) != state:
+            raise ValueError(f'Unknown state {state:08x}')
+        if not 0 <= base < len(cls.STATES):
+            raise ValueError(f'Unknown state {state:08x}')
+        return base
+
+    @classmethod
+    def _base_state(cls, state: int) -> int:
+        return state & ((1 << 5) - 1)
+
+    @classmethod
+    def _expand_state(cls, state: int) -> int:
+        base = cls._base_state(state)
+        return ((base << 25) | (base << 20) | (base << 15) | (base << 10) |
+                (base << 5) | base)
+
+    def _write_reg(self, name: str, value: int, offset: int = 0) -> None:
+        if value >= (1 << 32):
+            raise ValueError('Invalid value')
+        try:
+            reg = self.REGS[name] + offset
+        except KeyError as exc:
+            raise ValueError(f"No such LC register: '{name}'") from exc
+        self._log.info('write %s: 0x%08x', name, value)
+        return self._dmi.write(self._address + reg, value)
+
+    def _read_reg(self, name: str, offset: int = 0) -> int:
+        try:
+            reg = self.REGS[name] + offset
+        except KeyError as exc:
+            raise ValueError(f"No such LC register: '{name}'") from exc
+        self._log.info('read %s', name)
+        value = self._dmi.read(self._address + reg)
+        self._log.info('read 0x%08x', value)
+        return value
diff --git a/python/qemu/ot/lc_ctrl/tools.py b/python/qemu/ot/lc_ctrl/tools.py
new file mode 100644
index 0000000000000..134c2fd24caac
--- /dev/null
+++ b/python/qemu/ot/lc_ctrl/tools.py
@@ -0,0 +1,158 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""LifeCycle Controller utilities.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import hexlify
+from logging import getLogger
+from io import StringIO
+from random import randbytes
+from typing import NamedTuple
+
+import re
+
+try:
+    from Crypto.Hash import cSHAKE128
+except ModuleNotFoundError:
+    # see pip3 install -r requirements.txt
+    from Cryptodome.Hash import cSHAKE128
+
+
+class LifeCycleTokenPair(NamedTuple):
+    """Life Cycle token pair"""
+
+    text: bytes
+    hashed: bytes
+
+
+class LifeCycleTokenEngine:
+    """Life Controller token management.
+    """
+
+    TOKEN_LENGTH = 16
+    """Token length in bytes."""
+
+    TOKEN_CUSTOM = 'LC_CTRL'
+    """Token customisation string."""
+
+    TOKEN_VAR_NAME = 'LC_{var}_TOKEN{hashed}'
+    """Variable name template used to store a token value."""
+
+    def __init__(self):
+        self._log = getLogger('lc.token')
+
+    def generate(self) -> LifeCycleTokenPair:
+        """Generate a random token pair (clear, hashed)
+
+           :note: random quality is not suitable for production use
+        """
+        token_text = randbytes(self.TOKEN_LENGTH)
+        token_hash = self.hash(token_text)
+        return LifeCycleTokenPair(token_text, token_hash)
+
+    def hash(self, token: bytes) -> bytes:
+        """Hash a plain text token.
+
+           :param token: token to hash
+           :return: the hashed tocken
+        """
+        cshake = cSHAKE128.new(custom=self.TOKEN_CUSTOM.encode())
+        # convert natural byte order to little order
+        # (human readable, left to right, MSB to LSB) to LE
+        token_le = bytes(reversed(token))
+        cshake.update(token_le)
+        hash_le = cshake.read(self.TOKEN_LENGTH)
+        # convert back to natural byte order (from LE to human)
+        return bytes(reversed(hash_le))
+
+    def build_from_text(self, token: bytes) -> LifeCycleTokenPair:
+        """Build a token pair from a clear token.
+
+           :param token: clear token
+           :return: the token pair
+        """
+        return LifeCycleTokenPair(token, self.hash(token))
+
+    @classmethod
+    def build_rust_def(cls, name: str, value: bytes) -> str:
+        """Build Rust definition for a token.
+
+           :param name: the token name radix
+           :param value: the token value
+           :return: the generated definition
+        """
+        code = StringIO()
+        print(f'// {hexlify(value).decode()}', file=code)
+        print(f'const {name.upper()}: [u8; {len(value)}] = [', file=code)
+        value = bytes(value)
+        for pos in range(0, len(value), 8):
+            s = ', '.join((f'0x{c:02x}' for c in value[pos:pos+8]))
+            print(f'   {s},', file=code)
+        print('];', file=code)
+        return code.getvalue()
+
+    @classmethod
+    def build_qemu_def(cls, name: str, value: bytes) -> str:
+        """Build QEMU definition for a token.
+
+           :param name: the token name radix
+           :param value: the token value
+           :return: the generated definition
+        """
+        code = StringIO()
+        print(f'// {hexlify(value).decode()}', file=code)
+        print(f'static const OtOTPTokenValue {name.upper()} = {{', file=code)
+        print(f'    .hi = 0x{int.from_bytes(value[:8], "big"):016x}u,'
+              f' .lo = 0x{int.from_bytes(value[8:], "big"):016x}u,',
+              file=code)
+        print('}};', file=code)
+        return code.getvalue()
+
+    def generate_code(self, lang: str, name: str, tkpair: LifeCycleTokenPair) \
+            -> str:
+        """Generate code to store a token pair.
+
+           :param lang: the output type
+           :param name: the token name radix
+           :param value: the token value
+           :return: the generated code
+        """
+        builder = getattr(self, f'build_{lang}_def', None)
+        if not builder and not callable(builder):
+            raise ValueError('Unsupported language')
+        # pylint: disable=not-callable
+        lines = (
+            builder(self.TOKEN_VAR_NAME.format(var=name, hashed=''),
+                    tkpair.text),
+            builder(self.TOKEN_VAR_NAME.format(var=name, hashed='_HASHED'),
+                    tkpair.hashed),
+            ''
+        )
+        return '\n'.join(lines)
+
+    def parse_rust(self, rust_code: str) -> dict[str, LifeCycleTokenPair]:
+        """Parse Rust code and extract Token definitions.
+
+           :param rust_code: rust code to parse
+           :return: a dictionary of token pair, indexed by name
+        """
+        var_re = self.TOKEN_VAR_NAME.format(var='(.*)', hashed='(_HASHED)?')
+        rcre = re.compile(r'const ' + var_re + r': *\[u8; +16\] *= '
+                          r'*\[((?:[\s\n]+0x[0-9a-fA-F]{2},){16})(?:[\s\n]+)];')
+        tokens: dict[str, list[bytes, bytes]] = {}
+        for rmo in rcre.finditer(rust_code):
+            token = rmo.group(1)
+            hashed = bool(rmo.group(2))
+            seq = re.sub(r'(0x|\s|,)', '', rmo.group(3))
+            if token not in tokens:
+                tokens[token] = [bytes(0), bytes(0)]
+            pos = int(hashed)
+            if tokens[token][pos]:
+                raise ValueError(f'Redefinition of '
+                                 f'{"hashed" if hashed else "plain"} {token}')
+            tokens[token][pos] = int(seq, 16).to_bytes(self.TOKEN_LENGTH)
+        tkpairs = {n: LifeCycleTokenPair(*v) for n, v in tokens.items()}
+        return tkpairs
diff --git a/python/qemu/ot/mailbox/__init__.py b/python/qemu/ot/mailbox/__init__.py
new file mode 100644
index 0000000000000..f777a2d21e612
--- /dev/null
+++ b/python/qemu/ot/mailbox/__init__.py
@@ -0,0 +1,4 @@
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Mailbox tools."""
diff --git a/python/qemu/ot/mailbox/doe.py b/python/qemu/ot/mailbox/doe.py
new file mode 100644
index 0000000000000..0579c1764c3b6
--- /dev/null
+++ b/python/qemu/ot/mailbox/doe.py
@@ -0,0 +1,161 @@
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Device proxy for OpenTitan devices and peripherals
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from logging import getLogger
+from struct import calcsize as scalc, pack as spack, unpack as sunpack
+
+from .sysmbox import SysMbox, SysMboxError
+
+
+class DOEHeader:
+    """Container/helper for DOE headers.
+
+       :param vid: vendor identifier
+       :param objtype: object type
+       :param dwlength: count of 32-bit words in the DOE packet (incl. the
+                        header 2x 32-bit words)
+    """
+
+    FORMAT = '<HBxI'
+    """Encoding format."""
+
+    SIZE = scalc(FORMAT)
+    """Size of encoded content in bytes."""
+
+    DWSIZE = SIZE//4
+    """Size of encoded content in double word."""
+
+    def __init__(self, vid: int, objtype: int, dwlength: int = 0):
+        if not isinstance(vid, int) or not 0 <= vid <= 0xffff:
+            raise ValueError('Invalid VID')
+        if not isinstance(objtype, int) or not 0 <= objtype <= 0xff:
+            raise ValueError('Invalid objtype')
+        if not isinstance(dwlength, int) or not 0 <= dwlength <= 0x3ff:
+            raise ValueError('Invalid dwlength')
+        self._vid = vid
+        self._objtype = objtype
+        self._dwlength = dwlength
+
+    def __str__(self) -> str:
+        return f'vid:0x{self._vid:04x}, objtype:0x{self._objtype:02x}'
+
+    def __repr__(self) -> str:
+        return f'{self.__class__.__name__} ' \
+               f'0x{self._vid:04x},0x{self._objtype:02x}'
+
+    def set_dwlength(self, dwlength: int) -> None:
+        """Set the actual 32-bit word length of the DOE packet."""
+        if not isinstance(dwlength, int) or not 0 <= dwlength <= 0x3ff:
+            raise ValueError('Invalid dwlength')
+        self._dwlength = dwlength
+
+    @property
+    def vid(self):
+        """Report the stored vendor identifier."""
+        return self._vid
+
+    @property
+    def objtype(self):
+        """Report the stored object type."""
+        return self._objtype
+
+    @property
+    def dwlength(self):
+        """Report the count of double words (i.e. 32 bit words) including
+           the two double words from this very header in the DOE packet.
+        """
+        return self._dwlength
+
+    @classmethod
+    def decode(cls, buf: bytes) -> 'DOEHeader':
+        """Decode a byte buffer into a DOE header."""
+        if len(buf) < cls.SIZE:
+            raise ValueError('Too short a buffer')
+        vid, objtype, length = sunpack(cls.FORMAT, buf)
+        length &= 0x3ff
+        return cls(vid, objtype, length)
+
+    def encode(self) -> bytes:
+        """Encode this DOE header into a byte sequence."""
+        buf = spack(self.FORMAT, self._vid, self._objtype, self._dwlength)
+        return buf
+
+
+class DOEMailbox:
+    """Mailbox with a DOE header.
+
+       :param mailbox: a system mailbox instance
+       :param vid: vendor ID for the DOE header
+    """
+
+    def __init__(self, mailbox: SysMbox, vid: int):
+        self._mbox = mailbox
+        self._vid = vid
+        self._log = getLogger('mbox.doe')
+
+    def abort(self):
+        """Tell the mailbox to abort the request / clear any error."""
+        self._mbox.abort()
+
+    @property
+    def busy(self) -> bool:
+        """Report whether the mailbox is busy."""
+        return self._mbox.busy
+
+    @property
+    def on_error(self) -> bool:
+        """Report whether the mailbox is on error."""
+        return self._mbox.on_error
+
+    @property
+    def object_ready(self) -> bool:
+        """Report whether the mailbox contains a response."""
+        return self._mbox.object_ready
+
+    def write(self, oid: int, msg: bytes) -> None:
+        """Send a DOE message."""
+        hdr = DOEHeader(self._vid, oid)
+        trailing = len(msg) & 0x3
+        if trailing:
+            msg = b''.join((msg, bytes(4-trailing)))
+        dwlen = len(msg)//4 + DOEHeader.DWSIZE
+        hdr.set_dwlength(dwlen)
+        req = b''.join((hdr.encode(), msg))
+        self._log.debug('len %d', len(req))
+        count = self._mbox.write(req)
+        if count != len(req):
+            raise SysMboxError(f'Cannot write full buffer {count}/{len(req)}')
+        if self._mbox.on_error:
+            raise SysMboxError('JTAG mailbox on error')
+
+    def read(self) -> tuple[int, bytes]:
+        """Receive a DOE message."""
+        resp = self._mbox.read()
+        if not resp:
+            raise SysMboxError('No response from host')
+        if len(resp) < DOEHeader.SIZE:
+            raise SysMboxError('Truncated response from host')
+        self._log.debug('len %d', len(resp))
+        hdr = DOEHeader.decode(resp[:DOEHeader.SIZE])
+        if hdr.vid != self._vid:
+            raise SysMboxError(f'Unexpected vendor ID 0x{hdr.vid:04x}')
+        plen = (hdr.dwlength - DOEHeader.DWSIZE) * 4
+        payload = resp[DOEHeader.SIZE:]
+        if plen != len(payload):
+            raise SysMboxError(f'Unexpected payload length '
+                               f'{plen}/{len(payload)}')
+        oid = hdr.objtype
+        return oid, payload
+
+    def exchange(self, oid: int, msg: bytes) -> bytes:
+        """Exchange a message/response on the mailbox."""
+        self.write(oid, msg)
+        roid, payload = self.read()
+        if roid != oid:
+            raise SysMboxError(f'Unexpected object type: {oid}/{roid}')
+        return payload
diff --git a/python/qemu/ot/mailbox/jtag.py b/python/qemu/ot/mailbox/jtag.py
new file mode 100644
index 0000000000000..9aff2117540d6
--- /dev/null
+++ b/python/qemu/ot/mailbox/jtag.py
@@ -0,0 +1,78 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Mailbox over JTAG access.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from logging import getLogger
+
+from .sysmbox import SysMbox
+from ..dtm import DebugTransportModule
+
+
+class JtagMbox(SysMbox):
+    """JTAG Mailbox requester API
+    """
+
+    DEFAULT_DMI_ADDRESS = 0x880
+    """Default DMI address of the mailbox."""
+
+    SYSREGS = {'control': 2, 'status': 3, 'wdata': 4, 'rdata': 5}
+
+    def __init__(self, dtm: 'DebugTransportModule', address: int):
+        super().__init__()
+        self._log = getLogger('dtm.jtagmbx')
+        self._dmi = dtm['dmi']
+        self._address = address
+
+    @property
+    def busy(self) -> bool:
+        return bool(self._read_reg('status') & 0b001)
+
+    @property
+    def on_error(self) -> bool:
+        return bool(self._read_reg('status') & 0b100)
+
+    @property
+    def object_ready(self) -> bool:
+        return bool(self._read_reg('status') >> 31)
+
+    def go(self) -> None:
+        self._write_reg('control', 1 << 31)
+
+    def abort(self) -> None:
+        self._write_reg('control', 0b1)
+
+    def write_word(self, word: int) -> None:
+        self._write_reg('wdata', word)
+
+    def read_word(self, ack: bool = True) -> int:
+        word = self._read_reg('rdata')
+        if ack:
+            self.acknowledge_read()
+        return word
+
+    def acknowledge_read(self) -> None:
+        self._write_reg('rdata', 0)  # value is meaningless
+
+    def _write_reg(self, name: str, value: int) -> None:
+        if value >= (1 << 32):
+            raise ValueError('Invalid value')
+        try:
+            reg = self.SYSREGS[name]
+        except KeyError as exc:
+            raise ValueError(f"No such mailbox register: '{name}'") from exc
+        self._log.info('write %s: 0x%08x', name, value)
+        return self._dmi.write(self._address + reg, value)
+
+    def _read_reg(self, name: str) -> int:
+        try:
+            reg = self.SYSREGS[name]
+        except KeyError as exc:
+            raise ValueError(f"No such mailbox register: '{name}'") from exc
+        self._log.info('read %s', name)
+        value = self._dmi.read(self._address + reg)
+        self._log.info('read 0x%08x', value)
+        return value
diff --git a/python/qemu/ot/mailbox/sysmbox.py b/python/qemu/ot/mailbox/sysmbox.py
new file mode 100644
index 0000000000000..cfe6b034fa21f
--- /dev/null
+++ b/python/qemu/ot/mailbox/sysmbox.py
@@ -0,0 +1,108 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""System Mailbox.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import hexlify
+from logging import getLogger
+from time import sleep, time as now
+
+
+class SysMboxError(RuntimeError):
+    """System mailbox error."""
+
+
+class SysMbox:
+    """Mailbox requester API
+    """
+    def __init__(self):
+        self._log = getLogger('mbox.sys')
+
+    @property
+    def busy(self) -> bool:
+        """Report whether the mailbox is busy."""
+        raise NotImplementedError('ABC')
+
+    @property
+    def on_error(self) -> bool:
+        """Report whether the mailbox is on error."""
+        raise NotImplementedError('ABC')
+
+    @property
+    def object_ready(self) -> bool:
+        """Report whether the mailbox contains a response."""
+        raise NotImplementedError('ABC')
+
+    def go(self) -> None:
+        """Tell the mailbox to process the request."""
+        # pylint: disable=invalid-name
+        raise NotImplementedError('ABC')
+
+    def abort(self) -> None:
+        """Tell the mailbox to abort the request / clear any error."""
+        raise NotImplementedError('ABC')
+
+    def write_word(self, word: int) -> None:
+        """Write a single request word into the mailbox.
+
+           It is the caller responsability to check the mailbox is ready to
+           receive a new word.
+        """
+        raise NotImplementedError('ABC')
+
+    def read_word(self, ack: bool = True) -> int:
+        """Read a single response word from the mailbox.
+
+           It is the caller responsability to check the mailbox contains a new
+           word.
+        """
+        raise NotImplementedError('ABC')
+
+    def acknowledge_read(self) -> None:
+        """Acknowledge the read out of the last retrieved word."""
+        raise NotImplementedError('ABC')
+
+    def write(self, request: bytes) -> int:
+        """Send a request to the mailbox."""
+        if self.busy:
+            raise SysMboxError('Mailbox is busy')
+        if self.on_error:
+            raise SysMboxError('Mailbox is on error')
+        trailing = len(request) & 0x3
+        if trailing:
+            request = b''.join((request, bytes(4-trailing)))
+        self._log.info('TX: (%d) %s', len(request), hexlify(request).decode())
+        reqlen = 0
+        while request:
+            chunk, request = request[:4], request[4:]
+            self.write_word(int.from_bytes(chunk, 'little'))
+            reqlen += 4
+        self.go()
+        return reqlen
+
+    def read(self) -> bytes:
+        """Receive a response from the mailbox."""
+        timeout = now() + 2.0
+        while True:
+            if self.on_error:
+                self.abort()
+                raise SysMboxError('Mailbox is on error')
+            if self.object_ready:
+                break
+            if now() > timeout:
+                raise TimeoutError('No response from mailbox')
+            sleep(0.1)
+        response = bytearray()
+        while self.object_ready:
+            chunk = self.read_word()
+            response.extend(chunk.to_bytes(4, 'little'))
+        self._log.info('RX: (%d) %s', len(response), hexlify(response).decode())
+        return bytes(response)
+
+    def exchange(self, request: bytes) -> bytes:
+        """Performs a full half-duplex response-request on the mailbox."""
+        self.write(request)
+        return self.read()
diff --git a/python/qemu/ot/otp/__init__.py b/python/qemu/ot/otp/__init__.py
new file mode 100644
index 0000000000000..0d512184f8fa6
--- /dev/null
+++ b/python/qemu/ot/otp/__init__.py
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""One-Time Programmable controller."""
+
+from .descriptor import OtpPartitionDesc, OtpRegisterDef  # noqa: F401
+from .image import OtpImage  # noqa: F401
+from .map import OtpMap  # noqa: F401
+from .partition import OtpLifecycleExtension, OtpPartition  # noqa: F401
diff --git a/python/qemu/ot/otp/const.py b/python/qemu/ot/otp/const.py
new file mode 100644
index 0000000000000..3411da8042f35
--- /dev/null
+++ b/python/qemu/ot/otp/const.py
@@ -0,0 +1,270 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Lifecycle helpers.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import hexlify, unhexlify
+from logging import getLogger
+from typing import Any, Optional, TextIO
+import re
+
+from ot.util.misc import camel_to_snake_case
+
+
+class OtpConstants:
+    """OTP constant manager.
+    """
+
+    def __init__(self):
+        self._log = getLogger('otp.const')
+        self._consts: dict[str, list[str]] = {}
+        self._enums: dict[str, dict[str, int]] = {}
+        self._inv_defaults: list[Optional[str]] = []
+
+    def load_sv(self, svp: TextIO) -> bool:
+        """Decode OTP information from a System Verilog file.
+
+           :param svp: System Verilog stream with OTP definitions.
+           :return: True if some OTP information has been detected
+        """
+        svdata = svp.read()
+        for smo in re.finditer(r"\stypedef\s+enum\s+logic\s+\[[^]]+\]\s"
+                               r"{((?:\s+\w+,?)+)\s*}\s(\w+)_sel_e;", svdata):
+            values, name = smo.groups()
+            if name in self._consts:
+                raise ValueError(f'Multiple definitions of enumeration {name}')
+            enums = self._enums[name] = {}
+            for emo in re.finditer(r"\s+(\w+),?", values):
+                vname = camel_to_snake_case(emo.group(1))
+                enums[vname] = len(enums)
+
+        for amo in re.finditer(r"\s+parameter\s+(\w+)_array_t\s+(\w+)\s+=\s+"
+                               r"{(\s+(?:(?:64|128)'h[0-9A-F]+,?\s+)+)};",
+                               svdata):
+            _type, name, values = amo.groups()
+            sc_name = camel_to_snake_case(name)
+            sc_parts = sc_name.split('_')
+            if sc_parts[0] == 'rnd':
+                sc_parts.pop(0)
+            if sc_parts[0] == 'cnst':
+                sc_parts.pop(0)
+            name = '_'.join(sc_parts)
+            if name in self._consts:
+                raise ValueError(f'Multiple definitions of constant {name}')
+            consts = self._consts[name] = []
+            for cmo in re.finditer(r"(64|128)'h([0-9A-F]+),?", values):
+                nibble_count = (int(cmo.group(1)) + 3) // 4
+                hexa_str = cmo.group(2).lower()
+                hexa_str_len = len(hexa_str)
+                if hexa_str_len < nibble_count:
+                    pad_str = '0' * (nibble_count - hexa_str_len)
+                    hexa_str = f'{pad_str}{hexa_str}'
+                assert len(hexa_str) == nibble_count
+                consts.append(hexa_str)
+            # RTL order in array is reversed
+            consts.reverse()
+        inv_default = []
+        total_byte_count = 0
+        for imo in re.finditer(r"(?s) +parameter +logic +\[\d+:0\] +"
+                               r"PartInvDefault += +(\d+)'\(\{(.*)\}\);",
+                               svdata):
+            if inv_default:
+                raise ValueError('PartInvDefault redefined')
+            total_byte_count = int(imo.group(1)) // 8
+            for pmo in re.finditer(r"(\d+)'\(\{([^\}]*)\}\)", imo.group(2)):
+                part_byte_count = int(pmo.group(1)) // 8
+                chunks = []
+                for bmo in re.finditer(r"(\d+)'h([0-9A-Fa-f]+)", pmo.group(2)):
+                    byte_count = int(bmo.group(1)) // 8
+                    hexa_str = bmo.group(2)
+                    hexa_str_len = len(hexa_str)
+                    exp_len = byte_count * 2
+                    if hexa_str_len < exp_len:
+                        pad_str = '0' * (exp_len - hexa_str_len)
+                        hexa_str = f'{pad_str}{hexa_str}'
+                    hexa_bytes = unhexlify(hexa_str)
+                    assert len(hexa_bytes) == byte_count
+                    chunks.append(hexa_bytes)
+                chunk_byte_count = sum(len(c) for c in chunks)
+                if chunk_byte_count != part_byte_count:
+                    raise RuntimeError('Invalid partition default bytes')
+                # RTL order is last-to-first
+                inv_default.append(list(reversed(chunks)))
+        byte_count = sum(len(c) for part in inv_default for c in part)
+        if byte_count != total_byte_count:
+            raise RuntimeError('Invalid partition default bytes')
+        # RTL order is last-to-first
+        inv_default.reverse()
+        self._inv_defaults.clear()
+        for pno, part_chunks in enumerate(inv_default):
+            last_part = pno == len(inv_default) - 1
+            # last partition does not have digest,
+            # all digests are 8-byte long
+            if not last_part and len(part_chunks[-1]) == 8:
+                check_chunks = part_chunks[:-1]
+            else:
+                check_chunks = part_chunks
+            if not any(any(c) for c in check_chunks):
+                self._inv_defaults.append(None)
+                continue
+            defaults = b''.join(bytes(reversed(c)) for c in part_chunks)
+            self._inv_defaults.append(hexlify(defaults).decode())
+        return any(self._inv_defaults) and any(self._consts)
+
+    def load_secrets(self, secrets: dict[str, Any]) -> bool:
+        """Load OTP secrets from a (HJSON) map.
+
+           :param secrets: secret definitions as a map
+        """
+        modules = secrets.get('module', [])
+        otp: Optional[dict] = None
+        for mod in modules:
+            if mod.get('type') == 'otp_ctrl':
+                otp = mod
+                break
+        if not otp:
+            raise ValueError('Cannot locate OTP secrets')
+
+        try:
+            otp_map = otp['otp_mmap']
+            otp_size = otp_map['otp']['size']
+            scrambling = otp_map['scrambling']
+            parts = otp_map['partitions']
+        except KeyError as exc:
+            raise ValueError(f'Cannot find partition secrets: {exc}') from exc
+
+        sizes = {kp[0]: v for k, v in scrambling.items()
+                 if (kp := k.split('_', 1))[-1] == 'size'}
+        self._consts['key'] = [
+            hexlify(kv.to_bytes(sizes['key'], 'big')).decode()
+            for kd in scrambling['keys']
+            for kn, kv in kd.items() if kn == 'value'
+        ]
+        self._consts['digest_const'] = [
+            hexlify(kv.to_bytes(sizes['cnst'], 'big')).decode()
+            for kd in scrambling['digests']
+            for kn, kv in kd.items() if kn == 'cnst_value'
+        ]
+        self._consts['digest_iv'] = [
+            hexlify(kv.to_bytes(sizes['iv'], 'big')).decode()
+            for kd in scrambling['digests']
+            for kn, kv in kd.items() if kn == 'iv_value'
+        ]
+
+        offset = 0
+        total_size = 0
+        for part in parts or []:
+            part_name = part['name']
+            part_size = 0
+            part_inv_bytes: list[bytes] = []
+            part_inv_sum = 0
+            # there is not a 'buffered' boolean in the HJSON file
+            # the variant is either "unbuffered", "buffered" or "lifecyle";
+            # however lifeycle partition is actually a buffered partition.
+            part_buffered = part.get('variant', '').lower() != 'unbuffered'
+            for item in part['items']:
+                size = item['size']
+                name = item['name']
+                part_size += size
+                if item['offset'] != offset:
+                    missing = item['offset'] - offset
+                    self._log.info('Gap before %s.%s: %u bytes',
+                                   part_name, name, missing)
+                    assert missing > 0, 'Invalid negative offset'
+                    part_inv_bytes[-1] = b''.join((part_inv_bytes[-1],
+                                                   bytes(missing)))
+                    part_size += missing
+                offset = item['offset'] + size
+                inv_default = item['inv_default']
+                inv_bytes = inv_default.to_bytes(size, 'big')
+                if inv_default and not item['isdigest']:
+                    part_inv_sum += inv_default
+                part_inv_bytes.append(inv_bytes)
+            if part_size != part['size']:
+                raise ValueError(f'Invalid byte count for part {part_name}: '
+                                 f"{part_size} != {part['size']}")
+            # invalid default values are defined in RTL and HJSON for all
+            # partitions, whereas they can only be used for buffered partitions;
+            # discard values for non-buffered partitions
+            if part_buffered and part_inv_sum:
+                part_inv_str = hexlify(b''.join(part_inv_bytes)).decode()
+                self._inv_defaults.append(part_inv_str)
+            else:
+                if part_inv_sum:
+                    self._log.debug('Discard inv default values for unbuffered '
+                                    'part %s', part_name)
+                self._inv_defaults.append(None)
+            total_size += part_size
+        if total_size != otp_size:
+            raise ValueError(f'Invalid byte count for OTP '
+                             f'{total_size} != {otp_size}')
+
+    def get_enums(self) -> list[str]:
+        """Return a list of parsed enumerations."""
+        return list(self._enums.keys())
+
+    def get_digests(self) -> list[str]:
+        """Return a list of parsed digests."""
+        try:
+            return list(self._enums['digest'])
+        except KeyError as exc:
+            raise ValueError("No 'digest' enum found") from exc
+
+    def get_scrambling_keys(self) -> list[str]:
+        """Return a list of parsed scrambling keys for secret partitions."""
+        try:
+            return list(self._enums['key'])
+        except KeyError as exc:
+            raise ValueError("No 'key' enum found") from exc
+
+    def get_digest_pair(self, name: str, prefix: str) -> dict[str, str]:
+        """Return a dict of digest pair.
+           :param name: one of the enumerated values, see #get_digests
+           :param prefix: the prefix to add to each dict key.
+        """
+        try:
+            idx = self._enums['digest'][name]
+        except KeyError as exc:
+            raise ValueError(f'Unknown digest pair {name}') from exc
+        odict = {}
+        for kname, values in self._consts.items():
+            if kname.startswith('digest_'):
+                if len(values) < idx:
+                    raise ValueError(f'No such digest {name}')
+                oname = f"{prefix}_{kname.split('_', 1)[-1]}"
+                odict[oname] = values[idx]
+        return odict
+
+    def get_scrambling_key(self, name: str) -> str:
+        """Get the value of a scrambling key.
+           :param name: One of the enumerated values, see #get_scrambling_keys
+        """
+        try:
+            idx = self._enums['key'][name]
+        except KeyError as exc:
+            raise ValueError(f'Unknown scrambling key {name}') from exc
+        try:
+            key_values = self._consts['key']
+        except KeyError as exc:
+            raise ValueError('No scrambling key constants found') from exc
+        if len(key_values) <= idx:
+            raise ValueError(f'No such key {name} in the key array')
+        return key_values[idx]
+
+    def get_partition_inv_defaults(self, partition: int) -> Optional[str]:
+        """Return the invalid default values for a partition, if any.
+           Partitions with only digest defaults are considered without default
+           values.
+
+           :param partition: the partition index
+           :return: either None or the default hex-encoded bytes, including any
+                    digest and zero-ing trailing bytes
+        """
+        try:
+            return self._inv_defaults[partition]
+        except IndexError as exc:
+            raise ValueError(f'No such partition:{partition}') from exc
diff --git a/python/qemu/ot/otp/descriptor.py b/python/qemu/ot/otp/descriptor.py
new file mode 100644
index 0000000000000..856d257c017aa
--- /dev/null
+++ b/python/qemu/ot/otp/descriptor.py
@@ -0,0 +1,395 @@
+# Copyright (c) 2023-2024 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""OTP descriptors.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from logging import getLogger
+from typing import NamedTuple, Optional, TYPE_CHECKING, TextIO
+
+from ot.top import OpenTitanTop
+from ot.util.misc import redent
+from .partition import OtpPartition
+
+if TYPE_CHECKING:
+    from .map import OtpMap
+
+
+class OtpSlotDescriptor(NamedTuple):
+    """A location descriptor in OTP, either a whole partition or an item.
+
+       It has no other purpose than storing intermediate info as a container.
+    """
+
+    name: str
+    """Name of the slot."""
+
+    offset: str
+    """Offset in bytes."""
+
+    size: str
+    """Size in bytes."""
+
+    gen: bool = False
+    """Whether this slot is generated by the script or defined."""
+
+    part: bool = False
+    """Whether the slot defines the whole partition or a single item."""
+
+
+class OtpPartitionDesc:
+    """OTP Partition descriptor generator."""
+
+    ATTRS = {
+        'size': None,
+        'offset': None,
+        'digest_offset': None,
+        'zer_offset': None,
+        'hw_digest': '',
+        'sw_digest': '',
+        'secret': '',
+        'variant': 'buffer',
+        'write_lock': 'wlock',
+        'read_lock': 'rlock',
+        'integrity': '',
+        'zeroizable': '',
+        'iskeymgr': '',
+        'iskeymgr_creator': '',
+        'iskeymgr_owner': '',
+        'wide': ''
+    }
+
+    def __init__(self, otpmap: 'OtpMap'):
+        self._log = getLogger('otp.partdesc')
+        self._otpmap = otpmap
+
+    def save(self, kind: str, hjname: str, scriptname: str, cfp: TextIO) \
+            -> None:
+        """Generate a source file with a static description for the partitions.
+
+           :param kind: kind of generation output
+           :param hjname: the name of the input HJSON configuration file
+           :param scriptname: the name of the script that generates this output
+           :param cfp: the output text stream
+        """
+        # pylint: disable=f-string-without-interpolation
+        if kind != 'qemu':
+            raise NotImplementedError(f'No support for {kind}')
+        attrs = {n: getattr(self, f'_convert_to_{k}') if k else lambda x: x
+                 for n, k in self.ATTRS.items() if k is not None}
+        msg = f'Generated from {hjname} with {scriptname}'
+        git_version = self._otpmap.git_version
+        if git_version:
+            print(f'/*\n * {msg}\n * Top version: {git_version}\n */', file=cfp)
+        else:
+            print(f'/* ${msg} */', file=cfp)
+        print(file=cfp)
+        print('/* clang-format off */', file=cfp)
+        print('/* NOLINTBEGIN */', file=cfp)
+        print('static const OtOTPPartDesc OT_OTP_PART_DESCS[] = {', file=cfp)
+        for part in self._otpmap.enumerate_partitions():
+            print(f'    [OTP_PART_{part.name}] = {{', file=cfp)
+            print(f'        .name = "{part.name}",', file=cfp)
+            print(f'        .size = {part.size}u,', file=cfp)
+            print(f'        .offset = {part.offset}u,', file=cfp)
+            if part.zer_offset is not None:
+                print(f'        .zer_offset = {part.zer_offset}u,',
+                      file=cfp)
+            else:
+                print(f'        .zer_offset = UINT16_MAX,',   # noqa: F541
+                      file=cfp)
+            if part.digest_offset is not None:
+                print(f'        .digest_offset = {part.digest_offset}u,',
+                      file=cfp)
+            else:
+                print(f'        .digest_offset = UINT16_MAX,',   # noqa: F541
+                      file=cfp)
+            for attr in attrs:
+                value = getattr(part, attr, None)
+                if value is None:
+                    continue
+                convs = attrs[attr](value)
+                if not isinstance(convs, list):
+                    convs = [convs]
+                for conv in convs:
+                    if isinstance(conv, tuple):
+                        attr_name = conv[0]
+                        attr_val = conv[1]
+                    else:
+                        attr_name = attr
+                        attr_val = conv
+                    if isinstance(attr_val, bool):
+                        attr_val = str(attr_val).lower()
+                    print(f'        .{attr_name} = {attr_val},', file=cfp)
+            print('    },', file=cfp)
+        print('};', file=cfp)
+        print('', file=cfp)
+        print('#define OTP_PART_COUNT ARRAY_SIZE(OT_OTP_PART_DESCS)', file=cfp)
+        print(file=cfp)
+        key_seeds: list[tuple[str, str, int, int]] = []
+        for kseed in self._otpmap.key_seeds:
+            if kseed.name == 'SRAM_DATA':
+                # the OTBN key is derived from the SRAM key
+                key_seeds.append(('OT_OTP_KEY_OTBN',
+                                  f'OTP_PART_{kseed.part_name}',
+                                  kseed.offset, kseed.size))
+                key_seeds.append(('OT_OTP_KEY_SRAM',
+                                  f'OTP_PART_{kseed.part_name}',
+                                  kseed.offset, kseed.size))
+                continue
+            key_seeds.append((f'OT_OTP_KEY_{kseed.name}',
+                              f'OTP_PART_{kseed.part_name}',
+                              kseed.offset, kseed.size))
+        print('static const OtOTPKeySeed '
+              'OT_OTP_KEY_SEEDS[OT_OTP_KEY_COUNT] = {',
+              file=cfp)
+        for ksd in key_seeds:
+            print(f'    [{ksd[0]}] = {{', file=cfp)
+            print(f'        .partition = {ksd[1]},', file=cfp)
+            print(f'        .offset = {ksd[2]},', file=cfp)
+            print(f'        .size = {ksd[3]},', file=cfp)
+            print('    },', file=cfp)
+        print('};', file=cfp)
+        print('', file=cfp)
+        print('/* NOLINTEND */', file=cfp)
+        print('/* clang-format on */', file=cfp)
+        # pylint: enable=f-string-without-interpolation
+
+    @classmethod
+    def _convert_to_bool(cls, value) -> str:
+        return str(value).lower()
+
+    @classmethod
+    def _convert_to_buffer(cls, value) -> tuple[str, bool]:
+        return {
+            'unbuffered': ('buffered', False),
+            'buffered': ('buffered', True),
+            'lifecycle': ('buffered', True),
+        }[value.lower()]
+
+    @classmethod
+    def _convert_to_wlock(cls, value) -> bool:
+        return value == 'digest'
+
+    @classmethod
+    def _convert_to_rlock(cls, value) -> list[tuple[str, bool]]:
+        value = value.lower()
+        if value == 'csr':
+            return [('read_lock_csr', True), ('read_lock', True)]
+        if value == 'digest':
+            return 'read_lock', True
+        if value == 'none':
+            return 'read_lock', False
+        assert False, 'Unknown RLOCK type'
+
+
+class OtpRegisterDef:
+    """OTP Partition register generator."""
+
+    def __init__(self, otpmap: 'OtpMap'):
+        self._log = getLogger('otp.reg')
+        self._otpmap = otpmap
+
+    def save(self, kind: str, topname: Optional[str], hjname: str,
+             scriptname: str, cfp: TextIO) -> None:
+        """Generate a source file with register definition for the partitions.
+
+           :param kind: kind of generation output
+           :param topname: the name of the OpenTitan top
+           :param hjname: the name of the input HJSON configuration file
+           :param scriptname: the name of the script that generates this output
+           :param cfp: the output text stream
+        """
+        try:
+            save = getattr(self, f'_save_{kind.lower()}')
+        except AttributeError as exc:
+            raise NotImplementedError(f'No support for {kind}') from exc
+        slots: list[OtpSlotDescriptor] = []
+        for part in self._otpmap.enumerate_partitions():
+            offset = part.offset
+            slots.append(OtpSlotDescriptor(part.name, offset, part.size, True,
+                                           True))
+            for itname, itdict in part.items.items():
+                size = itdict['size']
+                if not itname.startswith(f'{part.name}_'):
+                    name = f'{part.name}_{itname}'.upper()
+                else:
+                    name = itname
+                slots.append(OtpSlotDescriptor(name, offset, size))
+                offset += size
+            zeroizable = getattr(part, 'zeroizable', False)
+            digest = any(getattr(part, f'{k}w_digest', False) for k in 'sh')
+            if digest:
+                offset = part.offset + part.size - OtpPartition.DIGEST_SIZE
+                if zeroizable:
+                    offset -= OtpPartition.ZER_SIZE
+                slots.append(OtpSlotDescriptor(f'{part.name}_DIGEST', offset,
+                                               OtpPartition.DIGEST_SIZE, True))
+            if zeroizable:
+                offset = part.offset + part.size - OtpPartition.DIGEST_SIZE
+                slots.append(OtpSlotDescriptor(f'{part.name}_ZER', offset,
+                                               OtpPartition.ZER_SIZE, True))
+
+        save(topname, hjname, scriptname, cfp, slots)
+
+    def _save_qemu(self, topname: Optional[str], hjname: str, scriptname: str,
+                   cfp: TextIO, slots: list[OtpSlotDescriptor]) -> None:
+        msg = f'Generated from {hjname} with {scriptname}'
+        git_version = self._otpmap.git_version
+        if git_version:
+            print(f'/*\n * {msg}\n * Top version: {git_version}\n */', file=cfp)
+        else:
+            print(f'/* ${msg} */', file=cfp)
+        print(file=cfp)
+        for slot in slots:
+            if slot.part:
+                continue
+            print(f'REG32({slot.name}, {slot.offset}u)', file=cfp)
+        print(file=cfp)
+
+        regwidth = max(len(s.name) for s in slots)
+        regwidth += len('_SIZE')
+        for slot in slots:
+            if slot.gen and not slot.part:
+                continue
+            name = f'{slot.name}_SIZE'
+            print(f'#define {name:{regwidth}s} {slot.size}u', file=cfp)
+        print(file=cfp)
+
+        part_names = [slot.name for slot in slots if slot.part]
+        pcount = len(part_names)
+        part_names = [f'OTP_PART_{pn}' for pn in part_names]
+        part_names.extend((
+            'OTP_PART_COUNT',
+            'OTP_ENTRY_DAI = OTP_PART_COUNT, '
+            '/* Fake partitions for error (...) */',
+            'OTP_ENTRY_KDI, /* Key derivation issue, not really OTP */',
+            'OTP_ENTRY_COUNT'))
+        print('typedef enum {', file=cfp)
+        for pname in part_names:
+            print(f'    {pname}{"," if "," not in pname else ""}', file=cfp)
+        print('} OtOTPPartitionType;', file=cfp)
+        print(file=cfp)
+
+        print('static const char *PART_NAMES[] = {', file=cfp)
+        print('    /* clang-format off */', file=cfp)
+        for pname in part_names[:pcount]:
+            print(f'    OT_OTP_NAME_ENTRY({pname}),', file=cfp)
+        print('    /* fake partitions */', file=cfp)
+        print('    OT_OTP_NAME_ENTRY(OTP_ENTRY_DAI),', file=cfp)
+        print('    OT_OTP_NAME_ENTRY(OTP_ENTRY_KDI),', file=cfp)
+        print('    /* clang-format on */', file=cfp)
+        print('};', file=cfp)
+        print(file=cfp)
+
+        cases: list[str] = []
+        for slot in slots:
+            if slot.part:
+                continue
+            if slot.gen:
+                cases.append(f'CASE_WIDE({slot.name});')
+            elif slot.size > 4:
+                cases.append(f'CASE_RANGE({slot.name});')
+            elif slot.size == 1:
+                cases.append(f'CASE_BYTE({slot.name});')
+            elif slot.size < 4:
+                cases.append(f'CASE_SUB({slot.name}, {slot.size}u);')
+            else:
+                cases.append(f'CASE_REG({slot.name});')
+
+        code = '''
+        static const char *ot_otp_swcfg_reg_name(unsigned swreg)
+        {
+        #define CASE_BYTE(_reg_) \\
+            case A_##_reg_: \\
+                return stringify(_reg_)
+        #define CASE_SUB(_reg_, _sz_) \\
+            case A_##_reg_...(A_##_reg_ + (_sz_) - 1u): \\
+                return stringify(_reg_)
+        #define CASE_REG(_reg_) \\
+            case A_##_reg_...(A_##_reg_ + 3u): \\
+                return stringify(_reg_)
+        #define CASE_WIDE(_reg_) \\
+            case A_##_reg_...(A_##_reg_ + 7u): \\
+                return stringify(_reg_)
+        #define CASE_RANGE(_reg_) \\
+            case A_##_reg_...(A_##_reg_ + (_reg_##_SIZE) - 1u): \\
+                return stringify(_reg_)
+
+            switch (swreg) {
+                _CASES_
+            default:
+                return "<?>";
+            }
+
+        #undef CASE_BYTE
+        #undef CASE_SUB
+        #undef CASE_REG
+        #undef CASE_RANGE
+        #undef CASE_DIGEST
+        }
+        '''
+        if topname:
+            tname = OpenTitanTop.short_name(topname)
+            if tname:
+                code = code.replace('ot_otp_swcfg_reg_name',
+                                    f'ot_otp_{tname}_swcfg_reg_name')
+        code = redent(code)
+        code = code.replace('_CASES_', '\n        '.join(cases))
+        print(redent(code), '', file=cfp)
+
+    def _save_bmtest(self, topname: Optional[str], hjname: str, scriptname: str,
+                     cfp: TextIO, slots: list[OtpSlotDescriptor]) -> None:
+        # pylint: disable=unused-argument
+        print(f'// Generated from {hjname} with {scriptname}', file=cfp)
+        if self._otpmap.git_version:
+            print(f'// Top version: {self._otpmap.git_version}', file=cfp)
+        print(file=cfp)
+        rec_p2 = 1 << (len(slots) - 1).bit_length()
+        print(f'#![recursion_limit = "{rec_p2}"]', file=cfp)
+        print(file=cfp)
+        print('#[derive(Clone, Copy, Debug, PartialEq)]', file=cfp)
+        print('pub enum Partition {', file=cfp)
+        part_names = [slot.name for slot in slots if slot.part]
+        for pname in part_names:
+            pname = pname.title().replace('_', '')
+            print(f'    {pname},', file=cfp)
+        print('}', file=cfp)
+        print(file=cfp)
+        print('register_structs! {', file=cfp)
+        print('    pub OtpSwCfgRegs {', file=cfp)
+        slot = OtpSlotDescriptor('', 0, 0)  # default slot if none is defined
+        end = 0
+        rsv = 0
+        for slot in slots:
+            if slot.part:
+                continue
+            if slot.offset > end:
+                missing = slot.offset - end
+                count = missing // 4
+                if count > 1:
+                    print(f'        (0x{end:04x} => '
+                          f'_reserved{rsv}: [ReadOnly<u32>; {count}]),',
+                          file=cfp)
+                else:
+                    width = missing * 8
+                    print(f'        (0x{end:04x} => '
+                          f'_reserved{rsv}: ReadOnly<u{width}>),', file=cfp)
+                rsv += 1
+            if slot.size <= 4:
+                width = slot.size * 8
+                print(f'        (0x{slot.offset:04x} => '
+                      f'{slot.name.lower()}: ReadOnly<u{width}>),', file=cfp)
+            else:
+                count = slot.size // 4
+                print(f'        (0x{slot.offset:04x} => '
+                      f'{slot.name.lower()}: [ReadOnly<u32>; {count}]),',
+                      file=cfp)
+            end = slot.offset + slot.size
+        print(f'        (0x{slot.offset+slot.size:04x} => @END),', file=cfp)
+        print('    }', file=cfp)
+        print('}', file=cfp)
+        print(file=cfp)
diff --git a/python/qemu/ot/otp/image.py b/python/qemu/ot/otp/image.py
new file mode 100644
index 0000000000000..9be74a1558f84
--- /dev/null
+++ b/python/qemu/ot/otp/image.py
@@ -0,0 +1,881 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""OTP QEMU image.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import unhexlify
+from configparser import ConfigParser, NoOptionError
+from io import BytesIO
+from logging import getLogger
+from struct import (calcsize as scalc, iter_unpack as iunpack, pack as spack,
+                    unpack as sunpack)
+from typing import Any, BinaryIO, Optional, Sequence, TextIO, Union
+import re
+
+from ot.util.misc import HexInt, classproperty, split_map_join
+
+from .map import OtpMap
+from .partition import OtpPartition, OtpLifecycleExtension
+
+
+class OtpImage:
+    """QEMU 'RAW' OTP image."""
+
+    HEADER_FORMAT = {
+        'magic': '4s',  # "vOTP"
+        'hlength': 'I',  # count of header bytes after this point
+        'version': 'I',  # version of the header
+        'eccbits': 'H',  # count of ECC bits for each ECC granule
+        'eccgran': 'H',  # size in bytes of ECC granule
+        'dlength': 'I',  # count of data bytes (padded to 64-bit entries)
+        'elength': 'I',  # count of ecc bytes (padded to 64-bit entries)
+    }
+
+    HEADER_FORMAT_V2_EXT = {
+        'digiv':   '8s',  # Present digest scrambler IV
+        'digfc':   '16s',  # Present digest scrambler finalization constant
+    }
+
+    KINDS = {
+        'OTP MEM': 'otp',
+        'FUSEMAP': 'fuz',
+    }
+
+    RE_VMEMLOC = r'(?i)^@((?:[0-9a-f]{2})+)\s((?:[0-9a-f]{2})+)$'
+    RE_VMEMDESC = r'(?i)^//\s?([\w\s]+) file with (\d+)[^\d]*(\d+)\s?bit layout'
+
+    DEFAULT_ECC_BITS = 6
+
+    SYNDROME_HAMMING_22_16 = (
+        (0x01ad5b, 0x02366d, 0x04c78e, 0x0807f0, 0x10f800, 0x3fffff),
+        (0x23, 0x25, 0x26, 0x27, 0x29, 0x2a, 0x2b, 0x2c,
+         0x2d, 0x2e, 0x2f, 0x31, 0x32, 0x33, 0x34, 0x35)
+    )
+
+    def __init__(self, ecc_bits: Optional[int] = None):
+        self._log = getLogger('otp.img')
+        self._header: dict[str, Any] = {}
+        self._magic = b''
+        self._changed = False
+        self._data = bytearray()
+        self._ecc = bytearray()
+        if ecc_bits is None:
+            ecc_bits = self.DEFAULT_ECC_BITS
+        self._ecc_bits = ecc_bits
+        self._ecc_bytes = (ecc_bits + 7) // 8
+        self._ecc_granule = 0
+        self._digest_iv: Optional[int] = None
+        self._digest_constant: Optional[int] = None
+        self._partitions: list[OtpPartition] = []
+        self._part_offsets: list[int] = []
+        self._dirty_offsets: list[int] = []
+        self._header_comments: list[str] = []
+
+    @property
+    def version(self) -> int:
+        """Provide the version of the RAW image."""
+        return self._header.get('version', 0)
+
+    @property
+    def loaded(self) -> int:
+        """Report whether data have been loaded into the image."""
+        return len(self._data) > 0
+
+    @property
+    def is_opentitan(self) -> bool:
+        """Report whether the current image contains OpenTitan OTP data."""
+        return self._magic == b'vOTP'
+
+    @property
+    def changed(self) -> bool:
+        """Report whether the content of the partition (data or ecc) has been
+           modified since it has been loaded or since the last time it has been
+           saved.
+        """
+        return self._changed
+
+    @classproperty
+    def vmem_kinds(cls) -> list[str]:
+        """Reports the supported content kinds of VMEM files."""
+        # pylint: disable=no-self-argument
+        return ['auto'] + list(cls.KINDS.values())
+
+    @classproperty
+    def logger(self):
+        """Return logger instance."""
+        # pylint: disable=no-self-argument
+        return getLogger('otptool')
+
+    def load_raw(self, rfp: BinaryIO) -> None:
+        """Load OTP image from a QEMU 'RAW' image stream."""
+        header = self._load_header(rfp)
+        self._header = header
+        self._data = bytearray(rfp.read(header['dlength']))
+        self._ecc = bytearray(rfp.read(header['elength']))
+        self._ecc_bits = header['eccbits']
+        self._ecc_bytes = header['dlength']
+        self._ecc_granule = header['eccgran']
+        self._ecc_bytes = (self._ecc_bits + 7) // 8
+        self._dirty_offsets.clear()
+        if header['version'] > 1:
+            self._digest_iv = header['digiv']
+            self._digest_constant = header['digfc']
+        self._changed = False
+
+    def save_raw(self, rfp: BinaryIO) -> None:
+        """Save OTP image as a QEMU 'RAW' image stream."""
+        header = self._build_header()
+        rfp.write(header)
+        self._pad(rfp)
+        rfp.write(self._data)
+        self._pad(rfp)
+        rfp.write(self._ecc)
+        self._pad(rfp, 4096)
+        self._changed = False
+
+    def load_vmem(self, vfp: TextIO, vmem_kind: Optional[str] = None,
+                  swap: bool = True):
+        """Parse a VMEM '24' text stream."""
+        data_buf: list[bytes] = []
+        ecc_buf: list[bytes] = []
+        last_addr = 0
+        granule_sizes: set[int] = set()
+        vkind: Optional[str] = None
+        row_count = 0
+        byte_count = 0
+        line_count = 0
+        if vmem_kind:
+            vmem_kind = vmem_kind.lower()
+            if vmem_kind == 'auto':
+                vmem_kind = None
+        if vmem_kind and vmem_kind not in self.KINDS.values():
+            raise ValueError(f"Unknown VMEM file kind '{vmem_kind}'")
+        for lno, line in enumerate(vfp, start=1):
+            if vkind is None:
+                kmo = re.match(self.RE_VMEMDESC, line)
+                if kmo:
+                    self._header_comments.append(line.rstrip())
+                    vkind = kmo.group(1)
+                    row_count = int(kmo.group(2))
+                    bits = int(kmo.group(3))
+                    byte_count = bits // 8
+                    continue
+            if line.startswith('// '):
+                self._header_comments.append(line.rstrip())
+            line = re.sub(r'//.*', '', line)
+            line = line.strip()
+            if not line:
+                continue
+            lmo = re.match(self.RE_VMEMLOC, line)
+            if not lmo:
+                self._log.error('Unexpected line @ %d: %s', lno, line)
+                continue
+            line_count += 1
+            saddr, sdata = lmo.groups()
+            addr = int(saddr, 16)
+            if last_addr < addr:
+                self._log.info('Padding addr from 0x%04x to 0x%04x',
+                               last_addr, addr)
+                data_buf.append(bytes(addr-last_addr))
+            rdata = unhexlify(sdata)
+            if byte_count != len(rdata):
+                self._log.warning('Expected %d bytes @ line %s, found %d',
+                                  byte_count, lno, len(sdata))
+            ecc, data = rdata[:self._ecc_bytes], rdata[self._ecc_bytes:]
+            if swap:
+                data = bytes(reversed(data))
+            data_buf.append(data)
+            ecc_buf.append(ecc)
+            dlen = len(data)
+            granule_sizes.add(dlen)
+            last_addr = addr+dlen  # ECC is not accounted for in address
+        self._data = bytearray(b''.join(data_buf))
+        self._ecc = bytearray(b''.join(ecc_buf))
+        if granule_sizes:
+            if len(granule_sizes) != 1:
+                raise ValueError('Variable data size')
+            self._ecc_granule = granule_sizes.pop()
+        if row_count and row_count != line_count:
+            self._log.error('Should have parsed %d lines, found %d',
+                            row_count, line_count)
+        if not vkind:
+            if vmem_kind:
+                vkind = vmem_kind
+        else:
+            vkind = self.KINDS.get(vkind.upper(), None)
+            if vmem_kind:
+                if vkind and vkind != vmem_kind:
+                    self._log.warning("Detected VMEM kind '%s' differs from "
+                                      "'%s'", vkind, vmem_kind)
+                # use user provided type, even if it is not the one detected
+                vkind = vmem_kind
+        if not vkind:
+            raise ValueError('Unable to detect VMEM find, please specify')
+        self._magic = f'v{vkind[:3].upper()}'.encode()
+        self._changed = False
+
+    def save_vmem(self, vfp: TextIO, verbose: bool = False) -> None:
+        """Save a VMEM '24' text stream."""
+        if verbose and not (self._partitions and self._part_offsets):
+            self._log.warning('Verbose mode disabled as no OTP map is known')
+            verbose = False
+        dsrc = iunpack('<H', self._data)
+        if self._header_comments:
+            if verbose:
+                # for some reason original format starts with an empty comment
+                print('//', file=vfp)
+            print('\n'.join(self._header_comments), file=vfp)
+        if verbose:
+            fields = self.document_partitions()
+            for addr, (dword, ecc, doc) in enumerate(
+                    zip(dsrc, self._ecc, fields)):
+                print(f'@{addr:06x} {ecc:02x}{dword[0]:04x} // {doc}', file=vfp)
+        else:
+            for addr, (dword, ecc) in enumerate(zip(dsrc, self._ecc)):
+                print(f'@{addr:06x} {ecc:02x}{dword[0]:04x}', file=vfp)
+
+    def load_lifecycle(self, lcext: OtpLifecycleExtension) -> None:
+        """Load lifecyle values."""
+        for part in self._partitions:
+            if part.name == 'LIFE_CYCLE':
+                part.set_decoder(lcext)
+
+    def load_config(self, cfp: TextIO, section: Optional[str] = None) -> None:
+        """Load Present constant from a QEMU configuration file.
+
+           :param cfp: the configuration stream
+           :param section: the section name where to find the constants.
+                           if not set, try to discover the OTP section name
+        """
+        cfg = ConfigParser()
+        cfg.read_file(cfp)
+        prefix = 'ot_device '
+        ot_sections = [s for s in cfg.sections() if s.startswith(prefix)]
+        devnames = [s.removeprefix(prefix).strip('"') for s in ot_sections]
+        if not section:
+            otpnames = {d.split('.')[0] for d in devnames
+                        if d.startswith('ot-otp')}
+            if len(otpnames) != 1:
+                # section should be explicitly defined in this case
+                # this internal error may be raised if either:
+                # - the configuration file does not contain an OTP section
+                # - the OTP section name does not match the expected format
+                # - several OTP-like sections could match, but there is no way
+                #   to discriminate which one is valid/usable
+                raise ValueError('Unable to discover the name of OTP device')
+            section = otpnames.pop()
+            self._log.debug('Detected OTP section prefix: %s', section)
+        elif not cfg.has_section(section):
+            raise ValueError(f"No OTP device '{section}'")
+        sectnames = set()
+        for devname in devnames:
+            if devname != section and not devname.startswith(f'{section}.'):
+                continue
+            sectnames.add(f'{prefix}"{devname}"')
+            self._log.info('Found OTP candidate section %s', devname)
+        if not sectnames:
+            raise ValueError(f"Cannot find OTP device section '{section}'")
+        # accept multiple sections with Present constants definitions as long
+        # as they do match
+        constants = set()
+        ivs = set()
+        for sectname in sectnames:
+            try:
+                constants.add(cfg.get(sectname, 'digest_const')
+                              .strip('"').lower())
+                ivs.add(cfg.get(sectname, 'digest_iv')
+                        .strip('"').lower())
+            except NoOptionError:
+                pass
+        if not constants or not ivs:
+            raise ValueError('Incomplete configuration file')
+        if len(constants) > 1 or len(ivs) > 1:
+            raise ValueError(f"Too many OTP device sections '{section}'")
+        self._digest_constant = HexInt.parse(constants.pop(), 16)
+        self._digest_iv = HexInt.parse(ivs.pop(), 16)
+
+    # pylint: disable=invalid-name
+    def set_digest_iv(self, iv: int) -> None:
+        """Set the Present digest initialization 64-bit vector."""
+        if iv >> 64:
+            raise ValueError('Invalid digest initialization vector')
+        self._digest_iv = iv
+
+    def set_digest_constant(self, constant: int) -> None:
+        """Set the Present digest finalization 128-bit constant."""
+        if constant >> 128:
+            raise ValueError('Invalid digest finalization constant')
+        self._digest_constant = constant
+
+    @property
+    def has_present_constants(self) -> bool:
+        """Reports whether the Present scrambler constants are known/defined."""
+        return self._digest_iv is not None and self._digest_constant is not None
+
+    def dispatch(self, cfg: OtpMap) -> None:
+        """Dispatch RAW image data into the partitions."""
+        bfp = BytesIO(self._data)
+        for part in cfg.enumerate_partitions():
+            pos = bfp.tell()
+            self._log.debug('%s %d', part.name, pos)
+            part.load(bfp)
+            self._partitions.append(part)
+            self._part_offsets.append(pos)
+        self._part_offsets.append(bfp.tell())
+        # all data bytes should have been dispatched into the partitions
+        assert bfp.tell() == len(self._data), 'Unexpected remaining data bytes'
+        if self._header:
+            data_size = self._header.get('dlength', 0)
+            assert bfp.tell() == data_size, 'Unexpected remaining data bytes'
+
+    def verify(self, show: bool = False) -> bool:
+        """Verify the partition digests, if any."""
+        if any(c is None for c in (self._digest_iv, self._digest_constant)):
+            raise RuntimeError('Missing Present constants')
+        results: dict[str, Optional[bool]] = {}
+        for part in self._partitions:
+            if not part.hw_digest:
+                continue
+            results[part.name] = part.verify(self._digest_iv,
+                                             self._digest_constant)
+        if show:
+            print('HW digests:')
+            width = max(len(x) for x in results)
+            for name, result in results.items():
+                if result is None:
+                    status = 'No digest'
+                elif result:
+                    status = 'OK'
+                else:
+                    status = 'Failed'
+                print(f' * {name:{width}s}: {status}')
+        # any partition with a defined digest should be valid
+        return not any(r is False for r in results.values())
+
+    def decode(self, decode: bool = True, wide: int = 0,
+               ofp: Optional[TextIO] = None, decode_version: bool = True,
+               field_filters: Optional[list[str]] = None) -> None:
+        """Decode the content of the image, one partition at a time.
+
+           :param decode: whether to attempt to decode value whose encoding/
+                    meaning is known
+           :param wide: whether to use compact, truncated long value or emit
+                    the whole value, possibly generating very long lines
+           :param decode_version: whether to decode and report the version
+           :param field_filters: optional filter to select which partitions/
+                    fields to report as a list of <part>:<field> strings, joker
+                    char '*' is supported.
+        """
+        version = self.version
+        if version and decode_version:
+            print(f'OTP image v{version}')
+            if version > 1:
+                print(f' * present iv       {self._digest_iv:016x}')
+                print(f' * present constant {self._digest_constant:032x}')
+        part_filters: dict[str, str] = {}
+        partnames = {p.name for p in self._partitions}
+        for filt in field_filters or []:
+            parts = filt.split(':')
+            if len(parts) > 2:
+                raise ValueError(f"Invalid filter '{filt}'")
+            part_re = f'^{parts[0].replace("*", ".*")}$'
+            field = parts[1] if len(parts) > 1 else '*'
+            for partname in partnames:
+                if not re.match(part_re, partname, re.IGNORECASE):
+                    continue
+                if partname not in part_filters:
+                    part_filters[partname] = set()
+                if field == '*':
+                    # any field would match, discard any existing one
+                    part_filters[partname].clear()
+                part_filters[partname].add(field)
+        for part in self._partitions:
+            if part_filters and part.name not in part_filters:
+                continue
+            base = self._get_partition_bounds(part)[0]
+            part.decode(base, decode, wide, ofp, part_filters.get(part.name))
+
+    def clear_bits(self, bitdefs: Sequence[tuple[int, int]]) -> None:
+        """Clear one or more bits.
+
+           :param bitdefs: a sequence of bits to clear, where each bit is
+                           specified as a 2-uple (offset, bit position)
+                           If bit position is larger than data width for the
+                           specified offset, it indicates an ECC bit to change
+        """
+        self._change_bits(bitdefs, False)
+
+    def set_bits(self, bitdefs: Sequence[tuple[int, int]]) -> None:
+        """Set one or more bits.
+
+           :param bitdefs: a sequence of bits to set, where each bit is
+                           specified as a 2-uple (offset, bit position)
+                           If bit position is larger than data width for the
+                           specified offset, it indicates an ECC bit to change
+        """
+        self._change_bits(bitdefs, True)
+
+    def toggle_bits(self, bitdefs: Sequence[tuple[int, int]]) -> None:
+        """Toggle one or more bits.
+
+           :param bitdefs: a sequence of bits to toggle, where each bit is
+                           specified as a 2-uple (offset, bit position)
+                           If bit position is larger than data width for the
+                           specified offset, it indicates an ECC bit to change
+        """
+        self._change_bits(bitdefs, None)
+
+    def get_partition(self, partition: Union[int, str]) -> OtpPartition:
+        """Retrieve a partition.
+
+           :param partition: the partition to retrieve, either specified as an
+                             index or as the partition name
+           :return: the partition object
+        """
+        return self._retrieve_partition(partition)[1]
+
+    def empty_partition(self, partition: Union[int, str]) -> None:
+        """Empty the whole content of a partition, including its digest if any,
+           and its ECC bits if any.
+
+           :param partition: the partition to empty, either specified as an
+                             index or as the partition name
+        """
+        partix, part = self._retrieve_partition(partition)
+        part.empty()
+        if not part.is_empty:
+            raise RuntimeError(f"Unable to empty partition '{partition}'")
+        start, end = self._reload(partix, False)
+        self._ecc[start // 2:end // 2] = bytes((end-start) // 2)
+
+    def get_field(self, partition: Union[int, str], field: str) -> bytes:
+        """Get the content of a field within a partition.
+
+           :param partition: the name or the index of the partition to erase
+           :param field: the name of the field to erase
+           :return: the content of the field as bytes
+        """
+        part = self._retrieve_partition(partition)[1]
+        return part.get_field(field)
+
+    def change_field(self, partition: Union[int, str], field: str,
+                     value: Union[bytes, bytearray, bool, int, str]) -> None:
+        """Change the content of a field within a partition.
+
+           :param partition: the name or the index of the partition to erase
+           :param field: the name of the field to erase
+           :param value: the new value of the field
+
+           Valid value types depend on the actual partition's field.
+
+           ECC is not automatically updated
+        """
+        partix, part = self._retrieve_partition(partition)
+        part.change_field(field, value)
+        self._reload(partix, True)
+
+    def erase_field(self, partition: Union[int, str], field: str) -> None:
+        """Erase (reset) the content of a field within a partition.
+
+           :param partition: the name or the index of the partition to erase
+           :param field: the name of the field to erase
+
+           ECC is not automatically updated
+        """
+        partix, part = self._retrieve_partition(partition)
+        part.erase_field(field)
+        self._reload(partix, True)
+
+    def change_data(self, addr: int, value: bytes) -> None:
+        """Change an arbitrary sequence of data bytes.
+
+           :param addr: address of the first byte to change
+           :param value: the new data bytes (full replacement)
+        """
+        end = addr + len(value)
+        if end > len(self._data):
+            raise ValueError(f'Invalid address/length: [0x{addr:x}..0x{end:x}] '
+                             f'beyond 0x{len(self._data):x}')
+        self._data[addr:end] = value
+        addr &= ~(self._ecc_granule - 1)
+        for pos in range(addr, end, self._ecc_granule):
+            self._dirty_offsets.append(pos)
+        self._changed = True
+
+    def build_digest(self, partition: Union[int, str], erase: bool) -> None:
+        """Rebuild the digest of a partition from its content.
+
+           :param partition: the name or the index of the partition to erase
+           :param erase: whether to erase any existing digest or combine it
+        """
+        if any(c is None for c in (self._digest_iv, self._digest_constant)):
+            raise RuntimeError('Missing Present constants')
+        partix, part = self._retrieve_partition(partition)
+        part.build_digest(self._digest_iv, self._digest_constant, erase)
+        self._reload(partix, True)
+
+    @staticmethod
+    def bit_parity(data: int) -> int:
+        """Compute the bit parity of an integer, i.e. reduce the vector to a
+           single bit.
+        """
+        data ^= data >> 16  # useless for 16 bits data
+        data ^= data >> 8
+        data ^= data >> 4
+        data ^= data >> 2
+        data ^= data >> 1
+        return data & 1
+
+    def verify_ecc(self, recover: bool) -> tuple[int, int]:
+        """Verify data with ECC.
+
+           :return: 2-uple of count of uncorrectable and corrected errors.
+        """
+        granule = self._ecc_granule
+        bitgran = granule * 8
+        ecclen = (self._ecc_bits + 7) // 8
+        bitcount = bitgran + self._ecc_bits
+        self._log.info('ECC check (%d, %d)', bitcount, bitgran)
+        if len(self._ecc) * granule != len(self._data):
+            self._log.critical('Incoherent ECC size w/ granule %d',
+                               granule)
+        try:
+            ecc_fn = getattr(self.__class__, f'decode_ecc_{bitcount}_{bitgran}')
+        except AttributeError as exc:
+            raise NotImplementedError('ECC function for {self._ecc.bits}'
+                                      'not supported') from exc
+        err_cnt = fatal_cnt = 0
+        updated_parts: set[OtpPartition] = set()
+        for off in range(0, len(self._data), granule):
+            chunk = int.from_bytes(self._data[off:off+granule], 'little')
+            eccoff = off//granule
+            if ecclen == 1:
+                ecc = self._ecc[eccoff]
+            else:
+                ecc = int.from_bytes(self._ecc[eccoff:eccoff+ecclen], 'little')
+            if not chunk and not ecc:
+                continue
+            partition = self._get_partition_at_offset(off)
+            err, fchunk = ecc_fn(chunk, ecc)
+            self._log.debug("ECC check @ %u data:%04x ecc:%02x",
+                            off, chunk, ecc)
+            partinfo = f' in {partition.name}' if partition else ''
+            if err > 0:
+                if not getattr(partition, 'integrity', False):
+                    self._log.warning('Ignoring ECC error%s @ '
+                                      '0x%04x', partinfo, off)
+                    continue
+                if chunk == fchunk:
+                    # error is in ECC bits
+                    self._log.warning('ECC single bit corruption @ 0x%04x%s, '
+                                      'ignored: data:%04x ecc:%02x', off,
+                                      partinfo, chunk, ecc)
+                else:
+                    self._log.warning('ECC recover%s error @ 0x%04x%s: '
+                                      'data:%04x->%04x ecc:%02x',
+                                      'ed' if recover else 'able',
+                                      off, partinfo, chunk, fchunk, ecc)
+                self._dirty_offsets.append(off)
+                if recover:
+                    self._data[off:off+granule] = fchunk.to_bytes(granule,
+                                                                  'little')
+                    self._changed = True
+                    updated_parts.add(partition)
+                err_cnt += 1
+            elif err < 0:
+                self._log.critical('Unrecoverable ECC error @ 0x%04x%s: '
+                                   'data:%04x, ecc:%02x', off, partinfo, chunk,
+                                   ecc)
+                fatal_cnt += 1
+        for part in updated_parts:
+            bounds = self._get_partition_bounds(part)
+            if not bounds:
+                self._log.warning('Unknown partiton bounds for %s, '
+                                  'cannot updated recovered data', part.name)
+                continue
+            bfp = BytesIO(self._data[bounds[0]:bounds[1]])
+            self._log.info('Updating partition %s with recover data', part.name)
+            part.load(bfp)
+        return fatal_cnt, err_cnt
+
+    def fix_ecc(self) -> int:
+        """Fix all ECC regions that have been flagged as defective or whose
+           data have been altered.
+
+           :return: how many ECC locations have been updated
+        """
+        if not self._dirty_offsets:
+            self._log.info('No ECC to fix')
+            return 0
+        dirty_len = len(self._dirty_offsets)
+        self._log.info('%d dirty locations to fix', dirty_len)
+        granule = self._ecc_granule
+        ecclen = (self._ecc_bits + 7) // 8
+        if ecclen != 1:
+            raise NotImplementedError('Multi-byte ECC not yet supported')
+        bitgran = granule * 8
+        bitcount = bitgran + self._ecc_bits
+        try:
+            ecc_fn = getattr(self.__class__,
+                             f'compute_ecc_{bitcount}_{bitgran}')
+        except AttributeError as exc:
+            raise NotImplementedError('ECC function for {self._ecc.bits}'
+                                      'not supported') from exc
+
+        for off in self._dirty_offsets:
+            data = int.from_bytes(self._data[off:off+granule], 'little')
+            new_ecc = ecc_fn(data)
+            eccoff = off//granule
+            old_ecc = self._ecc[eccoff]
+            self._log.info('New ECC @ 0x%04x: 0x%x -> 0x%x', off, old_ecc,
+                           new_ecc)
+            self._ecc[eccoff] = new_ecc
+            self._changed = True
+        self._dirty_offsets.clear()
+        return dirty_len
+
+    @classmethod
+    def compute_ecc_22_16(cls, data: int) -> int:
+        """Generate the 6-bit ECC value from a 16-bit word.
+
+           :param data: 16-bit word
+           :return: 6-bit ECC
+        """
+        data |= cls.bit_parity(data & 0x00ad5b) << 16
+        data |= cls.bit_parity(data & 0x00366d) << 17
+        data |= cls.bit_parity(data & 0x00c78e) << 18
+        data |= cls.bit_parity(data & 0x0007f0) << 19
+        data |= cls.bit_parity(data & 0x00f800) << 20
+        data |= cls.bit_parity(data & 0x1fffff) << 21
+
+        return (data & 0x3f0000) >> 16
+
+    @classmethod
+    def decode_ecc_22_16(cls, data: int, ecc: int) -> tuple[int, int]:
+        """Check and fix 16-bit data with 6 bits ECC.
+
+           :param data: a 16-bit integer
+           :return: 2-uple error, data, where err is
+                    0 if no error has been spotted
+                    1 if a single bit error has been detected and recovered
+                    -1 if a double bit error has been detected and not fixed
+        """
+        assert (data >> 16) == 0
+
+        idata = data | (ecc << 16)
+
+        synd_mask, synd_code = cls.SYNDROME_HAMMING_22_16
+
+        syndrome = sum(1 << b for b, m in enumerate(synd_mask)
+                       if cls.bit_parity(idata & m))
+
+        err = (syndrome >> 5) & 1
+        if not err:
+            err = -int(syndrome & 0x1f != 0)
+        if not err:
+            return 0, data
+
+        odata = sum(1 << b for b, s in enumerate(synd_code)
+                    if (syndrome == s) ^ ((idata >> b) & 1))
+
+        return err, odata
+
+    def document_partitions(self) -> list[str]:
+        """Return the documentation for each 16-bit word.
+
+           Try to match the exact comment syntax from OpenTitan tool.
+
+           :return: the meaning of each half-words
+        """
+        fields: list[str] = []
+        for part in self._partitions:
+            for field in part.document_fields():
+                if not field:
+                    fields.append('unallocated')
+                    continue
+                if ',' in field:
+                    # pylint: disable=cell-var-from-loop
+                    fields.append(split_map_join(', ', field,
+                                  lambda fld: f'{part.name}: {fld}'))
+                    continue
+                fields.append(f'{part.name}: {field}')
+        return fields
+
+    def _load_header(self, bfp: BinaryIO) -> dict[str, Any]:
+        hfmt = self.HEADER_FORMAT
+        fhfmt = ''.join(hfmt.values())
+        # hlength is the length of header minus the two first items (T, L)
+        fhsize = scalc(fhfmt)
+        hdata = bfp.read(fhsize)
+        parts = sunpack(f'<{fhfmt}', hdata)
+        header = dict(zip(hfmt.keys(), parts))
+        magics = set(f'v{k.upper()}'.encode() for k in self.KINDS.values())
+        if header['magic'] not in magics:
+            raise ValueError(f'{bfp.name} is not a QEMU OTP RAW image')
+        self._magic = header['magic']
+        version = header['version']
+        if version > 2:
+            raise ValueError(f'{bfp.name} is not a valid QEMU OTP RAW image')
+        if version > 1:
+            hfmt = self.HEADER_FORMAT_V2_EXT
+            fhfmt = ''.join(hfmt.values())
+            fhsize = scalc(fhfmt)
+            hdata = bfp.read(fhsize)
+            parts = sunpack(f'<{fhfmt}', hdata)
+            headerv2 = dict(zip(hfmt.keys(),
+                                (HexInt(int.from_bytes(v, 'little'))
+                                    for v in parts)))
+            header.update(headerv2)
+        return header
+
+    def _build_header(self) -> bytes:
+        assert self._magic, "File kind unknown"
+        hfmt = self.HEADER_FORMAT
+        # use V2 image format if Present scrambling constants are available,
+        # otherwise use V1
+        use_v2 = bool(self._digest_iv) or bool(self._digest_constant)
+        if use_v2:
+            hfmt.update(self.HEADER_FORMAT_V2_EXT)
+        fhfmt = ''.join(hfmt.values())
+        shfmt = ''.join(hfmt[k] for k in list(hfmt)[:2])
+        # hlength is the length of header minus the two first items (T, L)
+        hlen = scalc(fhfmt)-scalc(shfmt)
+        dlen = (len(self._data)+7) & ~0x7
+        elen = (len(self._ecc)+7) & ~0x7
+        values = {
+            'magic': self._magic, 'hlength': hlen, 'version': 1+int(use_v2),
+            'eccbits': self._ecc_bits, 'eccgran': self._ecc_granule,
+            'dlength': dlen, 'elength': elen
+        }
+        if use_v2:
+            values['digiv'] = self._digest_iv.to_bytes(8, byteorder='little')
+            values['digfc'] = self._digest_constant.to_bytes(16,
+                                                             byteorder='little')
+        args = [values[k] for k in hfmt]
+        header = spack(f'<{fhfmt}', *args)
+        return header
+
+    def _pad(self, bfp: BinaryIO, padsize: Optional[int] = None):
+        if padsize is None:
+            padsize = OtpMap.BLOCK_SIZE
+        tail = bfp.tell() % padsize
+        if tail:
+            bfp.write(bytes(padsize-tail))
+
+    def _change_bits(self, bits: Sequence[tuple[int, int]],
+                     level: Optional[bool]) -> None:
+        granule = self._ecc_granule
+        bitgran = granule * 8
+        bitcount = bitgran + self._ecc_bits
+        ecclen = (self._ecc_bits + 7) // 8
+        for off, bit in bits:
+            off -= off % granule
+            if off > len(self._data):
+                raise ValueError(f'Invalid bit offset: 0x{off:x}')
+            if bit >= bitcount:
+                raise ValueError(f'Invalid bit position: {bit}')
+            if bit >= bitgran:  # ECC bit
+                eccoff = off//granule
+                if ecclen == 1:
+                    ecc = self._ecc[eccoff]
+                else:
+                    ecc = int.from_bytes(self._ecc[eccoff:eccoff+ecclen],
+                                         'little')
+                bitval = 1 << (bit - bitgran)
+                old = ecc
+                if level is None:
+                    ecc ^= bitval
+                elif level:
+                    ecc |= bitval
+                else:
+                    ecc &= ~bitval
+                self._log.info('Changed ECC bit %d @ 0x%x: 0x%x -> 0x%x',
+                               bit-bitgran, off, old, ecc)
+                if ecclen == 1:
+                    self._ecc[eccoff] = ecc
+                else:
+                    self._ecc[eccoff] = ecc.to_bytes(ecclen, 'little')
+                    ecc = int.from_bytes(self._ecc[eccoff:eccoff+ecclen],
+                                         'little')
+                self._changed = True
+            else:  # Data bit
+                chunk = int.from_bytes(self._data[off:off+granule], 'little')
+                bitval = 1 << bit
+                old = chunk
+                if level is None:
+                    chunk ^= bitval
+                elif level:
+                    chunk |= bitval
+                else:
+                    chunk &= ~bitval
+                self._log.info('Changed data bit %d @ 0x%x: 0x%x -> 0x%x',
+                               bit, off, old, chunk)
+                self._data[off:off+granule] = chunk.to_bytes(granule, 'little')
+                self._dirty_offsets.append(off)
+                self._changed = True
+
+    def _get_partition_bounds(self, partref: Union[str, OtpPartition]) \
+            -> Optional[tuple[int, int]]:
+        if isinstance(partref, str):
+            name = partref
+        elif isinstance(partref, OtpPartition):
+            name = partref.name
+        else:
+            raise TypeError('Unsupported partition definition')
+        for pos, (part, start) in enumerate(zip(self._partitions,
+                                                self._part_offsets)):
+            if part.name == name:
+                return (start, self._part_offsets[pos+1])
+        return None
+
+    def _get_partition_at_offset(self, off: int) -> Optional[OtpPartition]:
+        for pos, (part, start) in enumerate(zip(self._partitions,
+                                                self._part_offsets)):
+            if off >= start:
+                end = self._part_offsets[pos+1]
+                if off < end:
+                    return part
+        return None
+
+    def _retrieve_partition(self, partition: Union[int, str]) \
+            -> tuple[int, OtpPartition]:
+        part = None
+        partix = None
+        if isinstance(partition, int):
+            try:
+                part = self._partitions[partition]
+                partix = partition
+            except IndexError:
+                pass
+        elif isinstance(partition, str):
+            partname = partition.lower().replace('_', '')
+            try:
+                partix, part = {(i, p) for i, p in enumerate(self._partitions)
+                                if p.__class__.__name__[:-4].lower() ==
+                                partname}.pop()
+            except KeyError:
+                pass
+        if not part or partix is None:
+            raise ValueError(f"Unknown partition '{partition}'")
+        return partix, part
+
+    def _reload(self, partix: int, flag_dirty: bool = True) -> tuple[int, int]:
+        partition = self._partitions[partix]
+        content = BytesIO()
+        partition.save(content)
+        data = content.getvalue()
+        length = len(data)
+        start = self._part_offsets[partix]
+        granule = self._ecc_granule
+        if flag_dirty:
+            for offset in range(0, length, granule):
+                if self._data[start+offset:start+offset+granule] != \
+                        data[offset:offset+2]:
+                    self._dirty_offsets.append(start+offset)
+        self._data[start:start+length] = data
+        self._changed = True
+        return (start, start+length)
diff --git a/python/qemu/ot/otp/lifecycle.py b/python/qemu/ot/otp/lifecycle.py
new file mode 100644
index 0000000000000..78bc9a6d56845
--- /dev/null
+++ b/python/qemu/ot/otp/lifecycle.py
@@ -0,0 +1,190 @@
+# Copyright (c) 2023-2024 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Lifecycle helpers.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import unhexlify
+from io import StringIO
+from logging import getLogger
+from textwrap import fill
+from typing import Optional, TextIO
+import re
+
+from ot.util.misc import camel_to_snake_case, group, retrieve_git_version
+
+
+class OtpLifecycle:
+    """Decoder for Lifecyle bytes sequences.
+    """
+
+    EXTRA_SLOTS = {
+        'lc_state': {
+            'post_transition': None,
+            'escalate': None,
+            'invalid': None,
+        }
+    }
+
+    def __init__(self):
+        self._log = getLogger('otp.lc')
+        self._sequences: dict[str, dict[str, list[str]]] = {}
+        self._tables: dict[str, dict[str, str]] = {}
+        self._tokens: dict[str, str] = {}
+        self._git_version: Optional[str] = None
+
+    def load(self, svp: TextIO):
+        """Decode LifeCycle information.
+
+           :param svp: System Verilog stream with OTP definitions.
+        """
+        ab_re = (r"\s*parameter\s+logic\s+\[\d+:\d+\]\s+"
+                 r"([ABCDEFGH]\d+|ZRO)\s+=\s+"
+                 r"\d+'(b(?:[01]+)|h(?:[0-9a-fA-F]+));")
+        tbl_re = (r"\s*(LcSt|LcCnt|OwnershipSt|SocDbgSt)(\w+)\s+="
+                  r"\s+\{([^\}]+)\}\s*,?")
+        codes: dict[str, int] = {}
+        sequences: dict[str, dict[str, list[str]]] = {}
+        if svp.name and isinstance(svp.name, str):
+            self._git_version = retrieve_git_version(svp.name)
+        svp = StringIO(svp.read())
+        for line in svp:
+            cmt = line.find('//')
+            if cmt >= 0:
+                line = line[:cmt]
+            line = line.strip()
+            abmo = re.match(ab_re, line)
+            if not sequences and abmo:
+                name = abmo.group(1)
+                sval = abmo.group(2)
+                val = int(sval[1:], 2 if sval.startswith('b') else 16)
+                val = ((val >> 8) & 0xff) | ((val & 0xff) << 8)
+                if name in codes:
+                    self._log.error('Redefinition of %s', name)
+                    continue
+                codes[name] = val
+                continue
+            smo = re.match(tbl_re, line)
+            if smo:
+                kind = smo.group(1).lower()
+                name = smo.group(2)
+                seq = smo.group(3)
+                items = [x.strip() for x in reversed(seq.split(','))]
+                inv = [it for it in items if it not in codes]
+                if inv:
+                    self._log.error('Unknown state seq: %s', ', '.join(inv))
+                if kind not in sequences:
+                    sequences[kind] = {}
+                sequences[kind][name] = items
+                continue
+        self._sequences = sequences
+        svp.seek(0)
+        for tmo in re.finditer(r"\s+parameter\s+lc_token_t\s+(\w+)\s+="
+                               r"\s+\{\s+128'h([0-9A-F]+)\s+\};",
+                               svp.getvalue()):
+            token, value = tmo.group(1), tmo.group(2)
+            if token in self._tokens:
+                raise ValueError(f'Multiple definitions of token {token}')
+            self._tokens[token] = value.lower()
+        for kind, seqs in sequences.items():
+            mkind, conv = {'lcst': ('LC_STATE', str),
+                           'lccnt': ('LC_TRANSITION_CNT', int),
+                           'ownershipst': ('OWNERSHIP', str),
+                           'socdbgst': ('SOC_DBG', str)}[kind]
+            self._tables[mkind] = {}
+            for ref, seq in seqs.items():
+                seq = ''.join((f'{x:04x}'for x in map(codes.get, seq)))
+                self._tables[mkind][seq] = conv(ref)
+
+    def save(self, kind: str, cfp: TextIO, data_mode: bool) -> None:
+        """Save OTP life cycle definitions as a source file.
+
+           :param kind: output format
+           :param cfp: output text stream
+           :param data_mode: whether to output data or template
+        """
+        if kind.lower() != 'qemu':
+            raise NotImplementedError(f'No support for {kind}')
+        msg = f'Section auto-generated with {__name__} module'
+        if self._git_version:
+            print(f'/*\n * {msg}\n * Top version: {self._git_version}\n */',
+                  file=cfp)
+        else:
+            print(f'/* ${msg} */', file=cfp)
+        if data_mode:
+            self._save_data(cfp)
+        else:
+            self._save_template(cfp)
+        print('/* End of auto-generated section */', file=cfp)
+
+    def _save_data(self, cfp: TextIO) -> None:
+        for kind, table in self._tables.items():
+            enum_io = StringIO()
+            array_io = StringIO()
+            count = len(table)
+            length = max(len(x) for x in table.keys())//2
+            print(f'static const char {kind.lower()}s[{count}u][{length}u]'
+                  f' = {{', file=array_io)
+            pad = ' ' * 8
+            for seq, ref in table.items():
+                if isinstance(ref, str):
+                    slot = f'{kind}_{ref}'.upper()
+                    print(f'    {slot},', file=enum_io)
+                else:
+                    slot = f'{ref}u'
+                seqstr = ', '.join((f'0x{b:02x}u' for b in
+                                    reversed(unhexlify(seq))))
+                defstr = fill(seqstr, width=80, initial_indent=pad,
+                              subsequent_indent=pad)
+                print(f'    [{slot}] = {{\n{defstr}\n    }},',
+                      file=array_io)
+            print('};', file=array_io)
+            for extra in self.EXTRA_SLOTS.get(kind.lower(), {}):
+                slot = f'{kind}_{extra}'.upper()
+                print(f'    {slot},', file=enum_io)
+            enum_str = enum_io.getvalue()
+            if enum_str:
+                # likely to be moved to a header file
+                print(f'enum {kind.lower()} {{\n{enum_str}}};\n', file=cfp)
+            print(f'{array_io.getvalue()}', file=cfp)
+
+    def _save_template(self, cfp: TextIO) -> None:
+        print('/* clang-format off */', file=cfp)
+        states = self._sequences.get('lcst') or {}
+        print('static const uint8_t', file=cfp)
+        print('LC_STATES_TPL[LC_STATE_VALID_COUNT][LC_STATE_SLOT_COUNT] = {',
+              file=cfp)
+        for stname, stwords in states.items():
+            print(f'    [LC_STATE_{stname.upper()}] = {{', file=cfp)
+            for wgrp in group(stwords, len(stwords)//2):
+                items = (re.sub(r'(\d+)', r'(\1)', wg) for wg in wgrp)
+                stws = ' '.join(f'{w:<6s}' for w in (f'{i},' for i in items))
+                print(f'        {stws.rstrip()}', file=cfp)
+            print('    },', file=cfp)
+        print('};', file=cfp)
+        print('/* clang-format on */', file=cfp)
+
+    def get_configuration(self, name: str) -> dict[str, str]:
+        """Provide a dictionary of configurable elements for QEMU."""
+        return dict(self._tables.get(name, {}))
+
+    def get_tokens(self, hashed: bool, zero: bool) -> dict[str, str]:
+        """Return a dictionary of parsed tokens."""
+        tokens = {}
+        for token, value in self._tokens.items():
+            sltoken = camel_to_snake_case(token)
+            token_parts = sltoken.split('_')
+            if token_parts[0] == 'rnd':
+                token_parts.pop(0)
+            if token_parts[0] == 'cnst':
+                token_parts.pop(0)
+            if not hashed and token_parts[-1] == 'hashed':
+                continue
+            if not zero and token_parts[-2] == 'zero':
+                continue
+            tkname = '_'.join(token_parts)
+            tokens[tkname] = value
+        return tokens
diff --git a/python/qemu/ot/otp/map.py b/python/qemu/ot/otp/map.py
new file mode 100644
index 0000000000000..bde13c51cad3f
--- /dev/null
+++ b/python/qemu/ot/otp/map.py
@@ -0,0 +1,266 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""OTP map.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from logging import getLogger
+from typing import Any, Iterator, NamedTuple, Optional, TextIO
+
+try:
+    # try to load HJSON if available
+    from hjson import load as hjload
+except ImportError:
+    hjload = None
+
+from ot.util.mbb import MB8_FALSE, MB8_TRUE
+from ot.util.misc import retrieve_git_version, round_up
+
+
+class OtpKeySeed(NamedTuple):
+    """Key seed definition."""
+
+    name: str
+    """Name of the key seed."""
+
+    part_name: str
+    """Partition name where the key seed is stored."""
+
+    offset: int
+    """Offset of the first data byte of the item within the partition."""
+
+    size: int
+    """Length in bytes of the item within the partition."""
+
+
+class OtpMap:
+    """OTP configuration.
+
+       Assume partition file does not contain any error or missing information,
+       it should have been validated by OT tools first.
+    """
+    BLOCK_SIZE = 8
+
+    HARDENED_BOOLEANS = {
+        0x739: True,
+        0x1d4: False
+    }
+
+    MUBI8_BOOLEANS = {
+        MB8_FALSE: False,
+        MB8_TRUE: True,
+        0x00: None
+    }
+
+    def __init__(self):
+        self._log = getLogger('otp.map')
+        self._map: dict = {}
+        self._otp_size = 0
+        self._partitions: list[OtpPartition] = []
+        self._git_version: Optional[str] = None
+
+    def load(self, hfp: TextIO, absorb: Optional[bool] = False) -> None:
+        """Parse a HJSON configuration file, typically otp_ctrl_mmap.hjson
+        """
+        if hjload is None:
+            raise ImportError('HJSON module is required')
+        self._map = hjload(hfp, object_pairs_hook=dict)
+        if hfp.name and isinstance(hfp.name, str):
+            self._git_version = retrieve_git_version(hfp.name)
+        try:
+            otp = self._map['otp']
+        except KeyError as exc:
+            raise ValueError('Unable to find OTP description; '
+                             'wrong input file kind?') from exc
+        self._otp_size = int(otp['width']) * int(otp['depth'])
+        self._generate_partitions()
+        self._compute_locations(absorb)
+
+    @property
+    def partitions(self) -> dict[str, Any]:
+        """Return the partitions (in any)"""
+        return {p['name']: p for p in self._map.get('partitions', [])}
+
+    @property
+    def git_version(self) -> Optional[str]:
+        """Return Git version if known."""
+        return self._git_version
+
+    @classmethod
+    def part_offset(cls, part: dict[str, Any]) -> int:
+        """Get the offset of a partition."""
+        # expect a KeyError if missing
+        return int(part['offset'])
+
+    def enumerate_partitions(self) -> Iterator['OtpPartition']:
+        """Enumerate the partitions in their address order."""
+        return iter(self._partitions)
+
+    def find_field(self, field: str) -> list['OtpPartition']:
+        """Find in which partition(s) a field is defined.
+
+           :param name: the name of the field to locate
+           :return: a list of partitions which contains such a field
+        """
+        return [p for p in self.enumerate_partitions() if p.has_field(field)]
+
+    @property
+    def key_seeds(self) -> list[OtpKeySeed]:
+        """Return the list of defined key seeds.
+
+           :return: a list of OtpKeySeed
+        """
+        key_seeds: list[OtpKeySeed] = []
+        key_seed_suffix = '_KEY_SEED'
+        for part in self.enumerate_partitions():
+            for prop in part.enumerate_properties():
+                if not prop.name.endswith(key_seed_suffix):
+                    continue
+                key_seed = OtpKeySeed(prop.name.removesuffix(key_seed_suffix),
+                                      part.name, prop.offset, prop.size)
+                key_seeds.append(key_seed)
+        return key_seeds
+
+    def _generate_partitions(self) -> None:
+        parts = self._map.get('partitions', [])
+        have_offset = all('offset' in p for p in parts)
+        if not have_offset:
+            # either all or no partition should have an offset definition
+            if any('offset' in p for p in parts):
+                raise RuntimeError('Incoherent offset use in partitions')
+        if have_offset:
+            # if offset are defined, first create a shallow copy of the
+            # partition in sorted order
+            parts = list(sorted(parts, key=OtpMap.part_offset))
+        self._partitions = []
+        for part in parts:
+            # shallow copy of the partition
+            part = dict(part)
+            name = part['name']
+            # remove the name from the dict
+            del part['name']
+            desc = part.get('desc', '').replace('\n', ' ')
+            # remove description from partition
+            if desc:
+                del part['desc']
+            # remove descriptions from items
+            items = {}
+            for item in part.get('items', []):
+                assert isinstance(item, dict)
+                # shallow copy
+                item = dict(item)
+                if 'desc' in item:
+                    del item['desc']
+                # assume name & size are always defined for each item
+                item_name = item['name']
+                del item['name']
+                # absorbing items may have no size
+                item_size = int(item.get('size', 0))
+                item['size'] = item_size
+                assert item_name not in items
+                items[item_name] = item
+            part['items'] = items
+            items_size = sum(it['size'] for it in items.values())
+            # some partitions define their overall size, most don't
+            # if the size is defined, it takes precedence over the sum of its
+            # items
+            part_size = int(part.get('size', '0'))
+            has_digest = any(part.get(f'{k}w_digest') for k in 'sh')
+            if has_digest:
+                items_size += OtpPartition.DIGEST_SIZE
+            has_zero = part.get('zeroizable', False)
+            if has_zero:
+                items_size += OtpPartition.ZER_SIZE
+            if part_size:
+                assert items_size <= part_size
+            else:
+                part_size = round_up(items_size, self.BLOCK_SIZE)
+            # update the partition with is actual size
+            part['size'] = part_size
+            # special ugly case as configuration file defines is_keymgr per item
+            # but RTL defines it per partition for some reason
+            kmm = self._check_keymgr_materials(name, part['items'])
+            if kmm:
+                part[kmm[0]] = kmm[1]
+            prefix = name.title().replace('_', '')
+            partname = f'{prefix}Part'
+            # create an OtpPartition class specialized for the current partition
+            partcls = type(partname, (OtpPartition,),
+                           {'name': name, '__doc__': desc})
+            # instantiate a new partition of this type
+            partobj = partcls(part)
+            self._partitions.append(partobj)
+
+    def _check_keymgr_materials(self, partname: str, items: dict[str, dict]) \
+            -> Optional[tuple[str, bool]]:
+        """Check partition for key manager material fields."""
+        kms: dict[str, bool] = {}
+        kmprefix = 'iskeymgr'
+        for props in items.values():
+            for prop, value in props.items():
+                if prop.startswith(kmprefix):
+                    kind = prop.removeprefix(kmprefix)
+                    if kind not in kms:
+                        kms[kind] = set()
+                    kms[kind].add(value)
+        kind_count = len(kms)
+        if not kind_count:
+            return None
+        if kind_count > 1:
+            raise ValueError(f'Incoherent key manager material definition in '
+                             f'{partname} partition')
+        kind = set(kms).pop()
+        enable = any(kms[kind])
+        return f'{kmprefix}{kind}', enable
+
+    def _compute_locations(self, absorb: bool) -> None:
+        """Update partitions with their location within the OTP map."""
+        absorb_parts = [p for p in self._partitions
+                        if getattr(p, 'absorb', False)]
+        total_size = sum(p.size for p in self._partitions)
+        rem_size = self._otp_size - total_size
+        rem_blocks = rem_size // self.BLOCK_SIZE
+        absorb_count = len(absorb_parts)
+        blk_per_part = rem_blocks // absorb_count
+        extra_blocks = rem_blocks % absorb_count
+        self._log.info("%d bytes (%d blocks) to absorb into %d partition%s",
+                       rem_size, rem_blocks, absorb_count,
+                       's' if absorb_count > 1 else '')
+        for part in absorb_parts:
+            psize = part.size
+            part.size += self.BLOCK_SIZE * blk_per_part
+            if extra_blocks:
+                part.size += self.BLOCK_SIZE
+                extra_blocks -= 1
+            self._log.info('Partition %s size augmented from %u to %u bytes',
+                           part.name, psize, part.size)
+            if absorb:
+                part.dispatch_absorb()
+        for part in self._partitions:
+            part_offset = 0
+            for part in self._partitions:
+                zeroizable = getattr(part, 'zeroizable', False)
+                if zeroizable:
+                    zer_offset = part_offset + part.size - OtpPartition.ZER_SIZE
+                else:
+                    zer_offset = None
+                if part.sw_digest or part.hw_digest:
+                    digest_offset = (part_offset + part.size -
+                                     OtpPartition.DIGEST_SIZE)
+                    if zeroizable:
+                        digest_offset -= OtpPartition.ZER_SIZE
+                else:
+                    digest_offset = None
+                setattr(part, 'offset', part_offset)
+                setattr(part, 'digest_offset', digest_offset)
+                setattr(part, 'zer_offset', zer_offset)
+                part_offset += part.size
+        assert part_offset == self._otp_size, "Unexpected partition offset"
+
+
+# imported here to avoid Python circular dependency issue
+# pylint: disable=cyclic-import
+# pylint: disable=wrong-import-position
+from .partition import OtpPartition  # noqa: E402
diff --git a/python/qemu/ot/otp/partition.py b/python/qemu/ot/otp/partition.py
new file mode 100644
index 0000000000000..b4c4cce26a3f8
--- /dev/null
+++ b/python/qemu/ot/otp/partition.py
@@ -0,0 +1,520 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""OTP partitions.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import hexlify, unhexlify, Error as hexerror
+from io import BytesIO
+from logging import getLogger
+from re import IGNORECASE, match
+from typing import (BinaryIO, Iterator, NamedTuple, Optional, Sequence, TextIO,
+                    Union)
+
+from .lifecycle import OtpLifecycle
+
+try:
+    # try to load Present if available
+    from ot.util.present import Present
+except ImportError:
+    Present = None
+
+
+class OtpPartitionDecoder:
+    """Custom partition value decoder."""
+
+    def decode(self, category: str, seq: str) -> Union[str, int, None]:
+        """Decode a value (if possible)."""
+        raise NotImplementedError('abstract base class')
+
+
+class OtpPartitionItemProp(NamedTuple):
+    """Item/field properties."""
+
+    name: str
+    """Name of the item."""
+
+    offset: int
+    """Offset of the first data byte of the item within the partition."""
+
+    size: int
+    """Length in bytes of the item within the partition."""
+
+    end: int
+    """Offset past the last data byte in the partition, i.e. offset+length."""
+
+    mubi8: bool = False
+    """Whether the field is a known 8-bit boolean value (which differs
+       from hardened boolean values and other complex boolean types)."""
+
+
+class OtpPartition:
+    """Partition abstract base class.
+
+       :param params: initial partition attributes. Those parameters are added
+                      to the instance dictionary, which means that most of the
+                      partition attributes are explicitly listed in __init__
+    """
+    # pylint: disable=no-member
+
+    DIGEST_SIZE = 8  # bytes
+
+    ZER_SIZE = 8  # bytes
+
+    MAX_DATA_WIDTH = 20
+
+    def __init__(self, params):
+        self.__dict__.update(params)
+        self._decoder = None
+        self._log = getLogger('otp.part')
+        self._data = b''
+        self._digest_bytes: Optional[bytes] = None
+        self._zer_bytes: Optional[bytes] = None
+
+    @property
+    def has_digest(self) -> bool:
+        """Check if the partition supports any kind of digest (SW or HW)."""
+        return any(getattr(self, f'{k}w_digest', False) for k in 'sh')
+
+    @property
+    def has_hw_digest(self) -> bool:
+        """Check if the partition supports HW digest."""
+        return getattr(self, 'hw_digest', False)
+
+    @property
+    def is_locked(self) -> bool:
+        """Check if the partition is locked, based on its digest."""
+        return (self.has_digest and self._digest_bytes and
+                self._digest_bytes != bytes(self.DIGEST_SIZE))
+
+    @property
+    def is_zeroizable(self) -> bool:
+        """Check if the partition supports zeroization."""
+        return getattr(self, 'zeroizable', False)
+
+    @property
+    def is_absorb(self) -> bool:
+        """Check if the partition can use unassigned storage."""
+        return getattr(self, 'absorb', False)
+
+    @property
+    def is_empty(self) -> bool:
+        """Report if the partition is empty."""
+        if self._digest_bytes and sum(self._digest_bytes):
+            return False
+        if self._zer_bytes and sum(self._zer_bytes):
+            return False
+        return sum(self._data) == 0
+
+    def __repr__(self) -> str:
+        return repr(self.__dict__)
+
+    def load(self, bfp: BinaryIO) -> None:
+        """Load the content of the partition from a binary stream."""
+        data = bfp.read(self.size)
+        if len(data) != self.size:
+            raise IOError(f'{self.name} Cannot load {self.size} from stream')
+        zer_data = None
+        if self.is_zeroizable:
+            data, zer_data = data[:-self.ZER_SIZE], data[-self.ZER_SIZE:]
+            self._zer_bytes = zer_data
+        if self.has_digest:
+            data, digest = data[:-self.DIGEST_SIZE], data[-self.DIGEST_SIZE:]
+            self._digest_bytes = digest
+        self._data = data
+
+    def save(self, bfp: BinaryIO) -> None:
+        """Save the content of the partition to a binary stream."""
+        pos = bfp.tell()
+        bfp.write(self._data)
+        bfp.write(self._digest_bytes)
+        bfp.write(self._zer_bytes)
+        size = bfp.tell() - pos
+        if size != self.size:
+            raise RuntimeError(f"Failed to save partition {self.name} content")
+
+    def verify(self, digest_iv: int, digest_constant: int) -> Optional[bool]:
+        """Verify if the digest matches the content of the partition, if any.
+        """
+        self._log.debug('Verify %s', self.name)
+        if not self.is_locked:
+            self._log.info('%s has no stored digest', self.name)
+            return None
+        return self.check_digest(digest_iv, digest_constant)
+
+    def check_digest(self, digest_iv: int, digest_constant: int) \
+            -> Optional[bool]:
+        """Verify if the digest matches the content of the partition."""
+        # don't ask about the byte order. Something is inverted somewhere, and
+        # this is all that matters for now
+        assert self._digest_bytes is not None
+        idigest = int.from_bytes(self._digest_bytes, byteorder='little')
+        if idigest == 0:
+            self._log.warning('Partition %s digest empty', self.name)
+            return None
+        lidigest = self.compute_digest(self._data, digest_iv, digest_constant)
+        if lidigest != idigest:
+            self._log.error('Partition %s digest mismatch (%016x/%016x)',
+                            self.name, lidigest, idigest)
+            return False
+        self._log.info('Partition %s digest match (%016x)', self.name, lidigest)
+        return True
+
+    @classmethod
+    def compute_digest(cls, data: bytes, digest_iv: int, digest_constant: int) \
+            -> int:
+        """Compute the HW digest of the partition."""
+        if Present is None:
+            raise RuntimeError('Cannot check digest, Present module not found')
+        block_sz = OtpMap.BLOCK_SIZE
+        assert block_sz == Present.BLOCK_BIT_SIZE // 8
+        if len(data) % block_sz != 0:
+            # this case is valid but not yet implemented (paddding)
+            raise RuntimeError('Invalid partition size')
+        block_count = len(data) // block_sz
+        if block_count & 1:
+            data = b''.join((data, data[-block_sz:]))
+        state = digest_iv
+        for offset in range(0, len(data), 16):
+            chunk = data[offset:offset+16]
+            b128 = int.from_bytes(chunk, byteorder='little')
+            present = Present(b128)
+            tmp = present.encrypt(state)
+            state ^= tmp
+        present = Present(digest_constant)
+        state ^= present.encrypt(state)
+        return state
+
+    def set_decoder(self, decoder: OtpPartitionDecoder) -> None:
+        """Assign a custom value decoder."""
+        self._decoder = decoder
+
+    def decode(self, base: Optional[int], decode: bool = True, wide: int = 0,
+               ofp: Optional[TextIO] = None,
+               filters: Optional[Sequence[str]] = None) -> None:
+        """Decode the content of the partition."""
+        buf = BytesIO(self._data)
+        if ofp:
+            def emit(fmt, *args):
+                print(f'%-52s %s {fmt}' % args, file=ofp)
+        else:
+            def emit(fmt, *args):
+                fmt = f'%-52s %s {fmt}'
+                self._log.info(fmt, *args)
+        pname = self.name
+        offset = 0
+        soff = 0
+        if filters:
+            fre = '|'.join(f.replace('*', '.*') for f in filters)
+            filter_re = f'^({fre})$'
+        else:
+            filter_re = r'.*'
+        for itname, itdef in self.items.items():
+            itsize = itdef['size']
+            if not itsize:
+                self._log.error('Zero sized %s.%s', self.name, itname)
+            itvalue = buf.read(itsize)
+            soff = f'[{f"{base+offset:d}":>5s}]' if base is not None else ''
+            offset += itsize
+            prefix = f'{pname}_'
+            name = f'{pname}:{itname.removeprefix(prefix)}'
+            if not match(filter_re, itname, IGNORECASE):
+                continue
+            if itsize > 8:
+                rvalue = bytes(reversed(itvalue))
+                sval = hexlify(rvalue).decode()
+                if decode and self._decoder:
+                    dval = self._decoder.decode(itname, sval)
+                    if dval is not None:
+                        emit('(decoded) %s', name, soff, dval)
+                        continue
+                ssize = f'{{{itsize}}}'
+                if not sum(itvalue) and wide < 2:
+                    if decode:
+                        emit('%5s (empty)', name, soff, ssize)
+                    else:
+                        emit('%5s 0...', name, soff, ssize)
+                else:
+                    if not wide and itsize > self.MAX_DATA_WIDTH:
+                        sval = f'{sval[:self.MAX_DATA_WIDTH*2]}...'
+                    emit('%5s %s', name, soff, ssize, sval)
+            else:
+                ival = int.from_bytes(itvalue, 'little')
+                if decode:
+                    if itdef.get('ismubi'):
+                        emit('(decoded) %s',
+                             name, soff,
+                             str(OtpMap.MUBI8_BOOLEANS.get(ival, ival)))
+                        continue
+                    if itsize == 4 and ival in OtpMap.HARDENED_BOOLEANS:
+                        emit('(decoded) %s',
+                             name, soff, str(OtpMap.HARDENED_BOOLEANS[ival]))
+                        continue
+                emit('%x', name, soff, ival)
+        offset = (offset + OtpMap.BLOCK_SIZE - 1) & ~(OtpMap.BLOCK_SIZE - 1)
+        rpos = self.size
+        dsoff = zsoff = f'[{"":5s}]'
+        if self.is_zeroizable:
+            rpos -= self.ZER_SIZE
+            if base is not None:
+                zsoff = f'[{f"{base+rpos:d}":>5s}]'
+        if self.has_digest:
+            rpos -= self.DIGEST_SIZE
+            if base is not None:
+                dsoff = f'[{f"{base+rpos:d}":>5s}]'
+        if self._digest_bytes is not None:
+            if match(filter_re, 'DIGEST', IGNORECASE):
+                if not sum(self._digest_bytes) and decode:
+                    val = '(empty)'
+                else:
+                    val = hexlify(self._digest_bytes).decode()
+                ssize = f'{{{len(self._digest_bytes)}}}'
+                emit('%5s %s', f'{pname}:DIGEST', dsoff, ssize, val)
+        if self._zer_bytes is not None:
+            if match(filter_re, 'ZER', IGNORECASE):
+                if not sum(self._zer_bytes) and decode:
+                    val = '(empty)'
+                else:
+                    val = hexlify(self._zer_bytes).decode()
+                ssize = f'{{{len(self._zer_bytes)}}}'
+                emit('%5s %s', f'{pname}:ZER', zsoff, ssize, val)
+        if offset != rpos:
+            self._log.warning('%s: offset %d, size %d', self.name, offset, rpos)
+
+    def dispatch_absorb(self) -> None:
+        """Request the partition to resize its fields."""
+        if not self.is_absorb:
+            raise RuntimeError('Partition cannot absorb free space')
+        if not self.items:
+            # no field to dispatch spare space into
+            return
+        absorb_fields = {n: v for n, v in self.items.items()
+                         if v.get('absorb', False)}
+        avail_size = self.size
+        if self.has_digest:
+            avail_size -= self.DIGEST_SIZE
+        if self.is_zeroizable:
+            avail_size -= self.ZER_SIZE
+        avail_blocks = avail_size // OtpMap.BLOCK_SIZE
+        if not absorb_fields:
+            # This version of OTP defines 'absorb' as a partition property but
+            # does not document which fields can absorb the extra space.
+            # Allocate it to the last field of the partition.
+            last = list(self.items)[-1]
+            absorb_fields = {last: self.items[last]}
+            self._log.warning("No absorption defined for partition %s, "
+                              "assigning to last field '%s'", self.name, last)
+        absorb_count = len(absorb_fields)
+        blk_per_field = avail_blocks // absorb_count
+        extra_blocks = avail_blocks % absorb_count
+        self._log.info("%s: %d bytes (%d blocks) to absorb into %d field%s",
+                       self.name, avail_size, avail_blocks, absorb_count,
+                       's' if absorb_count > 1 else '')
+        for itname, itfield in absorb_fields.items():
+            fsize = itfield['size']
+            itfield['size'] += OtpMap.BLOCK_SIZE * blk_per_field
+            if extra_blocks:
+                itfield['size'] += OtpMap.BLOCK_SIZE
+                extra_blocks -= 1
+            self._log.info('%s.%s size augmented from %u to %u bytes',
+                           self.name, itname, fsize, itfield['size'])
+
+    def empty(self) -> None:
+        """Empty the partition, including its digest if any."""
+        self._data = bytes(len(self._data))
+        if self.has_digest:
+            self._digest_bytes = bytes(self.DIGEST_SIZE)
+
+    def change_field(self, field: str,
+                     value: Union[bytes, bytearray, bool, int, str]) -> None:
+        """Change the content of a field.
+
+           :param field: the name of the field to erase
+           :param value: the new value of the field
+
+           Valid value types depend on the field.
+        """
+        prop = self._retrieve_properties(field)
+        if isinstance(value, str):
+            value = value.encode('utf8')
+        elif isinstance(value, bytearray):
+            value = bytes(value)
+        if isinstance(value, bytes):
+            size = len(value)
+            if size > prop.size:
+                raise ValueError(f'{self.name}:{field} value cannot fit in '
+                                 f'partition field')
+            if size < prop.size:
+                # pad value with NUL bytes
+                value = b''.join((value, bytes(prop.size-size)))
+        elif isinstance(value, bool):
+            if not prop.mubi8:
+                bool_type = 'hardened'
+                bool_size = 4
+            else:
+                bool_type = 'mubi8'
+                bool_size = 1
+            if prop.size != bool_size:
+                raise ValueError(f'{self.name}:{field} does not expect a '
+                                 f'boolean value')
+            bool_map = getattr(OtpMap, f'{bool_type.upper()}_BOOLEANS')
+            ivalue = {v: k for k, v in bool_map.items()}[value]
+            value = ivalue.to_bytes(length=bool_size, byteorder='little')
+        elif isinstance(value, int):
+            try:
+                value = value.to_bytes(length=prop.size, byteorder='little')
+            except ValueError as exc:
+                raise ValueError(f'{self.name}:{field} cannot encode {value}') \
+                    from exc
+        self._log.info('Updating 0x%x..0x%x from %s', prop.offset, prop.end,
+                       self.name)
+        self._data = b''.join((self._data[:prop.offset], value,
+                               self._data[prop.end:]))
+
+    def decode_field(self, field: str) -> None:
+        """Decode the content of a field.
+
+           :param field: the name of the field to decode
+           :param value: the value to decode
+        """
+        if not self._decoder:
+            return None
+        val = self.get_field(field)
+        sval = hexlify(bytes(reversed(val)))
+        return self._decoder.decode(field, sval).upper()
+
+    def get_field(self, field: str) -> bytes:
+        """Retrieve the content of a field.
+
+           :param field: the name of the field to retrieve
+        """
+        prop = self._retrieve_properties(field)
+        return self._data[prop.offset:prop.end]
+
+    def erase_field(self, field: str) -> None:
+        """Erase (reset) the content of a field.
+
+           :param field: the name of the field to erase
+        """
+        prop = self._retrieve_properties(field)
+        self._log.info('Erasing 0x%x..0x%x from %s', prop.offset, prop.end,
+                       self.name)
+        self._data = b''.join((self._data[:prop.offset], bytes(prop.size),
+                               self._data[prop.end:]))
+
+    def build_digest(self, digest_iv: int, digest_constant: int, erase: bool) \
+            -> None:
+        """Rebuild the digest of a partition from its content.
+
+           :param erase: whether to erase any existing digest or combine it
+        """
+        if not self.has_hw_digest:
+            raise ValueError(f'Partition {self.name} does not have a HW digest')
+        assert self._digest_bytes is not None
+        digest = self.compute_digest(self._data, digest_iv, digest_constant)
+        self._log.info('New partition %s digest: %016x', self.name, digest)
+        digest_len = len(self._digest_bytes)
+        if erase:
+            self._digest_bytes = bytes(digest_len)
+        bdigest = digest.to_bytes(length=digest_len, byteorder='little')
+        self._digest_bytes = bytes((a | b)
+                                   for a, b in zip(self._digest_bytes, bdigest))
+
+    def has_field(self, field: str) -> bool:
+        """Tell whether the partition has a field by its name.
+
+           :param field: the name of the field to locate
+           :return: true if the field is defined, false otherwise
+        """
+        try:
+            self._retrieve_properties(field)
+            return True
+        except ValueError:
+            return False
+
+    def enumerate_properties(self) -> Iterator[OtpPartitionItemProp]:
+        """Enumerate all partition properties."""
+        offset = 0
+        itsize = 0
+        mubi8 = False
+        for itname, itdef in self.items.items():
+            itsize = itdef['size']
+            mubi8 = itsize == 1 and itdef.get('ismubi', False)
+            yield OtpPartitionItemProp(itname, offset, itsize, offset + itsize,
+                                       mubi8)
+            offset += itsize
+
+    def document_fields(self) -> list[str]:
+        """Return the documentation of each 16-bit word.
+
+           :return: the meaning of each half-words
+        """
+        fields: list[str] = []
+        offset = 0
+        for itname, itdef in self.items.items():
+            itsize = itdef['size']
+            if itsize < 2:
+                if offset & 1:
+                    fields[-1] = f'{fields[-1]}, {itname}'
+                else:
+                    fields.append(itname)
+            else:
+                assert itsize & 1 == 0
+            span = itsize // 2
+            fields.extend([itname] * span)
+            offset += itdef['size']
+        hsize = len(self._data)
+        if offset < hsize:
+            if offset & 1:
+                offset += 1
+            fields.extend([''] * ((hsize - offset) // 2))
+        if self.has_digest:
+            fields.extend([f'{self.name}_DIGEST'] * (self.DIGEST_SIZE // 2))
+            if self.is_zeroizable:
+                fields.extend([f'{self.name}_ZER'] * (self.ZER_SIZE // 2))
+        return fields
+
+    def _retrieve_properties(self, field: str) -> OtpPartitionItemProp:
+        is_digest = self.has_digest and field.upper() == 'DIGEST'
+        if not is_digest:
+            if field not in self.items:
+                # for some reason, some partitions are defined with their own
+                # partition name as a prefix for their field name, some other
+                # are not; try to workaround these inconsistent definitions
+                search_field = f'{self.name}_{field}'
+                if search_field not in self.items:
+                    raise ValueError(f"No such field: '{field}'")
+            else:
+                search_field = field
+        offset = 0
+        itsize = 0
+        mubi8 = False
+        for itname, itdef in self.items.items():
+            itsize = itdef['size']
+            if itname == search_field:
+                mubi8 = itsize == 1 and itdef.get('ismubi', False)
+                break
+            offset += itsize
+        end = offset + itsize
+        return OtpPartitionItemProp(field, offset, itsize, end, mubi8)
+
+
+class OtpLifecycleExtension(OtpLifecycle, OtpPartitionDecoder):
+    """Decoder for Lifecyle bytes sequences.
+    """
+
+    def decode(self, category: str, seq: str) -> Union[str, int, None]:
+        try:
+            iseq = hexlify(bytes(reversed(unhexlify(seq)))).decode()
+        except (ValueError, TypeError, hexerror) as exc:
+            self._log.error('Unable to parse LC data: %s', str(exc))
+            return None
+        return self._tables.get(category, {}).get(iseq, None)
+
+
+# imported here to avoid Python circular dependency issue
+# pylint: disable=cyclic-import
+# pylint: disable=wrong-import-position
+from .map import OtpMap  # noqa: E402
diff --git a/python/qemu/ot/otp/secret.py b/python/qemu/ot/otp/secret.py
new file mode 100644
index 0000000000000..b565e724db950
--- /dev/null
+++ b/python/qemu/ot/otp/secret.py
@@ -0,0 +1,65 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""OTP secret helpers.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from typing import Any, Optional, Union
+import re
+
+from ot.util.misc import camel_to_snake_case
+
+OtParamRegex = str
+"""Definition of a parameter to seek and how to shorten it."""
+
+
+class OtpSecretConstants:
+    """OTP secret constant helper.
+    """
+
+    @classmethod
+    def load_values(cls, module: dict[str, Any],
+                    odict: Union[dict[str, str],
+                                 dict[Optional[int], dict[str, str]]],
+                    multi: bool, *regexes: tuple[OtParamRegex, ...]) \
+            -> None:
+        """Load values from OTP secret dictionary.
+
+           :param module: the OTP secret module source
+           :param odict: output dictionary. If multi is false, a simple
+                         key-value map is generated, otherwise a map of indices
+                         as keys for a sub dictionary of key-values is generated
+           :param multi: whether to generate a single level or index-based map.
+           :param regexes: one of more regular expression to match in the
+                           input module. First group define the part of the
+                           matched entry to keep as key names, which are
+                           converted to snake cases.
+        """
+        modname = module.get('name')
+        if not modname:
+            return
+        for params in module.get('param_list', []):
+            if not isinstance(params, dict):
+                continue
+            for regex in regexes:
+                pmo = re.match(regex, params['name'])
+                if not pmo:
+                    continue
+                value = params.get('default')
+                if not value:
+                    continue
+                if value.startswith('0x'):
+                    value = value[2:]
+                if len(value) & 1:
+                    value = f'0{value}'
+                kname = camel_to_snake_case(pmo.group(1))
+                if multi:
+                    imo = re.search(r'(\d+)$', modname)
+                    idx = int(imo.group(1)) if imo else None
+                    if idx not in odict:
+                        odict[idx] = {}
+                    odict[idx][kname] = value
+                else:
+                    odict[kname] = value
diff --git a/python/qemu/ot/pyot/__init__.py b/python/qemu/ot/pyot/__init__.py
new file mode 100644
index 0000000000000..05ba5db16590b
--- /dev/null
+++ b/python/qemu/ot/pyot/__init__.py
@@ -0,0 +1,10 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""OpenTitan unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+DEFAULT_TIMEOUT = 60  # seconds
+DEFAULT_TIMEOUT_FACTOR = 1.0
diff --git a/python/qemu/ot/pyot/context.py b/python/qemu/ot/pyot/context.py
new file mode 100644
index 0000000000000..1f2c242d78800
--- /dev/null
+++ b/python/qemu/ot/pyot/context.py
@@ -0,0 +1,181 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Test context for OpenTitan unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from logging import getLogger, DEBUG, ERROR, INFO
+from os import environ, pardir, sep
+from os.path import basename, dirname, normpath, relpath
+from subprocess import Popen, PIPE, TimeoutExpired
+from threading import Event
+from typing import Optional
+
+import re
+
+from .util import LogMessageClassifier
+from .worker import ContextWorker
+
+
+class ExecContext:
+    """Execution context for test executer session.
+
+       Execute commands before, while and after test executer runs.
+
+       :param test_name: the name of the test executer should execute
+       :param ex_cmd: the host command and argument to execute the test
+       :param context: the contex configuration for the current test
+    """
+
+    def __init__(self, test_name: str, ex_cmd: list[str],
+                 context: dict[str, list[str]],
+                 env: Optional[dict[str, str]] = None):
+        # pylint: disable=too-many-arguments
+        self._clog = getLogger('pyot.ctx')
+        self._test_name = test_name
+        self._ex_cmd = ex_cmd
+        self._context = context
+        self._env = env or {}
+        self._workers: list[Popen] = []
+        self._first_error: str = ''
+        self._classifier = LogMessageClassifier()
+
+    @property
+    def test_name(self) -> str:
+        """Provide the test name."""
+        return self._test_name
+
+    def execute(self, ctx_name: str, code: int = 0,
+                sync: Optional[Event] = None) -> None:
+        """Execute all commands, in order, for the selected context.
+
+           Synchronous commands are executed in order. If one command fails,
+           subsequent commands are not executed.
+
+           Background commands are started in order, but a failure does not
+           stop other commands.
+
+           :param ctx_name: the name of the execution context
+           :param code: a previous error completion code, if any
+           :param sync: an optional synchronisation event to start up the
+                        execution
+        """
+        ctx = self._context.get(ctx_name, None)
+        if ctx_name == 'post' and code:
+            self._clog.info("Discard execution of '%s' commands after failure "
+                            "of '%s'", ctx_name, self._test_name)
+            return
+        env = dict(environ)
+        env.update(self._env)
+        if self._ex_cmd:
+            env['PATH'] = ':'.join((env['PATH'], dirname(self._ex_cmd[0])))
+        if ctx:
+            for cmd in ctx:
+                bkgnd = ctx_name == 'with'
+                timeout = 5
+                optmo = re.match(r'^(.*)(?:(&)|(!)(?:@(\d+))?)$', cmd)
+                if optmo:
+                    cmd = optmo.group(1)
+                    if optmo.group(2):
+                        bkgnd = True
+                    elif optmo.group(3):
+                        bkgnd = False
+                        if optmo.group(4):
+                            timeout = int(optmo.group(4))
+                cmd = normpath(cmd.rstrip())
+                if bkgnd:
+                    if ctx_name == 'post':
+                        raise ValueError(f"Cannot execute background command "
+                                         f"in [{ctx_name}] context for "
+                                         f"'{self._test_name}'")
+                    rcmd = relpath(cmd)
+                    if rcmd.startswith(pardir):
+                        rcmd = cmd
+                    rcmd = ' '.join(p if not p.startswith(sep) else basename(p)
+                                    for p in rcmd.split(' '))
+                    self._clog.info('Execute "%s" in background for [%s] '
+                                    'context', rcmd, ctx_name)
+                    worker = ContextWorker(cmd, env, sync)
+                    worker.run()
+                    self._workers.append(worker)
+                else:
+                    if sync:
+                        self._clog.debug('Synchronization ignored')
+                    cmd = normpath(cmd.rstrip())
+                    rcmd = relpath(cmd)
+                    if rcmd.startswith(pardir):
+                        rcmd = cmd
+                    rcmd = ' '.join(p if not p.startswith(sep) else basename(p)
+                                    for p in rcmd.split(' '))
+                    self._clog.info('Execute "%s" in sync for [%s] context',
+                                    rcmd, ctx_name)
+                    # pylint: disable=consider-using-with
+                    proc = Popen(cmd, bufsize=1, stdout=PIPE, stderr=PIPE,
+                                 shell=True, env=env, encoding='utf-8',
+                                 errors='ignore', text=True)
+                    ret = 0
+                    try:
+                        outs, errs = proc.communicate(timeout=timeout)
+                        ret = proc.returncode
+                    except TimeoutExpired:
+                        proc.kill()
+                        outs, errs = proc.communicate()
+                        ret = proc.returncode
+                    for sfp, deflevel in zip((outs, errs),
+                                             (DEBUG, ERROR if ret else INFO)):
+                        for line in sfp.split('\n'):
+                            line = line.strip()
+                            if line:
+                                loglevel = self._classifier.classify(line,
+                                                                     deflevel)
+                                self._clog.log(loglevel, line)
+                                if loglevel >= ERROR and not self._first_error:
+                                    self._first_error = line
+                    if not self._first_error:
+                        self._first_error = errs.split('\n', 1)[0]
+                    if ret:
+                        self._clog.error("Fail to execute '%s' command for "
+                                         "'%s'", cmd, self._test_name)
+                        errmsg = self._first_error or \
+                            f'Cannot execute [{ctx_name}] command'
+                        raise OSError(ret, errmsg)
+
+    def check_error(self) -> int:
+        """Check if any background worker exited in error.
+
+           :return: a non-zero value on error
+        """
+        for worker in self._workers:
+            ret = worker.exit_code()
+            if not ret:
+                continue
+            if not self._first_error:
+                self._first_error = worker.first_error
+            self._clog.error("%s exited with %d", worker.command, ret)
+            return ret
+        return 0
+
+    @property
+    def first_error(self):
+        """Return the message of the first error, if any."""
+        return self._first_error
+
+    def finalize(self) -> int:
+        """Terminate any running background command, in reverse order.
+
+           :return: a non-zero value if one or more workers have reported an
+                    error
+        """
+        rets = {0}
+        while self._workers:
+            worker = self._workers.pop()
+            ret = worker.stop()
+            rets.add(ret)
+            if ret:
+                self._clog.warning("Command '%s' has failed for '%s': %d",
+                                   worker.command, self._test_name, ret)
+                if not self._first_error:
+                    self._first_error = worker.first_error
+        return max(rets)
diff --git a/python/qemu/ot/pyot/executer.py b/python/qemu/ot/pyot/executer.py
new file mode 100644
index 0000000000000..f7d79151cce05
--- /dev/null
+++ b/python/qemu/ot/pyot/executer.py
@@ -0,0 +1,565 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Test executer for OpenTitan unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import Namespace
+from collections import defaultdict
+from csv import writer as csv_writer
+from fnmatch import fnmatchcase
+from glob import glob
+from logging import DEBUG as LOG_DEBUG, INFO as LOG_INFO, getLogger, FileHandler
+from os import curdir, environ, getcwd, sep
+from os.path import (abspath, basename, dirname, isabs, isfile,
+                     join as joinpath, normpath)
+from traceback import format_exc
+from typing import Any, Iterator, Optional
+
+import re
+import sys
+
+from ot.util.file import guess_file_type
+from ot.util.log import flush_memory_loggers
+from ot.util.misc import EasyDict, alphanum_key, flatten
+
+from . import DEFAULT_TIMEOUT, DEFAULT_TIMEOUT_FACTOR
+from .context import ExecContext
+from .filemgr import FileManager
+from .util import ExecTime, TestCandidate, TestResult
+from .wrapper import Wrapper
+
+
+class Executer:
+    """Test execution sequencer.
+
+       :param tfm: file manager that tracks temporary files
+       :param config: configuration dictionary
+       :param args: parsed arguments
+    """
+
+    CONTEXT_ERROR = 99
+
+    RESULT_MAP = {
+        -1: 'SKIPPED',
+        0: 'PASS',
+        1: 'ERROR',
+        6: 'ABORT',
+        11: 'CRASH',
+        Wrapper.GUEST_ERROR_OFFSET - 1: 'GUEST_ESC',
+        Wrapper.GUEST_ERROR_OFFSET + 1: 'FAIL',
+        98: 'UNEXP_SUCCESS',
+        CONTEXT_ERROR: 'CONTEXT',
+        # convention: exit code in [100..115] range report uncaught exceptions
+        100: 'INST_ADDR_MISALIGN',
+        101: 'INST_ACCESS_FAULT',
+        102: 'INST_ILLEGAL',
+        103: 'BREAKPOINT',
+        104: 'LOAD_ADDR_ALIGN',
+        105: 'LOAD_ACCESS_FAULT',
+        106: 'STORE_ADDR_ALIGN',
+        107: 'STORE_ACCESS_FAULT',
+        108: 'ECALL_U_MODE',
+        109: 'ECALL_S_MODE',
+        110: 'ECALL_H_MODE',
+        111: 'ECALL_M_MODE',
+        112: 'INST_PAGE_FAULT',
+        113: 'LOAD_PAGE_FAULT',
+        115: 'STORE_PAGE_FAULT',
+        # end of RISC-V exception converted to exit code
+        124: 'TIMEOUT',
+        125: 'DEADLOCK',
+        126: 'CONTEXT',
+        Wrapper.NO_MATCH_RETURN_CODE: 'UNKNOWN',
+    }
+
+    DEFAULT_START_DELAY = 1.0
+    """Default start up delay to let QEMU initialize before connecting the
+       virtual UART port.
+    """
+
+    DEFAULT_SERIAL_PORT = 'serial0'
+    """Default VCP name."""
+
+    WRAPPER = Wrapper
+    """Default wrapper."""
+
+    def __init__(self, tfm: FileManager, config: dict[str, any],
+                 args: Namespace):
+        self._log = getLogger('pyot.exec')
+        self._tfm = tfm
+        self._config = config
+        self._args = args
+        self._argdict: dict[str, Any] = {}
+        self._qemu_cmd: list[str] = []
+        self._suffixes = []
+        self._virtual_tests: dict[str, str] = {}
+        if hasattr(self._args, 'opts'):
+            setattr(self._args, 'global_opts', getattr(self._args, 'opts'))
+            setattr(self._args, 'opts', [])
+        else:
+            setattr(self._args, 'global_opts', [])
+
+    def build(self) -> None:
+        """Build initial QEMU arguments.
+
+           :raise ValueError: if some argument is invalid
+        """
+        exec_info = self._build_command(self._args)
+        self._qemu_cmd = exec_info.command
+        self._argdict = dict(self._args.__dict__)
+        self._suffixes = []
+        suffixes = self._config.get('suffixes', [])
+        if not isinstance(suffixes, list):
+            raise ValueError('Invalid suffixes sub-section')
+        self._suffixes.extend(suffixes)
+
+    def enumerate_tests(self) -> Iterator[str]:
+        """Enumerate tests to execute.
+        """
+        self._argdict = dict(self._args.__dict__)
+        for candidate in sorted(self._build_test_list()):
+            tst, reason = candidate.name, candidate.reason
+            tpath = self._virtual_tests.get(tst)
+            ttype = guess_file_type(tpath or tst)
+            rpath = f' [{basename(tpath)}]' if tpath else ''
+            discarded = f' {{discarded: {reason}}}' if reason else ''
+            yield f'{basename(tst)} ({ttype}){rpath}{discarded}'
+
+    def run(self, debug: bool, allow_no_test: bool) -> int:
+        """Execute all requested tests.
+
+           :return: success or the code of the first encountered error
+        """
+        log_classifiers = self._config.get('logclass', {})
+        qot = self.WRAPPER(log_classifiers, debug)
+        ret = 0
+        results = defaultdict(int)
+        result_file = self._argdict.get('result')
+        # pylint: disable=consider-using-with
+        cfp = open(result_file, 'wt', encoding='utf-8') if result_file else None
+        try:
+            csv = csv_writer(cfp) if cfp else None
+            if csv:
+                csv.writerow((x.title() for x in TestResult._fields))
+            app = self._argdict.get('exec')
+            if app:
+                assert 'timeout' in self._argdict
+                timeout = int(float(self._argdict.get('timeout')) *
+                              float(self._argdict.get('timeout_factor',
+                                                      DEFAULT_TIMEOUT_FACTOR)))
+                self._log.debug('Execute %s', basename(self._argdict['exec']))
+                adef = EasyDict(command=self._qemu_cmd, timeout=timeout,
+                                start_delay=self.DEFAULT_START_DELAY,
+                                asan=self._argdict.get('asan', False))
+                ret, xtime, err = qot.run(adef)
+                results[ret] += 1
+                sret = self.RESULT_MAP.get(ret, ret)
+                icount = self._argdict.get('icount')
+                if csv:
+                    csv.writerow(TestResult(self.get_test_radix(app), sret,
+                                            xtime, icount, err))
+                    cfp.flush()
+            tests = self._build_test_list()
+            tcount = len(tests)
+            self._log.info('Found %d tests to execute', tcount)
+            if not tcount and not allow_no_test:
+                self._log.error('No test can be run')
+                return 1
+            targs = None
+            temp_files = {}
+            for tpos, tcand in enumerate(tests, start=1):
+                test, reason = tcand.name, tcand.reason
+                test_name = self.get_test_radix(test)
+                vcplogfile = None
+                if reason:
+                    tret = -1
+                    sret = self.RESULT_MAP[tret]
+                    if csv:
+                        self._log.info('[TEST %s] (%d/%d) skipped',
+                                       test_name, tpos, tcount)
+                        csv.writerow(TestResult(test_name, sret, '',
+                                                '', reason.title()))
+                        cfp.flush()
+                        results[tret] += 1
+                    continue
+                try:
+                    self._tfm.define_transient({
+                        'UTPATH': test,
+                        'UTDIR': normpath(dirname(test)),
+                        'UTFILE': basename(test),
+                    })
+                    self._log.info('[TEST %s] (%d/%d)', test_name, tpos, tcount)
+                    context = 'pre'
+                    exec_info = self._build_test_command(test)
+                    exec_info.test_name = test_name
+                    vcplogfile = self._log_vcp_streams(exec_info)
+                    exec_info.context.execute(context)
+                    context = 'with'
+                    tret, xtime, err = qot.run(exec_info)
+                    cret = exec_info.context.finalize()
+                    if exec_info.expect_result != 0:
+                        if tret == exec_info.expect_result:
+                            self._log.info('QEMU failed with expected error, '
+                                           'assume success')
+                            tret = 0
+                        elif tret == 0:
+                            self._log.warning('QEMU success while expected '
+                                              'error %d, assume error', tret)
+                            tret = 98
+                    if tret == 0 and cret != 0:
+                        tret = self.CONTEXT_ERROR
+                    if tret and not err:
+                        err = exec_info.context.first_error
+                    if not tret:
+                        context = 'post'
+                    exec_info.context.execute(context, tret)
+                # pylint: disable=broad-except
+                except Exception as exc:
+                    self._log.critical('%s', str(exc))
+                    if debug:
+                        print(format_exc(chain=False), file=sys.stderr)
+                    tret = self.CONTEXT_ERROR
+                    xtime = ExecTime(0.0)
+                    err = str(exc)
+                finally:
+                    self._discard_vcp_log(vcplogfile)
+                    self._tfm.cleanup_transient()
+                    if not self._tfm.keep_temporary:
+                        self._tfm.delete_default_dir(test_name)
+                    flush_memory_loggers(['pyot', 'pyot.vcp', 'pyot.ctx',
+                                          'pyot.file'], LOG_INFO)
+                results[tret] += 1
+                sret = self.RESULT_MAP.get(tret) or str(tret)
+                if tret == self.CONTEXT_ERROR:
+                    sret = f'{sret} ({context.upper()})'
+                try:
+                    targs = exec_info.args
+                    icount = self.get_namespace_arg(targs, 'icount')
+                except (AttributeError, KeyError, UnboundLocalError):
+                    icount = None
+                if csv:
+                    csv.writerow(TestResult(test_name, sret, xtime, icount,
+                                            err))
+                    # want to commit result as soon as possible if some client
+                    # is live-tracking progress on long test runs
+                    cfp.flush()
+                else:
+                    self._log.info('"%s" executed in %s (%s)',
+                                   test_name, xtime, sret)
+                self._cleanup_temp_files(temp_files)
+        finally:
+            if cfp:
+                cfp.close()
+        for kind in sorted(results):
+            self._log.info('%s count: %d',
+                           self.RESULT_MAP.get(kind, kind),
+                           results[kind])
+        # sort by the largest occurrence, discarding success
+        errors = sorted((x for x in results.items() if x[0] > 0),
+                        key=lambda x: -x[1])
+        # overall return code is the most common error, or success otherwise
+        ret = errors[0][0] if errors else 0
+        self._log.info('Total count: %d, overall result: %s',
+                       sum(results.values()),
+                       self.RESULT_MAP.get(ret, ret))
+        return ret
+
+    def get_test_radix(self, filename: str) -> str:
+        """Extract the radix name from a test pathname.
+
+           :param filename: the path to the test executable
+           :return: the test name
+        """
+        test_name = basename(filename).split('.')[0]
+        for suffix in self._suffixes:
+            if not test_name.endswith(suffix):
+                continue
+            return test_name[:-len(suffix)]
+        return test_name
+
+    @classmethod
+    def get_namespace_arg(cls, args: Namespace, name: str) -> Optional[str]:
+        """Extract a value from a namespace.
+
+           :param args: the namespace
+           :param name: the value's key
+           :return: the value if any
+        """
+        return args.__dict__.get(name)
+
+    @staticmethod
+    def abspath(path: str) -> str:
+        """Build absolute path"""
+        if isabs(path):
+            return normpath(path)
+        return normpath(joinpath(getcwd(), path))
+
+    def _cleanup_temp_files(self, storage: dict[str, set[str]]) -> None:
+        if self._tfm.keep_temporary:
+            return
+        for kind, files in storage.items():
+            delete_file = getattr(self._tfm, f'delete_{kind}_image')
+            for filename in files:
+                delete_file(filename)
+
+    def _build_command(self, args: Namespace,
+                       opts: Optional[list[str]] = None) -> EasyDict[str, Any]:
+        raise NotImplementedError('Abstract command')
+
+    def _build_test_command(self, filename: str) -> EasyDict[str, Any]:
+        test_name = self.get_test_radix(filename)
+        args, opts, timeout, texp = self._build_test_args(test_name)
+        setattr(args, 'exec', filename)
+        exec_info = self._build_command(args, opts)
+        exec_info.pop('connection', None)
+        exec_info.args = args
+        exec_info.context = self._build_test_context(test_name)
+        exec_info.timeout = timeout
+        exec_info.expect_result = texp
+        return exec_info
+
+    def _build_test_list(self) -> list[TestCandidate]:
+        pathnames = set()
+        testdir = normpath(self._tfm.interpolate(self._config.get('testdir',
+                                                                  curdir)))
+        self._tfm.define({'testdir': testdir})
+        cfilters = self._args.filter or []
+        pfilters = [f for f in cfilters if not f.startswith('!')]
+        if not pfilters:
+            cfilters = ['*'] + cfilters
+            tfilters = ['*'] + pfilters
+        else:
+            tfilters = list(pfilters)
+        virttests = self._config.get('virtual', {})
+        if not isinstance(virttests, dict):
+            raise ValueError('Invalid virtual tests definition')
+        vtests = {}
+        for vname, vpath in virttests.items():
+            if not isinstance(vname, str):
+                raise ValueError(f"Invalid virtual test definition '{vname}'")
+            if sep in vname:
+                raise ValueError(f"Virtual test name cannot contain directory "
+                                 f"specifier: '{vname}'")
+            rpath = normpath(self._tfm.interpolate(vpath))
+            if not isfile(rpath):
+                raise ValueError(f"Invalid virtual test '{vname}': "
+                                 f"missing file '{rpath}'")
+            vtests[vname] = rpath
+        self._virtual_tests.update(vtests)
+        inc_filters = self._build_config_list('include')
+        if inc_filters:
+            self._log.debug('Searching for tests from %s dir', testdir)
+            for candidate in inc_filters:
+                path_filter = candidate.name
+                if not path_filter:
+                    continue
+                if testdir:
+                    path_filter = joinpath(testdir, path_filter)
+                paths = set(glob(path_filter, recursive=True))
+                for path in paths:
+                    if isfile(path):
+                        for tfilter in tfilters:
+                            if fnmatchcase(self.get_test_radix(path), tfilter):
+                                pathnames.add(path)
+                                break
+                for vpath in vtests:
+                    for tfilter in tfilters:
+                        if fnmatchcase(self.get_test_radix(vpath), tfilter):
+                            pathnames.add(vpath)
+                            break
+        for testfile in self._enumerate_from('include_from'):
+            if not isfile(testfile):
+                raise ValueError(f'Unable to locate test file '
+                                 f'"{testfile}"')
+            for tfilter in tfilters:
+                if fnmatchcase(self.get_test_radix(testfile), tfilter):
+                    pathnames.add(testfile)
+        if not pathnames:
+            return []
+        roms = self._argdict.get('rom', [])
+        pathnames -= {normpath(rom) for rom in roms}
+
+        xtfilters = [TestCandidate(f[1:].strip(), 'CMDLINE')
+                     for f in cfilters if f.startswith('!')]
+        exc_filters = self._build_config_list('exclude')
+        xtfilters.extend(exc_filters)
+        discarded: set[TestCandidate] = set()
+        if xtfilters:
+            for candidate in xtfilters:
+                path_filter, reason = candidate.name, candidate.reason
+                if not path_filter:
+                    continue
+                if testdir:
+                    path_filter = joinpath(testdir, path_filter)
+                paths = set(glob(path_filter, recursive=True))
+                if reason:
+                    discarded.update(TestCandidate(t, reason)
+                                     for t in pathnames & paths)
+                pathnames -= paths
+                vdiscards: set[str] = set()
+                for vpath in vtests:
+                    if fnmatchcase(vpath, basename(path_filter)):
+                        vdiscards.add(vpath)
+                if reason:
+                    discarded.update(TestCandidate(t, reason)
+                                     for t in pathnames & vdiscards)
+                pathnames -= vdiscards
+        ftfilters = set(self._enumerate_from('exclude_from'))
+        pathnames -= ftfilters
+        candidates = set(TestCandidate(t) for t in pathnames)
+        candidates.update(discarded)
+        return sorted(candidates,
+                      key=lambda tc: alphanum_key(basename(tc.name)))
+
+    def _enumerate_from(self, config_entry: str) -> Iterator[str]:
+        incf_filters = self._build_config_list(config_entry)
+        if incf_filters:
+            for candidate in incf_filters:
+                incf = candidate.name
+                incf = normpath(self._tfm.interpolate(incf))
+                if not isfile(incf):
+                    raise ValueError(f'Invalid test file: "{incf}"')
+                self._log.debug('Loading test list from %s', incf)
+                incf_dir = dirname(incf)
+                with open(incf, 'rt', encoding='utf-8') as ifp:
+                    for testfile in ifp:
+                        testfile = re.sub('#.*$', '', testfile).strip()
+                        if not testfile:
+                            continue
+                        testfile = self._tfm.interpolate(testfile)
+                        if not testfile.startswith(sep):
+                            testfile = joinpath(incf_dir, testfile)
+                        yield normpath(testfile)
+
+    def _build_config_list(self, config_entry: str) -> list[TestCandidate]:
+        cfglist: list[str] = []
+        items = self._config.get(config_entry)
+        if not items:
+            return cfglist
+        if not isinstance(items, list):
+            raise ValueError(f'Invalid configuration file: '
+                             f'"{config_entry}" is not a list')
+        for item in items:
+            if isinstance(item, str):
+                cfglist.append(TestCandidate(item))
+                continue
+            if isinstance(item, dict):
+                for dname, dval in item.items():
+                    try:
+                        cond = bool(int(environ.get(dname, '0')))
+                    except (ValueError, TypeError):
+                        cond = False
+                    if not cond:
+                        continue
+                    if isinstance(dval, str):
+                        dval = [dval]
+                    if isinstance(dval, list):
+                        for sitem in dval:
+                            if isinstance(sitem, str):
+                                cfglist.append(TestCandidate(sitem, dname))
+        return cfglist
+
+    def _build_test_args(self, test_name: str) \
+            -> tuple[Namespace, list[str], int, int]:
+        tests_cfg = self._config.get('tests', {})
+        if not isinstance(tests_cfg, dict):
+            raise ValueError('Invalid tests sub-section')
+        kwargs = dict(self._args.__dict__)
+        test_cfg = tests_cfg.get(test_name, {})
+        if test_cfg is None:
+            # does not default to an empty dict to differentiate empty from
+            # inexistent test configuration
+            self._log.debug('No configuration for test %s', test_name)
+            opts = None
+        else:
+            # use same arg parser dash-underscore replacement for option name
+            test_cfg = {k.replace('-', '_'): v for k, v in test_cfg.items()
+                        if k not in ('pre', 'post', 'with')}
+            self._log.debug('Using custom test config for %s', test_name)
+            discards = {k for k, v in test_cfg.items() if v == ''}
+            if discards:
+                test_cfg = dict(test_cfg)
+                for discard in discards:
+                    del test_cfg[discard]
+                    if discard in kwargs:
+                        del kwargs[discard]
+            kwargs.update(test_cfg)
+            opts = kwargs.get('opts')
+            if opts and not isinstance(opts, list):
+                raise ValueError('fInvalid QEMU options for {test_name}')
+            opts = flatten([opt.split(' ') for opt in opts])
+            opts = [self._tfm.interpolate(opt) for opt in opts]
+            opts = flatten([opt.split(' ') for opt in opts])
+            opts = [self._tfm.interpolate_dirs(opt, test_name) for opt in opts]
+        timeout = float(kwargs.get('timeout', DEFAULT_TIMEOUT))
+        tmfactor = float(kwargs.get('timeout_factor', DEFAULT_TIMEOUT_FACTOR))
+        itimeout = int(timeout * tmfactor)
+        texpect = kwargs.get('expect', 0)
+        try:
+            texp = int(texpect)
+        except ValueError:
+            result_map = {v: k for k, v in self.RESULT_MAP.items()}
+            try:
+                texp = result_map[texpect.upper()]
+            except KeyError as exc:
+                raise ValueError(f'Unsupported expect: {texpect}') from exc
+        return Namespace(**kwargs), opts or [], itimeout, texp
+
+    def _build_test_context(self, test_name: str) -> ExecContext:
+        context = defaultdict(list)
+        tests_cfg = self._config.get('tests', {})
+        test_cfg = tests_cfg.get(test_name, {})
+        test_env = None
+        if test_cfg:
+            for ctx_name in ('pre', 'with', 'post'):
+                if ctx_name not in test_cfg:
+                    continue
+                ctx = test_cfg[ctx_name]
+                if not isinstance(ctx, list):
+                    raise ValueError(f'Invalid context "{ctx_name}" '
+                                     f'for test {test_name}')
+                for pos, cmd in enumerate(ctx, start=1):
+                    if not isinstance(cmd, str):
+                        raise ValueError(f'Invalid command #{pos} in '
+                                         f'"{ctx_name}" for test {test_name}')
+                    cmd = re.sub(r'[\n\r]', ' ', cmd.strip())
+                    cmd = re.sub(r'\s{2,}', ' ', cmd)
+                    cmd = self._tfm.interpolate(cmd)
+                    cmd = self._tfm.interpolate_dirs(cmd, test_name)
+                    context[ctx_name].append(cmd)
+            env = test_cfg.get('env')
+            if env:
+                if not isinstance(env, dict):
+                    raise ValueError('Invalid context environment')
+                test_env = {k: self._tfm.interpolate(v) for k, v in env.items()}
+        return ExecContext(test_name, self._qemu_cmd, dict(context), test_env)
+
+    def _log_vcp_streams(self, exec_info: EasyDict[str, Any]) -> str:
+        logfile = exec_info.get('logfile', None)
+        if not logfile:
+            return None
+        assert exec_info.test_name
+        logfile = self._tfm.interpolate_dirs(logfile, exec_info.test_name)
+        vcplog = getLogger('pyot.vcp')
+        logfh = FileHandler(logfile, 'w')
+        # log everything
+        logfh.setLevel(LOG_DEBUG)
+        # force the logger to emit all messages as well
+        # (side effect on all handlers)
+        vcplog.setLevel(LOG_DEBUG)
+        vcplog.handlers.append(logfh)
+        return logfile
+
+    def _discard_vcp_log(self, vcplogfile: Optional[str]) -> None:
+        if not vcplogfile:
+            return
+        vcplogfile = abspath(vcplogfile)
+        vcplog = getLogger('pyot.vcp')
+        for handler in vcplog.handlers:
+            if isinstance(handler, FileHandler):
+                if handler.baseFilename == vcplogfile:
+                    handler.close()
+                    vcplog.removeHandler(handler)
diff --git a/python/qemu/ot/pyot/filemgr.py b/python/qemu/ot/pyot/filemgr.py
new file mode 100644
index 0000000000000..bac1569bbbe88
--- /dev/null
+++ b/python/qemu/ot/pyot/filemgr.py
@@ -0,0 +1,334 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""File manager for OpenTitan unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from atexit import register
+from logging import getLogger
+from io import BytesIO
+from os import close, environ, sep, unlink
+from os.path import abspath, basename, exists, isdir, isfile, normpath, splitext
+from shutil import rmtree
+from tempfile import mkdtemp, mkstemp
+from typing import Any, Optional
+
+import re
+
+from ot.util.elf import ElfBlob
+from ot.util.file import guess_file_type
+
+
+class FileManager:
+    """Simple file manager to generate and track temporary files.
+
+       :param keep_temp: do not automatically discard generated files on exit
+    """
+
+    def __init__(self, keep_temp: bool = False):
+        self._log = getLogger('pyot.file')
+        self._keep_temp = keep_temp
+        self._in_fly: set[str] = set()
+        self._otp_files: dict[str, tuple[str, int]] = {}
+        self._env: dict[str, str] = {}
+        self._transient_vars: set[str] = set()
+        self._dirs: dict[str, str] = {}
+        register(self._cleanup)
+
+    @property
+    def keep_temporary(self) -> bool:
+        """Tell whether temporary files and directories should be preserved or
+           not.
+
+           :return: True if temporary items should not be suppressed
+        """
+        return self._keep_temp
+
+    def set_qemu_src_dir(self, path: str) -> None:
+        """set the QEMU "source" directory.
+
+           :param path: the path to the QEMU source directory
+        """
+        self._env['QEMU_SRC_DIR'] = abspath(path)
+
+    def set_qemu_bin_dir(self, path: str) -> None:
+        """set the QEMU executable directory.
+
+           :param path: the path to the QEMU binary directory
+        """
+        self._env['QEMU_BIN_DIR'] = abspath(path)
+
+    def set_config_dir(self, path: str) -> None:
+        """Assign the configuration directory.
+
+           :param path: the directory that contains the input configuration
+                        file
+        """
+        self._env['CONFIG'] = abspath(path)
+
+    def set_udp_log_port(self, port: int) -> None:
+        """Assign the UDP logger port.
+
+           :param port: the UDP logger port
+        """
+        self._env['UDPLOG'] = f'{port}'
+
+    def interpolate(self, value: Any) -> str:
+        """Interpolate a ${...} marker with shell substitutions or local
+           substitution.
+
+           :param value: input value
+           :return: interpolated value as a string
+        """
+        def replace(smo: re.Match) -> str:
+            name = smo.group(1)
+            val = self._env[name] if name in self._env \
+                else environ.get(name, '')
+            if not val:
+                getLogger('pyot.file').warning("Unknown placeholder '%s'",
+                                               name)
+            return val
+        svalue = str(value)
+        nvalue = re.sub(r'\$\{(\w+)\}', replace, svalue)
+        if nvalue != svalue:
+            self._log.debug('Interpolate %s with %s', value, nvalue)
+        return nvalue
+
+    def define(self, aliases: dict[str, Any]) -> None:
+        """Store interpolation variables into a local dictionary.
+
+            Variable values are interpolated before being stored.
+
+           :param aliases: an alias JSON (sub-)tree
+        """
+        def replace(smo: re.Match) -> str:
+            name = smo.group(1)
+            val = self._env[name] if name in self._env \
+                else environ.get(name, '')
+            return val
+        for name in aliases:
+            value = str(aliases[name])
+            value = re.sub(r'\$\{(\w+)\}', replace, value)
+            if exists(value):
+                value = normpath(value)
+            aliases[name] = value
+            self._env[name.upper()] = value
+            self._log.debug('Store %s as %s', name.upper(), value)
+
+    def define_transient(self, aliases: dict[str, Any]) -> None:
+        """Add short-lived aliases that are all discarded when cleanup_transient
+           is called.
+
+           :param aliases: a dict of aliases
+        """
+        for name in aliases:
+            name = name.upper()
+            # be sure not to make an existing non-transient variable transient
+            if name not in self._env:
+                self._transient_vars.add(name)
+        self.define(aliases)
+
+    def cleanup_transient(self) -> None:
+        """Remove all transient variables."""
+        for name in self._transient_vars:
+            if name in self._env:
+                del self._env[name]
+        self._transient_vars.clear()
+
+    def interpolate_dirs(self, value: str, default: str) -> str:
+        """Resolve temporary directories, creating ones whenever required.
+
+           :param value: the string with optional directory placeholders
+           :param default: the default name to use if the placeholder contains
+                           none
+           :return: the interpolated string
+        """
+        def replace(smo: re.Match) -> str:
+            name = smo.group(1)
+            if name == '':
+                name = default
+            if name not in self._dirs:
+                tmp_dir = mkdtemp(prefix='qemu_ot_dir_')
+                self._dirs[name] = tmp_dir
+            else:
+                tmp_dir = self._dirs[name]
+            if not tmp_dir.endswith(sep):
+                tmp_dir = f'{tmp_dir}{sep}'
+            return tmp_dir
+        nvalue = re.sub(r'\@\{(\w*)\}/', replace, value)
+        if nvalue != value:
+            self._log.debug('Interpolate %s with %s', value, nvalue)
+        return nvalue
+
+    def delete_default_dir(self, name: str) -> None:
+        """Delete a temporary directory, if has been referenced.
+
+           :param name: the name of the directory reference
+        """
+        if name not in self._dirs:
+            return
+        if not isdir(self._dirs[name]):
+            return
+        try:
+            self._log.debug('Removing tree %s for %s', self._dirs[name], name)
+            rmtree(self._dirs[name])
+            del self._dirs[name]
+        except OSError:
+            self._log.error('Cannot be removed dir %s for %s', self._dirs[name],
+                            name)
+
+    def create_eflash_image(self, app: Optional[str] = None,
+                            bootloader: Optional[str] = None,
+                            no_flash_header: bool = False) -> str:
+        """Generate a temporary flash image file.
+
+           :param app: optional path to the application or the rom extension
+           :param bootloader: optional path to a bootloader
+           :param no_flash_header: input binary file do not contain an OpenTitan
+                                   application header (i.e. regular files)
+           :return: the full path to the temporary flash file
+        """
+        # pylint: disable=import-outside-toplevel
+        from ot.eflash.gen import FlashGen
+        gen = FlashGen(FlashGen.CHIP_ROM_EXT_SIZE_MAX if bool(bootloader)
+                       else 0, True)
+        flash_fd, flash_file = mkstemp(suffix='.raw', prefix='qemu_ot_flash_')
+        self._in_fly.add(flash_file)
+        close(flash_fd)
+        self._log.debug('Create %s', basename(flash_file))
+        try:
+            gen.open(flash_file)
+            xfiles = ((app, 'rom_ext'), (bootloader, 'bootloader'))
+            for xpath, xhdlr in xfiles:
+                if not xpath:
+                    continue
+                xtype = guess_file_type(xpath)
+                xstore = getattr(gen, f'store_{xhdlr}')
+                xname = basename(xpath)
+                if xtype == 'elf':
+                    with open(xpath, 'rb') as efp:
+                        elf = ElfBlob()
+                        elf.load(efp)
+                        if elf.address_size != 32:
+                            raise RuntimeError(f'{xname}: not an ELF32 file')
+                        xfp = BytesIO(elf.blob)
+                        xfp.name = f'{splitext(xname)[0]}.bin'
+                        xstore(0, xfp, xpath, no_header=no_flash_header)
+                elif xtype == 'bin':
+                    with open(xpath, 'rb') as xfp:
+                        xstore(0, xfp, no_header=no_flash_header)
+                else:
+                    raise RuntimeError(f'{xname} format {xtype.upper()} is '
+                                       f'not supported')
+        finally:
+            gen.close()
+        return flash_file
+
+    def create_otp_image(self, vmem: str) -> str:
+        """Generate a temporary OTP image file.
+
+           If a temporary file has already been generated for the input VMEM
+           file, use it instead.
+
+           :param vmem: path to the VMEM source file
+           :return: the full path to the temporary OTP file
+        """
+        # pylint: disable=import-outside-toplevel
+        if vmem in self._otp_files:
+            otp_file, ref_count = self._otp_files[vmem]
+            self._log.debug('Use existing %s', basename(otp_file))
+            self._otp_files[vmem] = (otp_file, ref_count + 1)
+            return otp_file
+        from otptool import OtpImage
+        otp = OtpImage()
+        with open(vmem, 'rt', encoding='utf-8') as vfp:
+            otp.load_vmem(vfp, 'otp')
+        otp_fd, otp_file = mkstemp(suffix='.raw', prefix='qemu_ot_otp_')
+        self._log.debug('Create %s', basename(otp_file))
+        self._in_fly.add(otp_file)
+        close(otp_fd)
+        with open(otp_file, 'wb') as rfp:
+            otp.save_raw(rfp)
+        self._otp_files[vmem] = (otp_file, 1)
+        return otp_file
+
+    def delete_flash_image(self, filename: str) -> None:
+        """Delete a previously generated flash image file.
+
+           :param filename: full path to the file to delete
+        """
+        if not isfile(filename):
+            self._log.warning('No such flash image file %s', basename(filename))
+            return
+        self._log.debug('Delete flash image file %s', basename(filename))
+        unlink(filename)
+        self._in_fly.discard(filename)
+
+    def delete_otp_image(self, filename: str) -> None:
+        """Delete a previously generated OTP image file.
+
+           The file may be used by other tests, it is only deleted if it not
+           useful anymore.
+
+           :param filename: full path to the file to delete
+        """
+        if not isfile(filename):
+            self._log.warning('No such OTP image file %s', basename(filename))
+            return
+        for vmem, (raw, count) in self._otp_files.items():
+            if raw != filename:
+                continue
+            count -= 1
+            if not count:
+                self._log.debug('Delete OTP image file %s', basename(filename))
+                unlink(filename)
+                self._in_fly.discard(filename)
+                del self._otp_files[vmem]
+            else:
+                self._log.debug('Keep OTP image file %s', basename(filename))
+                self._otp_files[vmem] = (raw, count)
+            break
+
+    def _cleanup(self) -> None:
+        """Remove a generated, temporary flash image file.
+        """
+        removed: set[str] = set()
+        for tmpfile in self._in_fly:
+            if not isfile(tmpfile):
+                removed.add(tmpfile)
+                continue
+            if not self._keep_temp:
+                self._log.debug('Delete %s', basename(tmpfile))
+                try:
+                    unlink(tmpfile)
+                    removed.add(tmpfile)
+                except OSError:
+                    self._log.error('Cannot delete %s', basename(tmpfile))
+        self._in_fly -= removed
+        if self._in_fly:
+            if not self._keep_temp:
+                raise OSError(f'{len(self._in_fly)} temp. files cannot be '
+                              f'removed')
+            for tmpfile in self._in_fly:
+                self._log.warning('Temporary file %s not suppressed', tmpfile)
+        removed: set[str] = set()
+        if not self._keep_temp:
+            for tmpname, tmpdir in self._dirs.items():
+                if not isdir(tmpdir):
+                    removed.add(tmpname)
+                    continue
+                self._log.debug('Delete dir %s', tmpdir)
+                try:
+                    rmtree(tmpdir)
+                    removed.add(tmpname)
+                except OSError as exc:
+                    self._log.error('Cannot delete %s: %s', tmpdir, exc)
+            for tmpname in removed:
+                del self._dirs[tmpname]
+        if self._dirs:
+            if not self._keep_temp:
+                raise OSError(f'{len(self._dirs)} temp. dirs cannot be removed')
+            for tmpdir in self._dirs.values():
+                self._log.warning('Temporary dir %s not suppressed', tmpdir)
diff --git a/python/qemu/ot/pyot/qemu/__init__.py b/python/qemu/ot/pyot/qemu/__init__.py
new file mode 100644
index 0000000000000..a4d6004e65891
--- /dev/null
+++ b/python/qemu/ot/pyot/qemu/__init__.py
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU tools to execute OpenTitan tests.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
diff --git a/python/qemu/ot/pyot/qemu/executer.py b/python/qemu/ot/pyot/qemu/executer.py
new file mode 100644
index 0000000000000..94e329f6f9f2f
--- /dev/null
+++ b/python/qemu/ot/pyot/qemu/executer.py
@@ -0,0 +1,268 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU test executer for OpenTitan unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import Namespace
+from collections import defaultdict
+from os.path import isfile
+from typing import Any, Optional
+
+import re
+
+from ot.util.file import guess_file_type
+from ot.util.misc import EasyDict
+
+from ..executer import Executer
+from .wrapper import QEMUWrapper
+
+
+class QEMUExecuter(Executer):
+    """Test execution engine using a QEMU virtual machine
+    """
+
+    LOG_SHORTCUTS = {
+        'A': 'in_asm',
+        'E': 'exec',
+        'G': 'guest_errors',
+        'H': 'help',
+        'I': 'int',
+        'M': 'mmu',
+        'R': 'cpu_reset',
+        'U': 'unimp',
+    }
+    """Shortcut names for QEMU log sources."""
+
+    WRAPPER = QEMUWrapper
+    """QEMU wrapper."""
+
+    def _build_fw_args(self, args: Namespace) \
+            -> tuple[str, Optional[str], list[str], Optional[str]]:
+        rom_exec = bool(args.rom_exec)
+        roms = args.rom or []
+        # rom can be specified as a string or a list of strings
+        if isinstance(roms, str):
+            roms = [roms]
+        multi_rom = (len(roms) + int(rom_exec)) > 1
+        # generate pre-application ROM option
+        fw_args: list[str] = []
+        machine = args.machine
+        variant = args.variant
+        chiplet_count = 1
+        if variant:
+            machine = f'{machine},variant={variant}'
+            try:
+                chiplet_count = sum(int(x)
+                                    for x in re.split(r'[A-Za-z]', variant)
+                                    if x)
+            except ValueError:
+                self._log.warning('Unknown variant syntax %s', variant)
+        rom_counts: list[int] = [0]
+        for chip_id in range(chiplet_count):
+            rom_count = 0
+            for rom in roms:
+                if rom in ('-', '_'):
+                    # special marker to disable a specific ROM
+                    rom_count += 1
+                    continue
+                rom_path = self._tfm.interpolate(rom)
+                if not isfile(rom_path):
+                    raise ValueError(f'Unable to find ROM file {rom_path}')
+                rom_ids = []
+                if args.first_soc:
+                    if chiplet_count == 1:
+                        rom_ids.append(f'{args.first_soc}.')
+                    else:
+                        rom_ids.append(f'{args.first_soc}{chip_id}.')
+                rom_ids.append('rom')
+                if multi_rom:
+                    rom_ids.append(f'{rom_count}')
+                rom_id = ''.join(rom_ids)
+                rom_opt = f'ot-rom_img,id={rom_id},file={rom_path}'
+                fw_args.extend(('-object', rom_opt))
+                rom_count += 1
+            rom_counts.append(rom_count)
+        rom_count = max(rom_counts)
+        xtype = None
+        if args.exec:
+            exec_path = self._virtual_tests.get(args.exec)
+            if not exec_path:
+                exec_path = self.abspath(args.exec)
+            xtype = guess_file_type(exec_path)
+            if xtype == 'spiflash':
+                fw_args.extend(('-drive',
+                                f'if=mtd,id=spiflash,bus=0,format=raw,'
+                                f'file={exec_path}'))
+            elif xtype == 'bin':
+                if args.embedded_flash is None:
+                    raise ValueError(f'{xtype} test type not supported without '
+                                     f'embedded-flash option')
+            else:
+                if xtype != 'elf':
+                    raise ValueError(f'No support for test type: '
+                                     f'{xtype.upper()} for {exec_path}')
+                if rom_exec:
+                    # generate ROM option(s) for the application itself
+                    for chip in range(chiplet_count):
+                        rom_id_parts = []
+                        if args.first_soc:
+                            if chiplet_count == 1:
+                                rom_id_parts.append(f'{args.first_soc}.')
+                            else:
+                                rom_id_parts.append(f'{args.first_soc}{chip}.')
+                        rom_id_parts.append('rom')
+                        if multi_rom:
+                            rom_id_parts.append(f'{rom_count}')
+                        rom_id = ''.join(rom_id_parts)
+                        rom_opt = f'ot-rom_img,id={rom_id},file={exec_path}'
+                        fw_args.extend(('-object', rom_opt))
+                    rom_count += 1
+                else:
+                    if args.embedded_flash is None:
+                        if not roms:
+                            fw_args.extend(('-kernel', exec_path))
+                        else:
+                            fw_args.extend(('-device',
+                                            f'loader,file={exec_path}'))
+        else:
+            exec_path = None
+        return machine, xtype, fw_args, exec_path
+
+    def _build_log_sources(self, args: Namespace) -> list[str]:
+        if not args.log:
+            return []
+        log_args = []
+        for arg in args.log:
+            if arg.lower() == arg:
+                log_args.append(arg)
+                continue
+            for upch in arg:
+                try:
+                    logname = self.LOG_SHORTCUTS[upch]
+                except KeyError as exc:
+                    raise ValueError(f"Unknown log name '{upch}'") from exc
+                log_args.append(logname)
+        return ['-d', ','.join(log_args)]
+
+    def _build_vcp_args(self, args: Namespace) -> \
+            tuple[list[str], dict[str, tuple[str, int]]]:
+        device = args.device
+        devdesc = device.split(':')
+        host = devdesc[0]
+        try:
+            port = int(devdesc[1])
+            if not 0 < port < 65536:
+                raise ValueError(f'Invalid serial TCP port: {port}')
+        except IndexError as exc:
+            raise ValueError(f'TCP port not specified: {device}') from exc
+        except TypeError as exc:
+            raise ValueError(f'Invalid TCP serial device: {device}') from exc
+        mux = f'mux={"on" if args.muxserial else "off"}'
+        vcps = args.vcp or [self.DEFAULT_SERIAL_PORT]
+        vcp_args = ['-display', 'none']
+        vcp_map = {}
+        for vix, vcp in enumerate(vcps):
+            vcp_map[vcp] = (host, port+vix)
+            vcp_args.extend(('-chardev',
+                             f'socket,id={vcp},host={host},port={port+vix},'
+                             f'{mux},server=on,wait=on'))
+            if vcp == self.DEFAULT_SERIAL_PORT:
+                vcp_args.extend(('-serial', 'chardev:serial0'))
+        return vcp_args, vcp_map
+
+    def _build_command(self, args: Namespace,
+                       opts: Optional[list[str]] = None) -> EasyDict[str, Any]:
+        """Build QEMU command line from argparser values.
+
+           :param args: the parsed arguments
+           :param opts: any QEMU-specific additional options
+           :return: a dictionary defining how to execute the command
+        """
+        if args.qemu is None:
+            raise ValueError('QEMU path is not defined')
+        machine, xtype, fw_args, xexec = self._build_fw_args(args)
+        qemu_args = [args.qemu, '-M', machine]
+        for otcfg in args.otcfg or []:
+            qemu_args.extend(('-readconfig', self.abspath(otcfg)))
+        qemu_args.extend(fw_args)
+        temp_files = defaultdict(set)
+        if all((args.otp, args.otp_raw)):
+            raise ValueError('OTP VMEM and RAW options are mutually exclusive')
+        if args.otp:
+            if not isfile(args.otp):
+                raise ValueError(f'No such OTP file: {args.otp}')
+            otp_file = self._tfm.create_otp_image(args.otp)
+            temp_files['otp'].add(otp_file)
+            qemu_args.extend(('-drive',
+                              f'if=pflash,file={otp_file},format=raw'))
+        elif args.otp_raw:
+            otp_raw_path = self.abspath(args.otp_raw)
+            qemu_args.extend(('-drive',
+                              f'if=pflash,file={otp_raw_path},format=raw'))
+        if args.flash:
+            if xtype == 'spiflash':
+                raise ValueError('Cannot use a flash file with a flash test')
+            if not isfile(args.flash):
+                raise ValueError(f'No such flash file: {args.flash}')
+            if any((args.exec, args.boot)):
+                raise ValueError('Flash file argument is mutually exclusive '
+                                 'with bootloader or rom extension')
+            flash_path = self.abspath(args.flash)
+            if args.embedded_flash is None:
+                raise ValueError('Embedded flash bus not defined')
+            qemu_args.extend(('-drive', f'if=mtd,id=eflash,'
+                                        f'bus={args.embedded_flash},'
+                                        f'file={flash_path},format=raw'))
+        elif any((xexec, args.boot)):
+            if xexec and not isfile(xexec):
+                raise ValueError(f'No such exec file: {xexec}')
+            if args.boot and not isfile(args.boot):
+                raise ValueError(f'No such bootloader file: {args.boot}')
+            if args.embedded_flash is not None:
+                no_flash_header = args.no_flash_header
+                flash_file = self._tfm.create_eflash_image(xexec, args.boot,
+                                                           no_flash_header)
+                temp_files['flash'].add(flash_file)
+                qemu_args.extend(('-drive', f'if=mtd,id=eflash,'
+                                            f'bus={args.embedded_flash},'
+                                            f'file={flash_file},format=raw'))
+        if args.qemu_log:
+            qemu_args.extend(('-D', self.abspath(args.qemu_log)))
+        for trace in args.trace or []:
+            qemu_args.append('-trace')
+            if isfile(trace):
+                qemu_args.append(f'events={self.abspath(trace)}')
+            else:
+                qemu_args.append(trace)
+        qemu_args.extend(self._build_log_sources(args))
+        if args.singlestep:
+            qemu_args.extend(('-accel', 'tcg,one-insn-per-tb=on'))
+        if 'icount' in args:
+            if args.icount is not None:
+                qemu_args.extend(('-icount', f'shift={args.icount}'))
+        try:
+            start_delay = float(getattr(args, 'start_delay') or
+                                self.DEFAULT_START_DELAY)
+        except ValueError as exc:
+            raise ValueError(f'Invalid start up delay {args.start_delay}') \
+                from exc
+        start_delay *= args.timeout_factor
+        trigger = getattr(args, 'trigger', '')
+        validate = getattr(args, 'validate', '')
+        if trigger and validate:
+            raise ValueError(f"{getattr(args, 'exec', '?')}: 'trigger' and "
+                             f"'validate' are mutually exclusive")
+        asan = getattr(args, 'asan', False)
+        logfile = getattr(args, 'log_file', None)
+        vcp_args, vcp_map = self._build_vcp_args(args)
+        qemu_args.extend(vcp_args)
+        qemu_args.extend(args.global_opts or [])
+        if opts:
+            qemu_args.extend((str(o) for o in opts))
+        return EasyDict(command=qemu_args, vcp_map=vcp_map,
+                        tmpfiles=temp_files, start_delay=start_delay,
+                        trigger=trigger, validate=validate, asan=asan,
+                        logfile=logfile)
diff --git a/python/qemu/ot/pyot/qemu/wrapper.py b/python/qemu/ot/pyot/qemu/wrapper.py
new file mode 100644
index 0000000000000..e67cc0d754ad1
--- /dev/null
+++ b/python/qemu/ot/pyot/qemu/wrapper.py
@@ -0,0 +1,28 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU executer wrapper for OpentTitan unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+import re
+
+from ..wrapper import Wrapper
+
+
+class QEMUWrapper(Wrapper):
+    """Test execution wrapper using a QEMU virtual machine
+    """
+
+    NAME = 'QEMU'
+
+    USELESS_ERR_CRE = re.compile(r'^\*{1,4}$')
+    """Useless error stuff from QEMU."""
+
+    def _discard_log(self, err: bool, line: str):
+        return self.USELESS_ERR_CRE.match(line)
+
+    def _decrease_log(self, err: bool, line: str):
+        return line.find('QEMU waiting for connection') >= 0
diff --git a/python/qemu/ot/pyot/util.py b/python/qemu/ot/pyot/util.py
new file mode 100644
index 0000000000000..9ccb3b3cb5230
--- /dev/null
+++ b/python/qemu/ot/pyot/util.py
@@ -0,0 +1,146 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Utilities for OpenTitan unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from csv import reader as csv_reader
+from textwrap import shorten
+from typing import NamedTuple, Optional
+
+import logging
+import re
+
+
+class ExecTime(float):
+    """Float with hardcoded formatter.
+    """
+
+    def __repr__(self) -> str:
+        return f'{self*1000:.0f} ms'
+
+
+class TestCandidate(NamedTuple):
+    """Test candidate.
+    """
+    name: str
+    reason: Optional[str] = None
+
+
+class TestResult(NamedTuple):
+    """Test result.
+    """
+    name: str
+    result: str
+    time: ExecTime
+    icount: Optional[str]
+    error: str
+
+
+class ResultFormatter:
+    """Format a result CSV file as a simple result table."""
+
+    def __init__(self):
+        self._results = []
+
+    def load(self, csvpath: str) -> None:
+        """Load a CSV file (generated with an Executer) and parse it.
+
+           :param csvpath: the path to the CSV file.
+        """
+        with open(csvpath, 'rt', encoding='utf-8') as cfp:
+            csv = csv_reader(cfp)
+            for row in csv:
+                self._results.append(row)
+
+    def show(self, spacing: bool = False, result: Optional[str] = None) -> None:
+        """Print a simple formatted ASCII table with loaded CSV results.
+
+           :param spacing: add an empty line before and after the table
+           :param result: overall result, if any
+        """
+        results = [r[:-1] + [shorten(r[-1], width=100)] for r in self._results]
+        if not results:
+            return
+        if spacing:
+            print('')
+        # third row is time, always defined as ms, see ExecTime
+        exec_times = [r[2].strip().split(' ')[0] for r in self._results[1:]]
+        total_time = sum(float(t) for t in exec_times if t)
+        tt_str = f'{total_time / 1000:.1f} s'
+        last_row = ['TEST SESSION', result or '?', tt_str]
+        last_row.extend([''] * (len(self._results) - len(last_row)))
+        results.append(last_row)
+        widths = [max(len(x) for x in col) for col in zip(*results)]
+        self._show_line(widths, '-')
+        self._show_row(widths, results[0])
+        self._show_line(widths, '=')
+        last_rix = len(self._results) - 2
+        for rix, row in enumerate(results[1:]):
+            self._show_row(widths, row)
+            self._show_line(widths, '-' if rix != last_rix else '=')
+        if spacing:
+            print('')
+
+    def _show_line(self, widths: list[int], csep: str) -> None:
+        print(f'+{"+".join([csep * (w+2) for w in widths])}+')
+
+    def _show_row(self, widths: list[int], cols: list[str]) -> None:
+        line = '|'.join([f' {c:{">" if p else "<"}{w}s} '
+                         for p, (w, c) in enumerate(zip(widths, cols))])
+        print(f'|{line}|')
+
+
+class LogMessageClassifier:
+    """Log level classifier for log messages.
+
+       :param classifiers: a map of loglevel, list of RE-compatible strings
+                           to match messages
+       :param app_exec: the executable name, to filter out useless messages
+    """
+
+    def __init__(self, classifiers: Optional[dict[str, list[str]]] = None,
+                 app_exec: Optional[str] = None):
+        self._app_exec = app_exec
+        if classifiers is None:
+            classifiers = {}
+        self._regexes: dict[int, re.Pattern] = {}
+        for klv in 'error warning info debug'.split():
+            uklv = klv.upper()
+            cstrs = classifiers.get(klv, [])
+            if not isinstance(cstrs, list):
+                raise ValueError(f'Invalid log classifiers for {klv}')
+            regexes = [f'{klv}: ', f'^{uklv} ', f' {uklv} ']
+            for cstr in cstrs:
+                try:
+                    # only sanity-check pattern, do not use result
+                    re.compile(cstr)
+                except re.error as exc:
+                    raise ValueError(f"Invalid log classifier '{cstr}' for "
+                                     f"{klv}: {exc}") from exc
+                regexes.append(cstr)
+            if regexes:
+                lvl = getattr(logging, uklv)
+                self._regexes[lvl] = re.compile(f"({'|'.join(regexes)})")
+            else:
+                lvl = getattr(logging, 'NOTSET')
+                # never match RE
+                self._regexes[lvl] = re.compile(r'\A(?!x)x')
+
+    def classify(self, line: str, default: int = logging.ERROR) -> int:
+        """Classify log level of a line depending on its content.
+
+           :param line: line to classify
+           :param default: defaut log level in no classification is found
+           :return: the logger log level to use
+        """
+        if self._app_exec and line.startswith(self._app_exec):
+            # discard QEMU internal messages that cannot be disable from the VM
+            if line.find("QEMU waiting") > 0:
+                return logging.NOTSET
+        for lvl, pattern in self._regexes.items():
+            if pattern.search(line):
+                return lvl
+        return default
diff --git a/python/qemu/ot/pyot/worker.py b/python/qemu/ot/pyot/worker.py
new file mode 100644
index 0000000000000..15bdbefb5558c
--- /dev/null
+++ b/python/qemu/ot/pyot/worker.py
@@ -0,0 +1,140 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Test executer for OpenTitan unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+
+from collections import deque
+from logging import getLogger
+from os.path import basename, normpath
+from subprocess import Popen, PIPE, TimeoutExpired
+from threading import Event, Thread
+from typing import Optional
+
+from .util import LogMessageClassifier
+
+
+class ContextWorker:
+
+    """Background task for test executer context.
+    """
+
+    def __init__(self, cmd: str, env: dict[str, str],
+                 sync: Optional[Event] = None):
+        self._log = getLogger('pyot.cmd')
+        self._cmd = cmd
+        self._env = env
+        self._sync = sync
+        self._log_q = deque()
+        self._resume = False
+        self._thread: Optional[Thread] = None
+        self._ret = None
+        self._first_error = ''
+
+    def run(self):
+        """Start the worker.
+        """
+        self._thread = Thread(target=self._run, daemon=True)
+        self._thread.start()
+
+    def stop(self) -> int:
+        """Stop the worker.
+        """
+        if self._thread is None:
+            raise ValueError('Cannot stop idle worker')
+        self._resume = False
+        self._thread.join()
+        return self._ret
+
+    def exit_code(self) -> Optional[int]:
+        """Return the exit code of the worker.
+
+           :return: the exit code or None if the worked has not yet completed.
+        """
+        return self._ret
+
+    @property
+    def command(self) -> str:
+        """Return the executed command name.
+        """
+        return normpath(self._cmd.split(' ', 1)[0])
+
+    @property
+    def first_error(self) -> str:
+        """Return the message of the first error, if any."""
+        return self._first_error
+
+    def _run(self) -> None:
+        self._resume = True
+        if self._sync and not self._sync.is_set():
+            self._log.info('Waiting for sync')
+            while self._resume:
+                if self._sync.wait(0.1):
+                    self._log.debug('Synchronized')
+                    break
+            self._sync.clear()
+        # pylint: disable=consider-using-with
+        proc = Popen(self._cmd,  bufsize=1, stdout=PIPE, stderr=PIPE,
+                     shell=True, env=self._env, encoding='utf-8',
+                     errors='ignore', text=True)
+        Thread(target=self._logger, args=(proc, True), daemon=True).start()
+        Thread(target=self._logger, args=(proc, False), daemon=True).start()
+        host_app_exec = f'{basename(self._cmd[0])}: '
+        classifier = LogMessageClassifier(app_exec=host_app_exec)
+        while self._resume:
+            while self._log_q:
+                err, qline = self._log_q.popleft()
+                if err:
+                    if not self._first_error:
+                        self._first_error = qline
+                    loglevel = classifier.classify(qline)
+                    self._log.log(loglevel, qline)
+                else:
+                    self._log.debug(qline)
+            if proc.poll() is not None:
+                # worker has exited on its own
+                self._resume = False
+                break
+        try:
+            # give some time for the process to complete on its own
+            proc.wait(0.2)
+            self._ret = proc.returncode
+            self._log.debug("'%s' completed with '%d'", self.command, self._ret)
+        except TimeoutExpired:
+            # still executing
+            proc.terminate()
+            try:
+                # leave 1 second for QEMU to cleanly complete...
+                proc.wait(1.0)
+                self._ret = 0
+            except TimeoutExpired:
+                # otherwise kill it
+                self._log.error("Force-killing command '%s'", self.command)
+                proc.kill()
+                self._ret = proc.returncode
+        # retrieve the remaining log messages
+        stdlog = self._log.info if self._ret else self._log.debug
+        try:
+            outs, errs = proc.communicate(timeout=0.1)
+            if not self._first_error:
+                self._first_error = errs.split('\n', 1)[0]
+            for sfp, logger in zip((outs, errs), (stdlog, self._log.error)):
+                for line in sfp.split('\n'):
+                    line = line.strip()
+                    if line:
+                        logger(line)
+        except TimeoutExpired:
+            proc.kill()
+            if self._ret is None:
+                self._ret = proc.returncode
+
+    def _logger(self, proc: Popen, err: bool):
+        # worker thread, blocking on VM stdout/stderr
+        stream = proc.stderr if err else proc.stdout
+        while proc.poll() is None:
+            line = stream.readline().strip()
+            if line:
+                self._log_q.append((err, line))
diff --git a/python/qemu/ot/pyot/wrapper.py b/python/qemu/ot/pyot/wrapper.py
new file mode 100644
index 0000000000000..88e88f4bffb60
--- /dev/null
+++ b/python/qemu/ot/pyot/wrapper.py
@@ -0,0 +1,493 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Host executer wrapper for OpentTitan unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from collections import deque
+from os import environ, unlink
+from os.path import basename, dirname, isfile, join as joinpath
+from select import POLLIN, POLLERR, POLLHUP, poll as spoll
+from socket import socket, timeout as LegacyTimeoutError
+from subprocess import Popen, PIPE, TimeoutExpired
+from threading import Event, Thread
+from time import time as now
+from traceback import format_exc
+from typing import Any, Optional
+
+import logging
+import re
+import sys
+
+from ot.util.log import ColorLogFormatter
+from ot.util.misc import EasyDict, split_map_join
+
+from .util import ExecTime, LogMessageClassifier
+
+
+class Wrapper:
+    """A small engine to run OpenTitan tests.
+
+       :param log_classifiers: a map of loglevel, list of RE-compatible strings
+                               to match messages
+       :param debug: whether running in debug mode
+    """
+    # pylint: disable=too-few-public-methods
+
+    EXIT_ON = rb'(PASS|FAIL)!\r'
+    """Matching strings to search for in guest output.
+
+       The return code of the script is the position plus the GUEST_ERROR_OFFSET
+       in the above RE group when matched, except first item which is always 0.
+       This offset is used to differentiate from host app own return codes.
+       Host app may return negative values, which are the negative value of
+       POSIX signals, such as SIGABRT.
+    """
+
+    ANSI_CRE = re.compile(rb'(\x9B|\x1B\[)[0-?]*[ -\/]*[@-~]')
+    """ANSI escape sequences."""
+
+    GUEST_ERROR_OFFSET = 40
+    """Offset for guest errors. Should be larger than the host max signal value.
+    """
+
+    NO_MATCH_RETURN_CODE = 100
+    """Return code when no matching string is found in guest output."""
+
+    ASAN_LOGFILE_PREFIX = 'asan.log'
+    """Address sanitizer log prefix."""
+
+    NAME = 'generic'
+    """Wrapper name."""
+
+    def __init__(self, log_classifiers: dict[str, list[str]], debug: bool):
+        self._log_classifiers = log_classifiers
+        self._debug = debug
+        self._log = logging.getLogger('pyot')
+        self._wlog = logging.getLogger(f'pyot.{self.NAME.lower()}')
+
+    def run(self, tdef: EasyDict[str, Any]) -> tuple[int, ExecTime, str]:
+        """Execute the specified host app command, aborting execution if the
+           host app does not exit after the specified timeout.
+
+           :param tdef: test definition and parameters
+                - command, a list of strings defining the host app command to
+                           execute with all its options
+                - vcp_map: how to connect to host app virtual communication
+                           ports
+                - timeout, the allowed time for the command to execute,
+                           specified as a real number
+                - expect_result, the expected outcome of the host app, i.e. its
+                           exit code. Some tests may expect that host app
+                           terminates with a non-zero exit code
+                - context, an option ContextWorker instance, to execute
+                           concurrently with the host app process. Many tests
+                           expect to communicate with the host app process.
+                - trigger, a string to match on the host app virtual comm port
+                           output to trigger the context execution. It may be
+                           defined as a regular expression.
+                - validate, a string to match on the host app virtual comm port
+                           output to early exit. It may be defined as a regular
+                           expression.
+                - start_delay, the delay to wait before starting the execution
+                           of the context once the host app command has been
+                           started.
+                - asan, whether to redirect and post-process AddressSanitizer
+                           output log
+           :return: a 3-uple of exit code, execution time, and last guest error
+        """
+        # stdout and stderr belongs to host app
+        # OT's UART0 is redirected to a TCP stream that can be accessed through
+        # self._device. The VM pauses till the TCP socket is connected
+        xre = re.compile(self.EXIT_ON)
+        sync_event = None
+        if tdef.trigger:
+            sync_event = Event()
+        match_pattern = tdef.trigger or tdef.validate
+        if match_pattern:
+            if match_pattern.startswith("r'") and match_pattern.endswith("'"):
+                try:
+                    tmo = re.compile(match_pattern[2:-1].encode())
+                except re.error as exc:
+                    raise ValueError('Invalid regex: {exc}') from exc
+
+                def trig_match(bline):
+                    return tmo.match(bline)
+            else:
+                btrigger = match_pattern.encode()
+
+                def trig_match(bline):
+                    return bline.find(btrigger) >= 0
+        else:
+            trig_match = None
+        ret = None
+        proc = None
+        xstart = None
+        xend = None
+        log = self._log
+        last_error = ''
+        vcp_map = tdef.vcp_map
+        vcp_ctxs: dict[int, list[str, socket, bytearray, logging.Logger]] = {}
+        asan_file = None
+        log_q = deque()
+        host_app_exec = f'{basename(tdef.command[0])}: '
+        classifier = LogMessageClassifier(classifiers=self._log_classifiers,
+                                          app_exec=host_app_exec)
+        try:
+            workdir = dirname(tdef.command[0])
+            tdef_cli = self._simplify_cli(tdef.command)
+            log.debug('Executing %s as %s', self.NAME, tdef_cli)
+            env = dict(environ)
+            if tdef.asan:
+                # note cannot use a FileManager temp file here, as the full
+                # pathname is built by the ASAN tool once host app has started.
+                # store this temporary file in the FileManager-managed
+                # work directory
+                asan_prefix = joinpath(workdir, self.ASAN_LOGFILE_PREFIX)
+                env['ASAN_OPTIONS'] = f'log_path={asan_prefix}'
+            else:
+                asan_prefix = None
+            # pylint: disable=consider-using-with
+            proc = Popen(tdef.command, bufsize=1, cwd=workdir, stdout=PIPE,
+                         stderr=PIPE, encoding='utf-8', errors='ignore',
+                         text=True, env=env)
+            try:
+                proc.wait(0.1)
+            except TimeoutExpired:
+                pass
+            else:
+                ret = proc.returncode
+                log.fatal('%s bailed out: %d for "%s"',
+                          self.NAME, ret, tdef.test_name)
+                raise OSError()
+            log.debug('Execute %s for %.0f secs', self.NAME, tdef.timeout)
+            if asan_prefix:
+                asan_file = f'{asan_prefix}.{proc.pid}'
+            # unfortunately, subprocess's stdout calls are blocking, so the
+            # only way to get near real-time output from the host app is to use
+            # a dedicated thread that may block whenever no output is available
+            # from the VM. This thread reads and pushes back lines to a local
+            # queue, which is popped and logged to the local logger on each
+            # loop. Note that Popen's communicate() also relies on threads to
+            # perform stdout/stderr read out.
+            logname = self.NAME.lower()
+            Thread(target=self._log_worker, name=f'{logname}_out_logger',
+                   args=(proc, log_q, True), daemon=True).start()
+            Thread(target=self._log_worker, name=f'{logname}_err_logger',
+                   args=(proc, log_q, False), daemon=True).start()
+            poller = spoll()
+            connect_map = vcp_map.copy()
+            timeout = now() + tdef.start_delay
+            # ensure that host app starts and give some time for it to set up
+            # when multiple VCPs are set to 'wait', one VCP can be connected at
+            # a time, i.e. host app does not open all connections at once.
+            vcp_lognames = []
+            vcplogname = 'pyot.vcp'
+            while connect_map:
+                if now() > timeout:
+                    minfo = ', '.join(f'{d} @ {r[0]}:{r[1]}'
+                                      for d, r in connect_map.items())
+                    if proc.poll():
+                        raise OSError(proc.returncode)
+                    raise TimeoutError(f'Cannot connect to {self.NAME} '
+                                       f'VCPs: {minfo}')
+                connected = []
+                for vcpid, (host, port) in connect_map.items():
+                    try:
+                        # timeout for connecting to VCP
+                        sock = socket()
+                        sock.settimeout(1)
+                        sock.connect((host, port))
+                        connected.append(vcpid)
+                        vcp_name = re.sub(r'^.*[-\.+]', '', vcpid)
+                        vcp_lognames.append(vcp_name)
+                        vcp_log = logging.getLogger(f'{vcplogname}.{vcp_name}')
+                        vcp_ctxs[sock.fileno()] = [vcpid, sock, bytearray(),
+                                                   vcp_log]
+                        # remove timeout for VCP comm, as poll is used
+                        sock.settimeout(None)
+                        poller.register(sock, POLLIN | POLLERR | POLLHUP)
+                    except ConnectionRefusedError:
+                        continue
+                    except OSError as exc:
+                        log.error('Cannot setup {%s} VCP connection %s: %s',
+                                  self.NAME, vcpid, exc)
+                        print(format_exc(chain=False), file=sys.stderr)
+                        raise
+                # removal from dictionary cannot be done while iterating it
+                for vcpid in connected:
+                    del connect_map[vcpid]
+            self._colorize_vcp_log(vcplogname, vcp_lognames)
+            xstart = now()
+            if tdef.context:
+                try:
+                    tdef.context.execute('with', sync=sync_event)
+                except OSError as exc:
+                    ret = exc.errno
+                    last_error = exc.strerror
+                    raise
+                # pylint: disable=broad-except
+                except Exception as exc:
+                    ret = 126
+                    last_error = str(exc)
+                    raise
+            abstimeout = float(tdef.timeout) + now()
+            vcp_default_log = logging.DEBUG
+            while now() < abstimeout:
+                log_err = self._process_log_queue(log_q, classifier)
+                if not last_error and log_err:
+                    last_error = log_err
+                if tdef.context:
+                    wret = tdef.context.check_error()
+                    if wret:
+                        ret = wret
+                        last_error = tdef.context.first_error or \
+                            'Fail to execute worker'
+                        raise OSError(wret, last_error)
+                xret = proc.poll()
+                if xret is not None:
+                    if xend is None:
+                        xend = now()
+                    ret = xret
+                    if ret != 0:
+                        if ret != tdef.expect_result:
+                            logfn = getattr(log, 'critical')
+                        else:
+                            logfn = getattr(log, 'warning')
+                        logfn('Abnormal %s termination: %d for "%s"',
+                              self.NAME, ret, tdef.test_name)
+                    break
+                for vfd, event in poller.poll(0.01):
+                    if event in (POLLERR, POLLHUP):
+                        poller.modify(vfd, 0)
+                        continue
+                    vcpid, vcp, vcp_buf, vcp_log = vcp_ctxs[vfd]
+                    try:
+                        data = vcp.recv(4096)
+                    except (TimeoutError, LegacyTimeoutError):
+                        log.error('Unexpected timeout w/ poll on %s', vcp)
+                        continue
+                    vcp_buf += data
+                    if not vcp_buf:
+                        continue
+                    lines = vcp_buf.split(b'\n')
+                    vcp_buf[:] = bytearray(lines[-1])
+                    for line in lines[:-1]:
+                        line = self.ANSI_CRE.sub(b'', line)
+                        if trig_match and trig_match(line):
+                            # reset timeout from this event
+                            abstimeout = float(tdef.timeout) + now()
+                            trig_match = None
+                            if sync_event:
+                                log.info('Trigger pattern detected, resuming '
+                                         'for %.0f secs', tdef.timeout)
+                                sync_event.set()
+                            else:
+                                log.info('Validation pattern detected, exiting')
+                                ret = 0
+                                break
+                        xmo = xre.search(line)
+                        if xmo:
+                            xend = now()
+                            exit_word = xmo.group(1).decode('utf-8',
+                                                            errors='ignore')
+                            ret = self._get_exit_code(xmo)
+                            log.info("Exit sequence detected: '%s' -> %d",
+                                     exit_word, ret)
+                            if ret == 0:
+                                last_error = ''
+                            break
+                        sline = line.decode('utf-8', errors='ignore').rstrip()
+                        level = classifier.classify(sline, vcp_default_log)
+                        if level == logging.ERROR:
+                            err = re.sub(r'^.*:\d+]', '', sline).lstrip()
+                            # be sure not to preserve comma as this char is
+                            # used as a CSV separator.
+                            last_error = err.strip('"').replace(',', ';')
+                        vcp_log.log(level, sline)
+                    else:
+                        # no match for exit sequence on current VCP
+                        continue
+                    if ret is not None:
+                        # match for exit sequence on current VCP
+                        break
+                if ret is not None:
+                    # match for exit sequence on last VCP
+                    break
+            if ret is None:
+                log.warning('Execution timed out for "%s"', tdef.test_name)
+                ret = 124  # timeout
+        except (OSError, ValueError) as exc:
+            if ret is None:
+                ret = proc.returncode if proc.poll() is not None else 125
+                log.fatal('Unable to execute %s: %s', self.NAME, exc)
+        finally:
+            if xend is None:
+                xend = now()
+            for _, sock, _, _ in vcp_ctxs.values():
+                sock.close()
+            vcp_ctxs.clear()
+            log_err = self._process_log_queue(log_q, classifier)
+            if not last_error and log_err:
+                last_error = log_err
+            if proc:
+                if xend is None:
+                    xend = now()
+                proc.terminate()
+                try:
+                    # leave 1 second for host app to cleanly complete...
+                    proc.wait(1.0)
+                except TimeoutExpired:
+                    # otherwise kill it
+                    log.error('Force-killing %s', self.NAME)
+                    proc.kill()
+                if ret is None:
+                    ret = proc.returncode
+                # retrieve the remaining log messages
+                stdlog = self._wlog.info if ret else self._wlog.debug
+                for msg, logger in zip(proc.communicate(timeout=1.1),
+                                       (stdlog, self._wlog.error)):
+                    for line in msg.split('\n'):
+                        line = line.strip()
+                        if line:
+                            logger(line)
+            if asan_file:
+                self._post_process_asan(asan_file)
+        xtime = ExecTime(xend-xstart) if xstart and xend else 0.0
+        app_cmd_lead = f'{basename(tdef.command[0])}: '
+        return abs(ret) or 0, xtime, last_error.removeprefix(app_cmd_lead)
+
+    @classmethod
+    def classify_log(cls, line: str, default: int = logging.ERROR,
+                     app_exec: Optional[str] = None) -> int:
+        """Classify log level of a line depending on its content.
+
+           :param line: line to classify
+           :param default: defaut log level in no classification is found
+           :param app_exec: host application basename
+           :return: the logger log level to use
+        """
+        if app_exec and line.startswith(app_exec):
+            # discard host app internal messages that cannot be disabled from
+            # the VM
+            return logging.NOTSET
+        if (line.find('info: ') >= 0 or
+            line.startswith('INFO ') or
+            line.find(' INFO ') >= 0):  # noqa
+            return logging.INFO
+        if (line.find('warning: ') >= 0 or
+            line.startswith('WARNING ') or
+            line.find(' WARNING ') >= 0):  # noqa
+            return logging.WARNING
+        if (line.find('debug: ') >= 0 or
+            line.startswith('DEBUG ') or
+            line.find(' DEBUG ') >= 0):  # noqa
+            return logging.DEBUG
+        return default
+
+    def _simplify_cli(self, args: list[str]) -> str:
+        """Shorten the test execution command line."""
+        if self._debug:
+            # do not simplify the argument line if debug mode is enabled
+            return ' '.join(args)
+        return ' '.join(split_map_join(',', arg,
+                                       lambda part: split_map_join('=', part,
+                                                                   basename))
+                        for arg in args)
+
+    def _colorize_vcp_log(self, vcplogname: str, lognames: list[str]) -> None:
+        vlog = logging.getLogger(vcplogname)
+        clr_fmt = None
+        while vlog:
+            for hdlr in vlog.handlers:
+                if isinstance(hdlr.formatter, ColorLogFormatter):
+                    clr_fmt = hdlr.formatter
+                    break
+            vlog = vlog.parent
+        if not clr_fmt:
+            return
+        for color, logname in enumerate(sorted(lognames)):
+            clr_fmt.add_logger_colors(f'{vcplogname}.{logname}', color)
+
+    def _discard_log(self, err: bool, line: str):
+        # pylint: disable=unused-argument
+        return False
+
+    def _decrease_log(self, err: bool, line: str):
+        # pylint: disable=unused-argument
+        return False
+
+    def _process_log_queue(self, log_q, classifier) -> Optional[str]:
+        first_err = None
+        while log_q:
+            err, qline = log_q.popleft()
+            if err:
+                if self._discard_log(err, qline):
+                    continue
+                level = classifier.classify(qline, logging.ERROR)
+                if level == logging.INFO and self._decrease_log(err, qline):
+                    level = logging.DEBUG
+                if level >= logging.ERROR and not first_err:
+                    first_err = qline
+            else:
+                level = logging.INFO
+            self._wlog.log(level, qline)
+        return first_err
+
+    def _log_worker(self, proc: Popen, queue: deque, err: bool):
+        # worker thread, blocking on VM stdout/stderr
+        stream = proc.stderr if err else proc.stdout
+        while proc.poll() is None:
+            line = stream.readline().strip()
+            if line:
+                queue.append((err, line))
+
+    def _get_exit_code(self, xmo: re.Match) -> int:
+        groups = xmo.groups()
+        if not groups:
+            self._log.debug('No matching group, using defaut code')
+            return self.NO_MATCH_RETURN_CODE
+        match = groups[0]
+        try:
+            # try to match an integer value
+            return int(match)
+        except ValueError:
+            pass
+        # try to find in the regular expression whether the match is one of
+        # the alternative in the first group
+        alts = re.sub(rb'^.*\((.*?)\).*$', rb'\1', xmo.re.pattern).split(b'|')
+        try:
+            pos = alts.index(match)
+            if pos:
+                pos += self.GUEST_ERROR_OFFSET
+            return pos
+        except ValueError as exc:
+            self._log.error('Invalid match: %s with %s', exc, alts)
+            return len(alts)
+        # any other case
+        self._log.debug('No match, using defaut code')
+        return self.NO_MATCH_RETURN_CODE
+
+    def _post_process_asan(self, asan_file: str):
+        alog = logging.getLogger('pyot.asan')
+        try:
+            if not isfile(asan_file):
+                raise ValueError('ASAN output lost')
+            with open(asan_file, 'rt') as afp:
+                asan = afp.read()
+            # 3 following messages are useless, discard them
+            for aline in asan.split('\n'):
+                if aline.find('ASan is ignoring requested') >= 0:
+                    continue
+                if aline.find('False positive error reports may follow') >= 0:
+                    continue
+                if aline.find('https://github.com') >= 0:
+                    continue
+                if not aline:
+                    continue
+                alog.error(aline.rstrip())
+            unlink(asan_file)
+        except (OSError, ValueError) as exc:
+            self._wlog.error('Cannot process ASAN file: %s', exc)
diff --git a/python/qemu/ot/rom/image.py b/python/qemu/ot/rom/image.py
new file mode 100644
index 0000000000000..ade0faf8b25bc
--- /dev/null
+++ b/python/qemu/ot/rom/image.py
@@ -0,0 +1,675 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""OpenTitan ROM image support.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import hexlify, unhexlify
+from configparser import RawConfigParser
+from io import BytesIO
+from logging import getLogger
+from functools import lru_cache
+from os.path import basename
+from typing import BinaryIO, Optional, TextIO, Union
+
+try:
+    from itertools import batched
+except ImportError:
+    # workaround for old Python versions (<3.12)
+    def batched(seq, n_count):
+        for pos in range(0, len(seq), n_count):
+            yield seq[pos:pos+n_count]
+import re
+
+from ot.util.elf import ElfBlob
+from ot.util.file import guess_file_type
+from ot.util.misc import classproperty
+from ot.util.prince import PrinceCipher
+
+# ruff: noqa: E402
+_CRYPTO_EXC: Optional[Exception] = None
+try:
+    from Crypto.Hash import cSHAKE256
+except ModuleNotFoundError:
+    try:
+        # see pip3 install -r requirements.txt
+        from Cryptodome.Hash import cSHAKE256
+    except ModuleNotFoundError as exc:
+        _CRYPTO_EXC = exc
+
+
+class ROMImage:
+    """ROM controller image helper to manipulate ROM images
+
+       Support scrambling, descrambling, file format conversions.
+
+       :param name: an optional name for logging purposes
+       :param snp: use legacy substitute and permute stages
+    """
+
+    ADDR_SUBST_PERM_ROUNDS = 2
+    DATA_SUBST_PERM_ROUNDS = 2
+    PRINCE_HALF_ROUNDS_SNP = 2  # legacy mode
+    PRINCE_HALF_ROUNDS = 3  # new mode w/o S&P
+    DATA_BITS = 4 * 8
+    ECC_BITS = 7
+    WORD_BITS = DATA_BITS + ECC_BITS
+    WORD_BYTES = (WORD_BITS + 7) // 8
+    DIGEST_BYTES = 32
+    DIGEST_WORDS = DIGEST_BYTES // 4
+
+    SBOX4 = [12, 5, 6, 11, 9, 0, 10, 13, 3, 14, 15, 8, 4, 7, 1, 2]
+    """PRESENT S-box permutation."""
+    SBOX4_INV = [5, 14, 15, 8, 12, 1, 2, 13, 11, 4, 6, 3, 0, 7, 9, 10]
+    """PRESENT S-box inverted permutation."""
+
+    ECC_39_32 = [0x2606bd25, 0xdeba8050, 0x413d89aa, 0x31234ed1,
+                 0xc2c1323b, 0x2dcc624c, 0x98505586]
+    """HSIAO constants for "inverted" 32-bit data with 7-bit SEC-DED."""
+
+    VMEM_LINE_WIDTH = 80
+    """Number of max char per line on generated VMEM files."""
+
+    def __init__(self, name: Union[str, int, None] = None, snp: bool = False):
+        logname = 'romimg'
+        if isinstance(name, (int, str)):
+            logname = f'{logname}.{name}'
+        self._log = getLogger(logname)
+        self._snp = snp
+        self._prince_half_rounds = (self.PRINCE_HALF_ROUNDS if not snp else
+                                    self.PRINCE_HALF_ROUNDS_SNP)
+        self._name = name
+        self._clear_data = bytearray()
+        self._scrambled_words: list[int] = []  # in logical address order
+        self._key: Optional[int] = None
+        self._nonce: Optional[int] = None
+        self._addr_nonce = 0
+        self._data_nonce = 0
+        self._addr_width = 0
+        self._khi = 0
+        self._klo = 0
+        self._digest: Optional[bytes] = None
+
+    def load(self, rfp: BinaryIO, size: Optional[int] = None):
+        """Load a ROM file. Can either be:
+
+           - a so called 'HEX' file, which is assumed to be scrambled
+           - a pure raw binary file
+           - a RISC-V RV32 ELF file
+
+           :param rfp: input binary stream
+           :param size: optional size, required for binary and ELF file format
+        """
+        ftype = guess_file_type(rfp)
+        loader = getattr(self, f'_load_{ftype}', None)
+        if not loader:
+            raise ValueError(f'Unsupported ROM file type: {ftype}')
+        filename = basename(rfp.name) if rfp.name else '?'
+        self._log.info('loading ROM image %s as %s file',
+                       filename, ftype.upper())
+        loader(rfp, size)
+
+    def save(self, rfp: BinaryIO, ftype: str) -> None:
+        """Save a ROM file.
+
+           :param rfp: output binary stream
+           :param ftype: the output file format. Either 'hex', 'vmem' or 'svem'
+        """
+        saver = getattr(self, f'_save_{ftype.lower()}', None)
+        if not saver:
+            raise ValueError(f'Unsupported ROM file type: {ftype}')
+        filename = basename(rfp.name) if isinstance(rfp.name, str) else '?'
+        self._log.info('storing ROM image %s as %s file', filename, ftype)
+        saver(rfp)
+
+    @classproperty
+    def save_formats(self) -> set[str]:
+        """Supported output formats."""
+        formats = set()
+        prefix = '_save_'
+        for item in dir(self):
+            if item.startswith(prefix):
+                formats.add(item.removeprefix(prefix).upper())
+        return formats
+
+    def load_config(self, config_file: TextIO, rom_idx: Optional[int]) -> None:
+        """Load ROM parameters from QEMU 'readconfig' file.
+
+        :param config_file: the config file text stream
+        :param rom_idx: the ROM index (when several ROMs are defined)
+        """
+        config = RawConfigParser()
+        config.read_file(config_file)
+        for section in config.sections():
+            prefix = 'ot_device '
+            if not section.startswith(prefix):
+                continue
+            devname = section.removeprefix(prefix).strip(' "')
+            devdescs = devname.split('.')
+            devtype = devdescs[0]
+            if devtype != 'ot-rom_ctrl':
+                continue
+            if len(devdescs) > 1:
+                devinst = devdescs[-1]
+                prefix = 'rom'
+                if not devinst.startswith(prefix):
+                    raise ValueError(f'Invalid ROM instance name: {devinst}')
+                devidx_str = devinst.removeprefix(prefix)
+            else:
+                devidx_str = ''
+            if devidx_str:
+                devidx = int(devidx_str)
+                if devidx != rom_idx:
+                    continue
+            elif rom_idx:
+                continue
+            for opt in config.options(section):
+                val = config.get(section, opt).strip('"')
+                setattr(self, opt, unhexlify(val))
+            return
+        if rom_idx is None:
+            rom_idx = 'undefined'
+        raise ValueError(f"Unable to find configuration for ROM '{rom_idx}'")
+
+    @property
+    def digest(self) -> bytes:
+        """Return the current digest of the ROM image.
+
+           Digest is computed on-the-fly if not already known.
+
+           :return: the digest
+        """
+        if not self._digest:
+            self._make_digest()
+        return self._digest
+
+    @property
+    def hexdigest(self) -> str:
+        """Return the current digest of the ROM image.
+
+           Digest is computed on-the-fly if not already known.
+
+           :return: the digest as a hexa string.
+        """
+        return hexlify(self.digest).decode()
+
+    @property
+    def key(self) -> Optional[int]:
+        """Key observer."""
+        return None if self._key is None else self._key.to_bytes(16, 'big')
+
+    @key.setter
+    def key(self, value: bytes) -> None:
+        """Key modifier."""
+        if not isinstance(value, bytes):
+            raise TypeError('Key must be bytes')
+        self._key = int.from_bytes(value, 'big')
+        self._khi = self._key >> 64
+        self._klo = self._key & 0xFFFFFFFFFFFFFFFF
+
+    @property
+    def nonce(self) -> Optional[int]:
+        """Nonce observer."""
+        return None if self._nonce is None else self._nonce.to_bytes(8, 'big')
+
+    @nonce.setter
+    def nonce(self, value: bytes):
+        """Nonce modifier."""
+        if not isinstance(value, bytes):
+            raise TypeError('Nonce must be bytes')
+        self._nonce = int.from_bytes(value, 'big')
+        self._addr_nonce = 0
+        self._data_nonce = 0
+
+    @classmethod
+    def ctz(cls, val: int) -> int:
+        """Count trailing zero bit in an integer."""
+        if val == 0:
+            raise ValueError('CTZ undefined')
+        pos = 0
+        while (val & 1) == 0:
+            val >>= 1
+            pos += 1
+        return pos
+
+    @classmethod
+    def bitswap(cls, in_: int, mask: int, shift: int) -> int:
+        """Bit swapping helper function."""
+        return ((in_ & mask) << shift) | ((in_ & ~mask) >> shift)
+
+    @classmethod
+    def bitswap64(cls, val: int) -> int:
+        """Swap (reverse) 64-bit integer."""
+        val = cls.bitswap(val, 0x5555555555555555, 1)
+        val = cls.bitswap(val, 0x3333333333333333, 2)
+        val = cls.bitswap(val, 0x0f0f0f0f0f0f0f0f, 4)
+        val = cls.bitswap(val, 0x00ff00ff00ff00ff, 8)
+        val = cls.bitswap(val, 0x0000ffff0000ffff, 16)
+        val = (val << 32) | (val >> 32)
+
+        return val
+
+    @classmethod
+    def sbox(cls, in_: int, width: int, sbox: int) -> int:
+        """PRESENT S-box permutation."""
+        assert width < 64
+
+        full_mask = (1 << width) - 1
+        width &= ~3
+        sbox_mask = (1 << width) - 1
+
+        out = in_ & (full_mask & ~sbox_mask)
+        for ix in range(0, width, 4):
+            nibble = (in_ >> ix) & 0xf
+            out |= sbox[nibble] << ix
+
+        return out
+
+    @classmethod
+    def flip(cls, in_: int, width: int) -> int:
+        """Reverse N bit in an integer."""
+        out = cls.bitswap64(in_)
+        out >>= 64 - width
+
+        return out
+
+    @classmethod
+    def perm(cls, in_: int, width: int, invert: bool) -> int:
+        """PRESENT permutation."""
+        assert width < 64
+
+        full_mask = (1 << width) - 1
+        width &= ~1
+        bfly_mask = (1 << width) - 1
+
+        out = in_ & (full_mask & ~bfly_mask)
+
+        width >>= 1
+        if not invert:
+            for ix in range(width):
+                bit = (in_ >> (ix << 1)) & 1
+                out |= bit << ix
+                bit = (in_ >> ((ix << 1) + 1)) & 1
+                out |= bit << (width + ix)
+        else:
+            for ix in range(width):
+                bit = (in_ >> ix) & 1
+                out |= bit << (ix << 1)
+                bit = (in_ >> (ix + width)) & 1
+                out |= bit << ((ix << 1) + 1)
+
+        return out
+
+    @classmethod
+    def subst_perm_enc(cls, in_: int, key: int, width: int, num_round: int) \
+            -> int:
+        """Substitute-permute rounds."""
+        state = in_
+        while num_round:
+            num_round -= 1
+            state ^= key
+            state = cls.sbox(state, width, cls.SBOX4)
+            state = cls.flip(state, width)
+            state = cls.perm(state, width, False)
+        state ^= key
+
+        return state
+
+    @classmethod
+    def subst_perm_dec(cls, val: int, key: int, width: int, num_round: int) \
+            -> int:
+        """Substitute-permute rounds."""
+        state = val
+        while num_round:
+            num_round -= 1
+            state ^= key
+            state = cls.perm(state, width, True)
+            state = cls.flip(state, width)
+            state = cls.sbox(state, width, cls.SBOX4_INV)
+        state ^= key
+
+        return state
+
+    def addr_sp_enc(self, addr: int) -> int:
+        """Encode a logical (CPU) address into a physical (ROM storage) address.
+        """
+        return self.subst_perm_enc(addr, self._addr_nonce, self._addr_width,
+                                   self.ADDR_SUBST_PERM_ROUNDS)
+
+    def addr_sp_dec(self, addr: int) -> int:
+        """Decode a physical (ROM storage) address into a logical (CPU) address.
+        """
+        return self.subst_perm_dec(addr, self._addr_nonce, self._addr_width,
+                                   self.ADDR_SUBST_PERM_ROUNDS)
+
+    @classmethod
+    def add_ecc_inv_39_32(cls, data: int) -> int:
+        """Compute and add HSIAO SEC-DEC to a 32 bit value.
+
+           :param data: 32-bit value
+           :return: 39-bit value (upper bits contain the ECC)
+        """
+        ecc = 0
+        inv = False
+        for mask in reversed(cls.ECC_39_32):
+            ecc <<= 1
+            parity = (data & mask).bit_count() & 1
+            ecc |= parity ^ int(inv)
+            inv = not inv
+        return (ecc << 32) | data
+
+    @classmethod
+    @lru_cache
+    def data_sp_enc(cls, val: int) -> int:
+        """Encode (scramble) data."""
+        return cls.subst_perm_enc(val, 0, cls.WORD_BITS,
+                                  cls.DATA_SUBST_PERM_ROUNDS)
+
+    @classmethod
+    @lru_cache
+    def data_sp_dec(cls, val: int) -> int:
+        """Decode (unscramble) data."""
+        return cls.subst_perm_dec(val, 0, cls.WORD_BITS,
+                                  cls.DATA_SUBST_PERM_ROUNDS)
+
+    def _load_hex(self, rfp: BinaryIO, size: Optional[int]) -> None:
+        words: list[int] = []  # 64-bit values
+        for lpos, line in enumerate(rfp.readlines(), start=1):
+            line = line.strip()
+            if len(line) != 10:
+                raise ValueError(f'Unsupported ROM HEX format at line {lpos}')
+            try:
+                words.append(int(line, 16))
+            except ValueError as exc:
+                raise ValueError(f'Invalid HEX data at line {lpos}: {exc}')
+        if size is not None and size != len(words) * 4:
+            raise ValueError('HEX content does not match ROM size')
+        self._handle_scrambled_data(words)
+
+    def _load_svmem(self, rfp: BinaryIO, size: Optional[int]) -> None:
+        # load VMEM handle both kinds of VMEM files
+        self._load_vmem(rfp, size)
+
+    def _load_vmem(self, rfp: BinaryIO, size: Optional[int]) -> None:
+        words: list[int] = []  # 64-bit values
+        scrambled: Optional[bool] = None
+        next_addr = 0
+        # note: address marker (@address) defines the index in the destination
+        # memory. For ROM images, each index represents a 32-bit memory address.
+        # Each location contains 32 bits of data, and optionally 7 bits of ECC.
+        # ECC extension is only supported in scrambled files. The ECC is stored
+        # in the MSB of each VMEM word.
+        for lpos, line in enumerate(rfp.readlines(), start=1):
+            line = line.strip()
+            if not line.startswith(b'@'):
+                continue
+            parts = re.split(rb'\s+', line[1:])
+            address_str = parts[0]
+            data_str = parts[1:]
+            scrambled_data = all(len(d) in (9, 10) for d in data_str)
+            plain_data = all(len(d) in (7, 8) for d in data_str)
+            if not scrambled_data ^ plain_data:
+                raise ValueError(f'Unknown VMEM format @ {lpos}')
+            if scrambled is None:
+                scrambled = scrambled_data
+                self._log.info('Identified %s as %s VMEM format',
+                               rfp.name or '?',
+                               'scrambled' if scrambled else 'plain')
+            elif scrambled != scrambled_data:
+                raise ValueError(f'Incoherent VMEM format @ {lpos}')
+            try:
+                address = int(address_str, 16)
+                words.extend(int(d, 16) for d in data_str)
+            except (TypeError, ValueError) as exc:
+                raise ValueError(f'Invalid data in VMEM format @ '
+                                 f'{lpos}') from exc
+            if address != next_addr:
+                raise ValueError(f'Incoherent next address @ {lpos}')
+            next_addr += len(data_str)
+        if scrambled is None:
+            self._log.error('No valid data found in VMEM file')
+            return
+        if scrambled:
+            if size is not None and size != len(words) * 4:
+                raise ValueError(f'ROM size ({size}) does not match the '
+                                 f'scrambled content size ({len(words) * 4})')
+            self._handle_scrambled_data(words)
+        else:
+            if not size:
+                raise ValueError('ROM size not specified')
+            clrdata = bytearray()
+            for word in words:
+                clrdata.extend(word.to_bytes(4, 'little'))
+            data_len = len(clrdata)
+            if data_len < size:
+                clrdata.extend(bytes(size - data_len))
+            self._clear_data = clrdata
+            bndigest = bytes(reversed(self.digest))
+            self._log.info('computed digest: %s', hexlify(bndigest).decode())
+
+    def _load_bin(self, rfp: BinaryIO, size: Optional[int]) -> None:
+        if not size:
+            raise ValueError('ROM size not specified')
+        if _CRYPTO_EXC:
+            raise ModuleNotFoundError('Crypto module not found')
+        data = bytearray(rfp.read())
+        data_len = len(data)
+        if data_len > size:
+            raise ValueError(f'Specified ROM size is too small to fit '
+                             f'{rfp.name or '?'}')
+        if data_len < size:
+            data.extend(bytes(size - data_len))
+        self._clear_data = data
+        bndigest = bytes(reversed(self.digest))
+        self._log.info('computed digest: %s', hexlify(bndigest).decode())
+
+    def _load_elf(self, rfp: BinaryIO, size: Optional[int]) -> None:
+        elf = ElfBlob()
+        elf.load(rfp)
+        bin_io = BytesIO(elf.blob)
+        self._load_bin(bin_io, size)
+
+    def _save_hex(self, rfp: BinaryIO) -> None:
+        # assume a scrambled output image
+        self._prepare_scrambled_data()
+        scrwords = self._scrambled_words
+        rfp.write('\n'.join(f'{scrwords[self.addr_sp_dec(pa)]:010X}'
+                            for pa in range(len(scrwords))).encode())
+        rfp.write(b'\n')
+
+    def _save_svmem(self, rfp: BinaryIO) -> None:
+        # create scrambled data if not yet available
+        self._prepare_scrambled_data()
+        scrwords = [self._scrambled_words[self.addr_sp_dec(pa)]
+                    for pa in range(len(self._scrambled_words))]
+        word_char = 10
+        addr_char = 8 + 1
+        word_per_line = (self.VMEM_LINE_WIDTH - addr_char) // (word_char + 1)
+        self._print_vmem(rfp, scrwords, word_per_line, word_char)
+
+    def _save_vmem(self, rfp: BinaryIO) -> None:
+        # scrambled output image
+        clrwords = [int.from_bytes(bs, 'little')
+                    for bs in batched(self._clear_data, 4)]
+        word_char = 8
+        addr_char = 8 + 1
+        word_per_line = (self.VMEM_LINE_WIDTH - addr_char) // (word_char + 1)
+        self._print_vmem(rfp, clrwords, word_per_line, word_char)
+
+    def _print_vmem(self, rfp: BinaryIO, words: list[int],
+                    word_per_line: int, word_char: int) -> None:
+        pos = 0
+        # note: address marker (@address) defines the index in the destination
+        # memory. See _load_vmem for details
+        for words in batched(words, word_per_line):
+            data = ' '.join(f'{w:0{word_char}X}' for w in words)
+            rfp.write(f'@{pos:08X} {data}\n'.encode())
+            pos += len(words)
+
+    def _save_bin(self, rfp: BinaryIO) -> None:
+        rfp.write(self._clear_data)
+
+    def _prepare_scrambled_data(self):
+        if self._key is None:
+            raise RuntimeError('Key not defined, cannot scramble HEX file')
+        if self._nonce is None:
+            raise RuntimeError('Nonce not defined, cannot scramble HEX file')
+        if not self._clear_data:
+            self._log.warning('No data to save')
+            return
+        # ensure scrambled data and digest are generated
+        bndigest = bytes(reversed(self.digest))
+        self._log.info('computed digest: %s', hexlify(bndigest).decode())
+
+    def _handle_scrambled_data(self, data: list[int]) -> None:
+        word_count = len(data)
+        addr_bits = self.ctz(word_count)
+        data_nonce_width = 64 - addr_bits
+        if self._key is None:
+            raise RuntimeError('Key not defined, cannot unscramble HEX file')
+        if self._nonce is None:
+            raise RuntimeError('Nonce not defined, cannot unscramble HEX file')
+        self._addr_nonce = self._nonce >> data_nonce_width
+        self._data_nonce = self._nonce & ((1 << data_nonce_width) - 1)
+        self._addr_width = addr_bits
+        self._log.debug('nonce_width: %d', data_nonce_width)
+        self._log.debug('addr_width:  %d', self._addr_width)
+        self._log.debug('addr_nonce:  %06x', self._addr_nonce)
+        self._log.debug('data_nonce:  %012x', self._data_nonce)
+        self._log.debug('key_hi:      %016x', self._khi)
+        self._log.debug('key_lo:      %016x', self._klo)
+        self._unscramble(data)
+        bndigest = bytes(reversed(self._digest))
+        self._log.info('stored digest: %s', hexlify(bndigest).decode())
+        local_digest = self.digest
+        bndigest = bytes(reversed(local_digest))
+        self._log.info('local digest:  %s', hexlify(bndigest).decode())
+        if local_digest != self._digest:
+            self._log.error('Digest mismatch')
+
+    def _get_keystream(self, addr: int):
+        scramble = (self._data_nonce << self._addr_width) | addr
+        stream = PrinceCipher.run(scramble, self._khi, self._klo,
+                                  self._prince_half_rounds)
+        return stream & ((1 << self.WORD_BITS) - 1)
+
+    def _scramble_word(self, addr: int, value: int):
+        keystream = self._get_keystream(addr)
+        if not self._snp:
+            return keystream ^ value
+        return self.data_sp_enc(keystream ^ value)
+
+    def _unscramble_word(self, addr: int, value: int):
+        keystream = self._get_keystream(addr)
+        if not self._snp:
+            return keystream ^ value
+        spd = self.data_sp_dec(value)
+        return keystream ^ spd
+
+    def _scramble(self, data: Union[bytes, bytearray]) -> None:
+        data_len = len(data)
+        if data_len & (data_len - 1):
+            self._log.warning('Unexpected data length: %d, not a 2^N value',
+                              data_len)
+        word_count = data_len // 4
+        addr_bits = self.ctz(word_count)
+        data_nonce_width = 64 - addr_bits
+        if self._nonce is None:
+            raise RuntimeError('Nonce not defined, cannot scramble data')
+        addr_nonce = self._nonce >> data_nonce_width
+        data_nonce = self._nonce & ((1 << data_nonce_width) - 1)
+        addr_width = addr_bits
+        if not self._addr_nonce:
+            self._addr_nonce = addr_nonce
+        elif self._addr_nonce != addr_nonce:
+            raise RuntimeError('Addr nonce discrepancy')
+        if not self._data_nonce:
+            self._data_nonce = data_nonce
+        elif self._data_nonce != data_nonce:
+            raise RuntimeError('Data nonce discrepancy')
+        if not self._addr_width:
+            self._addr_width = addr_width
+        elif self._addr_width != addr_width:
+            raise RuntimeError('Addr width discrepancy')
+        self._log.debug('nonce_width: %d', data_nonce_width)
+        self._log.debug('addr_width:  %d', self._addr_width)
+        self._log.debug('addr_nonce:  %06x', self._addr_nonce)
+        self._log.debug('data_nonce:  %012x', self._data_nonce)
+        scrambled: list[int] = []
+        word_count = len(data) // 4
+        dig_addr = len(data) - self.DIGEST_BYTES
+        for log_addr in range(word_count):
+            assert 0 <= log_addr < word_count
+            byte_addr = log_addr << 2
+            clrdata = int.from_bytes(data[byte_addr:byte_addr + 4], 'little')
+            if byte_addr < dig_addr:
+                clrdata = self.add_ecc_inv_39_32(clrdata)
+                assert 0 <= clrdata < (1 << self.WORD_BITS), "invalid data"
+                scrdata = self._scramble_word(log_addr, clrdata)
+                scrambled.append(scrdata)
+            else:
+                # digest is not scrambled and contains no ECC
+                scrambled.append(clrdata)
+        self._scrambled_words = scrambled
+
+    def _unscramble(self, scr: list[int]) -> None:
+        # do not attempt to detect or correct errors for now
+        word_count = len(scr)  # each slot is a 32-bit data value + ECC
+        if word_count & (word_count - 1):
+            self._log.warning('Unexpected word count: %d, not a 2^N value',
+                              word_count)
+        scr_word_count = word_count - self.DIGEST_BYTES // 4
+        self._log.debug('word_count: %d, scr_word_count %d',
+                        word_count, scr_word_count)
+        log_addr = 0
+        dst: list[int] = [0] * word_count  # 32-bit values
+        scrambled_words: list[int] = []
+        while log_addr < scr_word_count:
+            phy_addr = self.addr_sp_enc(log_addr)
+            assert phy_addr < word_count, "unexpected physical address"
+            scrdata = scr[phy_addr]
+            scrambled_words.append(scrdata)
+            clrdata = self._unscramble_word(log_addr, scrdata)
+            dst[log_addr] = clrdata & 0xffffffff
+            log_addr += 1
+        # digest words are not scrambled
+        wix = 0
+        digest_parts: list[int] = []  # 32-bit values
+        while wix < self.DIGEST_WORDS:
+            phy_addr = self.addr_sp_enc(log_addr)
+            assert phy_addr < word_count, "unexpected physical address"
+            word = scr[phy_addr] & 0xffffffff
+            scrambled_words.append(word)
+            digest_parts.append(word)
+            wix += 1
+            log_addr += 1
+        digest = b''.join((dp.to_bytes(4, 'little') for dp in digest_parts))
+        data = bytearray()
+        for val in dst:
+            data.extend(val.to_bytes(4, 'little'))
+        self._clear_data = data
+        self._scrambled_words = scrambled_words
+        self._digest = digest
+
+    def _compute_digest(self) -> None:
+        scrambled_data = bytearray()
+        word_bytes = len(self._clear_data)
+        scr_word_count = (word_bytes - self.DIGEST_BYTES) // 4
+        for word in self._scrambled_words[:scr_word_count]:
+            scrambled_data.extend(word.to_bytes(self.WORD_BYTES, 'little'))
+        shake = cSHAKE256.new(custom=b'ROM_CTRL')
+        shake.update(scrambled_data)
+        self._digest = shake.read(self.DIGEST_BYTES)
+        if len(self._scrambled_words) > scr_word_count:
+            self._scrambled_words[:] = self._scrambled_words[:scr_word_count]
+        digest_words = [int.from_bytes(self._digest[a:a+4], 'little')
+                        for a in range(0, len(self._digest), 4)]
+        self._scrambled_words.extend(digest_words)
+
+    def _make_digest(self) -> bytes:
+        if not self._scrambled_words:
+            self._scramble(self._clear_data)
+        self._compute_digest()
+        return self._digest
diff --git a/python/qemu/ot/socdbg/__init__.py b/python/qemu/ot/socdbg/__init__.py
new file mode 100644
index 0000000000000..7f28e7c541e5a
--- /dev/null
+++ b/python/qemu/ot/socdbg/__init__.py
@@ -0,0 +1,6 @@
+"""SoC debug controller."""
+
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+from .socdbgdmi import SocDbgController  # noqa: F401
diff --git a/python/qemu/ot/socdbg/socdbgdmi.py b/python/qemu/ot/socdbg/socdbgdmi.py
new file mode 100644
index 0000000000000..30f069222dc4c
--- /dev/null
+++ b/python/qemu/ot/socdbg/socdbgdmi.py
@@ -0,0 +1,117 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""SoC Debug Controller DMI.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from logging import getLogger
+from typing import NamedTuple
+
+from ot.dtm import DebugTransportModule
+
+
+class SocDbgStatus(NamedTuple):
+    """Execution status."""
+    auth_debug_intent_set: bool
+    auth_window_open: bool
+    auth_window_closed: bool
+    auth_unlock_success: bool
+    auth_unlock_failed: bool
+    current_policy: int
+    requested_policy: int
+
+
+class SocDbgBootStatus(NamedTuple):
+    """Boot status."""
+    main_clock: bool
+    io_clock: bool
+    usb_clock: bool
+    otp_done: bool
+    lc_done: bool
+    rom_good: list[bool]
+    rom_done: list[bool]
+    cpu_fetch: bool
+
+
+class SocDbgController:
+    """SoC Debug Controller over DMI."""
+
+    REGS = {'control': 0, 'jtag_status': 1, 'jtag_boot_status': 2}
+    """Registers."""
+
+    ROM_COUNT = 3
+    """Count of ROMs, including non-ROM ones."""
+
+    POLICY_WIDTH = 4
+    """Num of bits in policy fields."""
+
+    DEFAULT_DMI_ADDRESS = 0x8c0
+    """Default DMI address of the controller."""
+
+    def __init__(self, dtm: DebugTransportModule, address: int):
+        self._log = getLogger('dtm.socdbg')
+        self._dtm = dtm
+        self._dmi = dtm['dmi']
+        self._address = address
+
+    def restart_system(self) -> None:
+        """Restart the remote machine."""
+        self._dtm.engine.controller.system_reset()
+
+    def resume_boot(self, resume: bool = True) -> None:
+        """Tell the SoCDbg controller Ibex execution may resume."""
+        self._write_reg('control', int(bool(resume)))
+
+    @property
+    def status(self) -> SocDbgStatus:
+        """Report the current status."""
+        regval = self._read_reg('jtag_status')
+        values = []
+        for name, type_ in SocDbgStatus.__annotations__.items():
+            length = 1 if type_ is bool else self.POLICY_WIDTH
+            val = regval & ((1 << length) - 1)
+            values.append(type_(val))
+            regval >>= length if name != 'auth_debug_intent_set' else 4
+        status = SocDbgStatus(*values)
+        return status
+
+    @property
+    def boot_status(self) -> SocDbgBootStatus:
+        """Report the boot status."""
+        regval = self._read_reg('jtag_boot_status')
+        values = []
+        for type_ in SocDbgBootStatus.__annotations__.values():
+            item = []
+            if type_ is bool:
+                values.append(bool(regval & 1))
+                regval >>= 1
+            else:
+                item = []
+                for _ in range(self.ROM_COUNT):
+                    item.append(bool(regval & 1))
+                    regval >>= 1
+                values.append(item)
+        status = SocDbgBootStatus(*values)
+        return status
+
+    def _write_reg(self, name: str, value: int) -> None:
+        if value >= (1 << 32):
+            raise ValueError('Invalid value')
+        try:
+            reg = self.REGS[name]
+        except KeyError as exc:
+            raise ValueError(f"No such SocDbg register: '{name}'") from exc
+        self._log.info('write %s: 0x%08x', name, value)
+        return self._dmi.write(self._address + reg, value)
+
+    def _read_reg(self, name: str) -> int:
+        try:
+            reg = self.REGS[name]
+        except KeyError as exc:
+            raise ValueError(f"No such SocDbg register: '{name}'") from exc
+        self._log.info('read %s', name)
+        value = self._dmi.read(self._address + reg)
+        self._log.info('read 0x%08x', value)
+        return value
diff --git a/python/qemu/ot/spi/__init__.py b/python/qemu/ot/spi/__init__.py
new file mode 100644
index 0000000000000..1fd6cc4695b70
--- /dev/null
+++ b/python/qemu/ot/spi/__init__.py
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""SPI device tools."""
+
+from .spi_device import JedecId, SpiDevice  # noqa: F401
diff --git a/python/qemu/ot/spi/spi_device.py b/python/qemu/ot/spi/spi_device.py
new file mode 100644
index 0000000000000..a1507c17d394a
--- /dev/null
+++ b/python/qemu/ot/spi/spi_device.py
@@ -0,0 +1,458 @@
+# Copyright (c) 2023-2025, Rivos, Inc.
+# All rights reserved.
+
+"""SPI device proxy.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from binascii import hexlify
+from logging import getLogger
+from select import POLLIN, poll as spoll
+from socket import (AF_UNIX, IPPROTO_TCP, TCP_NODELAY, SHUT_RDWR, SOCK_STREAM,
+                    create_connection, socket, timeout as LegacyTimeoutError)
+from struct import calcsize as scalc, pack as spack
+from time import sleep, time as now
+from typing import NamedTuple, Optional, Union
+
+
+class JedecId(NamedTuple):
+    """JEDEC identifier.
+
+       See JEDEC Standard Manufacturer’s Identification Code (JEP106BK.pdf)
+    """
+    bank: int
+    """Which page/bank the manufacturer code belongs to."""
+    jedec: bytes
+    """JEDEC device identifier. First byte is the manufacturer code."""
+
+
+class SpiDevice:
+    """SPI device proxy that implements the SPI device protocol over TCP."""
+
+    TIMEOUT = 2.0
+    """Default allowed timeout to complete an exchange with the remote target.
+    """
+
+    CONN_TIMEOUT = 1.0
+    """Maximum time to connect to the remote peer.
+    """
+
+    POLL_TIMEOUT = 0.05
+    """Maximum time to wait on a blocking operation.
+    """
+
+    VERSION = 0
+    """Protocol version."""
+
+    CS_HEADER_FMT = '3sBBxH'
+    """CS header format."""
+
+    CS_HEADER_SIZE = scalc(CS_HEADER_FMT)
+    """Size of a CS header."""
+
+    BUSY = 1 << 0
+    """Status register BUSY bit."""
+
+    WEL = 1 << 1
+    """Status register write enabled bit."""
+
+    READ_BUFFER_SIZE = 0x400
+    """1 KiB HW buffer."""
+
+    MAILBOX_SIZE = 0x400
+    """1 KiB mailbox."""
+
+    COMMANDS = {
+        'PAGE_PROGRAM': 0x02,
+        'READ_DATA': 0x3,
+        'WRITE_DISABLE': 0x04,
+        'READ_STATUS': 0x05,
+        'WRITE_ENABLE': 0x06,
+        'FAST_READ': 0x0b,
+        'READ_SFDP': 0x5a,
+        'READ_JEDEC_ID': 0x9f,
+        'ENTER_ADDR4': 0xb7,
+        'POWER_DOWN': 0xb9,
+        'EXIT_ADDR4': 0xe9,
+        'CHIP_ERASE': 0xc7,
+        'BLOCK_ERASE': 0xd8,
+        'SECTOR_ERASE': 0x20,
+        'RESET1': 0x66,
+        'RESET2': 0x99,
+        'CHECK_ANSWER': 0xca,
+        'CUSTOM_COMMAND': 0xed,  # reserved opcode for custom commands
+    }
+    """Supported *25 SPI data flash device commands."""
+
+    def __init__(self):
+        self._log = getLogger('spidev.dev')
+        self._socket: Optional[socket] = None
+        self._mode = 0
+        self._4ben = False
+        self._rev_rx = False
+        self._rev_tx = False
+        self._timeout = self.TIMEOUT
+
+    def connect(self, host: str, port: Optional[int] = None) -> None:
+        """Open a connection to the remote host.
+
+           @param host the host name or the connection string
+           @param port the TCP port
+        """
+        if self._socket:
+            raise RuntimeError('Cannot open multiple comm port at once')
+        if port is not None:
+            if not isinstance(port, int):
+                raise ValueError('Invalid port type')
+            try:
+                self._socket = create_connection((host, port),
+                                                 timeout=self.CONN_TIMEOUT)
+                self._socket.setsockopt(IPPROTO_TCP, TCP_NODELAY, 1)
+            except OSError:
+                self._log.fatal('Cannot connect to %s:%d', host, port)
+                raise
+        else:
+            sock_args = host.split(':')
+            try:
+                if sock_args[0] == 'tcp':
+                    try:
+                        host, sport = sock_args[1:]
+                        port = int(sport)
+                    except ValueError as exc:
+                        raise ValueError('TCP port not specified') from exc
+                    self._socket = create_connection((host, port),
+                                                     timeout=self.CONN_TIMEOUT)
+                    self._socket.setsockopt(IPPROTO_TCP, TCP_NODELAY, 1)
+                elif sock_args[0] == 'unix':
+                    self._socket = socket(AF_UNIX, SOCK_STREAM)
+                    self._socket.settimeout(self.CONN_TIMEOUT)
+                    self._socket.connect(sock_args[1])
+                else:
+                    raise ValueError(f'Unsupported connection string: {host}')
+            except OSError:
+                if port:
+                    self._log.fatal('Cannot connect to %s:%d', host, port)
+                else:
+                    self._log.fatal('Cannot connect to %s', host)
+                raise
+        self._socket.settimeout(None)  # use poll
+
+    def disconnect(self) -> None:
+        """Close the communication socket."""
+        if self._socket:
+            self._socket.shutdown(SHUT_RDWR)
+            self._socket.close()
+            self._socket = None
+
+    @property
+    def exchange_timeout(self) -> float:
+        """Get the maximum allowed time to perform a SPI round trip.
+
+           :return: the timeout in seconds
+        """
+        return self._timeout
+
+    @exchange_timeout.setter
+    def exchange_timeout(self, timeout: float) -> None:
+        """Set the maximum allowed time to perform a SPI round trip.
+
+           :param timeout: the timeout in seconds
+        """
+        self._timeout = timeout
+
+    quit = disconnect
+    """Old API."""
+
+    def transmit(self, cmd: Optional[int] = None,
+                 in_payload: Union[bytes, bytearray, int, None] = None,
+                 out_len: int = 0, release: bool = True) -> bytes:
+        """SPI data transfer.
+
+           :param cmd: the command to send
+           :param in_payload: the payload to send
+           :param out_len: the count of meaningful bytes to receive
+           :param release: whether to release /CS line (to manage transactions)
+        """
+        return self._transmit(cmd, in_payload, out_len, release)
+
+    def read_status_register(self) -> int:
+        """Read out the flash status register."""
+        resp = self._transmit(self.COMMANDS['READ_STATUS'], out_len=1)
+        return resp[0]
+
+    def is_busy(self, sreg: Optional[int] = None) -> bool:
+        """Check if the flash device is busy."""
+        if sreg is None:
+            sreg = self.read_status_register()
+        return bool(sreg & self.BUSY)
+
+    def is_wel(self, sreg: Optional[int] = None) -> bool:
+        """Check if the flash device is write-enabled."""
+        if sreg is None:
+            sreg = self.read_status_register()
+        return bool(sreg & self.WEL)
+
+    def wait_idle(self, timeout: float = 1.0, pace: float = 0.0005) -> None:
+        """Wait for the flash device to become idle.
+
+           :param timeout: raise a TimeoutError if flash does not become
+                           available after this delay
+           :param pace: delay between each flash device poll request.
+        """
+        expire = timeout + now()
+        while True:
+            status = self.read_status_register()
+            if not status & self.BUSY:
+                break
+            if now() > expire:
+                raise TimeoutError(f'Busy bit stuck for {timeout:.1f}s')
+            sleep(pace)
+
+    def read_jedec_id(self) -> JedecId:
+        """Read out the flash device JEDEC ID."""
+        jedec = bytearray()
+        self.transmit(self.COMMANDS['READ_JEDEC_ID'], release=False)
+        page = 0
+        while True:
+            manuf = self.transmit(out_len=1, release=False)[0]
+            if manuf != 0x7f:
+                jedec.append(manuf)
+                break
+            page += 1
+        jedec.extend(self.transmit(out_len=2))
+        return JedecId(page, bytes(jedec))
+
+    def read_sfdp(self, address: int = 0) -> bytes:
+        """Read out the flash device SFTP descriptor."""
+        # SFTP command expects a dummy byte before the SFDP payload is actually
+        # streamed, address should be 3 byte long
+        payload = spack('>Ix', address)[1:]
+        return self.transmit(self.COMMANDS['READ_SFDP'], payload, 256)
+
+    def enable_write(self):
+        """Enable write."""
+        self.transmit(self.COMMANDS['WRITE_ENABLE'])
+
+    def disable_write(self):
+        """Disable write."""
+        self.transmit(self.COMMANDS['WRITE_DISABLE'])
+
+    def enable_4b_address(self, enable: bool):
+        """Enable or disable 4-byte addressing mode."""
+        self.transmit(self.COMMANDS['ENTER_ADDR4' if enable else 'EXIT_ADDR4'])
+        self._4ben = enable
+
+    def page_program(self, address: int, buffer: bytes):
+        """Program a page (usually 256 bytes) into the flash device.
+
+           :param address: address of the first byte to program
+           :param buffer: the page content
+        """
+        addr = spack('>I', address)
+        if not self.is_4b_addr:
+            if address >= (1 << 24):
+                raise ValueError('Cannot encode address')
+            addr = addr[1:]
+        self.transmit(self.COMMANDS['PAGE_PROGRAM'], b''.join((addr, buffer)))
+
+    def power_down(self):
+        """Power down the device (may trigger a QEMU shurtdown)."""
+        self.transmit(self.COMMANDS['POWER_DOWN'])
+
+    def chip_erase(self):
+        """Erase the content of the whole chip."""
+        self.transmit(self.COMMANDS['CHIP_ERASE'])
+
+    def block_erase(self, address: int):
+        """Erase a 64 KiB block."""
+        address &= ~(64 << 10)
+        addr = spack('>I', address)
+        if not self.is_4b_addr:
+            if address >= (1 << 24):
+                raise ValueError('Cannot encode address')
+            addr = addr[1:]
+        self.transmit(self.COMMANDS['BLOCK_ERASE'], addr)
+
+    def sector_erase(self, address: int):
+        """Erase a 4 KiB block."""
+        address &= ~(4 << 10)
+        addr = spack('>I', address)
+        if not self.is_4b_addr:
+            if address >= (1 << 24):
+                raise ValueError('Cannot encode address')
+            addr = addr[1:]
+        self.transmit(self.COMMANDS['SECTOR_ERASE'], addr)
+
+    def reset(self, alt: bool = False):
+        """Reset the flash device."""
+        self.transmit(self.COMMANDS['RESET2' if not alt else 'RESET1'])
+
+    def read(self, address: int, length: int, fast: bool = False,
+             release: bool = True) -> bytes:
+        """Read out from the flash device.
+
+           :param address: the address of the first byte to read
+           :param length: how many bytes to read
+           :param fast: whether to use the fast SPI read command
+           :param release: whether to release /CS line
+        """
+        if fast:
+            cmd = self.COMMANDS['FAST_READ']
+            dummy = True
+        else:
+            cmd = self.COMMANDS['READ_DATA']
+            dummy = False
+        addr = spack('>I', address)
+        if not self.is_4b_addr:
+            if address >= (1 << 24):
+                raise ValueError('Cannot encode address')
+            addr = addr[1:]
+        if dummy:
+            addr.append(0)
+        return self.transmit(cmd, addr, length, release)
+
+    def read_cont(self, length: int, release: bool = True) -> bytes:
+        """Continue a read transation.
+
+           :param length: how many bytes to read
+           :param release: whether to release /CS line
+        """
+        return self.transmit(None, None, length, release)
+
+    def custom_command(self, address: Optional[int] = None,
+                       payload: Optional[bytes] = None) -> bytes:
+        """Execute a custom command.
+
+           :param address: optional address, sent as 3 or 4 bytes, depending on
+                           the current mode
+           :param payload: optional payload
+        """
+        if address is not None:
+            byte_count = 4 if self.is_4b_addr else 3
+            if address >= (1 << (byte_count * 8)):
+                raise ValueError('Cannot encode address')
+            addr = spack('>I', address)
+            if not self.is_4b_addr:
+                addr = addr[1:]
+        else:
+            addr = b''
+        payload = b''.join((addr, payload or b''))
+        return self.transmit(self.COMMANDS['CUSTOM_COMMAND'], addr)
+
+    def release(self) -> None:
+        """Release /CS line."""
+        data = self._build_cs_header(0, True)
+        self._log.debug('/CS')
+        self._socket.send(data)
+
+    @staticmethod
+    def rev8(num: int) -> int:
+        """Bit-wise reversal for a byte."""
+        num = ((num >> 1) & 0x55) | ((num & 0x55) << 1)
+        num = ((num >> 2) & 0x33) | ((num & 0x33) << 2)
+        num = ((num >> 4) & 0x0f) | (num << 4)
+        return num & 0xff
+
+    def enable_rx_lsb(self, enable: bool):
+        """Change RX bit ordering."""
+        self._rev_rx = enable
+        if enable:
+            self._mode |= 1 << 3
+        else:
+            self._mode &= ~(1 << 3)
+
+    def enable_tx_lsb(self, enable: bool):
+        """Change TX bit ordering."""
+        self._rev_tx = enable
+        if enable:
+            self._mode |= 1 << 2
+        else:
+            self._mode &= ~(1 << 2)
+
+    def check_answer(self) -> None:
+        """Check is the remote peer has data to read.
+           This is a proprietary (i.e. non *25 series standard) command.
+
+           Caller should call wait_idle() till busy bit is released.
+        """
+        self.transmit(self.COMMANDS['CHECK_ANSWER'])
+
+    @property
+    def is_4b_addr(self) -> bool:
+        """Report wether 4-byte addressing mode is active."""
+        return self._4ben
+
+    def _build_cs_header(self, size: int, release: bool = True) -> bytes:
+        mode = self._mode & 0xf
+        if not release:
+            mode |= 0x80
+        header = spack(self.CS_HEADER_FMT, b'/CS', self.VERSION, mode,
+                       size)
+        self._log.debug('Header: %s', hexlify(header).decode())
+        return header
+
+    def _transmit(self, cmd: Optional[int] = None,
+                  in_payload: Union[bytes, bytearray, int, None] = None,
+                  out_len: int = 0, release: bool = True) -> bytes:
+        if isinstance(in_payload, int):
+            in_payload = bytes([0xff] * in_payload)
+        elif in_payload is not None:
+            assert isinstance(in_payload, (bytes, bytearray))
+        else:
+            in_payload = bytes()
+        assert isinstance(out_len, int) and 0 <= out_len <= 0xffff
+        if cmd is not None:
+            assert 0 <= cmd <= 0xff
+            tx_payload = b''.join((bytes([cmd]), in_payload, bytes(out_len)))
+        else:
+            tx_payload = b''.join((in_payload, bytes(out_len)))
+        if self._rev_tx:
+            tx_payload = bytes(SpiDevice.rev8(x) for x in tx_payload)
+        rx_payload = self._exchange(tx_payload, release)
+        if self._rev_rx:
+            rx_payload = bytes(SpiDevice.rev8(x) for x in rx_payload)
+        assert len(rx_payload) == len(tx_payload)
+        return rx_payload[-out_len:]
+
+    def _send(self, buf: bytes, release: bool = True):
+        data = b''.join((self._build_cs_header(len(buf), release), buf))
+        self._log.debug('TX[%d]: %s %s', len(buf), hexlify(buf).decode(),
+                        '/' if release else '...')
+        self._socket.send(data)
+
+    def _receive(self, size: int) -> bytes:
+        buf = bytearray()
+        rem = size
+        timeout = now() + self._timeout
+        poller = spoll()
+        poller.register(self._socket, POLLIN)
+        while rem:
+            for _ in poller.poll(self.POLL_TIMEOUT):
+                try:
+                    data = self._socket.recv(rem)
+                    buf.extend(data)
+                    rem -= len(data)
+                    if rem == 0:
+                        break
+                except (TimeoutError, LegacyTimeoutError):
+                    self._log.error('Unexpected timeout w/ poll')
+                    raise
+            if rem == 0:
+                break
+            if now() > timeout:
+                raise TimeoutError('Failed to receive response')
+        else:
+            raise TimeoutError(f'{"No" if len(buf) == 0 else "Truncated"} '
+                               f'response from host')
+        self._log.debug("RX[%d]: %s", len(buf), hexlify(buf).decode())
+        return bytes(buf)
+
+    def _exchange(self, requ: bytes, release: bool = True) -> bytes:
+        txlen = len(requ)
+        self._send(requ, release)
+        resp = self._receive(txlen)
+        rxlen = len(resp)
+        if rxlen != txlen:
+            raise RuntimeError(f'Response truncated {rxlen}/{txlen}')
+        return resp
diff --git a/python/qemu/ot/top/__init__.py b/python/qemu/ot/top/__init__.py
new file mode 100644
index 0000000000000..9dfa907f46a27
--- /dev/null
+++ b/python/qemu/ot/top/__init__.py
@@ -0,0 +1,27 @@
+# Copyright (c) 2025 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""OpenTitan Tops."""
+
+from ot.util.misc import classproperty
+from typing import Optional
+
+
+class OpenTitanTop:
+    """OpenTitan supported tops."""
+
+    SHORT_MAP = {
+        'darjeeling': 'dj',
+        'earlgrey': 'eg',
+    }
+
+    @classproperty
+    def names(cls) -> list[str]:
+        """Supported top names."""
+        # pylint: disable=no-self-argument
+        return list(cls.SHORT_MAP)
+
+    @classmethod
+    def short_name(cls, topname: str) -> Optional[str]:
+        """Get the short form of a top."""
+        return cls.SHORT_MAP.get(topname.lower())
diff --git a/python/qemu/ot/util/__init__.py b/python/qemu/ot/util/__init__.py
new file mode 100644
index 0000000000000..06db848f9d4b2
--- /dev/null
+++ b/python/qemu/ot/util/__init__.py
@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Utilities."""
diff --git a/python/qemu/ot/util/arg.py b/python/qemu/ot/util/arg.py
new file mode 100644
index 0000000000000..0ad2fa844788d
--- /dev/null
+++ b/python/qemu/ot/util/arg.py
@@ -0,0 +1,32 @@
+# Copyright (c) 2024-2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""ArgumentParser extension.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+# pylint: disable=unused-import
+# ruff: noqa: F401
+from argparse import ArgumentParser as _ArgumentParser
+from sys import stderr
+
+
+class ArgError(Exception):
+    """Argument error.
+
+       ArgError may be used to signal an argument parser error from a call
+       stack back to the ArgumentParser instance.
+    """
+
+
+class ArgumentParser(_ArgumentParser):
+    """Report usage error first, before printing out the usage. This enables
+       catching the first line as the main error message.
+    """
+
+    def error(self, message):
+        print(f'{self.prog}: error: {message}\n', file=stderr)
+        self.print_usage(stderr)
+        self.exit(2)
diff --git a/python/qemu/ot/util/elf.py b/python/qemu/ot/util/elf.py
new file mode 100644
index 0000000000000..1a67484188ff8
--- /dev/null
+++ b/python/qemu/ot/util/elf.py
@@ -0,0 +1,262 @@
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""ELF helpers.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from io import BytesIO
+from logging import getLogger
+from os.path import basename
+from typing import BinaryIO, Iterator, NamedTuple, Optional
+import re
+
+try:
+    _ELF_ERROR = None
+    # note: pyelftools package is an OpenTitan toolchain requirement, see
+    # python-requirements.txt file from OT top directory.
+    from elftools.common.exceptions import ELFError
+    from elftools.elf.constants import SH_FLAGS
+    from elftools.elf.elffile import ELFFile
+    from elftools.elf.sections import Section, SymbolTableSection
+    from elftools.elf.segments import Segment
+except ImportError as elf_exc:
+    _ELF_ERROR = str(elf_exc)
+
+try:
+    _RUST_ERROR = None
+    from rust_demangler import demangle as rust_demangle
+except ImportError as rust_exc:
+    _RUST_ERROR = rust_exc
+    def rust_demangle(sym):  # noqa: E301
+        """Fake demangler."""
+        return sym
+
+
+class ElfSymbolExtent(NamedTuple):
+    """ELF symbol extent."""
+
+    start: int  # start address
+    end: int  # end address
+    func: str  # function name
+    module: str  # ELF name
+
+
+class ElfBlob:
+    """Load ELF application."""
+
+    ELF_ERROR = _ELF_ERROR
+    """Report whether ELF tools have been loaded."""
+
+    RUST_ERROR = _RUST_ERROR
+    """Report whether Rust tools have been loaded."""
+
+    RUST_TRAIL_CRE = re.compile(r'::h[0-9a-f]{16}$')
+    """Regex to get rid of Rust trailing symbol string."""
+
+    def __init__(self):
+        if self.ELF_ERROR:
+            raise ImportError('pyelftools package not available')
+        self._log = getLogger('elf')
+        self._elf: Optional[ELFFile] = None
+        self._payload_address: int = 0
+        self._payload_size: int = 0
+        self._payload: bytes = b''
+        self._name = ''
+
+    def load(self, efp: BinaryIO) -> None:
+        """Load the content of an ELF file.
+
+           The ELF file stream is no longer accessed once this method
+           completes.
+
+           :param efp: a File-like (binary read access)
+        """
+        # use a copy of the stream to release the file pointer.
+        try:
+            self._elf = ELFFile(BytesIO(efp.read()))
+            self._name = efp.name
+        except ELFError as exc:
+            raise ValueError(f'Invalid ELF file: {exc}') from exc
+        if self._elf['e_machine'] != 'EM_RISCV':
+            raise ValueError('Not an RISC-V ELF file')
+        if self._elf['e_type'] != 'ET_EXEC':
+            raise ValueError('Not an executable ELF file')
+        self._log.debug('entry point: 0x%X', self.entry_point)
+        self._log.debug('data size: %d', self.size)
+
+    @property
+    def address_size(self) -> int:
+        """Provide the width of address value used in the ELFFile.
+
+           :return: the address width in bits (not bytes!)
+        """
+        return self._elf.elfclass if self._elf else 0
+
+    @property
+    def entry_point(self) -> Optional[int]:
+        """Provide the entry point of the application, if any.
+
+           :return: the entry point address
+        """
+        return self._elf and self._elf.header.get('e_entry', None)
+
+    @property
+    def size(self) -> int:
+        """Provide the size of the payload section, if any.
+
+           :return: the data/payload size in bytes
+        """
+        if not self._payload_size:
+            self._payload_address, self._payload_size = self._parse_segments()
+        return self._payload_size
+
+    @property
+    def load_address(self) -> int:
+        """Provide the first destination address on target to copy the
+           application blob.
+
+           :return: the load address
+        """
+        if not self._payload_address:
+            self._payload_address, self._payload_size = self._parse_segments()
+        return self._payload_address
+
+    @property
+    def blob(self) -> bytes:
+        """Provide the application blob, i.e. the whole loadable binary.
+
+           :return: the raw application binary.
+        """
+        if not self._payload:
+            self._payload = self._build_payload()
+        if len(self._payload) != self.size:
+            raise RuntimeError('Internal error: size mismatch')
+        return self._payload
+
+    @property
+    def name(self) -> str:
+        """Return the filename of the loaded ELF."""
+        return basename(self._name)
+
+    @property
+    def code_span(self) -> tuple[int, int]:
+        """Report the extent of the executable portion of the ELF file.
+
+           :return: (start address, end address)
+        """
+        loadable_segments = list(self._loadable_segments())
+        base_addr = None
+        last_addr = None
+        for section in self._elf.iter_sections():
+            if not self.is_section_executable(section):
+                continue
+            for segment in loadable_segments:
+                if segment.section_in_segment(section):
+                    break
+            else:
+                continue
+            addr = section.header['sh_addr']
+            size = section.header['sh_size']
+            if base_addr is None or base_addr > addr:
+                base_addr = addr
+            last = addr + size
+            if last_addr is None or last_addr < last:
+                last_addr = last
+            self._log.debug('Code section @ 0x%08x 0x%08x bytes', addr, size)
+        return base_addr, last_addr
+
+    def is_section_executable(self, section: 'Section') -> bool:
+        """Report whether the section is flagged as executable.
+
+           :return: True is section is executable
+        """
+        return bool(section.header['sh_flags'] & SH_FLAGS.SHF_EXECINSTR)
+
+    def get_symbols(self) -> list[ElfSymbolExtent]:
+        """Retrieve symbols from ELF.
+
+           :return: a list of symbol extents
+        """
+        symbols = []
+        name = self.name
+        for sect in self._elf.iter_sections():
+            if not isinstance(sect, SymbolTableSection):
+                continue
+            for symb in sect.iter_symbols():
+                if not symb.name or symb.name.startswith('.L'):
+                    continue
+                if symb.entry.st_info.type != 'STT_FUNC':
+                    continue
+                func = symb.name
+                if func.startswith('_ZN'):
+                    func = rust_demangle(func)
+                    func = self.RUST_TRAIL_CRE.sub('', func)
+                symbols.append((symb.entry.st_value,
+                                symb.entry.st_value + symb.entry.st_size, func,
+                                name))
+        symbols.sort(key=lambda s: (s[0], s[1]))
+        for addr, end, func, _ in symbols:
+            self._log.debug('%s: %08x..%08x %s', name, addr, end, func)
+        return symbols
+
+    def _loadable_segments(self) -> Iterator['Segment']:
+        """Provide an iterator on segments that should be loaded into the final
+           binary.
+        """
+        if not self._elf:
+            raise RuntimeError('No ELF file loaded')
+        for segment in sorted(self._elf.iter_segments(),
+                              key=lambda seg: seg['p_paddr']):
+            if segment['p_type'] not in ('PT_LOAD', ):
+                continue
+            if not segment['p_filesz']:
+                continue
+            yield segment
+
+    def _parse_segments(self) -> tuple[int, int]:
+        """Parse ELF segments and extract physical location and size.
+
+           :return: the location of the first byte and the overall payload size
+                    in bytes
+        """
+        size = 0
+        phy_start = None
+        for segment in self._loadable_segments():
+            seg_size = segment['p_filesz']
+            if not seg_size:
+                continue
+            phy_addr = segment['p_paddr']
+            if phy_start is None:
+                phy_start = phy_addr
+            else:
+                if phy_addr > phy_start+size:
+                    self._log.debug('fill gap with previous segment')
+                    size = phy_addr-phy_start
+            size += seg_size
+        if phy_start is None:
+            raise ValueError('No loadable segment found')
+        return phy_start, size
+
+    def _build_payload(self) -> bytes:
+        """Extract the loadable payload from the ELF file and generate a
+           unique, contiguous binary buffer.
+
+           :return: the payload to store as the application blob
+        """
+        buf = BytesIO()
+        phy_start = None
+        for segment in self._loadable_segments():
+            phy_addr = segment['p_paddr']
+            if phy_start is None:
+                phy_start = phy_addr
+            else:
+                current_addr = phy_start+buf.tell()
+                if phy_addr > current_addr:
+                    fill_size = phy_addr-current_addr
+                    buf.write(bytes(fill_size))
+            buf.write(segment.data())
+        data = buf.getvalue()
+        buf.close()
+        return data
diff --git a/python/qemu/ot/util/eval.py b/python/qemu/ot/util/eval.py
new file mode 100644
index 0000000000000..0768b58286b17
--- /dev/null
+++ b/python/qemu/ot/util/eval.py
@@ -0,0 +1,62 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Safe expression evaluation.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from typing import Any
+
+import ast
+import operator
+
+
+def safe_eval(value: str, parameters: dict[str, int]) -> int:
+    """Evaluate a basic arithmetic expression using known parameters.
+
+        This is much safer than default Python's eval/expr functions, which
+        could execute any untrusted code.
+
+        Here, only known variables are replaced and basic arithmetic
+        operations are allowed.
+
+        :param value: the value to evaluate
+        :param parameters: a map a key-val named integer values
+        :return: the evaluated integer
+        :raise ValueError: for any unsupported syntax.
+    """
+    def _eval(node: ast.AST) -> Any:
+        if isinstance(node, ast.Expression):
+            return _eval(node.body)
+
+        # Numeric literal (Python 3.8+: ast.Constant)
+        if isinstance(node, ast.Constant):
+            if isinstance(node.value, (int, float)):
+                return node.value
+            raise ValueError('Unsupported constant')
+
+        # Variables/names
+        if isinstance(node, ast.Name):
+            if node.id in parameters:
+                return parameters[node.id]
+            raise ValueError(f'Unknown parameter: {node.id}')
+
+        # Binary operations
+        if isinstance(node, ast.BinOp):
+            op_type = type(node.op)
+            oper = {
+                ast.Add: operator.add,
+                ast.Sub: operator.sub,
+                ast.Mult: operator.mul,
+                ast.Div: operator.truediv,
+            }.get(op_type)
+            if not oper:
+                raise ValueError(f'Cannot evaluate: {op_type.__name__}')
+            left = _eval(node.left)
+            right = _eval(node.right)
+            return oper(left, right)
+
+        raise ValueError(f'Unsupported expression: {type(node).__name__}')
+
+    return _eval(ast.parse(value, mode='eval'))
diff --git a/python/qemu/ot/util/file.py b/python/qemu/ot/util/file.py
new file mode 100644
index 0000000000000..d4b25727f19aa
--- /dev/null
+++ b/python/qemu/ot/util/file.py
@@ -0,0 +1,116 @@
+# Copyright (c) 2023-2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""File utilities.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from io import BufferedReader
+from os import stat
+from os.path import relpath
+from time import localtime, strftime
+from typing import BinaryIO, TextIO, Union
+
+import re
+
+from .elf import ElfBlob
+from .recfmt import RecordSegment, VMemBuilder
+
+
+def guess_file_type(file: Union[str, BufferedReader]) -> str:
+    """Guess a file type from its contents.
+
+       Only supports useful type for QEMU/OT needs.
+
+       :return: identified content
+    """
+    if isinstance(file, str):
+        with open(file, 'rb') as bfp:
+            header = bfp.read(1024)
+    elif isinstance(file, BufferedReader):
+        header = file.peek(1024)
+    else:
+        raise TypeError('file must be a string or a binary file object')
+    if header[:4] == b'\x7fELF':
+        return 'elf'
+    if header[:4] == b'OTPT':
+        return 'spiflash'
+    vmem_re = rb'(?i)^@[0-9A-F]{4,}\s([0-9A-F]{6,})'
+    for line in header.split(b'\n'):
+        if line.startswith(b'/*') or line.startswith(b'#'):
+            continue
+        vmo = re.match(vmem_re, line)
+        if vmo:
+            bcount = len(vmo.group(1)) // 2
+            # heuristic for VMEM files:
+            # - plain VMEM contain 16 or 32 data bit per block
+            # - special VMEM (ECC, scrambled, ...) usually contain an extra byte
+            # we only need to distinguish this kinds of files for now, it is not
+            # intended to be used for any purpose outside QEMU & Verilator
+            # tooling.
+            reg = bcount & 1 == 0
+            return 'vmem' if reg else 'svmem'
+    hex_re = rb'(?i)^[0-9A-F]{6,}'
+    count = 0
+    for line in header.split(b'\n'):
+        if re.match(hex_re, line) and (len(line) & 1) == 0:
+            count += 1
+        else:
+            count = 0
+            break
+        if count > 4:
+            return 'hex'
+    return 'bin'
+
+
+def make_vmem_from_elf(elf_file: Union[str, BinaryIO],
+                       vmem_file: Union[str, TextIO],
+                       offset: int = 0,
+                       chunksize: int = 4,
+                       offsetsize: int = 0,
+                       close_elf: bool = True) -> None:
+    """Create a VMEM file from an ELF file.
+
+       :param elf_file:   ELF to convert, as either a file path or a binary
+                          file object
+       :param vmem_file:  ELF to convert, either a file path or a text file
+                          object
+       :param offset:     optional offset in bytes within the VMEM file to store
+                          the ELF blob
+       :param chunksize:  how many bytes per VMEM chunk to generate
+       :param offsetsize: how many chars to use to emit the chunk offset
+       :param close_elf:  whether to close the ELF input file object
+    """
+    elf = ElfBlob()
+    if isinstance(elf_file, str):
+        with open(elf_file, 'rb') as efp:
+            elfstat = stat(efp.fileno())
+            elf.load(efp)
+        elfname = relpath(elf_file)
+    else:
+        elf.load(elf_file)
+        elfname = relpath(elf_file.name)
+        elfstat = stat(elf_file.fileno())
+        if close_elf:
+            elf_file.close()
+
+    seg = RecordSegment()
+    seg.write(elf.blob, offset=offset)
+
+    vmem = VMemBuilder(byteorder='little', chunksize=chunksize,
+                       offsetsize=offsetsize)
+    vmem.build([seg])
+
+    elftime = localtime(elfstat.st_mtime)
+    is_path = isinstance(vmem_file, str)
+    with open(vmem_file, 'wt') if is_path else vmem_file as vfp:
+        print(f'// name:       {elfname}', file=vfp)
+        print(f'// built:      {strftime("%Y/%m/%d %H:%M:%S", elftime)}',
+              file=vfp)
+        print(f'// size:       {elfstat.st_size}', file=vfp)
+        print(f'// rawsize:    {elf.size}', file=vfp)
+        print(f'// entrypoint: 0x{elf.entry_point:08x}', file=vfp)
+        print(file=vfp)
+        vfp.write(vmem.getvalue())
diff --git a/python/qemu/ot/util/log.py b/python/qemu/ot/util/log.py
new file mode 100644
index 0000000000000..fd881ad06a5d9
--- /dev/null
+++ b/python/qemu/ot/util/log.py
@@ -0,0 +1,385 @@
+# Copyright (c) 2023-2024 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Logging helpers.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from os import getenv, isatty
+from pickle import loads as ploads
+from socketserver import DatagramRequestHandler, ThreadingUDPServer
+from struct import calcsize as scalc, unpack as sunpack
+from sys import stderr
+from threading import Thread
+from typing import NamedTuple, Optional, Sequence, Union
+
+import logging
+from logging.handlers import (DatagramHandler, MemoryHandler,
+                              DEFAULT_UDP_LOGGING_PORT)
+
+
+try:
+    getLevelNamesMapping = logging.getLevelNamesMapping
+except AttributeError:
+    # getLevelNamesMapping not supported on old Python versions (< 3.11)
+    def getLevelNamesMapping() -> dict[str, int]:
+        # pylint: disable=invalid-name,missing-function-docstring
+        return {lvl: getattr(logging, lvl) for lvl in
+                'CRITICAL FATAL ERROR WARNING INFO DEBUG'.split()}
+
+_LEVELS = {k: v for k, v in getLevelNamesMapping().items()
+           if k not in ('NOTSET', 'WARN')}
+
+
+FileHandler = logging.FileHandler
+
+
+class Color(NamedTuple):
+    """Simple color wrapper."""
+    color: str
+
+
+class ColorLogFormatter(logging.Formatter):
+    """Custom log formatter for ANSI terminals.
+       Colorize log levels.
+
+       Optional features:
+         * 'time' (boolean): prefix log messsages with 24h HH:MM:SS time
+         * 'ms' (boolean): prefix log messages with 24h HH:MM:SS.msec time
+         * 'lineno'(boolean): show line numbers
+         * 'name_width' (int): padding width for logger names
+         * 'color' (boolean): enable/disable log level colorization
+    """
+
+    COLORS = {
+        'BLUE': 34,
+        'CYAN': 36,
+        'YELLOW': 33,
+        'GREEN': 32,
+        'MAGENTA': 35,
+        'RED': 31,
+        'GREY': 38,
+        'WHITE': 37,
+        'BLACK': 30,
+    }
+
+    XCOLORS = (
+        202,
+        214,
+        228,
+        154,
+        48,
+        39,
+        111,
+        135,
+        165,
+        197,
+        208,
+        226,
+        82,
+        51,
+        105,
+        99,
+        171,
+        201,
+    )
+    """Extended ANSI colors for 256-color terminals."""
+
+    RESET = "\x1b[0m"
+    FMT_LEVEL = '%(levelname)8s'
+
+    # pylint: disable=no-self-argument
+    def _make_fg_color(code: int, ext: bool = False,
+                       bright: Optional[bool] = None) -> str:
+        """Create the ANSI escape sequence for a foregound color.
+
+           :param code: color code
+           :param ext: whether to use limited (16) or extended (256) color
+                       palette
+           :param bright: when set, use bright mode
+           :return: the ANSI escape sequence
+        """
+        if not ext:
+            if not 30 <= code <= 39:
+                raise ValueError(f'Invalid ANSI color: {code}')
+            bri = 1 if bright else 20
+            return f'\x1b[{code};{bri}m' if code != 38 else '\x1b[38;20m'
+        if not 0 <= code < 255:
+            raise ValueError(f'Invalid ANSI color: {code}')
+        return f'\x1b[38;5;{code}m'
+
+    # pylint: disable=no-staticmethod-decorator
+    make_fg_color = staticmethod(_make_fg_color)
+
+    LOG_COLORS = {
+        logging.DEBUG: _make_fg_color(COLORS['GREY']),
+        logging.INFO: _make_fg_color(COLORS['WHITE'], bright=True),
+        logging.WARNING: _make_fg_color(COLORS['YELLOW'], bright=True),
+        logging.ERROR: _make_fg_color(COLORS['RED'], bright=True),
+        logging.CRITICAL: _make_fg_color(COLORS['MAGENTA'], bright=True),
+    }
+
+    def __init__(self, *args, **kwargs):
+        kwargs = dict(kwargs)
+        name_width = kwargs.pop('name_width', 10)
+        self._use_ansi = kwargs.pop('ansi', isatty(stderr.fileno()))
+        self._use_xansi = self._use_ansi and getenv('TERM', '').find('256') >= 0
+        use_func = kwargs.pop('funcname', False)
+        use_ms = kwargs.pop('ms', False)
+        use_time = kwargs.pop('time', use_ms)
+        use_lineno = kwargs.pop('lineno', False)
+        super().__init__(*args, **kwargs)
+        self._logger_colors: dict[str, tuple[str, str]] = {}
+        if use_time:
+            tfmt = '%(asctime)s ' if not use_ms else '%(asctime)s.%(msecs)03d '
+        else:
+            tfmt = ''
+        sep = ' ' if not use_lineno else ''
+        fnc = f' %(funcName)s(){sep}' if use_func else ' '
+        sep = ' ' if not use_func else ''
+        lno = f'{sep}[%(lineno)d] ' if use_lineno else ''
+        fmt_trail = f' %(name)-{name_width}s{fnc}{lno}%(scr)s%(message)s%(ecr)s'
+        self._plain_format = f'{tfmt}{self.FMT_LEVEL}{fmt_trail}'
+        self._color_formats = {
+            lvl: f'{tfmt}{clr}{self.FMT_LEVEL}{self.RESET}{fmt_trail}'
+            for lvl, clr in self.LOG_COLORS.items()
+        }
+        self._formatter_args = ['%H:%M:%S'] if use_time else []
+
+    def format(self, record):
+        log_fmt = self._color_formats[record.levelno] if self._use_ansi \
+                  else self._plain_format
+        scr, ecr = ('', '')
+        if self._use_ansi:
+            logname = record.name
+            while logname:
+                if logname in self._logger_colors:
+                    scr, ecr = self._logger_colors[logname]
+                    break
+                if '.' not in logname:
+                    break
+                logname = logname.rsplit('.', 1)[0]
+        setattr(record, 'scr', scr)
+        setattr(record, 'ecr', ecr)
+        formatter = logging.Formatter(log_fmt, *self._formatter_args)
+        return formatter.format(record)
+
+    def add_logger_colors(self, logname: str, color: Union[int, str]) -> None:
+        """Assign a color to the message of a specific logger."""
+        if not self._use_ansi:
+            return
+        if isinstance(color, int):
+            if self._use_xansi:
+                code = self.XCOLORS[color % len(self.XCOLORS)]
+                start_color = self.make_fg_color(code, ext=True)
+            else:
+                code = list(self.COLORS.values())[color % len(self.COLORS)]
+                start_color = self.make_fg_color(code)
+        elif isinstance(color, str):
+            scolor = self.COLORS.get(color.upper(), '')
+            if not scolor:
+                return
+            start_color = self.make_fg_color(scolor)
+        else:
+            raise TypeError(f'Unknown logger color specifier: {color}')
+        end_color = self.RESET
+        self._logger_colors[logname] = (start_color, end_color)
+
+    @classmethod
+    def override_xcolors(cls, codes: Sequence[int]) -> None:
+        """Override default extended color palette.
+
+           :param codes: ANSI color codes
+        """
+        xcolors = list(codes)
+        if any(c for c in xcolors
+               if not (isinstance(c, int) and 0 <= c <= 255)):
+            raise ValueError('Invalid color code(s)')
+        cls.XCOLORS = xcolors
+
+
+class RemoteLogHandler(DatagramRequestHandler):
+    """Handle a remote log UDP request."""
+
+    HEADER_FMT = '!L'
+    """UDP prefix that specifies the payload length."""
+
+    HEADER_SIZE = scalc(HEADER_FMT)
+    """The length in bytes of the header."""
+
+    def handle(self):
+        buffer = bytearray()
+        while True:
+            data = self.rfile.read(4)
+            if not data:
+                break
+            buffer.extend(data)
+            if len(buffer) < self.HEADER_SIZE:
+                continue
+            header, buffer = (buffer[:self.HEADER_SIZE],
+                              buffer[self.HEADER_SIZE:])
+            record_len, = sunpack(self.HEADER_FMT, header)
+            while len(buffer) < record_len:
+                data = self.rfile.read(4096)
+                if not data:
+                    break
+                buffer.extend(data)
+            obj_data = buffer[:record_len]
+            obj = ploads(obj_data)
+            record = logging.makeLogRecord(obj)
+            logname = f'pyot.{record.name}'
+            self.server.do_log(logname, record)
+
+
+class RemoteLogServer(ThreadingUDPServer):
+    """ThreadingUDPServer extension with logger cache manager."""
+
+    def __init__(self, *args, **kwargs):
+        super().__init__(*args, **kwargs)
+        self._cache: dict[str, logging.Logger] = {}
+
+    def do_log(self, logname: str, record: logging.LogRecord):
+        """Do actual log.
+
+           This function enables log level local filtering and caching.
+
+           :param logname: name of the logger
+           :param record: the log record
+        """
+        if logname not in self._cache:
+            logger = logging.getLogger(logname)
+            self._cache[logname] = logger
+        lgr = self._cache[logname]
+        lgr.handle(record)
+
+
+class RemoteLogService:
+    """Simple UDP receiver for handling remote log record."""
+
+    allow_reuse_address = True
+    daemon_threads = True
+
+    def __init__(self,  host='127.0.0.1', port=0):
+        RemoteLogServer.allow_reuse_address = True
+        RemoteLogServer.daemon_threads = True
+        self._port = port or DEFAULT_UDP_LOGGING_PORT
+        self._server = RemoteLogServer((host, self._port), RemoteLogHandler)
+        self._thread = Thread(target=self._serve, daemon=True)
+
+    @property
+    def port(self) -> int:
+        """Return the selected UDP port."""
+        return self._port
+
+    def start(self):
+        """Start the logging service thread."""
+        self._thread.start()
+
+    def stop(self):
+        """Stop the logging service thread."""
+        self._server.shutdown()
+
+    def _serve(self):
+        with self._server:
+            self._server.serve_forever()
+
+
+def configure_loggers(level: int, *lognames: list[Union[str, int, Color]],
+                      **kwargs) -> list[logging.Logger]:
+    """Configure loggers.
+
+       :param level: level (stepping: 1)
+       :param lognames: one or more loggers to configure, or log modifiers
+       :param kwargs: optional features
+       :return: configured loggers or level change
+    """
+    loglevel = logging.ERROR - (10 * (level or 0))
+    loglevel = min(logging.ERROR, loglevel)
+    loglevels = {}
+    for lvl in _LEVELS:
+        lnames = kwargs.pop(lvl.lower(), None)
+        if lnames:
+            if isinstance(lnames, str):
+                lnames = [lnames]
+            loglevels[lvl] = tuple(lnames)
+    quiet = kwargs.pop('quiet', False)
+    filelog = kwargs.pop('filelog', None)
+    udplog = kwargs.pop('udplog', None)
+    formatter = ColorLogFormatter(**kwargs)
+    if udplog is not None:
+        udpport = udplog or DEFAULT_UDP_LOGGING_PORT
+        assert isinstance(udpport, int)
+        # use IP value rather than localhost host to avoid repetitive name
+        # resolution
+        shandler = DatagramHandler('127.0.0.1', udpport)
+    else:
+        shandler = logging.StreamHandler(stderr)
+    if filelog:
+        logfh = FileHandler(filelog, 'w')
+        logfh.setFormatter(formatter)
+    else:
+        logfh = None
+    shandler.setFormatter(formatter)
+    if quiet:
+        logh = MemoryHandler(100000, target=shandler, flushOnClose=False)
+        shandler.setLevel(loglevel)
+    else:
+        logh = shandler
+    loggers: list[logging.Logger] = []
+    logdefs: list[tuple[list[str], logging.Logger]] = []
+    color = None
+    for logdef in lognames:
+        if isinstance(logdef, int):
+            loglevel += -10 * logdef
+            continue
+        if isinstance(logdef, Color):
+            color = logdef.color
+            continue
+        if color:
+            formatter.add_logger_colors(logdef, color)
+        log = logging.getLogger(logdef)
+        log.setLevel(max(logging.DEBUG, loglevel))
+        loggers.append(log)
+        logdefs.append((logdef.split('.'), log))
+    for lvl, lnames in loglevels.items():
+        for lname in lnames:
+            log = logging.getLogger(lname)
+        log.setLevel(_LEVELS[lvl])
+    logdefs.sort(key=lambda p: len(p[0]))
+    # ensure there is only one handler per logger subtree
+    for _, log in logdefs:
+        if not log.hasHandlers():
+            log.addHandler(logh)
+            if logfh:
+                log.addHandler(logfh)
+    return loggers
+
+
+def flush_memory_loggers(loggers: Sequence[Union[logging.Logger, str]],
+                         level: Optional[int] = None) -> None:
+    """Discard all buffered records of any MemoryHandler logger handlers.
+
+       :param loggers: the loggers to consider, or the root logger if none is
+                       specified.
+       :param level: if not None, flush all records whose level is higher or
+                     equal to the specified level.
+    """
+    if not loggers:
+        loggers = [logging.getLogger()]
+    for log in loggers:
+        if isinstance(log, str):
+            log = logging.getLogger(log)
+        for hdlr in log.handlers:
+            if not isinstance(hdlr, MemoryHandler):
+                continue
+            if level is None:
+                super(MemoryHandler, hdlr).flush()
+                continue
+            with hdlr.lock:
+                if hdlr.target:
+                    for record in hdlr.buffer:
+                        if record.levelno >= level:
+                            hdlr.target.handle(record)
+                    hdlr.buffer.clear()
diff --git a/python/qemu/ot/util/mbb.py b/python/qemu/ot/util/mbb.py
new file mode 100644
index 0000000000000..995e82baf6847
--- /dev/null
+++ b/python/qemu/ot/util/mbb.py
@@ -0,0 +1,15 @@
+# Copyright (c) 2024-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""MultiBit Boolean values
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+MB4_TRUE = 0x6
+MB4_FALSE = 0x9
+MB4_MASK = 0xf
+
+MB8_TRUE = 0x96
+MB8_FALSE = 0x69
+MB8_MASK = 0xff
diff --git a/python/qemu/ot/util/misc.py b/python/qemu/ot/util/misc.py
new file mode 100644
index 0000000000000..46a821f3a5cc8
--- /dev/null
+++ b/python/qemu/ot/util/misc.py
@@ -0,0 +1,292 @@
+# Copyright (c) 2024-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Miscellaneous helpers.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from collections.abc import Callable
+from io import BytesIO
+from os.path import abspath, dirname, exists, isdir, isfile, join as joinpath
+from subprocess import DEVNULL, SubprocessError, check_output
+from sys import stdout
+from textwrap import dedent, indent
+from typing import Any, Iterable, Optional, TextIO, Union
+import re
+
+
+_TRUE_BOOLEANS = ['on', 'high', 'true', 'enable', 'enabled', 'yes', '1']
+"""String values evaluated as true boolean values"""
+
+_FALSE_BOOLEANS = ['off', 'low', 'false', 'disable', 'disabled', 'no', '0']
+"""String values evaluated as false boolean values"""
+
+
+class classproperty(property):
+    """Getter property decorator for a class"""
+
+    # pylint: disable=invalid-name
+    def __get__(self, obj: Any, objtype=None):
+        return super().__get__(objtype)
+
+
+class HexInt(int):
+    """Simple wrapper to always represent an integer in hexadecimal format."""
+
+    def __repr__(self) -> str:
+        return f'0x{self:x}'
+
+    @staticmethod
+    def parse(val: Optional[Union[str, int]], base: Optional[int] = None,
+              accept_int: bool = False) \
+            -> Optional['HexInt']:
+        """Simple helper to support hexadecimal integer in argument parser."""
+        if val is None:
+            return None
+        if accept_int and isinstance(val, int):
+            return HexInt(val)
+        if base is not None:
+            return HexInt(int(val, base))
+        return HexInt(int(val, val.startswith('0x') and 16 or 10))
+
+    @staticmethod
+    def xparse(value: Union[None, int, str]) -> Optional['HexInt']:
+        """Parse a value and convert it into an integer value if possible.
+
+        Input value may be:
+        - None
+        - a string with an integer coded as a decimal value
+        - a string with an integer coded as a hexadecimal value
+        - a integral value
+        - a integral value with a unit specifier (kilo or mega)
+
+        :param value: input value to convert to an integer
+        :return: the value as an integer
+        :raise ValueError: if the input value cannot be converted into an int
+        """
+        if value is None:
+            return None
+        if isinstance(value, int):
+            return HexInt(value)
+        imo = re.match(r'^\s*(\d+)\s*(?:([KMkm]i?)?B?)?\s*$', value)
+        if imo:
+            mult = {'K': (1000),
+                    'KI': (1 << 10),
+                    'M': (1000 * 1000),
+                    'MI': (1 << 20)}
+            value = int(imo.group(1))
+            if imo.group(2):
+                value *= mult[imo.group(2).upper()]
+            return value
+        return HexInt(int(value.strip(), value.startswith('0x') and 16 or 10))
+
+
+class EasyDict(dict):
+    """Dictionary whose members can be accessed as instance members
+    """
+
+    def __init__(self, dictionary=None, **kwargs):
+        if dictionary is not None:
+            self.update(dictionary)
+        self.update(kwargs)
+
+    def __getattr__(self, name):
+        try:
+            return self.__getitem__(name)
+        except KeyError as exc:
+            raise AttributeError(f"'{self.__class__.__name__}' object has no "
+                                 f"attribute '{name}'") from exc
+
+    def __setattr__(self, name, value):
+        self.__setitem__(name, value)
+
+    def __dir__(self) -> Iterable[Any]:
+        items = set(super().__dir__())
+        items.update(set(self))
+        yield from sorted(items)
+
+
+def flatten(lst: list) -> list:
+    """Flatten a list."""
+    return [item for sublist in lst for item in sublist]
+
+
+def group(lst, count):
+    """Group a list into consecutive count-tuples. Incomplete tuples are
+    discarded.
+
+    `group([0,3,4,10,2,3], 2) => [(0,3), (4,10), (2,3)]`
+
+    From: http://aspn.activestate.com/ASPN/Cookbook/Python/Recipe/303060
+    """
+    return list(zip(*[lst[i::count] for i in range(count)]))
+
+
+def dump_buffer(buffer: Union[bytes, bytearray, BytesIO], addr: int = 0,
+                file: Optional[TextIO] = None) -> None:
+    """Dump a binary buffer, same format as hexdump -C."""
+    if isinstance(buffer, BytesIO):
+        buffer = buffer.getbuffer()
+    size = len(buffer)
+    if not file:
+        file = stdout
+    for pos in range(0, size, 16):
+        chunks = buffer[pos:pos+8], buffer[pos+8:pos+16]
+        buf = '  '.join(' '.join(f'{x:02x}' for x in c) for c in chunks)
+        if len(buf) < 48:
+            buf = f'{buf}{" " * (48 - len(buf))}'
+        chunk = buffer[pos:pos+16]
+        text = ''.join(chr(c) if 0x20 <= c < 0x7f else '.' for c in chunk)
+        if len(text) < 16:
+            text = f'{text}{" " * (16-len(text))}'
+        print(f'{addr+pos:08x}  {buf}  |{text}|', file=file)
+
+
+def round_up(value: int, rnd: int) -> int:
+    """Round up a integer value."""
+    return (value + rnd - 1) & -rnd
+
+
+def camel_to_snake_case(camel: str) -> str:
+    """Convert CamelString string into snake_case lower string."""
+    pattern = r'(?<=[a-z])(?=[A-Z])|(?<=[A-Z])(?=[A-Z][a-z])'
+    return re.sub(pattern, '_', camel).lower()
+
+
+def camel_to_snake_uppercase(name: str) -> str:
+    """Extended version of camel_to_snake_case to convert device/parameter
+       names.
+    """
+    pattern = r'(?<=[\d])(?=[A-Z]{2,})'
+    return re.sub(pattern, '_', camel_to_snake_case(name).upper())
+
+
+def to_bool(value, permissive=True, prohibit_int=False):
+    """Parse a string and convert it into a boolean value if possible.
+
+       Input value may be:
+       - a string with an integer value, if `prohibit_int` is not set
+       - a boolean value
+       - a string with a common boolean definition
+
+       :param value: the value to parse and convert
+       :type value: str or int or bool
+       :param bool permissive: default to the False value if parsing fails
+       :param bool prohibit_int: prohibit an integral type as the input value
+       :rtype: bool
+       :raise ValueError: if the input value cannot be converted into an bool
+    """
+    if value is None:
+        return False
+    if isinstance(value, bool):
+        return value
+    if isinstance(value, int):
+        if not prohibit_int:
+            if permissive:
+                return bool(value)
+            if value in (0, 1):
+                return bool(value)
+        raise ValueError(f"Invalid boolean value: '{value}'")
+    if value.lower() in _TRUE_BOOLEANS:
+        return True
+    if permissive or (value.lower() in _FALSE_BOOLEANS):
+        return False
+    raise ValueError(f"Invalid boolean value: '{value}")
+
+
+def alphanum_key(text: str) -> list[Union[int, str]]:
+    """Alphanumerical sorting key.
+
+       :param text: the text to generate a sorting key from
+       :return: a list of alternating str and integer values
+    """
+    return [int(t) if t.isdigit() else t for t in re.split(r'(\d+)', text)]
+
+
+def redent(text: str, spc: int = 0, strip_end: bool = False) -> str:
+    """Utility function to re-indent code string.
+
+        :param text: the text to re-indent
+        :param spc: the number of leading empty space chars to prefix lines
+        :param strip_end: whether to strip trailing whitespace and newline
+    """
+    text = dedent(text.lstrip('\n'))
+    text = indent(text, ' ' * spc)
+    if strip_end:
+        text = text.rstrip(' ').rstrip('\n')
+    return text
+
+
+def retrieve_git_version(path: str, max_tag_dist: int = 100) \
+        -> Optional[str]:
+    """Return a Git identifier whenever possible.
+
+        :param path: the configuration file or directory to track the repository
+                     version identifier. Note that the returned Git identifier
+                     is not the commit version of this file / directory, but the
+                     one of the repo top-level directory.
+        :param max_tag_dist: maximum distance (in commit number) to the closest
+                             tag. If distance is greater, only emit the commit
+                             identifier
+        :return: Git version of the top-level directory
+    """
+    cfgdir: Optional[str] = None
+    path = abspath(path)
+    if isfile(path):
+        cfgdir = dirname(path)
+    elif isdir(path):
+        cfgdir = path
+    else:
+        return None
+    while cfgdir and isdir(cfgdir):
+        gitdir = joinpath(cfgdir, '.git')
+        if exists(gitdir):  # either a dir or a file for worktree
+            break
+        pardir = dirname(cfgdir)
+        if pardir == cfgdir:
+            # reach top of tree hierarchy without any detected .git directory
+            return None
+        cfgdir = pardir
+    else:
+        return None
+    assert cfgdir is not None
+    try:
+        descstr = check_output(['git', 'describe', '--long', '--dirty'],
+                               text=True, cwd=cfgdir, stderr=DEVNULL).strip()
+        gmo = re.match(r'^(?P<tag>.*)-(?P<dist>\d+)-g(?P<commit>[0-9a-f]+)'
+                       r'(?:-(?P<dirty>dirty))?$', descstr)
+        if not gmo:
+            raise ValueError('Unknown Git describe format')
+        distance = int(gmo.group('dist'))
+        dirty = gmo.group('dirty')
+        if distance == 0:
+            return '-'.join(filter(None, (gmo.group('tag'), dirty)))
+        if distance <= max_tag_dist:
+            return descstr
+        return '-'.join(filter(None, (gmo.group('commit'), dirty)))
+    except (OSError, SubprocessError, ValueError):
+        pass
+    try:
+        change = check_output(['git', 'status', '--porcelain'],
+                              text=True, cwd=cfgdir, stderr=DEVNULL).strip()
+        descstr = check_output(['git', 'rev-parse', '--short', 'HEAD'],
+                               text=True, cwd=cfgdir, stderr=DEVNULL).strip()
+        if len(change) > 1:
+            descstr = f'{descstr}-dirty'
+        return descstr
+    except (OSError, SubprocessError):
+        pass
+    return None
+
+
+def split_map_join(sep: str, seq: str, func: Callable[[str], str]) -> str:
+    """Split then re-join a string, applying a conversion function on
+       each elememnt.
+
+        :param sep: the separator character for splitting and joining
+        :param seq: the string to process
+        :param func: the conversion function that accepts a string as its
+                    unique argument and return the converted string
+    """
+    return sep.join(func(val) for val in seq.split(sep))
diff --git a/python/qemu/ot/util/present.py b/python/qemu/ot/util/present.py
new file mode 100644
index 0000000000000..4810e5fff724e
--- /dev/null
+++ b/python/qemu/ot/util/present.py
@@ -0,0 +1,185 @@
+# Python PRESENT implementation
+#
+# Copyright (c) 2008
+#     Christophe Oosterlynck <christophe.oosterlynck_AT_gmail.com> $
+#     NXP ( Philippe Teuwen <philippe.teuwen_AT_nxp.com> )
+# Updated 2024 Emmanuel Blot <eblot@rivosinc.com> for QEMU/OT
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+""" PRESENT block cipher implementation.
+
+>> from pypresent import Present
+
+Encrypting with a 128-bit key:
+------------------------------
+>>> key = 0x0123456789abcdef0123456789abcdef
+>>> plain = 0x0123456789abcdef
+>>> cipher = Present(key)
+>>> encrypted = cipher.encrypt(plain)
+>>> hex(encrypted)
+'0xe9d28685e671dd6'
+>>> decrypted = cipher.decrypt(encrypted)
+>>> hex(decrypted)
+'0x123456789abcdef'
+"""
+
+
+def _tinvert(tpl):
+    return tuple(tpl.index(x) for x in range(len(tpl)))
+
+
+class Present:
+    """PRESENT cipher object
+
+       :param key: the 128-bit key as an integer
+       :param rounds: the number of rounds as an integer
+    """
+
+    BLOCK_BIT_SIZE = 64
+
+    SBOX = (12, 5, 6, 11, 9, 0, 10, 13, 3, 14, 15, 8, 4, 7, 1, 2)
+
+    SBOX_INV = _tinvert(SBOX)
+
+    PBOX = (0, 16, 32, 48, 1, 17, 33, 49, 2, 18, 34, 50, 3, 19, 35, 51, 4, 20,
+            36, 52, 5, 21, 37, 53, 6, 22, 38, 54, 7, 23, 39, 55, 8, 24, 40, 56,
+            9, 25, 41, 57, 10, 26, 42, 58, 11, 27, 43, 59, 12, 28, 44, 60, 13,
+            29, 45, 61, 14, 30, 46, 62, 15, 31, 47, 63)
+
+    PBOX_INV = _tinvert(PBOX)
+
+    def __init__(self, key, rounds=32):
+        self._roundkeys = self._generate_roundkeys(key, rounds)
+
+    @property
+    def rounds(self) -> int:
+        """Return the number of rounds
+
+           :return: the number of rounds
+        """
+        return len(self._roundkeys)
+
+    def encrypt(self, block: int) -> int:
+        """Encrypt 1 block (8 bytes)
+
+           :param block: plaintext block
+           :return: ciphertext block
+        """
+        state = block
+        for i in range(self.rounds - 1):
+            state = self._add_round_key(state, self._roundkeys[i])
+            state = self._sbox_layer(state)
+            state = self._p_layer(state)
+        cipher = self._add_round_key(state, self._roundkeys[-1])
+        return cipher
+
+    def decrypt(self, block: int) -> int:
+        """Decrypt 1 block (8 bytes)
+
+           :param block: ciphertext block
+           :return: plaintext block
+        """
+        state = block
+        for i in range(self.rounds - 1):
+            state = self._add_round_key(state, self._roundkeys[-i - 1])
+            state = self._p_layer_dec(state)
+            state = self._sbox_layer_dec(state)
+        decipher = self._add_round_key(state, self._roundkeys[0])
+        return decipher
+
+    @classmethod
+    def _generate_roundkeys(cls, key: int, rounds: int) -> list[int]:
+        """Generate the roundkeys for a 128-bit key
+
+           :param key: the key as a 128-bit integer
+           :param rounds: the number of rounds
+           :return: list of 64-bit roundkeys
+        """
+        roundkeys = []
+        for rnd in range(rounds):  # (K1 ... K32)
+            # rawkey: used in comments to show what happens at bitlevel
+            roundkeys.append(key >> 64)
+            # 1. Shift
+            key = ((key & (2**67 - 1)) << 61) + (key >> 67)
+            # 2. SBox
+            key = (cls.SBOX[key >> 124] << 124) + \
+                  (cls.SBOX[(key >> 120) & 0xF] << 120) + (key & (2**120 - 1))
+            # 3. Salt
+            # rawKey[62:67] ^ i
+            key ^= (rnd + 1) << 62
+        return roundkeys
+
+    @classmethod
+    def _add_round_key(cls, state: int, roundkey: int) -> int:
+        return state ^ roundkey
+
+    @classmethod
+    def _sbox_layer(cls, state: int) -> int:
+        """SBox function for encryption
+
+           :param state: 64-bit integer
+           :return: 64-bit integer
+        """
+
+        output = 0
+        for idx in range(16):
+            output += cls.SBOX[(state >> (idx * 4)) & 0xF] << (idx * 4)
+        return output
+
+    @classmethod
+    def _sbox_layer_dec(cls, state: int) -> int:
+        """Inverse SBox function for decryption
+
+           :param state: 64-bit integer
+           :return: 64-bit integer
+        """
+        output = 0
+        for idx in range(16):
+            output += cls.SBOX_INV[(state >> (idx * 4)) & 0xF] << (idx * 4)
+        return output
+
+    @classmethod
+    def _p_layer(cls, state: int) -> int:
+        """Permutation layer for encryption
+
+           :param state: 64-bit integer
+           :return: 64-bit integer
+        """
+        output = 0
+        for i in range(64):
+            output += ((state >> i) & 0x01) << cls.PBOX[i]
+        return output
+
+    @classmethod
+    def _p_layer_dec(cls, state: int) -> int:
+        """Permutation layer for decryption
+
+           :param state: 64-bit integer
+           :return: 64-bit integer
+        """
+        output = 0
+        for i in range(64):
+            output += ((state >> i) & 0x01) << cls.PBOX_INV[i]
+        return output
+
+
+if __name__ == '__main__':
+    from doctest import testmod
+    testmod()
diff --git a/python/qemu/ot/util/prince.py b/python/qemu/ot/util/prince.py
new file mode 100644
index 0000000000000..3ceef81dfe35d
--- /dev/null
+++ b/python/qemu/ot/util/prince.py
@@ -0,0 +1,155 @@
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""PRINCE cipher implementation.
+"""
+
+from functools import lru_cache
+
+# pylint: disable=missing-docstring
+
+
+class PrinceCipher:
+
+    SBOX4 = [
+        0xb, 0xf, 0x3, 0x2, 0xa, 0xc, 0x9, 0x1,
+        0x6, 0x7, 0x8, 0x0, 0xe, 0x5, 0xd, 0x4
+    ]
+
+    SBOX4_INV = [
+        0xb, 0x7, 0x3, 0x2, 0xf, 0xd, 0x8, 0x9,
+        0xa, 0x6, 0x4, 0x0, 0x5, 0xe, 0xc, 0x1
+    ]
+
+    SHIFT_ROWS64 = [
+        0x4, 0x9, 0xe, 0x3, 0x8, 0xd, 0x2, 0x7,
+        0xc, 0x1, 0x6, 0xb, 0x0, 0x5, 0xa, 0xf
+    ]
+
+    SHIFT_ROWS64_INV = [
+        0xc, 0x9, 0x6, 0x3, 0x0, 0xd, 0xa, 0x7,
+        0x4, 0x1, 0xe, 0xb, 0x8, 0x5, 0x2, 0xf
+    ]
+    ROUND_CONSTS = [
+        0x0000000000000000, 0x13198a2e03707344,
+        0xa4093822299f31d0, 0x082efa98ec4e6c89,
+        0x452821e638d01377, 0xbe5466cf34e90c6c,
+        0x7ef84f78fd955cb1, 0x85840851f1ac43aa,
+        0xc882d32f25323c54, 0x64a51195e0e3610d,
+        0xd3b5a399ca0c2399, 0xc0ac29b7c97c50dd
+    ]
+
+    @classmethod
+    def sbox(cls, in_: int, width: int, sbox: list[int]) -> int:
+        full_mask = 0 if (width >= 64) else (1 << width) - 1
+        width &= ~3
+        sbox_mask = 0 if (width >= 64) else (1 << width) - 1
+
+        ret = in_ & (full_mask & ~sbox_mask)
+
+        for ix in range(0, width, 4):
+            nibble = (in_ >> ix) & 0xf
+            ret |= sbox[nibble] << ix
+
+        return ret
+
+    @classmethod
+    @lru_cache(maxsize=65536)
+    def nibble_red16(cls, data: int) -> int:
+        nib0 = (data >> 0) & 0xf
+        nib1 = (data >> 4) & 0xf
+        nib2 = (data >> 8) & 0xf
+        nib3 = (data >> 12) & 0xf
+        return nib0 ^ nib1 ^ nib2 ^ nib3
+
+    @staticmethod
+    def mult_prim_const() -> list[tuple[int, tuple[int, int]]]:
+        bconsts = []
+        shift_rows_consts = [
+            0x7bde, 0xbde7, 0xde7b, 0xe7bd
+        ]
+        for blk_idx in range(4):
+            consts = []
+            start_sr_idx = 0 if blk_idx in (0, 3) else 1
+            blk_const = blk_idx * 16
+            for nibble_idx in range(4):
+                sr_idx = (start_sr_idx + 3 - nibble_idx) & 0x3
+                sr_const = shift_rows_consts[sr_idx]
+                shift_const = blk_const + nibble_idx * 4
+                consts.append((shift_const, sr_const))
+            bconsts.append((blk_const, consts))
+        return bconsts
+
+    MULT_PRIM_CONST = mult_prim_const()
+
+    @classmethod
+    def mult_prime(cls, data: int) -> int:
+        ret = 0
+        for blk_const, consts in cls.MULT_PRIM_CONST:
+            data_hw = data >> blk_const
+            for sh, sr in consts:
+                ret |= cls.nibble_red16(data_hw & sr) << sh
+        return ret
+
+    @classmethod
+    def shiftrows(cls, data: int, invert: bool) -> int:
+        shifts = cls.SHIFT_ROWS64_INV if invert else cls.SHIFT_ROWS64
+        ret = 0
+        for nibble_idx in range(64//4):
+            src_nibble_idx = shifts[nibble_idx]
+            src_nibble = (data >> (4 * src_nibble_idx)) & 0xf
+            ret |= src_nibble << (4 * nibble_idx)
+        return ret
+
+    @classmethod
+    def fwd_round(cls, rc: int, key: int, data: int) -> int:
+        data = cls.sbox(data, 64, cls.SBOX4)
+        data = cls.mult_prime(data)
+        data = cls.shiftrows(data, False)
+        data ^= rc
+        data ^= key
+        return data
+
+    @classmethod
+    def inv_round(cls, rc: int, key: int, data: int) -> int:
+        data ^= key
+        data ^= rc
+        data = cls.shiftrows(data, True)
+        data = cls.mult_prime(data)
+        data = cls.sbox(data, 64, cls.SBOX4_INV)
+        return data
+
+    # Run the PRINCE cipher.
+    # This uses the new keyschedule proposed by Dinur in "Cryptanalytic
+    # Time-Memory-Data Tradeoffs for FX-Constructions with Applications to
+    # PRINCE and PRIDE".
+    @classmethod
+    def run(cls, data: int, khi: int, klo: int, num_rounds_half: int) -> int:
+        khi_rot1 = ((khi & 1) << 63) | (khi >> 1)
+        khi_prime = khi_rot1 ^ (khi >> 63)
+
+        data ^= khi
+        data ^= klo
+        data ^= cls.ROUND_CONSTS[0]
+
+        for hri in range(num_rounds_half):
+            round_idx = 1 + hri
+            rc = cls.ROUND_CONSTS[round_idx]
+            rk = khi if (round_idx & 1) else klo
+            data = cls.fwd_round(rc, rk, data)
+
+        data = cls.sbox(data, 64, cls.SBOX4)
+        data = cls.mult_prime(data)
+        data = cls.sbox(data, 64, cls.SBOX4_INV)
+
+        for hri in range(num_rounds_half):
+            round_idx = 11 - num_rounds_half + hri
+            rc = cls.ROUND_CONSTS[round_idx]
+            rk = klo if (round_idx & 1) else khi
+            data = cls.inv_round(rc, rk, data)
+
+        data ^= cls.ROUND_CONSTS[11]
+        data ^= klo
+        data ^= khi_prime
+
+        return data
diff --git a/python/qemu/ot/util/recfmt.py b/python/qemu/ot/util/recfmt.py
new file mode 100644
index 0000000000000..8e3fc980958be
--- /dev/null
+++ b/python/qemu/ot/util/recfmt.py
@@ -0,0 +1,850 @@
+# Copyright (c) 2019 Emmanuel Blot <emmanuel.blot@free.fr>
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: MIT License
+
+"""Text-record tools
+"""
+
+from array import array as Array
+from binascii import hexlify, unhexlify
+from io import BytesIO, StringIO
+from os import stat, linesep, SEEK_SET
+from re import compile as re_compile
+from struct import pack as spack
+from typing import BinaryIO, Optional, TextIO
+
+import sys
+
+
+# pylint: disable-msg=broad-except,invalid-name
+
+
+class RecordError(ValueError):
+    """Error in text record content"""
+
+
+class SRecError(RecordError):
+    """Error in SREC content"""
+
+
+class IHexError(RecordError):
+    """Error in iHex content"""
+
+
+class TItxtError(RecordError):
+    """Error in TI-txt content"""
+
+
+class VMemError(RecordError):
+    """Error in VMem content"""
+
+
+class RecordSegment:
+    """Data container for a consecutive sequence of bytes.
+
+       ..note:: RecordSegment methods are extensively called, so the code has
+                been optimized to decrease Python call overhead.
+    """
+
+    def __init__(self, baseaddr=0):
+        self._baseaddr = baseaddr
+        self._size = 0
+        self._buffer = BytesIO()
+
+    @property
+    def size(self):
+        """Return the size in bytes of a segment."""
+        return self._size
+
+    @property
+    def baseaddr(self):
+        """Return the address of the first byte of the segment."""
+        return self._baseaddr
+
+    @property
+    def absaddr(self):
+        """Return the absolute address of this segment."""
+        return self._baseaddr + self._size
+
+    @property
+    def reladdr(self):
+        """Return the relative address of this segment."""
+        return self._size
+
+    @property
+    def data(self) -> bytes:
+        """Return the segment payload."""
+        return self._buffer.getvalue()
+
+    def __str__(self):
+        return f'Data segment @ {self._baseaddr:08x} {self._size} bytes'
+
+    def write(self, data: bytes, offset=None):
+        """Write new data to the segment, at the specified offset."""
+        self.write_with_size(data, len(data), offset)
+
+    def write_with_size(self, data, size, offset):
+        """Write new data to the segment, at the specified offset, with a
+           specific size."""
+        if offset is not None and (offset - self._baseaddr) != self._size:
+            offset -= self._baseaddr
+            self._buffer.seek(offset, SEEK_SET)
+            size += offset - self._size
+        self._buffer.write(data)
+        self._size += size
+
+
+class RecordParser:
+    """Abstract record file parser.
+
+      :param src: file object for sourcing stream
+      :param offset: byte offset to substract to encoded address
+      :param min_addr: lowest address to consider
+      :param max_addr: highest address to consider
+      :param segment_gap: distance between non-consecutive address to trigger
+                          a new segment
+      :param verbose: emit extra information while processing the stream
+      :param verify: verify the checksum with calculated one
+    """
+
+    (INFO, DATA, EXECUTE, EOF) = range(1, 5)
+
+    def __init__(self, src: TextIO, offset: int = 0, min_addr: int = 0x0,
+                 max_addr: int = 0xffffffff, segment_gap: int = 16,
+                 verbose: bool = False, verify: bool = True):
+        if segment_gap < 1:
+            raise ValueError("Invalid segment gap")
+        self._src: TextIO = src
+        self._offset: int = offset
+        self._min_addr: int = min_addr
+        self._max_addr: int = max_addr
+        self._verbose: bool = verbose
+        self._exec_addr: Optional[int] = None
+        self._segments: list[RecordSegment] = []
+        self._info: Optional[RecordSegment] = None
+        self._gap: int = segment_gap
+        self._seg: Optional[RecordSegment] = None
+        self._bytes: int = 0
+        self._verify: bool = verify
+
+    def parse(self):
+        """Parse the stream"""
+        for (record, address, value) in self:
+            if record == RecordParser.DATA:
+                addr = address - self._offset
+                if self._seg and (abs(addr - self._seg.absaddr) >= self._gap):
+                    self._store_segment()
+                if not self._seg:
+                    self._seg = RecordSegment(addr)
+                self._seg.write(value, addr)
+            elif record == RecordParser.EXECUTE:
+                self._exec_addr = address
+            elif record == RecordParser.INFO:
+                if not self._info:
+                    self._info = RecordSegment(address)
+                self._info.write(value, address)
+            elif record == RecordParser.EOF:
+                pass
+            else:
+                raise RuntimeError("Internal error")
+        self._store_segment()
+
+    def __iter__(self):
+        return self._get_next_chunk()
+
+    def _get_next_chunk(self):
+        raise NotImplementedError()
+
+    def get_data_segments(self) -> list[RecordSegment]:
+        """Return all segments."""
+        return self._segments
+
+    def get_info(self) -> bytes:
+        """Return the info segment data, if there is such a segment."""
+        return bytes(self._info.data) if self._info else bytes()
+
+    def getexec(self) -> Optional[int]:
+        """Return the execution address (entry point) if any."""
+        return self._exec_addr
+
+    @classmethod
+    def is_valid_syntax(cls, file):
+        """Tell whether the file contains a valid syntax.
+
+           :param file: either a filepath or a file-like object
+           :return: True if the file content looks valid
+        """
+        cre = getattr(cls, 'SYNTAX_CRE', None)
+        if not cre:
+            return False
+        last = False
+        with isinstance(file, str) and open(file, 'rt') or file as hfp:
+            try:
+                for line in hfp:
+                    line = line.strip()
+                    if not line:
+                        last = True
+                        continue
+                    if not cre.match(line) or last:
+                        # there should be no empty line but the last one(s)
+                        return False
+            except Exception:
+                return False
+        return True
+
+    def _verify_address(self, address):
+        if (address < self._min_addr) or (address > self._max_addr):
+            raise RecordError(f"Address out of range [0x{self._min_addr:08x}.."
+                              f"0x{self._max_addr:08x}: 0x{address:08x}")
+        if address < self._offset:
+            raise RecordError(f"Invalid address in file: 0x{address:08x}")
+
+    def _store_segment(self):
+        if self._seg and self._seg.size:
+            self._segments.append(self._seg)
+        self._seg = None
+
+
+class SRecParser(RecordParser):
+    """S-record file parser.
+    """
+
+    SYNTAX_CRE = re_compile('(?i)^S([0-9])((?:[0-9A-F]{2})+)$')
+
+    def _get_next_chunk(self):
+        # test if the file size can be found...
+        try:
+            self._bytes = stat(self._src.name)[6]
+        except Exception:
+            pass
+        bc = 0
+        try:
+            for (lno, line) in enumerate(self._src, start=1):
+                line = line.strip()
+                if self._verbose and self._bytes:
+                    opc = (50 * bc) // self._bytes
+                    bc += len(line)
+                    pc = (50 * bc) // self._bytes
+                    if pc > opc:
+                        info = f"\rAnalysing SREC file [{2*pc:3d}%%] {'.' * pc}"
+                        sys.stdout.write(info)
+                        sys.stdout.flush()
+                try:
+                    # avoid line stripping, SREC files always use DOS format
+                    if len(line) < 5:
+                        continue
+                    if line[0] != 'S':
+                        raise SRecError("Invalid SREC header")
+                    record = int(line[1])
+                    if record == 1:
+                        addrend = 3
+                        address = int(line[4:8], 16)
+                        type_ = RecordParser.DATA
+                    elif record == 2:
+                        addrend = 4
+                        address = int(line[4:10], 16)
+                        type_ = RecordParser.DATA
+                    elif record == 3:
+                        addrend = 5
+                        address = int(line[4:12], 16)
+                        type_ = RecordParser.DATA
+                    elif record == 7:
+                        addrend = 5
+                        address = int(line[4:12], 16)
+                        type_ = RecordParser.EXECUTE
+                    elif record == 8:
+                        addrend = 4
+                        address = int(line[4:10], 16)
+                        type_ = RecordParser.EXECUTE
+                    elif record == 9:
+                        addrend = 3
+                        address = int(line[4:8], 16)
+                        type_ = RecordParser.EXECUTE
+                    elif record == 0:
+                        addrend = 3
+                        address = int(line[4:8], 16)
+                        type_ = RecordParser.INFO
+                    else:
+                        raise SRecError("Unsupported SREC record")
+                    try:
+                        bytes_ = unhexlify(line[2:-2])
+                    except TypeError as exc:
+                        raise SRecError(f"{exc} @ line {lno}") from exc
+                    size = int(line[2:4], 16)
+                    effsize = len(bytes_)
+                    if size != effsize:
+                        raise SRecError(f"Expected {size} bytes, got {effsize} "
+                                        f"@ line {lno}")
+                    if self._verify:
+                        csum = sum(Array('B', bytes_))
+                        csum &= 0xff
+                        csum ^= 0xff
+                        rsum = int(line[-2:], 16)
+                        if rsum != csum:
+                            raise SRecError(f"Invalid checksum: 0x{rsum:02x} / "
+                                            f"0x{csum:02x}")
+                    if self._verify and record:
+                        self._verify_address(address)
+                    yield (type_, address, bytes_[addrend:])
+                except RecordError as exc:
+                    raise exc.__class__(f"{exc} @ line {lno}:'{line}'") from exc
+        finally:
+            if self._verbose:
+                print('')
+
+
+class IHexParser(RecordParser):
+    """Intel Hex record file parser.
+    """
+
+    SYNTAX_CRE = re_compile('(?i)^:[0-9A-F]+$')
+
+    def __init__(self, *args, **kwargs):
+        super().__init__(*args, **kwargs)
+        self._offset_addr = 0
+
+    def _get_next_chunk(self):
+        # test if the file size can be found...
+        try:
+            self._bytes = stat(self._src.name)[6]
+        except Exception:
+            pass
+        bc = 0
+        try:
+            for (lno, line) in enumerate(self._src, start=1):
+                line = line.strip()
+                if self._verbose and self._bytes:
+                    opc = (50 * bc) // self._bytes
+                    bc += len(line)
+                    pc = (50 * bc) // self._bytes
+                    if pc > opc:
+                        info = f"\rAnalysing iHEX file [{2*pc:3d}%%] {'.' * pc}"
+                        sys.stdout.write(info)
+                        sys.stdout.flush()
+                try:
+                    if len(line) < 5:
+                        continue
+                    if line[0] != ':':
+                        raise IHexError("Invalid IHEX header")
+                    size = int(line[1:3], 16)
+                    address = int(line[3:7], 16)
+                    record = int(line[7:9])
+                    if record == 0:
+                        type_ = RecordParser.DATA
+                    elif record == 1:
+                        type_ = RecordParser.EOF
+                        if address != 0:
+                            print(f"Unexpected non-zero address in EOF: "
+                                  f"0x{address:04x}", file=sys.stderr)
+                    elif record == 2:
+                        self._offset_addr &= ~((1 << 20) - 1)
+                        self._offset_addr |= int(line[9:-2], 16) << 4
+                        continue
+                    elif record == 4:
+                        self._offset_addr = int(line[9:-2], 16) << 16
+                        continue
+                    elif record == 3:
+                        type_ = RecordParser.EXECUTE
+                        cs = int(line[9:13], 16)
+                        ip = int(line[13:-2], 16)
+                        address = (cs << 4) + ip
+                    else:
+                        raise IHexError(f"Unsupported IHEX record: {record}")
+                    try:
+                        bytes_ = unhexlify(line[9:-2])
+                    except TypeError as exc:
+                        raise IHexError(f"{exc} @ line {lno}") from exc
+                    effsize = len(bytes_)
+                    if size != effsize:
+                        raise IHexError(f"Expected {size} bytes, got {effsize} "
+                                        f"@ line {lno}")
+                    if self._verify:
+                        csum = sum(Array('B', unhexlify(line[1:-2])))
+                        csum = (-csum) & 0xff
+                        rsum = int(line[-2:], 16)
+                        if rsum != csum:
+                            raise IHexError(f"Invalid checksum: 0x{rsum:02x} / "
+                                            f"0x{csum:02x}")
+                    if type_ == RecordParser.DATA:
+                        address += self._offset_addr
+                    if self._verify and record:
+                        self._verify_address(address)
+                    yield (type_, address, bytes_)
+                except RecordError as exc:
+                    raise exc.__class__(f"{exc} @ line {lno}:'{line}'") from exc
+        finally:
+            if self._verbose:
+                print('')
+
+
+class IHexFastParser(RecordParser):
+    """Intel Hex record file parser.
+
+       Faster implementation than IHexParser, but less readable.
+    """
+
+    # pylint: disable=abstract-method
+
+    HEXCRE = re_compile(r'(?aim)^:((?:[0-9A-F][0-9A-F]){5,})$')
+
+    def __init__(self, *args, **kwargs):
+        super().__init__(*args, **kwargs)
+        self._offset_addr = 0
+
+    @classmethod
+    def is_valid_syntax(cls, file):
+        """Tell whether the file contains a valid HEX syntax.
+
+           :param file: either a filepath or a file-like object
+           :return: True if the file content looks valid
+        """
+        valid = False
+        with isinstance(file, str) and open(file, 'rt') or file as hfp:
+            try:
+                data = hfp.read()
+                # it seems there is no easy way to full match a multiline re
+                # so compare the count of line vs, the count of matching ihex
+                # valid lines as a quick workaround. This could give false
+                # positive or negative, but this approximation is for now
+                # sufficient to fast match a file.
+                ihex_count = len(cls.HEXCRE.findall(data))
+                lf_count = data.count('\n')
+                valid = ihex_count == lf_count
+            except Exception:
+                pass
+        return valid
+
+    def parse(self):
+        for pos, mo in enumerate(self.HEXCRE.finditer(self._src.read()),
+                                 start=1):
+            bvalues = unhexlify(mo.group(0)[1:])
+            size = bvalues[0]
+            rsum = bvalues[-1]
+            data = bvalues[4:-1]
+            if len(data) != size:
+                raise IHexError(f'Invalid line @ {pos} in HEX file')
+            if self._verify:
+                csum = sum(bvalues[:-1])
+                csum = (-csum) & 0xff
+                if rsum != csum:
+                    raise IHexError(f"Invalid checksum: 0x{rsum:02x} /"
+                                    f" 0x{csum:02x}")
+            address = (bvalues[1] << 8) + bvalues[2]
+            record = bvalues[3]
+            if self._verify and record:
+                self._verify_address(address)
+            if record == 0:
+                # RecordParser.DATA
+                address += self._offset_addr
+                addr = address - self._offset
+                if self._seg:
+                    gap = addr - self._seg.absaddr
+                    if gap < 0:
+                        gap = -gap
+                    if gap >= self._gap:
+                        self._store_segment()
+                if not self._seg:
+                    self._seg = RecordSegment(addr)
+                self._seg.write_with_size(data, size, addr)
+            elif record == 1:
+                # RecordParser.EOF
+                if address != 0:
+                    print(f"Unexpected non-zero address @ EOF: "
+                          f"0x:{address:04x}", file=sys.stderr)
+            elif record == 2:
+                if size != 2:
+                    raise IHexError('Invalid segment address')
+                self._offset_addr &= ~((1 << 20) - 1)
+                self._offset_addr |= ((data[0] << 8) + data[1]) << 4
+                continue
+            elif record == 4:
+                if size != 2:
+                    raise IHexError('Invalid linear address')
+                self._offset_addr = ((data[0] << 8) + data[1]) << 16
+                continue
+            elif record == 3:
+                # RecordParser.EXECUTE
+                if size != 4:
+                    raise IHexError('Invalid start address')
+                cs = (data[0] << 8) + data[1]
+                ip = (data[2] << 8) + data[3]
+                address = (cs << 4) + ip
+                self._exec_addr = address
+        self._store_segment()
+
+
+class TItxtParser(RecordParser):
+    """TI txt record file parser.
+    """
+
+    def _get_next_chunk(self):
+        # test if the file size can be found...
+        try:
+            self._bytes = stat(self._src.name)[6]
+        except Exception:
+            pass
+        bc = 0
+        try:
+            for (lno, line) in enumerate(self._src, start=1):
+                line = line.strip()
+                if self._verbose and self._bytes:
+                    opc = (50 * bc) // self._bytes
+                    bc += len(line)
+                    pc = (50 * bc) // self._bytes
+                    if pc > opc:
+                        info = (f"\rAnalysing TItxt file [{2*pc:3d}%%] "
+                                f"{'.' * pc}")
+                        sys.stdout.write(info)
+                        sys.stdout.flush()
+                try:
+                    if line.startswith('@'):
+                        address = int(line[1:], 16)
+                        continue
+                    if line == 'q':
+                        yield (RecordParser.EOF, 0, b'')
+                        break
+                    try:
+                        bytes_ = unhexlify(line)
+                    except TypeError as exc:
+                        raise IHexError(f'{exc} @ line {lno}') from exc
+                    self._verify_address(address)
+                    yield (RecordParser.DATA, address, bytes_)
+                    address += len(bytes_)
+                except RecordError as exc:
+                    raise exc.__class__(f"{exc} @ line {lno}:'{line}'") from exc
+        finally:
+            if self._verbose:
+                print('')
+
+
+class VMemParser(RecordParser):
+    """VMEM record file parser.
+
+       Additional named arguments:
+
+       :param eccbits: count of trailing bits in each data chunk
+       :param byteorder: either 'little' or 'big', default to big
+    """
+
+    def __init__(self, src, *args, **kwargs):
+        if 'eccbits' in kwargs:
+            try:
+                self._eccbits = int(kwargs.pop('eccbits'))
+            except ValueError as exc:
+                raise ValueError('Invalid ecc bit count') from exc
+        else:
+            self._eccbits = 0
+        self._ecc_bytes = (self._eccbits + 7) // 8
+        if 'byteorder' in kwargs:
+            byteorder = kwargs.pop('byteorder')
+            try:
+                self._reverse = {'little': True, 'big': False}[byteorder]
+            except KeyError as exc:
+                raise ValueError('Invalid byte order') from exc
+        else:
+            self._reverse = False
+        super().__init__(src, *args, **kwargs)
+
+    def _get_next_chunk(self):
+        cmt_re = re_compile(r'(#|//).*$')
+        address = 0
+        block_count = 0
+        if self._ecc_bytes:
+            bs = slice(0, -self._ecc_bytes)
+            be = slice(-self._ecc_bytes, None)
+        else:
+            bs, be = slice(None), slice(0)
+
+        if self._reverse:
+            def conv(data):
+                return bytes(reversed(data))
+        else:
+            def conv(data):
+                return data
+
+        for lno, line in enumerate(self._src, start=1):
+            line = cmt_re.sub('', line).rstrip()
+            if not line:
+                continue
+            if not line.startswith('@'):
+                raise VMemError(f'Invalid line @ {lno}')
+            parts = line[1:].split(' ')
+            part_count = len(parts)
+            try:
+                block = int(parts[0], 16)
+            except ValueError as exc:
+                raise VMemError(f"Invalid address @ line {lno}: {exc}") from exc
+            if block != block_count:
+                raise VMemError(f"Unexpected block {block} @ line {lno}")
+            try:
+                bmap = map(unhexlify, parts[1:])
+            except (TypeError, ValueError) as exc:
+                raise VMemError(f"{exc} @ line {lno}") from exc
+            blocks = ((conv(b[bs]), conv(b[be])) for b in bmap)
+            # _ecc is not yet managed/verified, only discarded
+            data, _ecc = (b''.join(x) for x in zip(*blocks))
+            self._verify_address(address)
+            yield (RecordParser.DATA, address, data)
+            address += len(data)
+            block_count += part_count - 1
+
+
+class RecordBuilder:
+    """Abstract record generator.
+
+       :param crlf: whether to force CRLF line terminators or use host default
+    """
+
+    def __init__(self, crlf=False):
+        self._linesep = '\r\n' if crlf else linesep
+        self._buffer = StringIO()
+
+    def build(self, datasegs, infoseg=None, execaddr=None, offset=0):
+        """Build the SREC stream from a binary stream"""
+        if infoseg:
+            self._buffer.write(self._create_info(infoseg))
+            self._buffer.write(self._linesep)
+        for dataseg in datasegs:
+            for line in self._create_data(offset, dataseg):
+                self._buffer.write(line)
+                self._buffer.write(self._linesep)
+        if execaddr is not None:
+            self._buffer.write(self._create_exec(execaddr))
+            self._buffer.write(self._linesep)
+        eof = self._create_eof()
+        if eof:
+            self._buffer.write(eof)
+            self._buffer.write(self._linesep)
+
+    def getvalue(self) -> str:
+        """Return the record as as string."""
+        return self._buffer.getvalue()
+
+    def _create_info(self, segment):
+        raise NotImplementedError()
+
+    def _create_data(self, offset, segment):
+        raise NotImplementedError()
+
+    def _create_exec(self, address):
+        raise NotImplementedError()
+
+    def _create_eof(self):
+        raise NotImplementedError()
+
+
+class SRecBuilder(RecordBuilder):
+    """Intel Hex generator.
+    """
+
+    @classmethod
+    def checksum(cls, hexastr: str) -> int:
+        """Compute the checksum of an hexa string."""
+        dsum = sum(Array('B', unhexlify(hexastr)))
+        dsum &= 0xff
+        return dsum ^ 0xff
+
+    def _create_info(self, segment):
+        msg = segment.data[:16]
+        line = f'S0{len(msg)+2+1:02x}{0:04x}'
+        line += hexlify(msg)
+        line += f'{SRecBuilder.checksum(line[2:]):02x}'
+        return line.upper()
+
+    def _create_data(self, offset, segment):
+        data = segment.data
+        upaddr = segment.baseaddr+len(data)
+        if upaddr < (1 << 16):
+            prefix = 'S1%02x%04x'
+        elif upaddr < (1 << 24):
+            prefix = 'S2%02x%06x'
+        else:
+            prefix = 'S3%02x%08x'
+        for pos in range(0, len(data), 16):
+            chunk = data[pos:pos+16]
+            hexachunk = hexlify(chunk).decode()
+            line = prefix % (len(chunk) + int(prefix[1]) + 1 + 1,
+                             offset + segment.baseaddr) + hexachunk
+            line += f'{SRecBuilder.checksum(line[2:]):02x}'
+            yield line.upper()
+            offset += 16
+
+    def _create_exec(self, address):
+        if address < (1 << 16):
+            prefix = 'S903%04x'
+        elif address < (1 << 24):
+            prefix = 'S804%06x'
+        else:
+            prefix = 'S705%08x'
+        line = prefix % address
+        line += f'{SRecBuilder.checksum(line[2:]):02x}'
+        return line.upper()
+
+    def _create_eof(self):
+        return ''
+
+
+class IHexBuilder(RecordBuilder):
+    """S-record generator.
+    """
+
+    @classmethod
+    def checksum(cls, hexastr: str) -> int:
+        """Compute the checksum of an hexa string."""
+        csum = sum(Array('B', unhexlify(hexastr)))
+        csum = (-csum) & 0xff
+        return csum
+
+    def _create_info(self, segment):
+        return ''
+
+    def _create_data(self, offset, segment):
+        data = segment.data
+        address = offset + segment.baseaddr
+        high_addr = None
+        for pos in range(0, len(data), 16):
+            high = address >> 16
+            if high != high_addr:
+                hi_bytes = spack('>H', high)
+                yield self._create_line(4, 0, hi_bytes)
+                high_addr = high
+            chunk = data[pos:pos+16]
+            yield self._create_line(0, address & 0xffff, chunk)
+            address += 16
+
+    def _create_exec(self, address):
+        if address < (1 << 20):
+            cs = address >> 4
+            ip = address & 0xFFFF
+            addr = (cs << 16) | ip
+            addr = spack('>I', addr)
+            return self._create_line(3, 0, addr)
+        addr = spack('>I', address)
+        return self._create_line(5, 0, addr)
+
+    def _create_eof(self):
+        return self._create_line(1)
+
+    def _create_line(self, type_, address=0, data=None):
+        if not data:
+            data = b''
+        hexdat = hexlify(data).decode()
+        length = len(data)
+        datastr = f'{length:02X}{address:04X}{type_:02X}{hexdat}'
+        checksum = self.checksum(datastr)
+        line = f':{datastr}{checksum:02X}'
+        return line.upper()
+
+
+class TItxtBuilder(RecordBuilder):
+    """TI-txt generator.
+    """
+
+    # pylint: disable=abstract-method
+
+    def _create_data(self, offset, segment):
+        data = segment.data
+        if data:
+            yield f'@{segment.baseaddr + offset:04x}'
+        for pos in range(0, len(data), 16):
+            chunk = data[pos:pos+16]
+            line = ' '.join((f'{b:02x}' for b in chunk))
+            yield line.upper()
+
+    def _create_eof(self):
+        return 'q'
+
+
+class VMemBuilder(RecordBuilder):
+    """VMEM generator.
+
+       :param crlf: whether to force CRLF line terminators or use host default
+       :param byteorder: either 'little' or 'big', default to big
+       :param chunksize: how many bytes to encode per chunk
+       :param offsetize: how many chars to encode the VMEM offset (0: auto)
+       :param linewidth: maximum character per output line
+    """
+
+    # pylint: disable=abstract-method
+
+    def __init__(self, crlf=False, byteorder: Optional[str] = None,
+                 chunksize: int = 4, offsetsize: int = 0, linewidth: int = 80):
+        super().__init__(crlf)
+        self._chunk_size = chunksize
+        self._offset_size = offsetsize
+        self._line_width = linewidth
+        try:
+            self._reverse = {'little': True, 'big': False}[byteorder]
+        except KeyError as exc:
+            raise ValueError('Invalid byte order') from exc
+
+    def _create_data(self, offset, segment):
+        if offset:
+            raise ValueError('VMEM format does not support offsets')
+        data = segment.data
+        if not data:
+            return
+        total_chunk_count = ((segment.size + self._chunk_size - 1) //
+                             self._chunk_size)
+        max_bit_count = total_chunk_count.bit_length()
+        off_char_len = 2 * ((max_bit_count + 7) // 8)
+        if self._offset_size:
+            if self._offset_size < off_char_len:
+                raise ValueError('Not enough char to encode VMEM offset')
+            off_char_len = self._offset_size
+        off_len = len(f'@{0:0{off_char_len}X} ')
+        chunk_len = 2 * self._chunk_size + 1
+        chunk_per_line = (self._line_width - off_len) // chunk_len
+        line_byte_count = self._chunk_size * chunk_per_line
+        chunk_indices = [x * self._chunk_size for x in range(0, chunk_per_line)]
+        offpos = 0
+        cksize = self._chunk_size
+
+        if self._reverse:
+            def conv(data):
+                return bytes(reversed(data))
+        else:
+            def conv(data):
+                return data
+
+        for pos in range(0, len(data), line_byte_count):
+            chunks = (hexlify(conv(data[pos+ck:pos+ck+cksize])).upper().decode()
+                      for ck in chunk_indices)
+            yield f'@{offpos:0{off_char_len}X} {" ".join(chunks)}'
+            offpos += chunk_per_line
+
+    def _create_eof(self):
+        return ''
+
+
+class BinaryBuilder:
+    """Raw binary generator.
+    """
+
+    # pylint: disable=missing-function-docstring
+
+    def __init__(self, maxsize):
+        self._iofp = BytesIO()
+        self._maxsize = maxsize
+
+    def build(self, datasegs):
+        addr_offset = None
+        for segment in sorted(datasegs, key=lambda seg: seg.baseaddr):
+            if addr_offset is None:
+                addr_offset = segment.baseaddr
+            offset = segment.baseaddr-addr_offset
+            if not 0 <= offset < self._maxsize:
+                # segment cannot start outside flash area
+                raise ValueError('Invalid HEX file')
+            if offset + segment.size > self._maxsize:
+                raise ValueError('Invalid HEX file')
+            self._iofp.seek(segment.baseaddr-addr_offset)
+            self._iofp.write(segment.data)
+        self._iofp.seek(0, SEEK_SET)
+
+    def getvalue(self) -> bytes:
+        return self._iofp.getvalue()
+
+    @property
+    def io(self) -> BinaryIO:
+        return self._iofp
diff --git a/python/qemu/ot/util/sqmp.py b/python/qemu/ot/util/sqmp.py
new file mode 100644
index 0000000000000..5af0f705a5be7
--- /dev/null
+++ b/python/qemu/ot/util/sqmp.py
@@ -0,0 +1,85 @@
+# Copyright (c) 2024, Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""QMP synchronous wrapper.
+"""
+
+from asyncio import new_event_loop, run_coroutine_threadsafe, set_event_loop
+from functools import wraps
+from inspect import stack, getargvalues  # noqa: F401
+from logging import getLogger
+from threading import Thread
+
+from qmp.protocol import Runstate
+from qmp.qmp_client import QMPClient
+
+
+class QMPWrapper:
+    """Small wrapper around QMPClient to call async QEMU API from a synchronous
+       context.
+    """
+
+    def __init__(self, target: tuple[str, int]):
+        self._qmp = QMPClient('opentitan')
+        self._target = target
+        self._log = getLogger('qmp')
+        self._loop = new_event_loop()
+        self._thread = Thread(target=self._run_event_loop, args=(self._loop,),
+                              daemon=True)
+        self._thread.start()
+
+    def _run_event_loop(self, loop):
+        set_event_loop(loop)
+        loop.run_forever()
+
+    def reboot(self) -> None:
+        """Reboot the guest."""
+        self._call_async()
+
+    @property
+    def loop(self):
+        """Return the event loop."""
+        return self._loop
+
+    @staticmethod
+    def sync(func):
+        """Wrap the function into its asynchronous version."""
+        @wraps(func)
+        def wrapper(self, *args, **kwargs):
+            func_name = func.__name__
+            async_fn = getattr(self, f'_{func_name}', None)
+            if not async_fn or not callable(async_fn):
+                raise RuntimeError(f"Unable to locate asynchrounous function "
+                                   f"'{func_name}'")
+            # pylint: disable=not-callable
+            future = run_coroutine_threadsafe(async_fn(*args, **kwargs),
+                                              self.loop)
+            return future.result()
+        return wrapper
+
+    def _call_async(self) -> None:
+        caller = stack()[1]
+        frame = caller.frame
+        func_name = frame.f_code.co_name
+        argvalues = getargvalues(frame)
+        argnames = argvalues[0][1:]  # discard self
+        argvals = argvalues[-1]
+        kwargs = {k: argvals[k] for k in argnames}
+        async_fn = getattr(self, f'_{func_name}', None)
+        if not async_fn or not callable(async_fn):
+            raise RuntimeError(f"Unable to locate asynchrounous function "
+                               f"'{func_name}'")
+        # pylint: disable=not-callable
+        future = run_coroutine_threadsafe(async_fn(**kwargs), self._loop)
+        future.result()
+
+    async def _reboot(self):
+        """Reset the VM."""
+        await self._reconnect()
+        self._log.info('Resetting')
+        await self._qmp.execute('system_reset')
+
+    async def _reconnect(self):
+        if self._qmp.runstate != Runstate.RUNNING:
+            self._log.info('Connecting to %s:%d', *self._target)
+            await self._qmp.connect(self._target)
diff --git a/python/qemu/ot/verilator/__init__.py b/python/qemu/ot/verilator/__init__.py
new file mode 100644
index 0000000000000..2605651963329
--- /dev/null
+++ b/python/qemu/ot/verilator/__init__.py
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""OpenTitan Verilator tools
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+DEFAULT_TIMEOUT = 10.0 * 60
+"""Default execution timeout."""
diff --git a/python/qemu/ot/verilator/executer.py b/python/qemu/ot/verilator/executer.py
new file mode 100644
index 0000000000000..5112b8bb6f102
--- /dev/null
+++ b/python/qemu/ot/verilator/executer.py
@@ -0,0 +1,702 @@
+# Copyright (c) 2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Verilator wrapper."""
+
+from collections import deque
+from io import TextIOWrapper
+from os import close, environ, getcwd, rename, symlink, unlink
+from os.path import (abspath, basename, exists, isfile, islink,
+                     join as joinpath, realpath, splitext)
+from shutil import copyfile
+from subprocess import Popen, PIPE, TimeoutExpired
+from sys import stderr
+from tempfile import mkstemp
+from threading import Event, Thread
+from time import sleep, time as now
+from traceback import format_exc
+from typing import NamedTuple, Optional, Union
+
+import logging
+import re
+
+from ot.rom.image import ROMImage
+from ot.util.elf import ElfBlob
+from ot.util.file import guess_file_type, make_vmem_from_elf
+from ot.util.misc import HexInt, split_map_join
+
+from . import DEFAULT_TIMEOUT
+from .filemgr import VtorFileManager
+from .spi import VtorSpiBridge
+from .vcp import VtorVcpManager
+
+
+class VtorMemRange(NamedTuple):
+    """Memory range (for an initializable memory device)."""
+
+    address: HexInt
+    """Base address."""
+    size: HexInt
+    """Size (in bytes)."""
+
+
+class VtorExecuter:
+    """Verilator wrapper."""
+
+    VMEM_OFFSET = 0
+    """Offset when converting BM test to VMEM file."""
+
+    DV_CRE = re.compile(r'^(\d+):\s\(../.*?\)\s(.*)$')
+    """DV macro messages."""
+
+    VTOR_CRE = re.compile(r'^%(Error|Warning|Info|Debug):(.*)$')
+    """Verilator log messages."""
+
+    DEADLOCK = 125
+    """Default error code when Verilator is stuck."""
+
+    START_TIMEOUT = 2.0
+    """Initial timeout to load and query Verilator."""
+
+    TERMINATION_TIMEOUT = 2.0
+    """Delay for Verilator to quit on request, before being force-killed."""
+
+    def __init__(self, vfm: VtorFileManager, verilator: str,
+                 profile: Optional[str], debug: bool = False):
+        self._log = logging.getLogger('vtor.exec')
+        self._vlog = logging.getLogger('vtor.out')
+        self._profile = profile
+        self._debug = debug
+        self._verilator = verilator
+        self._fm = vfm
+        self._artifact_name: Optional[str] = None
+        self._generate_spi_log = False
+        self._save_xlog = False
+        self._link_xlog = False
+        self._gen_wave = False
+        # parsed communication ports from Verilator
+        self._ports: dict[str, Union[int, str]] = {}
+        self._vcp = VtorVcpManager()
+        self._spi_event = Event()
+        self._spi = VtorSpiBridge(debug)
+        # where Verilator stores the SPI device log file
+        self._spilog_path: Optional[str] = None
+        # where Verilator stores the execution log file
+        self._xlog_path: Optional[str] = None
+        self._resume = False
+        self._threads: list[Thread] = []
+        self._devices: dict[str, VtorMemRange[int, int]] = {}
+        self._secret_file: Optional[str] = None
+        self._device_aliases: dict[str, str] = {}
+
+    def _simplifly_cli(self, args: list[str]) -> str:
+        """Shorten the Verilator command line."""
+        if self._debug:
+            # do not simplify the argument line if debug mode is enabled
+            return ' '.join(args)
+        return ' '.join(split_map_join(',', arg,
+                                       lambda part: split_map_join('=', part,
+                                                                   basename))
+                        for arg in args)
+
+    def enable_exec_log(self, save_log: bool, link_log: bool = False) -> None:
+        """Configure management of the execution log file."""
+        self._save_xlog = save_log
+        self._link_xlog = link_log
+
+    def generate_wave(self, enable: bool) -> None:
+        """Enable generation of an FST wave file."""
+        self._gen_wave = enable
+
+    def show_init_devices(self):
+        """Show initializable devices"""
+        if not self._devices:
+            self._load_devices()
+        width = max(len(d) for d in self._devices) + 1
+        for name, mrg in self._devices.items():
+            print(f'{name:{width}s} 0x{mrg.address:08x} '
+                  f'{mrg.size // 1024:5d} KiB')
+
+    @property
+    def artifact_name(self) -> Optional[str]:
+        """Return the selected name for artifacts, if any."""
+        return self._artifact_name
+
+    @artifact_name.setter
+    def artifact_name(self, basepath: str):
+        """Set the base path for all artifact files."""
+        # store the absolute path, as Verilator runs from a temporary directory
+        self._artifact_name = abspath(basepath)
+
+    @property
+    def rom_devices(self) -> list[str]:
+        """Return a list of supported ROM devices."""
+        if not self._devices:
+            self._load_devices()
+        return [d for d in self._devices if d.startswith('rom')]
+
+    @property
+    def flash_devices(self) -> list[str]:
+        """Return a list of supported embedded flash devices."""
+        if not self._devices:
+            self._load_devices()
+        return [d for d in self._devices if d.startswith('flash')]
+
+    @property
+    def ram_devices(self) -> list[str]:
+        """Return a list of supported RAM devices."""
+        if not self._devices:
+            self._load_devices()
+        return [d for d in self._devices if d.startswith('ram')]
+
+    @property
+    def otp_device(self) -> Optional[str]:
+        """Return the name of the OTP device, if any."""
+        if not self._devices:
+            self._load_devices()
+        return 'otp' if 'otp' in self._devices else None
+
+    @property
+    def secret_file(self) -> Optional[str]:
+        """Secret file observer."""
+        return self._secret_file
+
+    @secret_file.setter
+    def secret_file(self, file_path: str) -> None:
+        """Secret file modifier."""
+        if not isinstance(file_path, str) or not isfile(file_path):
+            raise FileNotFoundError(f'No such secret file {file_path}')
+        self._secret_file = file_path
+
+    def create_spi_device_bridge(self, spi_port: int) -> None:
+        """Create a fake QEMU SPI device server to bridge Verilator SPI device.
+
+           :param spi_port: optional TCP port to create a SPI device bridge
+        """
+        self._spi.create(spi_port, self._spi_event)
+        self._generate_spi_log = True
+
+    def verilate(self, rom_files: list[str], ram_files: list[str],
+                 flash_files: list[str], app_files: list[str],
+                 otp: Optional[str], timeout: float = None,
+                 cycles: Optional[int] = None, ) \
+            -> int:
+        """Execute a Verilator simulation.
+
+           :param rom_files: optional list of files to load in ROMs
+           :param ram_files: optional list of files to load in RAM
+           :param flash_files: optional list of files to load in eFlash
+           :param app_files: optional list of application ELF files to execute
+           :param otp: optional file to load as OTP image
+           :param timeout: optional max execution delay in seconds
+           :param cycles: optional max execution cycles
+        """
+        workdir = self._fm.tmp_dir
+        self._log.debug('Work dir: %s', workdir)
+        if not timeout:
+            timeout = DEFAULT_TIMEOUT
+        ret = None
+        xend = None
+        proc = None
+        simulate = False
+        log_q: Optional[deque] = None
+        profile_file = None
+        if not self._devices:
+            self._load_devices()
+        try:
+            args = [self._verilator]
+            mem_init: dict[str, str] = {}
+            self._assign_init(mem_init, 'rom', rom_files)
+            self._assign_init(mem_init, 'flash', flash_files)
+            self._assign_init(mem_init, 'ram', ram_files)
+            self._assign_apps(mem_init, app_files)
+            args.extend(self._make_init(mem_init))
+            app_name = self._get_app_name(app_files, flash_files, ram_files,
+                                          rom_files)
+            if not app_name:
+                raise RuntimeError('Unable to find an application to run')
+            if not self._artifact_name:
+                basepath = splitext(basename(app_name))[0]
+                self._artifact_name = realpath(joinpath(getcwd(), basepath))
+            if self._profile:
+                args.append('--prof-pgo')
+                profile_file = abspath(self._profile)
+                if isfile(profile_file):
+                    self._log.info('Using profile file %s', profile_file)
+                    args.append(profile_file)
+            if otp:
+                if not self.otp_device:
+                    raise ValueError('Verilator does not support OTP device')
+                otp = abspath(otp)
+                if not isfile(otp):
+                    raise ValueError(f'No such OTP file: {otp}')
+                args.append(f'--meminit=otp,{otp}')
+            if cycles:
+                args.append(f'--term-after-cycles={cycles}')
+            if self._gen_wave:
+                wave_name = f'{self._artifact_name}.fst'
+                args.append(f'--trace={wave_name}')
+            self._log.debug('Executing Verilator as %s',
+                            self._simplifly_cli(args))
+            env = dict(environ)
+            if self._generate_spi_log:
+                # 'P': log SPI PTY protocol (do not use M': SPI "monitor")
+                env['VERILATOR_SPI_LOG'] = 'P'
+            # pylint: disable=consider-using-with
+            proc = Popen(args,
+                         bufsize=1, cwd=workdir, env=env,
+                         stdout=PIPE, stderr=PIPE,
+                         encoding='utf-8', errors='ignore', text=True)
+            try:
+                proc.wait(0.1)
+            except TimeoutExpired:
+                pass
+            else:
+                ret = proc.returncode
+                self._log.error('Verilator bailed out: %d', ret)
+                raise OSError()
+            # if execution starts and the log file should be generated, discards
+            # any previous file to avoid leaving a previous version of such file
+            # that would not match the current session
+            self._discard_logs()
+            log_q = deque()
+            self._resume = True
+            for pos, stream in enumerate(('out', 'err')):
+                thread = Thread(target=self._vtor_logger,
+                                name=f'veri_{stream}_logger',
+                                args=(getattr(proc, f'std{stream}'), log_q,
+                                      bool(pos)),
+                                daemon=True)
+                self._threads.append(thread)
+                thread.start()
+            abstimeout = float(timeout) + now()
+            while now() < abstimeout:
+                if self._spi_event.is_set():
+                    match self._spi.exception:
+                        case TimeoutError():
+                            reason = 'no response from Verilator'
+                        case BrokenPipeError() | ConnectionResetError():
+                            reason = 'host disconnected'
+                        case Exception():
+                            reason = str(self._spi.exception)
+                        case _:
+                            reason = 'unknown'
+                    if not ret:
+                        ret = proc.poll()
+                    if not ret:
+                        ret = 1
+                    self._log.error('Exiting on %s SPI bridge event, code %d',
+                                    reason, ret)
+                    break
+                while log_q:
+                    err, qline = log_q.popleft()
+                    if err:
+                        level = logging.ERROR
+                    else:
+                        # for some reason, Verilator outputs log messages to
+                        # stdout, not stderr
+                        if self._parse_verilator_log(qline):
+                            continue
+                        level = logging.INFO
+                    if not err and not simulate:
+                        if qline.startswith('Simulation running, '):
+                            simulate = True
+                            self._vcp.connect({
+                                k: v for k, v in self._ports.items()
+                                if k.startswith('uart')}, 2.0)
+                            spi_ptys = sorted([v for p, v in self._ports.items()
+                                               if p.startswith('spi')])
+                            if spi_ptys:
+                                self._spi.connect_pty(spi_ptys[0])
+                                # only support a single SPI device bridge
+                                if len(spi_ptys) > 1:
+                                    self._log.warning('Too many SPI devices')
+                            self._log.info('Simulation begins')
+                        else:
+                            self._parse_verilator_info(qline)
+                    else:
+                        qline = self._parse_verilator_output(qline, err)
+                        if qline:
+                            self._vlog.log(level, qline)
+                    break
+                else:
+                    sleep(0.005)
+                xret = proc.poll()
+                if xret is None:
+                    xret = self._vcp.process()
+                if xret is not None:
+                    self._log.debug('Verilator exited with code %d', xret)
+                    if xend is None:
+                        xend = now()
+                    ret = xret
+                    break
+        except (OSError, ValueError) as exc:
+            if self._debug:
+                print(format_exc(chain=False), file=stderr)
+            if ret is None:
+                self._log.error('Unable to execute Verilator: %s', exc)
+                if proc and proc.poll() is not None:
+                    ret = proc.returncode
+                else:
+                    ret = self.DEADLOCK
+        finally:
+            self._spi.disconnect()
+            self._vcp.disconnect()
+            if proc:
+                # leave some for Verilator to cleanly complete and flush its
+                # streams
+                wait = self.TERMINATION_TIMEOUT
+                if xend is None:
+                    xend = now()
+                waited_time = now()
+                proc.terminate()
+                try:
+                    # go through if Verilator has exited on its own
+                    proc.wait(wait)
+                except TimeoutExpired:
+                    # otherwise kill it
+                    self._log.error('Force-killing Verilator')
+                    proc.kill()
+                # ensure completion delay is always satisfied whatever the
+                # termination reason
+                waited_time = now() - waited_time
+                rem = wait - waited_time
+                if rem > 0.0:
+                    sleep(rem)
+                if ret is None:
+                    ret = proc.returncode
+                self._resume = False
+                timeout_count = 10
+                while self._threads:
+                    timeout_count -= 1
+                    if not timeout_count:
+                        self._log.error('Cannot terminate %s',
+                                        ', '.join((t.name
+                                                   for t in self._threads)))
+                        break
+                    thread = self._threads.pop(0)
+                    thread.join(timeout=0.2)
+                    if thread.is_alive():
+                        self._threads.append(thread)
+                # retrieve the remaining log messages
+                while log_q:
+                    err, qline = log_q.popleft()
+                    level = logging.ERROR if err else logging.INFO
+                    qline = self._parse_verilator_output(qline, err)
+                    if qline:
+                        self._vlog.log(level, qline)
+                for msg, logger in zip(proc.communicate(timeout=0.1),
+                                       (self._vlog.info, self._vlog.error)):
+                    # should have been captured by the logger threads
+                    for line in msg.splitlines():
+                        line = line.rstrip()
+                        if line:
+                            logger(line)
+                if log_q:
+                    # should never happen
+                    self._vlog.error('Lost traces')
+                self._save_logs()
+            tmp_profile = joinpath(workdir, 'profile.vlt')
+            if isfile(tmp_profile) and profile_file:
+                self._log.info('Saving profile file as %s', profile_file)
+                copyfile(tmp_profile, profile_file)
+        if ret:
+            self._log.error("Verilator failed: %s", ret)
+        else:
+            self._log.info("Success")
+        return abs(ret or 0)
+
+    def _vtor_logger(self, stream: TextIOWrapper, queue: deque, err: bool) \
+            -> None:
+        # worker thread, blocking on VM stdout/stderr
+        if not stream:
+            self._log.error('No Verilator std%s stream',
+                            'err' if err else 'out')
+            return
+        while self._resume:
+            try:
+                line = stream.readline().rstrip()
+            # pylint: disable=broad-except
+            except Exception as exc:
+                # do not raise an error if stream disappears
+                self._log.error('%s', exc)
+                if self._debug:
+                    print(format_exc(chain=False), file=stderr)
+                break
+            if line:
+                queue.append((err, line))
+            else:
+                sleep(0.005)
+        self._log.debug('End of std%s logger thread', 'err' if err else 'out')
+
+    def _load_devices(self) -> None:
+        args = [self._verilator, '--meminit=list']
+        out = ''
+        with Popen(args, bufsize=1, cwd=self._fm.tmp_dir, encoding='utf-8',
+                   errors='ignore', text=True, stdout=PIPE) as proc:
+            proc.wait(self.START_TIMEOUT)
+            out = proc.stdout.read()
+        for mro in re.finditer(r"'(?P<name>\w+)'.*"
+                               r"\[(?P<start>0x[0-9a-f]+),\s*"
+                               r"(?P<end>0x[0-9a-f]+)\]", out):
+            self._devices[mro.group('name')] = VtorMemRange(
+                start := HexInt(mro.group('start'), 16),
+                HexInt(mro.group('end'), 16) - start + 1)
+        # handle the special DJ case where RAM is call CTN_RAM
+        if 'ctn_ram' in self._devices:
+            # rename any existing ram devices
+            ram_devices = sorted(d for d in self._devices
+                                 if d.startswith('ram'))
+            renamed_devices: dict[str, str] = {}
+            for rpos, ram_dev in enumerate(ram_devices, 1):
+                ram_name = f'ram{rpos}'
+                renamed_devices[ram_name] = self._devices.pop(ram_dev)
+                self._device_aliases[ram_name] = ram_dev
+            # insert CTM_RAM as the first RAM device, since this is likely the
+            # one to be used for loading application
+            self._devices['ram0'] = self._devices.pop('ctn_ram')
+            self._device_aliases['ram0'] = 'ctn_ram'
+            self._devices.update(renamed_devices)
+
+    def _assign_init(self, mem_init: dict[str, str], dev_kind: str,
+                     dev_files: list[str]) -> list[str]:
+        known_devs = getattr(self, f'{dev_kind}_devices', [])
+        if len(dev_files) > len(known_devs):
+            raise ValueError(f'Verilator does not support {len(dev_files)} '
+                             f'{dev_kind.upper()} images')
+        for dpos, (kdev, dev_file) in enumerate(zip(known_devs, dev_files)):
+            if not dev_file:
+                continue
+            file_kind = guess_file_type(dev_file)
+            if dev_kind == 'rom':
+                size = self._devices[kdev].size
+                real_file = self._convert_rom_file(file_kind, dev_file, size,
+                                                   dpos)
+            else:
+                real_file = self._convert_app_file(file_kind, dev_file)
+            mem_init[kdev] = real_file
+
+    def _assign_apps(self, mem_init: dict[str, str], app_files: list[str]):
+        for app_file in app_files:
+            file_kind = guess_file_type(app_file)
+            base_file = basename(app_file)
+            # only ELF file contains meta information to know the load address
+            # if any other type of file is used (bin/vmem/svmem/hex), the
+            # load destination device needs to be specified, assigning the app
+            # to a known device
+            if file_kind != 'elf':
+                raise ValueError(f'No known address to load {base_file}')
+            # load the ELF to retrieve load address and size
+            elf = ElfBlob()
+            with open(app_file, 'rb') as efp:
+                elf.load(efp)
+            app_addr = elf.load_address
+            app_size = elf.size
+            app_end = app_addr + app_size
+            # find the destination device based on the extracted meta info
+            for dev_name, mrg in self._devices.items():
+                dev_end = mrg.address + mrg.size
+                if mrg.address <= app_addr < dev_end:
+                    real_name = self._device_aliases.get(dev_name, dev_name)
+                    if app_end > dev_end:
+                        raise ValueError(f'{base_file} cannot fit in '
+                                         f'{real_name}')
+                    if dev_name in mem_init:
+                        raise ValueError(f'{base_file} overrides another file '
+                                         f'in {real_name}')
+                    self._log.info('Locating %s in %s', base_file, real_name)
+                    # if the destination device is a ROM device, then the file
+                    # to load need to be scrambled
+                    if dev_name.startswith('rom'):
+                        dev_idx = list(self.rom_devices).index(dev_name)
+                        mem_init[dev_name] = \
+                            self._convert_rom_file(file_kind, app_file,
+                                                   mrg.size, dev_idx)
+                    # otherwise, a regular VMEM should be enough
+                    else:
+                        mem_init[dev_name] = self._convert_app_file(file_kind,
+                                                                    app_file)
+                    break
+            else:
+                raise ValueError(f'No matching device to fit {base_file}')
+
+    def _make_init(self, mem_init: dict[str, str]) -> list[str]:
+        """Build the initialization argument list from the memory device map."""
+        args = []
+        for dev_name, real_file in mem_init.items():
+            real_dev = self._device_aliases.get(dev_name, dev_name)
+            args.append(f'--meminit={real_dev},{real_file}')
+        return args
+
+    def _get_app_name(self, *args) -> Optional[str]:
+        """Try to find which application is tested from the list of initialized
+           devices.
+        """
+        for apps in args:
+            if not isinstance(apps, list):
+                apps = [apps]
+            for app in reversed(apps):
+                if app:
+                    return app
+        return None
+
+    def _parse_verilator_info(self, line: str) -> None:
+        """Parse initial verilator output which contains communication port
+           descriptors as strings.
+        """
+        if line.startswith('remote_bitbang_port '):
+            self._ports['jtag'] = int(line.split(' ')[1])
+            return
+        if line.startswith('GPIO: FIFO pipes'):
+            parts = line.split(' ')
+            for gdir in ('read', 'write'):
+                pos = parts.index(f'({gdir})')
+                if pos > 0:
+                    self._ports[f'gpio_{gdir[0]}'] = parts[pos-1]
+            return
+        if any((line.startswith(f'{dev}: Created ')
+                for dev in ('UART', 'SPI'))):
+            parts = line.split('.')[0].split(' ')
+            self._ports[parts[-1]] = parts[-3]
+            return
+        spi_prefix = 'SPI: PTY output file created at '
+        if line.startswith(spi_prefix):
+            spi_log_line = line.removeprefix(spi_prefix)
+            self._spilog_path = spi_log_line.rsplit('.', 1)[0]
+            self._log.debug('SPI PTY log path: %s', self._spilog_path)
+
+    def _parse_verilator_log(self, line: str) -> bool:
+        """Parse verilator log mesage.
+
+           If the log message is emitted from Verilator engine, route the
+           message with the matching level to the logger and return True to
+           indicate the message has been handled. Return False otherwise so that
+           the message is handled with the next log message handler.
+        """
+        lmo = self.VTOR_CRE.search(line)
+        if lmo:
+            vlevel = lmo.group(1).upper()
+            level = getattr(logging, vlevel)
+            self._vlog.log(level, lmo.group(2).strip())
+            return True
+        return False
+
+    def _parse_verilator_output(self, line: str, err: bool) -> str:
+        if err:
+            return line
+        dvmo = self.DV_CRE.match(line)
+        if dvmo:
+            return ' '.join(dvmo.groups())
+        if not line.startswith('TOP.chip_sim_tb'):
+            return line
+        if not self._xlog_path:
+            trace_msg = 'Writing execution trace to '
+            pos = line.find(trace_msg)
+            if pos >= 0:
+                self._xlog_path = realpath(joinpath(self._fm.tmp_dir,
+                                                    line[pos+len(trace_msg):]))
+                self._log.info('Execution log: %s', self._xlog_path)
+                if self._link_xlog:
+                    assert self._artifact_name is not None
+                    log_path = f'{self._artifact_name}.log'
+                    tmpslnk = f'{log_path}.tmp'
+                    if islink(tmpslnk):
+                        unlink(tmpslnk)
+                    elif exists(tmpslnk):
+                        raise FileExistsError(f'File {tmpslnk} already exists')
+                    self._log.debug('Symlinking execution log as %s', log_path)
+                    symlink(self._xlog_path, tmpslnk)
+                    rename(tmpslnk, log_path)
+                return ''
+        return line
+
+    def _discard_logs(self) -> None:
+        if not self._artifact_name:
+            return
+        for log_suffix in ('', 'spi.'):
+            log_path = f'{self._artifact_name}.{log_suffix}log'
+            if not isfile(log_path):
+                continue
+            try:
+                unlink(log_path)
+                self._log.debug('Old execution log file discarded: %s',
+                                log_path)
+            except OSError as exc:
+                self._log.error('Cannot remove previous execution log file: %s',
+                                exc)
+
+    def _save_logs(self) -> None:
+        self._save_exec_log()
+        self._save_spi_log()
+
+    def _save_exec_log(self) -> None:
+        if not self._save_xlog:
+            return
+        if not self._xlog_path:
+            self._log.error('No execution log file found')
+            return
+        if not isfile(self._xlog_path):
+            self._log.error('Missing execution log file')
+            return
+        assert self._artifact_name is not None
+        log_path = f'{self._artifact_name}.log'
+        # discard existing log_path if it has been created as a symlink
+        if self._link_xlog and islink(log_path):
+            unlink(log_path)
+        self._log.debug('Saving execution log as %s', log_path)
+        copyfile(self._xlog_path, log_path)
+
+    def _save_spi_log(self) -> None:
+        if not self._generate_spi_log:
+            return
+        if not self._spilog_path:
+            self._log.error('No SPI log file found')
+            return
+        if not isfile(self._spilog_path):
+            self._log.error('Missing SPI log file')
+            return
+        assert self._artifact_name is not None
+        log_path = f'{self._artifact_name}.spi.log'
+        self._log.debug('Saving SPI log as %s', log_path)
+        copyfile(self._spilog_path, log_path)
+
+    def _convert_rom_file(self, file_kind: str, file_path: str, size: int,
+                          rom_idx: int) -> str:
+        if file_kind in ('hex', 'svmem'):
+            # no conversion required
+            return file_path
+        # need to create a scrambled version of the file for the ROM
+        if not self._secret_file:
+            raise RuntimeError('Cannot create a scrambled ROM image w/o '
+                               'ROM secrets')
+        rom = ROMImage()
+        with open(self._secret_file, 'rt') as cfp:
+            rom.load_config(cfp, rom_idx)
+        with open(file_path, 'rb') as rfp:
+            rom.load(rfp, size)
+        prefix = f'{splitext(basename(file_path))[0]}.'
+        hex_no, hex_path = mkstemp(suffix='.39.vmem', prefix=prefix,
+                                   dir=self._fm.tmp_dir, text=True)
+        close(hex_no)
+        with open(hex_path, 'wb') as hfp:
+            rom.save(hfp, 'svmem')
+        self._log.debug('ROM#%d: using temp scrambled as ROM file %s, %d bytes',
+                        rom_idx, basename(hex_path), size)
+        return hex_path
+
+    def _convert_app_file(self, file_kind: str, file_path: str) -> str:
+        if file_kind == 'vmem':
+            # no conversion required
+            return abspath(file_path)
+        if file_kind == 'elf':
+            prefix = f'{splitext(basename(file_path))[0]}.'
+            vmem_no, vmem_path = mkstemp(suffix='.vmem', prefix=prefix,
+                                         dir=self._fm.tmp_dir, text=True)
+            with open(vmem_no, 'wt') as vfp:
+                make_vmem_from_elf(file_path, vfp, offset=self.VMEM_OFFSET,
+                                   chunksize=8, offsetsize=8)
+            self._log.debug('Using temp application file %s',
+                            basename(vmem_path))
+            return vmem_path
+        raise RuntimeError(f'Unsupported application file type: {file_kind}')
diff --git a/python/qemu/ot/verilator/filemgr.py b/python/qemu/ot/verilator/filemgr.py
new file mode 100644
index 0000000000000..9451eb0ac568a
--- /dev/null
+++ b/python/qemu/ot/verilator/filemgr.py
@@ -0,0 +1,45 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Verilator wrapper."""
+
+from atexit import register
+from logging import getLogger
+from os.path import isdir
+from shutil import rmtree
+from tempfile import mkdtemp
+from typing import Optional
+
+
+class VtorFileManager:
+    """File manager.
+
+       Handle temporary directories and files.
+
+       :param keep_temp: do not automatically discard generated files on exit
+       :param tmp_dir: store the temporary files in the specified directory
+    """
+
+    def __init__(self, keep_temp: bool = False, tmp_dir: Optional[str] = None):
+        self._log = getLogger('vtor.file')
+        self._keep_temp = keep_temp
+        self._base_tmp_dir = tmp_dir
+        self._tmp_dir: Optional[str] = None
+        register(self._cleanup)
+
+    @property
+    def tmp_dir(self) -> str:
+        """Provides the main temporary directory for executing Verilator."""
+        if not self._tmp_dir:
+            self._tmp_dir = mkdtemp(prefix='verilator_ot_dir_',
+                                    dir=self._base_tmp_dir)
+        return self._tmp_dir
+
+    def _cleanup(self):
+        if self._tmp_dir and isdir(self._tmp_dir):
+            if self._keep_temp:
+                self._log.warning('Preserving temp dir %s', self._tmp_dir)
+                return
+            self._log.debug('Removing temp dir %s', self._tmp_dir)
+            rmtree(self._tmp_dir)
+            self._tmp_dir = None
diff --git a/python/qemu/ot/verilator/spi.py b/python/qemu/ot/verilator/spi.py
new file mode 100644
index 0000000000000..6ed7bfee602d2
--- /dev/null
+++ b/python/qemu/ot/verilator/spi.py
@@ -0,0 +1,375 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Verilator SPI protocol bridge.
+
+   Accept incoming requests using QEMU OT SPI device protocol (TCP socket)
+   Converts requests/responses to/from Verilator SPI DPI simplified protocol
+   (PTY socket).
+
+   See https://github.com/lowRISC/opentitan/pull/28803 for SPI DPI protocol.
+"""
+
+from binascii import hexlify
+from collections import deque
+from enum import IntFlag
+from fcntl import fcntl, F_GETFL, F_SETFL
+from os import O_NONBLOCK
+from io import BufferedRandom
+from socket import create_server, socket, SHUT_RDWR
+from struct import unpack as sunpack
+from threading import Event, Thread
+from time import sleep, time as now
+from traceback import format_exc
+from typing import Optional, Union
+
+import logging
+import sys
+
+from ot.spi.spi_device import SpiDevice
+
+
+class VtorSpiInput(IntFlag):
+    """Bit assignment on Verilator SPI device input."""
+    SCK = 0
+    CSB = 1
+    SDI = 2
+
+
+class VtorSpiOutput(IntFlag):
+    """Bit assignment on Verilator SPI device output."""
+    SDO_EN = 0
+    SDO = 1
+
+
+class VtorSpiBridge:
+    """SPI bridge.
+
+       Expose a QEMU OT SPI device-compatible socket.
+       Relay SPI bus requests to Verilator SPI device port.
+    """
+
+    CONN_TIMETOUT = 0.25
+    """Maximum time waiting for a connection before yielding
+    """
+
+    POLL_TIMEOUT = 0.05
+    """Maximum time to wait on a blocking operation.
+    """
+
+    PTY_SYNC = 0.1
+    """Time to poll for PTY connection.
+    """
+
+    SPI_BUS_TIMEOUT = 0.5
+    """Maximum time to receive a response from Verilator PTY.
+    """
+
+    SCK_LOW = 0
+    SCK_HIGH = 1 << VtorSpiInput.SCK
+    CSB_LOW = 0
+    CSB_HIGH = 1 << VtorSpiInput.CSB
+    SDI_LOW = 0
+    SDI_HIGH = 1 << VtorSpiInput.SDI
+    SDO_EN_HIGH = 1 << VtorSpiOutput.SDO_EN
+    SDO_HIGH = 1 << VtorSpiOutput.SDO
+
+    # Each byte requires 16 PTY chars (two clock edges per bit, i.e. two chars).
+    PTY_CHAR_PER_BYTE = 16
+    DEFAULT_PTY_BUF_SIZE = 512  # 1024 should be a safe value
+
+    ASCII_ZERO = ord('0')
+
+    def __init__(self, debug: bool = False):
+        self._log = logging.getLogger('vtor.spi')
+        self._slog = logging.getLogger('vtor.spi.server')
+        self._clog = logging.getLogger('vtor.spi.client')
+        self._debug = debug
+        self._server: Optional[Thread] = None
+        self._pty: Optional[BufferedRandom] = None
+        self._resume = False
+        self._cs = False  # note: False means inactive (i.e. /CS high)
+        self._exception = Optional[Exception]
+        self._chunk_size = 0
+        # initialize self._chunk_size with the property setter
+        self.pty_buffer_size = self.DEFAULT_PTY_BUF_SIZE
+
+    def create(self, tcp_port: int, end_event: Event) -> None:
+        """Create fake QEMU SPI device server.
+           :param tcp_port: TCP port on local host to listen for incoming
+                            connections.
+           :param end_event: event to signal on SPI bridge termination.
+        """
+        if not self._server:
+            self._server = Thread(target=self._serve, name='spibridge',
+                                  daemon=True, args=(tcp_port, end_event))
+
+    @property
+    def pty_buffer_size(self) -> int:
+        """Get current PTY usable buffer size."""
+        return self._chunk_size * self.PTY_CHAR_PER_BYTE
+
+    @pty_buffer_size.setter
+    def pty_buffer_size(self, pty_buffer_size: int) -> None:
+        """Set PTY usable buffer size."""
+        self._chunk_size = pty_buffer_size // self.PTY_CHAR_PER_BYTE
+
+    def connect_pty(self, pty_name: str) -> None:
+        """Connect Verilator SPI device pseudo-terminal.
+
+           :param pty_name: pseudo terminal device to use for the SPI device
+        """
+        if self._pty:
+            raise RuntimeError('Cannot reconnect to PTY')
+        try:
+            # pylint: disable=consider-using-with
+            pty = open(pty_name, 'rb+', buffering=0)
+            flags = fcntl(pty, F_GETFL)
+            fcntl(pty, F_SETFL, flags | O_NONBLOCK)
+            self._log.debug('SPI device PTY %s connected', pty_name)
+            self._pty = pty
+        except (ConnectionError, OSError) as exc:
+            self._log.error('Cannot connect Verilator SPI device PTY %s: '
+                            '%s', pty_name, exc)
+            raise
+        if not self._server:
+            return
+        self._resume = True
+        self._server.start()
+
+    def disconnect(self) -> None:
+        """Disconnect all managed VCPs."""
+        self._resume = False
+        if self._server:
+            if self._server.is_alive():
+                self._server.join()
+            self._server = None
+        if self._pty:
+            self._pty.close()
+            self._pty = None
+
+    @property
+    def exception(self) -> Optional[Exception]:
+        """Return last exception, if any has been raised."""
+        return self._exception
+
+    def _serve(self, tcp_port: int, event: Event):
+        """Worker thread that bridge SPI device communication between a QEMU
+           SPI device client and Verilator bitbang SPI device PTY.
+        """
+        try:
+            sock = create_server(('localhost', tcp_port),
+                                 backlog=1, reuse_port=True)
+        except OSError:
+            self._log.fatal('Cannot connect to :%d', tcp_port)
+            raise
+        sock.settimeout(self.CONN_TIMETOUT)
+        with sock:
+            try:
+                while self._resume:
+                    try:
+                        conn, addr = sock.accept()
+                    except TimeoutError:
+                        # check whether server should resume every CONN_TIMEOUT
+                        # to avoid deadlocking when no client wants to connect
+                        continue
+                    self._log.debug('New SPI device connection %s:%s', *addr)
+                    with conn:
+                        self._serve_connection(conn)
+            except Exception as exc:
+                self._exception = exc
+                event.set()
+                raise
+            finally:
+                try:
+                    sock.shutdown(SHUT_RDWR)
+                    sock.close()
+                except OSError:
+                    pass
+
+    def _serve_connection(self, sock: socket) -> None:
+        buffer = bytearray()
+        length = 0
+        pty_en = False
+        cfg = 0
+        while self._resume:
+            if not self._pty:
+                # there is no point handling incoming SPI host requests while
+                # downstream PTY is not available
+                sleep(self.PTY_SYNC)
+                continue
+            if not pty_en:
+                # set IDLE state on SPI device connection: /CS high, SCK low
+                self._log.debug('SPI idle')
+                idle = bytes([self.CSB_HIGH | self.SCK_LOW])
+                sync = 10
+                while sync:
+                    self._pty.write(idle)
+                    data = self._pty.read(len(idle))
+                    if data:
+                        break
+                    sleep(0.1)
+                    sync -= 1
+                else:
+                    raise TimeoutError('No reply from SPI device')
+                pty_en = True
+            try:
+                # arbitrary length to receive all buffered data at once.
+                data = sock.recv(1024)
+                if not data:
+                    self._log.warning('SPI host disconnected')
+                    return
+                buffer.extend(data)
+                if not buffer:
+                    # wait for data
+                    continue
+                if not length:
+                    # wait for header
+                    if len(buffer) < SpiDevice.CS_HEADER_SIZE:
+                        continue
+                    magic, version, cfg, length = \
+                        sunpack(SpiDevice.CS_HEADER_FMT,
+                                buffer[:SpiDevice.CS_HEADER_SIZE])
+                    if magic != b'/CS':
+                        self._slog.error('Invalid SPI magic: %s',
+                                         hexlify(magic).decode())
+                        if self._debug:
+                            raise RuntimeError('SPI protocol error')
+                        return
+                    if version != 0:
+                        self._slog.error('Invalid SPI protocol version: %d',
+                                         version)
+                        if self._debug:
+                            raise RuntimeError('SPI version error')
+                        return
+                    buffer = buffer[SpiDevice.CS_HEADER_SIZE:]
+                if len(buffer) < length:
+                    # wait for SPI packet/payload
+                    self._slog.debug('Expect %d bytes, got %d; %d to go',
+                                     length, len(buffer), length-len(buffer))
+                    continue
+                request, buffer = bytes(buffer[:length]), buffer[length:]
+                release = not bool(cfg >> 7)
+                cfg &= 0b1111
+                if cfg:
+                    # only support SPI mode 0, default order
+                    self._slog.error('SPI mode/config not supported: %s',
+                                     f'0b{cfg:04b}')
+                    sock.send(bytes([0xff] * length))
+                    length = 0
+                    continue
+                if len(request) <= 32:
+                    self._slog.debug('SPI request  > %s (%d)',
+                                     hexlify(request).decode(), len(request))
+                else:
+                    self._slog.debug('SPI request  > %s (%d) ...',
+                                     hexlify(request[:32]).decode(),
+                                     len(request))
+                response = self._handle_spi_request(request, release)
+                if len(request) <= 32:
+                    self._slog.debug('SPI response < %s, %s /CS',
+                                     hexlify(response).decode(),
+                                     'release' if release else 'hold')
+                else:
+                    self._slog.debug('SPI response < %s, %s ... /CS',
+                                     hexlify(response[:32]).decode(),
+                                     'release' if release else 'hold')
+                assert len(response) == length
+                length = 0
+                if not sock.send(response):
+                    self._log.warning('SPI host disconnected')
+                    return
+            except (BrokenPipeError, ConnectionResetError):
+                self._log.warning('SPI host disconnected')
+                return
+            # pylint: disable=broad-except
+            except Exception as exc:
+                # connection shutdown may have been requested
+                if self._resume:
+                    self._resume = False
+                    self._log.fatal('Exception: %s', exc)
+                    if self._debug:
+                        print(format_exc(chain=False), file=sys.stderr)
+                    raise
+
+    def _exchange_pty(self, bit_seq: Union[bytes, bytearray]) -> bytearray:
+        self._pty.write(bit_seq)
+        return self._read_from_pty(len(bit_seq))
+
+    def _read_from_pty(self, size: int) -> bytearray:
+        mi_bit_seq = bytearray()
+        # increase a bit the timeout for large packets
+        timeout = now() + self.SPI_BUS_TIMEOUT * (1 + size / 20)
+        while now() < timeout:
+            data = self._pty.read(size-len(mi_bit_seq))
+            if not data:
+                continue
+            mi_bit_seq.extend(data)
+            if len(mi_bit_seq) == size:
+                break
+        else:
+            raise TimeoutError(f'Not enough data received from SPI device: '
+                               f'{len(mi_bit_seq)} < {size}')
+        return mi_bit_seq
+
+    def _handle_spi_request(self, request: bytes, release: bool) -> bytes:
+        # ensure CSB is low (if not already)
+        prolog = bytes([self.CSB_LOW | self.SCK_LOW])
+        self._exchange_pty(prolog)
+        mo_bit_seq = bytearray()
+        mi_bit_que = deque()
+        # add ASCII '0' so it's easier to debug the comm channel:
+        # no need to hexlify, upper nibble is never printed out (0x01 -> '1')
+        # the remote peer (Verilator SPI DPI) only considers the 3 LSBs anyway.
+        pos = 0
+        # PTY buffer size is hardcoded (OS setting, not configurable)
+        # we do not want to overshoot its capability, so split the request
+        # into manageable chunks.
+        for _ in range(0, len(request), self._chunk_size):
+            for _ in range(self._chunk_size):
+                byte = request[pos]
+                for _ in range(8):
+                    bit = byte & 0x80
+                    byte <<= 1
+                    sdi = self.SDI_HIGH if bit else self.SDI_LOW
+                    mo_bit_seq.append(self.ASCII_ZERO | sdi |
+                                      self.CSB_LOW | self.SCK_LOW)
+                    mo_bit_seq.append(self.ASCII_ZERO | sdi |
+                                      self.CSB_LOW | self.SCK_HIGH)
+                pos += 1
+                if pos == len(request):
+                    break
+            self._clog.debug('MOSI %s', mo_bit_seq.decode())
+            mi_bit_seq = self._exchange_pty(mo_bit_seq)
+            self._clog.debug('MISO %s', bytes(mi_bit_seq).decode())
+            assert len(mo_bit_seq) == len(mi_bit_seq)
+            mo_bit_seq.clear()
+            mi_bit_que.extend(mi_bit_seq)
+        if release:
+            self._clog.debug('Release')
+            epilog = bytes([self.ASCII_ZERO |
+                            self.SDI_LOW | self.CSB_HIGH | self.SCK_LOW])
+            self._exchange_pty(epilog)
+        self._cs = not release
+        response = bytearray()
+        req_byte_count = len(request)
+        while len(response) < req_byte_count:
+            byte = 0
+            for _ in range(8):
+                if len(mi_bit_que) < 2:
+                    raise RuntimeError('Incoherent response length')
+                mi_bit_que.popleft()  # sample (clock low)
+                bval = mi_bit_que.popleft()  # sample (clock high / raise)
+                # ignore ASCII MSBs if any
+                # pylint: disable=superfluous-parens
+                if not (bval & self.SDO_EN_HIGH):
+                    bit = 0
+                else:
+                    bit = int(bool(bval & self.SDO_HIGH))
+                byte <<= 1
+                byte |= bit
+            response.append(byte)
+        if mi_bit_que:
+            raise RuntimeError(f'Incoherent response length {len(mi_bit_que)} '
+                               f'/ {int(release)}')
+        return response
diff --git a/python/qemu/ot/verilator/vcp.py b/python/qemu/ot/verilator/vcp.py
new file mode 100644
index 0000000000000..f90a2b177b7e2
--- /dev/null
+++ b/python/qemu/ot/verilator/vcp.py
@@ -0,0 +1,150 @@
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Verilator virtual comm port management."""
+
+from fcntl import fcntl, F_GETFL, F_SETFL
+from os import O_NONBLOCK
+from io import BufferedRandom
+from select import POLLIN, POLLERR, POLLHUP, poll as sel_poll
+from sys import stderr
+from time import time as now
+from traceback import format_exc
+from typing import NamedTuple, Optional
+
+import logging
+import re
+
+from ot.util.log import ColorLogFormatter
+
+
+class VtorVcpDescriptor(NamedTuple):
+    """ Virtual communication port."""
+
+    vcpid: str
+    """VCP identifier."""
+    pty: BufferedRandom
+    """Attached pseudo terminal."""
+    buffer: bytearray
+    """Data buffer."""
+    logger: logging.Logger
+    """Associated logger."""
+
+
+class VtorVcpManager:
+    """Virtual COM port manager.
+
+       Handles messages emitted on serial port.
+    """
+
+    ANSI_CRE = re.compile(rb'(\x9B|\x1B\[)[0-?]*[ -\/]*[@-~]')
+    """ANSI escape sequences."""
+
+    def __init__(self):
+        self._log = logging.getLogger('vtor.vcp')
+        self._vcps: dict[int, VtorVcpDescriptor] = {}
+        self._poller = sel_poll()
+
+    def connect(self, vcp_map: dict[str, str], delay: float) -> None:
+        """Connect Verilator pseudo-terminals.
+
+           :param vcp_map: a map of serial port, pseudo terminal device
+           :param delay: how long to wait for a successful connection,
+                         in seconds
+        """
+        vcp_map = dict(vcp_map)
+        timeout = now() + delay
+        # ensure that QEMU starts and give some time for it to set up
+        # when multiple VCPs are set to 'wait', one VCP can be connected at
+        # a time, i.e. QEMU does not open all connections at once.
+        vcp_lognames = []
+        vcplogname = 'vtor'
+        vcplognames = []
+        while vcp_map:
+            if now() > timeout:
+                minfo = ', '.join(f'{d} @ {r}'
+                                  for d, r in vcp_map.items())
+                raise TimeoutError(f'Cannot connect to Verilator VCPs: {minfo}')
+            connected = []
+            for vcpid, ptyname in vcp_map.items():
+                try:
+                    # pylint: disable=consider-using-with
+                    vcp = open(ptyname, 'rb+', buffering=0)
+                    flags = fcntl(vcp, F_GETFL)
+                    fcntl(vcp, F_SETFL, flags | O_NONBLOCK)
+                    connected.append(vcpid)
+                    vcp_lognames.append(vcpid)
+                    vcp_log = logging.getLogger(f'{vcplogname}.{vcpid}')
+                    vcplognames.append(vcpid)
+                    vcp_fno = vcp.fileno()
+                    assert vcp_fno not in self._vcps
+                    self._vcps[vcp_fno] = VtorVcpDescriptor(vcpid, vcp,
+                                                            bytearray(),
+                                                            vcp_log)
+                    self._log.debug('VCP %s connected to pty %s',
+                                    vcpid, ptyname)
+                    self._poller.register(vcp, POLLIN | POLLERR | POLLHUP)
+                except ConnectionRefusedError:
+                    continue
+                except OSError as exc:
+                    self._log.error('Cannot setup Verilator VCP connection %s: '
+                                    '%s', vcpid, exc)
+                    print(format_exc(chain=False), file=stderr)
+                    raise
+            # removal from dictionary cannot be done while iterating it
+            for vcpid in connected:
+                del vcp_map[vcpid]
+        self._colorize_vcp_log(vcplogname, vcplognames)
+
+    def disconnect(self) -> None:
+        """Disconnect all managed VCPs."""
+        for _, vcp, _, _ in self._vcps.values():
+            self._poller.unregister(vcp)
+            vcp.close()
+        self._vcps.clear()
+
+    def process(self) -> Optional[int]:
+        """Handle any received message on VCPs.
+
+           :return: an optional integer (exit code) to early abort execution.
+                    not yet implemented, always return None.
+        """
+        ret = None
+        for vfd, event in self._poller.poll(0.01):
+            if event in (POLLERR, POLLHUP):
+                self._poller.modify(vfd, 0)
+                continue
+            _, vcp, vcp_buf, vcp_log = self._vcps[vfd]
+            try:
+                data = vcp.read(256)
+            except TimeoutError:
+                self._log.error('Unexpected timeout w/ poll on %s', vcp)
+                continue
+            if not data:
+                continue
+            vcp_buf += data
+            lines = vcp_buf.split(b'\n')
+            vcp_buf[:] = bytearray(lines[-1])
+            for line in lines[:-1]:
+                line = self.ANSI_CRE.sub(b'', line)
+                sline = line.decode('utf-8', errors='ignore').rstrip()
+                level = logging.INFO
+                vcp_log.log(level, sline)
+            if ret is not None:
+                # match for exit sequence on current VCP
+                break
+        return ret
+
+    def _colorize_vcp_log(self, logbase: str, lognames: list[str]) -> None:
+        vlog = logging.getLogger(logbase)
+        clr_fmt = None
+        while vlog:
+            for hdlr in vlog.handlers:
+                if isinstance(hdlr.formatter, ColorLogFormatter):
+                    clr_fmt = hdlr.formatter
+                    break
+            vlog = vlog.parent
+        if not clr_fmt:
+            return
+        for color, logname in enumerate(sorted(lognames)):
+            clr_fmt.add_logger_colors(f'{logbase}.{logname}', color)
diff --git a/qapi/qom.json b/qapi/qom.json
index 6f5c9de0f0b29..29f47ccb556bc 100644
--- a/qapi/qom.json
+++ b/qapi/qom.json
@@ -1167,6 +1167,19 @@
   'data': { '*cpu-affinity': ['uint16'],
             '*node-affinity': ['uint16'] } }
 
+##
+# @OtRomImgProperties:
+#
+# Properties for OpenTitan ROM image objects.
+#
+# @file: the filename for the ROM image file
+#    supported format: ELF, raw BIN, VMEM (unscrambled no ECC,
+#    scrambled with ECC), raw HEX (scrambled with ECC)
+#
+##
+{ 'struct': 'OtRomImgProperties',
+  'data': { 'file': 'str' } }
+
 ##
 # @ObjectType:
 #
@@ -1217,6 +1230,7 @@
     'memory-backend-ram',
     { 'name': 'memory-backend-shm',
       'if': 'CONFIG_POSIX' },
+    'ot-rom_img',
     'pef-guest',
     { 'name': 'pr-manager-helper',
       'if': 'CONFIG_LINUX' },
@@ -1295,6 +1309,7 @@
       'memory-backend-ram':         'MemoryBackendProperties',
       'memory-backend-shm':         { 'type': 'MemoryBackendShmProperties',
                                       'if': 'CONFIG_POSIX' },
+      'ot-rom_img':                 'OtRomImgProperties',
       'pr-manager-helper':          { 'type': 'PrManagerHelperProperties',
                                       'if': 'CONFIG_LINUX' },
       'qtest':                      'QtestProperties',
diff --git a/scripts/opentitan/.flake8 b/scripts/opentitan/.flake8
new file mode 100644
index 0000000000000..fbd6e07a1d5c0
--- /dev/null
+++ b/scripts/opentitan/.flake8
@@ -0,0 +1,3 @@
+[flake8]
+max-line-length = 80
+extend-ignore = E402
diff --git a/scripts/opentitan/.pylintrc b/scripts/opentitan/.pylintrc
new file mode 100644
index 0000000000000..08cca9a65f31e
--- /dev/null
+++ b/scripts/opentitan/.pylintrc
@@ -0,0 +1,20 @@
+[MESSAGES CONTROL]
+
+disable=
+    unknown-option-value,
+    import-error,
+    too-few-public-methods,
+    too-many-arguments,
+    too-many-branches,
+    too-many-function-args,
+    too-many-instance-attributes,
+    too-many-lines,
+    too-many-locals,
+    too-many-nested-blocks,
+    too-many-positional-arguments,
+    too-many-public-methods,
+    too-many-return-statements,
+    too-many-statements,
+    unspecified-encoding,
+    wrong-import-order,
+    wrong-import-position
diff --git a/scripts/opentitan/autoreg.py b/scripts/opentitan/autoreg.py
new file mode 100755
index 0000000000000..33099115c8daf
--- /dev/null
+++ b/scripts/opentitan/autoreg.py
@@ -0,0 +1,1435 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Generate device definitions for OpenTitan device.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, FileType
+from enum import StrEnum, auto
+from io import StringIO
+from logging import getLogger
+from os.path import basename, dirname, join as joinpath, normpath, splitext
+from time import localtime
+from traceback import format_exception
+from typing import Any, NamedTuple, Optional, TextIO, Union
+
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+# ruff: noqa: E402
+from ot.util.eval import safe_eval
+from ot.util.log import configure_loggers
+from ot.util import mbb
+from ot.util.misc import (HexInt, camel_to_snake_case, camel_to_snake_uppercase,
+                          classproperty, flatten, redent, retrieve_git_version,
+                          to_bool)
+from ot.util.arg import ArgError
+
+try:
+    _HJSON_ERROR = None
+    from hjson import load as hjload
+except ImportError as hjson_exc:
+    _HJSON_ERROR = str(hjson_exc)
+
+
+class AutoAccess(StrEnum):
+    """Type of access to a register or a field."""
+    UNDEF = auto()
+    RO = auto()
+    RW = auto()
+    WO = auto()
+    RC = auto()
+    RW0C = auto()
+    RW1C = auto()
+    RW1S = auto()
+    R0W1C = auto()
+    URO = auto()  # "unused read/only"
+
+
+class AutoField(NamedTuple):
+    """Register field."""
+
+    name: str
+    desc: Optional[str]
+    offset: int
+    width: int
+    access: AutoAccess
+    reset: int = 0
+
+    def __str__(self) -> str:
+        """Return a compact representation of a field."""
+        return (f'{self.__class__.__name__}({self.offset}:{self.name}:'
+                f'{self.width} {self.access})')
+
+
+class AutoRegister(NamedTuple):
+    """Device register."""
+
+    name: str
+    desc: Optional[str]
+    address: int
+    access: AutoAccess
+    fields: list[AutoField] = []
+    reset: Optional[int] = None
+    count: int = 1
+    shared_fields: bool = False
+
+
+class AutoReg:
+    """Register definition generator.
+
+       :param devname: the name of the generated QEMU device
+       :param ignore_prefix: an optional prefix to discard useless register
+                             definitions. Registers and fields starting with
+                             this prefix are ignored.
+       :param resets: a list of reset functions to generate, if any.
+    """
+
+    RESETS = ['enter', 'hold', 'exit']
+
+    WINDOW_LIMIT = 64
+    """Default window item count limit."""
+
+    def __init__(self, devname: str, ignore_prefix: Optional[str] = None,
+                 resets: Optional[list[str]] = None):
+        self._log = getLogger('autoreg')
+        self._devname = devname
+        self._ignore_prefix = ignore_prefix
+        self._git_version = 'unknown'
+        self._resets = resets or []
+        self._parameters: dict[str, Union[int, bool]] = {}
+        self._regwidth = 0  # bits
+        self._registers: list[AutoRegister] = []
+        self._copyright = '@todo Add copyright attributions'
+        self._reg_groups: dict[str, set[str]] = {}  # group, reg names
+        self._group_offsets: dict[str, int] = {}
+        self._irq_count = 0
+        self._alert_count = 0
+        self._nibcount = 0
+
+    @classproperty
+    def generators(cls):
+        """Provide a list of supported generators."""
+        # pylint: disable=no-self-argument
+        actions: list[str] = []
+        prefix = 'generate_'
+        for item in dir(cls):
+            if not item.startswith(prefix):
+                continue
+            actions.append(item.removeprefix(prefix))
+        actions.sort()
+        return actions
+
+    def load(self, hfp: TextIO, win_lim: Optional[int] = None) -> None:
+        """Load a register map definition from an OT HJSON file."""
+        if hfp.name:
+            git_version = retrieve_git_version(hfp.name)
+            if git_version:
+                self._git_version = git_version
+                self._log.info('Git info for %s: %s', basename(hfp.name),
+                               self._git_version)
+        hjson = hjload(hfp, object_pairs_hook=dict)
+        # heuristics
+        # registers -seem- to either be a list of registers, or a map of buses
+        # which contain the list of registers; need to check if some bus name
+        # is defined for the registers that need to be parsed
+        bus_if = None
+        for bus in hjson.get('bus_interfaces', []):
+            if bus.get('protocol') != 'tlul':
+                continue
+            if bus.get('direction') != 'device':
+                continue
+            bus_if = bus.get('name')
+            break
+        self._parameters.update(self._parse_parameters(hjson.get('param_list',
+                                                       [])))
+        self._regwidth = int(hjson.get('regwidth', 32))
+        addr_inc = self._regwidth // 8
+        address = 0
+        registers: list[AutoRegister] = []
+        registers.extend(self._parse_interrupts(hjson, address, addr_inc))
+        address = len(registers) * addr_inc
+        registers.extend(self._parse_alerts(hjson, address))
+        address = len(registers) * addr_inc
+        regnames: set[str] = set(r.name for r in registers)
+        regdefs = hjson['registers']
+        if bus_if:
+            self._log.info("Using registers from bus '%s'", bus_if)
+            regdefs = regdefs[bus_if]
+        for item in regdefs:
+            if 'skipto' in item:
+                address = HexInt.parse(item['skipto'])
+                continue
+            if 'multireg' in item:
+                item = item['multireg']
+                # compact field can either be a string, a boolean, an integer
+                # and may be present or not
+                force_compact = item.get('compact')
+                reg = self._parse_register(address, item)
+                count = safe_eval(item['count'], self._parameters)
+                if force_compact is not None:
+                    compact = to_bool(force_compact)
+                else:
+                    compact = len(reg.fields) == 1
+                if compact:
+                    # single register with multiple fields with the same prefix
+                    if len(reg.fields) > 1:
+                        # this case is not yet supported
+                        raise NotImplementedError(f'Too many compact fields for'
+                                                  f' {reg.name}')
+                    field = reg.fields[0]
+                    fwidth = field.offset + field.width
+                    fcount = min(count, self._regwidth // fwidth)
+                    if fcount > 1:
+                        reg = reg._replace(fields=[
+                            field._replace(name=f'{field.name}_{pos}',
+                                           offset=pos)
+                            for pos in range(fcount)
+                        ])
+                    else:
+                        reg = reg._replace(fields=[])
+                    count = count // fcount
+                if count > 1:
+                    # multiple registers with the same name prefix
+                    reg = reg._replace(count=count)
+                    regnames.add((f'{reg.name}_{ix}' for ix in range(count)))
+                registers.append(reg)
+                address += addr_inc * count
+                continue
+            if 'window' in item:
+                item = item['window']
+                reg = self._parse_register(address, item)
+                count = safe_eval(item['items'], self._parameters)
+                if count > (win_lim or self.WINDOW_LIMIT):
+                    self._log.warning(
+                        'Ignoring oversized window %s with %u items',
+                        reg.name, count)
+                    continue
+                fields = reg.fields
+                if not reg.fields:
+                    validbits = item.get('validbits')
+                    if validbits:
+                        field = AutoField("data", desc=None, offset=0,
+                                          width=int(validbits),
+                                          access=reg.access)
+                        fields = [field]
+                reg = reg._replace(count=count, fields=fields)
+                regnames.add((f'{reg.name}_{ix}' for ix in range(count)))
+                registers.append(reg)
+                address += addr_inc * count
+                continue
+            reg = self._parse_register(address, item)
+
+            if reg:
+                if reg.name in regnames:
+                    prefix = reg.name.split('_')[0]
+                    if prefix in ('INTR', 'ALERT'):
+                        # Comportable registers may already be defined, discard
+                        continue
+                    raise ValueError(f'Register {reg.name} redefined')
+                regnames.add(reg.name)
+                registers.append(reg)
+                address += addr_inc
+        registers.sort(key=lambda r: r.address)
+        self._registers = registers
+        self._reg_groups[''] = {reg.name for reg in registers}
+        self._group_offsets[''] = 0
+        max_addr = max(reg.address for reg in registers)
+        self._nibcount = (max_addr.bit_length() + 3) // 4
+
+    @property
+    def copyright(self) -> str:
+        """Return current copyright string.
+        """
+        return self._copyright
+
+    @copyright.setter
+    def copyright(self, copyright_str: str) -> None:
+        """Set copyright string.
+        """
+        self._copyright = copyright_str
+
+    def segment(self, segdescs: list[str]) -> None:
+        """Create register segmentation."""
+        renum_names: dict[str, str] = {}
+        for segdesc in segdescs:
+            try:
+                regname, segment = segdesc.split(':')
+            except ValueError as exc:
+                raise ArgError(f'Invalid segment declaration: '
+                               f'{segdesc}') from exc
+            regname = regname.upper()
+            if regname in renum_names:
+                raise ArgError(f'Multiple segmentation on {regname}')
+            if segment in renum_names.values():
+                raise ArgError(f'Multiple definition of {segment}')
+            renum_names[regname] = segment.upper()
+        reg_names = {reg.name for reg in self._registers}
+        missing = set(renum_names) - reg_names
+        if missing:
+            raise ArgError(f'Unknown registers: {", ".join(missing)}')
+        upregs: list[AutoRegister] = []
+        addr_inc = self._regwidth // 8
+        address = 0
+        group = self._reg_groups.popitem()[0]
+        del self._group_offsets[group]
+        for reg in self._registers:
+            new_group = renum_names.get(reg.name)
+            if new_group:
+                self._log.info('Reset address base on %s', reg.name)
+                group = new_group
+                address = 0
+            if group not in self._reg_groups:
+                self._reg_groups[group] = []
+                self._group_offsets[group] = reg.address
+            self._reg_groups[group].append(reg.name)
+            upregs.append(reg._replace(address=address))
+            address += addr_inc * reg.count
+        self._registers = upregs
+
+    def generate_register(self, tfp: TextIO) -> None:
+        """Generate the register map.
+
+           :param tfp: output file stream
+        """
+        self._generate_registers(tfp)
+
+    def _parse_interrupts(self, hjson: dict[str, Any], address: int,
+                          addr_inc: int) -> list[AutoRegister]:
+        fields: list[AutoField] = []
+        if hjson.get('no_auto_intr_regs', False):
+            self._log.info('Comportable interrupt generation disabled')
+            return []
+        for fpos, item in enumerate(hjson.get('interrupt_list', [])):
+            access = 'ro' if item.get('type') == 'status' else 'rw1c'
+            fieldargs = [item['name'].upper(), item['desc'], fpos, 1,
+                         AutoAccess(access), 0]
+            fields.append(AutoField(*fieldargs))
+        self._irq_count = len(fields)
+        if not fields:
+            return []
+        registers: list[AutoRegister] = []
+        # pylint: disable=use-dict-literal
+        regargs = dict(
+            name='INTR_STATE',
+            desc='Interrupt state',
+            address=address,
+            access=self._build_reg_access(fields),
+            fields=fields,
+            reset=0,
+            count=1,
+            shared_fields=True
+        )
+        registers.append(AutoRegister(**regargs))
+        address += addr_inc
+        regargs = dict(
+            name='INTR_ENABLE',
+            desc='Interrupt enable',
+            address=address,
+            access=AutoAccess('rw'),
+        )
+        registers.append(AutoRegister(**regargs))
+        address += addr_inc
+        regargs = dict(
+            name='INTR_TEST',
+            desc='Interrupt test',
+            address=address,
+            access=AutoAccess('wo'),
+        )
+        registers.append(AutoRegister(**regargs))
+        return registers
+
+    def _parse_alerts(self, hjson: dict[str, Any], address: int) \
+            -> list[AutoRegister]:
+        fields: list[AutoField] = []
+        if hjson.get('no_auto_alert_regs', False):
+            self._log.info('Comportable alert generation disabled')
+            return []
+        wo_acc = AutoAccess('wo')
+        for fpos, item in enumerate(hjson.get('alert_list', [])):
+            fieldargs = [item['name'].upper(), item['desc'], fpos, 1, wo_acc, 0]
+            fields.append(AutoField(*fieldargs))
+        self._alert_count = len(fields)
+        if not fields:
+            return []
+        # pylint: disable=use-dict-literal
+        regargs = dict(
+            name='ALERT_TEST',
+            desc='Alert test',
+            address=address,
+            access=wo_acc,
+            fields=fields,
+            reset=0
+        )
+        return [AutoRegister(**regargs)]
+
+    def _parse_register(self, address: int, reg: dict[str, Any]) \
+            -> Optional[AutoRegister]:
+        name = reg.get('name')
+        if not name:
+            return None
+        if self._ignore_prefix and name.startswith(self._ignore_prefix):
+            return None
+        desc = reg.get('desc')
+        self._log.debug('Register: %s', name)
+        fields = self._parse_reg_fields(reg)
+        fields.sort(key=lambda f: f.offset)
+        reset = self._build_reg_reset(fields)
+        access = self._build_reg_access(fields)
+        rname = camel_to_snake_case(name).upper()
+        regargs = [rname, desc, address, access, fields, reset]
+        return AutoRegister(*regargs)
+
+    def _parse_reg_fields(self, reg: dict[str, Any]) -> list[AutoField]:
+        fields: list[AutoField] = []
+        bitfield = 0
+        reg_swaccess = reg.get('swaccess')
+        rname = reg['name']
+        nibcount = self._regwidth // 4
+        for field in reg.get('fields', []):
+            name = field.get('name')
+            if not name:
+                name = rname
+                if fields:
+                    raise ValueError(f'Multiple anonymous bitfields '
+                                     f'for reg {name}')
+            if self._ignore_prefix and name.startswith(self._ignore_prefix):
+                continue
+            desc = field.get('desc')
+            bits = field.get('bits')
+            if isinstance(bits, str) and ':' in bits:
+                hibit, lobit = (self._parse_bits(x) for x in bits.split(':'))
+                offset = lobit
+                width = hibit-lobit+1
+            else:
+                offset = self._parse_bits(bits)
+                width = 1
+            bitmask = ((1 << width) - 1) << offset
+            if bitmask & bitfield:
+                raise ValueError(f'Bitfield {name} overlap: '
+                                 f'0x{bitfield:0{nibcount}x}, mask '
+                                 f'0x{bitmask:0{nibcount}x}')
+            bitfield |= bitmask
+            try:
+                access = getattr(AutoAccess,
+                                 field.get('swaccess', reg_swaccess).upper())
+            except KeyError as exc:
+                raise RuntimeError(f'Cannot find swaccess for {name}') from exc
+            resval = field.get('resval')
+            mubi = field.get('mubi', False)
+            if isinstance(resval, bool):
+                if mubi:
+                    mubi_symbol = f'MB{width}_{str(resval).upper()}'
+                    reset = getattr(mbb, mubi_symbol, None)
+                    if reset is None:
+                        raise ValueError(f'Unknown value for {mubi_symbol}')
+                else:
+                    reset = int(resval)
+            else:
+                reset = HexInt.parse(resval, accept_int=True) \
+                        if resval else HexInt(0)
+            fname = camel_to_snake_case(name).upper()
+            fieldargs = [fname, desc, offset, width, access, reset]
+            fields.append(AutoField(*fieldargs))
+        bitmask = (1 << self._regwidth) - 1
+        if bitfield & ~bitmask:
+            raise ValueError(f'Bitfield {name} out of range: '
+                             f'0x{bitfield:0{nibcount}x}, mask '
+                             f'0x{bitmask:0{nibcount}x}')
+        return fields
+
+    def _parse_bits(self, value: Union[int, str]) -> int:
+        try:
+            # simple integer
+            return int(value)
+        except ValueError:
+            eval_value = safe_eval(value, self._parameters)
+            self._log.info("parametric value '%s' evaluated as '%s'",
+                           value, eval_value)
+            return eval_value
+
+    def _parse_parameters(self, params: list[dict[str, Any]]) \
+            -> dict[str, Union[int, bool]]:
+        parameters: dict[str, Union[int, bool]] = {}
+        converters = {
+            'int': HexInt.parse,
+            'int unsigned': HexInt.parse,
+            'bit': bool
+        }
+        for param in params:
+            name = param.get('name')
+            type_ = param.get('type')
+            value = param.get('default')
+            if not all((name, type_, value is not None)):
+                continue
+            conv = converters.get(type_)
+            if not conv:
+                self._log.warning("Type '%s' for param '%s' is not supported",
+                                  type_, name)
+                continue
+            parameters[name] = conv(value)
+        return parameters
+
+    def _build_reg_reset(self, fields):
+        reset = 0
+        for field in fields:
+            reset |= field.reset << field.offset
+        return reset
+
+    def _build_reg_access(self, fields):
+        access = set(f.access for f in fields)
+        if len(access) == 1:
+            return access.pop()
+        return AutoAccess.UNDEF
+
+    def _generate_registers(self, tfp: TextIO) -> None:
+        raise NotImplementedError("Abstract base class")
+
+
+class QEMUAutoReg(AutoReg):
+    """Generator for QEMU skeleton files."""
+
+    def generate_all(self, tfp: TextIO) -> None:
+        """Generate a QEMU device skeleton file based on the register map.
+
+           :param tfp: output file stream
+        """
+        self.generate_header(tfp)
+        self.generate_param(tfp)
+        self.generate_register(tfp)
+        self.generate_mask(tfp)
+        self.generate_regname(tfp)
+        self.generate_struct(tfp)
+        self.generate_io(tfp)
+        self.generate_device(tfp)
+
+    def generate_header(self, tfp: TextIO) -> None:
+        """Generate the skeleton for the header of a device driver.
+
+           :param tfp: output file stream
+        """
+        dname = self._devname
+        pname = dname.title().replace('_', ' ')
+        year = localtime().tm_year
+        code = f'''
+        /*
+         * QEMU {pname} device
+         *
+         * Copyright (c) {year} {self.copyright}
+         *
+         * Author(s):
+         *
+         * Permission is hereby granted, free of charge, to any person obtaining a copy
+         * of this software and associated documentation files (the "Software"), to deal
+         * in the Software without restriction, including without limitation the rights
+         * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+         * copies of the Software, and to permit persons to whom the Software is
+         * furnished to do so, subject to the following conditions:
+         *
+         * The above copyright notice and this permission notice shall be included in
+         * all copies or substantial portions of the Software.
+         *
+         * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+         * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+         * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+         * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+         * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+         * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+         * THE SOFTWARE.
+         *
+         * Based on OpenTitan {self._git_version}
+         */
+
+        #include "qemu/osdep.h"
+        #include "qemu/log.h"
+        #include "hw/qdev-properties.h"
+        #include "hw/registerfields.h"
+        #include "hw/sysbus.h"
+        #include "trace.h"
+
+        '''  # noqa: E501
+        print(redent(code), file=tfp)
+
+    def generate_struct(self, tfp: TextIO) -> None:
+        """Generate the skeleton for the device state and class structs.
+
+           :param tfp: output file stream
+        """
+        dname = self._devname
+        hdname = dname.title().replace('_', '')
+        header = f'''
+        struct {hdname}State {{
+            SysBusDevice parent_obj;
+
+            MemoryRegion mmio;
+        '''
+        extras = []
+        indent = header.rsplit('\n', 1)[-1]
+        if len(self._reg_groups) > 1:
+            for group in self._reg_groups:
+                extras.append(f'    MemoryRegion mmio_{group.lower()};'
+                              f'\n{indent}')
+        if self._irq_count or self._alert_count:
+            extras.append(f'\n{indent}')
+        if self._irq_count:
+            extras.append(f'    IbexIRQ irqs[NUM_IRQS];\n{indent}')
+        if self._alert_count:
+            extras.append(f'    IbexIRQ alerts[NUM_ALERTS];\n{indent}')
+        extras.append(f'\n{indent}')
+        if len(self._reg_groups) == 1:
+            extras.append(f'    uint{self._regwidth}_t *regs;\n{indent}')
+        else:
+            for group in self._reg_groups:
+                sregs = f'regs_{group.lower()}'
+                extras.append(f'    uint{self._regwidth}_t *{sregs};\n{indent}')
+        extra = ''.join(extras)
+        footer = f'''
+            char *ot_id;
+        }};
+
+        struct {hdname}Class {{
+            SysBusDeviceClass parent_class;
+            ResettablePhases parent_phases;
+        }};
+
+        '''
+        code = f'{header}{extra}{footer}'
+        print(redent(code), file=tfp)
+
+    def generate_param(self, tfp: TextIO) -> None:
+        """Generate the parameter constants.
+
+           :param tfp: output file stream
+        """
+        cat_params: dict[str, dict[str, int]] = {}
+        max_length = 0
+        name_first = ('NUM', )
+        parameters = dict(self._parameters)
+        if self._irq_count:
+            parameters['NUM_IRQS'] = self._irq_count
+        if self._alert_count:
+            parameters['NUM_ALERTS'] = self._alert_count
+        for name, value in parameters.items():
+            ucname = camel_to_snake_uppercase(name)
+            parts = ucname.split('_')
+            pre = parts[0]
+            suf = parts[-1]
+            if pre in name_first:
+                cat = pre
+            else:
+                cat = suf
+            if cat not in cat_params:
+                cat_params[cat] = {}
+            cat_params[cat][ucname] = value
+            max_length = max(max_length, len(ucname))
+        for cat in name_first:
+            if cat in cat_params:
+                cat_params[cat] = dict(sorted(cat_params[cat].items()))
+        cat_fmt = {
+            'OFFSET': 'x'
+        }
+        for cat, fmt in cat_fmt.items():
+            if not fmt.endswith('x'):
+                continue
+            if cat not in cat_params:
+                continue
+            maxval = max(cat_params[cat].values())
+            nibble = (maxval.bit_length() + 3) // 4
+            cat_params[cat] = {n: f'0x{v:0{nibble}{fmt}}u'
+                               for n, v in cat_params[cat].items()}
+        for cat in sorted(cat_params):
+            params = cat_params[cat]
+            for name, value in params.items():
+                if isinstance(value, bool):
+                    # no use case for this kind of parameter
+                    continue
+                imod = 'u' if isinstance(value, int) and value >= 0 else ''
+                print(f'#define {name:<{max_length}s} {value}{imod}', file=tfp)
+        print(file=tfp)
+
+    def generate_reset(self, tfp: TextIO) -> None:
+        """Generate reset initialization values.
+
+           :param tfp: output file stream
+        """
+        for group, regs in self._build_reg_groups():
+            for reg in regs:
+                self._generate_reg_reset(group, reg, tfp)
+
+    def generate_mask(self, tfp: TextIO) -> None:
+        """Generate the write mask associated with the register map.
+
+           :param tfp: output file stream
+        """
+        for _, regs in self._build_reg_groups():
+            self._generate_mask(regs, tfp)
+        print(file=tfp)
+
+    def generate_io(self, tfp: TextIO) -> None:
+        """Generate the skeleton for the MMIO read and write functions.
+
+           :param tfp: output file stream
+        """
+        groups = self._build_reg_groups()
+        for group, regs in groups:
+            self._generate_io(group, regs, False, tfp)
+        for group, regs in groups:
+            self._generate_io(group, regs, True, tfp)
+
+    def generate_regname(self, tfp: TextIO) -> None:
+        """Generate the array of register names.
+
+           :param tfp: output file stream
+        """
+        print(f'#define R{self._regwidth}_OFF(_r_) ((_r_) / '
+              f'sizeof(uint{self._regwidth}_t))\n', file=tfp)
+        groups = self._build_reg_groups()
+        for group, regs in groups:
+            self._generate_reg_wrappers(group, regs, tfp)
+        print('#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)',
+              file=tfp)
+        for pos, (group, regs) in enumerate(groups):
+            self._generate_regname_array(group, regs, tfp)
+            if pos < len(groups) - 1:
+                print('', file=tfp)
+        print('#undef REG_NAME_ENTRY\n', file=tfp)
+
+    def generate_device(self, tfp: TextIO) -> None:
+        """Generate the skeleton for the device initialization functions.
+
+           :param tfp: output file stream
+        """
+        self._generate_mr_ops(tfp)
+        self._generate_props(tfp)
+        for reset_type in self._resets:
+            self._generate_reset(tfp, reset_type)
+        self._generate_realize(tfp)
+        self._generate_init(tfp)
+        self._generate_class_init(tfp)
+        self._generate_type(tfp)
+
+    @classmethod
+    def tweak_field_name(cls, regname: str, fieldname: str) -> str:
+        """Attempt to simplify field names to avoid useless duplication
+           of the register name in the field name.
+        """
+        last = regname.split('_')[-1]
+        if regname != fieldname:
+            if last != fieldname:
+                return fieldname
+        if last in ('ENABLE', 'REGWEN'):
+            return 'EN'
+        return 'VAL'
+
+    def _build_reg_groups(self) -> list[tuple[str, list[AutoRegister]]]:
+        """Build list of register grouped by segment groups
+
+           :return: a list of (group, ordered(AutoRegister))
+        """
+        return [(group, [reg for reg in self._registers
+                         if reg.name in regnames])
+                for group, regnames in self._reg_groups.items()]
+
+    def _generate_registers(self, tfp: TextIO) -> None:
+        print('/* clang-format off */', file=tfp)
+        for reg in self._registers:
+            if reg.count == 1:
+                self._generate_register(reg, tfp)
+                continue
+            address = reg.address
+            addr_inc = self._regwidth // 8
+            for rpos in range(reg.count):
+                rreg = reg._replace(name=f'{reg.name}_{rpos}',
+                                    address=address, count=1,
+                                    fields=reg.fields if rpos == 0 else [],
+                                    shared_fields=rpos == 0)
+                self._generate_register(rreg, tfp)
+                address += addr_inc
+        print('/* clang-format on */\n', file=tfp)
+
+    def _generate_register(self, reg: AutoRegister, tfp: TextIO) -> None:
+        print(f'REG{self._regwidth}({reg.name}, '
+              f'0x{reg.address:0{self._nibcount}x}u)',
+              file=tfp)
+        if not reg.shared_fields:
+            if len(reg.fields) > 1:
+                for field in reg.fields:
+                    fdname = self.tweak_field_name(reg.name, field.name)
+                    print(f'    FIELD({reg.name}, {fdname}, '
+                          f'{field.offset}u, '
+                          f'{field.width}u)', file=tfp)
+            elif reg.fields:
+                field = reg.fields[0]
+                if field.width != self._regwidth:
+                    # do not emit a field if the field covers the entire reg
+                    fdname = self.tweak_field_name(reg.name, field.name)
+                    print(f'    FIELD({reg.name}, {fdname}, {field.offset}u, '
+                          f'{field.width}u)', file=tfp)
+        else:
+            name = '_'.join(reg.name.rsplit('_', 1)[:-1])
+            if len(reg.fields) > 1:
+                for field in reg.fields:
+                    print(f'    SHARED_FIELD({name}_{field.name}, '
+                          f'{field.offset}u, '
+                          f'{field.width}u)', file=tfp)
+            elif reg.fields:
+                field = reg.fields[0]
+                if field.width != self._regwidth:
+                    # do not emit a field if the field covers the entire reg
+                    if name != field.name:
+                        shname = f'{name}_{field.name}'
+                    else:
+                        shname = name
+                    print(f'    SHARED_FIELD({shname}, '
+                          f'{field.offset}u, '
+                          f'{field.width}u)', file=tfp)
+
+    def _generate_reg_reset(self, group: str, reg: AutoRegister,
+                            tfp: TextIO) -> None:
+        if reg.reset:
+            regs = f'regs_{group.lower()}' if group else 'regs'
+            print(f'    s->{regs}[R_{reg.name}] = 0x{reg.reset:x}u;',
+                  file=tfp)
+
+    def _generate_mask(self, regs: list[AutoRegister], tfp: TextIO) -> None:
+        for reg in regs:
+            if len(reg.fields) < 2:
+                continue
+            bitmask = sum(((1 << bf.width) - 1) << bf.offset
+                          for bf in reg.fields)
+            bitfield = (1 << self._regwidth) - 1
+            if bitfield & ~bitmask == 0:
+                continue
+            if not reg.shared_fields:
+                masks: list[str] = [
+                    f'{reg.name}_{field.name}_MASK' for field in reg.fields
+                    if field.access not in (AutoAccess.RO,)
+                ]
+            else:
+                name = '_'.join(reg.name.rsplit('_', 1)[:-1]) or reg.name
+                masks: list[str] = [
+                    f'{name}_{field.name}_MASK' for field in reg.fields
+                    if field.access not in (AutoAccess.RO,)
+                ]
+            if not masks:
+                continue
+            maskstr = ' | \\\n     '.join(masks)
+            if not reg.shared_fields:
+                name = reg.name
+            else:
+                name = '_'.join(reg.name.rsplit('_', 1)[:-1]) or reg.name
+            print(f'#define {name}_WMASK \\\n    ({maskstr})', file=tfp)
+            # special cast for interrupt testing with mixed fields
+            if (reg.name == 'INTR_STATE' and reg.shared_fields and
+               reg.access == AutoAccess.UNDEF):
+                masks: list[str] = [
+                    f'{name}_{field.name}_MASK' for field in reg.fields
+                ]
+                maskstr = ' | \\\n     '.join(masks)
+                print(f'#define INTR_TEST_WMASK \\\n    ({maskstr})',
+                      file=tfp)
+
+    def _generate_io(self, group: str, regs: list[AutoRegister], write: bool,
+                     tfp: TextIO) -> None:
+        unfold_regs: list[AutoRegister] = []
+        for reg in regs:
+            if reg.count > 1:
+                addr_inc = self._regwidth // 8
+                for rpos in range(reg.count):
+                    unfold_regs.append(
+                        reg._replace(name=f'{reg.name}_{rpos}',
+                                     address=reg.address + addr_inc * rpos,
+                                     count=1))
+            else:
+                unfold_regs.append(reg)
+        nregs = {r.name: r for r in unfold_regs}
+        reg_names = set(nregs)
+        reg_defs = {r.name: (sum(((1 << bf.width) - 1) << bf.offset
+                                 for bf in r.fields), r.access)
+                    for r in unfold_regs}
+        if write:
+            noaccess_types = (AutoAccess.RO, AutoAccess.URO)
+        else:
+            noaccess_types = (AutoAccess.WO, )
+        noaccess_names = {
+            r.name for r in unfold_regs if r.access in noaccess_types
+        }
+        rc_names = {
+            r.name for r in unfold_regs if r.access == AutoAccess.RC
+        }
+        reg_names -= noaccess_names
+        if not write and rc_names:
+            reg_names -= rc_names
+        rwidth = self._regwidth
+        dname = self._devname
+        if group:
+            lgroup = group.lower()
+            larg = f'"{lgroup}", '
+            sregs = f's->regs_{lgroup}'
+        else:
+            sregs = 's->regs'
+            larg = ''
+        dpad = ' ' * (len(dname) - 7)
+        hsname = self._devname.title().replace('_', '')
+        rnm = '_'.join(filter(None, ('REG', group, 'NAME')))
+        vnm = f'val{rwidth}'
+        if write:
+            if rwidth < 64:
+                vcast = f'uint{rwidth}_t val{rwidth} = (uint{rwidth}_t)val64;'
+            else:
+                vcast = ''
+            code = f'''
+            static void {dname}_regs_write(void *opaque, hwaddr addr,
+                                    {dpad}uint64_t val64, unsigned size)
+            {{
+                {hsname}State *s = opaque;
+                (void)size;
+                {vcast}
+                hwaddr reg = R{rwidth}_OFF(addr);
+
+                uint32_t pc = ibex_get_current_pc();
+                trace_{dname}_io_write(s->ot_id, {larg}(uint32_t)addr,
+                                       {dpad}{rnm}(reg), val{rwidth}, pc);
+            '''
+        else:
+            if rwidth < 64:
+                vdef = f'uint{rwidth}_t val{rwidth};'
+            else:
+                vdef = ''
+            code = f'''
+            static uint64_t {dname}_regs_read(void *opaque, hwaddr addr,
+                                       {dpad}unsigned size)
+            {{
+                {hsname}State *s = opaque;
+                (void)size;
+                {vdef}
+
+                hwaddr reg = R{rwidth}_OFF(addr);
+            '''
+        print(redent(code), file=tfp)
+        lines = []
+        lines.append('    switch (reg) {')
+        bitfield = (1 << rwidth) - 1
+        if not write:
+            for rname in sorted(reg_names, key=lambda r: nregs[r].address):
+                lines.append(f'case R_{rname}:')
+            lines.append(f'    {vnm} = {sregs}[reg];')
+            lines.append('    break;')
+        else:
+            for rname in sorted(reg_names, key=lambda r: nregs[r].address):
+                lines.append(f'case R_{rname}:')
+                rbm, racc = reg_defs[rname]
+                if bitfield & rbm:
+                    lines.append(f'    {vnm} &= R_{rname}_WMASK;')
+                if racc in (AutoAccess.RW1C, AutoAccess.R0W1C):
+                    lines.append(f'    {sregs}[reg] &= ~{vnm}; '
+                                 f'/* {racc.upper()} */')
+                elif racc == AutoAccess.RW0C:
+                    lines.append(f'    {sregs}[reg] &= {vnm}; /* RW0C */')
+                elif racc == AutoAccess.RW1S:
+                    lines.append(f'    {sregs}[reg] |= {vnm}; /* RW1S */')
+                else:
+                    if racc == AutoAccess.UNDEF:
+                        self._log.warning(
+                            "Register '%s' has multiple access types which is "
+                            "not supported by this script, defaulting to RW.",
+                            rname)
+                        lines.append('    /* @todo handle multiple access type '
+                                     'bitfield */')
+                        lines.append(f'    {sregs}[reg] = {vnm};')
+                lines.append('    break;')
+        if noaccess_names:
+            for rname in sorted(noaccess_names, key=lambda r: nregs[r].address):
+                lines.append(f'case R_{rname}:')
+            a = 'R' if write else 'W'
+            lines.append(redent(f'''
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: %s: {a}/O register 0x%02" HWADDR_PRIx " (%s)\\n",
+                          __func__, s->ot_id, addr, {rnm}(reg));
+            ''', 4, True))
+            if not write:
+                lines.append('    val32 = 0;')
+            lines.append('    break;')
+        lines.append('default:')
+        lines.append(redent('''
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: %s: Bad offset 0x%" HWADDR_PRIx "\\n",
+                      __func__, s->ot_id, addr);
+        ''', 4, True))  # noqa: E501
+        if not write:
+            lines.append('    val32 = 0;')
+        lines.append('    break;')
+        lines.append('}')
+        print('\n    '.join(lines), file=tfp)
+        if write:
+            code = '};\n'
+        else:
+            rval = f'(uint64_t)val{rwidth}' if rwidth < 64 else 'val64'
+            code = f'''
+
+                uint32_t pc = ibex_get_current_pc();
+                trace_{dname}_io_read_out(s->ot_id, {larg}(uint32_t)addr,
+                                          {dpad}{rnm}(reg), val{rwidth}, pc);
+
+                return {rval};
+            }}
+            '''
+        print(redent(code), '', file=tfp)
+
+    def _generate_reg_wrappers(self, group: Optional[str],
+                               regs: list[AutoRegister], tfp: TextIO) -> None:
+        last = regs[-1]
+        sep = f'_{group}_' if group else '_'
+        lines = []
+        if last.count > 1:
+            lines.append(f'#define R_LAST{sep}REG '
+                         f'(R_{last.name}_{last.count-1})')
+        else:
+            lines.append(f'#define R_LAST{sep}REG (R_{last.name})')
+        lines.append(f'#define REGS{sep}COUNT (R_LAST{sep}REG + 1u)')
+        lines.append(f'#define REGS{sep}SIZE  (REGS{sep}COUNT * '
+                     f'sizeof(uint{self._regwidth}_t))')
+        if len(self._reg_groups) > 1:
+            base = self._group_offsets[group]
+            lines.append(f'#define REGS{sep}BASE 0x{base:0{self._nibcount}x}u')
+        lines.append(f'#define REG{sep}NAME(_reg_) \\')
+        lines.append(f'    ((((_reg_) < REGS{sep}COUNT) && '
+                     f'REG{sep}NAMES[_reg_]) ? REG{sep}NAMES[_reg_] : "?")')
+        lines.append('')
+        print('\n'.join(lines), file=tfp)
+
+    def _generate_regname_array(self, group: Optional[str],
+                                regs: list[AutoRegister], tfp: TextIO) -> None:
+        lines = []
+        reg_names = '_'.join(filter(None, ('REG', group, 'NAMES')))
+        reg_count = '_'.join(filter(None, ('REG', group, 'COUNT')))
+        lines.append(f'static const char *{reg_names}[{reg_count}] = {{')
+        lines.append('    /* clang-format off */')
+        for reg in regs:
+            if reg.count > 1:
+                for rpos in range(reg.count):
+                    lines.append(f'    REG_NAME_ENTRY({reg.name}_{rpos}),')
+            else:
+                lines.append(f'    REG_NAME_ENTRY({reg.name}),')
+        lines.append('    /* clang-format on */')
+        lines.append('};')
+        print('\n'.join(lines), file=tfp)
+
+    def _generate_mr_ops(self, tfp: TextIO) -> None:
+        for group in self._reg_groups:
+            if group:
+                dname = f'{self._devname}_{group.lower()}'
+            else:
+                dname = self._devname
+            code = f'''
+            static const MemoryRegionOps {dname}_ops = {{
+                .read = &{dname}_regs_read,
+                .write = &{dname}_regs_write,
+                .endianness = DEVICE_LITTLE_ENDIAN,
+                .impl = {{
+                    .min_access_size = 4u,
+                    .max_access_size = 4u,
+                }},
+            }};
+            '''
+            print(redent(code), file=tfp)
+
+    def _generate_props(self, tfp: TextIO) -> None:
+        dname = self._devname
+        hdname = dname.title().replace('_', '')
+        code = f'''
+        static Property {dname}_properties[] = {{
+            DEFINE_PROP_STRING(OT_COMMON_DEV_ID, {hdname}State, ot_id),
+            DEFINE_PROP_END_OF_LIST(),
+        }};
+        '''
+        print(redent(code), file=tfp)
+
+    def _generate_reset(self, tfp: TextIO, reset_type: str) -> None:
+        dname = self._devname
+        hdname = dname.title().replace('_', '')
+        uname = dname.upper()
+        regio = StringIO()
+        groups = self._build_reg_groups()
+        for group, regs in groups:
+            for reg in regs:
+                self._generate_reg_reset(group, reg, regio)
+        regcode = redent(regio.getvalue(), 12, strip_end=True).lstrip()
+
+        code = f'''
+        static void {dname}_reset_{reset_type}(Object *obj, ResetType type)
+        {{
+            {hdname}Class *c = {uname}_GET_CLASS(obj);
+            {hdname}State *s = {uname}(obj);
+
+            if (c->parent_phases.{reset_type}) {{
+                c->parent_phases.{reset_type}(obj, type);
+            }}
+        '''
+        indent = code.rsplit('\n', 1)[-1]
+        lines = [f'\n{indent}']
+        if reset_type == "enter":
+            for group in self._reg_groups:
+                regname = f'regs_{group.lower()}' if group else 'regs'
+                lines.append(f'    memset(s->{regname}, 0, '
+                             f'{regname.upper()}_SIZE);\n{indent}')
+        lines.append(f'\n{indent}    {regcode}\n{indent}')
+        lines.append('}\n')
+        code = f'{code}{"".join(lines)}'
+        print(redent(code), file=tfp)
+
+    def _generate_realize(self, tfp: TextIO) -> None:
+        dname = self._devname
+        hdname = dname.title().replace('_', '')
+        uname = dname.upper()
+        code = f'''
+        static void {dname}_realize(DeviceState *dev, Error **errp)
+        {{
+            {hdname}State *s = {uname}(dev);
+            (void)errp;
+        }}
+        '''
+        print(redent(code), file=tfp)
+
+    def _generate_init(self, tfp: TextIO) -> None:
+        dname = self._devname
+        hdname = dname.title().replace('_', '')
+        uname = dname.upper()
+        lines: list[str] = [
+            f'static void {dname}_init(Object *obj)',
+            '{'
+        ]
+        multi = len(self._reg_groups) > 1
+        lines.append(f'{hdname}State *s = {uname}(obj);')
+        lines.append('')
+        if not multi:
+            lines.append(
+                f'memory_region_init_io(&s->mmio, obj, &{dname}_regs_ops, s,')
+            lines.append(
+                f'                       TYPE_{uname}, REGS_SIZE);')
+        else:
+            # need to map up to the very last register
+            aperture = self._registers[-1].address + self._regwidth // 8
+            # apertures are defined as power-of-2
+            aperture = 1 << (aperture - 1).bit_length()
+            lines.append(f'#define {uname}_APERTURE 0x{aperture:x}u')
+            lines.append('')
+            lines.append(
+                f'memory_region_init(&s->mmio, obj, TYPE_{uname} "-regs",')
+            lines.append(
+                f'                   {uname}_APERTURE);')
+        lines.append('sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);')
+        lines.append('')
+        if multi:
+            for group in self._reg_groups:
+                lgroup = group.lower()
+                lines.append(
+                    f'memory_region_init_io(&s->mmio_{lgroup}, obj, '
+                    f'&{dname}_{lgroup}_ops, s,'
+                )
+                lines.append(
+                    f'                      TYPE_{uname} "-regs-{lgroup}", '
+                    f'REGS_{group}_SIZE);'
+                )
+                lines.append(
+                    f'memory_region_add_subregion(&s->mmio, REGS_{group}_BASE, '
+                    f'&s->mmio_{lgroup});'
+                )
+                lines.append('')
+        for group in self._reg_groups:
+            regname = f'regs_{group.lower()}' if group else 'regs'
+            lines.append(f's->{regname} = g_new0(uint{self._regwidth}_t, '
+                         f'{regname.upper()}_COUNT);')
+        lines.append('')
+        if self._irq_count:
+            lines.append('for (unsigned ix = 0; ix < NUM_IRQS; ix++) {')
+            lines.append('    ibex_sysbus_init_irq(obj, &s->irqs[ix]);')
+            lines.append('}')
+        if self._alert_count:
+            lines.append('')
+            lines.append('for (unsigned ix = 0; ix < NUM_ALERTS; ix++) {')
+            lines.append('    ibex_qdev_init_irq(obj, &s->alerts[ix], '
+                         'OT_DEVICE_ALERT);')
+            lines.append('}')
+        lines.append('}')
+        last_line = len(lines)
+        for lno, line in enumerate(lines, 1):
+            if lno in (1, 2, last_line) or line.startswith('#'):
+                print(line, file=tfp)
+            else:
+                print(f'    {line}'.rstrip(), file=tfp)
+        print(file=tfp)
+
+    def _generate_class_init(self, tfp: TextIO) -> None:
+        dname = self._devname
+        hdname = dname.title().replace('_', '')
+        uname = dname.upper()
+        resets = ', '.join((f'&{dname}_reset_{r}' if r in self._resets
+                            else 'NULL' for r in self.RESETS))
+        code = f'''
+        static void {dname}_class_init(ObjectClass *klass, void *data)
+        {{
+            DeviceClass *dc = DEVICE_CLASS(klass);
+            (void)data;
+
+            dc->realize = &{dname}_realize;
+            device_class_set_props(dc, {dname}_properties);
+            set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+
+            ResettableClass *rc = RESETTABLE_CLASS(klass);
+            {hdname}Class *mc = {uname}_CLASS(klass);
+            resettable_class_set_parent_phases(rc, {resets},
+                                               &mc->parent_phases);
+        }}
+        '''
+        print(redent(code), file=tfp)
+
+    def _generate_type(self, tfp: TextIO) -> None:
+        dname = self._devname
+        hdname = dname.title().replace('_', '')
+        uname = dname.upper()
+        code = f'''
+        static const TypeInfo {dname}_info = {{
+            .name = TYPE_{uname},
+            .parent = TYPE_SYS_BUS_DEVICE,
+            .instance_size = sizeof({hdname}State),
+            .instance_init = &{dname}_init,
+            .class_size = sizeof({hdname}Class),
+            .class_init = &{dname}_class_init,
+        }};
+
+        static void {dname}_register_types(void)
+        {{
+            type_register_static(&{dname}_info);
+        }}
+
+        type_init({dname}_register_types);
+        '''
+        print(redent(code), file=tfp)
+
+
+class BmTestAutoReg(AutoReg):
+    """Generator for Baremetal Test skeleton files."""
+
+    def generate_all(self, tfp: TextIO) -> None:
+        """Generate a QEMU device skeleton file based on the register map.
+
+           :param tfp: output file stream
+        """
+        self.generate_header(tfp)
+        self.generate_struct(tfp)
+        self.generate_register(tfp)
+
+    def generate_header(self, tfp: TextIO) -> None:
+        """Generate the skeleton for the header of a device driver.
+
+           :param tfp: output file stream
+        """
+        year = localtime().tm_year
+        code = f'''
+        // Copyright (c) {year} {self.copyright}
+        // Licensed under the Apache License, Version 2.0, see LICENSE for details.
+        // SPDX-License-Identifier: Apache-2.0
+
+        #![no_std]
+
+        use tock_registers::interfaces::{{ReadWriteable, Readable, Writeable}};
+        use tock_registers::registers::{{ReadOnly, ReadWrite, WriteOnly}};
+        use tock_registers::{{register_bitfields, register_structs}};
+        '''  # noqa: E501
+        # @todo ideally RW/RO/WO use should depend on the actual register
+        # definitions. This is not yet supported.
+        print(redent(code), file=tfp)
+
+    def generate_struct(self, tfp: TextIO) -> None:
+        """Generate the skeleton for the device state and class structs.
+
+           :param tfp: output file stream
+        """
+        dname = self._devname
+        hdname = dname.title().replace('_', '')
+        code = f'''
+        pub struct {hdname} {{
+            regs: &'static mut {hdname}Regs,
+        }}
+        '''
+        print(redent(code), file=tfp)
+
+    def _generate_registers(self, tfp: TextIO) -> None:
+        dname = self._devname
+        hdname = dname.title().replace('_', '')
+        print('register_structs! {', file=tfp)
+        print(f'    pub {hdname}Regs {{', file=tfp)
+        shared_fields: dict[str, tuple[list[AutoField], set[str]]] = {}
+        bitfields: dict[str, list[AutoField]] = {}
+        for reg in self._registers:
+            radix = reg.name.rsplit('_', 1)[0]
+            if reg.shared_fields:
+                if radix in shared_fields:
+                    raise RuntimeError(f"Redefinition of shared field for "
+                                       f"'{radix}'")
+                shared_fields[radix] = (reg.fields, {reg.name})
+                bitfields[radix] = reg.fields
+            elif radix in shared_fields:
+                shared_fields[radix][1].add(reg.name)
+            else:
+                flds = reg.fields
+                if flds and (len(flds) > 1 or flds[0].width != self._regwidth):
+                    bitfields[reg.name] = reg.fields
+        reg = None
+        address = 0
+        rsvcnt = 0
+        nibcount = self._nibcount
+        for reg in self._registers:
+            if reg.address > address:
+                rsvcnt += 1
+                self._generate_reserved_register(address, f'_reserved{rsvcnt}',
+                                                 nibcount, tfp)
+            self._generate_register(reg, shared_fields, nibcount, reg.count,
+                                    tfp)
+            address = reg.address + (reg.count * self._regwidth) // 8
+        print(f'        (0x{address:0{nibcount}x} => @END),', file=tfp)
+        print('    }\n}\n', file=tfp)
+        print(f'register_bitfields! [u{self._regwidth},', file=tfp)
+        for name, fields in bitfields.items():
+            print(f'    {name} [', file=tfp)
+            for fld in fields:
+                print(f'        {fld.name} OFFSET({fld.offset}) '
+                      f'NUMBITS({fld.width}) [],', file=tfp)
+            print('    ],', file=tfp)
+        print('];\n', file=tfp)
+
+    def _generate_register(self, reg: AutoRegister,
+                           shfields: dict[str, tuple[list[AutoField],
+                                                     set[str]]],
+                           nibcount: int, repcount: int, tfp: TextIO) -> None:
+        regtype = {
+            AutoAccess.RO: 'ReadOnly',
+            AutoAccess.WO: 'WriteOnly',
+        }.get(reg.access, 'ReadWrite')
+        regdesc = ''
+        radix = reg.name.rsplit('_', 1)[0]
+        if radix in shfields and reg.name in shfields[radix][1]:
+            fields = shfields[radix][0]
+            regdescname = radix
+        else:
+            fields = reg.fields
+            regdescname = reg.name
+        if fields and (len(fields) > 1 or fields[0].width != self._regwidth):
+            regdesc = f', {regdescname.upper()}::Register'
+        if repcount > 1:
+            print(f'        (0x{reg.address:0{nibcount}x} => '
+                  f'{reg.name.lower()}: '
+                  f'[{regtype}<u{self._regwidth}{regdesc}>; {repcount}]),',
+                  file=tfp)
+        else:
+            print(f'        (0x{reg.address:0{nibcount}x} => '
+                  f'{reg.name.lower()}: '
+                  f'{regtype}<u{self._regwidth}{regdesc}>),', file=tfp)
+
+    def _generate_reserved_register(self, address: int, name: str,
+                                    nibcount: int, tfp: TextIO):
+        print(f'        (0x{address:0{nibcount}x} => {name},', file=tfp)
+
+
+def main():
+    """Main routine"""
+    debug = True
+    mod = sys.modules[__name__]
+    desc = mod.__doc__.split('.', 1)[0].strip()
+    argparser = ArgumentParser(description=f'{desc}.')
+    base = 'AutoReg'
+    autoregs = {
+        name.removesuffix(base).lower(): tit
+        for name, tit in [(m, getattr(mod, m)) for m in dir(mod)]
+        if isinstance(tit, type) and issubclass(tit, AutoReg) and name != base
+    }
+    default_outkind = 'qemu'
+    outkinds = sorted(autoregs, key=lambda n: '' if n == default_outkind else n)
+    assert len(outkinds) > 0
+    generators = sorted(set(flatten([areg.generators
+                                     for areg in autoregs.values()])))
+    try:
+        files = argparser.add_argument_group(title='Files')
+        files.add_argument('-c', '--config', type=FileType('rt'),
+                           metavar='HJSON', required=True,
+                           help='input HJSON definition file')
+        files.add_argument('-o', '--output', type=FileType('wt'),
+                           metavar='FILE',
+                           help='output source file')
+        params = argparser.add_argument_group(title='Parameters')
+        files.add_argument('-C', '--copyright',
+                           help='define copyright string')
+        params.add_argument('-g', '--generate', action='append',
+                            choices=generators,
+                            help='what to generate')
+        params.add_argument('-k', '--out-kind', choices=outkinds,
+                            default=outkinds[0],
+                            help=f'output file format '
+                                 f'(default: {outkinds[0]})')
+        params.add_argument('-n', '--name', help='device name')
+        params.add_argument('-p', '--ignore', metavar='PREFIX',
+                            help='ignore register/fields starting with prefix')
+        params.add_argument('-S', '--segment', metavar='REGNAME:SEGMENT',
+                            action='append', default=[],
+                            help='Creage a segment on specified register '
+                                 '(may be repeated)')
+        params.add_argument('-r', '--reset', action='append',
+                            choices=AutoReg.RESETS,
+                            help='generate reset code')
+        params.add_argument('-w', '--win-limit', type=HexInt.parse,
+                            metavar='ITEMS', default=AutoReg.WINDOW_LIMIT,
+                            help=f'Max window size, discard larger '
+                                 f'(default: {AutoReg.WINDOW_LIMIT} items)')
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+
+        args = argparser.parse_args()
+        debug = args.debug
+
+        if _HJSON_ERROR:
+            argparser.error(f'Missing HJSON module: {_HJSON_ERROR}')
+
+        log = configure_loggers(args.verbose, 'autoreg')[0]
+
+        reggen = autoregs[args.out_kind]
+        name = args.name or f'ot_{splitext(basename(args.config.name))[0]}'
+        areg = reggen(name, args.ignore, args.reset)
+        if args.copyright:
+            areg.copyright = args.copyright
+        areg.load(args.config, args.win_limit)
+        if args.generate:
+            areg.segment(args.segment)
+            for gen in args.generate:
+                generate = getattr(areg, f'generate_{gen}', None)
+                if not generate:
+                    argparser.error(f'{gen} is not supported for '
+                                    f'{args.out_kind}')
+                generate(args.output or sys.stdout)
+        else:
+            log.warning('No generation requested')
+
+    except ArgError as exc:
+        argparser.error(str(exc))
+    except (IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(''.join(format_exception(exc, chain=False)),
+                  file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/autotop.py b/scripts/opentitan/autotop.py
new file mode 100755
index 0000000000000..67a6a8d2683d0
--- /dev/null
+++ b/scripts/opentitan/autotop.py
@@ -0,0 +1,551 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Generate machine definitions for OpenTitan top.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, FileType
+from logging import getLogger
+from os import listdir
+from os.path import (abspath, basename, commonprefix, dirname, isdir, isfile,
+                     join as joinpath)
+from traceback import format_exception
+from typing import Any, NamedTuple, TextIO
+import re
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(abspath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+# ruff: noqa: E402
+from ot.util.arg import ArgError
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt, camel_to_snake_uppercase, classproperty, redent
+
+try:
+    _HJSON_ERROR = None
+    from hjson import load as hjload
+except ImportError as hjson_exc:
+    _HJSON_ERROR = str(hjson_exc)
+
+
+class QEMUDevice(NamedTuple):
+    """A device slot."""
+
+    base: HexInt
+    size: HexInt
+    aspc: str
+
+
+class QEMUSignal(NamedTuple):
+    """Interrupt or Alert"""
+
+    name: str
+    index: int
+
+
+class AutoTop:
+    """Helper class to generate QEMU machine definition from Top definitions.
+    """
+
+    SV_ENUM_CRE = re.compile(
+        r'(?s)typedef\s+enum\s+([\w\s]*){([^\}]*)}\s+(\w+);')
+    SV_ENUM_ITEM_CRE = re.compile(r'(?s)([\w\d]+)(?:\s+=\s+(\d+))?,')
+    SV_PARAM_CRE = re.compile(r"parameter\sint\sunsigned\s([A-Z0-9_]+)\s"
+                              r"=\s\d+'h([0-9a-fA-F]+);")
+    DEVICE_MAP = {
+        'OTP_MACRO': 'OTP_BACKEND',
+        'RV_CORE_IBEX': 'IBEX_WRAPPER',
+        'RV_PLIC': 'PLIC',
+        'RV_TIMER': 'TIMER',
+    }
+    """RTL-to-QEMU renamed devices."""
+
+    def __init__(self, topname):
+        self._log = getLogger('autotop')
+        self._topname = topname
+        self._ases: list[str] = []
+        self._devices: dict[str, dict[str, QEMUDevice]] = {}
+        self._interrupts: dict[str, list[tuple[str, int]]] = {}
+        self._alerts: dict[str, list[tuple[str, int]]] = {}
+        self._pinmux: dict[str, list[str]] = {}
+        self._mbox_indices: dict[str, int] = {}
+
+    def load(self, ot_dir: str) -> None:
+        """Load configuration files.
+
+           :param: OpenTitan top directory
+        """
+        ot_dir = abspath(ot_dir)
+        top = f'top_{self._topname}'
+        topdir = joinpath(ot_dir, f'hw/{top}')
+        if not isdir(topdir):
+            raise ArgError(f"No such top '{self._topname}'")
+        topcfg = joinpath(topdir, 'data/autogen', f'{top}.gen.hjson')
+        if not isfile(topcfg):
+            raise ArgError(f"No config file for top '{self._topname}'")
+        self._load_devices(topdir)
+        with open(topcfg, 'rt') as hfp:
+            hjson = hjload(hfp, object_pairs_hook=dict)
+        self._load_all_interrupts(hjson)
+        self._load_all_alerts(hjson)
+        self._load_pinmux(hjson)
+
+    @classmethod
+    def device_name(cls, name: str, discard_aon: bool = False) -> str:
+        """Generate the devices name.
+
+           :param name: original name
+           :param discard_aon: discard AON qualifier
+        """
+        pname = name.upper()
+        if discard_aon:
+            pname = pname.replace('_AON', '')
+        return cls.DEVICE_MAP.get(pname, pname)
+
+    @classproperty
+    def outkinds(cls) -> list[str]:
+        """Report which generation output formats are supported.
+        """
+        # pylint: disable=no-self-argument
+        prefix = 'generate_'
+        return [f.removeprefix(prefix) for f in dir(cls)
+                if f.startswith(prefix)]
+
+    def generate_qemu(self, prefix: str, tfp: TextIO) -> None:
+        """Generate a QEMU template file or machine definition.
+
+           :param prefix: prefix for C definition
+           :param tfp: output file stream
+        """
+        lprefix = prefix.lower()
+        self._generate_qemu_dev_enum(prefix, tfp)
+        self._generate_qemu_pinmux(prefix, tfp)
+        print(f'static const IbexDeviceDef {lprefix}_devices[] = {{', file=tfp)
+        print('/* clang-format off */', file=tfp)
+        for devname in sorted(self._devices, key=self._device_address):
+            self._generate_qemu_devices(prefix, devname, tfp)
+        print('/* clang-format on */', file=tfp)
+        print('};', file=tfp)
+
+    def generate_bmtest(self, _: str, tfp: TextIO) -> None:
+        """Generate a Rust template file for machine definition.
+
+           :param tfp: output file stream
+        """
+        self._generate_bmtest_base_addresses(tfp)
+        self._generate_bmtest_interrupts(tfp)
+        self._generate_bmtest_alerts(tfp)
+        self._generate_bmtest_pinmux(tfp)
+
+    def _load_devices(self, topdir: str) -> None:
+        iptopdir = f'{topdir}/ip'
+        for ipdir in listdir(iptopdir):
+            ippath = joinpath(iptopdir, ipdir)
+            if not isdir(ippath) or not ipdir.startswith('xbar_'):
+                continue
+            gendir = joinpath(ippath, 'data/autogen')
+            if not isdir(gendir):
+                continue
+            for genfile in listdir(gendir):
+                if (not genfile.endswith('.gen.hjson') or
+                   not genfile.startswith('xbar_')):
+                    continue
+                xbarcfg = joinpath(gendir, genfile)
+                if not isfile(xbarcfg):
+                    continue
+                self._load_xbar(xbarcfg)
+
+    def _load_xbar(self, xbarcfg: str) -> None:
+        """Load a Top xbar configuration file.
+
+           :param xbarcfg: path to the HJSON to load
+        """
+        with open(xbarcfg, 'rt') as hfp:
+            hjson = hjload(hfp, object_pairs_hook=dict)
+        self._ases = hjson.get('addr_spaces')
+        if not self._ases:
+            raise ValueError('No address space defined')
+        if len(self._ases) > 1:
+            raise NotImplementedError('Multiple address spaces')
+        aspc = self._ases[0]
+        xbar = basename(xbarcfg).split('.')[0].split('_', 1)[-1]
+        self._log.debug('Address space for %s: %s', xbar, ', '.join(self._ases))
+        for node in hjson.get('nodes', []):
+            if node['type'] != 'device':
+                continue
+            if node['xbar']:
+                continue
+            parts = node['name'].split('.', 1)
+            name = parts[0]
+            subname = parts[1] if len(parts) > 1 else 'regs'
+            if subname in ('core', 'jtag', 'dmi', 'prim', 'cfg'):
+                subname = 'regs'
+            addr_ranges = node.get('addr_range')
+            if not addr_ranges:
+                continue
+            self._log.debug('loading device %s (%s)', name, subname)
+            for addr_range in addr_ranges:
+                base_addrs = addr_range.get('base_addrs', {})
+                if len(base_addrs) != 1:
+                    raise NotImplementedError('Multiple base addresses')
+                addr = HexInt(base_addrs[aspc], 16)
+                size = HexInt(addr_range.get('size_byte', 0), 16)
+                dev = QEMUDevice(addr, size, aspc)
+                uname = self.device_name(name, True)
+                if uname not in self._devices:
+                    self._devices[uname] = {}
+                self._devices[uname][subname] = dev
+
+    def _load_all_interrupts(self, hjson: dict[str, Any]) -> None:
+        interrupts = self._load_interrupts(hjson.get('interrupt', []))
+        irq_num = 0
+        for dev, name in interrupts:
+            if dev not in self._interrupts:
+                self._interrupts[dev] = []
+            irq_num += 1  # IRQ #0 is not an IRQ
+            self._interrupts[dev].append(QEMUSignal(name, irq_num))
+        self._log.info('found %d interrupts', irq_num)
+
+    def _load_interrupts(self, interrupts: dict[str, Any]) \
+            -> list[tuple[str, str]]:
+        int_list: list[tuple[str, str]] = []
+        for interrupt in interrupts:
+            dev = self.device_name(interrupt['module_name'], True)
+            width = interrupt.get('width', 1)
+            prefix = f'{dev.lower()}_'
+            name = interrupt['name'].lower().removeprefix(prefix)
+            if width == 1:
+                int_list.append((dev, name))
+            else:
+                int_list.extend((dev, f'{name}{pos}') for pos in range(width))
+        return int_list
+
+    def _load_all_alerts(self, hjson: dict[str, Any]) -> None:
+        alerts: list[tuple[str, str]] = []
+        alerts.extend(self._load_alerts('', hjson.get('alert', [])))
+        for cat, cat_alerts in hjson.get('incoming_alert', {}).items():
+            alerts.extend(self._load_alerts(f'incoming_{cat}', cat_alerts))
+        alert_num = 0
+        for dev, name in alerts:
+            if dev not in self._alerts:
+                self._alerts[dev] = []
+            self._alerts[dev].append(QEMUSignal(name, alert_num))
+            alert_num += 1
+        self._log.info('found %d alerts', alert_num)
+
+    def _load_alerts(self, cat: str, alerts: dict[str, Any]) \
+            -> None:
+        alert_list: list[tuple[str, str]] = []
+        if cat:
+            cat = f'{cat}_'.upper()
+        for alert in alerts:
+            dev = self.device_name(alert['module_name'], True)
+            prefix = f'{dev.lower()}_'
+            lname = alert['name'].lower().removeprefix(prefix)
+            alert_list.append((f'{cat}{dev}', lname))
+        return alert_list
+
+    def _load_pinmux(self, hjson: dict[str, Any]) -> None:
+        pinmux = hjson.get('pinmux', {})
+        ios = pinmux.get('ios', [])
+        pinmap: dict[str, list[str]] = {
+            'dio': [],
+            'mio_in': [],
+            'mio_out': [],
+            'mio_inout': [],
+        }
+        for ioe in ios:
+            name = ioe['name']
+            cnx = ioe['connection']
+            idx = ioe['idx']
+            type_ = ioe['type']
+            iname = f'{name}{idx}' if idx >= 0 else name
+            if cnx == 'direct':
+                pinmap['dio'].append(iname)
+            elif cnx == 'muxed':
+                if type_ == 'input':
+                    pinmap['mio_in'].append(iname)
+                elif type_ == 'output':
+                    pinmap['mio_out'].append(iname)
+                elif type_ == 'inout':
+                    pinmap['mio_inout'].append(iname)
+                else:
+                    self._log.error('Unknown MIO type %s', type_)
+            elif cnx == 'manual':
+                # not yet implemented
+                self._log.warning('Unmanaged connection type %s', cnx)
+            else:
+                self._log.error('Unknown connection type %s', cnx)
+        self._pinmux = pinmap
+
+    def _device_address(self, dev: str) -> int:
+        try:
+            return self._devices[dev]['regs'].base
+        except KeyError:
+            try:
+                return self._devices[dev]['ctn'].base
+            except KeyError:
+                return -1
+
+    def _get_mbox_index(self, udev: str) -> int:
+        if udev not in self._mbox_indices:
+            self._mbox_indices[udev] = len(self._mbox_indices)
+        return self._mbox_indices[udev]
+
+    def _generate_qemu_dev_enum(self, prefix: str, tfp: TextIO) -> None:
+        lines = []
+        uprefix = prefix.upper()
+        tprefix = prefix.title().replace('_', '')
+        print(f'enum {tprefix}Device {{', file=tfp)
+        for dev in sorted(self._devices):
+            lines.append(f'{uprefix}_DEV_{dev}')
+        code = redent(',\n'.join(lines), 4)
+        print(code, file=tfp)
+        print('}\n', file=tfp)
+
+    def _generate_qemu_pinmux(self, prefix: str, tfp: TextIO) -> None:
+        tprefix = prefix.title().replace('_', '')
+        for ioname, pinmux in self._pinmux.items():
+            lines = []
+            u_ioname = ioname.upper()
+            uc_ioname = ioname.title().replace('_', '')
+            print(f'enum {tprefix}Pinmux{uc_ioname} {{', file=tfp)
+            max_val = 0
+            for val, ion in enumerate(pinmux):
+                us_ion = camel_to_snake_uppercase(ion)
+                lines.append(f'{u_ioname}_{us_ion}, /* {val} */')
+                max_val = max(val, max_val)
+            lines.append(f'{u_ioname}_COUNT, /* {max_val + 1} */')
+            code = redent('\n'.join(lines), 4)
+            print(code, file=tfp)
+            print('};\n', file=tfp)
+
+    def _generate_qemu_devices(self, prefix: str, dev: str, tfp: TextIO) \
+            -> None:
+        lines: list[str] = []
+        uprefix = prefix.upper()
+        irq_defs = self._generate_qemu_irq_defs(uprefix, dev)
+        alert_defs = self._generate_qemu_alert_defs(uprefix, dev)
+        mmap_defs = self._generate_qemu_mmap_defs(dev)
+        if dev not in self._devices:
+            self._log.warning('%s not in devices', dev)
+        lines.append(f'[{uprefix}_DEV_{dev}] = {{')
+        mmo = re.match(r'(MBX(?:_[A-Z]+)?)\d*$', dev)
+        if mmo:
+            # mailboxes are defined with a macro
+            mbxidx = self._get_mbox_index(dev)
+            addr = self._devices[dev]['regs'].base
+            irq = self._interrupts[dev][0]
+            try:
+                alert = self._alerts[dev][0]
+            except KeyError:
+                # temporary
+                alert = QEMUSignal("missing", -1)
+            mbox_map = {'MBX_JTAG': 'DEBUG'}
+            if mmo.group(1) not in mbox_map:
+                lines.append(f'    {uprefix}_DEV_MBX({mbxidx}, {addr}u, '
+                             f'"ot-mbx.sram", {irq.index}, {alert.index}),')
+            else:
+                mmem = mbox_map[dev]
+                spacer = ' ' * len(f'    {uprefix}_DEV_MBX_DUAL(')
+                lines.append(f'    {uprefix}_DEV_MBX_DUAL({mbxidx}, {addr}u, '
+                             f'"ot-mbx.sram", {irq.index}, {alert.index},')
+                lines.append(f'{spacer}'
+                             f'{mmem}_MEMORY({uprefix}_{mmem}_{dev}_ADDR))')
+        else:
+            devbase = re.sub(r'\d+$', '', dev)
+            lines.append(f'    .type = TYPE_OT_{devbase},')
+            if mmap_defs:
+                lines.append('    .memmap = MEMMAPENTRIES(')
+                lines.append(redent(',\n'.join(mmap_defs), 8))
+                lines.append('    ),')
+            if irq_defs or alert_defs:
+                defs = []
+                defs.extend(irq_defs)
+                defs.extend(alert_defs)
+                lines.append('    .gpio = IBEXGPIOCONNDEFS(')
+                lines.append(redent(',\n'.join(defs), 8))
+                lines.append('    ),')
+        lines.append('},')
+        code = redent('\n'.join(lines), 4)
+        print(code, file=tfp)
+
+    def _generate_qemu_mmap_defs(self, device: str) -> list[str]:
+        # sorting memory range the weird way (hack ahead)
+        # we want the IBEX bus to be seen first (vs. debug or external buses)
+        # and appear in the logical address order
+        def _sort_mems(dev):
+            bus, addr = dev.base >> 28, dev.base & ~(0xf << 28)
+            if dev.aspc == 'hart':
+                return ('', -bus, addr)
+            return (dev.aspc, -bus, addr)
+
+        mmaps = []
+        for dev in sorted(self._devices.get(device, {}).values(),
+                          key=_sort_mems):
+            width = '08' if dev.aspc == 'hart' else ''
+            mmaps.append(f'{{ .base = 0x{dev.base:{width}x}u }}')
+        return mmaps
+
+    def _generate_qemu_alert_defs(self, prefix: str, dev: str) -> list[str]:
+        alerts = []
+        for pos, alert in enumerate(self._alerts.get(dev, [])):
+            alerts.append(f'{prefix}_GPIO_ALERT({pos}, {alert.index})')
+        return alerts
+
+    def _generate_qemu_irq_defs(self, prefix: str, dev: str) -> list[str]:
+        irqs = []
+        for pos, irq in enumerate(self._interrupts.get(dev, [])):
+            irqs.append(f'{prefix}_GPIO_SYSBUS_IRQ({pos}, PLIC, '
+                        f'{irq.index})')
+        return irqs
+
+    def _generate_bmtest_base_addresses(self, tfp):
+        utop = self._topname.upper()
+        print('pub mod base_addresses {', file=tfp)
+        for dev in sorted(self._devices, key=self._device_address):
+            devices = self._devices[dev]
+            devcount = len(devices)
+            dev = re.sub('^RV_', '', dev)
+            dev = re.sub(f'_{utop}$', '', dev)
+            dev = re.sub(f'^{utop}_', '', dev)
+            for name, slot in devices.items():
+                suffix = ''
+                if devcount > 1:
+                    if name in ('dbg', 'soc'):
+                        continue
+                    mbxmo = re.match(r'^MBX(.*)', dev)
+                    if mbxmo:
+                        dev = f'MBXHOST{mbxmo.group(1)}'
+                        suffix = ''
+                    else:
+                        suffix = {
+                            'regs': '_CTRL',
+                            'mem': '_MEM',
+                            'ram': '_MEM',
+                            'rom': '_MEM',
+                        }.get(name) or f'_{name.upper()}'
+                elif dev.startswith('SOC_PROXY'):
+                    dev = 'CTN'
+                print(f'    pub const {dev}{suffix}: usize = {slot.base:#_x};',
+                      file=tfp)
+        print('}\n', file=tfp)
+
+    def _generate_bmtest_interrupts(self, tfp):
+        irqs: dict[str, int] = {}
+        if not self._interrupts:
+            return
+        for dev, dev_irqs in self._interrupts.items():
+            for irq in dev_irqs:
+                irqname = irq.name.upper()
+                prefix = commonprefix((irqname, dev))
+                if prefix:
+                    irqname = irqname.removeprefix(prefix).lstrip('_')
+                irqs[f'{dev}_{irqname}'] = irq.index
+        print('pub mod irq_num {', file=tfp)
+        max_val = 0
+        for name, val in sorted(irqs.items(), key=lambda irq: irq[1]):
+            print(f'    pub const {name}: usize = {val};', file=tfp)
+            max_val = max(val, max_val)
+        print(f'    pub const COUNT: usize = {max_val + 1};', file=tfp)
+        print('}\n', file=tfp)
+
+    def _generate_bmtest_alerts(self, tfp) -> None:
+        alerts: dict[str, int] = {}
+        if not self._alerts:
+            return
+        for dev, dev_alerts in self._alerts.items():
+            for alert in dev_alerts:
+                alerts[f'{dev}_{alert.name.upper()}'] = alert.index
+        print('pub mod alert_num {', file=tfp)
+        max_val = 0
+        for name, val in sorted(alerts.items(), key=lambda alert: alert[1]):
+            print(f'    pub const {name}: usize = {val};', file=tfp)
+            max_val = max(val, max_val)
+        print(f'    pub const COUNT: usize = {max_val + 1};', file=tfp)
+        print('}\n', file=tfp)
+
+    def _generate_bmtest_pinmux(self, tfp) -> None:
+        for ioname, pinmux in self._pinmux.items():
+            if not pinmux:
+                continue
+            print(f'pub mod pinmux_{ioname} {{', file=tfp)
+            max_val = 0
+            for val, ion in enumerate(pinmux):
+                us_ion = camel_to_snake_uppercase(ion)
+                print(f'    pub const {us_ion}: usize = {val};', file=tfp)
+                max_val = max(val, max_val)
+            print(f'    pub const COUNT: usize = {max_val + 1};', file=tfp)
+            print('}\n', file=tfp)
+
+
+def main():
+    """Main routine."""
+    debug = True
+    desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+    argparser = ArgumentParser(description=f'{desc}.')
+    try:
+        default_outkind = 'qemu'
+        outkinds = sorted(AutoTop.outkinds,
+                          key=lambda n: '' if n == default_outkind else n)
+        assert len(outkinds) > 0
+        top = argparser.add_argument_group(title='Top')
+        top.add_argument('opentitan', nargs='?', metavar='OTDIR',
+                         help='OpenTitan root directory')
+        top.add_argument('-T', '--top', required=True,
+                         help='OpenTitan top name')
+        files = argparser.add_argument_group(title='Files')
+        files.add_argument('-o', '--output', type=FileType('wt'),
+                           metavar='FILE',
+                           help='output file name')
+        files.add_argument('-p', '--prefix', default='ot_dj_soc',
+                           help='constant prefix (default: ot_dj_soc)')
+        files.add_argument('-k', '--out-kind', choices=outkinds,
+                           default=outkinds[0],
+                           help=f'output file format '
+                                f'(default: {outkinds[0]})')
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+
+        args = argparser.parse_args()
+        debug = args.debug
+
+        if _HJSON_ERROR:
+            argparser.error(f'Missing HJSON module: {_HJSON_ERROR}')
+
+        configure_loggers(args.verbose, 'autotop')
+
+        ot_dir = args.opentitan
+        if not args.opentitan:
+            argparser.error('OTDIR is required is no top file is specified')
+        if not isdir(ot_dir):
+            argparser.error('Invalid OpenTitan root directory')
+        atop = AutoTop(args.top)
+        atop.load(ot_dir)
+        getattr(atop, f'generate_{args.out_kind}')(args.prefix,
+                                                   args.output or sys.stdout)
+
+    except ArgError as exc:
+        argparser.error(str(exc))
+    except (IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(''.join(format_exception(exc, chain=False)),
+                  file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/cfggen.py b/scripts/opentitan/cfggen.py
new file mode 100755
index 0000000000000..498d464bc0e94
--- /dev/null
+++ b/scripts/opentitan/cfggen.py
@@ -0,0 +1,704 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2024 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""OpenTitan QEMU configuration file generator.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser
+from configparser import ConfigParser
+from logging import getLogger
+from os.path import (abspath, basename, dirname, isdir, isfile,
+                     join as joinpath, normpath)
+from traceback import format_exc
+from typing import NamedTuple, Optional, TextIO
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+try:
+    _HJSON_ERROR = None
+    from hjson import load as hjload
+except ImportError as hjson_exc:
+    _HJSON_ERROR = str(hjson_exc)
+    def hjload(*_, **__):  # noqa: E301
+        """dummy func if HJSON module is not available"""
+        return {}
+
+from ot.lc_ctrl.const import LcCtrlConstants
+from ot.otp.const import OtpConstants
+from ot.otp.secret import OtpSecretConstants
+from ot.top import OpenTitanTop
+from ot.util.arg import ArgError
+from ot.util.log import configure_loggers
+from ot.util.misc import alphanum_key, retrieve_git_version, to_bool
+
+
+OtParamRegex = str
+"""Definition of a parameter to seek and how to shorten it."""
+
+
+class OtClock(NamedTuple):
+    """Clock definition."""
+
+    name: str
+    """Clock signal name."""
+
+    frequency: int
+    """Clock frequency in Hz."""
+
+    aon: bool
+    """Whether the clock is always on."""
+
+    ref: bool
+    """Whether the clock is a reference clock."""
+
+
+class OtDerivedClock(NamedTuple):
+    """Clock derived from a top level clock definition."""
+
+    name: str
+    """Clock signal name."""
+
+    source: str
+    """Clock source signal name."""
+
+    div: int
+    """Divider."""
+
+
+class OtClockGroup(NamedTuple):
+    """Clock logicial group definition."""
+
+    name: str
+    """Group name."""
+
+    sources: list[str]
+    """Clock source signal names."""
+
+    sw_cg: bool
+    """Whether clock group can be managed by SW."""
+
+    hint: bool
+    """Whether clock group can be hinted by SW."""
+
+
+class OtConfiguration:
+    """QEMU configuration file generator.
+
+       This may seem complicated and duplicated, since it is. This script tries
+       to deal with the many way to define constants that have been used in many
+       implementations of OpenTitan and that have changed over time. YMMV.
+    """
+
+    MODULES = {
+        'rom_ctrl': (True, r'RndCnstScr(.*)'),
+        'otp_ctrl': (False, r'RndCnst(.*)Init'),
+        'lc_ctrl': (False, r'RndCnstLcKeymgrDiv(.*)'),
+        'keymgr':  (False, r'RndCnst((?:.*)Seed)',
+                           # The CDI keymgr seed does not match 'RndCnst.*Seed'
+                           r'RndCnst(Cdi)'),
+        'keymgr_dpe': (False, r'RndCnst((?:.*)Seed)'),
+    }
+    """Secrets to extract from OT modules, defined as regexes where the first
+       capturing group of the first matching string in the module defines the
+       secret name to store.
+    """
+
+    TRANSLATIONS = {
+        'keymgr': {'cdi': 'cdi_seed'}
+    }
+    """Secret name translations from OT definitions to QEMU property names."""
+
+    def __init__(self):
+        self._log = getLogger('cfggen.cfg')
+        self._otpconst = OtpConstants()
+        self._lcconst = LcCtrlConstants()
+        self._constants: dict[str, dict[Optional[int], dict[str, str]]] = {}
+        self._top_clocks: dict[str, OtClock] = {}
+        self._sub_clocks: dict[str, OtDerivedClock] = {}
+        self._clock_groups: dict[str, OtClockGroup] = {}
+        self._mod_clocks: dict[str, list[str]] = {}
+        self._top_name: Optional[str] = None
+        self._git_version: Optional[str] = None
+        self._exclusions: dict[str, set[str]] = {}
+
+    @property
+    def top_name(self) -> Optional[str]:
+        """Return the name of the top as defined in a configuration file."""
+        return self._top_name
+
+    def load_config(self, toppath: str) -> None:
+        """Load data from HJSON configuration file."""
+        assert not _HJSON_ERROR
+        with open(toppath, 'rt') as tfp:
+            cfg = hjload(tfp, object_pairs_hook=dict)
+        self._top_name = cfg.get('name')
+        topbase = basename(toppath)
+
+        self._git_version = retrieve_git_version(toppath)
+
+        for module in cfg.get('module') or []:
+            modtype = module.get('type')
+            moddefs = self.MODULES.get(modtype)
+            if not moddefs:
+                continue
+            multi, regexes = moddefs[0], moddefs[1:]
+            consts = {}
+            OtpSecretConstants.load_values(module, consts, multi, *regexes)
+            if not consts:
+                continue
+            for cname, tname in self.TRANSLATIONS.get(modtype, {}).items():
+                if cname in consts:
+                    consts[tname] = consts.pop(cname)
+            self._log.debug('Constants for %s loaded from %s', modtype, topbase)
+            exist = modtype in self._constants
+            if multi:
+                if not exist:
+                    self._constants[modtype] = consts
+                else:
+                    self._constants[modtype].update(consts)
+            else:
+                if exist:
+                    raise ValueError(f'Redefinition of {modtype}')
+                self._constants[modtype] = {None: consts}
+
+        clocks = cfg.get('clocks', {})
+        for clock in clocks.get('srcs', []):
+            name = clock['name']
+            aon = to_bool(clock['aon'], False)
+            ref = to_bool(clock['ref'], False)
+            freq = int(clock['freq'])
+            self._top_clocks[name] = OtClock(name, freq, aon, ref)
+        for clock in clocks.get('derived_srcs', []):
+            name = clock['name']
+            src = clock['src']
+            aon = to_bool(clock['aon'], False)
+            freq = int(clock['freq'])
+            div = int(clock['div'])
+            src_clock = self._top_clocks.get(src)
+            if not src_clock:
+                raise ValueError(f'Invalid top clock {src} '
+                                 f'referenced from {name}')
+            if src_clock.frequency // div != freq:
+                raise ValueError(f'Incoherent derived clock {name} frequency: '
+                                 f'{src_clock.frequency}/{div} != {freq}')
+            if aon and not src_clock.aon:
+                raise ValueError(f'Incoherent derived clock {name} AON')
+            self._sub_clocks[name] = OtDerivedClock(name, src, div)
+        clock_names = set(self._top_clocks.keys())
+        clock_names.update(set(self._sub_clocks.keys()))
+        for group in clocks.get('groups', []):
+            ext = group['src'] == 'ext'
+            if ext:
+                continue
+            name = group['name']
+            hint = group['sw_cg'] == 'hint'
+            sw_cg = not hint and to_bool(group['sw_cg'], False)
+            clk_srcs = []
+            for clk_name, clk_src in group.get('clocks', {}).items():
+                if not hint:
+                    exp_name = f'clk_{clk_src}_{name}'
+                    if clk_name != exp_name:
+                        raise ValueError(f'Unexpected clock {clk_name} in group'
+                                         f' {name} (exp: {exp_name})')
+                    clk_srcs.append(clk_src)
+                else:
+                    exp_prefix = f'clk_{clk_src}_'
+                    if not clk_name.startswith(exp_prefix):
+                        raise ValueError(f'Unexpected clock {clk_name} in group'
+                                         f' {name}')
+                    src_name = clk_name.removeprefix(exp_prefix)
+                    clk_srcs.append(src_name)
+                    if src_name in self._sub_clocks:
+                        raise ValueError(f'Refinition of clock {src_name}')
+                    self._sub_clocks[src_name] = OtDerivedClock(src_name,
+                                                                clk_src, 1)
+            self._clock_groups[name] = OtClockGroup(name, clk_srcs, sw_cg,
+                                                    hint)
+        modules = cfg.get('module', [])
+        mod_clocks = {}
+        for module in modules:
+            type_ = module['type']
+            if type_ in ('ast', 'clkmgr'):
+                continue
+            name = module['name']
+            clk_srcs = module.get('clock_srcs', {})
+            clk_grp = module.get('clock_group', '')
+            clocks = []
+            for clk in clk_srcs.values():
+                if isinstance(clk, dict):
+                    clocks.append(f'{clk["group"]}.{clk["clock"]}')
+                else:
+                    clocks.append(f'{clk_grp}.{clk}')
+            mod_clocks[name] = clocks
+        self._mod_clocks = mod_clocks
+
+    def load_lifecycle(self, svpath: str) -> None:
+        """Load LifeCycle data from RTL file.
+
+           :param svpath: System Verilog file with OTP constants
+        """
+        with open(svpath, 'rt') as cfp:
+            self._log.debug('Loading LC constants from %s', svpath)
+            self._lcconst.load_sv(cfp)
+
+    def load_otp_constants(self, svpath: str) -> None:
+        """Load OTP data from RTL file.
+
+           :param svpath: System Verilog file with OTP constants
+        """
+        with open(svpath, 'rt') as cfp:
+            self._log.debug('Loading OTP constants from %s', svpath)
+            self._otpconst.load_sv(cfp)
+
+    def load_constants(self, hjpath: Optional[str]) -> None:
+        """Load definitions from HJSON file.
+
+           :param hjpath: HJSON file with constants
+        """
+        if not hjpath:
+            return
+        assert not _HJSON_ERROR
+        self._log.debug('Loading secrets from %s', hjpath)
+        hjbase = basename(hjpath)
+        with open(hjpath, 'rt') as tfp:
+            cfg = hjload(tfp, object_pairs_hook=dict)
+        for module in cfg.get('module') or []:
+            modtype = module.get('type')
+            moddefs = self.MODULES.get(modtype)
+            if not moddefs:
+                continue
+            multi, regexes = moddefs[0], moddefs[1:]
+            consts = {}
+            OtpSecretConstants.load_values(module, consts, multi, *regexes)
+            if not consts:
+                continue
+            for cname, tname in self.TRANSLATIONS.get(modtype, {}).items():
+                if cname in consts:
+                    consts[tname] = consts.pop(cname)
+            self._log.debug('Constants for %s loaded from %s',
+                            modtype, hjbase)
+            exist = modtype in self._constants
+            if multi:
+                if not exist:
+                    self._constants[modtype] = consts
+                else:
+                    self._constants[modtype].update(consts)
+            else:
+                if exist:
+                    raise ValueError(f'Redefinition of {modtype}')
+                self._constants[modtype] = {None: consts}
+        self._otpconst.load_secrets(cfg)
+
+    def prepare(self) -> None:
+        """Prepare generation of data, aggregating several sources.
+        """
+        digests = {
+            'cnsty_digest': 'digest',
+            'flash_data_key': 'flash_data',
+            'flash_addr_key': 'flash_addr',
+            'sram_data_key': 'sram',
+        }
+        avail_digests = self._otpconst.get_digests()
+        otp_ctrl = self._constants['otp_ctrl'][None]
+        for digest, prefix in digests.items():
+            if digest not in avail_digests:
+                continue
+            pair = self._otpconst.get_digest_pair(digest, prefix)
+            otp_ctrl.update(pair)
+        for key in self._otpconst.get_scrambling_keys():
+            key_value = self._otpconst.get_scrambling_key(key)
+            key = key.removesuffix("key") + "_scramble_key"
+            otp_ctrl[key] = key_value
+        idx = 0
+        while True:
+            try:
+                defaults = self._otpconst.get_partition_inv_defaults(idx)
+                if defaults:
+                    otp_ctrl[f'inv_default_part_{idx}'] = defaults
+                idx += 1
+            except ValueError:
+                break
+        lc_ctrl = self._constants['lc_ctrl'][None]
+        lc_ctrl.update(self._lcconst.tokens)
+
+    def exclude(self, exclusions: list[str]) -> None:
+        """Add property exclusions.
+
+           :param exclusions: property defined as <device>.<name_prefix> to
+                              exclude from generation
+        """
+        for exclude in exclusions:
+            try:
+                dev, prop = exclude.split('.')
+            except ValueError as exc:
+                raise ArgError(f'Invalid exclusion format: {exclude}') from exc
+            if dev not in self._exclusions:
+                self._exclusions[dev] = set()
+            self._exclusions[dev].add(prop)
+
+    def save(self, variant: str, socid: Optional[str], count: Optional[int],
+             ofp: Optional[TextIO]) -> None:
+        """Save QEMU configuration file using a INI-like file format,
+           compatible with the `-readconfig` option of QEMU.
+        """
+        cfg = ConfigParser()
+        self._generate_roms(cfg, socid, count or 1)
+        self._generate_otp(cfg, variant, socid)
+        self._generate_lc_ctrl(cfg, socid)
+        self._generate_key_mgr(cfg, socid)
+        self._generate_ast(cfg, variant, socid)
+        self._generate_clkmgr(cfg, socid)
+        self._generate_pwrmgr(cfg, socid)
+        if self._git_version:
+            print(f'# Generated from OpenTitan commit: {self._git_version}\n',
+                  file=ofp)
+        cfg.write(ofp)
+
+    def show_clocks(self, ofp: Optional[TextIO]) -> None:
+        """List clock inputs for each module."""
+        mod_max_len = max(map(len, self._mod_clocks.keys()))
+        for modname, modclocks in sorted(self._mod_clocks.items()):
+            print(f'{modname:{mod_max_len}s}', ', '.join(modclocks), file=ofp)
+
+    def add_pair(self, devname: str, data: dict[str, str], kname: str,
+                 value: str) -> None:
+        """Helper to create key, value pair entries."""
+        for exc in self._exclusions.get(devname, []):
+            if kname.startswith(exc):
+                self._log.debug('Discarding %s.%s property', devname, kname)
+                return
+        if value:
+            data[f'  {kname}'] = f'"{value}"'
+
+    def _generate_roms(self, cfg: ConfigParser, socid: Optional[str] = None,
+                       count: int = 1) -> None:
+        for cnt in range(count):
+            for rom, data in self._constants['rom_ctrl'].items():
+                nameargs = ['ot-rom_ctrl']
+                if socid:
+                    if count > 1:
+                        nameargs.append(f'{socid}{cnt}')
+                    else:
+                        nameargs.append(socid)
+                if rom is not None:
+                    nameargs.append(f'rom{rom}')
+                romname = '.'.join(nameargs)
+                romdata = {}
+                for kname, val in sorted(data.items()):
+                    self.add_pair(romname, romdata, kname, val)
+                cfg[f'ot_device "{romname}"'] = romdata
+
+    def _generate_otp(self, cfg: ConfigParser, variant: str,
+                      socid: Optional[str] = None) -> None:
+        nameargs = [f'ot-otp-{variant}']
+        if socid:
+            nameargs.append(socid)
+        otpname = '.'.join(nameargs)
+        otpdata = {}
+        otp_ctrl = self._constants['otp_ctrl'][None]
+        for kname, val in otp_ctrl.items():
+            self.add_pair(otpname, otpdata, kname, val)
+
+        otpdata = dict(sorted(otpdata.items(),
+                              key=lambda x: alphanum_key(x[0])))
+        cfg[f'ot_device "{otpname}"'] = otpdata
+
+    def _generate_lc_ctrl(self, cfg: ConfigParser,
+                          socid: Optional[str] = None) -> None:
+        nameargs = ['ot-lc_ctrl']
+        if socid:
+            nameargs.append(socid)
+        lcname = '.'.join(nameargs)
+        lcdata = {}
+        for name, states in self._lcconst.states.items():
+            self.add_pair(lcname, lcdata, f'{name}_first', states[0])
+            self.add_pair(lcname, lcdata, f'{name}_last', states[1])
+        lc_ctrl = self._constants['lc_ctrl'][None]
+        for kname, value in lc_ctrl.items():
+            self.add_pair(lcname, lcdata, kname, value)
+        lcdata = dict(sorted(lcdata.items()))
+        cfg[f'ot_device "{lcname}"'] = lcdata
+
+    def _generate_key_mgr(self, cfg: ConfigParser,
+                          socid: Optional[str] = None) -> None:
+        keymgr = None
+        for keymgr_name in ('keymgr', 'keymgr_dpe'):
+            if keymgr_name in self._constants:
+                keymgr = self._constants[keymgr_name][None]
+                break
+        else:
+            return
+        nameargs = [f'ot-{keymgr_name}']
+        if socid:
+            nameargs.append(socid)
+        kmname = '.'.join(nameargs)
+        kmdata = {}
+        for kname, value in keymgr.items():
+            self.add_pair(kmname, kmdata, kname, value)
+            kmdata = dict(sorted(kmdata.items()))
+            cfg[f'ot_device "{kmname}"'] = kmdata
+
+    def _generate_ast(self, cfg: ConfigParser, variant: str,
+                      socid: Optional[str] = None) -> None:
+        nameargs = [f'ot-ast-{variant}']
+        if socid:
+            nameargs.append(socid)
+        astname = '.'.join(nameargs)
+        astdata = {}
+        topclockstr = ','.join(f'{c.name}:{c.frequency}'
+                               for c in self._top_clocks.values())
+        aonclockstr = ','.join(c.name for c in self._top_clocks.values()
+                               if c.aon)
+        self.add_pair(astname, astdata, 'topclocks', topclockstr)
+        self.add_pair(astname, astdata, 'aonclocks', aonclockstr)
+        cfg[f'ot_device "{astname}"'] = astdata
+
+    def _generate_clkmgr(self, cfg: ConfigParser,
+                         socid: Optional[str] = None) -> None:
+        nameargs = ['ot-clkmgr']
+        if socid:
+            nameargs.append(socid)
+        clkname = '.'.join(nameargs)
+        clkdata = {}
+        refclocks = [c for c in self._top_clocks.values() if c.ref]
+        if len(refclocks) > 1:
+            raise ValueError(f'Multiple reference clocks detected: '
+                             f'{", ".join(refclocks)}')
+        if refclocks:
+            clkrefname = refclocks[0].name
+            clfrefval = self._top_clocks.get(clkrefname)
+            if not clfrefval:
+                raise ValueError(f'Invalid reference clock {clkrefname}')
+        else:
+            clkrefname = None
+            clfrefval = None
+        topclockdefs = []
+        for ckname, ckval in self._top_clocks.items():
+            if clfrefval:
+                clkratio = ckval.frequency // clfrefval.frequency
+            else:
+                clkratio = 1
+            topclockdefs.append(f'{ckname}:{clkratio}')
+        topclockstr = ','.join(topclockdefs)
+        subclockstr = ','.join(f'{c.name}:{c.source}:{c.div}'
+                               for c in self._sub_clocks.values())
+        groupstr = ','.join(f'{g.name}:{"+".join(sorted(g.sources))}'
+                            for g in self._clock_groups.values())
+        swcgstr = ','.join(g.name for g in self._clock_groups.values()
+                           if g.sw_cg)
+        hintstr = ','.join(g.name for g in self._clock_groups.values()
+                           if g.hint)
+        self.add_pair(clkname, clkdata, 'topclocks', topclockstr)
+        if clkrefname:
+            self.add_pair(clkname, clkdata, 'refclock', clkrefname)
+        self.add_pair(clkname, clkdata, 'subclocks', subclockstr)
+        self.add_pair(clkname, clkdata, 'groups', groupstr)
+        self.add_pair(clkname, clkdata, 'swcg', swcgstr)
+        self.add_pair(clkname, clkdata, 'hint', hintstr)
+        cfg[f'ot_device "{clkname}"'] = clkdata
+
+    def _generate_pwrmgr(self, cfg: ConfigParser,
+                         socid: Optional[str] = None) -> None:
+        nameargs = ['ot-pwrmgr']
+        if socid:
+            nameargs.append(socid)
+        pwrname = '.'.join(nameargs)
+        pwrdata = {}
+        clockstr = ','.join(c.name for c in self._top_clocks.values()
+                            if not c.aon)
+        self.add_pair(pwrname, pwrdata, 'clocks', clockstr)
+        cfg[f'ot_device "{pwrname}"'] = pwrdata
+
+
+def main():
+    """Main routine"""
+    debug = True
+    actions = ['config', 'clock']
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        files = argparser.add_argument_group(title='Files')
+        files.add_argument('opentitan', nargs='?', metavar='OTDIR',
+                           help='OpenTitan root directory')
+        files.add_argument('-T', '--top', choices=OpenTitanTop.names,
+                           help='OpenTitan top name')
+        files.add_argument('-o', '--out', metavar='CFG',
+                           help='Filename of the config file to generate')
+        files.add_argument('-c', '--otpconst', metavar='SV',
+                           help='OTP Constant SV file (default: auto)')
+        files.add_argument('-l', '--lifecycle', metavar='SV',
+                           help='LifeCycle SV file (default: auto)')
+        files.add_argument('-S', '--secrets', metavar='HJSON',
+                           help='Secret HJSON file (default: auto)')
+        files.add_argument('-t', '--topcfg', metavar='HJSON',
+                           help='OpenTitan top HJSON config file '
+                                '(default: auto)')
+        mods = argparser.add_argument_group(title='Modifiers')
+        mods.add_argument('-s', '--socid',
+                          help='SoC identifier, if any')
+        mods.add_argument('-C', '--count', default=1, type=int,
+                          help='SoC count (default: 1)')
+        mods = argparser.add_argument_group(title='Actions')
+        mods.add_argument('-a', '--action', choices=actions,
+                          action='append', default=[],
+                          help=f'Action(s) to perform, default: {actions[0]}')
+        mods.add_argument('-x', '--exclude', action='append',
+                          metavar='DEVICE.NAME', default=[],
+                          help='Discard any property from DEVICE that starts '
+                               'with NAME (may be repeated)')
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        log = configure_loggers(args.verbose, 'cfggen', 'lc', 'otp')[0]
+
+        if _HJSON_ERROR:
+            argparser.error(f'Missing HJSON module: {_HJSON_ERROR}')
+
+        cfg = OtConfiguration()
+
+        topcfg = args.topcfg
+        ot_dir = args.opentitan
+        if not args.action:
+            args.action.append(actions[0])
+        if not topcfg:
+            if not args.opentitan:
+                argparser.error('OTDIR is required is no top file is specified')
+            if not isdir(ot_dir):
+                argparser.error('Invalid OpenTitan root directory')
+            ot_dir = abspath(ot_dir)
+            if not args.top:
+                argparser.error('Top name is required if no top file is '
+                                'specified')
+            top = f'top_{args.top}'
+            topvar = OpenTitanTop.short_name(args.top)
+            topcfg = joinpath(ot_dir, f'hw/{top}/data/autogen/{top}.gen.hjson')
+            if not isfile(topcfg):
+                argparser.error(f"No such file '{topcfg}'")
+            log.info("Top config: '%s'", topcfg)
+            cfg.load_config(topcfg)
+        else:
+            if not isfile(topcfg):
+                argparser.error(f'No such top file: {topcfg}')
+            cfg.load_config(topcfg)
+            ltop = cfg.top_name
+            if not ltop:
+                argparser.error('Unknown top name')
+            log.info("Top: '%s'", ltop)
+            ltop = ltop.lower()
+            topvar = OpenTitanTop.short_name(cfg.top_name)
+            if not topvar:
+                argparser.error(f'Unsupported top name: {cfg.top_name}')
+            top = f'top_{ltop}'
+            if not ot_dir:
+                check_dir = f'hw/{top}/data'
+                cur_dir = dirname(topcfg)
+                while cur_dir:
+                    check_path = joinpath(cur_dir, check_dir)
+                    if isdir(check_path):
+                        ot_dir = cur_dir
+                        break
+                    cur_dir = dirname(cur_dir)
+                if not ot_dir:
+                    argparser.error('Cannot find OT root directory')
+            elif not isdir(ot_dir):
+                argparser.error('Invalid OpenTitan root directory')
+            ot_dir = abspath(ot_dir)
+            log.info("OT directory: '%s'", ot_dir)
+        log.info("Variant: '%s'", topvar)
+        top_dir = joinpath(ot_dir, 'hw', top)
+
+        lcfilename = 'lc_ctrl_state_pkg.sv'
+        lcpath = args.lifecycle
+        if not lcpath:
+            lc_constant_locations = [
+                # master branch development environment
+                joinpath(top_dir, f'rtl/autogen/testing/{lcfilename}'),
+                # (obsolete) master branch development environment
+                joinpath(top_dir, f'rtl/autogen/dev/{lcfilename}'),
+                # (obsolete) master branch
+                joinpath(top_dir, f'rtl/autogen/{lcfilename}'),
+                # earlgrey_1.0.0 branch
+                joinpath(ot_dir, f'hw/ip/lc_ctrl/rtl/{lcfilename}'),
+            ]
+            for maybe_lcpath in lc_constant_locations:
+                if isfile(maybe_lcpath):
+                    lcpath = maybe_lcpath
+                    break
+        if not lcpath:
+            argparser.error(f"Unknown location for '{lcfilename}'")
+        if not isfile(lcpath):
+            argparser.error(f"No such file '{lcpath}'")
+        log.debug(f"'{lcfilename}' location: '%s'", lcpath)
+
+        ocfilename = 'otp_ctrl_part_pkg.sv'
+        ocpath = args.otpconst
+        if not ocpath:
+            otp_constant_locations = [
+                # master branch
+                joinpath(top_dir, f'ip_autogen/otp_ctrl/rtl/{ocfilename}'),
+                # earlgrey_1.0.0 branch
+                joinpath(ot_dir, f'hw/ip/otp_ctrl/rtl/{ocfilename}'),
+            ]
+            for maybe_ocpath in otp_constant_locations:
+                if isfile(maybe_ocpath):
+                    ocpath = maybe_ocpath
+                    break
+        if not ocpath:
+            argparser.error(f"Unknown location for '{ocfilename}'")
+        if not isfile(ocpath):
+            argparser.error(f"No such file '{ocpath}'")
+        log.debug(f"'{ocfilename}' location: '%s'", ocpath)
+
+        secpath = args.secrets
+        if secpath:
+            if not isfile(secpath):
+                argparser.error('No such secret file: {secpath}')
+        else:
+            sec_constant_locations = [
+                # master branch development environment
+                joinpath(top_dir,
+                         f'data/autogen/{top}.secrets.testing.gen.hjson'),
+                # (obsolete) master branch development environment
+                joinpath(top_dir, f'data/autogen/{top}.secrets.dev.gen.hjson'),
+            ]
+            for maybe_secpath in sec_constant_locations:
+                if isfile(maybe_secpath):
+                    secpath = maybe_secpath
+                    break
+
+        cfg.load_lifecycle(lcpath)
+        cfg.load_otp_constants(ocpath)
+        cfg.load_constants(secpath)
+        cfg.prepare()
+        cfg.exclude(args.exclude)
+
+        with open(args.out, 'wt') if args.out else sys.stdout as ofp:
+            if 'config' in args.action:
+                cfg.save(topvar, args.socid, args.count, ofp)
+            if 'clock' in args.action:
+                cfg.show_clocks(ofp)
+
+    except (ArgError, IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/checkregs.py b/scripts/opentitan/checkregs.py
new file mode 100755
index 0000000000000..81a48e85220a4
--- /dev/null
+++ b/scripts/opentitan/checkregs.py
@@ -0,0 +1,283 @@
+#!/usr/bin/env python3
+
+"""Verify register definitions.
+"""
+
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+from argparse import ArgumentParser
+from logging import DEBUG, ERROR, getLogger, Formatter, StreamHandler
+from os import pardir, walk
+from os.path import (basename, dirname, join as joinpath, normpath, relpath,
+                     splitext)
+from traceback import format_exc
+from typing import NamedTuple, Optional, TextIO
+import re
+import sys
+
+
+class ValueLocation(NamedTuple):
+    """Location of a defined value."""
+    line: int  # line
+    start: int  # start column
+    end: int  # end column
+
+
+RegisterDefs = dict[str, tuple[int, ValueLocation]]
+"""Definition of a register value (name, value, location)."""
+
+# pylint: disable=missing-function-docstring
+
+
+class OtRegisters:
+    """Simple class to parse and compare register definitions
+    """
+
+    DEFMAP = {
+        'alert_handler': 'alert',
+        'flash_ctrl': 'flash',
+        'lc_ctrl': 'lifecycle',
+        'rv_core_ibex': 'ibex_wrapper',
+        'rv_timer': 'timer',
+        'sensor_ctrl': 'sensor'
+    }
+
+    def __init__(self):
+        self._log = getLogger('ot.regs')
+
+    def parse_defs(self, filename: str) -> RegisterDefs:
+        with open(filename, 'rt') as hfp:
+            return self._parse_defs(hfp)
+
+    def _parse_defs(self, hfp: TextIO) -> RegisterDefs:
+        radix = splitext(basename(hfp.name))[0]
+        radix = radix.rsplit('_', 1)[0]
+        defs = {}
+        rre = f'{radix.upper()}_'
+        # the following RE matches two kinds of definition:
+        #   #define <COMPONENT>_<RADIX>_REG_OFFSET <HEXVAL>
+        #   #define <COMPONENT>_PARAM_<RADIX>_OFFSET <HEXVAL>
+        reg_cre = re.compile(rf'^#define {rre}(?P<param>PARAM_)?'
+                             r'(?P<name>[A-Z][\w]+?)(?(param)|_REG)_OFFSET\s+'
+                             r'(?P<val>(?:0x)?[A-Fa-f0-9]+)(?:\s|$)')
+        for lno, line in enumerate(hfp, start=1):
+            line = line.strip()
+            rmo = reg_cre.match(line)
+            if not rmo:
+                continue
+            regname = rmo.group('name')
+            sregaddr = rmo.group('val')
+            vstart, vend = rmo.start('val'), rmo.end('val')
+            regaddr = int(sregaddr, 16 if sregaddr.startswith('0x') else 10)
+            self._log.debug("%s: 0x%x", regname, regaddr)
+            if regname in defs:
+                self._log.error('Redefinition of %s: %x -> %x', regname,
+                                defs[regname][0], regaddr)
+            defs[regname] = (regaddr, ValueLocation(lno, vstart, vend))
+        return defs
+
+    def find_qemu_impl(self, filename: str, basedir: str, nomap: bool) \
+            -> Optional[str]:
+        filename = basename(filename)
+        radix = re.sub(r'_regs$', '', splitext(filename)[0])
+        if not nomap:
+            radix = self.DEFMAP.get(radix, radix)
+        impl_name = f'ot_{radix}.c'
+        self._log.debug('Looking up %s for %s in %s',
+                        impl_name, filename, basedir)
+        for dirpath, _, filenames in walk(basedir):
+            if impl_name in filenames:
+                impl_path = joinpath(dirpath, impl_name)
+                self._log.debug('Found as %s', impl_path)
+                return impl_path
+        return None
+
+    def parse_ot_qemu(self, filename: str) -> RegisterDefs:
+        with open(filename, 'rt') as qfp:
+            return self._parse_ot_qemu(qfp)
+
+    def _parse_ot_qemu(self, qfp: TextIO) -> RegisterDefs:
+        defs = {}
+        regfield_cre = re.compile(r'^\s*REG32\(([A-Z][\w]+),\s+'
+                                  r'((?:0x)?[A-Fa-f0-9]+)u?\)(?:\s|$)')
+        for lno, line in enumerate(qfp, start=1):
+            line = line.strip()
+            rmo = regfield_cre.match(line)
+            if not rmo:
+                continue
+            regname = rmo.group(1)
+            sregaddr = rmo.group(2)
+            vstart, vend = rmo.start(2), rmo.end(2)
+            regaddr = int(sregaddr, 16 if sregaddr.startswith('0x') else 10)
+            self._log.debug("%s: 0x%x", regname, regaddr)
+            if regname in defs:
+                self._log.error('Redefinition of %s: %x -> %x', regname,
+                                defs[regname][0], regaddr)
+            defs[regname] = (regaddr, ValueLocation(lno, vstart, vend))
+        return defs
+
+    def compare(self, name: str, hdefs: RegisterDefs,
+                qdefs: RegisterDefs, show_all: bool) \
+            -> tuple[int, dict[ValueLocation, int], set[int]]:
+        name = basename(name)
+        chdefs = {k: v[0] for k, v in hdefs.items()}
+        cqdefs = {k: v[0] for k, v in qdefs.items()}
+        deprecated: set[int] = set()
+        appendable: dict[str, int] = {}
+        fixes: dict[ValueLocation, int] = {}
+        if chdefs == cqdefs:
+            self._log.info('%s: ok, %d register definitions', name, len(hdefs))
+            return 0, fixes, deprecated, appendable
+        if len(hdefs) == len(qdefs):
+            self._log.debug('%s: %d register definitions', name, len(hdefs))
+        hentries = set(hdefs)
+        qentries = set(qdefs)
+        mismatch_count = 0
+        if hentries != qentries:
+            hmissing = qentries - hentries
+            if hmissing:
+                missing = len(hmissing)
+                self._log.warning('QEMU %s contains %s non-existing defs',
+                                  name, missing)
+                for miss in sorted(hmissing, key=lambda e: qdefs[e][1]):
+                    deprecated.add(qdefs[miss][1].line)
+                    if show_all:
+                        self._log.warning('.. %s (0x%x)', miss, qdefs[miss][0])
+                mismatch_count += missing
+            qmissing = hentries - qentries
+            if qmissing:
+                missing = len(qmissing)
+                self._log.warning('QEMU %s is missing %d defs', name, missing)
+                for miss in sorted(qmissing, key=lambda e: hdefs[e][1]):
+                    appendable[miss] = hdefs[miss][0]
+                    if show_all:
+                        self._log.warning('.. %s (0x%x)', miss, hdefs[miss][0])
+                mismatch_count += missing
+        entries = hentries & qentries
+        for entry in sorted(entries, key=lambda e: hdefs[e][0]):
+            if hdefs[entry][0] != qdefs[entry][0]:
+                self._log.warning('Mismatched definition for %s: '
+                                  'OT: 0x%x @ line %d / QEMU 0x%x @ line %d',
+                                  entry, hdefs[entry][0], hdefs[entry][1].line,
+                                  qdefs[entry][0], qdefs[entry][1].line)
+                fixes[qdefs[entry][1]] = hdefs[entry][0]
+                mismatch_count += 1
+        self._log.error('%s: %d discrepancies', name, mismatch_count)
+        return mismatch_count, fixes, deprecated, appendable
+
+    def fix(self, filename: str, suffix: str, fixes: dict[ValueLocation, int],
+            deprecated: set[int], newvalues: dict[str, int]) \
+            -> None:
+        fix_lines = {loc.line: (loc.start, loc.end, val)
+                     for loc, val in fixes.items()}
+        parts = splitext(filename)
+        outfilename = f'{parts[0]}_{suffix}{parts[1]}'
+        with open(filename, 'rt') as ifp:
+            with open(outfilename, 'wt') as ofp:
+                for lno, line in enumerate(ifp, start=1):
+                    if lno in deprecated:
+                        # use a C++ comment to stress on this line, since QEMU
+                        # prohibit the use of this comment style, the output
+                        # file should be rejected by checkpatch.pl
+                        line = f'// {line.rstrip()} [deprecated]\n'
+                    elif lno in fix_lines:
+                        start, end, val = fix_lines[lno]
+                        lhs = line[:start]
+                        rhs = line[end:]
+                        hexfmt = line[start:].startswith('0x')
+                        if hexfmt:
+                            line = f'{lhs}0x{val:x}{rhs}'
+                        else:
+                            line = f'{lhs}{val}{rhs}'
+                    print(line, file=ofp, end='')
+                if newvalues:
+                    print('', file=ofp)
+                    print('// New registers', file=ofp)
+                    print('#ifdef USE_DECIMAL_VALUES', file=ofp)
+                    for name, val in newvalues.items():
+                        print(f'REG32({name}, {val}u)', file=ofp)
+                    print('#else // USE_DECIMAL_VALUES', file=ofp)
+                    for name, val in newvalues.items():
+                        print(f'REG32({name}, 0x{val:x}u)', file=ofp)
+                    print('#endf // !USE_DECIMAL_VALUES', file=ofp)
+
+
+def main():
+    """Main routine"""
+    debug = False
+    qemu_default_dir = dirname(dirname(dirname(normpath(__file__))))
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('regs', nargs='+', metavar='file',
+                               help='register header file')
+        argparser.add_argument('-q', '--qemu', default=qemu_default_dir,
+                               metavar='dir',
+                               help='QEMU directory to seek')
+        argparser.add_argument('-a', '--all', action='store_true',
+                               default=False,
+                               help='list all discrepancies')
+        argparser.add_argument('-k', '--keep', action='store_true',
+                               default=False,
+                               help='keep verifying if QEMU impl. is not found')
+        argparser.add_argument('-f', '--fix', metavar='SUFFIX', default=False,
+                               help='create a file with specified suffix '
+                                    'with possible fixes')
+        argparser.add_argument('-M', '--no-map', action='store_true',
+                               default=False,
+                               help='do not convert regs into QEMU impl. path')
+        argparser.add_argument('-v', '--verbose', action='count',
+                               help='increase verbosity')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        loglevel = max(DEBUG, ERROR - (10 * (args.verbose or 0)))
+        loglevel = min(ERROR, loglevel)
+        formatter = Formatter('%(levelname)8s %(name)-10s %(message)s')
+        log = getLogger('ot')
+        logh = StreamHandler(sys.stderr)
+        logh.setFormatter(formatter)
+        log.setLevel(loglevel)
+        log.addHandler(logh)
+
+        mismatch_count = 0
+        for regfile in args.regs:
+            otr = OtRegisters()
+            qemu_impl = otr.find_qemu_impl(regfile, args.qemu, args.no_map)
+            if not qemu_impl:
+                pretty_file = relpath(regfile)
+                if pretty_file.startswith(pardir):
+                    pretty_file = regfile
+                msg = f'Unable to locate implementation file for {pretty_file}'
+                if not args.keep:
+                    raise ValueError(msg)
+                log.info('%s', msg)
+                continue
+            hdefs = otr.parse_defs(regfile)
+            qdefs = otr.parse_ot_qemu(qemu_impl)
+            mm_count, fixes, deprecated, newvalues = \
+                otr.compare(qemu_impl, hdefs, qdefs, args.all)
+            if mm_count and args.fix:
+                otr.fix(qemu_impl, args.fix, fixes, deprecated, newvalues)
+            mismatch_count += mm_count
+
+        if mismatch_count:
+            print(f'{mismatch_count} differences', file=sys.stderr)
+            sys.exit(1)
+        print('No differences', file=sys.stderr)
+
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/clang-format.d/opentitan.lst b/scripts/opentitan/clang-format.d/opentitan.lst
new file mode 100644
index 0000000000000..d8c2d3124b39d
--- /dev/null
+++ b/scripts/opentitan/clang-format.d/opentitan.lst
@@ -0,0 +1,18 @@
+hw/jtag/*.c
+hw/misc/pulp_rv_dm.c
+hw/opentitan/*.c
+hw/opentitan/*.h
+hw/riscv/debug.c
+hw/riscv/dm*.c
+hw/riscv/dtm*.c
+hw/riscv/ibex*.c
+hw/riscv/ot_*.c
+include/hw/jtag/*.h
+include/hw/misc/pulp_rv_dm.h
+include/hw/opentitan/*.h
+include/hw/riscv/debug.h
+include/hw/riscv/dm*.h
+include/hw/riscv/dtm*.h
+include/hw/riscv/ibex*.h
+include/hw/riscv/ot_*.h
+target/riscv/ibex*.c
diff --git a/scripts/opentitan/clang-format.yml b/scripts/opentitan/clang-format.yml
new file mode 100644
index 0000000000000..581dbea1c68fd
--- /dev/null
+++ b/scripts/opentitan/clang-format.yml
@@ -0,0 +1,315 @@
+---
+# compatible with clang-format-19
+Language:        Cpp
+AccessModifierOffset: -2
+AlignAfterOpenBracket: Align
+AlignArrayOfStructures: None
+AlignConsecutiveAssignments:
+  Enabled:         false
+  AcrossEmptyLines: false
+  AcrossComments:  false
+  AlignCompound:   false
+  AlignFunctionDeclarations: false
+  AlignFunctionPointers: false
+  PadOperators:    true
+AlignConsecutiveBitFields:
+  Enabled:         false
+  AcrossEmptyLines: false
+  AcrossComments:  false
+  AlignCompound:   false
+  AlignFunctionDeclarations: false
+  AlignFunctionPointers: false
+  PadOperators:    true
+AlignConsecutiveDeclarations:
+  Enabled:         false
+  AcrossEmptyLines: false
+  AcrossComments:  false
+  AlignCompound:   false
+  AlignFunctionDeclarations: false
+  AlignFunctionPointers: false
+  PadOperators:    true
+AlignConsecutiveMacros:
+  Enabled:         true
+  AcrossEmptyLines: false
+  AcrossComments:  false
+  AlignCompound:   false
+  AlignFunctionDeclarations: false
+  AlignFunctionPointers: false
+  PadOperators:    false
+AlignConsecutiveShortCaseStatements:
+  Enabled:         false
+  AcrossEmptyLines: false
+  AcrossComments:  false
+  AlignCaseArrows: false
+  AlignCaseColons: false
+AlignConsecutiveTableGenBreakingDAGArgColons:
+  Enabled:         false
+  AcrossEmptyLines: false
+  AcrossComments:  false
+  AlignCompound:   false
+  AlignFunctionDeclarations: false
+  AlignFunctionPointers: false
+  PadOperators:    false
+AlignConsecutiveTableGenCondOperatorColons:
+  Enabled:         false
+  AcrossEmptyLines: false
+  AcrossComments:  false
+  AlignCompound:   false
+  AlignFunctionDeclarations: false
+  AlignFunctionPointers: false
+  PadOperators:    false
+AlignConsecutiveTableGenDefinitionColons:
+  Enabled:         false
+  AcrossEmptyLines: false
+  AcrossComments:  false
+  AlignCompound:   false
+  AlignFunctionDeclarations: false
+  AlignFunctionPointers: false
+  PadOperators:    false
+AlignEscapedNewlines: DontAlign
+AlignOperands:   Align
+AlignTrailingComments:
+  Kind:            Never
+  OverEmptyLines:  0
+AllowAllArgumentsOnNextLine: true
+AllowAllParametersOfDeclarationOnNextLine: true
+AllowBreakBeforeNoexceptSpecifier: Never
+AllowShortBlocksOnASingleLine: Never
+AllowShortCaseExpressionOnASingleLine: true
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortCompoundRequirementOnASingleLine: true
+AllowShortEnumsOnASingleLine: true
+AllowShortFunctionsOnASingleLine: Empty
+AllowShortIfStatementsOnASingleLine: Never
+AllowShortLambdasOnASingleLine: All
+AllowShortLoopsOnASingleLine: false
+AllowShortNamespacesOnASingleLine: false
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AttributeMacros:
+BinPackArguments: true
+BinPackParameters: BinPack
+BitFieldColonSpacing: None
+BraceWrapping:
+  AfterCaseLabel:  false
+  AfterClass:      false
+  AfterControlStatement: Never
+  AfterEnum:       false
+  AfterExternBlock: false
+  AfterFunction:   true
+  AfterNamespace:  false
+  AfterObjCDeclaration: false
+  AfterStruct:     false
+  AfterUnion:      false
+  BeforeCatch:     false
+  BeforeElse:      false
+  BeforeLambdaBody: false
+  BeforeWhile:     false
+  IndentBraces:    false
+  SplitEmptyFunction: true
+  SplitEmptyNamespace: true
+  SplitEmptyRecord: false
+BreakAfterAttributes: Never
+BreakAfterJavaFieldAnnotations: false
+BreakAfterReturnType: None
+BreakArrays:     true
+BreakBeforeBinaryOperators: None
+BreakBeforeBraces: Custom
+BreakBeforeConceptDeclarations: Always
+BreakBeforeInheritanceComma: false
+BreakBeforeInlineASMColon: OnlyMultiline
+BreakBeforeTemplateCloser: false
+BreakBeforeTernaryOperators: false
+BreakBinaryOperations: Never
+BreakConstructorInitializers: BeforeColon
+BreakConstructorInitializersBeforeComma: false
+BreakFunctionDefinitionParameters: false
+BreakInheritanceList: BeforeColon
+BreakStringLiterals: true
+BreakTemplateDeclarations: MultiLine
+ColumnLimit:     80
+CommentPragmas:  '^ IWYU pragma:'
+CompactNamespaces: false
+ConstructorInitializerIndentWidth: 4
+ContinuationIndentWidth: 4
+Cpp11BracedListStyle: false
+DeriveLineEnding: false
+DerivePointerAlignment: false
+DisableFormat:   false
+EmptyLineAfterAccessModifier: Never
+EmptyLineBeforeAccessModifier: LogicalBlock
+EnumTrailingComma: Leave
+ExperimentalAutoDetectBinPacking: false
+FixNamespaceComments: true
+ForEachMacros:
+  - foreach
+  - Q_FOREACH
+  - QLIST_FOREACH
+  - QLIST_FOREACH_RCU
+  - QLIST_FOREACH_ENTRY
+  - QLIST_FOREACH_SAFE
+  - QLIST_FOREACH_SAFE_RCU
+  - QSIMPLEQ_FOREACH
+  - QSIMPLEQ_FOREACH_RCU
+  - QSIMPLEQ_FOREACH_SAFE
+  - QSIMPLEQ_FOREACH_SAFE_RCU
+  - QTAILQ_FOREACH
+  - QTAILQ_FOREACH_RCU
+  - QTAILQ_FOREACH_SAFE
+  - QTAILQ_FOREACH_REVERSE
+  - QTAILQ_FOREACH_REVERSE_SAFE
+  - QTAILQ_RAW_FOREACH
+  - QLIST_RAW_FOREACH
+  - BOOST_FOREACH
+  - CPU_FOREACH
+IfMacros:
+  - KJ_IF_MAYBE
+IncludeBlocks:   Merge
+IncludeCategories:
+  - Regex:           '^"qemu/osdep.h"'
+    Priority:        0
+    SortPriority:    0
+    CaseSensitive:   false
+  - Regex:           '^<'
+    Priority:        1
+    SortPriority:    0
+    CaseSensitive:   false
+  - Regex:           '^"qemu/.*.h"'
+    Priority:        2
+    SortPriority:    0
+    CaseSensitive:   false
+  - Regex:           '^"qapi/.*.h"'
+    Priority:        3
+    SortPriority:    0
+    CaseSensitive:   false
+  - Regex:           '^"qom/.*.h"'
+    Priority:        3
+    SortPriority:    0
+    CaseSensitive:   false
+  - Regex:           '.*'
+    Priority:        4
+    SortPriority:    0
+    CaseSensitive:   false
+IncludeIsMainRegex: ''
+IncludeIsMainSourceRegex: ''
+IndentAccessModifiers: false
+IndentCaseBlocks: false
+IndentCaseLabels: false
+IndentExportBlock: true
+IndentExternBlock: AfterExternBlock
+IndentGotoLabels: true
+IndentPPDirectives: None
+IndentRequiresClause: true
+IndentWidth:     4
+IndentWrappedFunctionNames: false
+InsertBraces:    false
+InsertNewlineAtEOF: true
+InsertTrailingCommas: None
+IntegerLiteralSeparator:
+  Binary:          0
+  BinaryMinDigits: 0
+  Decimal:         0
+  DecimalMinDigits: 0
+  Hex:             0
+  HexMinDigits:    0
+JavaScriptQuotes: Leave
+JavaScriptWrapImports: true
+KeepEmptyLines:
+  AtEndOfFile:     true
+  AtStartOfBlock:  false
+  AtStartOfFile:   false
+KeepFormFeed:    false
+LambdaBodyIndentation: Signature
+LineEnding:      LF
+MacroBlockBegin: ''
+MacroBlockEnd:   ''
+MainIncludeChar: Quote
+MaxEmptyLinesToKeep: 2
+NamespaceIndentation: None
+ObjCBinPackProtocolList: Auto
+ObjCBlockIndentWidth: 2
+ObjCBreakBeforeNestedBlockParam: true
+ObjCSpaceAfterProperty: false
+ObjCSpaceBeforeProtocolList: true
+OneLineFormatOffRegex: ''
+PackConstructorInitializers: BinPack
+PenaltyBreakAssignment: 0
+PenaltyBreakBeforeFirstCallParameter: 500
+PenaltyBreakBeforeMemberAccess: 150
+PenaltyBreakComment: 300
+PenaltyBreakFirstLessLess: 120
+PenaltyBreakOpenParenthesis: 0
+PenaltyBreakScopeResolution: 500
+PenaltyBreakString: 1000
+PenaltyBreakTemplateDeclaration: 10
+PenaltyExcessCharacter: 1000000
+PenaltyIndentedWhitespace: 1
+PenaltyReturnTypeOnItsOwnLine: 60
+PointerAlignment: Right
+PPIndentWidth:   -1
+QualifierAlignment: Leave
+ReferenceAlignment: Pointer
+ReflowComments:  Always
+RemoveBracesLLVM: false
+RemoveEmptyLinesInUnwrappedLines: false
+RemoveParentheses: Leave
+RemoveSemicolon: false
+RequiresClausePosition: OwnLine
+RequiresExpressionIndentation: OuterScope
+SeparateDefinitionBlocks: Leave
+ShortNamespaceLines: 1
+SkipMacroDefinitionBody: false
+SortIncludes:
+  Enabled: true
+  IgnoreCase: true
+SortJavaStaticImport: Before
+SortUsingDeclarations: LexicographicNumeric
+SpaceAfterCStyleCast: false
+SpaceAfterLogicalNot: false
+SpaceAfterOperatorKeyword: false
+SpaceAfterTemplateKeyword: true
+SpaceAroundPointerQualifiers: Default
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCaseColon: false
+SpaceBeforeCpp11BracedList: false
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeJsonColon: false
+SpaceBeforeParens: ControlStatementsExceptControlMacros
+SpaceBeforeParensOptions:
+  AfterControlStatements: true
+  AfterForeachMacros: true
+  AfterFunctionDeclarationName: false
+  AfterFunctionDefinitionName: false
+  AfterIfMacros: true
+  AfterOverloadedOperator: false
+  AfterPlacementOperator: true
+  AfterRequiresInClause: false
+  AfterRequiresInExpression: false
+  BeforeNonEmptyParentheses: false
+SpaceBeforeRangeBasedForLoopColon: true
+SpaceBeforeSquareBrackets: false
+SpaceInEmptyBlock: false
+SpacesBeforeTrailingComments: 1
+SpacesInAngles:  Never
+SpacesInContainerLiterals: true
+SpacesInLineCommentPrefix:
+  Minimum:         1
+  Maximum:         -1
+SpacesInParens:  Never
+SpacesInParensOptions:
+  ExceptDoubleParentheses: false
+  InCStyleCasts:   false
+  InConditionalStatements: false
+  InEmptyParentheses: false
+  Other:           false
+SpacesInSquareBrackets: false
+Standard:        Latest
+StatementAttributeLikeMacros:
+StatementMacros:
+TabWidth:        4
+UseTab:          Never
+VerilogBreakBetweenInstancePorts: true
+WhitespaceSensitiveMacros:
+WrapNamespaceBodyWithEmptyLines: Leave
+...
diff --git a/scripts/opentitan/clang-tidy.d/opentitan.lst b/scripts/opentitan/clang-tidy.d/opentitan.lst
new file mode 100644
index 0000000000000..b5e77a69186e0
--- /dev/null
+++ b/scripts/opentitan/clang-tidy.d/opentitan.lst
@@ -0,0 +1,7 @@
+hw/misc/pulp_rv_dm.c
+hw/opentitan/*.c
+hw/riscv/debug.c
+hw/riscv/dm*.c
+hw/riscv/ot_*.c
+hw/riscv/ibex_*.c
+target/riscv/ibex*.c
diff --git a/scripts/opentitan/clang-tidy.yml b/scripts/opentitan/clang-tidy.yml
new file mode 100644
index 0000000000000..c72aeacad7ba8
--- /dev/null
+++ b/scripts/opentitan/clang-tidy.yml
@@ -0,0 +1,48 @@
+---
+Checks:          '*,
+                  -*-avoid-non-const-global-variables,
+                  -*-magic-numbers,
+                  -*-uppercase-literal-suffix,
+                  -altera-*,
+                  -android-cloexec-fopen,
+                  -bugprone-assignment-in-if-condition,
+                  -bugprone-branch-clone,
+                  -bugprone-casting-through-void,
+                  -bugprone-easily-swappable-parameters,
+                  -bugprone-implicit-widening-of-multiplication-result,
+                  -bugprone-multi-level-implicit-pointer-conversion,
+                  -bugprone-reserved-identifier,
+                  -bugprone-tagged-union-member-count,
+                  -clang-analyzer-optin.performance.Padding,
+                  -clang-analyzer-security.ArrayBound,
+                  -clang-analyzer-security.insecureAPI.DeprecatedOrUnsafeBufferHandling,
+                  -clang-diagnostic-error,
+                  -clang-diagnostic-unknown-warning-option,
+                  -cert-dcl37-c,-cert-dcl51-cpp,
+                  -cert-int09-c,
+                  -concurrency-mt-unsafe,
+                  -cppcoreguidelines-init-variables,
+                  -cppcoreguidelines-interfaces-global-init,
+                  -cppcoreguidelines-macro-to-enum,
+                  -google-readability-*,
+                  -hicpp-no-assembler,
+                  -hicpp-signed-bitwise,
+                  -llvmlibc-*,
+                  -llvm-*,
+                  -misc-include-cleaner,
+                  -modernize-macro-to-enum,
+                  -performance-no-int-to-ptr,
+                  -readability-avoid-nested-conditional-operator,
+                  -readability-function-cognitive-complexity,
+                  -readability-identifier-length,
+                  -readability-enum-initial-value,
+                  -readability-isolate-declaration,
+                  -readability-math-missing-parentheses,
+                  -readability-redundant-casting,
+                  -readability-redundant-declaration,
+                  -readability-use-concise-preprocessor-directives'
+
+UseColor: true
+SystemHeaders: false
+WarningsAsErrors: '*'
+...
diff --git a/scripts/opentitan/darjeeling-ocd.cfg b/scripts/opentitan/darjeeling-ocd.cfg
new file mode 100644
index 0000000000000..c1d180e041f28
--- /dev/null
+++ b/scripts/opentitan/darjeeling-ocd.cfg
@@ -0,0 +1,27 @@
+#-------------------------------------------------------------------------------
+# OpenTitan Darjeeling machine
+# Openocd configuration file for use with `-jtag tcp::3335` option
+#-------------------------------------------------------------------------------
+
+adapter driver remote_bitbang
+remote_bitbang host localhost
+remote_bitbang port 3335
+
+transport select jtag
+
+# TAP IR instruction length
+set _IRLENGTH 5
+
+# DMI addresses
+set _OT_DJ_DEBUG_RV_DM_ADDR        0x0
+set _OT_DJ_DEBUG_MBX_JTAG_ADDR     0x880
+set _OT_DJ_DEBUG_SOC_DBG_CTRL_ADDR 0x8c0
+set _OT_DJ_DEBUG_LC_CTRL_ADDR      0xc00
+
+set _CHIPNAME riscv
+# part 1, ver 0, lowRISC
+set _CPUTAPID 0x00011cdf
+
+jtag newtap $_CHIPNAME cpu -irlen $_IRLENGTH -expected-id $_CPUTAPID
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread -dbgbase $_OT_DJ_DEBUG_RV_DM_ADDR
diff --git a/scripts/opentitan/dtm.py b/scripts/opentitan/dtm.py
new file mode 100755
index 0000000000000..3cc175cea3107
--- /dev/null
+++ b/scripts/opentitan/dtm.py
@@ -0,0 +1,326 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2024, Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Debug Transport Module tiny demo.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, Namespace, FileType
+from binascii import unhexlify
+from io import BytesIO
+from os import linesep
+from os.path import dirname, join as joinpath, normpath
+from socket import create_connection, socket, AF_UNIX, SOCK_STREAM
+from time import sleep, time as now
+from traceback import format_exc
+from typing import Optional
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from jtagtools.rbb import JtagBitbangController
+from jtagtools.bits import BitSequence
+from jtagtools.jtag import JtagEngine
+
+from ot.dm import DebugModule
+from ot.dtm import DebugTransportModule
+from ot.dtm.dtm import DMI, DTMCS
+from ot.util.elf import ElfBlob
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt, dump_buffer
+
+try:
+    _FTDI_ERR = None
+    PYFTDI_MIN_VER = (0, 59)
+    from pyftdi import __version__ as PyFtdiVersion
+    from pyftdi.jtag import JtagFtdiController
+except ImportError as _exc:
+    _FTDI_ERR = str(_exc).split(':', 1)[-1]
+    JtagFtdiController = None
+
+
+DEFAULT_IR_LENGTH = 5
+"""Default TAP Instruction Register length."""
+
+DEFAULT_DMI_ADDRESS = 0x0
+"""Default DMI address of the DM."""
+
+
+def idcode(engine: JtagEngine, code: int, ir_length: int) -> int:
+    """Retrieve ID code."""
+    engine.write_ir(BitSequence(code, ir_length))
+    engine.read_dr(32)
+    engine.go_idle()
+    value = engine.scan()
+    return int(value)
+
+
+def main():
+    """Entry point."""
+    debug = True
+    default_socket = f'tcp:localhost:{JtagBitbangController.DEFAULT_PORT}'
+    default_idcode = JtagBitbangController.INSTRUCTIONS['idcode']
+    try:
+        args: Optional[Namespace] = None
+        argparser = ArgumentParser(
+            description=sys.modules[__name__].__doc__.split('.')[0])
+        qvm = argparser.add_argument_group(title='Virtual machine')
+
+        qvm.add_argument('-S', '--socket', default=default_socket,
+                         help=f'connection (default {default_socket})')
+        qvm.add_argument('-t', '--terminate', action='store_true',
+                         help='terminate QEMU when done')
+        qvm.add_argument('-w', '--idle', type=float, metavar='DELAY',
+                         action='append',
+                         help='stay idle before interacting with DTM')
+        dmi = argparser.add_argument_group(title='DMI')
+        dmi.add_argument('-l', '--ir-length', type=int,
+                         default=DEFAULT_IR_LENGTH,
+                         help=f'bit length of the IR register '
+                              f'(default: {DEFAULT_IR_LENGTH})')
+        dmi.add_argument('--idcode', type=int, default=default_idcode,
+                         help=f'define the ID code (default: {default_idcode})')
+        dmi.add_argument('--dtmcs', type=HexInt.parse,
+                         help=f'define an alternative DTMCS register '
+                              f'(default: 0x{DTMCS.ADDRESS:x})')
+        dmi.add_argument('--dmi', type=HexInt.parse,
+                         help=f'define an alternative DMI register '
+                              f'(default: 0x{DMI.ADDRESS:x})')
+        dmi.add_argument('-b', '--base', type=HexInt.parse,
+                         default=DEFAULT_DMI_ADDRESS,
+                         help=f'define DMI base address '
+                              f'(default: 0x{DEFAULT_DMI_ADDRESS:x})')
+        info = argparser.add_argument_group(title='Info')
+        info.add_argument('-I', '--info', action='store_true',
+                          help='report JTAG ID code and DTM configuration')
+        info.add_argument('-c', '--csr',
+                          help='read CSR value from hart')
+        info.add_argument('-C', '--csr-check', type=HexInt.parse, default=None,
+                          help='check CSR value matches')
+        act = argparser.add_argument_group(title='Actions')
+        act.add_argument('-x', '--execute', action='store_true',
+                         help='update the PC from a loaded ELF file')
+        act.add_argument('-X', '--no-exec', action='store_true', default=False,
+                         help='does not resume hart execution')
+        mem = argparser.add_argument_group(title='Memory')
+        mem.add_argument('-a', '--address', type=HexInt.parse,
+                         help='address of the first byte to access')
+        mem.add_argument('-m', '--mem', choices=('read', 'write'),
+                         help='access memory using System Bus')
+        mem.add_argument('-s', '--size', type=HexInt.parse,
+                         help='size in bytes of memory to access')
+        mem.add_argument('-f', '--file',
+                         help='file to read/write data for memory access')
+        mem.add_argument('-D', '--data',
+                         help='data to write using memory access')
+        mem.add_argument('-e', '--elf', type=FileType('rb'),
+                         help='load ELF file into memory')
+        mem.add_argument('-F', '--fast-mode', default=False,
+                         action='store_true',
+                         help='do not check system bus status while '
+                              'transferring')
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+
+        args = argparser.parse_args()
+        debug = args.debug
+
+        main_loggers = ['dtm']
+        try:
+            socket_type, socket_args = args.socket.split(':', 1)
+            if socket_type == 'tcp':
+                host, port = socket_args.split(':')
+                sock = create_connection((host, int(port)), timeout=0.5)
+            elif socket_type == 'unix':
+                sock = socket(AF_UNIX, SOCK_STREAM)
+                sock.connect(socket_args)
+            elif socket_type == 'ftdi':
+                if not JtagFtdiController:
+                    argparser.error(f'Cannot use PyFdti; {_FTDI_ERR}')
+                pyver = tuple(map(int, PyFtdiVersion.split('.')[:2]))
+                if pyver < PYFTDI_MIN_VER:
+                    argparser.error(f'PyFtdi version {PYFTDI_MIN_VER[0]}.'
+                                    f'{PYFTDI_MIN_VER[1]}+ required')
+                sock = None
+                main_loggers.append('pyftdi.jtag')
+            else:
+                raise ValueError(f'Invalid socket type {socket_type}')
+        except Exception as exc:
+            raise RuntimeError(f'Cannot connect to {args.socket}: '
+                               f'{exc}') from exc
+
+        log = configure_loggers(args.verbose, *main_loggers, -1, 'jtag',
+                                funcname=True, name_width=20)[0]
+
+        if sock:
+            sock.settimeout(0.1)
+            ctrl = JtagBitbangController(sock)
+            trst = True
+        else:
+            ctrl = JtagFtdiController()
+            ctrl.configure(args.socket, frequency=4000000, direction=0x60eb,
+                           initial=0x00e8)
+            trst = False
+        eng = JtagEngine(ctrl)
+        ctrl.tap_reset(trst)
+        ir_length = args.ir_length
+        if args.dtmcs:
+            DTMCS.ADDRESS = args.dtmcs
+        if args.dmi:
+            DMI.ADDRESS = args.dmi
+        dtm = DebugTransportModule(eng, ir_length)
+        rvdm = None
+
+        if args.idle:
+            log.info('Idling for %.1f seconds', args.idle[0])
+            sleep(args.idle[0])
+
+        try:
+            if args.info:
+                code = idcode(eng, args.idcode, ir_length)
+                print(f'IDCODE:    0x{code:x}')
+                version = dtm['dtmcs'].dmi_version
+                abits = dtm['dtmcs'].abits
+                print(f'DTM:       v{version[0]}.{version[1]}, {abits} bits')
+                dtm['dtmcs'].check()
+            dtm['dtmcs'].dmireset()
+            if args.csr_check is not None and not args.csr:
+                argparser.error('CSR check requires CSR option')
+            if args.csr:
+                if not rvdm:
+                    rvdm = DebugModule(dtm, args.base)
+                    rvdm.initialize()
+                # it may take some time for a hart to be initialized and to
+                # be up and running as HW initialization (ROM check, etc.)
+                # takes time. Wait for the hart to become available before
+                # attempting to halt it
+                timeout = now() + 2.0
+                while now() < timeout:
+                    if rvdm.is_available:
+                        break
+                    sleep(0.1)
+                else:
+                    raise ValueError('Hart did not become available')
+                rvdm.halt()
+                dmver = rvdm.status['version']
+                if args.info:
+                    print(f'DM:        {dmver.name}')
+                sbver = rvdm.system_bus_info['sbversion']
+                if args.info:
+                    print(f'SYSBUS:    {sbver.name}')
+                if not args.csr:
+                    csr = 'misa'
+                else:
+                    try:
+                        csr = HexInt.parse(args.csr)
+                    except ValueError:
+                        csr = args.csr
+                csr_val = rvdm.read_csr(csr)
+                if not args.no_exec:
+                    rvdm.resume()
+                if args.csr_check is not None:
+                    if csr_val != args.csr_check:
+                        raise RuntimeError(f'CSR {args.csr} check failed: '
+                                           f'0x{csr_val:08x} != '
+                                           f'0x{args.csr_check:08x}')
+                else:
+                    pad = ' ' * (10 - len(args.csr))
+                    print(f'{args.csr}:{pad}0x{csr_val:08x} (0b{csr_val:032b})')
+            if args.mem:
+                if args.address is None:
+                    argparser.error('no address specified for memory operation')
+                if args.mem == 'write':
+                    if not any((args.data, args.file)):
+                        argparser.error('no file nor data specified for mem '
+                                        'write operation')
+                    if all((args.data, args.file)):
+                        argparser.error('file and data options are mutually '
+                                        'exclusive')
+                if args.mem == 'read':
+                    if not args.size:
+                        argparser.error('no size specified for mem read '
+                                        'operation')
+                    if args.data:
+                        argparser.error('data option not supported for mem read'
+                                        ' operation')
+                if not rvdm:
+                    rvdm = DebugModule(dtm, args.base)
+                    rvdm.initialize()
+                if args.file:
+                    mode = 'rb' if args.mem == 'write' else 'wb'
+                    with open(args.file, mode) as mfp:
+                        rvdm.memory_copy(mfp, args.mem, args.address,
+                                         args.size, no_check=args.fast_mode)
+                elif args.data:
+                    try:
+                        if args.data.startswith(':'):
+                            bvalue = unhexlify(args.data[1:])
+                        else:
+                            bvalue = int(args.data, 0).to_bytes(args.size or 4,
+                                                                'little')
+                    except ValueError as exc:
+                        raise ValueError(f'Invalid value: {exc}') from exc
+                    bpadlen = len(bvalue) % 4
+                    if bpadlen:
+                        bvalue = b''.join((bvalue, bytes(4 - bpadlen)))
+                    if args.size and args.size != len(bvalue):
+                        raise ValueError('Invalid size')
+                    mfp = BytesIO(bvalue)
+                    rvdm.memory_copy(mfp, args.mem, args.address,
+                                     len(bvalue), no_check=args.fast_mode)
+                else:
+                    mfp = BytesIO()
+                    rvdm.memory_copy(mfp, args.mem, args.address, args.size,
+                                     no_check=args.fast_mode)
+                    dump_buffer(mfp, args.address)
+            if args.elf:
+                if ElfBlob.ELF_ERROR:
+                    argparser.error('pyelftools module not available')
+                elf = ElfBlob()
+                elf.load(args.elf)
+                args.elf.close()
+                if elf.address_size != 32:
+                    argparser.error('Only ELF32 files are supported')
+                if not rvdm:
+                    rvdm = DebugModule(dtm, args.base)
+                    rvdm.initialize()
+                try:
+                    rvdm.halt()
+                    mfp = BytesIO(elf.blob)
+                    rvdm.memory_copy(mfp, 'write', elf.load_address, args.size,
+                                     no_check=args.fast_mode)
+                    if args.execute:
+                        rvdm.set_pc(elf.entry_point)
+                finally:
+                    if args.execute or not args.no_exec:
+                        rvdm.resume()
+            else:
+                if args.execute:
+                    argparser.error('Cannot execute without loaded an ELF file')
+        finally:
+            if args.terminate:
+                if len(args.idle or []) > 1:
+                    log.info('Idling for %.1f seconds', args.idle[1])
+                    sleep(args.idle[1])
+                ctrl.quit()
+
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'{linesep}Error: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/earlgrey-ocd.cfg b/scripts/opentitan/earlgrey-ocd.cfg
new file mode 100644
index 0000000000000..bb89dec41d576
--- /dev/null
+++ b/scripts/opentitan/earlgrey-ocd.cfg
@@ -0,0 +1,16 @@
+# OpenTitan machine
+# Openocd configuration file for use with `-jtag tcp::3335` option
+
+adapter driver remote_bitbang
+remote_bitbang host localhost
+remote_bitbang port 3335
+
+transport select jtag
+
+set _CHIPNAME riscv
+# part 0, ver 0, lowRISC
+set _CPUTAPID 0x00001cdf
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
diff --git a/scripts/opentitan/flashgen.py b/scripts/opentitan/flashgen.py
new file mode 100755
index 0000000000000..a4796cfefdfe4
--- /dev/null
+++ b/scripts/opentitan/flashgen.py
@@ -0,0 +1,127 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Create/update an OpenTitan backend flash file.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, FileType
+from os import rename
+from os.path import dirname, exists, isfile, join as joinpath, normpath
+from traceback import format_exc
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ot.eflash.gen import FlashGen
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt
+
+
+def main():
+    """Main routine"""
+    debug = True
+    banks = list(range(FlashGen.NUM_BANKS))
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        img = argparser.add_argument_group(title='Image')
+        img.add_argument('flash', nargs=1, metavar='flash',
+                         help='virtual flash file')
+        img.add_argument('-D', '--discard', action='store_true',
+                               help='Discard any previous flash file content')
+        img.add_argument('-a', '--bank', type=int, choices=banks,
+                         default=banks[0],
+                         help=f'flash bank for data (default: {banks[0]})')
+        img.add_argument('-s', '--offset', type=HexInt.parse,
+                         default=FlashGen.CHIP_ROM_EXT_SIZE_MAX,
+                         help=f'offset of the BL0 file (default: '
+                              f'0x{FlashGen.CHIP_ROM_EXT_SIZE_MAX:x})')
+        files = argparser.add_argument_group(title='Files')
+        files.add_argument('-x', '--exec', type=FileType('rb'), metavar='file',
+                           help='rom extension or application')
+        files.add_argument('-X', '--exec-elf', metavar='elf',
+                           help='ELF file for rom extension or application, '
+                                'for symbol tracking (default: auto)')
+        files.add_argument('-b', '--boot', type=FileType('rb'),
+                           metavar='file', help='bootloader 0 file')
+        files.add_argument('-B', '--boot-elf', metavar='elf',
+                           help='ELF file for bootloader, for symbol tracking'
+                                ' (default: auto)')
+        files.add_argument('-t', '--otdesc', action='append', default=[],
+                           help='OpenTitan style file descriptor, '
+                                'may be repeated')
+        files.add_argument('-T', '--ignore-time', action='store_true',
+                           help='Discard time checking on ELF files')
+        files.add_argument('-U', '--unsafe-elf', action='store_true',
+                           help='Discard sanity checking on ELF files')
+        files.add_argument('-A', '--accept-invalid', action='store_true',
+                           help='Blindly accept invalid input files')
+        extra = argparser.add_argument_group(title='Extra')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'flashgen', 'elf')
+
+        use_bl0 = bool(args.boot) or len(args.otdesc) > 1
+        gen = FlashGen(args.offset if use_bl0 else 0, args.unsafe_elf,
+                       args.accept_invalid, args.ignore_time)
+        flash_pathname = args.flash[0]
+        backup_filename = None
+        if args.otdesc and any(filter(None, (args.bank,
+                                             args.boot, args.boot_elf,
+                                             args.exec, args.exec_elf))):
+            argparser.error('OT file descriptor mode is mutually exclusive '
+                            'with boot and exec options')
+        if args.boot_elf:
+            if not args.boot:
+                argparser.error('Bootloader ELF option requires bootloader '
+                                'binary')
+            if not isfile(args.boot_elf):
+                argparser.error('No such Bootloader ELF file')
+        if args.exec_elf:
+            if not args.exec:
+                argparser.error('Application ELF option requires application '
+                                'binary')
+            if not isfile(args.exec_elf):
+                argparser.error('No such Bootloader ELF file')
+        try:
+            if args.discard:
+                if exists(flash_pathname):
+                    backup_filename = f'{flash_pathname}.bak'
+                    rename(flash_pathname, backup_filename)
+            gen.open(args.flash[0])
+            if args.exec:
+                gen.store_rom_ext(args.bank, args.exec, args.exec_elf)
+            if args.boot:
+                gen.store_bootloader(args.bank, args.boot, args.boot_elf)
+            if args.otdesc:
+                gen.store_ot_files(args.otdesc)
+            backup_filename = None
+        finally:
+            gen.close()
+            if backup_filename:
+                print('Restoring previous file after error', file=sys.stderr)
+                rename(backup_filename, flash_pathname)
+
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/gdbreplay.py b/scripts/opentitan/gdbreplay.py
new file mode 100755
index 0000000000000..31c13d0445d54
--- /dev/null
+++ b/scripts/opentitan/gdbreplay.py
@@ -0,0 +1,718 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU GDB replay.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, FileType, Namespace
+from binascii import hexlify
+from logging import getLogger
+from os import linesep
+from os.path import dirname, isfile, join as joinpath, normpath
+from socket import (SOL_SOCKET, SO_REUSEADDR, SHUT_RDWR, socket,
+                    timeout as LegacyTimeoutError)
+from string import ascii_uppercase
+from traceback import format_exc
+from typing import BinaryIO, Optional, TextIO, Union
+import re
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ot.util.elf import ElfBlob
+from ot.util.log import configure_loggers
+
+
+class QEMUMemoryController:
+    """Memory controller.
+
+       Store known memory content in banks.
+    """
+
+    def __init__(self):
+        self._log = getLogger('gdbrp.mem')
+        self._banks: dict[tuple(int, int), bytes] = {}
+
+    def add_memory(self, addr: int, blob: bytes) -> None:
+        """Add a new memory bank.
+
+           :param addr: absolute address of the first memory cell
+           :param blob: memory content
+        """
+        length = len(blob)
+        rng = range(addr, addr+length)
+        self._banks[rng] = blob
+
+    def read(self, addr: int, length: int) -> bytes:
+        """Read the content of a memory region.
+
+           Note that the returned memory blob may be shorter than the requested
+           length (to match GDB behaviour)
+
+           :param addr: absolute address of the first cell to read out
+           :param length: count of bytes to read
+           :return: the memory blob as a byte sequence
+           :raise IndexError: if the selected address is not mapped
+        """
+        for rng, data in self._banks.items():
+            if addr not in rng:
+                continue
+            offset = addr-rng.start
+            self._log.debug('Mem section [%08x..%08x]', rng.start, rng.stop)
+            return bytes(data[offset:offset+length])
+        raise IndexError('Invalid memory address')
+
+
+class QEMUVCPU:
+    """Virtual CPU storage.
+
+       :param memctrl: memory controller
+    """
+
+    # pylint: disable=invalid-name
+
+    PC_XPOS = 32
+    """Index of the PC in the GPR sequence, starting from x0."""
+
+    def __init__(self, memctrl: QEMUMemoryController):
+        self._log = getLogger('gdbrp.vcpu')
+        self._seq: list[tuple[int, str]] = []
+        self._regs: list[Optional[int]] = [None] * 33
+        self._xpos = 0
+        self._memctrl = memctrl
+        self._hwbreaks: list[range] = []
+
+    def record(self, pc: int, func: Optional[str]) -> None:
+        """Record execution of a single instruction.
+
+           :param pc: the address of the instruction
+           :param func: the name of the executed function, if any
+        """
+        self._seq.append((pc, func))
+
+    def reset(self) -> None:
+        """Restart the execution of the vCPU to the very first registered
+           instruction.
+        """
+        self._xpos = 0
+
+    def step(self, back: bool = False) -> None:
+        """Advance a single vCPU instruction.
+
+           :param back: whether to step back or next (default)
+           :raise RuntimeError: if there are not more recorded instructions to
+                                'execute'
+        """
+        if not back:
+            self._xpos += 1
+            if self._xpos >= len(self._seq):
+                raise RuntimeError('Reached end of exec stream')
+        else:
+            if self._xpos > 0:
+                self._xpos -= 1
+            else:
+                raise RuntimeError('Reached start of exec stream')
+
+    def cont(self, back: bool = False, addr: Optional[int] = None) -> bool:
+        """Continue execution of instruction stream till either a HW breakpoint
+           or the end of the execution stream is reached.
+
+           :param back: wether to execute backward or forward (default)
+           :param addr: the address to resume from. A PC following the current
+                        execution matching this address is only looked up in
+                        the selected direction
+           :return: True if a HW breakpoint has been reached, False otherwise
+        """
+
+        if addr is not None:
+            try:
+                self._move_to(addr, not back)
+            except ValueError:
+                self._log.warning('Cannot resume from 0x%08x', addr)
+                self._xpos = len(self._seq)
+        last_pc = None
+        while True:
+            try:
+                self.step(back)
+            except RuntimeError as exc:
+                self._log.warning('%s', exc)
+                break
+            _ = self.instruction_length
+            pc = self.pc
+            if pc == last_pc:
+                continue
+            last_pc = pc
+            for hwp, hwb in enumerate(self._hwbreaks, start=1):
+                if pc in hwb:
+                    self._log.info('Breakpoint #%d @ %08x', hwp, pc)
+                    return True
+        return False
+
+    def add_hw_break(self, addr: int, length: int):
+        """Add a HW breakpoint.
+
+           :param addr: absolute address of the HW breakpoint
+           :param length: count of bytes starting from the address
+           :raise ValueError: if another breakpoint exists at this location
+        """
+        rng = range(addr, addr+length)
+        if rng in self._hwbreaks:
+            raise ValueError('Duplicate breakpoint')
+        self._hwbreaks.append(rng)
+        self._log.info('Add HW breakpoint on [%08x:%08x[', rng.start, rng.stop)
+
+    def del_hw_break(self, addr: int, length: int):
+        """Remove an existing HW breakpoint.
+
+           :param addr: absolute address of the HW breakpoint
+           :param length: count of bytes starting from the address
+           :raise ValueError: if no breakpoint exists at this location
+        """
+        rng = range(addr, addr+length)
+        try:
+            self._hwbreaks.remove(rng)
+            self._log.info('Remove HW breakpoint from [%08x:%08x[',
+                           rng.start, rng.stop)
+        except ValueError as exc:
+            raise ValueError('Non-existent breakpoint') from exc
+
+    @property
+    def instruction_count(self) -> int:
+        """Return the count of recorded instructions.
+
+           :return: the count of recorded instructions.
+        """
+        return len(self._seq)
+
+    @property
+    def instruction_length(self) -> int:
+        """Return the length of the current instruction.
+
+           :return: the length of the instruction (either 2 or 4)
+        """
+        return self._get_instruction_length(self.pc)
+
+    @property
+    def pc(self) -> int:
+        """Return the current instruction.
+
+           Note that the instruction may not be valid if execution point has
+           reached past the point of the latest recorded instruction.
+
+           :return: the instruction
+        """
+        if self._xpos < len(self._seq):
+            return self._seq[self._xpos][0]
+        last_pc = self._seq[-1][0]
+        return last_pc + self._get_instruction_length(last_pc)
+
+    @property
+    def regs(self) -> list[int]:
+        """Return the values of the GPRs.
+
+           This is a requirement of GDB.
+
+           There are all set to 0 for now, except the PC.
+        """
+        self._regs[-1] = self.pc
+        return self._regs
+
+    def _move_to(self, pc: int, forward: bool) -> None:
+        """Change execution point to the selected PC.
+
+           Note that there are many execution points that may contain the
+           selected PC in the execution stream, this function only reaches the
+           closest one toward the selected execution direction.
+
+           :param pc: the PC address to locate and execution point to
+           :param foward: whether to look forward or backward the current
+                          execution point
+           :raise ValueError: if no such PC is found
+        """
+        pos = self._xpos
+        if forward:
+            while pos < len(self._seq):
+                if self._seq[pos][0] == pc:
+                    self._xpos = pos
+                    self._log.info('Forward to PC %08x @ %d', pc, pos)
+                    return
+                pos += 1
+        else:
+            while pos >= 0:
+                if self._seq[pos][0] == pc:
+                    self._xpos = pos
+                    self._log.info('Rewind to PC %08x @ %d', pc, pos)
+                    return
+                pos -= 1
+        raise ValueError(f'No such address: 0x{pc:08x}')
+
+    def _get_instruction_length(self, pc: int) -> int:
+        """Return the length of the instruction at the specified address.
+
+           Note that if the selected address is not found, the default
+           instruction size (4) is returned.
+
+           :return: the length of the instruction (either 2 or 4)
+        """
+        try:
+            instr = int.from_bytes(self._memctrl.read(pc, 4), 'little')
+        except IndexError:
+            self._log.error('Invalid PC @ %d', self._xpos)
+            return 4
+        length = 4 if instr & 0x3 else 2
+        opcode = f'{instr:08x}' if length == 4 else f'{instr & 0xffff:04x}'
+        self._log.info('Instruction @ 0x%08x: %s', pc, opcode)
+        return length
+
+
+class QEMUGDBReplay:
+    """Tiny GDB server that replays a logged QEMU guest execution stream.
+
+       :param rv64: RV64 vs. RV32
+    """
+
+    DEFAULT_SERVICE = 'localhost:3333'
+    """Default TCP host:port to serve GDB remote clients."""
+
+    MAX_PACKET_LENGTH = 4096
+    """Maximum packet size."""
+
+    # Trace 0: 0x280003d00 [00000000/00008c9a/00101003/ff020000] _boot_start
+    TCRE = re.compile(r'^Trace\s(\d+):\s0x[0-9a-f]+\s\[[0-9a-f]+/([0-9a-f]+)'
+                      r'/[0-9a-f]+/[0-9a-f]+\](?:\s([&,<>\s\w:]+))?\s*$')
+    """Regex to parse QEMU execution trace from a QEMU log file."""
+
+    SIGNALS = {
+        'HUP': 1,
+        'INT': 2,
+        'QUIT': 3,
+        'ILL': 4,
+        'TRAP': 5,
+        'ABRT': 6
+    }
+    """GDB signals."""
+
+    def __init__(self, rv64: Optional[bool] = None):
+        self._log = getLogger('gdbrp')
+        self._rv64 = rv64
+        self._xlen = 8 if rv64 else 4
+        self._thread_id: Optional[int] = None
+        self._select_thread_id: Optional[int] = None
+        self._conn: Optional[socket] = None
+        self._no_ack = False
+        self._vcpus: dict[int, QEMUVCPU] = {}
+        self._memctrl = QEMUMemoryController()
+
+    @property
+    def xlen(self) -> int:
+        """Return current XLEN, default to RV32.
+
+           :return: xlen in bytes
+        """
+        return self._xlen or 4
+
+    def load(self, qfp: TextIO, cpus: Optional[list[int]] = None) -> None:
+        """Load a recorded execution stream from a QEMU log file.
+           see QEMU `-d exec` option.
+
+           :param qfp: text stream to parse
+        """
+        threshold = 10
+        for lno, line in enumerate(qfp, start=1):
+            tmo = self.TCRE.match(line)
+            if not tmo:
+                continue
+            scpu, spc, func = tmo.groups()
+            if lno > threshold:
+                threshold *= 10
+            if not lno % threshold:
+                self._log.debug('Parsed %d lines', lno)
+            xcpu = int(scpu)
+            if cpus and xcpu not in cpus:
+                continue
+            xpc = int(spc, 16)
+            if xcpu not in self._vcpus:
+                self._vcpus[xcpu] = QEMUVCPU(self._memctrl)
+            self._vcpus[xcpu].record(xpc, func)
+        qfp.close()
+        if not self._vcpus:
+            raise RuntimeError('Unable to find QEMU execution traces')
+        for vix, vcpu in self._vcpus.items():
+            self._log.info('CPU %d: %d instructions',
+                           vix, vcpu.instruction_count)
+            vcpu.reset()
+
+    def load_bin(self, address: int, bfp: BinaryIO) -> None:
+        """Load an application from a binary stream.
+
+           :param address: the address of the first byte in memory
+           :param bfp: the binary stream
+        """
+        blob = bfp.read()
+        # note: for now, overlapping memories are not managed
+        self._memctrl.add_memory(address, blob)
+
+    def load_elf(self, elf: BinaryIO) -> None:
+        """Load an application from a ELF stream.
+
+           :param elf: the ELF stream
+        """
+        blob = ElfBlob()
+        blob.load(elf)
+        if not self._xlen:
+            self._xlen = blob.address_size // 8
+        elif blob.address_size != self._xlen * 8:
+            raise ValueError('Wrong ELF file type (XLEN)')
+        # note: for now, overlapping memories are not managed
+        self._memctrl.add_memory(blob.load_address, blob.blob)
+
+    def serve(self, gdb: str) -> None:
+        """Serve GDB client requests.
+
+           :param gdb: TCP host:port description string.
+        """
+        devdesc = gdb.split(':')
+        try:
+            port = int(devdesc[1])
+        except TypeError as exc:
+            raise ValueError('Invalid TCP serial device') from exc
+        if not 0 < port < 65536:
+            raise ValueError('Invalid TCP port')
+        tcpdev = (devdesc[0], port)
+        gdbs = socket()
+        gdbs.setsockopt(SOL_SOCKET, SO_REUSEADDR, 1)
+        gdbs.bind(tcpdev)
+        while True:
+            gdbs.listen()
+            self._conn, peer = gdbs.accept()
+            self._log.info('Remote connection from %s:%d', *peer)
+            with self._conn:
+                self._conn.settimeout(0.1)
+                try:
+                    self._serve()
+                except OSError:
+                    break
+            self._conn = None
+
+    def _serve(self):
+        """Serve GDB request from a single client/connection.
+        """
+        buf = bytearray()
+        while self._conn:
+            try:
+                data = self._conn.recv(self.MAX_PACKET_LENGTH)
+            except (TimeoutError, LegacyTimeoutError):
+                continue
+            if not data:
+                continue
+            buf.extend(data)
+            start = buf.find(b'$')
+            if start < 0:
+                continue
+            end = buf.find(b'#', start)
+            if end < 0:
+                continue
+            if len(buf)-end < 2:
+                continue
+            req = buf[start+1:end]
+            crc = int(buf[end+1:end+3], 16)
+            buf = req[end+3:]
+            self._log.info('Request %s', bytes(req))
+            if not self._no_ack:
+                if sum(req) & 0xff != crc:
+                    self._log.error('Invalid CRC')
+                    self._conn.send(b'-')
+                else:
+                    self._conn.send(b'+')
+            self._handle_request(req)
+
+    def _handle_request(self, req: bytearray):
+        """Dispatch incoming GDB request.
+
+           :param req: the byte request received from the remote client.
+        """
+        for clen in 1, 2:
+            cmd = bytes(req[0:clen]).decode()
+            cmd = {'?': 'interrogate'}.get(cmd, cmd)
+            if cmd in ascii_uppercase:
+                cmd = f'_{cmd.lower()}'
+            handler = getattr(self, f'_do_{cmd}', None)
+            if handler:
+                break
+        else:
+            self._send('')
+            return
+        # pylint: disable=not-callable
+        resp = handler(bytes(req[clen:]))
+        if resp is not None:
+            self._send(resp)
+
+    def _send(self, payload: str):
+        """Send a reply to the remote GDB client.
+
+           :param payload: the string to send
+        """
+        self._log.info('Reply: "%s"', payload)
+        self._send_bytes(payload.encode())
+
+    def _send_bytes(self, payload: Union[bytes, bytearray]):
+        """Send a reply to the remote GDB client.
+
+           :param payload: the byte sequence to send
+        """
+        if not isinstance(payload, (bytes, bytearray)):
+            raise TypeError('Invalid payload type')
+        if self._conn:
+            crc = sum(payload) & 0xff
+            bcrc = f'{crc:02x}'.encode()
+            resp = b''.join((b'$', payload, b'#', bcrc))
+            self._log.debug('< %s', resp)
+            self._conn.send(resp)
+
+    def _do_interrogate(self, *_) -> str:
+        """Query current status."""
+        return 'S00'
+
+    def _do_bc(self, *_: bytes):
+        """Continue backward."""
+        vcpu = self._vcpus[self._thread_id]
+        hwbreak = vcpu.cont(True)
+        if hwbreak:
+            xpc = vcpu.pc
+            sig = self.SIGNALS['TRAP']
+            spc = hexlify(xpc.to_bytes(self.xlen, 'little')).decode()
+            return f'T{sig:02x}{vcpu.PC_XPOS:02x}:{spc};hwbreak:;'
+        # reached start of program
+        return 'S00'  # not sure about the expected code
+
+    def _do_c(self, payload: bytes):
+        """Continue."""
+        addr = int(payload) if payload else None
+        vcpu = self._vcpus[self._thread_id]
+        hwbreak = vcpu.cont(False, addr)
+        if hwbreak:
+            xpc = vcpu.pc
+            sig = self.SIGNALS['TRAP']
+            spc = hexlify(xpc.to_bytes(self.xlen, 'little')).decode()
+            return f'T{sig:02x}{vcpu.PC_XPOS:02x}:{spc};hwbreak:;'
+        # reached end of program
+        sig = self.SIGNALS['QUIT']
+        return f'S{sig:02x}'
+
+    def _do_g(self, *_):
+        """Get vCPU register values."""
+        # "The bytes with the register are transmitted in target byte order"
+        vcpu = self._vcpus[self._thread_id]
+        return ''.join(hexlify(r.to_bytes(self.xlen, 'little')).decode()
+                       if r is not None else 'xx' * self.xlen
+                       for r in vcpu.regs)
+
+    def _do_k(self, *_):
+        """Kill."""
+        for vcpu in self._vcpus.values():
+            vcpu.reset()
+        self._conn.shutdown(SHUT_RDWR)
+        self._conn.close()
+        self._conn = None
+
+    def _do_q(self, payload: bytes):
+        """Generic query decoder."""
+        parts = payload.split(b':', 1)
+        handler = getattr(self, f'_do_query_{parts[0].decode().lower()}', None)
+        if not handler:
+            return ''
+        # pylint: disable=not-callable
+        return handler(bytes(parts[1]) if len(parts) > 1 else b'')
+
+    def _do_m(self, payload: bytes) -> str:
+        """Read memory."""
+        addr, length = (int(x, 16) for x in payload.decode().split(',', 1))
+        self._log.info('Read mem [%08x..%08x]', addr, addr+length)
+        try:
+            data = self._memctrl.read(addr, length)
+        except IndexError:
+            return 'E01'
+        return hexlify(data).decode()
+
+    def _do_s(self, payload: bytes) -> str:
+        """Step instruction."""
+        vcpu = self._vcpus[self._thread_id]
+        if not payload:
+            vcpu.step()
+            addr = vcpu.pc
+            haddr = hexlify(addr.to_bytes(self.xlen, 'little')).decode()
+            sig = self.SIGNALS['TRAP']
+            return f'T{sig:02x}{vcpu.PC_XPOS:02x}:{haddr};'
+        # for now there is no way to jump to another PC location
+        return 'E01'
+
+    def _do_bs(self, *_: bytes) -> str:
+        """Step back instruction."""
+        vcpu = self._vcpus[self._thread_id]
+        vcpu.step(True)
+        addr = vcpu.pc
+        haddr = hexlify(addr.to_bytes(self.xlen, 'little')).decode()
+        sig = self.SIGNALS['TRAP']
+        return f'T{sig:02x}{vcpu.PC_XPOS:02x}:{haddr};'
+
+    def _do__h(self, payload: bytes) -> str:
+        """Select thread."""
+        cmd = payload[0:1]
+        if cmd in b'GgMmc':
+            try:
+                tid = int(payload[1:], 16)
+            except (TypeError, ValueError):
+                self._log.error('Unsupported thread id %s', payload[1:])
+                return 'E01'
+            if tid != -1 and tid not in self._vcpus:
+                self._log.warning('Unknown thread id %d ignored', tid)
+                return 'E02'
+            self._select_thread_id = tid
+            if tid <= 0:
+                self._thread_id = sorted(self._vcpus)[0]
+            return 'OK'
+        return 'E03'
+
+    def _do_z(self, payload: bytes) -> str:
+        """Remove breakpoint."""
+        return self._do__z(payload, True)
+
+    def _do__z(self, payload: bytes, remove=False) -> str:
+        """Add breakpoint."""
+        parts = payload.split(b';')
+        if len(parts) > 1:
+            self._log.warning('Conditional breakpoint not supported')
+            return ''
+        try:
+            kind, addr, length = (int(x, 16) for x in parts[0].split(b','))
+        except ValueError:
+            self._log.error('Invalid debug request')
+            return 'E01'
+        if kind != 1:
+            self._log.warning('Only hw breakpoint are supported')
+            return ''
+        vcpu = self._vcpus[self._thread_id]
+        try:
+            if not remove:
+                vcpu.add_hw_break(addr, length)
+            else:
+                vcpu.del_hw_break(addr, length)
+            return 'OK'
+        except ValueError:
+            return 'E02'
+
+    def _do_query_c(self, *_) -> str:
+        return f'QC{self._thread_id}'
+
+    def _do_query_supported(self, payload: bytes) -> str:
+        """Query supported features."""
+        req = payload.decode()
+        resp = [f'PacketSize={self.MAX_PACKET_LENGTH-16:x}',
+                'ReverseStep+', 'ReverseContinue+']
+        for cap in req.split(';'):
+            supp = cap in ('hwbreak+')
+            self._log.info('Query support for %s: %s',
+                           cap, 'Y' if supp else 'N')
+            if supp:
+                resp.append(cap)
+        return ';'.join(resp)
+
+    def _do_query_symbol(self, *_) -> str:
+        """Target does not need to lookup symbol."""
+        return 'OK'
+
+    def _do_query_tstatus(self, *_) -> str:
+        """Query stop reason."""
+        return 'T0;tnotrun:0'
+
+    def _do_query_fthreadinfo(self, *_) -> str:
+        """Query thread id, i.e. HW vCPUs identifiers."""
+        resp = ';'.join((f'{x:x}' for x in sorted(self._vcpus)))
+        return f'm{resp}'
+
+    def _do_query_sthreadinfo(self, *_) -> str:
+        """End of thread query."""
+        return 'l'
+
+    def _do_query_attached(self, *_) -> str:
+        """Query program status."""
+        return '0'  # or '1' ?
+
+
+def main():
+    """Main routine"""
+    debug = True
+    qemu_path = normpath(joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                                  'build', 'qemu-system-riscv32'))
+    if not isfile(qemu_path):
+        qemu_path = None
+    try:
+        args: Optional[Namespace] = None
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('-t', '--trace', metavar='LOG',
+                               type=FileType('rt'),
+                               help='QEMU execution trace log')
+        argparser.add_argument('-e', '--elf', action='append',
+                               type=FileType('rb'),
+                               help='ELF application')
+        argparser.add_argument('-c', '--cpu', action='append', type=int,
+                               help='Only consider selected CPUs')
+        argparser.add_argument('-a', '--address', action='append',
+                               type=lambda x: int(x, 16 if x[1:2].lower() == 'x'
+                                                  else 10),
+                               help='Address to load each specified binary')
+        argparser.add_argument('-b', '--bin', action='append',
+                               type=FileType('rb'),
+                               help='Binary application')
+        argparser.add_argument('-g', '--gdb',
+                               default=QEMUGDBReplay.DEFAULT_SERVICE,
+                               help=f'GDB server '
+                               f'(default to {QEMUGDBReplay.DEFAULT_SERVICE})')
+        argparser.add_argument('-v', '--verbose', action='count',
+                               help='increase verbosity')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'gdbrp', 'elf')
+
+        acount = len(args.address or [])
+        bcount = len(args.bin or [])
+        if acount != bcount:
+            argparser.error('Expecting same count of address and bin args')
+
+        gdbr = QEMUGDBReplay()
+        if args.elf:
+            if ElfBlob.ELF_ERROR:
+                argparser.error('Please install PyElfTools package')
+            for elf in args.elf:
+                gdbr.load_elf(elf)
+        if args.bin:
+            for addr, blob in zip(args.address, args.bin):
+                gdbr.load_bin(addr, blob)
+        if args.trace:
+            gdbr.load(args.trace, args.cpu)
+
+        gdbr.serve(args.gdb)
+
+        sys.exit(0)
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'{linesep}Error: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/gpiodev.py b/scripts/opentitan/gpiodev.py
new file mode 100755
index 0000000000000..b03fb44219c0b
--- /dev/null
+++ b/scripts/opentitan/gpiodev.py
@@ -0,0 +1,82 @@
+#!/usr/bin/env python3
+
+"""GPIO device tiny simulator.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+# Copyright (c) 2024 Rivos, Inc.
+# All rights reserved.
+
+from argparse import ArgumentParser, FileType
+from os.path import dirname, join as joinpath, normpath
+from traceback import format_exc
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ot.gpio.device import GpioDevice
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt
+
+
+def main():
+    """Main routine.
+    """
+    debug = False
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('-p', '--port', type=int, default=8007,
+                               help='remote host TCP port (defaults to 8007)')
+        argparser.add_argument('-c', '--check', type=FileType('rt'),
+                               help='input file to check command sequence')
+        argparser.add_argument('-r', '--record', type=FileType('wt'),
+                               help='output file to record command sequence')
+        argparser.add_argument('-e', '--end', type=HexInt.parse,
+                               help='emit the specified value to trigger '
+                                    'remote exit on last received command')
+        argparser.add_argument('-q', '--quit-on-error', action='store_true',
+                               default=False, help='exit on first error')
+        argparser.add_argument('-s', '--single', action='store_true',
+                               default=False,
+                               help='run once: terminate once first remote '
+                                    'disconnects')
+        argparser.add_argument('-t', '--log-time', action='store_true',
+                               default=False, help='emit time in log messages')
+        argparser.add_argument('-v', '--verbose', action='count',
+                               help='increase verbosity')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'gpio', ms=args.log_time)
+
+        if args.end and not args.check:
+            argparser.error('Auto-end cannot be enabled without a check file')
+
+        gpio = GpioDevice()
+        if args.check:
+            gpio.load(args.check)
+        try:
+            exec_ok = gpio.run(args.port, args.single, args.quit_on_error,
+                               args.end)
+        finally:
+            if args.record:
+                gpio.save(args.record)
+        sys.exit(int(not exec_ok))
+
+    except (IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/keymgr-dpe.py b/scripts/opentitan/keymgr-dpe.py
new file mode 100755
index 0000000000000..e4ae9d1fb2115
--- /dev/null
+++ b/scripts/opentitan/keymgr-dpe.py
@@ -0,0 +1,144 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU OT tool to generate Key Manager DPE keys.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+# pylint: disable=invalid-name
+# pylint: enable=invalid-name
+
+from argparse import ArgumentParser, FileType
+from os.path import dirname, join as joinpath, normpath
+from traceback import format_exception
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+# ruff: noqa: E402
+from ot.km.dpe import KeyManagerDpe
+from ot.km.engine import KeyManagerDpeEngine
+from ot.otp.image import OtpImage
+from ot.util.arg import ArgError
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt
+
+
+def main():
+    """Main routine"""
+    debug = True
+    desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+    argparser = ArgumentParser(description=f'{desc}.')
+    try:
+
+        files = argparser.add_argument_group(title='Files')
+        files.add_argument('-c', '--config', type=FileType('rt'),
+                           metavar='CFG', required=True,
+                           help='input QEMU OT config file')
+        files.add_argument('-j', '--otp-map', type=FileType('rt'),
+                           metavar='HJSON', required=True,
+                           help='input OTP controller memory map file')
+        files.add_argument('-l', '--lifecycle', type=FileType('rt'),
+                           metavar='SV',
+                           help='input lifecycle system verilog file')
+        files.add_argument('-m', '--vmem', type=FileType('rt'),
+                           help='input VMEM file')
+        files.add_argument('-R', '--raw', type=FileType('rb'),
+                           help='input QEMU OTP raw image file')
+        files.add_argument('-r', '--rom', type=FileType('rb'), action='append',
+                           help='input ROM image file, may be repeated')
+
+        params = argparser.add_argument_group(title='Parameters')
+        params.add_argument('-e', '--ecc', type=int,
+                            default=OtpImage.DEFAULT_ECC_BITS,
+                            metavar='BITS',
+                            help=f'ECC bit count (default: '
+                                 f'{OtpImage.DEFAULT_ECC_BITS})')
+        params.add_argument('-z', '--rom-size', metavar='SIZE',
+                            type=HexInt.xparse,
+                            action='append', default=[],
+                            help='ROM image size in bytes, may be repeated')
+
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+
+        subparsers = argparser.add_subparsers(help='Execution mode',
+                                              dest='exec')
+
+        genparser = subparsers.add_parser('generate', help='generate a key')
+        genparser.add_argument('-b', '--swbindings', action='append',
+                               default=[], metavar='HEXSTR',
+                               help='SW bindings, may be repeated')
+        genparser.add_argument('-g', '--gen-out', choices=KeyManagerDpe.OUTPUTS,
+                               help='generation output (default: auto)')
+        genparser.add_argument('-k', '--key-version', metavar='HEXSTR',
+                               type=HexInt, required=True,
+                               help='Key version')
+        genparser.add_argument('-o', '--output',
+                               help='output file with generated key')
+        genparser.add_argument('-R', '--rust-const', metavar='NAME',
+                               help='Rust constant name for the generated key')
+        genparser.add_argument('-s', '--salt', default=[], metavar='HEXSTR',
+                               required=True,
+                               help='Salt')
+        genparser.add_argument('-t', '--target',
+                               choices=KeyManagerDpe.TARGETS, required=True,
+                               help='destination device')
+
+        exeparser = subparsers.add_parser('execute', help='execute sequence')
+        exeparser.add_argument('-s', '--sequence', metavar='INI', required=True,
+                               type=FileType('rt'),
+                               help='execution sequence definition')
+
+        vrfparser = subparsers.add_parser('verify', help='verify execution log')
+        vrfparser.add_argument('-l', '--exec-log', metavar='LOG', required=True,
+                               type=FileType('rb'),
+                               help='execution log to verify')
+
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'keymgr', 'romimg', -1, 'otp',
+                          name_width=12)
+
+        if not (args.vmem or args.raw):
+            argparser.error('Either VMEM or RAW image file must be specified')
+        if args.vmem and args.raw:
+            argparser.error('Only one of VMEM or RAW image file can be '
+                            'specified')
+
+        if args.exec == 'generate':
+            KeyManagerDpe.from_args(args)
+        else:
+            kmd = KeyManagerDpe.create(
+                args.otp_map, args.ecc, args.vmem, args.raw, args.lifecycle,
+                args.config, args.rom, args.rom_size)
+            kme = KeyManagerDpeEngine(kmd)
+            if args.exec == 'execute':
+                kme.execute(args.sequence)
+            elif args.exec == 'verify':
+                kme.verify(args.exec_log)
+
+    except ArgError as exc:
+        argparser.error(str(exc))
+    except (IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(''.join(format_exception(exc, chain=False)),
+                  file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/lint-commits.sh b/scripts/opentitan/lint-commits.sh
new file mode 100755
index 0000000000000..7232f627687c3
--- /dev/null
+++ b/scripts/opentitan/lint-commits.sh
@@ -0,0 +1,82 @@
+#!/usr/bin/env sh
+# Copyright lowRISC.
+
+# This script checks that commit messages are in the correct format:
+#
+#   1. The title must be of the form `[ot] path/to/change: description`.
+#   2. The message must end with `Signed-off-by: Name <email@address>`.
+#
+# Usage:
+#
+#   lint-commits.sh <first commit>
+
+set -e
+
+# Check the commit title has the correct prefixes.
+lint_title() {
+  commit="$1"
+
+  title="$(git show "$commit" -s --format="format:%s")"
+  short_hash="$(git show "$commit" -s --format="format:%h")"
+
+  example() {
+    echo "Got:"                                                     >&2
+    echo "    ${title}"                                             >&2
+    echo
+    echo "Example:"                                                 >&2
+    echo "    [ot] hw/opentitan: ot_hmac: fix i2c register address" >&2
+  }
+
+  if echo "$title" | grep -P -q '^FROMLIST:'; then
+    exit 0
+  fi
+
+  if ! echo "$title" | grep -P -q '^\[ot\]'; then
+    echo "::error::${short_hash}: commit titles must have the prefix '[ot]'" >&2
+    example
+    exit 1
+  fi
+
+  if ! echo "$title" | grep -P -q '^\[ot\]\s+[^:]+:'; then
+    echo "::error::${short_hash}: commit titles must contain the path of the change" >&2
+    example
+    exit 1
+  fi
+
+  if ! echo "$title" | grep -P -q '^\[ot\]\s+[^:]+:\s+[^:]+:'; then
+    echo "::error::${short_hash}: commit titles must state the changed component" >&2
+    example
+    exit 1
+  fi
+}
+
+# Check the commit is signed off.
+lint_signed_off_by() {
+  commit="$1"
+
+  signed_off_by="$(git show "$commit" -s --format="format:%(trailers:key=Signed-off-by)")"
+  short_hash="$(git show "$commit" -s --format="format:%h")"
+
+  if [ -z "$signed_off_by" ]; then
+    echo "::error::${short_hash}: is missing a 'Signed-off-by' line" >&2
+    echo "Hint:"                                                     >&2
+    echo "Use \`git commit -s\` to add sign-offs"                    >&2
+    exit 1
+  fi
+}
+
+first_commit="$1"
+if [ -z "$first_commit" ]; then
+  echo "Usage: ${0} <first commit>" >&2
+  exit 1
+fi
+
+exit_code=0
+
+# Lint each commit from the merge target to now.
+for commit in $(git log "${first_commit}..HEAD" --format="format:%H" --no-merges); do
+  lint_title "$commit"         || exit_code=1
+  lint_signed_off_by "$commit" || exit_code=1
+done
+
+exit $exit_code
diff --git a/scripts/opentitan/loghelp.py b/scripts/opentitan/loghelp.py
new file mode 100755
index 0000000000000..171f928070329
--- /dev/null
+++ b/scripts/opentitan/loghelp.py
@@ -0,0 +1,127 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Verify register definitions.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, FileType
+from logging import getLogger
+from os.path import basename, dirname, splitext, join as joinpath, normpath
+from traceback import format_exc
+from typing import TextIO
+import re
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ot.util.log import configure_loggers
+
+# pylint: disable=missing-function-docstring
+
+REG_CRE = re.compile(r'^#define ([A-Z][\w]+)_REG_(OFFSET|RESVAL)\s+'
+                     r'((?:0x)?[A-Fa-f0-9]+)(?:\s|$)')
+
+RegisterDefs = dict[str, tuple[int, int]]
+
+
+def parse_defs(hfp: TextIO) -> RegisterDefs:
+    log = getLogger('ot')
+    radix = splitext(basename(hfp.name))[0]
+    radix = radix.rsplit('_', 1)[0]
+    radix_re = f'^{radix.upper()}_'
+    defs = {}
+    for line in hfp:
+        line = line.strip()
+        rmo = REG_CRE.match(line)
+        if not rmo:
+            continue
+        sregname = rmo.group(1)
+        sregkind = rmo.group(2)
+        sregaddr = rmo.group(3)
+        regname = re.sub(radix_re, '', sregname)
+        regval = int(sregaddr, 16 if sregaddr.startswith('0x') else 10)
+        if sregkind == 'OFFSET':
+            defs[regname] = (regval, 0)
+        else:
+            defs[regname] = (defs[regname][0], regval)
+            log.debug("%s @ 0x%x = 0x%x",
+                      regname, defs[regname][0], defs[regname][1])
+    return defs
+
+
+def check(lfp: TextIO, comp: str, defs: RegisterDefs):
+    prefix = f'ot_{comp}_io_'
+    device = {}
+    resvals = {v[0]: v[1] for v in defs.values()}
+    regnames = {v[0]: k for k, v in defs.items()}
+    for line in lfp:
+        line = line.strip()
+        if not line.startswith(prefix):
+            continue
+        parts = line.removeprefix(prefix).split(' ', 1)
+        items = dict(tuple(x.strip().split('=', 1))
+                     for x in parts[1].split(','))
+        vals = {k: int(v, 16) for k, v in items.items()}
+        addr = vals['addr']
+        val = vals['val']
+        if parts[0] == 'write':
+            device[addr] = val
+        else:
+            regname = regnames.get(addr, '?')
+            if addr in device:
+                if val != device[addr]:
+                    print(f'Unexpected value @ 0x{addr:x}: 0x{val:x} '
+                          f'(0x{device[addr]:x}) "{regname}"')
+            elif defs:
+                if addr not in resvals:
+                    print(f'No known reset value @ 0x{addr:x} "{regname}"')
+                elif val != resvals[addr]:
+                    print(f'Reset value differ @ 0x{addr:x}: 0x{val:x} '
+                          f'(0x{resvals[addr]:x}) "{regname}"')
+
+
+def main():
+    """Main routine"""
+    debug = False
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('log', nargs=1, metavar='file',
+                               type=FileType('rt'),
+                               help='log file')
+        argparser.add_argument('-c', '--component', metavar='name',
+                               required=True,
+                               help='name of the OT component in log file')
+        argparser.add_argument('-r', '--reg', metavar='file',
+                               type=FileType('rt'),
+                               help='register header file')
+        argparser.add_argument('-v', '--verbose', action='count',
+                               help='increase verbosity')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'ot', ms=True)
+
+        defs = parse_defs(args.reg) if args.reg else {}
+        check(args.log[0], args.component, defs)
+
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/make_release.sh b/scripts/opentitan/make_release.sh
new file mode 100755
index 0000000000000..88fbae0c262f4
--- /dev/null
+++ b/scripts/opentitan/make_release.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Create a tarball containing the binaries and scripts necessary for opentitan.
+set -e
+
+if [ $# -ne 3 ]; then
+    echo "Usage: $0 /path/to/output/tarball /path/to/src/dir build_dirname" >&2
+    exit 1
+fi
+
+OUT_TARBALL="$1"
+QEMU_DIR="$2"
+QEMU_BUILD="$3"
+# Create archive.
+tar --create --auto-compress --verbose --file="$OUT_TARBALL" \
+    --directory="$QEMU_DIR" \
+    "$QEMU_BUILD"/qemu-{system-riscv32,img} \
+    scripts/opentitan/{otptool,flashgen,cfggen}.py \
+    python/qemu/ot
diff --git a/scripts/opentitan/mbbdef.py b/scripts/opentitan/mbbdef.py
new file mode 100755
index 0000000000000..398a21a3e75c0
--- /dev/null
+++ b/scripts/opentitan/mbbdef.py
@@ -0,0 +1,148 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2024, Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Find and report multi-bit boolean definitions from HJSON configuration file.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser
+from logging import getLogger
+from os import walk
+from os.path import basename, dirname, join as joinpath, normpath, splitext
+from pprint import pprint
+from traceback import format_exc
+from typing import Iterator, TextIO
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ot.util.log import configure_loggers
+
+
+try:
+    from hjson import load as jload
+except ImportError as imp_exc:
+    raise ImportError('hjson module is required') from imp_exc
+
+
+@staticmethod
+def flatten(lst: list) -> list:
+    """Flatten nested list.
+    """
+    return [item for sublist in lst for item in sublist]
+
+
+class MbbChecker:
+    """Simple parser to retrieve MultiBitBool field definition from OpenTitan
+       HW definition file.
+    """
+
+    def __init__(self):
+        self._log = getLogger('mbb')
+        self.emit_ipname = True
+
+    def parse(self, hdir: str) -> None:
+        """Find and parse HW definition files.
+
+           :param hdir: HW top-level definition directory to scan for HW files.
+        """
+        for dirpath, _, filenames in walk(hdir):
+            leafdir = basename(dirpath)
+            if leafdir != 'data':
+                continue
+            radix = basename(dirname(dirpath))
+            deffile = f'{radix}.hjson'
+            if deffile not in filenames:
+                continue
+            filename = joinpath(dirpath, deffile)
+            with open(filename, 'rt', encoding='utf8') as hfp:
+                try:
+                    self._parse(hfp)
+                except Exception:
+                    self._log.error('Failed to parse %s', filename)
+                    raise
+
+    def _parse(self, hfp: TextIO) -> None:
+        values = jload(hfp, object_pairs_hook=dict)
+        filename = hfp.name
+        registers = values.get('registers')
+        self.emit_ipname = True
+        self._log.info('Parsing %s', filename)
+        for regs in self._enumerate_registers(registers):
+            try:
+                ipname = splitext(basename(filename))[0].upper()
+                self._parse_register(ipname, regs)
+            except Exception:
+                pprint(regs)
+                raise
+
+    def _enumerate_registers(self, values: [list, dict]) -> Iterator[dict]:
+        if isinstance(values, list):
+            for sub in values:
+                yield from self._enumerate_registers(sub)
+        if isinstance(values, dict):
+            if 'fields' in values:
+                yield values
+            else:
+                for regs in values.values():
+                    yield from self._enumerate_registers(regs)
+
+    def _parse_register(self, ipname: str,  reg: dict) -> None:
+        regname = reg.get('name')
+        self._log.debug('Parsing %s.%s', ipname, regname)
+        reg_swaccess = reg.get('swaccess')
+        emit_regname = True
+        for field in reg.get('fields', []):
+            fld_swaccess = field.get('swaccess', reg_swaccess).lower()
+            if fld_swaccess in ('ro', 'wo', 'rw'):
+                continue
+            mubi = bool(field.get('mubi', False))
+            if not mubi:
+                continue
+            if self.emit_ipname:
+                print(ipname)
+                self.emit_ipname = False
+            if emit_regname:
+                print(' *', regname)
+                emit_regname = False
+                print('   -', field.get('name'), fld_swaccess)
+
+
+def main():
+    """Main routine"""
+    debug = False
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('ot', nargs='+', metavar='dir',
+                               help='HJSON top-level directory')
+        argparser.add_argument('-v', '--verbose', action='count',
+                               help='increase verbosity')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'mbb')
+
+        for hjson in args.ot:
+            mbb = MbbChecker()
+            mbb.parse(hjson)
+
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/ot-format.sh b/scripts/opentitan/ot-format.sh
new file mode 100755
index 0000000000000..ef767b560fd07
--- /dev/null
+++ b/scripts/opentitan/ot-format.sh
@@ -0,0 +1,74 @@
+#!/bin/sh
+
+# Copyright (c) 2024-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+EXPECTED_VERSION="21"
+
+# find clang-format executable: either 'clang-format-XX,' or 'clang-format'
+for ver_suffix in "-${EXPECTED_VERSION}" ""; do
+    clangformat="$(which clang-format${ver_suffix} 2>/dev/null)"
+    if [ -n "${clangformat}" ]; then
+        break
+    fi
+done
+if [ -z "${clangformat}" ]; then
+    echo "Unable to locate clang-format" >&2
+    exit 1
+fi
+
+# check clang-format version
+version_full="$(${clangformat} --version | \
+    grep "clang-format version" | head -1 | \
+    sed -E 's/^.*clang-format version ([0-9]+\.[0-9]+\.[0-9]+).*$/\1/')"
+if [ -z "${version_full}" ]; then
+    echo "Unable to retrieve LLVM version" >&2
+    exit 1
+fi
+version_major="$(echo ${version_full} | cut -d. -f1)"
+if [ ${version_major} -lt ${EXPECTED_VERSION} ]; then
+    echo "clang-format v${EXPECTED_VERSION} required, found ${version_full}" >&2
+    exit 1
+else
+    if [ ${version_major} -ne ${EXPECTED_VERSION} ]; then
+        echo -n "clang-format v${EXPECTED_VERSION} expected, " >&2
+        echo "v${version_full} may generate unexpected results" >&2
+    fi
+fi
+
+CI_MODE=0
+ARGS=""
+
+# filter arguments
+while [ $# -gt 0 ]; do
+    case "$1" in
+        --ci)
+           CI_MODE=1
+           ;;
+        --style=*)
+           echo "Cannot override --style option" >&2
+           exit 1
+           ;;
+        *)
+           ARGS="$ARGS $1"
+           ;;
+    esac
+    shift
+done
+
+# config
+QEMU_ROOT="$(dirname $0)"/../..
+CFG="$(dirname $0)"/clang-format.yml
+FILES=""
+
+# automatic file list
+if [ $CI_MODE -eq 1 ]; then
+    # file list path
+    FILES_D="$(dirname $0)"/clang-format.d
+
+    for filespec in $(cat "$FILES_D"/*.lst); do
+        FILES="$FILES $QEMU_ROOT/$filespec"
+    done
+fi
+
+exec "${clangformat}" --style=file:"${CFG}" $ARGS $FILES
diff --git a/scripts/opentitan/ot-tidy.py b/scripts/opentitan/ot-tidy.py
new file mode 100755
index 0000000000000..b5db399774a6c
--- /dev/null
+++ b/scripts/opentitan/ot-tidy.py
@@ -0,0 +1,252 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""Wrapper script for 'clang-tidy', the LLVM C linter.
+
+   :author: Alice Ziuziakowska <a.ziuziakowska@lowrisc.org>
+"""
+
+# pylint: disable=invalid-name
+# pylint: enable=invalid-name
+
+import argparse
+import re
+import subprocess
+import sys
+from glob import glob
+from multiprocessing import cpu_count
+from os import execvp, scandir
+from os.path import abspath, dirname, isfile, join, normpath, relpath, splitext
+from traceback import format_exc
+
+LLVM_MAJOR = 21
+"""LLVM major version to check for"""
+
+OT_SCRIPTS = dirname(abspath(__file__))
+"""Directory this script is in"""
+
+QEMU_ROOT = dirname(dirname(OT_SCRIPTS))
+"""QEMU root directory"""
+
+DEF_BUILD_DIR = relpath(join(QEMU_ROOT, "build"))
+"""Default build directory is 'build' in QEMU root"""
+
+DEF_TIDY_YML = relpath(join(OT_SCRIPTS, "clang-tidy.yml"))
+"""Default 'clang-tidy' configuration file"""
+
+
+def ci_files() -> list[str]:
+    """Get list of files that are checked in CI"""
+    lst_files_list = []
+    ci_files_list = []
+    directory = join(OT_SCRIPTS, "clang-tidy.d")
+    for entry in scandir(directory):
+        if entry.is_file() and splitext(entry)[1] == ".lst":
+            lst_files_list.append(entry)
+    for entry in lst_files_list:
+        with open(entry, "rt") as f:
+            patterns = f.readlines()
+            for pattern in patterns:
+                # glob patterns are relative to QEMU root
+                ci_files_list.extend(glob(pattern.strip(), root_dir=QEMU_ROOT))
+    # convert QEMU relative paths to CWD relative paths
+    return [relpath(normpath(join(QEMU_ROOT, f))) for f in ci_files_list]
+
+
+def uint(value: str) -> int:
+    """Argparse function to parse integer greater than 0"""
+    v = int(value)
+    if v <= 0:
+        raise argparse.ArgumentTypeError("value is an integer <= 0")
+    return v
+
+
+def eprint_tty(*args, **kwargs) -> None:
+    """Wrapper for print to stderr with colour for tty"""
+    print("".join(["\x1b[33m", *args, "\x1b[0m"]), **kwargs, file=sys.stderr)
+
+
+def eprint_plain(*args, **kwargs) -> None:
+    """Wrapper for print to stderr"""
+    print(*args, **kwargs, file=sys.stderr)
+
+
+eprint = eprint_tty if sys.stderr.isatty() else eprint_plain
+
+
+def check_compile_commands(build_dir: str) -> None:
+    """
+    Check for 'compile_commands.json' in given build directory
+    """
+    if not isfile(join(build_dir, "compile_commands.json")):
+        eprint(f"missing 'compile_commands.json' in build directory "
+               f"'{build_dir}'.\n"
+               f"please specify the correct QEMU build directory with "
+               f"'-b'/'--build-dir',\n"
+               f"or make sure to run 'configure'")
+        raise FileNotFoundError("missing 'compile_commands.json' "
+                                "in build directory")
+
+
+def check_cc(build_dir: str) -> None:
+    """Check that the configured C compiler for the build is clang"""
+    cc_found = False
+    # look in <build_dir>/config.status and try to find CC variable
+    with open(join(build_dir, "config.status"), "rt") as f:
+        lines = f.readlines()
+        for line in lines:
+            match = re.match(r"^CC='(.*)'$", line)
+            if match is not None:
+                ccs = [f"clang-{LLVM_MAJOR}", "clang"]
+                if match.group(1) not in ccs:
+                    eprint(f"QEMU build is configured with non-clang C "
+                           f"compiler '{match.group(1)}'.\nunknown warning and "
+                           f"argument errors will appear, please re-'configure'"
+                           f" with '--cc=clang...'")
+                cc_found = True
+                break
+    if not cc_found:
+        # no CC option in config.status
+        eprint("no 'cc' argument given to configure.\n"
+               "if the host C compiler is not clang, unknown warning and "
+               "argument errors will appear.\nplease re-'configure' with "
+               "'--cc=clang...'")
+
+
+def check_and_get_clang_tidy() -> str:
+    """Check for and return an appropriate 'clang-tidy'"""
+    cmds = [f"clang-tidy-{LLVM_MAJOR}", "clang-tidy"]
+    for cmd in cmds:
+        try:
+            p = subprocess.run([cmd, "--version"],
+                               capture_output=True, text=True, check=True)
+            for line in p.stdout.split("\n"):
+                match = re.match(r"^.*LLVM version ([0-9]+)\..*$", line)
+                if match is not None:
+                    if int(match.group(1)) != LLVM_MAJOR:
+                        eprint(f"'{cmd}' is build with LLVM major version "
+                               f"{match.group(1)}, "
+                               f"expected version {LLVM_MAJOR}")
+                        break
+                    return cmd
+            else:
+                eprint(f"could not parse version of '{cmd}'")
+        except FileNotFoundError:
+            pass
+        except subprocess.CalledProcessError:
+            eprint(f"'{cmd}' exited with non-zero exit code")
+    raise FileNotFoundError("No suitable 'clang-tidy' found")
+
+
+def check_and_get_run_clang_tidy() -> str:
+    """Check for and return an appropriate 'run-clang-tidy'"""
+    # 'run-clang-tidy' does not have a version flag,
+    # and will try to run with no flags given,
+    # so run with '--help' and check if it exists
+    cmds = [f"run-clang-tidy-{LLVM_MAJOR}", "run-clang-tidy"]
+    for cmd in cmds:
+        try:
+            _ = subprocess.run([cmd, "--help"], capture_output=True, check=True)
+            return cmd
+        except FileNotFoundError:
+            pass
+        except subprocess.CalledProcessError:
+            eprint(f"'{cmd}' exited with non-zero exit code")
+    raise FileNotFoundError("No suitable 'run-clang-tidy' found")
+
+
+def main():
+    """Wrapper entry point"""
+    debug = True
+    try:
+        parser = argparse.ArgumentParser()
+
+        parser.add_argument("-b", "--build-dir", default=DEF_BUILD_DIR,
+                            help=(f"QEMU build directory path. Default is "
+                                  f"'{DEF_BUILD_DIR}'"))
+
+        parser.add_argument("-j", "--jobs", nargs="?", type=uint,
+                            default=1, const=cpu_count(),
+                            help=("Number of tidy jobs to run in parallel. "
+                                  "Default is number of threads if value "
+                                  "is unspecified"))
+
+        parser.add_argument("-C", "--config-file", default=DEF_TIDY_YML,
+                            help=(f"'clang-tidy' configuration file path. "
+                                  f"Default is '{DEF_TIDY_YML}'"))
+
+        parser.add_argument("-c", "--ci-files", action="store_true",
+                            help="Run on all files checked by CI")
+
+        parser.add_argument("files", nargs="*", default=[], action="extend",
+                            help="Files to run tidy on")
+
+        parser.add_argument("-d", "--debug", action="store_true",
+                            help="Enable debug mode")
+
+        parser.add_argument("-v", "--verbose", action="store_true",
+                            help="Enable verbose output")
+
+        args = parser.parse_args()
+
+        debug = args.debug
+
+        # normalise paths
+        args.build_dir = normpath(args.build_dir)
+        args.config_file = normpath(args.config_file)
+        args.files = [normpath(f) for f in args.files]
+
+        # append ci files
+        if args.ci_files:
+            args.files.extend(ci_files())
+
+        if not args.files:
+            parser.error("no input files provided. specify files, or use "
+                         "'-c'/'--ci-files' to run on files checked in CI.")
+
+        check_compile_commands(args.build_dir)
+        check_cc(args.build_dir)
+
+        cmd = ""
+        cmd_args = []
+
+        # use a 'run-clang-tidy' if running in parallel.
+        # this wrapper has slightly different command line arguments
+        if args.jobs == 1:
+            cmd = check_and_get_clang_tidy()
+            cmd_args = [
+                cmd,
+                "-p", args.build_dir,
+                "--config-file", args.config_file,
+            ]
+        else:
+            cmd = check_and_get_run_clang_tidy()
+            cmd_args = [
+                cmd,
+                "-quiet",
+                "-p", args.build_dir,
+                "-config-file", args.config_file,
+                "-j", str(args.jobs),
+            ]
+
+        if args.verbose:
+            fmt_args = " ".join(cmd_args[1:])
+            print(f"running '{cmd} {fmt_args} ... ({len(args.files)} files)'")
+
+        cmd_args.extend(args.files)
+        execvp(cmd, cmd_args)
+
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f"error: {exc}", file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/scripts/opentitan/ot-tidy.sh b/scripts/opentitan/ot-tidy.sh
new file mode 100755
index 0000000000000..05a740ecf9e6c
--- /dev/null
+++ b/scripts/opentitan/ot-tidy.sh
@@ -0,0 +1,74 @@
+#!/bin/sh
+
+# Copyright (c) 2024-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+EXPECTED_VERSION="21"
+
+# find clang-tidy executable: either 'clang-tidy-XX' or 'clang-tidy'
+for ver_suffix in "-${EXPECTED_VERSION}" ""; do
+    clangtidy="$(which clang-tidy${ver_suffix} 2>/dev/null)"
+    if [ -n "${clangtidy}" ]; then
+        break
+    fi
+done
+if [ -z "${clangtidy}" ]; then
+    echo "Unable to locate clang-tidy" >&2
+    exit 1
+fi
+
+# check clang-tidy version
+version_full="$(${clangtidy} --version | \
+    grep "LLVM version" | head -1 | \
+    sed -E 's/^.*LLVM version ([0-9]+\.[0-9]+\.[0-9]+).*$/\1/')"
+if [ -z "${version_full}" ]; then
+    echo "Unable to retrieve LLVM version" >&2
+    exit 1
+fi
+version_major="$(echo ${version_full} | cut -d. -f1)"
+if [ ${version_major} -lt ${EXPECTED_VERSION} ]; then
+    echo "clang-tidy v${EXPECTED_VERSION} required, found ${version_full}" >&2
+    exit 1
+else
+    if [ ${version_major} -ne ${EXPECTED_VERSION} ]; then
+        WMSG="clang-tidy v${EXPECTED_VERSION} expected,"
+        WMSG="${WMSG} v${version_full} may generate unexpected results"
+        echo "${WMSG}" >&2
+    fi
+fi
+
+CI_MODE=0
+ARGS=""
+
+# filter arguments
+while [ $# -gt 0 ]; do
+    case "$1" in
+        --ci)
+           CI_MODE=1
+           ;;
+        --config-file=*)
+           echo "Cannot override --config-file option" >&2
+           exit 1
+           ;;
+        *)
+           ARGS="$ARGS $1"
+           ;;
+    esac
+    shift
+done
+
+# config
+QEMU_ROOT="$(realpath $(dirname $0)/../..)"
+CFG="$(dirname $0)"/clang-tidy.yml
+FILES_D="$(dirname $0)"/clang-tidy.d
+FILES=""
+
+# automatic file list
+if [ $CI_MODE -eq 1 ]; then
+    for filespec in $(cat "$FILES_D"/*.lst); do
+        FILES="$FILES $QEMU_ROOT/$filespec"
+    done
+fi
+
+echo "Using ${clangtidy}"
+exec "${clangtidy}" --config-file="${CFG}" $ARGS $FILES
diff --git a/scripts/opentitan/otpdm.py b/scripts/opentitan/otpdm.py
new file mode 100755
index 0000000000000..ac9fc25d7d611
--- /dev/null
+++ b/scripts/opentitan/otpdm.py
@@ -0,0 +1,214 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2024, Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""OTP controller access through the RISC-V Debug Module.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, Namespace, FileType
+from binascii import hexlify
+from io import StringIO
+from os import linesep
+from os.path import dirname, join as joinpath, normpath
+from socket import create_connection
+from traceback import format_exc
+from typing import Optional
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from jtagtools.rbb import JtagBitbangController
+from jtagtools.jtag.engine import JtagEngine
+
+from ot.dm import DebugModule
+from ot.dm.otp import OTPController
+from ot.dtm import DebugTransportModule
+from ot.otp import OtpMap
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt, dump_buffer
+
+
+DEFAULT_IR_LENGTH = 5
+"""Default TAP Instruction Register length."""
+
+DEFAULT_DMI_ADDRESS = 0x0
+"""Default DMI address of the DM."""
+
+DEFAULT_OTP_BASE_ADDRESS = 0x30130000
+"""Default base address of the OTP controller on the OT local crossbar."""
+
+
+def main():
+    """Entry point."""
+    debug = True
+    try:
+        args: Optional[Namespace] = None
+        argparser = ArgumentParser(
+            description=sys.modules[__name__].__doc__.split('.')[0])
+        qvm = argparser.add_argument_group(title='Virtual machine')
+        qvm.add_argument('-H', '--host', default='127.0.0.1',
+                         help='JTAG host (default: localhost)')
+        qvm.add_argument('-P', '--port', type=int,
+                         default=JtagBitbangController.DEFAULT_PORT,
+                         help=f'JTAG port, '
+                              f'default: {JtagBitbangController.DEFAULT_PORT}')
+        qvm.add_argument('-Q', '--no-quit', action='store_true', default=False,
+                         help='do not ask the QEMU to quit on exit')
+        dmi = argparser.add_argument_group(title='DMI')
+        dmi.add_argument('-l', '--ir-length', type=int,
+                         default=DEFAULT_IR_LENGTH,
+                         help=f'bit length of the IR register '
+                              f'(default: {DEFAULT_IR_LENGTH})')
+        dmi.add_argument('-b', '--base', type=HexInt.parse,
+                         default=DEFAULT_DMI_ADDRESS,
+                         help=f'define DMI base address '
+                              f'(default: 0x{DEFAULT_DMI_ADDRESS:x})')
+        otp = argparser.add_argument_group(title='OTP')
+        otp.add_argument('-j', '--otp-map', type=FileType('rt'),
+                         metavar='HJSON',
+                         help='input OTP controller memory map file')
+        otp.add_argument('-a', '--address', type=HexInt.parse,
+                         default=DEFAULT_OTP_BASE_ADDRESS,
+                         help=f'base address the OTP controller, default: '
+                              f'0x{DEFAULT_OTP_BASE_ADDRESS:08x}')
+        otp.add_argument('-p', '--partition',
+                         help='select a partition')
+        otp.add_argument('-i', '--item',
+                         help='select a partition item')
+        otp.add_argument('-L', '--list', action='store_true',
+                         help='list the partitions and/or the items')
+        otp.add_argument('-r', '--read', action='store_true',
+                         help='read the value of the selected item')
+        otp.add_argument('-w', '--write',
+                         help='write the value to the selected item')
+        otp.add_argument('-D', '--digest', action='store_true',
+                         help='show the OTP HW partition digests')
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'dtm.rvdm', 'dtm.otp', -1, 'dtm',
+                          'jtag')
+
+        sock = create_connection((args.host, args.port), timeout=0.5)
+        sock.settimeout(0.1)
+
+        if args.otp_map:
+            otpmap = OtpMap()
+            otpmap.load(args.otp_map)
+            args.otp_map.close()
+        else:
+            if args.digest:
+                argparser.error('Digest feature requires an OTP map')
+            otpmap = None
+        ctrl = JtagBitbangController(sock)
+        eng = JtagEngine(ctrl)
+        ctrl.tap_reset(True)
+        ir_length = args.ir_length
+        dtm = DebugTransportModule(eng, ir_length)
+        rvdm = DebugModule(dtm, args.base)
+        try:
+            rvdm.initialize()
+            rvdm.halt()
+            otp = OTPController(rvdm, base=0x30130000)
+            partition = None
+            item = None
+            if otpmap:
+                otp.set_map(otpmap)
+            elif any((getattr(args, a) for a in
+                     ('partition', 'item', 'list', 'read', 'write', 'digest'))):
+                argparser.error('OTP map is required for this operation')
+            if args.partition:
+                partname = args.partition.upper()
+                try:
+                    partition = otpmap.partitions[partname]
+                except KeyError:
+                    argparser.error(f"Unknown partition '{args.partition}'")
+            else:
+                partition = None
+                partname = None
+            if args.item:
+                if not partition:
+                    argparser.error('Missing partition for selecting item')
+                item_name = args.item.upper()
+                item = None
+                for entry in partition['items']:
+                    if entry.get('name', '') == item_name:
+                        item = entry
+                        break
+                else:
+                    argparser.error(f"Unknown item '{args.item}")
+            else:
+                item = None
+            if args.digest:
+                if partition is None:
+                    print('HW digests:')
+                    for name, digest in otp.get_hw_partition_digests().items():
+                        print(f' * {name:10} 0x{digest:016x}')
+                else:
+                    digest = otp.get_hw_partition_digest(partname)
+                    print(f'0x{digest:016x}')
+            if args.list:
+                if partition:
+                    if not item:
+                        print('Items:')
+                        for item in partition.get('items', []):
+                            name = item['name']
+                            print(f' * {name}')
+                    else:
+                        print(item['name'])
+                        for name, value in item.items():
+                            if name == 'name':
+                                continue
+                            print(f' * {name}: {value}')
+                else:
+                    print('Partitions:')
+                    for part in otpmap.enumerate_partitions():
+                        print(f' * {part.name}')
+            if args.read or args.write:
+                if not partition or not partname:
+                    argparser.error('Partition is required for this operation')
+                if not item:
+                    argparser.error('Item is required for this operation')
+            if args.read:
+                val = otp.read_partition_item(partname, item['name'])
+                if isinstance(val, int):
+                    pad = ' * value: ' if args.list else ''
+                    print(f'{pad}0x{val:x}')
+                else:
+                    if args.list:
+                        out = StringIO()
+                        dump_buffer(val, file=out)
+                        print(' * value: |')
+                        for line in out.getvalue().split('\n'):
+                            print(f'   {line}')
+                    else:
+                        print(hexlify(val).decode())
+            if args.write:
+                otp.write_partition_item(partname, item['name'], args.write)
+        finally:
+            if not args.no_quit:
+                ctrl.quit()
+
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'{linesep}Error: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/otptool.py b/scripts/opentitan/otptool.py
new file mode 100755
index 0000000000000..a8c70e32fbbb7
--- /dev/null
+++ b/scripts/opentitan/otptool.py
@@ -0,0 +1,474 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU OT tool to manage OTP files.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, FileType
+from binascii import unhexlify
+from io import IOBase
+from os.path import (basename, dirname, isfile, join as joinpath, normpath,
+                     split as splitpath)
+from re import match as re_match
+from traceback import format_exception
+from typing import Optional, Union
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+# ruff: noqa: E402
+_EXC: Optional[Exception] = None
+try:
+    from ot.lc_ctrl.tools import LifeCycleTokenEngine, LifeCycleTokenPair
+except ModuleNotFoundError as exc:
+    _EXC = exc
+from ot.otp import (OtpImage, OtpLifecycleExtension, OtpMap, OtpPartition,
+                    OtpPartitionDesc, OtpRegisterDef)
+from ot.top import OpenTitanTop
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt, to_bool
+
+
+def parse_lc_token(tkdesc: str) -> tuple[str, 'LifeCycleTokenPair']:
+    """Parse a Rust file for a LC token and return its name and VALUE
+
+       :param tkdesc: argument parser input string
+       :return: a 2-uple of OTP map token name and LifeCycleTokenPair
+    """
+    token_desc, token_val = tkdesc.split('=', 1)
+    token_name = token_desc.upper()
+    tkeng = LifeCycleTokenEngine()
+    try:
+        tktext = unhexlify(token_val)
+        if len(tktext) != tkeng.TOKEN_LENGTH:
+            raise ValueError()
+    except ValueError as exc:
+        raise ValueError(f"No valid token '{token_name}'") from exc
+    return token_name, tkeng.build_from_text(tktext)
+
+
+def get_top_name(*filepaths: list[Union[str, IOBase]]) -> Optional[str]:
+    """Try to retrieve the top name from a list of configuration files.
+
+       :param filepaths: list of file path or file objects
+       :return: the name of the identified top, if found
+    """
+    for filepath in filepaths:
+        if not isinstance(filepath, str):
+            filepath = getattr(filepath, 'name', None)
+            if not filepath:
+                continue
+        if not isfile(filepath):
+            continue
+        fdir = dirname(filepath)
+        top_names = set(OpenTitanTop.names)
+        while fdir:
+            fdir, tail = splitpath(fdir)
+            top_prefix = 'top_'
+            if tail.startswith(top_prefix):
+                candidate = tail.removeprefix(top_prefix)
+                if candidate in top_names:
+                    return candidate
+        return None
+
+
+def main():
+    """Main routine"""
+    debug = True
+    genfmts = 'LCVAL LCTPL PARTS REGS'.split()
+    outkinds = ('qemu', 'bmtest')
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        files = argparser.add_argument_group(title='Files')
+        files.add_argument('-j', '--otp-map', type=FileType('rt'),
+                           metavar='HJSON',
+                           help='input OTP controller memory map file')
+        files.add_argument('-m', '--vmem', type=FileType('rt'),
+                           help='input VMEM file')
+        files.add_argument('-l', '--lifecycle', type=FileType('rt'),
+                           metavar='SV',
+                           help='input lifecycle system verilog file')
+        files.add_argument('-o', '--output', metavar='FILE',
+                           type=FileType('wt'),
+                           help='output filename (default to stdout)')
+        files.add_argument('-r', '--raw',
+                           help='QEMU OTP raw image file')
+        files.add_argument('-x', '--export', metavar='VMEM',
+                           help='Export data to a VMEM file')
+        files.add_argument('-X', '--export-verbose', metavar='VMEM',
+                           help='Export data to a VMEM file with field info')
+        params = argparser.add_argument_group(title='Parameters')
+        # pylint: disable=unsubscriptable-object
+        params.add_argument('-k', '--kind',
+                            choices=OtpImage.vmem_kinds,
+                            help=f'kind of content in VMEM input file, '
+                                 f'default: {OtpImage.vmem_kinds[0]}')
+        params.add_argument('-e', '--ecc', type=int,
+                            default=OtpImage.DEFAULT_ECC_BITS,
+                            metavar='BITS', help='ECC bit count')
+        params.add_argument('-C', '--config', type=FileType('rt'),
+                            help='read Present constants from QEMU config file')
+        params.add_argument('-c', '--constant', type=HexInt.parse,
+                            metavar='INT',
+                            help='finalization constant for Present scrambler')
+        params.add_argument('-i', '--iv', type=HexInt.parse, metavar='INT',
+                            help='initialization vector for Present scrambler')
+        params.add_argument('-w', '--wide', action='count', default=0,
+                            help='use wide output, non-abbreviated content')
+        params.add_argument('-n', '--no-decode', action='store_true',
+                            default=False,
+                            help='do not attempt to decode OTP fields')
+        params.add_argument('-f', '--filter', action='append',
+                            metavar='PART:FIELD',
+                            help='filter which OTP fields are shown')
+        params.add_argument('--force-absorb', action='store_true',
+                            help='force absorption')
+        params.add_argument('--no-version', action='store_true',
+                            help='do not report the OTP image version')
+        commands = argparser.add_argument_group(title='Commands')
+        commands.add_argument('-s', '--show', action='store_true',
+                              help='show the OTP content')
+        commands.add_argument('-E', '--ecc-recover', action='store_true',
+                              help='attempt to recover errors with ECC')
+        commands.add_argument('-D', '--digest', action='store_true',
+                              help='check the OTP HW partition digest')
+        commands.add_argument('-U', '--update', action='store_true',
+                              help='update RAW file after ECC recovery or bit '
+                                   'changes')
+        commands.add_argument('-g', '--generate', choices=genfmts,
+                              help='generate code, see doc for options')
+        commands.add_argument('-F', '--fix-ecc', action='store_true',
+                              help='rebuild ECC')
+        commands.add_argument('-G', '--fix-digest', action='append',
+                              metavar='PART', default=[],
+                              help='rebuild HW digest')
+        commands.add_argument('--change', action='append',
+                              metavar='PART:FIELD=VALUE', default=[],
+                              help='change the content of an OTP field')
+        commands.add_argument('--empty', metavar='PARTITION', action='append',
+                              default=[],
+                              help='reset the content of a whole partition, '
+                                   'including its digest if any')
+        commands.add_argument('--erase', action='append', metavar='PART:FIELD',
+                              default=[],
+                              help='clear out an OTP field')
+        commands.add_argument('--clear-bit', action='append', default=[],
+                              help='clear a bit at specified location')
+        commands.add_argument('--set-bit', action='append',  default=[],
+                              help='set a bit at specified location')
+        commands.add_argument('--toggle-bit', action='append',  default=[],
+                              help='toggle a bit at specified location')
+        commands.add_argument('--write', action='append',
+                              metavar='ADDR/HEXBYTES', default=[],
+                              help='write bytes at specified location')
+        commands.add_argument('--patch-token', action='append',
+                              metavar='NAME=VALUE', default=[],
+                              help='change a LC hashed token, using Rust file')
+        commands.add_argument('--out-kind', choices=outkinds,
+                              default=outkinds[0],
+                              help=f'select output format for code generation'
+                                   f' (default: {outkinds[0]})')
+        commands.add_argument('--top-name',
+                              help='optional top name for code generation '
+                                   '(default: auto)')
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        log = configure_loggers(args.verbose, 'otptool', 'otp')[0]
+
+        otp = OtpImage(args.ecc)
+
+        check_update = False
+
+        if not (args.vmem or args.raw):
+            if any((args.show, args.digest, args.ecc_recover, args.clear_bit,
+                    args.set_bit, args.toggle_bit, args.write, args.change,
+                    args.erase, args.fix_digest)):
+                argparser.error('At least one raw or vmem file is required')
+
+        if not args.vmem and args.kind:
+            argparser.error('VMEM kind only applies for VMEM input files')
+
+        if args.update:
+            if not args.raw:
+                argparser.error('No RAW file specified for update')
+            if args.vmem:
+                argparser.error('RAW update mutually exclusive with VMEM')
+
+        if args.filter and not args.show:
+            argparser.error('Filter only apply to the show command')
+
+        bit_actions = ('clear', 'set', 'toggle')
+        alter_bits: list[list[tuple[int, int]]] = []
+        for slot, bitact in enumerate(bit_actions):
+            bitdefs = getattr(args, f'{bitact}_bit')
+            alter_bits.append([])
+            for bitdef in bitdefs:
+                try:
+                    soff, sdata = bitdef.split('/', 1)
+                    if soff[1] == 'h':
+                        offset = HexInt.parse(soff.replace('h', 'x'))
+                        offset *= 2
+                    else:
+                        offset = HexInt.parse(soff)
+                    bit = HexInt.parse(sdata)
+                except ValueError as exc:
+                    argparser.error(f"Invalid bit specifier '{bitdef}', should "
+                                    f"be <offset>/<bit_num> format: {exc}")
+                alter_bits[slot].append((offset, bit))
+
+        otpmap: Optional[OtpMap] = None
+        lcext: Optional[OtpLifecycleExtension] = None
+        partdesc: Optional[OtpPartitionDesc] = None
+
+        if not args.otp_map:
+            if args.generate in ('PARTS', 'REGS'):
+                argparser.error('Generator requires an OTP map')
+            for feat in ('show', 'digest', 'empty', 'change', 'erase',
+                         'fix_digest', 'patch_token', 'export_verbose'):
+                if not getattr(args, feat):
+                    continue
+                argparser.error('Specified option requires an OTP map')
+        else:
+            otpmap = OtpMap()
+            otpmap.load(args.otp_map, args.force_absorb)
+
+        if args.lifecycle:
+            lcext = OtpLifecycleExtension()
+            lcext.load(args.lifecycle)
+        elif args.generate in ('LCVAL', 'LCTPL'):
+            argparser.error('Cannot generate LC array w/o a lifecycle file')
+
+        output = sys.stdout if not args.output else args.output
+
+        try:
+            if not args.generate:
+                pass
+            elif args.generate == 'PARTS':
+                partdesc = OtpPartitionDesc(otpmap)
+                partdesc.save(args.out_kind, basename(args.otp_map.name),
+                              basename(sys.argv[0]), output)
+            elif args.generate == 'REGS':
+                topname = args.top_name
+                if not topname:
+                    topname = get_top_name(args.otp_map)
+                regdef = OtpRegisterDef(otpmap)
+                regdef.save(args.out_kind, topname, basename(args.otp_map.name),
+                            basename(sys.argv[0]), output)
+            elif args.generate == 'LCVAL':
+                lcext.save(args.out_kind, output, True)
+            elif args.generate == 'LCTPL':
+                lcext.save(args.out_kind, output, False)
+        except NotImplementedError:
+            argparser.error(f'Cannot generate {args.generate} in '
+                            f'{args.out_kind}')
+
+        if args.vmem:
+            otp.load_vmem(args.vmem, args.kind)
+            if otpmap:
+                otp.dispatch(otpmap)
+            otp.verify_ecc(args.ecc_recover)
+
+        if args.raw:
+            # if no VMEM is provided, select the RAW file as an input file
+            # otherwise it is selected as an output file
+            if not args.vmem:
+                with open(args.raw, 'rb') as rfp:
+                    otp.load_raw(rfp)
+                if otpmap:
+                    otp.dispatch(otpmap)
+                otp.verify_ecc(args.ecc_recover)
+
+        if otp.loaded:
+
+            if not otp.is_opentitan:
+                ot_opts = ('iv', 'constant', 'digest', 'generate', 'otp_map',
+                           'lifecycle')
+                if any(getattr(args, a) for a in ot_opts):
+                    argparser.error('Selected option only applies to OpenTitan '
+                                    'images')
+                if args.show:
+                    argparser.error('Showing content of non-OpenTitan image is '
+                                    'not supported')
+            if args.empty:
+                for part in args.empty:
+                    otp.empty_partition(part)
+
+            for field_desc in args.erase:
+                try:
+                    part, field = field_desc.split(':')
+                    if not isinstance(part, str):
+                        raise ValueError()
+                except ValueError:
+                    argparser.error('Invalid field specifier, should follow '
+                                    '<PART>:<FIELD> syntax')
+                otp.erase_field(part, field)
+                check_update = True
+
+            for chg_desc in args.change:
+                try:
+                    fdesc, value = chg_desc.split('=')
+                except ValueError:
+                    argparser.error('Invalid change specifier, should follow '
+                                    '<PART>:<FIELD>=<VALUE> syntax')
+                try:
+                    part, field = fdesc.split(':')
+                    if not isinstance(part, str):
+                        raise ValueError()
+                except ValueError:
+                    argparser.error('Invalid field specifier, should follow '
+                                    '<PART>:<FIELD> syntax')
+                smo = re_match(r'^(?P<quote>[\"\'])(?P<value>.*)(?P=quote)$',
+                               value)
+                if smo:
+                    # single- or double- quoted string value
+                    value = smo.group('value')
+                else:
+                    if value.startswith('0x'):
+                        value = HexInt.parse(value)
+                    else:
+                        try:
+                            value = to_bool(value, permissive=False)
+                        except ValueError:
+                            pass
+                    if isinstance(value, str):
+                        try:
+                            value = bytes(reversed(unhexlify(value)))
+                        except ValueError:
+                            argparser.error(f'Unknown value type: {value}')
+                otp.change_field(part, field, value)
+                check_update = True
+
+            if args.config:
+                otp.load_config(args.config)
+
+            if args.iv:
+                otp.set_digest_iv(args.iv)
+
+            if args.constant:
+                otp.set_digest_constant(args.constant)
+
+            token_parts: set[OtpPartition] = set()
+
+            if args.patch_token and _EXC:
+                if debug:
+                    print(''.join(format_exception(_EXC, chain=False)),
+                          file=sys.stderr)
+                argparser.error(f'Missing PYTHONPATH: {_EXC}')
+            for tkdesc in args.patch_token:
+                if '=' not in tkdesc:
+                    argparser.error(f"Invalid token syntax: '{tkdesc}'")
+                token, value = parse_lc_token(tkdesc)
+                token_name = f'{token}_TOKEN'
+                token_parts = otpmap.find_field(token_name)
+                if len(token_parts) == 0:
+                    argparser.error(f"No such token '{token}' in OTP map")
+                if len(token_parts) > 1:
+                    argparser.error(
+                        f"Token '{token}' found in multiple partitions "
+                        f"{', '.join(p.name for p in token_parts)}")
+                part = token_parts[0]
+                # no sure why we need to revert the bytes here
+                # could be due to any other inversion in any other piece of SW
+                # ...
+                token_hash = bytes(reversed(value.hashed))
+                otp.change_field(part.name, token_name, token_hash)
+                if part.is_locked:
+                    token_parts.add(part.name)
+                check_update = True
+            for part in token_parts:
+                otp.build_digest(part.name, True)
+
+            if args.digest or args.fix_digest:
+                if not otp.has_present_constants:
+                    if args.raw and otp.version == 1:
+                        msg = '; OTP v1 image does not track them'
+                    else:
+                        msg = ''
+                    # can either be defined on the CLI or in an existing QEWU
+                    # image
+                    argparser.error(f'Present scrambler constants are required '
+                                    f'to handle the partition digest{msg}')
+            build_digest_parts = {p for p in args.fix_digest if p != 'tokens'}
+            if 'tokens' in args.fix_digest:
+                build_digest_parts.update((p.name for p in token_parts))
+            for part in build_digest_parts:
+                otp.build_digest(part, True)
+                check_update = True
+
+            if lcext:
+                otp.load_lifecycle(lcext)
+
+            if args.show:
+                otp.decode(not args.no_decode, args.wide, output,
+                           not args.no_version, args.filter)
+
+            if args.digest:
+                otp.verify(True)
+
+            for pos, bitact in enumerate(bit_actions):
+                if alter_bits[pos]:
+                    getattr(otp, f'{bitact}_bits')(alter_bits[pos])
+                check_update = True
+
+            for write in args.write:
+                try:
+                    saddr, sdata = write.split('/', 1)
+                    if saddr[1] == 'h':
+                        addr = HexInt.parse(saddr.replace('h', 'x'))
+                        addr *= 2
+                    else:
+                        addr = HexInt.parse(saddr)
+                    data = unhexlify(sdata)
+                except ValueError as exc:
+                    argparser.error(f'Invalid write syntax: {write} {exc}')
+                otp.change_data(addr, data)
+
+            if args.fix_ecc:
+                otp.fix_ecc()
+                check_update = True
+
+            if args.raw and (args.vmem or args.update):
+                if not args.update and any(alter_bits):
+                    otp.verify_ecc(False)
+                # when both RAW and VMEM are selected, QEMU RAW image file
+                # should be generated
+                with open(args.raw, 'wb') as rfp:
+                    otp.save_raw(rfp)
+
+            if args.raw and not args.vmem:
+                if not args.update and check_update:
+                    log.warning('OTP content modified, image file not updated')
+
+            xp_name = args.export or args.export_verbose
+            if xp_name:
+                if args.export and args.export_verbose:
+                    argparser.error('export options are mutually exclusive')
+                with open(xp_name, 'wt') if xp_name != '-' else \
+                        sys.stdout as xfp:
+                    otp.save_vmem(xfp, bool(args.export_verbose))
+
+    except (IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(''.join(format_exception(exc, chain=False)),
+                  file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/pyot.py b/scripts/opentitan/pyot.py
new file mode 100755
index 0000000000000..377723927ae04
--- /dev/null
+++ b/scripts/opentitan/pyot.py
@@ -0,0 +1,341 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2023-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""OpenTitan QEMU unit test sequencer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, FileType, Namespace
+try:
+    _HJSON_ERROR = None
+    from hjson import load as jload
+except ImportError as hjson_exc:
+    _HJSON_ERROR = str(hjson_exc)
+    def hjload(*_, **__):  # noqa: E301
+        """dummy func if HJSON module is not available"""
+        return {}
+from os import close, linesep, unlink
+from os.path import dirname, isfile, join as joinpath, normpath, relpath
+from tempfile import mkstemp
+from time import sleep
+from traceback import format_exc
+from typing import Optional
+
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+# pylint: disable=wrong-import-position
+# pylint: disable=wrong-import-order
+# pylint: disable=import-error
+
+from ot.pyot import DEFAULT_TIMEOUT, DEFAULT_TIMEOUT_FACTOR
+from ot.pyot.qemu.executer import QEMUExecuter
+from ot.pyot.filemgr import FileManager
+from ot.pyot.util import ResultFormatter
+from ot.util.log import ColorLogFormatter, RemoteLogService, configure_loggers
+from ot.util.misc import flatten
+
+DEFAULT_MACHINE = 'ot-earlgrey'
+DEFAULT_DEVICE = 'localhost:8000'
+
+
+def main():
+    """Main routine."""
+    debug = True
+    qemu_dir = normpath(joinpath(dirname(dirname(dirname(normpath(__file__))))))
+    qemu_paths = [normpath(joinpath(qemu_dir, 'build', 'qemu-system-riscv32'))]
+    if sys.platform == 'darwin':
+        qemu_paths.append(f'{qemu_paths[0]}-unsigned')
+    for qpath in qemu_paths:
+        if isfile(qpath):
+            qemu_path = qpath
+            break
+    else:
+        qemu_path = None
+    tmp_result: Optional[str] = None
+    result_file: Optional[str] = None
+    rlog: Optional[RemoteLogService] = None
+    ret = None
+    try:
+        args: Optional[Namespace] = None
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        qvm = argparser.add_argument_group(title='Virtual machine')
+        rel_qemu_path = relpath(qemu_path) if qemu_path else '?'
+        qvm.add_argument('-A', '--asan', action='store_const', const=True,
+                         help='redirect address sanitizer error log stream')
+        qvm.add_argument('-D', '--start-delay', type=float, metavar='DELAY',
+                         help='QEMU start up delay before initial comm')
+        qvm.add_argument('-i', '--icount',
+                         help='virtual instruction counter with 2^ICOUNT clock '
+                              'ticks per inst. or \'auto\'')
+        qvm.add_argument('-L', '--qemu-log', metavar='FILE',
+                         help='log file for trace and log messages')
+        qvm.add_argument('-M', '--variant',
+                         help='machine variant (machine specific)')
+        qvm.add_argument('-N', '--log', action='append',
+                         help='log message types')
+        qvm.add_argument('-m', '--machine',
+                         help=f'virtual machine (default to {DEFAULT_MACHINE})')
+        qvm.add_argument('-Q', '--opts', action='append',
+                         help='QEMU verbatim option (may be repeated)')
+        qvm.add_argument('-q', '--qemu',
+                         help=f'path to qemu application '
+                              f'(default: {rel_qemu_path})')
+        qvm.add_argument('-P', '--vcp', action='append',
+                         help='serial port devices (default: use serial0)')
+        qvm.add_argument('-p', '--device',
+                         help=f'serial port device name / template name '
+                              f'(default to {DEFAULT_DEVICE})')
+        qvm.add_argument('-S', '--first-soc', metavar='SOC', default=None,
+                         help='Identifier of the first SoC, if any')
+        qvm.add_argument('-s', '--singlestep', action='store_const',
+                         const=True,
+                         help='enable "single stepping" QEMU execution mode')
+        qvm.add_argument('-t', '--trace', action='append', metavar='TRACE|FILE',
+                         default=[],
+                         help='enable trace (may be repeated)')
+        qvm.add_argument('-U', '--muxserial', action='store_const',
+                         const=True,
+                         help='enable multiple virtual UARTs to be muxed into '
+                              'same host output channel')
+        files = argparser.add_argument_group(title='Files')
+        files.add_argument('-b', '--boot',
+                           metavar='file', help='bootloader 0 file')
+        files.add_argument('-c', '--config', metavar='HJSON',
+                           type=FileType('rt', encoding='utf-8'),
+                           help='path to HJSON configuration file')
+        files.add_argument('-e', '--embedded-flash', metavar='BUS', type=int,
+                           help='generate an eflash image file for MTD bus')
+        files.add_argument('-f', '--flash', metavar='RAW',
+                           help='SPI flash image file')
+        files.add_argument('-g', '--otcfg', metavar='CFGFILE', action='append',
+                           help='configuration option file for OT devices')
+        files.add_argument('-H', '--no-flash-header', action='store_const',
+                           const=True,
+                           help='application and/or bootloader files contain '
+                                'no OT header')
+        files.add_argument('-K', '--keep-tmp', action='store_true',
+                           help='Do not automatically remove temporary files '
+                                'and dirs on exit')
+        files.add_argument('-l', '--loader', metavar='file',
+                           help='ROM trampoline to execute, if any')
+        files.add_argument('-O', '--otp-raw', metavar='RAW',
+                           help='OTP image file')
+        files.add_argument('-o', '--otp', metavar='VMEM', help='OTP VMEM file')
+        files.add_argument('-r', '--rom', metavar='ELF', action='append',
+                           help='ROM file (may be repeated, in load order)')
+        files.add_argument('-w', '--result', metavar='CSV',
+                           help='path to output result file')
+        files.add_argument('-x', '--exec', metavar='file',
+                           help='application to load')
+        files.add_argument('-X', '--rom-exec', action='store_const', const=True,
+                           help='load application as ROM image '
+                                '(default: as kernel)')
+        exe = argparser.add_argument_group(title='Execution')
+        exe.add_argument('-F', '--filter', metavar='TEST', action='append',
+                         help='run tests with matching filter, prefix with "!" '
+                              'to exclude matching tests')
+        exe.add_argument('-k', '--timeout', metavar='SECONDS', type=float,
+                         help=f'exit after the specified seconds '
+                              f'(default: {DEFAULT_TIMEOUT} secs)')
+        exe.add_argument('-z', '--list', action='store_true',
+                         help='show a list of tests to execute and exit')
+        exe.add_argument('-R', '--summary', action='store_true',
+                         help='show a result summary')
+        exe.add_argument('-T', '--timeout-factor', type=float, metavar='FACTOR',
+                         default=DEFAULT_TIMEOUT_FACTOR,
+                         help='timeout factor')
+        exe.add_argument('-Z', '--zero', action='store_true',
+                         help='do not error if no test can be executed')
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-d', dest='dbg', action='store_true',
+                           help='enable debug mode')
+        extra.add_argument('-G', '--log-time', action='store_true',
+                           help='show local time in log messages')
+        extra.add_argument('-V', '--vcp-verbose', action='count',
+                           help='increase verbosity of QEMU virtual comm ports')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('--log-file', metavar='FILE',
+                           help='copy log messages to a file')
+        extra.add_argument('--log-udp', type=int, metavar='UDP_PORT',
+                           help='change UDP port for log messages, '
+                                'use 0 to disable')
+        extra.add_argument('--quiet', action='store_true',
+                           help='quiet logging: only be verbose on errors')
+        extra.add_argument('--debug', action='append', metavar='LOGGER',
+                           help='assign debug level to logger(s)')
+        extra.add_argument('--info', action='append', metavar='LOGGER',
+                           help='assign info level to logger(s)')
+        extra.add_argument('--warn', action='append', metavar='LOGGER',
+                           help='assign warning level to logger(s)')
+
+        try:
+            # all arguments after `--` are forwarded to QEMU
+            pos = sys.argv.index('--')
+            sargv = sys.argv[1:pos]
+            opts = sys.argv[pos+1:]
+        except ValueError:
+            sargv = sys.argv[1:]
+            opts = []
+        cli_opts = list(opts)
+        args = argparser.parse_args(sargv)
+        if args.dbg is not None:
+            debug = args.dbg
+
+        if _HJSON_ERROR:
+            argparser.error('Missing HJSON module: {_HJSON_ERROR}')
+
+        if args.summary:
+            if not args.result:
+                tmpfd, tmp_result = mkstemp(suffix='.csv')
+                close(tmpfd)
+                args.result = tmp_result
+            result_file = args.result
+
+        log = configure_loggers(args.verbose, 'pyot',
+                                -1, 'flashgen', 'elf', 'otp', 'pyot.file', 1,
+                                args.vcp_verbose or 0,
+                                'pyot.vcp', name_width=30,
+                                filelog=args.log_file,
+                                ms=args.log_time, quiet=args.quiet,
+                                debug=args.debug, info=args.info,
+                                warning=args.warn)[0]
+
+        qfm = FileManager(args.keep_tmp)
+        qfm.set_qemu_src_dir(qemu_dir)
+
+        if args.log_udp != 0:
+            rlog = RemoteLogService(port=args.log_udp)
+            rlog.start()
+            qfm.set_udp_log_port(rlog.port)
+
+        # this is a bit circomvulted, as we need to parse the config filename
+        # if any, and load the default values out of the configuration file,
+        # without overriding any command line argument that should take
+        # precedence. set_defaults() does not check values for validity, so it
+        # cannot be used as JSON configuration may also contain invalid values
+        json = {}
+        if args.config:
+            qfm.set_config_dir(dirname(args.config.name))
+            json = jload(args.config)
+            if 'aliases' in json:
+                aliases = json['aliases']
+                if not isinstance(aliases, dict):
+                    argparser.error('Invalid aliases definitions')
+                qfm.define(aliases)
+            jdefaults = json.get('default', {})
+            xcolors = jdefaults.get('vcp-color', [])
+            if xcolors:
+                # config file -only option, not exposed to the argparser
+                del jdefaults['vcp-color']
+                ColorLogFormatter.override_xcolors(xcolors)
+            jargs = []
+            for arg, val in jdefaults.items():
+                is_bool = isinstance(val, bool)
+                if is_bool:
+                    if not val:
+                        continue
+                optname = f'--{arg}' if len(arg) > 1 else f'-{arg}'
+                if isinstance(val, list):
+                    val = flatten(v.split() for v in val)
+                    for valit in val:
+                        jargs.append(f'{optname}={qfm.interpolate(valit)}')
+                else:
+                    jargs.append(optname)
+                    if is_bool:
+                        continue
+                    # arg parser expects only string args, and substitute shell
+                    # env.
+                    val = qfm.interpolate(val)
+                    jargs.append(val)
+            if jargs:
+                jwargs = argparser.parse_args(jargs)
+                # pylint: disable=protected-access
+                for name, val in jwargs._get_kwargs():
+                    if not hasattr(args, name):
+                        argparser.error(f'Unknown config file default: {name}')
+                    if getattr(args, name) is None:
+                        setattr(args, name, val)
+            opts = json.get('opts', [])
+            if not isinstance(opts, list):
+                argparser.error("'opts' should be defined as a list")
+            opts = [opt for optline in json.get('opts', [])
+                    for opt in optline.split() if opt]
+            opts.extend(getattr(args, 'opts', None) or [])
+            setattr(args, 'opts', opts)
+        elif args.filter:
+            argparser.error('Filter option only valid with a config file')
+        if cli_opts:
+            qopts = getattr(args, 'opts') or []
+            qopts.extend(cli_opts)
+            setattr(args, 'opts', qopts)
+        for otcfg in args.otcfg or []:
+            if not isfile(otcfg):
+                argparser.error(f'Invalid OpenTitan configuration file '
+                                f'{otcfg}')
+        # as the JSON configuration file may contain default value, the
+        # argparser default method cannot be used to define default values, or
+        # they would take precedence over the JSON defined ones
+        defaults = {
+            'qemu': qemu_path,
+            'timeout': DEFAULT_TIMEOUT,
+            'device': DEFAULT_DEVICE,
+            'machine': DEFAULT_MACHINE,
+        }
+        for name, val in defaults.items():
+            if getattr(args, name) is None:
+                setattr(args, name, val)
+        if args.qemu:
+            qfm.set_qemu_bin_dir(dirname(args.qemu))
+        qexc = QEMUExecuter(qfm, json, args)
+        if args.list:
+            for tst in qexc.enumerate_tests():
+                print(tst)
+            sys.exit(0)
+        try:
+            qexc.build()
+        except ValueError as exc:
+            if debug:
+                print(format_exc(chain=False), file=sys.stderr)
+            argparser.error(str(exc))
+        ret = qexc.run(debug, args.zero)
+        log.debug('End of execution with code %d', ret or 0)
+        if rlog:
+            # leave extra time for last logging packets to be received
+            sleep(0.1)
+        sys.exit(ret)
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'{linesep}Error: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+    finally:
+        if rlog:
+            rlog.stop()
+        if result_file:
+            rfmt = ResultFormatter()
+            try:
+                rfmt.load(result_file)
+                rfmt.show(True, QEMUExecuter.RESULT_MAP.get(ret))
+            # pylint: disable=broad-except
+            except Exception as exc:
+                print(f'Cannot generate result file: {exc}', file=sys.stderr)
+                if debug:
+                    print(format_exc(chain=False), file=sys.stderr)
+        if tmp_result and isfile(tmp_result):
+            unlink(tmp_result)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/requirements.txt b/scripts/opentitan/requirements.txt
new file mode 100644
index 0000000000000..8877b67bbb7ec
--- /dev/null
+++ b/scripts/opentitan/requirements.txt
@@ -0,0 +1,7 @@
+# Python requirements
+pylint>=3.3.3, <4.0
+flake8>=7.3.0, <8.0
+pyyaml>=6
+hjson>=3.1
+pyelftools>=0.30
+pycryptodome>=3.12
diff --git a/scripts/opentitan/romtool.py b/scripts/opentitan/romtool.py
new file mode 100755
index 0000000000000..02e5d45d5e116
--- /dev/null
+++ b/scripts/opentitan/romtool.py
@@ -0,0 +1,99 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU OT tool to generate a scrambled ROM image.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+# pylint: disable=invalid-name
+# pylint: enable=invalid-name
+
+from argparse import ArgumentParser, FileType
+from os.path import dirname, join as joinpath, normpath
+from traceback import format_exception
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+# ruff: noqa: E402
+from ot.rom.image import ROMImage
+from ot.util.arg import ArgError
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt
+
+
+def main():
+    """Main routine"""
+    debug = True
+    desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+    argparser = ArgumentParser(description=f'{desc}.')
+    out_formats = list(ROMImage.save_formats)
+    # make hex format, if supported, the first (default) one
+    out_formats.sort(key=lambda x: x if x != 'HEX' else '')
+    try:
+
+        files = argparser.add_argument_group(title='Files')
+        files.add_argument('rom', nargs=1, type=FileType('rb'),
+                           help='input ROM image file')
+        files.add_argument('-c', '--config', type=FileType('rt'),
+                           metavar='CFG', required=True,
+                           help='input QEMU OT config file')
+        files.add_argument('-o', '--output',
+                           help='output ROM image file')
+
+        params = argparser.add_argument_group(title='Parameters')
+        params.add_argument('-D', '--digest', action='store_true',
+                            help='Show the ROM digest')
+        params.add_argument('-f', '--output-format', choices=out_formats,
+                            default=out_formats[0],
+                            help=f'Output file format '
+                                 f'(default: {out_formats[0]})')
+        params.add_argument('-i', '--rom-id', type=int,
+                            help='ROM image identifier')
+        params.add_argument('-s', '--subst-perm', action='store_true',
+                            help='Enable legacy mode with S&P mode')
+        params.add_argument('-z', '--rom-size', metavar='SIZE',
+                            type=HexInt.xparse,
+                            help='ROM image size in bytes (accepts Ki suffix)')
+
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'romimg', -1, name_width=12)
+
+        rom_img = ROMImage(None, args.subst_perm)
+        rom_img.load_config(args.config, args.rom_id)
+        rom_img.load(args.rom[0], args.rom_size)
+
+        if args.digest:
+            print('Digest:', rom_img.hexdigest)
+
+        with open(args.output, 'wb') if args.output else \
+                sys.stdout.buffer as wfp:
+            rom_img.save(wfp, args.output_format)
+
+    except ArgError as exc:
+        argparser.error(str(exc))
+    except (IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(''.join(format_exception(exc, chain=False)),
+                  file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/run-bazel-tests.sh b/scripts/opentitan/run-bazel-tests.sh
new file mode 100755
index 0000000000000..ad5d42b4c3158
--- /dev/null
+++ b/scripts/opentitan/run-bazel-tests.sh
@@ -0,0 +1,142 @@
+#!/usr/bin/env sh
+# Copyright (c) 2025 lowRISC contributors.
+
+set -e
+
+# This script will run all QEMU tests in the provided OpenTitan repository,
+# comparing the results with a list of expected passes.
+#
+# USAGE: run-bazel-tests.sh path/to/opentitan/repo path/to/qemu/repo \
+#            [execution environment] [test_timeout]
+#
+# There is a companion file `tests/opentitan/data/earlgrey-tests.txt` that
+# is read by this script.
+# 
+# The idea is to keep the list of passing tests up to date as QEMU changes.
+#
+# * If a test starts passing, add it with a `pass` status to the test
+#   list to catch regressions.
+# * When a test starts failing, investigate why and fix it, or remove it
+#   from the test list if necessary.
+#
+# Tests which are marked `flaky` and may pass/fail randomly will still be run,
+# but can be marked as such to prevent them from causing warnings or failures.
+
+# CI-only job summary feature - write to `/dev/null` when run locally.
+GITHUB_STEP_SUMMARY="${GITHUB_STEP_SUMMARY:-/dev/null}"
+
+# CLI arguments:
+opentitan_path="$1"
+qemu_path="$2"
+qemu_exec_env="$3"
+test_timeout="$4"
+if [ ! -d "$opentitan_path" ] || [ ! -d "$qemu_path" ]; then
+  echo "USAGE: ${0} <OPENTITAN REPO> <QEMU REPO> [<EXEC ENV>] [<TIMEOUT>]"
+  exit 1
+fi
+opentitan_path="$(realpath "$opentitan_path")"
+qemu_path="$(realpath "$qemu_path")"
+if [ -z "$qemu_exec_env" ]; then
+  # catch-all tag for all QEMU exec envs
+  qemu_exec_env="qemu"
+  echo "Using default 'qemu' tag to test all exec envs"
+fi
+
+# Lists of passing and flaky OpenTitan tests:
+tests_path="${qemu_path}/tests/opentitan/data/earlgrey-tests.txt"
+
+# Ensure QEMU has already been built in `./build`:
+if [ ! -x "${qemu_path}/build/qemu-system-riscv32" ]; then
+  echo >&2 "ERROR: expected QEMU binary at '${qemu_path}/build/qemu-system-riscv32'"
+  exit 1
+fi
+
+# Check if needed Bazel repository override files exist
+prev_bazel_files=false
+if [ -f "${qemu_path}/REPO.bazel" ]; then
+  prev_bazel_files=true
+else
+  # Add temporary Bazel `REPO.bazel` file
+  touch "${qemu_path}/REPO.bazel"
+fi
+
+if [ -f "${qemu_path}/BUILD" ]; then
+  prev_bazel_files=true
+else
+  # Add temporary Bazel 'BUILD' file
+  ln -s                                                             \
+    "${opentitan_path}/third_party/qemu/BUILD.qemu_opentitan.bazel" \
+    "${qemu_path}/BUILD"
+fi
+
+
+# Temporary files used by this script:
+results="$(mktemp)"
+flaky="$(mktemp)"
+expected="$(mktemp)"
+all_passed="$(mktemp)"
+passed="$(mktemp)"
+cleanup() {
+  if [ "$prev_bazel_files" != "true" ]; then
+    rm -f "${qemu_path}/REPO.bazel" "${qemu_path}/BUILD"
+  fi
+  rm -f "$results" "$flaky" "$expected" "$all_passed" "$passed" 
+}
+trap "cleanup" EXIT
+
+## RUN BAZEL TESTS
+cd "$opentitan_path" >/dev/null
+
+test_args=""
+if [ -n "$test_timeout" ]; then
+  test_args="--test_timeout=$test_timeout"
+fi
+
+./bazelisk.sh test //...                                    \
+  --test_tag_filters="$qemu_exec_env"                       \
+  --test_summary="short"                                    \
+  --test_output=all                                         \
+  --override_repository="+qemu+qemu_opentitan=${qemu_path}" \
+  --build_tests_only                                        \
+  $test_args                                                \
+  | tee "$results"
+
+## COMPARE RESULTS
+
+# Ensure the flaky tests are sorted with the current locale.
+grep "flaky:.*$qemu_exec_env" "$tests_path" | cut -d" " -f2 | sort -u > "$flaky"
+
+# Load the list of passing tests
+grep -E "pass(ing)?:.*$qemu_exec_env" "$tests_path" | cut -d" " -f2 | sort -u > "$expected"
+
+# Find all the tests which passed in Bazel:
+grep "PASSED[^:]" "$results" | cut -d' ' -f1 | sort > "$all_passed"
+
+# Filter out the flaky tests:
+comm -23 "$all_passed" "$flaky" > "$passed"
+
+## REPORT MISMATCHES
+
+unexpected_failures="$(comm -13 "$passed" "$expected")"
+unexpected_passes="$(comm -23 "$passed" "$expected")"
+
+status=0
+
+if [ -n "$unexpected_failures" ]; then
+  echo                                                      | tee -a "$GITHUB_STEP_SUMMARY" >&2
+  echo "Tests that we expected to pass which did NOT pass:" | tee -a "$GITHUB_STEP_SUMMARY" >&2
+  echo "$unexpected_failures" | awk '$0="- `"$0"`"'         | tee -a "$GITHUB_STEP_SUMMARY" >&2
+  status=1
+
+  echo >&2 "::error::There were some unexpected test failures"
+fi
+
+if [ -n "$unexpected_passes" ]; then
+  echo                                                          | tee -a "$GITHUB_STEP_SUMMARY" >&2
+  echo "Tests which passed but we did NOT expect them to pass:" | tee -a "$GITHUB_STEP_SUMMARY" >&2
+  echo "$unexpected_passes" | awk '$0="- `"$0"`"'               | tee -a "$GITHUB_STEP_SUMMARY" >&2
+
+  echo >&2 "::warning::Some tests passed which we did not expect"
+fi
+
+exit $status
diff --git a/scripts/opentitan/spidevflash.py b/scripts/opentitan/spidevflash.py
new file mode 100755
index 0000000000000..f19e8725cf7af
--- /dev/null
+++ b/scripts/opentitan/spidevflash.py
@@ -0,0 +1,200 @@
+#!/usr/bin/env python3
+
+"""SPI device flasher tool.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+# Copyright (c) 2024-2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+from argparse import ArgumentParser, FileType
+from logging import getLogger
+from os import linesep
+from os.path import dirname, join as joinpath, normpath
+from time import sleep, time as now
+from traceback import format_exc
+from typing import Optional, Union
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ot.spi import JedecId, SpiDevice
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt
+
+
+class SpiDeviceFlasher:
+    """Simple SPI device flasher, using OT protocol.
+    """
+
+    DEFAULT_SYNC_TIME = 5.0
+    """Default synchronization max time."""
+
+    DEFAULT_PORT = 8004
+    """Default TCP port for SPI device."""
+
+    JEDEC_MANUFACTURER = (12, 0xef)
+    """Expected JEDEC manufacturer."""
+
+    def __init__(self):
+        self._log = getLogger('spidev.flash')
+        self._spidev = SpiDevice()
+
+    def connect(self, host: str, port: Optional[int], retry_count: int = 1,
+                sync_time: Optional[float] = None):
+        """Connect to the remote SPI device and wait for sync.
+
+           :param host: a hostname or a connection string
+           :param port: a TCP port, should be None if a connection string is
+                        defined
+           :param retry_count: how many attempts should be made at most to
+                               coonnect to the remote peer (once per second)
+           :param sync_time: max allowed synchronization time once a connection
+                             is established to receive a valid JEDEC ID.
+
+           Supported connection string format:
+            - tcp:<host>:<port>
+            - unix:<path>
+        """
+        while True:
+            try:
+                self._spidev.connect(host, port)
+                break
+            except TimeoutError:
+                retry_count -= 1
+                if not retry_count:
+                    raise
+        duration = now()
+        self._log.info('Synchronizing')
+        jedec_id = self._synchronize(sync_time or self.DEFAULT_SYNC_TIME)
+        if (jedec_id.bank, jedec_id.jedec[0]) != self.JEDEC_MANUFACTURER:
+            raise ValueError(f'Unexpected manufacurer '
+                             f'{jedec_id.bank}:{jedec_id.jedec[0]}')
+        duration = now() - duration
+        self._log.info('Synchronization completed in %.0f ms', duration * 1000)
+
+    def disconnect(self):
+        """Disconnect from the remote host."""
+        self._spidev.power_down()
+
+    def program(self, data: Union[bytes, bytearray], offset: int = 0):
+        """Programm a buffer into the remote flash device."""
+        start = now()
+        total = 0
+        page_size = 256
+        page_count = (len(data) + page_size - 1) // page_size
+        self._log.info('Chip erase')
+        self._spidev.enable_write()
+        self._spidev.chip_erase()
+        self._spidev.wait_idle(timeout=self.DEFAULT_SYNC_TIME, pace=0.1)
+        self._log.info('Upload file')
+        for pos in range(0, len(data), page_size):
+            page = data[pos:pos+page_size]
+            self._log.debug('Program page @ 0x%06x %d/%d, %d bytes',
+                            pos + offset, pos//page_size, page_count, len(page))
+            self._spidev.enable_write()
+            self._spidev.page_program(pos + offset, page)
+            self._spidev.wait_idle(timeout=self.DEFAULT_SYNC_TIME,
+                                   pace=0.01)
+            total += len(page)
+        delta = now() - start
+        msg = f'{delta:.1f}s to send {total/1024:.1f}KB: ' \
+              f'{total/(1024*delta):.1f}KB/s'
+        self._log.info('%s', msg)
+        self._spidev.reset()
+
+    def _synchronize(self, timeout: float) -> JedecId:
+        """Wait for remote peer to be ready."""
+        # use JEDEC ID presence as a sycnhronisation token
+        # remote SPI device firware should set JEDEC ID when it is full ready
+        # to handle requests
+        expire = now() + timeout
+        while now() < expire:
+            jedec_id = self._spidev.read_jedec_id()
+            jedec = set(jedec_id.jedec)
+            if len(jedec) > 1 or jedec.pop() not in (0x00, 0xff):
+                return jedec_id
+            sleep(0.1)
+        raise RuntimeError('Remote SPI device not ready')
+
+
+def main():
+    """Main routine"""
+    debug = True
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('-f', '--file', type=FileType('rb'),
+                               required=True,
+                               help='Binary file to flash')
+        argparser.add_argument('-a', '--address', type=HexInt.parse,
+                               default='0',
+                               help='Address in the SPI flash (default: 0)')
+        argparser.add_argument('-S', '--socket',
+                               help='connection string')
+        argparser.add_argument('-R', '--retry-count', type=int, default=1,
+                               help='connection retry count (default: 1)')
+        argparser.add_argument('-T', '--sync-time', type=float,
+                               default=SpiDeviceFlasher.DEFAULT_SYNC_TIME,
+                               help=f'synchronization max time (default: '
+                                    f'{SpiDeviceFlasher.DEFAULT_SYNC_TIME:.1f}'
+                                    f's)')
+        argparser.add_argument('--idle', type=float, metavar='DELAY',
+                               help='stay idle before establish connection')
+        argparser.add_argument('-t', '--terminate', action='store_true',
+                               help='terminate QEMU VM on completion')
+        argparser.add_argument('-r', '--host',
+                               help='remote host name (default: localhost)')
+        argparser.add_argument('-p', '--port', type=int,
+                               help=f'remote host TCP port (default: '
+                                    f'{SpiDeviceFlasher.DEFAULT_PORT})')
+        argparser.add_argument('--log-udp', type=int, metavar='UDP_PORT',
+                               help='Log to a local UDP logger')
+        argparser.add_argument('-v', '--verbose', action='count',
+                               help='increase verbosity')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        log = configure_loggers(args.verbose, 'spidev', -1, 'spidev.dev',
+                                udplog=args.log_udp)[0]
+
+        if args.idle:
+            log.info('Idling for %.1f seconds', args.idle)
+            sleep(args.idle)
+
+        flasher = SpiDeviceFlasher()
+        if args.socket:
+            if any((args.host, args.port)):
+                argparser.error('Connection string is mutually exclusive '
+                                'with host and port')
+            flasher.connect(args.socket, None, retry_count=args.retry_count,
+                            sync_time=args.sync_time)
+        else:
+            flasher.connect(args.host or 'localhost',
+                            args.port or SpiDeviceFlasher.DEFAULT_PORT,
+                            retry_count=args.retry_count,
+                            sync_time=args.sync_time)
+        data = args.file.read()
+        args.file.close()
+        flasher.program(data, args.address)
+        if args.terminate:
+            flasher.disconnect()
+
+        sys.exit(0)
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'{linesep}Error: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/spiflashpat.py b/scripts/opentitan/spiflashpat.py
new file mode 100755
index 0000000000000..9fde89e95bedd
--- /dev/null
+++ b/scripts/opentitan/spiflashpat.py
@@ -0,0 +1,169 @@
+#!/usr/bin/env python3
+
+"""SPI flash pattern generator tiny tool.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+# Copyright (c) 2024 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+from argparse import ArgumentParser
+from logging import getLogger
+from os import SEEK_SET, linesep, stat, truncate, unlink
+from os.path import dirname, exists, join as joinpath, normpath
+from traceback import format_exc
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ot.util.log import configure_loggers
+from ot.util.misc import HexInt
+
+
+class SpiFlashPatternGenerator:
+    """Tiny pattern generator for SPI flash device image."""
+
+    def __init__(self, size: int, path: str, big_endian: bool):
+        self._log = getLogger('spiflash.gen')
+        self._size = size
+        self._path = path
+        self._be = big_endian
+
+    def resize(self, reset: bool) -> None:
+        """Resize the flash image to the expected flash size.
+           Either truncate or zero-extend the image to match the target size.
+
+           :param reset: whether to clear out any existing flash image content.
+        """
+        if reset and exists(self._path):
+            unlink(self._path)
+        try:
+            stat_res = stat(self._path)
+        except FileNotFoundError:
+            self._log.info('Creating file of %d bytes', self._size)
+            with open(self._path, 'wb') as ffp:
+                ffp.write(bytes(self._size))
+            return
+        size = stat_res.st_size
+        if size > self._size:
+            self._log.info('Truncating file from %d bytes down to %d bytes',
+                           size, self._size)
+            truncate(self._path, self._size)
+        elif size < self._size:
+            self._log.info('Extending file from %d bytes up to %d bytes',
+                           size, self._size)
+            with open(self._path, 'ab') as ffp:
+                ffp.write(bytes(self._size - size))
+
+    def generate(self, address: int, byte_count: int, inc: int, length: int,
+                 width: int) -> None:
+        """Generate binary patterns as flash content.
+
+           :param address: start address of the first pattern
+           :param byte_count: how many bytes to generate
+           :param inc: increment value between each pattern
+           :param length: pattern length in byte
+           :param width: pattern width in bits, i.e. pattern repetition inside
+                         a single length-long pattern
+        """
+        count = byte_count // length
+        nlen = length * 2
+        dbg_str = f'Old val: 0x%0{nlen}x, new val: 0x%0{nlen}x, length: %d'
+        with open(self._path, 'r+b') as ffp:
+            ffp.seek(address, SEEK_SET)
+            rdata = ffp.read(length)
+            value = int.from_bytes(rdata, 'big' if self._be else 'little')
+            while count:
+                count -= 1
+                nvalue = self._gen_next_value(value, inc, length, width)
+                wdata = nvalue.to_bytes(length, 'big' if self._be else 'little')
+                self._log.debug(dbg_str, value, nvalue, len(wdata))
+                ffp.write(wdata)
+                value = nvalue
+
+    def _gen_next_value(self, value: int, inc: int, length: int, width: int) \
+            -> int:
+        out = 0
+        for pos in range(0, length * 8, width):
+            mask = (1 << width) - 1
+            val = (value >> pos) & mask
+            val = (val + inc) & mask
+            out |= val << pos
+        return out
+
+
+def main():
+    """Main routine"""
+    debug = True
+    widths = {
+        'nibble': 4,
+        'byte': 8,
+        'half': 16,
+        'word': 32,
+        'double': 64,
+    }
+
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('-f', '--file', required=True,
+                               help='Flash image file')
+        argparser.add_argument('-a', '--address', type=HexInt.xparse,
+                               default='0',
+                               help='Start address')
+        argparser.add_argument('-b', '--big-endian', action='store_true',
+                               help='Use big-endian encoding (default: little)')
+        argparser.add_argument('-c', '--count', default='0', type=HexInt.xparse,
+                               help='How many bytes to generate')
+        argparser.add_argument('-i', '--inc', default=1, type=int,
+                               help='Increment, may be negative (default: 1)')
+        argparser.add_argument('-l', '--length', choices=list(widths)[1:],
+                               default='byte',
+                               help='Length of each slot (default: byte)')
+        argparser.add_argument('-r', '--reset', action='store_true',
+                               help='Reset the flash image content (to 0)')
+        argparser.add_argument('-s', '--size', type=HexInt.xparse,
+                               default='64MiB',
+                               help='Flash image size (default: 64MiB)')
+        argparser.add_argument('-w', '--width', choices=widths, default='byte',
+                               help='Pattern width for each slot '
+                                    '(default: byte)')
+        argparser.add_argument('-v', '--verbose', action='count',
+                               help='increase verbosity')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'spiflash')
+
+        length = widths[args.length] // 8
+        if args.address + length > args.size:
+            argparser.error('Start address cannot extend after end of file')
+        bitwidth = widths[args.width]
+        if bitwidth > length * 8:
+            argparser.error('Pattern width larger than slot size')
+
+        flasher = SpiFlashPatternGenerator(args.size, args.file,
+                                           args.big_endian)
+        flasher.resize(args.reset)
+        flasher.generate(args.address, args.count, args.inc, length,
+                         bitwidth)
+
+        sys.exit(0)
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'{linesep}Error: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/swexit.py b/scripts/opentitan/swexit.py
new file mode 100755
index 0000000000000..953a6e724593b
--- /dev/null
+++ b/scripts/opentitan/swexit.py
@@ -0,0 +1,95 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""OpenTitan exit code generator for QEMU.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, FileType
+from struct import pack as spack
+from traceback import format_exc
+from typing import Union
+import sys
+
+# pylint: disable=missing-function-docstring
+
+BASE_ADDRESS = {
+    'earlgrey': 0x411f0000,
+    'darjeeling': 0x211f0000,
+    'ibexdemo': 0x20000,
+}
+
+LUI_MASK = (1 << 12) - 1
+
+
+def to_int(value: Union[int, str]) -> int:
+    if isinstance(value, int):
+        return value
+    return int(value.strip(), value.startswith('0x') and 16 or 10)
+
+
+def opentitan_code(addr: int) -> bytes:
+    addr &= ~LUI_MASK
+    lui = addr | 0x537
+    return spack('<IIII',
+                 lui,         # lui  a0,addr     # ibex_core_wrapper base
+                 0xc0de05b7,  # lui  a1,0xc0de0  # exit code (0)
+                 0x00b52423,  # sw   a1,8(a0)    # write to sw_fatal_err
+                 0x10500073)  # wfi              # stop here
+
+
+def ibexdemo_code(addr: int) -> bytes:
+    addr &= ~LUI_MASK
+    lui = addr | 0x537
+    return spack('<IIII',
+                 lui,         # lui  a0,addr     # simulator_ctrl base
+                 0x00100593,  # li   a1,1        # set bit 0 to exit
+                 0x00b52423,  # sw   a1,8(a0)    # write to sim_ctrl
+                 0x10500073)  # wfi              # stop here
+
+
+def main():
+    debug = False
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}')
+        argparser.add_argument('-a', '--address', type=to_int,
+                               help='Base address for swexit device '
+                                    '(default: depends on SoC)')
+        argparser.add_argument('-b', '--base', type=to_int, default=0x80,
+                               help='Offset for the first instruction '
+                                    '(default: 0x80)')
+        argparser.add_argument('-t', '--soc', choices=list(BASE_ADDRESS),
+                               help='SoC type', required=True)
+        argparser.add_argument('-o', '--output', type=FileType('wb'),
+                               help='output file, default to stdout')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        addr = args.address if args.address else BASE_ADDRESS[args.soc]
+        if args.soc == 'ibexdemo':
+            bincode = ibexdemo_code(addr)
+        else:
+            bincode = opentitan_code(addr)
+        out = args.output or sys.stdout.buffer
+        padding = bytes(args.base)
+        out.write(padding)
+        out.write(bincode)
+
+    # pylint: disable=broad-except
+    except Exception as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/tap.py b/scripts/opentitan/tap.py
new file mode 100755
index 0000000000000..85f044ec3720c
--- /dev/null
+++ b/scripts/opentitan/tap.py
@@ -0,0 +1,656 @@
+#!/usr/bin/env python3
+
+"""JTAG TAP controller tiny simulator.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+# Copyright (c) 2022-2024 Rivos, Inc.
+# All rights reserved.
+
+from argparse import ArgumentParser
+from enum import IntEnum
+from logging import getLogger
+from os.path import dirname, join as joinpath, normpath
+from socket import create_server, socket, SHUT_RDWR
+from traceback import format_exc
+from typing import Optional
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ot.util.log import configure_loggers
+
+# pylint: disable-msg=missing-function-docstring,empty-docstring
+# pylint: disable-msg=too-few-public-methods
+# pylint: disable-msg=too-many-instance-attributes
+
+
+class TAPState(IntEnum):
+    """
+    """
+    TEST_LOGIC_RESET = 0
+    RUN_TEST_IDLE = 1
+    SELECT_DR_SCAN = 2
+    CAPTURE_DR = 3
+    SHIFT_DR = 4
+    EXIT1_DR = 5
+    PAUSE_DR = 6
+    EXIT2_DR = 7
+    UPDATE_DR = 8
+    SELECT_IR_SCAN = 9
+    CAPTURE_IR = 10
+    SHIFT_IR = 11
+    EXIT1_IR = 12
+    PAUSE_IR = 13
+    EXIT2_IR = 14
+    UPDATE_IR = 15
+
+
+class TAPRegister:
+    """
+    """
+
+    def __init__(self, name: str, length: int, reset: int):
+        self._log = getLogger(f'tap.{name}')
+        self._length = length
+        self._reset = reset
+        self._reg = self._reset
+
+    @property
+    def value(self) -> int:
+        return self._reg
+
+    def binstr(self, val: int) -> str:
+        return f'[{val:0{self._length}b}]'
+
+    def reset(self):
+        self._reg = self._reset
+
+    def capture(self):
+        self._reg = self._reset
+        self._log.info('capture %s', self.binstr(self._reg))
+
+    def shift(self, tdi: bool):
+        self._reg >>= 1
+        self._reg |= int(tdi) << (self._length-1)
+        self._log.debug('tdi:%u -> %s', tdi, self.binstr(self._reg))
+
+    def update(self):
+        self._log.info('update %s', self.binstr(self._reg))
+
+
+class TAP_BYPASS(TAPRegister):
+    """
+    """
+
+    # pylint: disable-msg=invalid-name
+
+    def __init__(self):
+        super().__init__('bypass', 1, 0)
+
+
+class TAP_IDCODE(TAPRegister):
+    """
+    """
+
+    # pylint: disable-msg=invalid-name
+
+    def __init__(self, idcode: int):
+        super().__init__('idcode', 32, idcode)
+
+
+class TAP_DTMCS(TAPRegister):
+    """
+    """
+
+    # pylint: disable-msg=invalid-name
+
+    IDLE_CYCLE = 0
+    VERSION = 1  # RISC-V Debug 0.13
+
+    # 31..18      17         16    15  14..12  11..10   9..4   3..0
+    #   0    dmihardreset dmireset  0   idle  dmistat  abits  version
+    #  14         W:1        W:1    1   R:3     R:2     R:6    R:4
+
+    def __init__(self, abits: int, dmi: 'TAP_DMI'):
+        super().__init__('dtmcs', 32, (self.VERSION << 0) | (abits << 4))
+        self._log = getLogger('tap.dtmcs')
+        self._dmi = dmi
+        self._dmistat = 0
+
+    def set_error_failed(self):
+        self._log.warning('Failure')
+        self._dmistat = 0b10
+
+    def set_error_busy(self):
+        self._log.warning('Busy')
+        self._dmistat = 0b11
+
+    def capture(self):
+        self._reg = self._reset | (self._dmistat << 10)
+
+    def update(self):
+        self._log.debug('%s', self.binstr(self._reg))
+        dmireset = bool((self._reg >> 16) & 0xb1)
+        dmihardreset = bool((self._reg >> 17) & 0xb1)
+        if dmireset:
+            self._log.warning('DMI reset')
+            self._dmistat = 0
+        if dmihardreset:
+            self._log.warning('DMI hard reset')
+            self._dmi.hardreset()
+
+
+class TAPController:
+    """
+    """
+
+    STATES = {
+        TAPState.TEST_LOGIC_RESET:
+            (TAPState.RUN_TEST_IDLE, TAPState.TEST_LOGIC_RESET),
+        TAPState.RUN_TEST_IDLE:
+            (TAPState.RUN_TEST_IDLE, TAPState.SELECT_DR_SCAN),
+        TAPState.SELECT_DR_SCAN:
+            (TAPState.CAPTURE_DR, TAPState.SELECT_IR_SCAN),
+        TAPState.CAPTURE_DR:
+            (TAPState.SHIFT_DR, TAPState.EXIT1_DR),
+        TAPState.SHIFT_DR:
+            (TAPState.SHIFT_DR, TAPState.EXIT1_DR),
+        TAPState.EXIT1_DR:
+            (TAPState.PAUSE_DR, TAPState.UPDATE_DR),
+        TAPState.PAUSE_DR:
+            (TAPState.PAUSE_DR, TAPState.EXIT2_DR),
+        TAPState.EXIT2_DR:
+            (TAPState.SHIFT_DR, TAPState.UPDATE_DR),
+        TAPState.UPDATE_DR:
+            (TAPState.RUN_TEST_IDLE, TAPState.SELECT_DR_SCAN),
+        TAPState.SELECT_IR_SCAN:
+            (TAPState.CAPTURE_IR, TAPState.TEST_LOGIC_RESET),
+        TAPState.CAPTURE_IR:
+            (TAPState.SHIFT_IR, TAPState.EXIT1_IR),
+        TAPState.SHIFT_IR:
+            (TAPState.SHIFT_IR, TAPState.EXIT1_IR),
+        TAPState.EXIT1_IR:
+            (TAPState.PAUSE_IR, TAPState.UPDATE_IR),
+        TAPState.PAUSE_IR:
+            (TAPState.PAUSE_IR, TAPState.EXIT2_IR),
+        TAPState.EXIT2_IR:
+            (TAPState.SHIFT_IR, TAPState.UPDATE_IR),
+        TAPState.UPDATE_IR:
+            (TAPState.RUN_TEST_IDLE, TAPState.SELECT_DR_SCAN)
+    }
+
+    def __init__(self, irlength: int, ext: Optional['TAPExtension'] = None):
+        self._log = getLogger('tap.ctrl')
+        self._trst = False
+        self._srst = False
+        self._tck = False
+        self._tms = False
+        self._tdi = False
+        self._tdo = False
+        self._ext = ext
+        self._ir = TAPRegister('ir', irlength, 0b01)
+        self._dr: Optional[TAPRegister] = None
+        self._state = TAPState.RUN_TEST_IDLE
+        self._bypass = TAP_BYPASS()
+        self._idcode = TAP_IDCODE(0x04f5484d)
+        self._reset()
+
+    def _next(self, tms: bool) -> TAPState:
+        self._state = self.STATES[self._state][int(tms)]
+        return self._state
+
+    def _reset(self):
+        self._ir.reset()
+        if self._dr:
+            self._dr.reset()
+
+    def _step(self, tck: bool, tms: bool, tdi: bool):
+        if not self._tck and tck:
+            # Clock rising edge
+            if self._state == TAPState.SHIFT_IR:
+                self._ir.shift(self._tdi)
+            elif self._state == TAPState.SHIFT_DR:
+                self._dr.shift(self._tdi)
+            old = self._state
+            new = self._next(self._tms)
+            self._log.debug('State %s -> %s', old, new)
+        else:
+            # Clock falling edge
+            if self._state == TAPState.RUN_TEST_IDLE:
+                pass
+            elif self._state == TAPState.TEST_LOGIC_RESET:
+                self._reset()
+            elif self._state == TAPState.CAPTURE_DR:
+                self._capture_dr(self._ir.value)
+            elif self._state == TAPState.SHIFT_DR:
+                self._tdo = self._dr.value & 0b1
+            elif self._state == TAPState.UPDATE_DR:
+                self._dr.update()
+            elif self._state == TAPState.SHIFT_IR:
+                self._tdo = self._ir.value & 0b1
+            elif self._state == TAPState.UPDATE_IR:
+                self._ir.update()
+        self._tck = tck
+        self._tdi = tdi
+        self._tms = tms
+
+    def _capture_dr(self, value: int):
+        old_dr = self._dr
+        if value in (0x00, 0x1f):
+            self._dr = self._bypass
+        elif value == 0x01:
+            self._dr = self._idcode
+        else:
+            if self._ext:
+                dreg = self._ext.get_by_value(value)
+                if not dreg:
+                    raise ValueError('Unknown ID code')
+                self._dr = dreg
+        self._dr.capture()
+        if self._dr != old_dr:
+            self._log.info('Select DR %s', self._dr.__class__.__name__)
+
+
+class BitBangController(TAPController):
+    """
+    """
+
+    BB_MAP = {
+        b'B': ('blink', (True,)),
+        b'b': ('blink', (False,)),
+        b'R': ('read', (),),
+        b'Q': ('quit', (),),
+        b'0': ('write', (False, False, False)),
+        b'1': ('write', (False, False, True)),
+        b'2': ('write', (False, True, False)),
+        b'3': ('write', (False, True, True)),
+        b'4': ('write', (True, False, False)),
+        b'5': ('write', (True, False, True)),
+        b'6': ('write', (True, True, False)),
+        b'7': ('write', (True, True, True)),
+        b'r': ('reset', (False, False)),
+        b's': ('reset', (False, True)),
+        b't': ('reset', (True, False)),
+        b'u': ('reset', (True, True)),
+    }
+
+    IR_LENGTH = 0x5
+
+    def __init__(self, *args, **kwargs):
+        super().__init__(self.IR_LENGTH, *args, **kwargs)
+        self._socket: Optional[socket] = None
+        self._resume = False
+        self._reset()
+
+    def run(self, port: int):
+        self._socket = create_server(('localhost', port), reuse_port=True)
+        while True:
+            self._socket.listen(0)
+            self._resume = True
+            while self._resume:
+                peer, addr = self._socket.accept()
+                with peer:
+                    self._log.info('Connection from %s:%d', *addr)
+                    while True:
+                        req = peer.recv(1)
+                        if not req:
+                            break
+                        resp = self._inject(req)
+                        if resp is not None:
+                            out = bytes((0x30 + int(resp),))
+                            self._log.debug('Out %s', out)
+                            peer.send(out)
+        self._socket.shutdown(SHUT_RDWR)
+        self._socket = None
+
+    def _inject(self, req: bytes) -> Optional[bool]:
+        self._log.debug('[%s]', req.decode())
+        try:
+            command, args = self.BB_MAP[req]
+        except KeyError:
+            self._log.error('Unknown input [%s]', req)
+            return None
+        handler = getattr(self, f'_inject_{command}', None)
+        if handler is None:
+            self._log.warning('Unimplemented handler for %s', command)
+            return None
+        # pylint: disable=not-callable
+        return handler(*args)
+
+    def _inject_quit(self):
+        self._log.info('Quit')
+        self._resume = False
+
+    def _inject_blink(self, enable: bool):
+        self._log.debug('Blink %u', enable)
+
+    def _inject_reset(self, trst: bool, srst: bool):
+        if trst != self._trst:
+            self._log.info('TAP reset %u', trst)
+            self._reset()
+        if trst != self._trst:
+            self._log.info('System reset %u', srst)
+        self._trst, self._srst = trst, srst
+
+    def _inject_read(self) -> bool:
+        self._log.debug('TDO %u', self._tdo)
+        return self._tdo
+
+    def _inject_write(self, tck: bool, tms: bool, tdi: bool):
+        self._log.debug('TCK %u TMS %u TDI %u', tck, tms, tdi)
+        self._step(tck, tms, tdi)
+
+
+class GPR(IntEnum):
+    """
+    """
+
+    # pylint: disable-msg=invalid-name
+
+    zero = 0
+    ra = 1
+    sp = 2
+    gp = 3
+    tp = 4
+    t0 = 5
+    t1 = 6
+    t2 = 7
+    fp = 8
+    s1 = 9
+    a0 = 10
+    a1 = 11
+    a2 = 12
+    a3 = 13
+    a4 = 14
+    a5 = 15
+    a6 = 16
+    a7 = 17
+    s2 = 18
+    s3 = 19
+    s4 = 20
+    s5 = 21
+    s6 = 22
+    s7 = 23
+    s8 = 24
+    s9 = 25
+    s10 = 26
+    s11 = 27
+    t3 = 28
+    t4 = 29
+    t5 = 30
+    t6 = 31
+
+
+class CSR(IntEnum):
+    """
+    """
+
+    MISA = 0x301
+
+
+def isa(ext: str):
+    """Create MISA word's bit from a letter
+    """
+    return 1 << (ord(ext[0].upper())-ord('A'))
+
+
+class TAP_DMI(TAPRegister):
+    """
+    See https://github.com/lowRISC/opentitan/blob/master/hw/vendor/
+               pulp_riscv_dbg/doc/debug-system.md
+    """
+
+    # pylint: disable-msg=invalid-name
+
+    class CmdErr(IntEnum):
+        """
+        """
+        NONE = 0
+        BUSY = 1
+        NOT_SUPPORTED = 2
+        EXCEPTION = 3
+        HALT_RESUME = 4
+        BUS = 5
+        OTHER = 7
+
+    DM_REGISTERS = {
+        0x10: 'dmcontrol',
+        0x11: 'dmstatus',
+        0x12: 'hartinfo',
+        0x16: 'abstractcs',
+        0x17: 'command',
+        0x38: 'sbcs'
+    }
+
+    DM_NAMES = {v: k for k, v in DM_REGISTERS.items()}
+
+    DATABASE = 0x4
+    PROGBUFBASE = 0x20
+
+    DATACOUNT = 10
+    PROGBUFSIZE = 8
+
+    # RV32IMC
+    RV32 = 0b01 << 30
+    MISA = RV32 | isa('I') | isa('M') | isa('C')
+
+    def __init__(self, abits: int):
+        super().__init__('dmi', 32 + 2 + abits, 0)
+        self._abits = abits
+        self._addr = 0
+        self._registers = {reg: 0 for reg in self.DM_REGISTERS}
+        self._is_halted = False
+        self._is_resumed = False
+        self._sb_error = 0
+        self._data = [0] * self.DATACOUNT
+        self._progbuf = [0] * self.PROGBUFSIZE
+        self._cmderr = TAP_DMI.CmdErr.NONE
+
+    def hardreset(self):
+        self._log.warning('HARD RESET')
+
+    def capture(self):
+        addr = self._addr
+        regname = self.DM_REGISTERS.get(addr)
+        if 0 <= addr-self.DATABASE < self.DATACOUNT:
+            data = self._data[addr-self.DATABASE]
+        elif 0 <= addr-self.PROGBUFBASE < self.PROGBUFSIZE:
+            data = self._progbuf[addr-self.PROGBUFBASE]
+        else:
+            data = self._registers.get(addr, 0)
+        self._reg = addr << (32 + 2) | (data << 2)
+        self._log.info('%s @ 0x%02x = 0x%08x', regname, addr, data)
+
+    def update(self):
+        opname = {
+            0: 'nop', 1: 'read', 2: 'write', 3: 'rsv'
+        }.get(self.value & 0b11)
+        if opname == 'nop':
+            return
+        addr = self.value >> (32 + 2) & ((1 << self._abits) - 1)
+        data = (self.value >> 2) & ((1 << 32) - 1)
+        write = opname == 'write'
+        self._addr = addr
+        if 0 <= addr-self.DATABASE < self.DATACOUNT:
+            if write:
+                self._data[addr-self.DATABASE] = data
+            return
+        if 0 <= addr-self.PROGBUFBASE < self.PROGBUFSIZE:
+            if write:
+                self._data[addr-self.DATABASE] = data
+            return
+        regname = self.DM_REGISTERS.get(addr)
+        if regname is None:
+            self._log.warning('Unsupported DM register 0x%02x', addr)
+        else:
+            self._log.info('%s @ %s [%02x]%s',
+                           opname, regname, addr,
+                           f' {data:08x}' if write else '')
+        handler = getattr(self, f'_{regname}_{opname}', None)
+        if handler:
+            # pylint: disable=not-callable
+            handler(data)
+
+    def _dmcontrol_write(self, value: int):
+        # harteq | hartsellen (== 0) | dmactive
+        mask = (1 << 31) | (0 << 16) | (1 << 0)
+        self._registers[self.DM_NAMES['dmcontrol']] = value & mask
+        if value & (1 << 31):
+            self._is_halted = True
+            self._is_resumed = False
+        elif value & (1 << 30):
+            self._is_halted = False
+            self._is_resumed = True
+
+    def _command_write(self, value: int):
+        cmdtype = value >> 24
+        if cmdtype == 0:
+            self._cmderr = self._access_register(value)
+        elif cmdtype == 1:
+            self._cmderr = self._quick_access(value)
+        elif cmdtype == 2:
+            self._cmderr = self._access_memory(value)
+
+    def _dmstatus_read(self, *_):
+        version = (TAP_DTMCS.VERSION + 1) << 0
+        authenticated = 1 << 7
+        allhalted = int(self._is_halted) << 9
+        anyhalted = int(self._is_halted) << 8
+        allresumed = int(self._is_resumed) << 17
+        anyresumed = int(self._is_resumed) << 16
+        regno = self.DM_NAMES['dmstatus']
+        self._registers[regno] = (version | authenticated |
+                                  allhalted | anyhalted |
+                                  allresumed | anyresumed)
+
+    def _hartinfo_read(self, *_):
+        data_addr = 0 << 0
+        data_size = 0 << 12
+        data_access = 0 << 16
+        nscratch = 0 << 20
+        regno = self.DM_NAMES['hartinfo']
+        self._registers[regno] = nscratch | data_access | data_size | data_addr
+
+    def _sbcs_read(self, *_):
+        sbaccess8 = 1 << 0
+        sbaccess16 = 1 << 1
+        sbaccess32 = 1 << 2
+        sbasize = 32 << 5
+        sberror = self._sb_error << 12
+        sbversion = 1 << 29
+        regno = self.DM_NAMES['sbcs']
+        self._registers[regno] = (sbaccess8 | sbaccess16 | sbaccess32 |
+                                  sbasize | sberror | sbversion)
+
+    def _abstractcs_read(self, *_):
+        progbufsize = self.PROGBUFSIZE << 24
+        busy = 0 << 12
+        cmderr = self._cmderr << 8
+        datacount = self.DATACOUNT << 0
+        regno = self.DM_NAMES['abstractcs']
+        self._registers[regno] = progbufsize | busy | cmderr | datacount
+
+    def _access_register(self, value: int) -> 'TAP_DMI.CmdErr':
+        regno = value & ((1 << 16) - 1)
+        write = bool(value & (1 << 16))
+        transfer = bool(value & (1 << 17))
+        postexec = bool(value & (1 << 18))
+        aarpostincrement = bool(value & (1 << 19))
+        aarsize = (value >> 20) & ((1 << 2) - 1)
+        aarbits = 1 << (3 + aarsize)
+        if transfer:
+            if aarbits > 32:
+                self._log.warning('Aarsize not supported %u for regno %03x',
+                                  aarsize, regno)
+                return TAP_DMI.CmdErr.NOT_SUPPORTED
+            if aarpostincrement:
+                self._log.warning('Post-increment not supported')
+            if postexec:
+                self._log.warning('Post-exec not supported')
+        if write:
+            self._log.warning('Write to reg 0x%04x not supported', regno)
+            return TAP_DMI.CmdErr.NOT_SUPPORTED
+        if 0 <= regno <= 0x0fff:
+            try:
+                csr = CSR(regno)
+            except ValueError:
+                csr = f'CSR 0x{regno:03x}'
+            self._log.warning('Want to read %s', csr)
+            if csr == CSR.MISA:
+                self._data[0] = TAP_DMI.MISA
+                return TAP_DMI.CmdErr.NONE
+            self._log.warning('MISA: %08x', self.MISA)
+        elif 0x1000 <= regno <= 0x101f:
+            gpr = regno-0x1000
+            self._log.warning('Want to read %s (x%d)', GPR(gpr), gpr)
+        elif 0x1020 <= regno <= 0x103f:
+            self._log.warning('Want to read FPR f%d', regno-0x1020)
+            return TAP_DMI.CmdErr.NOT_SUPPORTED
+        elif 0xc000 <= regno <= 0xffff:
+            self._log.warning('Want to read custom 0x%02x', regno-0xc000)
+        else:
+            self._log.warning('Invalid register 0x%04x', regno)
+            return TAP_DMI.CmdErr.NOT_SUPPORTED
+        return TAP_DMI.CmdErr.NONE
+
+    def _quick_access(self, _value: int) -> 'TAP_DMI.CmdErr':
+        return TAP_DMI.CmdErr.NOT_SUPPORTED
+
+    def _access_memory(self, _value: int) -> 'TAP_DMI.CmdErr':
+        return TAP_DMI.CmdErr.NOT_SUPPORTED
+
+
+class TAPExtension:
+    """Support basic RISC-V DTM register
+    """
+
+    def __init__(self, abits: int):
+        self._log = getLogger('tap.ext')
+        dmi = TAP_DMI(abits)
+        dtmcs = TAP_DTMCS(abits, dmi)
+        self._irs = {0x10: dtmcs, 0x11: dmi}
+
+    def get_by_value(self, value: int) -> Optional[TAPRegister]:
+        return self._irs.get(value, None)
+
+
+def main():
+    """Main routine.
+    """
+    debug = False
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('-p', '--port', type=int, default=3335,
+                               help='remote host TCP port (defaults to 3335)')
+        argparser.add_argument('-a', '--abits', type=int, default=7,
+                               help='address width in bits (defaults to 7)')
+        argparser.add_argument('-v', '--verbose', action='count',
+                               help='increase verbosity')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'tap')
+
+        ext = TAPExtension(args.abits)
+        tap = BitBangController(ext)
+        tap.run(args.port)
+        sys.exit(0)
+
+    except (IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/timelog.py b/scripts/opentitan/timelog.py
new file mode 100755
index 0000000000000..c0f77b0e8b1a0
--- /dev/null
+++ b/scripts/opentitan/timelog.py
@@ -0,0 +1,38 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Tiny tool to convert time absolute log time into relative log time.
+   It enables comparing different runs time-wise with log files produced
+   with OT scripts using the --log-time option.
+
+   timelog.py < pyot.log > pyot-rel.log
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from time import mktime, strptime
+from typing import Optional
+import sys
+
+
+def main():
+    """Main routine."""
+    ts_base: Optional[float] = None
+    for line in sys.stdin:
+        line = line.strip()
+        ts_str, msg = line.split(' ', 1)
+        ts_hms, ts_ms = ts_str.split('.', 1)
+        ts_f = mktime(strptime(ts_hms, '%H:%M:%S'))
+        # for some reason, strptime does not parse %f millisecond string
+        ts_f += float(f'.{ts_ms}')
+        if ts_base is None:
+            ts_base = ts_f
+        ts_rel = ts_f - ts_base
+        ts_srel = f'{ts_rel:.3f}'
+        print(f'{ts_srel:<8s} {msg}')
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/tktool.py b/scripts/opentitan/tktool.py
new file mode 100755
index 0000000000000..815179f80f4b5
--- /dev/null
+++ b/scripts/opentitan/tktool.py
@@ -0,0 +1,113 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2025 Rivos, Inc.
+# Copyright (c) 2025 lowRISC contributors.
+# SPDX-License-Identifier: Apache2
+
+"""LifeCycle Controller tiny token tools
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser, FileType
+from binascii import hexlify, unhexlify
+from os.path import dirname, join as joinpath, normpath
+from traceback import format_exception
+from typing import Optional
+
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+# ruff: noqa: E402
+from ot.util.log import configure_loggers
+
+_IEXC: Optional[Exception] = None  # noqa: F841
+try:
+    from ot.lc_ctrl.tools import LifeCycleTokenEngine
+except ImportError as _IEXC:  # noqa: F841
+    pass
+
+
+def main():
+    """Main routine"""
+    debug = True
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('-s', '--hash', metavar='TOKEN',
+                               help='hash the submitted token')
+        argparser.add_argument('-g', '--generate', metavar='TOKEN_NAME',
+                               help='generate a new token pair')
+        argparser.add_argument('-r', '--parse-rust', metavar='FILE',
+                               type=FileType('rt'),
+                               help='parse token from a Rust file')
+        argparser.add_argument('-t', '--token', metavar='NAME',
+                               help='only report named token')
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'tkgen', -1, 'otp')
+
+        if _IEXC is not None:
+            if debug:
+                print(''.join(format_exception(_IEXC, chain=False)),
+                      file=sys.stderr)
+            argparser.error(f'Missing PYTHONPATH: {_IEXC}')
+
+        tkeng = LifeCycleTokenEngine()
+
+        if args.hash:
+            token = unhexlify(args.hash)
+            hashed_str = hexlify(tkeng.hash(token)).decode()
+            # try to follow the same case for the result as the input
+            if args.hash == args.hash.upper():
+                hashed_str = hashed_str.upper()
+            print(hashed_str)
+
+        if args.generate:
+            tkpair = tkeng.generate()
+            prefix = args.generate.upper()
+            rust_code = tkeng.generate_code('rust', prefix, tkpair)
+            print(rust_code)
+            qemu_code = tkeng.generate_code('qemu', prefix, tkpair)
+            print(qemu_code)
+
+        if args.token and not args.parse_rust:
+            argparser.error('Token name requires Rust file')
+
+        if args.parse_rust:
+            rust = args.parse_rust.read()
+            args.parse_rust.close()
+            tkpairs = tkeng.parse_rust(rust)
+            if args.token:
+                token_name = args.token.upper()
+                if token_name not in tkpairs:
+                    argparser.error('No such token')
+                print(hexlify(tkpairs[token_name].text).decode().upper())
+            else:
+                for name, tkpair in tkpairs.items():
+                    for kind in tkpair.__annotations__:
+                        print(f'LC_{name}_TOKEN_{kind.upper()}='
+                              f'{hexlify(getattr(tkpair, kind)).decode()}')
+                    print()
+
+    except (IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(''.join(format_exception(exc, chain=False)), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/treillis/boot.py b/scripts/opentitan/treillis/boot.py
new file mode 100644
index 0000000000000..931aa4bfe58c4
--- /dev/null
+++ b/scripts/opentitan/treillis/boot.py
@@ -0,0 +1,12 @@
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Configuration file for CircuitPython."""
+
+# pylint: disable=import-error
+
+import usb_cdc
+import usb_midi
+
+usb_midi.disable()
+usb_cdc.enable(console=True, data=True)
diff --git a/scripts/opentitan/treillis/code.py b/scripts/opentitan/treillis/code.py
new file mode 100644
index 0000000000000..1a97cb32acdf6
--- /dev/null
+++ b/scripts/opentitan/treillis/code.py
@@ -0,0 +1,233 @@
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""Simple CircuitPython script that maps QEMU GPIO chardev backend device onto
+   a NeoTreillis M4 Express device.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+# pylint: disable=import-error
+# pylint: disable=invalid-name
+# pylint: disable=missing-function-docstring
+# pylint: disable=consider-using-f-string
+# pylint: disable=missing-class-docstring
+# pylint: disable=protected-access
+# pylint: disable=attribute-defined-outside-init
+
+try:
+    from time import monotonic_ns as now
+    import usb_cdc
+    from adafruit_trellism4 import TrellisM4Express
+except ImportError:
+    print('This code should run on Adafruit NeoTrellis M4 Express with '
+          'CircuitPython')
+    raise
+
+
+class OtGPIO:
+    """OpenTitan GPIO interface with an Adafruit NeoTrellis M4 Express.
+
+       Demonstrate the GPIO protocol over a QEMU CharDev.
+    """
+
+    GPO_ON = (20, 0, 0)  # red
+    GPO_OFF = (0, 20, 0)  # green
+    GPI_ON = (20, 20, 0)  # bright blue
+    GPI_OFF = (0, 0, 80)  # yellow
+    GP_HIZ = (1, 1, 1)  # greyish
+    GP_PU = (15, 5, 0)  # orange
+    GP_PD = (0, 8, 3)  # greenish-blue
+
+    LOCK_TIME_MS = 300   # key depressed time to lock/unlock an input key
+
+    def __init__(self, serial):
+        self._serial = serial
+        self._trellis = TrellisM4Express()
+        # be sure to disable auto-refresh, as this causes a full matrix
+        # dump on each pixel change
+        self._trellis.pixels.auto_write = False
+        pixels = self._trellis.pixels
+        self._cache = [(0, 0, 0)] * pixels.width * pixels.height
+        # bypass the Adafruit API which is far too slow
+        self._neopixels = pixels._neopixel
+        self._wipe()
+
+    def _wipe(self):
+        # 32-bit bitmaps
+        self._oe = 0  # output enable (1: out, 0: in)
+        self._out = 0  # output value (from peer)
+        self._hiz = 0xfffffff  # high-Z
+        self._wpud = 0  # weak pull (1: up 0: down)
+        self._inact = 0  # input activated
+        self._in = 0  # input value (to peer)
+        self._kin = 0  # keyboard input
+        pixels = self._trellis.pixels
+        self._cache = [(0, 0, 0)] * pixels.width * pixels.height
+        self._lock_in = 0  # locked keys
+        self._lock_time = {}  # when key has been first pressed (ns timestamp)
+
+    def _update_input(self, newval, force=False):
+        # pylint: disable=unused-argument
+        ts = now()
+        change = self._kin ^ newval
+        self._inact |= change
+        self._kin = newval
+        # handle flip-flop: if a key is pressed long enough, its new value
+        # is stored
+        for pos in range(32):
+            bit = 1 << pos
+            # only consider keys that change
+            if not bit & change:
+                continue
+            # is the key down?
+            down = bool(bit & newval)
+            if down:
+                self._lock_time[pos] = ts
+                continue
+            # key is released
+            dtime = self._lock_time.get(pos)
+            if dtime is None:
+                continue
+            delay_ms = (ts - dtime) // 1_000_000
+            if delay_ms > self.LOCK_TIME_MS:
+                # Lock action
+                on = bool(self._lock_in & bit)
+                if on:
+                    self._lock_in &= ~bit
+                else:
+                    self._lock_in |= bit
+                self._lock_time.pop(pos)
+        self._in = self._lock_in ^ newval
+        return change
+
+    def _update_output(self, newval):
+        change = (self._out ^ newval) & self._oe
+        self._out = newval
+        return change
+
+    def _refresh_input(self, update):
+        lastpix = len(self._cache) - 1
+        for pos in range(32):
+            bit = 1 << pos
+            if not bit & update:
+                continue
+            if self._inact & bit:
+                if self._in & bit:
+                    color = self.GPI_ON
+                else:
+                    color = self.GPI_OFF
+            else:
+                if self._hiz & bit:
+                    color = self.GP_HIZ
+                else:
+                    if self._wpud & bit:
+                        color = self.GP_PU
+                    else:
+                        color = self.GP_PD
+            pixel = lastpix - pos
+            if self._cache[pixel] != color:
+                self._neopixels[pixel] = color
+                self._cache[pixel] = color
+
+    def _refresh_output(self, update):
+        lastpix = len(self._cache) - 1
+        for pos in range(32):
+            bit = 1 << pos
+            if not update & bit:
+                continue
+            if self._out & bit:
+                color = self.GPO_ON
+            else:
+                color = self.GPO_OFF
+            pixel = lastpix - pos
+            if self._cache[pixel] != color:
+                self._neopixels[pixel] = color
+                self._cache[pixel] = color
+
+    def run(self):
+        self._serial.timeout = 0.005
+        self._serial.write_timeout = 0.5
+        # query QEMU to repeat I/O config on startup.
+        self._serial.write(b'R:00000000\r\n')
+        buf = bytearray()
+        last_kin = 0
+        last_kact = 0
+        force = False
+        change = False
+        while True:
+            if change:
+                self._trellis.pixels.show()
+                change = False
+            kin = 0
+            for x, y in self._trellis.pressed_keys:
+                kin |= 1 << (31 - (8 * y + x))
+            if last_kin != kin:
+                change = self._update_input(kin)
+                if not force:
+                    change &= ~self._oe
+                self._refresh_input(change)
+                if last_kact != self._inact:
+                    self._serial.write(b'M:%08x\r\n' % ~self._inact)
+                    last_kact = self._inact
+                self._serial.write(b'I:%08x\r\n' % self._in)
+            last_kin = kin
+            data = self._serial.read()
+            if not data:
+                self._serial.timeout = 0.005
+                continue
+            self._serial.timeout = 0
+            for b in data:
+                if b != 0x0d:
+                    buf.append(b)
+            pos = buf.find(b'\n')
+            if pos < 0:
+                continue
+            line = bytes(buf[:pos])
+            buf = buf[pos+1:]
+            if not line:
+                continue
+            if len(line) < 2 or line[1] != ord(':'):
+                continue
+            cmd = line[0]
+            try:
+                val = int(line[2:], 16)
+            except ValueError:
+                continue
+            change = True
+            if cmd == ord('D'):
+                # update I/O direction
+                self._oe = val
+                self._refresh_output(self._oe)
+                self._refresh_input(~self._oe)
+            elif cmd == ord('O'):
+                # update output
+                change = self._update_output(val)
+                self._refresh_output(change)
+            elif cmd == ord('Z'):
+                # update high-z
+                self._hiz = val
+                self._refresh_input(~self._oe)
+            elif cmd == ord('P'):
+                # update pull-up/pull-down
+                self._wpud = val
+                self._refresh_input(~self._oe)
+            elif cmd == ord('C'):
+                self._wipe()
+                self._refresh_output(self._oe)
+                self._refresh_input(~self._oe)
+            elif cmd == ord('Q'):
+                # QEMU query for current Input state
+                self._serial.write(b'M:%08x\r\n' % ~self._inact)
+                self._serial.write(b'I:%08x\r\n' % self._in)
+            else:
+                print('Unknown command %s' % cmd)
+
+
+if __name__ == '__main__':
+    if not usb_cdc.data:
+        # boot.py should be used to enable the secondary, data CDC
+        # serial-over-USB device. The first port is reserved for the Console.
+        raise RuntimeError('No serial port available')
+    gpio = OtGPIO(usb_cdc.data)
+    gpio.run()
diff --git a/scripts/opentitan/uartmux.py b/scripts/opentitan/uartmux.py
new file mode 100755
index 0000000000000..8a19922b17470
--- /dev/null
+++ b/scripts/opentitan/uartmux.py
@@ -0,0 +1,258 @@
+#!/usr/bin/env python3
+
+# Copyright (c) 2023-2024 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+"""QEMU UART muxer.
+
+   :author: Emmanuel Blot <eblot@rivosinc.com>
+"""
+
+from argparse import ArgumentParser
+from collections import deque
+from logging import getLogger
+from os.path import dirname, join as joinpath, normpath
+from socketserver import StreamRequestHandler, ThreadingTCPServer
+from threading import Event, Lock, Thread
+from traceback import format_exc
+from typing import Optional, TextIO
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+from ot.util.log import configure_loggers
+
+
+class UartHandler(StreamRequestHandler):
+    """Handle a single QEMU output stream.
+    """
+
+    def __init__(self, *args, **kwargs):
+        self._buffer = bytearray()
+        self._id = - 1
+        self._log = None
+        # init calls handle immediately, so local attributes need to be
+        # initialized first
+        super().__init__(*args, **kwargs)
+
+    def setup(self):
+        self._id = self.server.get_id(self)
+        self._log = getLogger(f'mux.h[{self._id}]')
+        self._log.debug('connected')
+        self.request.settimeout(0.2)
+
+    def finish(self):
+        self._log.debug('disconnected')
+        self.server.discard(self)
+
+    def handle(self):
+        self._log.debug('handle')
+        try:
+            while self.server.resume:
+                try:
+                    rdata = self.request.recv(1024)
+                except TimeoutError:
+                    continue
+                except ConnectionResetError:
+                    break
+                if not rdata:
+                    # blocking socket reading nothing: client is disconnected
+                    break
+                self._buffer.extend(rdata)
+                while self._buffer:
+                    self._log.debug('buf: %d', len(self._buffer))
+                    pos = self._buffer.find(b'\n')
+                    self._log.debug('pos %d', pos)
+                    if pos < 0:
+                        break
+                    line = bytes(self._buffer[:pos+1])
+                    self._buffer[:] = self._buffer[pos+1:]
+                    self.server.push(self._id, line)
+        except Exception as exc:
+            if self.server.debug:
+                print(format_exc(chain=False), file=sys.stderr)
+            else:
+                self._log.critical('Error: %s', str(exc))
+            self.server.resume = False
+            raise
+
+
+class UartMuxer(ThreadingTCPServer):
+    """A simple UART muxer for multiple QEMU output streams
+    """
+
+    # do not wait for thread completion
+    daemon_threads = True
+    allow_reuse_address = True
+    timeout = None
+
+    COLOR_PREFIX = '\x1b['
+    COLOR_SUFFIX = ';1m'
+    RESET = '\x1b[0m'
+
+    def __init__(self, addr: tuple[str, int], out: TextIO, debug: bool = False,
+                 separator: Optional[str] = None):
+        super().__init__(addr, UartHandler)
+        self._out = out
+        self._debug = debug
+        self._log = getLogger('mux.muxer')
+        self._runner = Thread(target=self._pop, daemon=True)
+        self._resume = False
+        self._que: deque[tuple[int, bytes]] = deque()
+        self._evt = Event()
+        self._lock = Lock()
+        self._handlers: list[UartHandler] = []
+        self._discarded: set[UartHandler] = set()
+        self._channel_count = 1
+        self._channels: list[str] = []
+        self._use_color = out.isatty()
+        if separator:
+            sep = separator if ' ' in separator else (separator * 80)[:80]
+            self._sep = f'{sep}\n'
+        else:
+            self._sep = None
+
+    @property
+    def debug(self) -> bool:
+        """Tell whether mode is enabled."""
+        return self._debug
+
+    @property
+    def resume(self):
+        """Tell whether muxer should continue listening on."""
+        return self._resume
+
+    @resume.setter
+    def resume(self, value: bool):
+        value = bool(value)
+        if self._resume and not value:
+            self._resume = value
+            self._evt.set()
+            self.shutdown()
+        else:
+            self._resume = value
+
+    def run(self, channel_count: int, channels: list[str]) -> None:
+        """Start listening on QEMU streams."""
+        self._channel_count = min(channel_count, 8)
+        self._channels = channels
+        self._resume = True
+        self._runner.start()
+        try:
+            self.serve_forever()
+        finally:
+            if self._use_color:
+                self._out.write(self.RESET)
+
+    def push(self, uart_id: int, line: bytes) -> None:
+        """Push a new log message line from one of the QEMU stream listeners."""
+        self._que.append((uart_id, line))
+        self._evt.set()
+
+    def get_id(self, uart_handler: UartHandler) -> None:
+        """Get/assign a unique identifier to a listener."""
+        with self._lock:
+            if self._sep and not self._handlers:
+                self._out.write(self._sep)
+            if uart_handler not in self._handlers:
+                self._handlers.append(uart_handler)
+            return self._handlers.index(uart_handler)
+
+    def discard(self, uart_handler: UartHandler) -> None:
+        """Called when a listener terminates."""
+        with self._lock:
+            try:
+                self._discarded.add(uart_handler)
+            except ValueError:
+                pass
+            # track listeners; when all known ones are closed it is likely the
+            # QEMU VM has quit, reset the all listeners so on next QEMU run,
+            # same ids are assigned (which is likely to assign the same color
+            # for the same QEMU output stream, despite it is somewhat a
+            # heuristic)
+            if self._discarded == set(self._handlers):
+                self._discarded.clear()
+                self._handlers.clear()
+                self._log.debug('All clients flushed')
+
+    def _pop(self) -> None:
+        try:
+            while self._resume:
+                if not self._que:
+                    if not self._evt.wait(0.1):
+                        continue
+                    self._evt.clear()
+                if self._resume and self._que:
+                    uid, byteline = self._que.popleft()
+                    line = byteline.decode(errors='ignore')
+                    if uid < len(self._channels):
+                        name = f'{self._channels[uid]}: '
+                    else:
+                        name = ''
+                    if self._use_color:
+                        clr = uid % self._channel_count + 31
+                        ansi = f'{self.COLOR_PREFIX}{clr:d}{self.COLOR_SUFFIX}'
+                        # self._log.error('ANSI %s', ansi)
+                        self._out.write(f'{name}{ansi}{line}{self.RESET}')
+                        # raise ValueError()
+                    else:
+                        self._out.write(line)
+        finally:
+            self.resume = False
+
+
+def main():
+    """Main routine"""
+    debug = True
+    default_port = 9000
+    default_iface = 'localhost'
+    default_channel_count = 3
+    mux = None
+    try:
+        desc = sys.modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        argparser.add_argument('name', nargs='*',
+                               help='assign name to input connection')
+        argparser.add_argument('-i', '--iface', default=default_iface,
+                               help=f'specify TCP interface to listen to '
+                                    f'(default: {default_iface})')
+        argparser.add_argument('-p', '--port', default=default_port,
+                               help=f'specify TCP port to listen to '
+                                    f'(default: {default_port})')
+        argparser.add_argument('-c', '--channel',
+                               help=f'expected comm channel count'
+                                    f'(default: {default_channel_count})')
+        argparser.add_argument('-s', '--separator',
+                               help='repeat separator between each session')
+        argparser.add_argument('-v', '--verbose', action='count',
+                               help='increase verbosity')
+        argparser.add_argument('-d', '--debug', action='store_true',
+                               help='enable debug mode')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        configure_loggers(args.verbose, 'mux')
+
+        ThreadingTCPServer.allow_reuse_address = True
+        mux = UartMuxer((args.iface, args.port), sys.stdout, debug,
+                        args.separator)
+        channel = args.channel
+        if channel is None:
+            channel = len(args.name) if args.name else default_channel_count
+        mux.run(channel, args.name)
+
+    except (IOError, ValueError, ImportError) as exc:
+        print(f'\nError: {exc}', file=sys.stderr)
+        if debug:
+            print(format_exc(chain=False), file=sys.stderr)
+        sys.exit(1)
+    except KeyboardInterrupt:
+        if mux:
+            mux.resume = False
+        sys.exit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/opentitan/verilate.py b/scripts/opentitan/verilate.py
new file mode 100755
index 0000000000000..dce875db10714
--- /dev/null
+++ b/scripts/opentitan/verilate.py
@@ -0,0 +1,153 @@
+#!/usr/bin/env python3
+
+"""Verilator wrapper."""
+
+# Copyright (c) 2025 Rivos, Inc.
+# SPDX-License-Identifier: Apache2
+
+from os import getenv, sep, walk
+from os.path import (dirname, isdir, isfile, join as joinpath, normpath,
+                     realpath)
+from sys import exit as sysexit, modules, stderr
+from traceback import format_exc
+
+import sys
+
+QEMU_PYPATH = joinpath(dirname(dirname(dirname(normpath(__file__)))),
+                       'python', 'qemu')
+sys.path.append(QEMU_PYPATH)
+
+# pylint: disable=wrong-import-position
+# pylint: disable=wrong-import-order
+# pylint: disable=import-error
+
+from ot.util.arg import ArgumentParser  # noqa: E402
+from ot.util.log import configure_loggers  # noqa: E402
+from ot.verilator import DEFAULT_TIMEOUT  # noqa: E402
+from ot.verilator.filemgr import VtorFileManager  # noqa: E402
+from ot.verilator.executer import VtorExecuter  # noqa: E402
+
+
+def main():
+    """Main routine."""
+    debug = False
+    try:
+        desc = modules[__name__].__doc__.split('.', 1)[0].strip()
+        argparser = ArgumentParser(description=f'{desc}.')
+        files = argparser.add_argument_group(title='Files')
+        files.add_argument('app', nargs='*', metavar='ELF',
+                           help='application file, may be repeated')
+        files.add_argument('-V', '--verilator',
+                           help='Verilator executable')
+        files.add_argument('-R', '--rom', metavar='FILE', action='append',
+                           default=[],
+                           help='ROM file, may be repeated')
+        files.add_argument('-M', '--ram', metavar='FILE', action='append',
+                           default=[],
+                           help='RAM file, may be repeated')
+        files.add_argument('-F', '--flash', metavar='FILE', action='append',
+                           default=[],
+                           help='eFlash file, may be repeated')
+        files.add_argument('-O', '--otp', metavar='VMEM',
+                           help='OTP file')
+        files.add_argument('-K', '--keep-tmp', action='store_true',
+                           help='do not automatically remove temporary files '
+                                'and dirs on exit')
+        files.add_argument('-D', '--tmp-dir',
+                           help='store the temporary files in the specified '
+                                'directory')
+        files.add_argument('-c', '--config', metavar='CFG',
+                           help='input QEMU OT config file '
+                                '(required w/ non scrambled ROM images)')
+        veri = argparser.add_argument_group(title='Verilator')
+        veri.add_argument('-a', '--artifact-name', metavar='PREFIX',
+                          help='set an alternative artifact name '
+                               '(default is derived from the application name)')
+        veri.add_argument('-C', '--cycles', type=int,
+                          help='exit after the specified cycles')
+        veri.add_argument('-I', '--show-init', action='store_true',
+                          help='show initializable devices')
+        veri.add_argument('-k', '--timeout', metavar='SECONDS', type=float,
+                          help=f'exit after the specified seconds '
+                               f'(default: {DEFAULT_TIMEOUT} secs)')
+        veri.add_argument('-l', '--link-exec-log', action='store_true',
+                          help='create a symlink to the execution log file')
+        veri.add_argument('-P', '--profile', metavar='FILE',
+                          help='enable/manage profile file')
+        veri.add_argument('-w', '--wave-gen', action='store_true',
+                          help='generate output wave file')
+        veri.add_argument('-x', '--save-exec-log', action='store_true',
+                          help='save execution log')
+        extra = argparser.add_argument_group(title='Extras')
+        extra.add_argument('-v', '--verbose', action='count',
+                           help='increase verbosity')
+        extra.add_argument('-d', '--debug', action='store_true',
+                           help='enable debug mode')
+        extra.add_argument('-G', '--log-time', action='store_true',
+                           help='show local time in log messages')
+        args = argparser.parse_args()
+        debug = args.debug
+
+        log = configure_loggers(args.verbose, 'vtor', -1, 'elf', -1, 'romimg',
+                                name_width=12, ms=args.log_time)[0]
+
+        if args.tmp_dir and not isdir(args.tmp_dir):
+            argparser.error('Invalid directory for temporary files')
+
+        verilator = args.verilator or getenv('VERILATOR')
+        if not verilator:
+            argparser.error('Verilator tool not specified')
+        if not isfile(verilator) and isdir(verilator):
+            top_dir = realpath(verilator)
+            for dirpath, _, files in walk(top_dir):
+                if 'Vchip_sim_tb' in files:
+                    verilator = realpath(joinpath(dirpath, 'Vchip_sim_tb'))
+                    if isfile(verilator):
+                        short_veri = verilator.removeprefix(f'{top_dir}{sep}')
+                        log.debug('Found Verilator tool as %s', short_veri)
+                        break
+        if not isfile(verilator):
+            argparser.error('Verilator tool not found')
+
+        vfm = VtorFileManager(args.keep_tmp, args.tmp_dir)
+        vtor = VtorExecuter(vfm, verilator, args.profile, debug)
+
+        if args.show_init:
+            vtor.show_init_devices()
+            sysexit(0)
+
+        if args.config:
+            vtor.secret_file = args.config
+
+        filenames = list(args.rom)  # need a copy of the list
+        filenames.append(args.otp)
+        filenames.extend(args.ram)
+        filenames.extend(args.flash)
+        if args.app:
+            filenames.extend(args.app)
+        for filename in filenames:
+            if filename and not isfile(filename):
+                argparser.error(f'No such file: {filename}')
+
+        if args.artifact_name:
+            if not isdir(realpath(dirname(args.artifact_name))):
+                argparser.error('Invalid directory for execution log file')
+            vtor.artifact_name = args.artifact_name
+        vtor.enable_exec_log(args.save_exec_log, args.link_exec_log)
+        vtor.generate_wave(args.wave_gen)
+        ret = vtor.verilate(args.rom, args.ram, args.flash, args.app, args.otp,
+                            timeout=args.timeout, cycles=args.cycles)
+
+        sysexit(ret)
+    # pylint: disable-msg=broad-except
+    except Exception as exc:
+        print(f'\nError: {exc}', file=stderr)
+        if debug:
+            print(format_exc(chain=False), file=stderr)
+        sysexit(1)
+    except KeyboardInterrupt:
+        sysexit(2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/tracetool/__init__.py b/scripts/tracetool/__init__.py
index 74062d21a7ced..330a627308f03 100644
--- a/scripts/tracetool/__init__.py
+++ b/scripts/tracetool/__init__.py
@@ -261,8 +261,10 @@ def build(arg_str):
                 arg_type += '*'
                 identifier = identifier.strip()
             else:
-                arg_type, identifier = arg.rsplit(None, 1)
-
+                try:
+                    arg_type, identifier = arg.rsplit(None, 1)
+                except ValueError as exc:
+                    raise ValueError(f'Malformed argument: {arg}') from exc
             validate_type(arg_type)
             res.append((arg_type, identifier))
         return Arguments(res)
diff --git a/subprojects/bitflags.wrap b/subprojects/bitflags.wrap
new file mode 100644
index 0000000000000..35239f84419b4
--- /dev/null
+++ b/subprojects/bitflags.wrap
@@ -0,0 +1,8 @@
+[wrap-file]
+directory = bitflags-1.3.2
+
+source_url = https://github.com/bitflags/bitflags/archive/refs/tags/1.3.2.tar.gz
+source_filename = bitflags-1.3.2.tar.gz
+source_hash = 52ab9ccde868e856b38d4033a6bca0340422cb6460fd587fb26bf46659eb6e34
+
+diff_files = bitflags/0001.patch
diff --git a/subprojects/ethnum-rs.wrap b/subprojects/ethnum-rs.wrap
new file mode 100644
index 0000000000000..ab7346cd44acb
--- /dev/null
+++ b/subprojects/ethnum-rs.wrap
@@ -0,0 +1,7 @@
+[wrap-file]
+directory = ethnum-rs-1.3.0
+source_url = https://github.com/nlordell/ethnum-rs/archive/refs/tags/v1.3.0.tar.gz
+source_filename = ethnum-rs-1.3.0.tar.gz
+source_hash = 65d2f954d998565cfdd5ac107862e13c9ac2ed62cc68c454c5690c0982b9e02a
+
+diff_files = ethnum-rs/0001.patch
diff --git a/subprojects/libtomcrypt.wrap b/subprojects/libtomcrypt.wrap
new file mode 100644
index 0000000000000..339de7e5dc359
--- /dev/null
+++ b/subprojects/libtomcrypt.wrap
@@ -0,0 +1,8 @@
+[wrap-git]
+url=https://github.com/libtom/libtomcrypt.git
+revision=v1.18.2
+depth=1
+diff_files = libtomcrypt/0001.patch, libtomcrypt/0002.patch, libtomcrypt/0003.patch
+
+[provide]
+dependency_names = libtomcrypt
diff --git a/subprojects/packagefiles/bitflags/0001.patch b/subprojects/packagefiles/bitflags/0001.patch
new file mode 100644
index 0000000000000..f8c337d059f05
--- /dev/null
+++ b/subprojects/packagefiles/bitflags/0001.patch
@@ -0,0 +1,13 @@
+diff --git a/meson.build b/meson.build
+new file mode 100644
+index 0000000000..792c240684
+--- /dev/null
++++ b/meson.build
+@@ -0,0 +1,7 @@
++project('bitflags', 'rust', version: '1.3.2')
++
++bitflags_lib = static_library('bitflags',
++                              'src/lib.rs',
++                              install: true)
++
++bitflags_dep = declare_dependency(link_with: bitflags_lib)
diff --git a/subprojects/packagefiles/ethnum-rs/0001.patch b/subprojects/packagefiles/ethnum-rs/0001.patch
new file mode 100644
index 0000000000000..286ba307cb2f4
--- /dev/null
+++ b/subprojects/packagefiles/ethnum-rs/0001.patch
@@ -0,0 +1,14 @@
+diff --git a/meson.build b/meson.build
+new file mode 100644
+index 0000000000..1f7c0456e8
+--- /dev/null
++++ b/meson.build
+@@ -0,0 +1,8 @@
++project('ethnum', 'rust', version: '1.3.2')
++
++ethnum_lib = static_library('ethnum',
++                            'src/lib.rs',
++                            override_options: ['rust_std=2021'],
++                            install: true)
++
++ethnum_dep = declare_dependency(link_with: ethnum_lib)
diff --git a/subprojects/packagefiles/libtomcrypt/0001.patch b/subprojects/packagefiles/libtomcrypt/0001.patch
new file mode 100644
index 0000000000000..aa0e8f0bf56e5
--- /dev/null
+++ b/subprojects/packagefiles/libtomcrypt/0001.patch
@@ -0,0 +1,129 @@
+diff --git a/src/headers/tomcrypt_custom.h b/src/headers/tomcrypt_custom.h
+index 2d5cfec..a9b3a78 100644
+--- a/src/headers/tomcrypt_custom.h
++++ b/src/headers/tomcrypt_custom.h
+@@ -10,6 +10,10 @@
+ #ifndef TOMCRYPT_CUSTOM_H_
+ #define TOMCRYPT_CUSTOM_H_
+ 
++#define LTC_NO_TEST
++#define LTC_EASY
++#define LTC_NO_PROTOTYPES
++
+ /* macros for various libc functions you can change for embedded targets */
+ #ifndef XMALLOC
+ #define XMALLOC  malloc
+@@ -45,6 +49,12 @@
+ #ifndef XSTRCMP
+ #define XSTRCMP strcmp
+ #endif
++#ifndef XSTRLEN
++#define XSTRLEN  strlen
++#endif
++#ifndef XSTRNCPY
++#define XSTRNCPY strncpy
++#endif
+ 
+ #ifndef XCLOCK
+ #define XCLOCK   clock
+@@ -76,63 +86,65 @@
+ #ifdef LTC_EASY
+    #define LTC_NO_CIPHERS
+    #define LTC_RIJNDAEL
+-   #define LTC_BLOWFISH
+-   #define LTC_DES
+-   #define LTC_CAST5
++   #undef  LTC_BLOWFISH
++   #undef  LTC_DES
++   #undef  LTC_CAST5
+ 
+-   #define LTC_NO_MODES
++   #undef  LTC_NO_MODES
+    #define LTC_ECB_MODE
+    #define LTC_CBC_MODE
+    #define LTC_CTR_MODE
+ 
+    #define LTC_NO_HASHES
+-   #define LTC_SHA1
++   #undef  LTC_SHA1
+    #define LTC_SHA3
+    #define LTC_SHA512
+    #define LTC_SHA384
+    #define LTC_SHA256
+-   #define LTC_SHA224
+-   #define LTC_HASH_HELPERS
++   #undef  LTC_SHA224
++   #undef  LTC_HASH_HELPERS
+ 
+    #define LTC_NO_MACS
+-   #define LTC_HMAC
+-   #define LTC_OMAC
++   #undef  LTC_HMAC
++   #undef  LTC_OMAC
+    #define LTC_CCM_MODE
++   #define LTC_GCM_MODE
+ 
+    #define LTC_NO_PRNGS
+-   #define LTC_SPRNG
+-   #define LTC_YARROW
+-   #define LTC_DEVRANDOM
+-   #define LTC_TRY_URANDOM_FIRST
+-   #define LTC_RNG_GET_BYTES
+-   #define LTC_RNG_MAKE_PRNG
++   #undef  LTC_SPRNG
++   #undef  LTC_YARROW
++   #undef  LTC_DEVRANDOM
++   #undef  LTC_TRY_URANDOM_FIRST
++   #undef  LTC_RNG_GET_BYTES
++   #undef  LTC_RNG_MAKE_PRNG
+ 
+    #define LTC_NO_PK
+-   #define LTC_MRSA
+-   #define LTC_MECC
++   #define LTC_NO_PKCS
++   #undef LTC_MRSA
++   #undef LTC_MECC
+ 
+    #define LTC_NO_MISC
+-   #define LTC_BASE64
++   #undef  LTC_BASE64
+ #endif
+ 
+ /* The minimal set of functionality to run the tests */
+ #ifdef LTC_MINIMAL
+    #define LTC_RIJNDAEL
+-   #define LTC_SHA256
+-   #define LTC_YARROW
+-   #define LTC_CTR_MODE
++   #undef LTC_SHA256
++   #undef LTC_YARROW
++   #undef LTC_CTR_MODE
+ 
+-   #define LTC_RNG_MAKE_PRNG
+-   #define LTC_RNG_GET_BYTES
+-   #define LTC_DEVRANDOM
+-   #define LTC_TRY_URANDOM_FIRST
++   #undef LTC_RNG_MAKE_PRNG
++   #undef LTC_RNG_GET_BYTES
++   #undef LTC_DEVRANDOM
++   #undef LTC_TRY_URANDOM_FIRST
+ 
+    #undef LTC_NO_FILE
+ #endif
+ 
+ /* Enable self-test test vector checking */
+ #ifndef LTC_NO_TEST
+-   #define LTC_TEST
++   #undef LTC_TEST
+ #endif
+ /* Enable extended self-tests */
+ /* #define LTC_TEST_EXT */
+@@ -392,7 +404,7 @@
+ /* #define LTC_MKAT */
+ 
+ /* Digital Signature Algorithm */
+-#define LTC_MDSA
++#undef LTC_MDSA
+ 
+ /* ECC */
+ #define LTC_MECC
diff --git a/subprojects/packagefiles/libtomcrypt/0002.patch b/subprojects/packagefiles/libtomcrypt/0002.patch
new file mode 100644
index 0000000000000..9bc60ea0798b4
--- /dev/null
+++ b/subprojects/packagefiles/libtomcrypt/0002.patch
@@ -0,0 +1,73 @@
+diff --git a/meson.build b/meson.build
+new file mode 100644
+index 0000000..cdef610
+--- /dev/null
++++ b/meson.build
+@@ -0,0 +1,67 @@
++project('libtomcrypt', 'c')
++
++libtomcrypt = static_library('tomcrypt',
++                             files('src/ciphers/aes/aes.c',
++                                   'src/ciphers/aes/aes_tab.c',
++                                   'src/encauth/ccm/ccm_add_aad.c',
++                                   'src/encauth/ccm/ccm_add_nonce.c',
++                                   'src/encauth/ccm/ccm_done.c',
++                                   'src/encauth/ccm/ccm_init.c',
++                                   'src/encauth/ccm/ccm_memory.c',
++                                   'src/encauth/ccm/ccm_process.c',
++                                   'src/encauth/ccm/ccm_reset.c',
++                                   'src/encauth/ccm/ccm_test.c',
++                                   'src/encauth/gcm/gcm_add_aad.c',
++                                   'src/encauth/gcm/gcm_add_iv.c',
++                                   'src/encauth/gcm/gcm_done.c',
++                                   'src/encauth/gcm/gcm_gf_mult.c',
++                                   'src/encauth/gcm/gcm_init.c',
++                                   'src/encauth/gcm/gcm_memory.c',
++                                   'src/encauth/gcm/gcm_mult_h.c',
++                                   'src/encauth/gcm/gcm_process.c',
++                                   'src/encauth/gcm/gcm_reset.c',
++                                   'src/encauth/gcm/gcm_test.c',
++                                   'src/hashes/sha2/sha256.c',
++                                   'src/hashes/sha2/sha384.c',
++                                   'src/hashes/sha2/sha512.c',
++                                   'src/hashes/sha3.c',
++                                   'src/hashes/sha3_test.c',
++                                   'src/misc/crypt/crypt_argchk.c',
++                                   'src/misc/crypt/crypt_cipher_descriptor.c',
++                                   'src/misc/crypt/crypt_cipher_is_valid.c',
++                                   'src/misc/crypt/crypt_register_cipher.c',
++                                   'src/misc/mem_neq.c',
++                                   'src/misc/zeromem.c',
++                                   'src/modes/cbc/cbc_decrypt.c',
++                                   'src/modes/cbc/cbc_done.c',
++                                   'src/modes/cbc/cbc_encrypt.c',
++                                   'src/modes/cbc/cbc_getiv.c',
++                                   'src/modes/cbc/cbc_setiv.c',
++                                   'src/modes/cbc/cbc_start.c',
++                                   'src/modes/cfb/cfb_decrypt.c',
++                                   'src/modes/cfb/cfb_done.c',
++                                   'src/modes/cfb/cfb_encrypt.c',
++                                   'src/modes/cfb/cfb_getiv.c',
++                                   'src/modes/cfb/cfb_setiv.c',
++                                   'src/modes/cfb/cfb_start.c',
++                                   'src/modes/ctr/ctr_decrypt.c',
++                                   'src/modes/ctr/ctr_done.c',
++                                   'src/modes/ctr/ctr_encrypt.c',
++                                   'src/modes/ctr/ctr_getiv.c',
++                                   'src/modes/ctr/ctr_setiv.c',
++                                   'src/modes/ctr/ctr_start.c',
++                                   'src/modes/ctr/ctr_test.c',
++                                   'src/modes/ecb/ecb_decrypt.c',
++                                   'src/modes/ecb/ecb_done.c',
++                                   'src/modes/ecb/ecb_encrypt.c',
++                                   'src/modes/ecb/ecb_start.c',
++                                   'src/modes/ofb/ofb_decrypt.c',
++                                   'src/modes/ofb/ofb_done.c',
++                                   'src/modes/ofb/ofb_encrypt.c',
++                                   'src/modes/ofb/ofb_getiv.c',
++                                   'src/modes/ofb/ofb_setiv.c',
++                                   'src/modes/ofb/ofb_start.c'),
++                                include_directories: ['src/headers'])
++
++libtomcrypt_dep = declare_dependency(link_with: libtomcrypt,
++                                     include_directories: include_directories('src/headers'))
diff --git a/subprojects/packagefiles/libtomcrypt/0003.patch b/subprojects/packagefiles/libtomcrypt/0003.patch
new file mode 100644
index 0000000000000..a39fc8efc8527
--- /dev/null
+++ b/subprojects/packagefiles/libtomcrypt/0003.patch
@@ -0,0 +1,141 @@
+diff --git a/src/hashes/sha3.c b/src/hashes/sha3.c
+index c6faa0b..d596bd0 100644
+--- a/src/hashes/sha3.c
++++ b/src/hashes/sha3.c
+@@ -174,6 +174,102 @@ int sha3_shake_init(hash_state *md, int num)
+    if (num != 128 && num != 256) return CRYPT_INVALID_ARG;
+    XMEMSET(&md->sha3, 0, sizeof(md->sha3));
+    md->sha3.capacity_words = (unsigned short)(2 * num / (8 * sizeof(ulong64)));
++   md->sha3.suffix = 0x1F;
++   return CRYPT_OK;
++}
++
++static unsigned long cshake_left_encode(unsigned long num, unsigned char *buf)
++{
++   unsigned int n, i;
++   size_t v;
++
++   for (v = num, n = 0; v && (n < sizeof(unsigned long)); n++, v >>= 8) {
++       /* empty */
++   }
++   if (n == 0)
++      n = 1;
++
++   for (i = 1; i <= n; i++)
++   {
++      buf[i] = (unsigned char)(num >> (8 * (n - i)));
++   }
++   buf[0] = (unsigned char)n;
++
++   return n + 1;
++}
++
++static unsigned long cshake_left_encode_and_process_str(hash_state *md,
++        const unsigned char *data, unsigned long datalen)
++{
++   unsigned char buf[sizeof(unsigned long) + 1];
++   unsigned long len = 0;
++
++   len = cshake_left_encode(datalen * 8, buf);
++   sha3_process(md, buf, len);
++   if (datalen)
++      sha3_process(md, data, datalen);
++   len += datalen;
++
++   return len;
++}
++
++int sha3_cshake_init(hash_state *md, int num,
++        const unsigned char *func, unsigned long funclen,
++        const unsigned char *custom, unsigned long customlen)
++{
++   unsigned char buf[168];
++   unsigned long len, total = 0;
++   unsigned long rate;
++   LTC_ARGCHK(md != NULL);
++   if (num != 128 && num != 256) return CRYPT_INVALID_ARG;
++   rate = (num == 128) ? 168 : 136;
++   XMEMSET(&md->sha3, 0, sizeof(md->sha3));
++   md->sha3.capacity_words = (unsigned short)(2 * num / (8 * sizeof(ulong64)));
++
++   if (funclen == 0 && customlen == 0) {
++      /* no function, no customization => regular SHAKE */
++      md->sha3.suffix = 0x1F;
++   } else {
++      md->sha3.suffix = 0x04;
++
++      /* start bytepad */
++      len = cshake_left_encode(rate, buf);
++      sha3_process(md, buf, len);
++      total += len;
++
++      /* process function name */
++      total += cshake_left_encode_and_process_str(md, func, funclen);
++
++      /* process customization string */
++      total += cshake_left_encode_and_process_str(md, custom, customlen);
++
++      /* finish bytepad */
++      XMEMSET(buf, 0, sizeof(buf));
++      sha3_process(md, buf, rate - (total % rate));
++   }
++   return CRYPT_OK;
++}
++
++int sha3_process_kmac_key(hash_state * md, const unsigned char *key, unsigned long keylen)
++{
++   unsigned char buf[168];
++   unsigned long len, total = 0;
++   unsigned long rate;
++
++   rate = (md->sha3.capacity_words == 4) ? 168 : 136;
++
++   /* start bytepad */
++   len = cshake_left_encode(rate, buf);
++   sha3_process(md, buf, len);
++   total += len;
++
++   /* process key */
++   total += cshake_left_encode_and_process_str(md, key, keylen);
++
++   /* finish bytepad */
++   XMEMSET(buf, 0, sizeof(buf));
++   sha3_process(md, buf, rate - (total % rate));
++
+    return CRYPT_OK;
+ }
+ 
+@@ -261,7 +357,7 @@ int sha3_shake_done(hash_state *md, unsigned char *out, unsigned long outlen)
+ 
+    if (!md->sha3.xof_flag) {
+       /* shake_xof operation must be done only once */
+-      md->sha3.s[md->sha3.word_index] ^= (md->sha3.saved ^ (CONST64(0x1F) << (md->sha3.byte_index * 8)));
++      md->sha3.s[md->sha3.word_index] ^= (md->sha3.saved ^ ((ulong64)md->sha3.suffix << (md->sha3.byte_index * 8)));
+       md->sha3.s[SHA3_KECCAK_SPONGE_WORDS - md->sha3.capacity_words - 1] ^= CONST64(0x8000000000000000);
+       keccakf(md->sha3.s);
+       /* store sha3.s[] as little-endian bytes into sha3.sb */
+diff --git a/src/headers/tomcrypt_hash.h b/src/headers/tomcrypt_hash.h
+index ef494f7..b0565d8 100644
+--- a/src/headers/tomcrypt_hash.h
++++ b/src/headers/tomcrypt_hash.h
+@@ -17,6 +17,7 @@ struct sha3_state {
+     unsigned short word_index;      /* 0..24--the next word to integrate input (starts from 0) */
+     unsigned short capacity_words;  /* the double size of the hash output in words (e.g. 16 for Keccak 512) */
+     unsigned short xof_flag;
++    unsigned char suffix;           /* suffix for SHAKE/cSHAKE */
+ };
+ #endif
+ 
+@@ -285,6 +286,12 @@ int sha3_shake_init(hash_state *md, int num);
+ int sha3_shake_done(hash_state *md, unsigned char *out, unsigned long outlen);
+ int sha3_shake_test(void);
+ int sha3_shake_memory(int num, const unsigned char *in, unsigned long inlen, unsigned char *out, unsigned long *outlen);
++int sha3_cshake_init(hash_state *md, int num,
++        const unsigned char *func, unsigned long funclen,
++        const unsigned char *custom, unsigned long customlen);
++#define sha3_cshake_process(a,b,c) sha3_process(a,b,c)
++#define sha3_cshake_done(a,b,c) sha3_shake_done(a,b,c)
++int sha3_process_kmac_key(hash_state * md, const unsigned char *key, unsigned long keylen);
+ #endif
+ 
+ #ifdef LTC_SHA512
diff --git a/subprojects/packagefiles/paste/0001.patch b/subprojects/packagefiles/paste/0001.patch
new file mode 100644
index 0000000000000..e4145f5c9d306
--- /dev/null
+++ b/subprojects/packagefiles/paste/0001.patch
@@ -0,0 +1,13 @@
+diff --git a/meson.build b/meson.build
+new file mode 100644
+index 0000000000..f6c6338b22
+--- /dev/null
++++ b/meson.build
+@@ -0,0 +1,7 @@
++project('paste', 'rust', version: '1.0.49')
++
++paste_lib = shared_library('paste',
++                           'src/lib.rs',
++                            rust_crate_type: 'proc-macro')
++
++paste_dep = declare_dependency(link_with: paste_lib)
diff --git a/subprojects/paste.wrap b/subprojects/paste.wrap
new file mode 100644
index 0000000000000..48f228a52c846
--- /dev/null
+++ b/subprojects/paste.wrap
@@ -0,0 +1,8 @@
+[wrap-file]
+directory = paste-1.0.9
+
+source_url = https://github.com/dtolnay/paste/archive/refs/tags/1.0.9.tar.gz
+source_filename = paste-1.0.9.tar.gz
+source_hash = 37e94fb1b322b938159cf84361a479484d4eed1cec5346eaa0b9d3fe4be5fb8f
+
+diff_files = paste/0001.patch
diff --git a/system/cpus.c b/system/cpus.c
index ef2d2f241faaa..b574a03d135e0 100644
--- a/system/cpus.c
+++ b/system/cpus.c
@@ -330,7 +330,7 @@ int vm_shutdown(void)
 
 bool cpu_can_run(CPUState *cpu)
 {
-    if (cpu->stop) {
+    if (cpu->stop || unlikely(cpu->disabled)) {
         return false;
     }
     if (cpu_is_stopped(cpu)) {
@@ -353,9 +353,12 @@ void cpu_handle_guest_debug(CPUState *cpu)
             cpu_single_step(cpu, 0);
         }
     } else {
-        gdb_set_stop_cpu(cpu);
-        qemu_system_debug_request();
-        cpu->stopped = true;
+        CPUClass *cc = CPU_GET_CLASS(cpu);
+        if (!cc->debug_request || !cc->debug_request(cpu)) {
+            gdb_set_stop_cpu(cpu);
+            qemu_system_debug_request();
+            cpu->stopped = true;
+        }
     }
 }
 
@@ -916,4 +919,3 @@ void qmp_inject_nmi(Error **errp)
 {
     nmi_monitor_handle(monitor_get_cpu_index(monitor_cur()), errp);
 }
-
diff --git a/system/vl.c b/system/vl.c
index 5091fe52d9253..98a5ca34329ff 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -513,6 +513,15 @@ static QemuOptsList qemu_action_opts = {
     },
 };
 
+static QemuOptsList qemu_ot_device_opts = {
+    .name = "ot_device",
+    .implied_opt_name = "ot_id",
+    .head = QTAILQ_HEAD_INITIALIZER(qemu_ot_device_opts.head),
+    .desc = {
+         { /* end of list */ }
+    },
+};
+
 const char *qemu_get_vm_name(void)
 {
     return qemu_name;
@@ -2882,6 +2891,7 @@ void qemu_init(int argc, char **argv)
     qemu_add_opts(&qemu_semihosting_config_opts);
     qemu_add_opts(&qemu_fw_cfg_opts);
     qemu_add_opts(&qemu_action_opts);
+    qemu_add_opts(&qemu_ot_device_opts);
     qemu_add_run_with_opts();
     module_call_init(MODULE_INIT_OPTS);
 
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index e9c8d7f77803c..52ac2dad21aae 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -129,3 +129,141 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
 {
     return do_xperm(rs1, rs2, 3);
 }
+
+/*
+ * this table is already defined in hw/pc/pcnet.c, as well as likely implemented
+ * in zlib. It would make sense to move pcnet implementation into util/ as the
+ * latter already embeds crc32c table - and stop refering to zlib.h for CRC32
+ */
+static uint32_t zbr_crc32_table[256u] = {
+    0x00000000u, 0x77073096u, 0xee0e612cu, 0x990951bau, 0x076dc419u,
+    0x706af48fu, 0xe963a535u, 0x9e6495a3u, 0x0edb8832u, 0x79dcb8a4u,
+    0xe0d5e91eu, 0x97d2d988u, 0x09b64c2bu, 0x7eb17cbdu, 0xe7b82d07u,
+    0x90bf1d91u, 0x1db71064u, 0x6ab020f2u, 0xf3b97148u, 0x84be41deu,
+    0x1adad47du, 0x6ddde4ebu, 0xf4d4b551u, 0x83d385c7u, 0x136c9856u,
+    0x646ba8c0u, 0xfd62f97au, 0x8a65c9ecu, 0x14015c4fu, 0x63066cd9u,
+    0xfa0f3d63u, 0x8d080df5u, 0x3b6e20c8u, 0x4c69105eu, 0xd56041e4u,
+    0xa2677172u, 0x3c03e4d1u, 0x4b04d447u, 0xd20d85fdu, 0xa50ab56bu,
+    0x35b5a8fau, 0x42b2986cu, 0xdbbbc9d6u, 0xacbcf940u, 0x32d86ce3u,
+    0x45df5c75u, 0xdcd60dcfu, 0xabd13d59u, 0x26d930acu, 0x51de003au,
+    0xc8d75180u, 0xbfd06116u, 0x21b4f4b5u, 0x56b3c423u, 0xcfba9599u,
+    0xb8bda50fu, 0x2802b89eu, 0x5f058808u, 0xc60cd9b2u, 0xb10be924u,
+    0x2f6f7c87u, 0x58684c11u, 0xc1611dabu, 0xb6662d3du, 0x76dc4190u,
+    0x01db7106u, 0x98d220bcu, 0xefd5102au, 0x71b18589u, 0x06b6b51fu,
+    0x9fbfe4a5u, 0xe8b8d433u, 0x7807c9a2u, 0x0f00f934u, 0x9609a88eu,
+    0xe10e9818u, 0x7f6a0dbbu, 0x086d3d2du, 0x91646c97u, 0xe6635c01u,
+    0x6b6b51f4u, 0x1c6c6162u, 0x856530d8u, 0xf262004eu, 0x6c0695edu,
+    0x1b01a57bu, 0x8208f4c1u, 0xf50fc457u, 0x65b0d9c6u, 0x12b7e950u,
+    0x8bbeb8eau, 0xfcb9887cu, 0x62dd1ddfu, 0x15da2d49u, 0x8cd37cf3u,
+    0xfbd44c65u, 0x4db26158u, 0x3ab551ceu, 0xa3bc0074u, 0xd4bb30e2u,
+    0x4adfa541u, 0x3dd895d7u, 0xa4d1c46du, 0xd3d6f4fbu, 0x4369e96au,
+    0x346ed9fcu, 0xad678846u, 0xda60b8d0u, 0x44042d73u, 0x33031de5u,
+    0xaa0a4c5fu, 0xdd0d7cc9u, 0x5005713cu, 0x270241aau, 0xbe0b1010u,
+    0xc90c2086u, 0x5768b525u, 0x206f85b3u, 0xb966d409u, 0xce61e49fu,
+    0x5edef90eu, 0x29d9c998u, 0xb0d09822u, 0xc7d7a8b4u, 0x59b33d17u,
+    0x2eb40d81u, 0xb7bd5c3bu, 0xc0ba6cadu, 0xedb88320u, 0x9abfb3b6u,
+    0x03b6e20cu, 0x74b1d29au, 0xead54739u, 0x9dd277afu, 0x04db2615u,
+    0x73dc1683u, 0xe3630b12u, 0x94643b84u, 0x0d6d6a3eu, 0x7a6a5aa8u,
+    0xe40ecf0bu, 0x9309ff9du, 0x0a00ae27u, 0x7d079eb1u, 0xf00f9344u,
+    0x8708a3d2u, 0x1e01f268u, 0x6906c2feu, 0xf762575du, 0x806567cbu,
+    0x196c3671u, 0x6e6b06e7u, 0xfed41b76u, 0x89d32be0u, 0x10da7a5au,
+    0x67dd4accu, 0xf9b9df6fu, 0x8ebeeff9u, 0x17b7be43u, 0x60b08ed5u,
+    0xd6d6a3e8u, 0xa1d1937eu, 0x38d8c2c4u, 0x4fdff252u, 0xd1bb67f1u,
+    0xa6bc5767u, 0x3fb506ddu, 0x48b2364bu, 0xd80d2bdau, 0xaf0a1b4cu,
+    0x36034af6u, 0x41047a60u, 0xdf60efc3u, 0xa867df55u, 0x316e8eefu,
+    0x4669be79u, 0xcb61b38cu, 0xbc66831au, 0x256fd2a0u, 0x5268e236u,
+    0xcc0c7795u, 0xbb0b4703u, 0x220216b9u, 0x5505262fu, 0xc5ba3bbeu,
+    0xb2bd0b28u, 0x2bb45a92u, 0x5cb36a04u, 0xc2d7ffa7u, 0xb5d0cf31u,
+    0x2cd99e8bu, 0x5bdeae1du, 0x9b64c2b0u, 0xec63f226u, 0x756aa39cu,
+    0x026d930au, 0x9c0906a9u, 0xeb0e363fu, 0x72076785u, 0x05005713u,
+    0x95bf4a82u, 0xe2b87a14u, 0x7bb12baeu, 0x0cb61b38u, 0x92d28e9bu,
+    0xe5d5be0du, 0x7cdcefb7u, 0x0bdbdf21u, 0x86d3d2d4u, 0xf1d4e242u,
+    0x68ddb3f8u, 0x1fda836eu, 0x81be16cdu, 0xf6b9265bu, 0x6fb077e1u,
+    0x18b74777u, 0x88085ae6u, 0xff0f6a70u, 0x66063bcau, 0x11010b5cu,
+    0x8f659effu, 0xf862ae69u, 0x616bffd3u, 0x166ccf45u, 0xa00ae278u,
+    0xd70dd2eeu, 0x4e048354u, 0x3903b3c2u, 0xa7672661u, 0xd06016f7u,
+    0x4969474du, 0x3e6e77dbu, 0xaed16a4au, 0xd9d65adcu, 0x40df0b66u,
+    0x37d83bf0u, 0xa9bcae53u, 0xdebb9ec5u, 0x47b2cf7fu, 0x30b5ffe9u,
+    0xbdbdf21cu, 0xcabac28au, 0x53b39330u, 0x24b4a3a6u, 0xbad03605u,
+    0xcdd70693u, 0x54de5729u, 0x23d967bfu, 0xb3667a2eu, 0xc4614ab8u,
+    0x5d681b02u, 0x2a6f2b94u, 0xb40bbe37u, 0xc30c8ea1u, 0x5a05df1bu,
+    0x2d02ef8du
+};
+
+/*
+ * this table is already defined in util/crc32c.c, but the latter does not
+ * export a direct access function. See also comment in the previous table, it
+ * would make sense to group all CRC32* implementations into util/ directory.
+ */
+static uint32_t zbr_crc32c_table[256u] = {
+    0x00000000u, 0xf26b8303u, 0xe13b70f7u, 0x1350f3f4u, 0xc79a971fu,
+    0x35f1141cu, 0x26a1e7e8u, 0xd4ca64ebu, 0x8ad958cfu, 0x78b2dbccu,
+    0x6be22838u, 0x9989ab3bu, 0x4d43cfd0u, 0xbf284cd3u, 0xac78bf27u,
+    0x5e133c24u, 0x105ec76fu, 0xe235446cu, 0xf165b798u, 0x030e349bu,
+    0xd7c45070u, 0x25afd373u, 0x36ff2087u, 0xc494a384u, 0x9a879fa0u,
+    0x68ec1ca3u, 0x7bbcef57u, 0x89d76c54u, 0x5d1d08bfu, 0xaf768bbcu,
+    0xbc267848u, 0x4e4dfb4bu, 0x20bd8edeu, 0xd2d60dddu, 0xc186fe29u,
+    0x33ed7d2au, 0xe72719c1u, 0x154c9ac2u, 0x061c6936u, 0xf477ea35u,
+    0xaa64d611u, 0x580f5512u, 0x4b5fa6e6u, 0xb93425e5u, 0x6dfe410eu,
+    0x9f95c20du, 0x8cc531f9u, 0x7eaeb2fau, 0x30e349b1u, 0xc288cab2u,
+    0xd1d83946u, 0x23b3ba45u, 0xf779deaeu, 0x05125dadu, 0x1642ae59u,
+    0xe4292d5au, 0xba3a117eu, 0x4851927du, 0x5b016189u, 0xa96ae28au,
+    0x7da08661u, 0x8fcb0562u, 0x9c9bf696u, 0x6ef07595u, 0x417b1dbcu,
+    0xb3109ebfu, 0xa0406d4bu, 0x522bee48u, 0x86e18aa3u, 0x748a09a0u,
+    0x67dafa54u, 0x95b17957u, 0xcba24573u, 0x39c9c670u, 0x2a993584u,
+    0xd8f2b687u, 0x0c38d26cu, 0xfe53516fu, 0xed03a29bu, 0x1f682198u,
+    0x5125dad3u, 0xa34e59d0u, 0xb01eaa24u, 0x42752927u, 0x96bf4dccu,
+    0x64d4cecfu, 0x77843d3bu, 0x85efbe38u, 0xdbfc821cu, 0x2997011fu,
+    0x3ac7f2ebu, 0xc8ac71e8u, 0x1c661503u, 0xee0d9600u, 0xfd5d65f4u,
+    0x0f36e6f7u, 0x61c69362u, 0x93ad1061u, 0x80fde395u, 0x72966096u,
+    0xa65c047du, 0x5437877eu, 0x4767748au, 0xb50cf789u, 0xeb1fcbadu,
+    0x197448aeu, 0x0a24bb5au, 0xf84f3859u, 0x2c855cb2u, 0xdeeedfb1u,
+    0xcdbe2c45u, 0x3fd5af46u, 0x7198540du, 0x83f3d70eu, 0x90a324fau,
+    0x62c8a7f9u, 0xb602c312u, 0x44694011u, 0x5739b3e5u, 0xa55230e6u,
+    0xfb410cc2u, 0x092a8fc1u, 0x1a7a7c35u, 0xe811ff36u, 0x3cdb9bddu,
+    0xceb018deu, 0xdde0eb2au, 0x2f8b6829u, 0x82f63b78u, 0x709db87bu,
+    0x63cd4b8fu, 0x91a6c88cu, 0x456cac67u, 0xb7072f64u, 0xa457dc90u,
+    0x563c5f93u, 0x082f63b7u, 0xfa44e0b4u, 0xe9141340u, 0x1b7f9043u,
+    0xcfb5f4a8u, 0x3dde77abu, 0x2e8e845fu, 0xdce5075cu, 0x92a8fc17u,
+    0x60c37f14u, 0x73938ce0u, 0x81f80fe3u, 0x55326b08u, 0xa759e80bu,
+    0xb4091bffu, 0x466298fcu, 0x1871a4d8u, 0xea1a27dbu, 0xf94ad42fu,
+    0x0b21572cu, 0xdfeb33c7u, 0x2d80b0c4u, 0x3ed04330u, 0xccbbc033u,
+    0xa24bb5a6u, 0x502036a5u, 0x4370c551u, 0xb11b4652u, 0x65d122b9u,
+    0x97baa1bau, 0x84ea524eu, 0x7681d14du, 0x2892ed69u, 0xdaf96e6au,
+    0xc9a99d9eu, 0x3bc21e9du, 0xef087a76u, 0x1d63f975u, 0x0e330a81u,
+    0xfc588982u, 0xb21572c9u, 0x407ef1cau, 0x532e023eu, 0xa145813du,
+    0x758fe5d6u, 0x87e466d5u, 0x94b49521u, 0x66df1622u, 0x38cc2a06u,
+    0xcaa7a905u, 0xd9f75af1u, 0x2b9cd9f2u, 0xff56bd19u, 0x0d3d3e1au,
+    0x1e6dcdeeu, 0xec064eedu, 0xc38d26c4u, 0x31e6a5c7u, 0x22b65633u,
+    0xd0ddd530u, 0x0417b1dbu, 0xf67c32d8u, 0xe52cc12cu, 0x1747422fu,
+    0x49547e0bu, 0xbb3ffd08u, 0xa86f0efcu, 0x5a048dffu, 0x8ecee914u,
+    0x7ca56a17u, 0x6ff599e3u, 0x9d9e1ae0u, 0xd3d3e1abu, 0x21b862a8u,
+    0x32e8915cu, 0xc083125fu, 0x144976b4u, 0xe622f5b7u, 0xf5720643u,
+    0x07198540u, 0x590ab964u, 0xab613a67u, 0xb831c993u, 0x4a5a4a90u,
+    0x9e902e7bu, 0x6cfbad78u, 0x7fab5e8cu, 0x8dc0dd8fu, 0xe330a81au,
+    0x115b2b19u, 0x020bd8edu, 0xf0605beeu, 0x24aa3f05u, 0xd6c1bc06u,
+    0xc5914ff2u, 0x37faccf1u, 0x69e9f0d5u, 0x9b8273d6u, 0x88d28022u,
+    0x7ab90321u, 0xae7367cau, 0x5c18e4c9u, 0x4f48173du, 0xbd23943eu,
+    0xf36e6f75u, 0x0105ec76u, 0x12551f82u, 0xe03e9c81u, 0x34f4f86au,
+    0xc69f7b69u, 0xd5cf889du, 0x27a40b9eu, 0x79b737bau, 0x8bdcb4b9u,
+    0x988c474du, 0x6ae7c44eu, 0xbe2da0a5u, 0x4c4623a6u, 0x5f16d052u,
+    0xad7d5351u
+};
+
+target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz)
+{
+    for (target_ulong i = 0; i < sz; i++) {
+        rs1 = zbr_crc32_table[rs1 & 0xFF] ^ (rs1 >> 8);
+    }
+
+    return rs1;
+}
+
+target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz)
+{
+    for (target_ulong i = 0; i < sz; i++) {
+        rs1 = zbr_crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8);
+    }
+
+    return rs1;
+}
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 75f4e434085a7..a25e4daded652 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -34,6 +34,9 @@
 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
 #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
+#define TYPE_RISCV_CPU_LOWRISC_IBEX     RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_LOWRISC_IBEXDEMO RISCV_CPU_TYPE_NAME("lowrisc-ibexdemo")
+#define TYPE_RISCV_CPU_LOWRISC_OPENTITAN RISCV_CPU_TYPE_NAME("lowrisc-opentitan")
 #define TYPE_RISCV_CPU_RV32I            RISCV_CPU_TYPE_NAME("rv32i")
 #define TYPE_RISCV_CPU_RV32E            RISCV_CPU_TYPE_NAME("rv32e")
 #define TYPE_RISCV_CPU_RV64I            RISCV_CPU_TYPE_NAME("rv64i")
@@ -42,7 +45,6 @@
 #define TYPE_RISCV_CPU_RVA22S64         RISCV_CPU_TYPE_NAME("rva22s64")
 #define TYPE_RISCV_CPU_RVA23U64         RISCV_CPU_TYPE_NAME("rva23u64")
 #define TYPE_RISCV_CPU_RVA23S64         RISCV_CPU_TYPE_NAME("rva23s64")
-#define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
 #define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
 #define TYPE_RISCV_CPU_SIFIVE_E         RISCV_CPU_TYPE_NAME("sifive-e")
 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 73d4280d7c84a..04a2a4c286aae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -41,7 +41,7 @@
 /* RISC-V CPU definitions */
 static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH";
 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
-                              RVC, RVS, RVU, RVH, RVG, RVB, 0};
+                              RVC, RVS, RVU, RVH, RVG, RVB, RVX, 0};
 
 /*
  * From vector_helper.c
@@ -676,7 +676,8 @@ bool riscv_cpu_has_work(CPUState *cs)
      */
     return riscv_cpu_all_pending(env) != 0 ||
         riscv_cpu_sirq_pending(env) != RISCV_EXCP_NONE ||
-        riscv_cpu_vsirq_pending(env) != RISCV_EXCP_NONE;
+        riscv_cpu_vsirq_pending(env) != RISCV_EXCP_NONE ||
+        env->debug_cs;
 }
 #endif /* !CONFIG_USER_ONLY */
 
@@ -721,7 +722,6 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
     }
     env->mcause = 0;
     env->miclaim = MIP_SGEIP;
-    env->pc = env->resetvec;
     env->bins = 0;
     env->two_stage_lookup = false;
 
@@ -795,9 +795,47 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
     if (kvm_enabled()) {
         kvm_riscv_reset_vcpu(cpu);
     }
+
+    /* default physical memory protection configuration */
+    const RISCVCPUConfig *cfg = &cpu->cfg;
+    g_assert(cfg->pmp_cfg_count <= MAX_RISCV_PMPS);
+    g_assert(cfg->pmp_addr_count <= MAX_RISCV_PMPS);
+    for (i = 0; i < MAX_RISCV_PMPS; i++) {
+        env->pmp_state.pmp[i].cfg_reg =
+            i < cfg->pmp_cfg_count ? cfg->pmp_cfg[i] : 0;
+    }
+    for (i = 0; i < MAX_RISCV_PMPS; i++) {
+        env->pmp_state.pmp[i].addr_reg =
+            i < cfg->pmp_addr_count ? (target_ulong)cfg->pmp_addr[i] : 0;
+    }
+    for (i = 0; i < MAX_RISCV_PMPS; i++) {
+        pmp_update_rule_addr(env, i);
+    }
+    pmp_update_rule_nums(env);
+
+    env->mseccfg = (target_ulong)cfg->mseccfg;
 #endif
 }
 
+static void riscv_cpu_reset_exit(Object *obj, ResetType type)
+{
+    CPUState *cs = CPU(obj);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+
+#ifndef CONFIG_USER_ONLY
+    CPURISCVState *env = &cpu->env;
+
+    /* reset vector and mtvec may be updated while hart is in reset */
+    env->pc = env->resetvec;
+    env->mtvec = cpu->cfg.mtvec;
+#endif
+
+    if (mcc->parent_phases.exit) {
+        mcc->parent_phases.exit(obj, type);
+    }
+}
+
 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 {
     RISCVCPU *cpu = RISCV_CPU(s);
@@ -924,6 +962,56 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+static bool riscv_cpu_debug_request(CPUState *cs)
+{
+#ifndef CONFIG_USER_ONLY
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    if (!env->debug_dm) {
+        return false;
+    }
+
+    if (!get_field(env->dcsr, DCSR_STEP)) {
+        return false;
+    }
+
+    if (!env->debugger) {
+        env->dcsr = set_field(env->dcsr, DCSR_CAUSE, DCSR_CAUSE_STEP);
+        env->dcsr = set_field(env->dcsr, DCSR_PRV, env->priv);
+        env->dpc = env->pc;
+        env->debugger = true;
+        env->priv = PRV_M;
+        env->pc = env->dmhaltvec;
+        cs->singlestep_enabled = 0;
+        cs->exception_index = -1;
+    }
+
+    return true;
+#else
+    return false;
+#endif
+}
+
+static void riscv_cpu_debug_enable_singlestep(CPUState *s, vaddr pc)
+{
+    (void)pc;
+
+#ifndef CONFIG_USER_ONLY
+    RISCVCPU *cpu = RISCV_CPU(s);
+    CPURISCVState *env = &cpu->env;
+    if (!env->debug_dm) {
+        return;
+    }
+    s->singlestep_enabled = SSTEP_ENABLE | SSTEP_NOIRQ;
+    if (get_field(env->dcsr, DCSR_STOPTIME)) {
+        s->singlestep_enabled |= SSTEP_NOTIMER;
+    }
+#else
+    s->singlestep_enabled = SSTEP_ENABLE;
+#endif
+}
+
 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);
@@ -1047,7 +1135,8 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
             }
             break;
         default:
-            g_assert_not_reached();
+            /* Handle platform / custom local interrupts */
+            riscv_cpu_update_mip(env, 1ULL << irq, BOOL_TO_MASK(level));
         }
     } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
         /* Require H-extension for handling guest local interrupts */
@@ -1171,7 +1260,8 @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVH, "h", "Hypervisor"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)"),
+    MISA_EXT_INFO(RVX, "x", "Non-standard extensions")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
@@ -1373,6 +1463,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 /* These are experimental so mark with 'x-' */
 const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
+    MULTI_EXT_CFG_BOOL("x-zbr", ext_zbr, false),
 
     { },
 };
@@ -2662,6 +2753,14 @@ static const Property riscv_cpu_properties[] = {
 
 #ifndef CONFIG_USER_ONLY
     DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
+    DEFINE_PROP_UINT64("mtvec", RISCVCPU, cfg.mtvec, 0u),
+    DEFINE_PROP_UINT64("mseccfg", RISCVCPU, cfg.mseccfg, 0u),
+    DEFINE_PROP_ARRAY("pmp_cfg", RISCVCPU, cfg.pmp_cfg_count, cfg.pmp_cfg,
+                      qdev_prop_uint8, uint8_t),
+    DEFINE_PROP_ARRAY("pmp_addr", RISCVCPU, cfg.pmp_addr_count, cfg.pmp_addr,
+                      qdev_prop_uint64, uint64_t),
+    DEFINE_PROP_UINT64("dmhaltvec", RISCVCPU, env.dmhaltvec, 0),
+    DEFINE_PROP_UINT64("dmexcpvec", RISCVCPU, env.dmexcpvec, 0),
     DEFINE_PROP_UINT64("rnmi-interrupt-vector", RISCVCPU, env.rnmi_irqvec,
                        DEFAULT_RNMI_IRQVEC),
     DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec,
@@ -2727,7 +2826,8 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data)
     device_class_set_parent_realize(dc, riscv_cpu_realize,
                                     &mcc->parent_realize);
 
-    resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
+    resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold,
+                                       riscv_cpu_reset_exit,
                                        &mcc->parent_phases);
 
     cc->class_by_name = riscv_cpu_class_by_name;
@@ -2737,10 +2837,13 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data)
     cc->gdb_read_register = riscv_cpu_gdb_read_register;
     cc->gdb_write_register = riscv_cpu_gdb_write_register;
     cc->gdb_stop_before_watchpoint = true;
+    cc->debug_request = riscv_cpu_debug_request;
+    cc->debug_enable_singlestep = riscv_cpu_debug_enable_singlestep;
     cc->disas_set_info = riscv_cpu_disas_set_info;
 #ifndef CONFIG_USER_ONLY
     cc->sysemu_ops = &riscv_sysemu_ops;
     cc->get_arch_id = riscv_get_arch_id;
+    mcc->riscv_get_physical_address = riscv_get_physical_address;
 #endif
     cc->gdb_arch_name = riscv_gdb_arch_name;
 #ifdef CONFIG_TCG
@@ -3039,20 +3142,34 @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .misa_mxl_max = MXL_RV32,
     ),
 
-    DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU,
+    DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_LOWRISC_IBEX, TYPE_RISCV_VENDOR_CPU,
         .misa_mxl_max = MXL_RV32,
-        .misa_ext = RVI | RVM | RVC | RVU,
+        .misa_ext = RVI | RVM | RVC | RVU | RVX,
         .priv_spec = PRIV_VERSION_1_12_0,
         .cfg.max_satp_mode = VM_1_10_MBARE,
         .cfg.ext_zifencei = true,
         .cfg.ext_zicsr = true,
+
+        .cfg.marchid = 0x16u,
+        .cfg.mtvec = 0x00000001u,
+
+#ifndef CONFIG_USER_ONLY
+        .custom_csrs = ibex_csr_list,
+#endif
+    ),
+
+    DEFINE_RISCV_CPU(TYPE_RISCV_CPU_LOWRISC_IBEXDEMO, TYPE_RISCV_CPU_LOWRISC_IBEX,
+    ),
+
+    DEFINE_RISCV_CPU(TYPE_RISCV_CPU_LOWRISC_OPENTITAN, TYPE_RISCV_CPU_LOWRISC_IBEX,
         .cfg.pmp = true,
         .cfg.ext_smepmp = true,
 
         .cfg.ext_zba = true,
         .cfg.ext_zbb = true,
         .cfg.ext_zbc = true,
-        .cfg.ext_zbs = true
+        .cfg.ext_zbr = true,
+        .cfg.ext_zbs = true,
     ),
 
     DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 36e7f100374d8..faf8a905ac812 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;
 #define RVH RV('H')
 #define RVG RV('G')
 #define RVB RV('B')
+#define RVX RV('X')
 
 extern const uint32_t misa_bits[];
 const char *riscv_get_misa_ext_name(uint32_t bit);
@@ -407,6 +408,10 @@ struct CPUArchState {
      * translation active.
      */
     bool two_stage_lookup;
+
+    /* Whether to use virtual address for PMP (default: physical address) */
+    bool vaddr_pmp;
+
     /*
      * Signals whether the current exception occurred while doing two-stage
      * address translation for the VS-stage page table walk.
@@ -460,6 +465,11 @@ struct CPUArchState {
     int64_t last_icount;
     bool itrigger_enabled;
 
+    /* debug module */
+    uint32_t dcsr;
+    target_ulong dpc;
+    target_ulong dscratch[RV_MAX_DSCRATCH];
+
     /* machine specific rdtime callback */
     uint64_t (*rdtime_fn)(void *);
     void *rdtime_fn_arg;
@@ -480,13 +490,24 @@ struct CPUArchState {
         target_ulong *val, target_ulong new_val, target_ulong write_mask);
     void *aia_ireg_rmw_fn_arg[4];
 
-    /* True if in debugger mode.  */
-    bool debugger;
+    /*
+     * Debug support
+     */
+    bool debugger; /* True if in debugger mode.  */
+    bool debug_cs; /* Debugger critical section w/o HW IRQ nor WFI */
+    bool debug_dm; /* Debug module is available */
+    unsigned debug_cause; /* Reason for entering debug */
+    uint64_t dmhaltvec; /* Address of halt handler */
+    uint64_t dmexcpvec; /* Address of exception handler */
 
     uint64_t mstateen[SMSTATEEN_MAX_COUNT];
     uint64_t hstateen[SMSTATEEN_MAX_COUNT];
     uint64_t sstateen[SMSTATEEN_MAX_COUNT];
     uint64_t henvcfg;
+
+    /* Ibex custom CSRs */
+    target_ulong cpuctrlsts;
+    target_ulong secureseed;
 #endif
 
     /* Fields from here on are preserved across CPU reset. */
@@ -580,6 +601,14 @@ struct RISCVCPUClass {
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
+
+    int (*riscv_get_physical_address)(CPURISCVState *env, hwaddr *physical,
+                                      int *ret_prot, vaddr addr,
+                                      target_ulong *fault_pte_addr,
+                                      int access_type, int mmu_idx,
+                                      bool first_stage, bool two_stage,
+                                      bool is_debug, bool is_probe);
+
     RISCVCPUDef *def;
 };
 
@@ -626,6 +655,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 char *riscv_isa_string(RISCVCPU *cpu);
 int riscv_cpu_max_xlen(RISCVCPUClass *mcc);
 bool riscv_cpu_option_set(const char *optname);
+int riscv_get_physical_address(CPURISCVState *env, hwaddr *physical,
+                               int *ret_prot, vaddr addr,
+                               target_ulong *fault_pte_addr,
+                               int access_type, int mmu_idx,
+                               bool first_stage, bool two_stage,
+                               bool is_debug, bool is_probe);
 
 #ifndef CONFIG_USER_ONLY
 void riscv_cpu_do_interrupt(CPUState *cpu);
@@ -635,6 +670,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                      MMUAccessType access_type,
                                      int mmu_idx, MemTxAttrs attrs,
                                      MemTxResult response, uintptr_t retaddr);
+void riscv_cpu_store_debug_cause(CPUState *cs, unsigned cause);
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
@@ -982,6 +1018,9 @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* In ibex_csr.c */
+extern const RISCVCSR ibex_csr_list[];
+
 /* In th_csr.c */
 extern const RISCVCSR th_csr_list[];
 
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index b62dd82fe7c0c..70ac21acd57f4 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -455,7 +455,7 @@
 #define CSR_MNCAUSE         0x742
 #define CSR_MNSTATUS        0x744
 
-/* Debug/Trace Registers (shared with Debug Mode) */
+/* Trace Registers (shared with Debug Mode) */
 #define CSR_TSELECT         0x7a0
 #define CSR_TDATA1          0x7a1
 #define CSR_TDATA2          0x7a2
@@ -466,7 +466,8 @@
 /* Debug Mode Registers */
 #define CSR_DCSR            0x7b0
 #define CSR_DPC             0x7b1
-#define CSR_DSCRATCH        0x7b2
+#define CSR_DSCRATCH0       0x7b2
+#define CSR_DSCRATCH1       0x7b3
 
 /* Performance Counters */
 #define CSR_MHPMCOUNTER3    0xb03
@@ -693,6 +694,29 @@ typedef enum {
 /* vsstatus CSR bits */
 #define VSSTATUS64_UXL       0x0000000300000000ULL
 
+/* DCSR CSR bits */
+#define DCSR_PRV             0x00000003
+#define DCSR_STEP            0x00000004
+#define DCSR_NMIP            0x00000008
+#define DCSR_MPRVEN          0x00000010
+#define DCSR_CAUSE           0x000001C0
+#define DCSR_STOPTIME        0x00000200
+#define DCSR_STOPCOUNT       0x00000400
+#define DCSR_STEPIE          0x00000800
+#define DCSR_EBREAKU         0x00001000
+#define DCSR_EBREAKS         0x00002000
+#define DCSR_EBREAKH         0x00004000
+#define DCSR_EBREAKM         0x00008000
+#define DCSR_XDEBUGVER       0xF0000000
+#define DCSR_EBREAK_MASK     0x0000F000
+
+#define DCSR_CAUSE_NONE          0
+#define DCSR_CAUSE_EBREAK        1
+#define DCSR_CAUSE_BREAKPOINT    2
+#define DCSR_CAUSE_HALTREQ       3
+#define DCSR_CAUSE_STEP          4
+#define DCSR_CAUSE_RESETHALTREQ  5
+
 /* Privilege modes */
 #define PRV_U 0
 #define PRV_S 1
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index aa28dc8d7e616..29e02979179a9 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -65,4 +65,7 @@ MATERIALISE_EXT_PREDICATE(xtheadmempair)
 MATERIALISE_EXT_PREDICATE(xtheadsync)
 MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
 
+/* Extensions that are not yet upstream */
+MATERIALISE_EXT_PREDICATE(zbr);
+
 #endif
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index a154ecdc792b3..4e240376f1dc7 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -11,6 +11,7 @@ BOOL_FIELD(ext_zbc)
 BOOL_FIELD(ext_zbkb)
 BOOL_FIELD(ext_zbkc)
 BOOL_FIELD(ext_zbkx)
+BOOL_FIELD(ext_zbr)
 BOOL_FIELD(ext_zbs)
 BOOL_FIELD(ext_zca)
 BOOL_FIELD(ext_zcb)
@@ -155,6 +156,8 @@ BOOL_FIELD(misa_w)
 
 BOOL_FIELD(short_isa_string)
 
+TYPED_FIELD(uint64_t, mtvec, 0)
+
 TYPED_FIELD(uint32_t, mvendorid, 0)
 TYPED_FIELD(uint64_t, marchid, 0)
 TYPED_FIELD(uint64_t, mimpid, 0)
@@ -165,8 +168,15 @@ TYPED_FIELD(uint16_t, elen, 0)
 TYPED_FIELD(uint16_t, cbom_blocksize, 0)
 TYPED_FIELD(uint16_t, cbop_blocksize, 0)
 TYPED_FIELD(uint16_t, cboz_blocksize, 0)
-TYPED_FIELD(uint8_t,  pmp_regions, 0)
-TYPED_FIELD(uint32_t, pmp_granularity, 0)
+
+/* physical memory protection HW configuration */
+TYPED_FIELD(uint8_t,    pmp_regions, 0)
+TYPED_FIELD(uint32_t,   pmp_granularity, 0)
+TYPED_FIELD(uint8_t *,  pmp_cfg, NULL)
+TYPED_FIELD(uint32_t,   pmp_cfg_count, 0)
+TYPED_FIELD(uint64_t *, pmp_addr, NULL)
+TYPED_FIELD(uint32_t,   pmp_addr_count, 0)
+TYPED_FIELD(uint64_t,   mseccfg, 0)
 
 TYPED_FIELD(int8_t, max_satp_mode, -1)
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index c4fb68b5de8a3..69d73ac59d0f0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -51,7 +51,9 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
         uint64_t status = env->mstatus;
 
         if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
+            if (!env->debugger || get_field(env->dcsr, DCSR_MPRVEN)) {
+                mode = get_field(env->mstatus, MSTATUS_MPP);
+            }
             virt = get_field(env->mstatus, MSTATUS_MPV) &&
                    (mode != PRV_M);
             if (virt) {
@@ -551,6 +553,10 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     if (interrupt_request & mask) {
         RISCVCPU *cpu = RISCV_CPU(cs);
         CPURISCVState *env = &cpu->env;
+        if (unlikely(env->debug_dm &&
+                     (env->debugger || get_field(env->dcsr, DCSR_STEP)))) {
+            return false;
+        }
         int interruptno = riscv_cpu_local_irq_pending(env);
         if (interruptno >= 0) {
             cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
@@ -1163,7 +1169,8 @@ static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
 }
 
 /*
- * get_physical_address - get the physical address for this virtual address
+ * riscv_get_physical_address - get the physical address for this virtual
+ * address
  *
  * Do a page table walk to obtain the physical address corresponding to a
  * virtual address. Returns 0 if the translation was successful
@@ -1184,12 +1191,12 @@ static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
  * @two_stage: Are we going to perform two stage translation
  * @is_debug: Is this access from a debugger or the monitor?
  */
-static int get_physical_address(CPURISCVState *env, hwaddr *physical,
-                                int *ret_prot, vaddr addr,
-                                target_ulong *fault_pte_addr,
-                                int access_type, int mmu_idx,
-                                bool first_stage, bool two_stage,
-                                bool is_debug, bool is_probe)
+int riscv_get_physical_address(CPURISCVState *env, hwaddr *physical,
+                               int *ret_prot, vaddr addr,
+                               target_ulong *fault_pte_addr,
+                               int access_type, int mmu_idx,
+                               bool first_stage, bool two_stage,
+                               bool is_debug, bool is_probe)
 {
     /*
      * NOTE: the env->pc value visible here will not be
@@ -1339,10 +1346,10 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
             hwaddr vbase;
 
             /* Do the second stage translation on the base PTE address. */
-            int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
-                                                 base, NULL, MMU_DATA_LOAD,
-                                                 MMUIdx_U, false, true,
-                                                 is_debug, false);
+            int vbase_ret = riscv_get_physical_address(env, &vbase, &vbase_prot,
+                                                       base, NULL, MMU_DATA_LOAD,
+                                                       MMUIdx_U, false, true,
+                                                       is_debug, false);
 
             if (vbase_ret != TRANSLATE_SUCCESS) {
                 if (fault_pte_addr) {
@@ -1657,22 +1664,113 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
     env->two_stage_indirect_lookup = two_stage_indirect;
 }
 
+static bool riscv_cpu_handle_breakpoint(CPUState *cs)
+{
+    /*
+     * EBREAK/C.BREAK causes the receiving privilege mode’s epc register to be
+     * set to the address of the EBREAK instruction itself, not the address of
+     * the following instruction. As ECALL and EBREAK cause synchronous
+     * exceptions, they are not considered to retire, and should not increment
+     * the minstret CSR.
+
+     * Instruction address breakpoints have the same cause value as, but
+     * different priority than, data address breakpoints (a.k.a. watchpoints)
+     * and environment break exceptions (which are raised by the EBREAK
+     * instruction).
+
+     * DCSR ebreakX fields:
+     * 0: ebreak instructions in X-mode behave as described in the Priv. Spec.
+     *   a. the core enters the exception handler routine located at mtvec
+     *      (Debug Mode is not entered)
+     *   b. mepc and mcause are updated
+     * 1: ebreak instructions in X-mode enter Debug Mode.
+     *   a. the core enters Debug Mode and starts executing debug code located
+     *      at dmhaltvec (exception routine not called)
+     *   b. dpc and dcsr are updated
+     */
+    CPURISCVState *env = &RISCV_CPU(cs)->env;
+    target_ulong ebreak = get_field(env->dcsr, DCSR_EBREAK_MASK);
+    if (!(ebreak & (1u << env->priv)) && !env->debugger) {
+        /* breakpoint not handled, fall back to default exception handling */
+        return false;
+    }
+
+    /* clear current exception */
+    cs->exception_index = -1;
+    cs->interrupt_request |= CPU_INTERRUPT_DEBUG;
+    /* the current exception has been handled */
+    return true;
+}
+
+static bool riscv_cpu_handle_debug_exception(CPUState *cs, target_ulong cause)
+{
+    /*
+     * Note: RISCV_EXCP_BREAKPOINT && RISCV_EXCP_SEMIHOST already handled
+     *
+     * Exceptions don’t update any registers. That includes cause, epc, tval,
+     * dpc, and mstatus.
+     * To resume execution, the debug module sets a flag which causes the hart
+     * to execute a dret. When dret is executed, pc is restored from dpc and
+     * normal execution resumes at the privilege set by prv.
+     */
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    if (env->debug_dm) {
+        env->pc = env->dmexcpvec;
+        /* clear current exception */
+        cs->exception_index = -1;
+        return true;
+    }
+
+    return false;
+}
+
+void riscv_cpu_store_debug_cause(CPUState *cs, unsigned cause)
+{
+    /*
+     * Priorities from debug spec 0.13.2
+     * "4.8.1 Debug Control and Status (dcsr, at 0x7b0)"
+     */
+    static const uint8_t debug_cause_priority[] = {
+        [DCSR_CAUSE_NONE] = 0,
+        [DCSR_CAUSE_EBREAK] =  3,
+        [DCSR_CAUSE_BREAKPOINT] = 4,
+        [DCSR_CAUSE_HALTREQ] = 1,
+        [DCSR_CAUSE_STEP] = 0,
+        [DCSR_CAUSE_RESETHALTREQ] = 2,
+    };
+
+    CPURISCVState *env = &RISCV_CPU((cs))->env;
+
+    uint8_t new_prio = cause < ARRAY_SIZE(debug_cause_priority) ?
+        debug_cause_priority[cause] : 0u;
+    uint8_t cur_prio = debug_cause_priority[env->debug_cause];
+
+    if ((env->debug_cause == DCSR_CAUSE_NONE) || (new_prio > cur_prio)) {
+        env->debug_cause = cause;
+    }
+}
+
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPUClass *cc = RISCV_CPU_CLASS(cs->cc);
     CPURISCVState *env = &cpu->env;
     hwaddr phys_addr;
     int prot;
     int mmu_idx = riscv_env_mmu_index(&cpu->env, false);
 
-    if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
-                             true, env->virt_enabled, true, false)) {
+    if (cc->riscv_get_physical_address(env, &phys_addr, &prot, addr, NULL, 0,
+                                       mmu_idx, true, env->virt_enabled, true,
+                                       false)) {
         return -1;
     }
 
     if (env->virt_enabled) {
-        if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
-                                 0, MMUIdx_U, false, true, true, false)) {
+        if (cc->riscv_get_physical_address(env, &phys_addr, &prot, phys_addr,
+                                           NULL, 0, MMUIdx_U, false, true, true,
+                                           false)) {
             return -1;
         }
     }
@@ -1763,6 +1861,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                         bool probe, uintptr_t retaddr)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPUClass *cc = RISCV_CPU_CLASS(cs->cc);
     CPURISCVState *env = &cpu->env;
     vaddr im_address;
     hwaddr pa = 0;
@@ -1784,9 +1883,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     pmu_tlb_fill_incr_ctr(cpu, access_type);
     if (two_stage_lookup) {
         /* Two stage lookup */
-        ret = get_physical_address(env, &pa, &prot, address,
-                                   &env->guest_phys_fault_addr, access_type,
-                                   mmu_idx, true, true, false, probe);
+        ret = cc->riscv_get_physical_address(env, &pa, &prot, address,
+                                             &env->guest_phys_fault_addr,
+                                             access_type, mmu_idx, true, true,
+                                             false, probe);
 
         /*
          * A G-stage exception may be triggered during two state lookup.
@@ -1807,9 +1907,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             /* Second stage lookup */
             im_address = pa;
 
-            ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
-                                       access_type, MMUIdx_U, false, true,
-                                       false, probe);
+            ret = cc->riscv_get_physical_address(env, &pa, &prot2, im_address,
+                                                 NULL, access_type, MMUIdx_U,
+                                                 false, true,
+                                                 false, probe);
 
             qemu_log_mask(CPU_LOG_MMU,
                           "%s 2nd-stage address=%" VADDR_PRIx
@@ -1820,14 +1921,16 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             prot &= prot2;
 
             if (ret == TRANSLATE_SUCCESS) {
-                ret = get_physical_address_pmp(env, &prot_pmp, pa,
+                hwaddr pmp_addr = env->vaddr_pmp ? address : pa;
+
+                ret = get_physical_address_pmp(env, &prot_pmp, pmp_addr,
                                                size, access_type, mode);
-                tlb_size = pmp_get_tlb_size(env, pa);
+                tlb_size = pmp_get_tlb_size(env, pmp_addr);
 
                 qemu_log_mask(CPU_LOG_MMU,
                               "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
                               " %d tlb_size %" HWADDR_PRIu "\n",
-                              __func__, pa, ret, prot_pmp, tlb_size);
+                              __func__, pmp_addr, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
             } else {
@@ -1845,9 +1948,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
         }
     } else {
         /* Single stage lookup */
-        ret = get_physical_address(env, &pa, &prot, address, NULL,
-                                   access_type, mmu_idx, true, false, false,
-                                   probe);
+        ret = cc->riscv_get_physical_address(env, &pa, &prot, address, NULL,
+                                             access_type, mmu_idx, true, false,
+                                             false, probe);
 
         qemu_log_mask(CPU_LOG_MMU,
                       "%s address=%" VADDR_PRIx " ret %d physical "
@@ -1855,14 +1958,16 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       __func__, address, ret, pa, prot);
 
         if (ret == TRANSLATE_SUCCESS) {
-            ret = get_physical_address_pmp(env, &prot_pmp, pa,
+            hwaddr pmp_addr = env->vaddr_pmp ? address : pa;
+
+            ret = get_physical_address_pmp(env, &prot_pmp, pmp_addr,
                                            size, access_type, mode);
-            tlb_size = pmp_get_tlb_size(env, pa);
+            tlb_size = pmp_get_tlb_size(env, pmp_addr);
 
             qemu_log_mask(CPU_LOG_MMU,
                           "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
                           " %d tlb_size %" HWADDR_PRIu "\n",
-                          __func__, pa, ret, prot_pmp, tlb_size);
+                          __func__, pmp_addr, ret, prot_pmp, tlb_size);
 
             prot &= prot_pmp;
         }
@@ -2248,6 +2353,11 @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            if (env->debug_dm) {
+                if (riscv_cpu_handle_breakpoint(cs)) {
+                    return;
+                }
+            }
             tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
@@ -2274,16 +2384,22 @@ void riscv_cpu_do_interrupt(CPUState *cs)
                 cause = RISCV_EXCP_U_ECALL;
             }
         }
+
+        if (env->debug_dm && env->debugger) {
+            if (riscv_cpu_handle_debug_exception(cs, cause)) {
+                return;
+            }
+        }
     }
 
     trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
                      riscv_cpu_get_trap_name(cause, async));
 
     qemu_log_mask(CPU_LOG_INT,
-                  "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
+                  "%s: hart:%d/"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
                   "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
-                  __func__, env->mhartid, async, cause, env->pc, tval,
-                  riscv_cpu_get_trap_name(cause, async));
+                  __func__, cs->cpu_index, env->mhartid, async, cause, env->pc,
+                  tval, riscv_cpu_get_trap_name(cause, async));
 
     mode = env->priv <= PRV_S && cause < 64 &&
         (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PRV_M;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5c91658c3dc41..be147d1eef034 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -775,6 +775,15 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno)
     return RISCV_EXCP_ILLEGAL_INST;
 }
 
+static RISCVException have_mseccfg32(CPURISCVState *env, int csrno)
+{
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return have_mseccfg(env, csrno);
+}
+
 static RISCVException debug(CPURISCVState *env, int csrno)
 {
     if (riscv_cpu_cfg(env)->debug) {
@@ -1022,7 +1031,18 @@ static RISCVException write_vcsr(CPURISCVState *env, int csrno,
 /* User Timers and Counters */
 static target_ulong get_ticks(bool shift)
 {
-    int64_t val = cpu_get_host_ticks();
+    int64_t val;
+
+#if !defined(CONFIG_USER_ONLY)
+    if (icount_enabled()) {
+        val = icount_get_raw();
+    } else {
+        val = cpu_get_host_ticks();
+    }
+#else
+    val = cpu_get_host_ticks();
+#endif
+
     target_ulong result = shift ? val >> 32 : val;
 
     return result;
@@ -5296,6 +5316,20 @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException read_mseccfgh(CPURISCVState *env, int csrno,
+                                   target_ulong *val)
+{
+    *val = 0u;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mseccfgh(CPURISCVState *env, int csrno,
+                                    target_ulong val, uintptr_t ra)
+{
+    /* WARL: ignore all bits */
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
@@ -5402,6 +5436,58 @@ static RISCVException write_mcontext(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException read_dcsr(CPURISCVState *env, int csrno,
+                                target_ulong *val)
+{
+    *val = env->dcsr;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_dcsr(CPURISCVState *env, int csrno,
+                                 target_ulong val, uintptr_t ra)
+{
+    /* STEPIE feature is not supported */
+    target_ulong wmask = DCSR_PRV | DCSR_STEP | DCSR_STOPCOUNT | DCSR_STOPTIME |
+                         DCSR_EBREAKM;
+    if (riscv_has_ext(env, RVS)) {
+        wmask |= DCSR_EBREAKS;
+    }
+    if (riscv_has_ext(env, RVU)) {
+        wmask |= DCSR_EBREAKU;
+    }
+    env->dcsr &= ~wmask;
+    env->dcsr |= val & wmask;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_dpc(CPURISCVState *env, int csrno,
+                               target_ulong *val)
+{
+    *val = env->dpc;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_dpc(CPURISCVState *env, int csrno,
+                                target_ulong val, uintptr_t ra)
+{
+    env->dpc = val;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_dscratch(CPURISCVState *env, int csrno,
+                                    target_ulong *val)
+{
+    *val = env->dscratch[csrno - CSR_DSCRATCH0];
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_dscratch(CPURISCVState *env, int csrno,
+                                    target_ulong val, uintptr_t ra)
+{
+    env->dscratch[csrno - CSR_DSCRATCH0] = val;
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_mnscratch(CPURISCVState *env, int csrno,
                                      target_ulong *val)
 {
@@ -5766,7 +5852,7 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
 
 /*
  * Debugger support.  If not in user mode, set env->debugger before the
- * riscv_csrrw call and clear it after the call.
+ * riscv_csrrw call and restore it after the call.
  */
 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
                                  target_ulong *ret_value,
@@ -5775,6 +5861,7 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
 {
     RISCVException ret;
 #if !defined(CONFIG_USER_ONLY)
+    bool debugger = env->debugger;
     env->debugger = true;
 #endif
     if (!write_mask) {
@@ -5783,7 +5870,7 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
         ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask, 0);
     }
 #if !defined(CONFIG_USER_ONLY)
-    env->debugger = false;
+    env->debugger = debugger;
 #endif
     return ret;
 }
@@ -6164,7 +6251,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
 
     /* Physical Memory Protection */
-    [CSR_MSECCFG]    = { "mseccfg",   have_mseccfg, read_mseccfg, write_mseccfg,
+    [CSR_MSECCFG]    = { "mseccfg", have_mseccfg, read_mseccfg, write_mseccfg,
+                         .min_priv_ver = PRIV_VERSION_1_11_0           },
+    [CSR_MSECCFGH]   = { "mseccfgh", have_mseccfg32, read_mseccfgh, write_mseccfgh,
                          .min_priv_ver = PRIV_VERSION_1_11_0           },
     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
@@ -6307,7 +6396,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_PMPADDR63]  = { "pmpaddr63", pmp, read_pmpaddr, write_pmpaddr,
                          .min_priv_ver = PRIV_VERSION_1_12_0           },
 
-    /* Debug CSRs */
+    /* Trigger CSRs */
     [CSR_TSELECT]   =  { "tselect",  debug, read_tselect,  write_tselect  },
     [CSR_TDATA1]    =  { "tdata1",   debug, read_tdata,    write_tdata    },
     [CSR_TDATA2]    =  { "tdata2",   debug, read_tdata,    write_tdata    },
@@ -6315,6 +6404,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_TINFO]     =  { "tinfo",    debug, read_tinfo,    write_ignore   },
     [CSR_MCONTEXT]  =  { "mcontext", debug, read_mcontext, write_mcontext },
 
+    /* Debug CSRs */
+    [CSR_DCSR]      =  { "dcsr",      debug, read_dcsr,     write_dcsr     },
+    [CSR_DPC]       =  { "dpc",       debug, read_dpc,      write_dpc      },
+    [CSR_DSCRATCH0] =  { "dscratch0", debug, read_dscratch, write_dscratch },
+    [CSR_DSCRATCH1] =  { "dscratch1", debug, read_dscratch, write_dscratch },
+
+    /* Control Transfer Records */
     [CSR_MCTRCTL]    = { "mctrctl",    ctr_mmode,  NULL, NULL, rmw_xctrctl    },
     [CSR_SCTRCTL]    = { "sctrctl",    ctr_smode,  NULL, NULL, rmw_xctrctl    },
     [CSR_VSCTRCTL]   = { "vsctrctl",   ctr_smode,  NULL, NULL, rmw_xctrctl    },
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 56644667497c3..38364f4de51c7 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -31,6 +31,7 @@
 #include "exec/helper-proto.h"
 #include "exec/watchpoint.h"
 #include "system/cpu-timers.h"
+#include "system/cpus.h"
 #include "exec/icount.h"
 
 /*
@@ -113,13 +114,13 @@ static trigger_action_t get_trigger_action(CPURISCVState *env,
     case TRIGGER_TYPE_INT:
     case TRIGGER_TYPE_EXCP:
     case TRIGGER_TYPE_EXT_SRC:
-        qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
-                      trigger_type);
+        qemu_log_mask(LOG_UNIMP, "%s: trigger type: %d is not supported\n",
+                      __func__, trigger_type);
         break;
     case TRIGGER_TYPE_NO_EXIST:
     case TRIGGER_TYPE_UNAVAIL:
-        qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
-                      trigger_type);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger type: %d does not exit\n",
+                      __func__, trigger_type);
         break;
     default:
         g_assert_not_reached();
@@ -176,22 +177,24 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val)
     }
 }
 
-static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
-                                    trigger_type_t t)
+static target_ulong tdata1_validate(CPURISCVState *env, target_ulong index,
+                                    target_ulong val, trigger_type_t t)
 {
-    uint32_t type, dmode;
+    uint32_t type, dmode, cdmode;
     target_ulong tdata1;
 
     switch (riscv_cpu_mxl(env)) {
     case MXL_RV32:
         type = extract32(val, 28, 4);
         dmode = extract32(val, 27, 1);
+        cdmode = extract32(env->tdata1[index], 27, 1);
         tdata1 = RV32_TYPE(t);
         break;
     case MXL_RV64:
     case MXL_RV128:
         type = extract64(val, 60, 4);
         dmode = extract64(val, 59, 1);
+        cdmode = extract64(env->tdata1[index], 59, 1);
         tdata1 = RV64_TYPE(t);
         break;
     default:
@@ -200,11 +203,15 @@ static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
 
     if (type != t) {
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "ignoring type write to tdata1 register\n");
+                      "%s: ignoring type write to tdata1 register\n", __func__);
     }
 
-    if (dmode != 0) {
-        qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n");
+    if (!(env->debug_dm && env->debugger)) {
+        if (dmode != cdmode) {
+            qemu_log_mask(LOG_UNIMP,
+                          "%s: debug mode can only be changed from debugger\n",
+                          __func__);
+        }
     }
 
     return tdata1;
@@ -214,7 +221,7 @@ static inline void warn_always_zero_bit(target_ulong val, target_ulong mask,
                                         const char *msg)
 {
     if (val & mask) {
-        qemu_log_mask(LOG_UNIMP, "%s bit is always zero\n", msg);
+        qemu_log_mask(LOG_UNIMP, "%s: %s bit is always zero\n", __func__, msg);
     }
 }
 
@@ -278,24 +285,31 @@ static target_ulong textra_validate(CPURISCVState *env, target_ulong tdata3)
     return textra;
 }
 
-static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
+static void do_trigger_action(CPURISCVState *env, trigger_action_t action)
 {
-    trigger_action_t action = get_trigger_action(env, trigger_index);
-
     switch (action) {
     case DBG_ACTION_NONE:
         break;
     case DBG_ACTION_BP:
+        riscv_cpu_store_debug_cause(env_cpu(env), DCSR_CAUSE_EBREAK);
         riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
         break;
     case DBG_ACTION_DBG_MODE:
+        if (!env->debug_dm) {
+            cpu_handle_guest_debug(env_cpu(env));
+        } else {
+            riscv_cpu_store_debug_cause(env_cpu(env), DCSR_CAUSE_BREAKPOINT);
+            riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
+        }
+        break;
     case DBG_ACTION_TRACE0:
     case DBG_ACTION_TRACE1:
     case DBG_ACTION_TRACE2:
     case DBG_ACTION_TRACE3:
     case DBG_ACTION_EXT_DBG0:
     case DBG_ACTION_EXT_DBG1:
-        qemu_log_mask(LOG_UNIMP, "action: %d is not supported\n", action);
+        qemu_log_mask(LOG_UNIMP, "%s: action: %d is not supported\n",
+                    __func__, action);
         break;
     default:
         g_assert_not_reached();
@@ -437,27 +451,30 @@ static inline bool type2_breakpoint_enabled(target_ulong ctrl)
 }
 
 static target_ulong type2_mcontrol_validate(CPURISCVState *env,
+                                            target_ulong index,
                                             target_ulong ctrl)
 {
     target_ulong val;
     uint32_t size;
 
     /* validate the generic part first */
-    val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH);
+    val = tdata1_validate(env, index, ctrl, TRIGGER_TYPE_AD_MATCH);
 
     /* validate unimplemented (always zero) bits */
     warn_always_zero_bit(ctrl, TYPE2_MATCH, "match");
     warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain");
-    warn_always_zero_bit(ctrl, TYPE2_ACTION, "action");
     warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing");
     warn_always_zero_bit(ctrl, TYPE2_SELECT, "select");
     warn_always_zero_bit(ctrl, TYPE2_HIT, "hit");
+    warn_always_zero_bit(ctrl, !env->debug_dm ? TYPE2_ACTION : TYPE2_ACT_TRACE,
+                         "action");
 
     /* validate size encoding */
     size = type2_breakpoint_size(env, ctrl);
     if (access_size[size] == -1) {
-        qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
-                                 "SIZE_ANY\n", size);
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: access size %d is not supported, using SIZE_ANY\n",
+                      __func__, size);
     } else {
         val |= (ctrl & TYPE2_SIZELO);
         if (riscv_cpu_mxl(env) == MXL_RV64) {
@@ -466,8 +483,23 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,
     }
 
     /* keep the mode and attribute bits */
-    val |= (ctrl & (TYPE2_U | TYPE2_S | TYPE2_M |
-                    TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC));
+    target_ulong mask = (TYPE2_U | TYPE2_S | TYPE2_M |
+                         TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC);
+    if (env->debug_dm && env->debugger) {
+        mask |= TYPE2_ACT_DEBUG;
+        switch (riscv_cpu_mxl(env)) {
+        case MXL_RV32:
+            mask |= RV32_DMODE;
+            break;
+        case MXL_RV64:
+        case MXL_RV128:
+            mask |= RV64_DMODE;
+            break;
+        default:
+            g_assert_not_reached();
+        }
+    }
+    val |= ctrl & mask;
 
     return val;
 }
@@ -532,7 +564,7 @@ static void type2_reg_write(CPURISCVState *env, target_ulong index,
 
     switch (tdata_index) {
     case TDATA1:
-        new_val = type2_mcontrol_validate(env, val);
+        new_val = type2_mcontrol_validate(env, index, val);
         if (new_val != env->tdata1[index]) {
             env->tdata1[index] = new_val;
             type2_breakpoint_remove(env, index);
@@ -565,13 +597,14 @@ static inline bool type6_breakpoint_enabled(target_ulong ctrl)
 }
 
 static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
+                                             target_ulong index,
                                              target_ulong ctrl)
 {
     target_ulong val;
     uint32_t size;
 
     /* validate the generic part first */
-    val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6);
+    val = tdata1_validate(env, index, ctrl, TRIGGER_TYPE_AD_MATCH6);
 
     /* validate unimplemented (always zero) bits */
     warn_always_zero_bit(ctrl, TYPE6_MATCH, "match");
@@ -584,8 +617,9 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
     /* validate size encoding */
     size = extract32(ctrl, 16, 4);
     if (access_size[size] == -1) {
-        qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
-                                 "SIZE_ANY\n", size);
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: access size %d is not supported, using SIZE_ANY\n",
+                      __func__, size);
     } else {
         val |= (ctrl & TYPE6_SIZE);
     }
@@ -646,7 +680,7 @@ static void type6_reg_write(CPURISCVState *env, target_ulong index,
 
     switch (tdata_index) {
     case TDATA1:
-        new_val = type6_mcontrol6_validate(env, val);
+        new_val = type6_mcontrol6_validate(env, index, val);
         if (new_val != env->tdata1[index]) {
             env->tdata1[index] = new_val;
             type6_breakpoint_remove(env, index);
@@ -734,7 +768,7 @@ void helper_itrigger_match(CPURISCVState *env)
         itrigger_set_count(env, i, count--);
         if (!count) {
             env->itrigger_enabled = riscv_itrigger_enabled(env);
-            do_trigger_action(env, i);
+            do_trigger_action(env, get_trigger_action(env, i));
         }
     }
 }
@@ -771,7 +805,7 @@ static void riscv_itrigger_update_count(CPURISCVState *env)
             executed = current_icount - last_icount;
             itrigger_set_count(env, i, count - executed);
             if (count == executed) {
-                do_trigger_action(env, i);
+                do_trigger_action(env, get_trigger_action(env, i));
             }
         } else {
             /*
@@ -795,13 +829,13 @@ void riscv_itrigger_update_priv(CPURISCVState *env)
     riscv_itrigger_update_count(env);
 }
 
-static target_ulong itrigger_validate(CPURISCVState *env,
+static target_ulong itrigger_validate(CPURISCVState *env, target_ulong index,
                                       target_ulong ctrl)
 {
     target_ulong val;
 
     /* validate the generic part first */
-    val = tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT);
+    val = tdata1_validate(env, index, ctrl, TRIGGER_TYPE_INST_CNT);
 
     /* validate unimplemented (always zero) bits */
     warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action");
@@ -823,7 +857,7 @@ static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
     switch (tdata_index) {
     case TDATA1:
         /* set timer for icount */
-        new_val = itrigger_validate(env, val);
+        new_val = itrigger_validate(env, index, val);
         if (new_val != env->tdata1[index]) {
             env->tdata1[index] = new_val;
             if (icount_enabled()) {
@@ -838,7 +872,8 @@ static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
         break;
     case TDATA2:
         qemu_log_mask(LOG_UNIMP,
-                      "tdata2 is not supported for icount trigger\n");
+                      "%s: tdata2 is not supported for icount trigger\n",
+                      __func__);
         break;
     case TDATA3:
         env->tdata3[index] = textra_validate(env, val);
@@ -858,6 +893,35 @@ static int itrigger_get_adjust_count(CPURISCVState *env)
     return count;
 }
 
+static void tdata1_clear(CPURISCVState *env)
+{
+    target_ulong tselect = env->trigger_cur;
+    CPUState *cs = env_cpu(env);
+    if (cs->watchpoint_hit &&
+        cs->watchpoint_hit == env->cpu_watchpoint[tselect]) {
+        cs->watchpoint_hit = NULL;
+    }
+    int old_trig_type;
+    old_trig_type = extract_trigger_type(env, env->tdata1[tselect]);
+    switch (old_trig_type) {
+        case TRIGGER_TYPE_AD_MATCH:
+            type2_breakpoint_remove(env, tselect);
+            break;
+        case TRIGGER_TYPE_AD_MATCH6:
+            type6_breakpoint_remove(env, tselect);
+            break;
+        case TRIGGER_TYPE_NO_EXIST:
+        case TRIGGER_TYPE_UNAVAIL:
+            break;
+        default:
+            break;
+    }
+    /* only clear trigger config, not HW features */
+    env->tdata1[tselect] &= ~(riscv_cpu_mxl(env) == MXL_RV32 ?
+        (1 << (32-12)) - 1 : (1ll << (64-12)) - 1ll);
+
+}
+
 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
 {
     int trigger_type;
@@ -902,13 +966,19 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
     case TRIGGER_TYPE_INT:
     case TRIGGER_TYPE_EXCP:
     case TRIGGER_TYPE_EXT_SRC:
-        qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
-                      trigger_type);
+        qemu_log_mask(LOG_UNIMP, "%s: trigger type: %d is not supported\n",
+                      __func__, trigger_type);
         break;
     case TRIGGER_TYPE_NO_EXIST:
+        if (!val && tdata_index == TDATA1) {
+            /* Debugger clears TDATA1 to temporarily disable BP/WP */
+            tdata1_clear(env);
+            break;
+        }
+        /* fallthrough */
     case TRIGGER_TYPE_UNAVAIL:
-        qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
-                      trigger_type);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger type: %d does not exit\n",
+                      __func__, trigger_type);
         break;
     default:
         g_assert_not_reached();
@@ -922,18 +992,108 @@ target_ulong tinfo_csr_read(CPURISCVState *env)
            BIT(TRIGGER_TYPE_AD_MATCH6);
 }
 
+static inline const CPUBreakpoint* cpu_breakpoint_check(CPUState *cs, vaddr pc,
+                                                        int mask)
+{
+    CPUBreakpoint *bp;
+
+    if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+        QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
+            if (bp->pc == pc && (bp->flags & mask)) {
+                return bp;
+            }
+        }
+    }
+    return NULL;
+}
+
+static inline unsigned cpu_breakpoint_index(CPUState *cs,
+                                            const CPUBreakpoint* bp)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    unsigned ix=0;
+    for (; ix<RV_MAX_TRIGGERS; ix++) {
+        if (bp == env->cpu_breakpoint[ix]) {
+            break;
+        }
+    }
+
+    return ix;
+}
+
+static inline unsigned cpu_watchpoint_index(CPUState *cs,
+                                            const CPUWatchpoint* wp)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    unsigned ix=0;
+    for (; ix<RV_MAX_TRIGGERS; ix++) {
+        if (wp == env->cpu_watchpoint[ix]) {
+            break;
+        }
+    }
+
+    return ix;
+}
+
 void riscv_cpu_debug_excp_handler(CPUState *cs)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
 
+    if (env->debug_dm) {
+        switch (env->debug_cause) {
+            case DCSR_CAUSE_EBREAK:        /* 1 */
+            case DCSR_CAUSE_BREAKPOINT:    /* 2 */
+            case DCSR_CAUSE_HALTREQ:       /* 3 */
+            case DCSR_CAUSE_STEP:          /* 4 */
+            case DCSR_CAUSE_RESETHALTREQ:  /* 5 */
+                /*
+                 * When ebreak is executed in Debug Mode, ebreak halts the hart
+                 * again but without updating dpc or dcsr (otherwise the debugged
+                 * program return address is lost)
+                 */
+                if (!env->debugger) {
+                    env->dcsr = set_field(env->dcsr, DCSR_CAUSE, env->debug_cause);
+                    env->dcsr = set_field(env->dcsr, DCSR_PRV, env->priv);
+                    env->dpc = env->pc;
+                    env->debugger = true;
+                }
+                env->priv = PRV_M;
+                env->pc = env->dmhaltvec;
+                env->debug_cause = DCSR_CAUSE_NONE;
+                /*
+                 * clear out the exception, otherwise it would be handled over
+                 * to the debug system which in turn stops the VM, while we need to
+                 * execute the halt handler
+                 */
+                cs->exception_index = -1;
+                return;
+            case DCSR_CAUSE_NONE:          /* 0 */
+            default:
+                break;
+        }
+    }
+
     if (cs->watchpoint_hit) {
         if (cs->watchpoint_hit->flags & BP_CPU) {
-            do_trigger_action(env, DBG_ACTION_BP);
+            unsigned trig_idx = cpu_watchpoint_index(cs, cs->watchpoint_hit);
+            trigger_action_t action;
+             action = (trig_idx < RV_MAX_TRIGGERS) ?
+                 get_trigger_action(env, trig_idx) : DBG_ACTION_BP;
+            do_trigger_action(env, action);
         }
     } else {
-        if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
-            do_trigger_action(env, DBG_ACTION_BP);
+        const CPUBreakpoint *bp = cpu_breakpoint_check(cs, env->pc, BP_CPU);
+        if (bp) {
+            unsigned trig_idx = cpu_breakpoint_index(cs, bp);
+            trigger_action_t action;
+            action = (trig_idx < RV_MAX_TRIGGERS) ?
+                 get_trigger_action(env, trig_idx) : DBG_ACTION_BP;
+            do_trigger_action(env, action);
         }
     }
 }
@@ -1056,7 +1216,8 @@ void riscv_trigger_realize(CPURISCVState *env)
 
 void riscv_trigger_reset_hold(CPURISCVState *env)
 {
-    target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
+    target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH,
+                                       env->debug_dm, 0);
     int i;
 
     /* init to type 2 triggers */
@@ -1079,7 +1240,9 @@ void riscv_trigger_reset_hold(CPURISCVState *env)
         env->tdata3[i] = 0;
         env->cpu_breakpoint[i] = NULL;
         env->cpu_watchpoint[i] = NULL;
-        timer_del(env->itrigger_timer[i]);
+        if (env->itrigger_timer[i]) {
+            timer_del(env->itrigger_timer[i]);
+        }
     }
 
     env->mcontext = 0;
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index f76b8f944a2ef..abffaffae5645 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -24,7 +24,8 @@
 
 #include "exec/breakpoint.h"
 
-#define RV_MAX_TRIGGERS         2
+#define RV_MAX_TRIGGERS         4
+#define RV_MAX_DSCRATCH         2
 
 /* register index of tdata CSRs */
 enum {
@@ -81,6 +82,8 @@ typedef enum {
 #define TYPE2_MATCH     (0xf << 7)
 #define TYPE2_CHAIN     BIT(11)
 #define TYPE2_ACTION    (0xf << 12)
+#define TYPE2_ACT_DEBUG (0x1 << 12)
+#define TYPE2_ACT_TRACE (0xe << 12)
 #define TYPE2_SIZELO    (0x3 << 16)
 #define TYPE2_TIMING    BIT(18)
 #define TYPE2_SELECT    BIT(19)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b785456ee08d1..86bc3f42fa4cc 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -84,6 +84,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Floating Point - Half Precision */
 DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
@@ -132,6 +134,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(mnret, tl, env)
+DEF_HELPER_1(dret, tl, env)
 DEF_HELPER_1(ctr_clear, void, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(wrs_nto, void, env)
diff --git a/target/riscv/ibex_csr.c b/target/riscv/ibex_csr.c
new file mode 100644
index 0000000000000..b3c1ef34fd28a
--- /dev/null
+++ b/target/riscv/ibex_csr.c
@@ -0,0 +1,148 @@
+/*
+ * QEMU LowRisc Ibex core features
+ *
+ * Copyright (c) 2023-2024 Rivos, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+/* NOLINTBEGIN(misc-header-include-cycle) */
+#include "cpu.h"
+/* NOLINTEND(misc-header-include-cycle) */
+
+#if !defined(CONFIG_USER_ONLY)
+
+/* Custom CSRs */
+#define CSR_CPUCTRLSTS 0x7c0
+#define CSR_SECURESEED 0x7c1
+
+#define CPUCTRLSTS_ICACHE_ENABLE     0x000
+#define CPUCTRLSTS_DATA_IND_TIMING   0x001
+#define CPUCTRLSTS_DUMMY_INSTR_EN    0x002
+#define CPUCTRLSTS_DUMMY_INSTR_MASK  0x038
+#define CPUCTRLSTS_SYNC_EXC_SEEN     0x040
+#define CPUCTRLSTS_DOUBLE_FAULT_SEEN 0x080
+#define CPUCTRLSTS_IC_SCR_KEY_VALID  0x100
+
+static RISCVException read_cpuctrlsts(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
+{
+    (void)csrno;
+    *val = CPUCTRLSTS_IC_SCR_KEY_VALID | env->cpuctrlsts;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_cpuctrlsts(CPURISCVState *env, int csrno,
+                                       target_ulong val, uintptr_t ra)
+{
+    (void)csrno;
+    (void)ra;
+    /* b7 can only be cleared */
+    env->cpuctrlsts &= ~0xbf;
+    /* b6 should be cleared on mret */
+    env->cpuctrlsts |= val & 0x3f;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_secureseed(CPURISCVState *env, int csrno,
+                                      target_ulong *val)
+{
+    (void)env;
+    (void)csrno;
+    /*
+     * "Seed values are not actually stored in a register and so reads to this
+     * register will always return zero."
+     */
+    *val = 0;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_secureseed(CPURISCVState *env, int csrno,
+                                       target_ulong val, uintptr_t ra)
+{
+    (void)env;
+    (void)csrno;
+    (void)val;
+    (void)ra;
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException any(CPURISCVState *env, int csrno)
+{
+    (void)env;
+    (void)csrno;
+    /*
+     *  unfortunately, this predicate is not public, so duplicate the standard
+     *  implementation
+     */
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mtvec(CPURISCVState *env, int csrno,
+                                 target_ulong *val)
+{
+    (void)csrno;
+    *val = env->mtvec;
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mtvec(CPURISCVState *env, int csrno,
+                                  target_ulong val, uintptr_t ra)
+{
+    (void)csrno;
+    (void)ra;
+    /* bits [1:0] encode mode; Ibex only supports 1 = vectored */
+    if ((val & 3u) != 1u) {
+        qemu_log_mask(LOG_UNIMP,
+                      "CSR_MTVEC: reserved mode not supported 0x" TARGET_FMT_lx
+                      "\n",
+                      val);
+        /* WARL, Ibex will tie any invalid mode writes to 0b01 (vectored) */
+        val &= ~3u;
+        val |= 1u;
+    }
+
+    /* bits [7:2] are always 0, address should be aligned in 256 bytes */
+    env->mtvec = val & ~0xFCu;
+
+    return RISCV_EXCP_NONE;
+}
+
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+const RISCVCSR ibex_csr_list[] = {
+#if !defined(CONFIG_USER_ONLY)
+    {
+        .csrno = CSR_MTVEC,
+        .csr_ops = { "mtvec", any, &read_mtvec, &write_mtvec },
+    },
+    {
+        .csrno = CSR_CPUCTRLSTS,
+        .csr_ops = { "cpuctrlsts", any, &read_cpuctrlsts, &write_cpuctrlsts },
+    },
+    {
+        .csrno = CSR_SECURESEED,
+        .csr_ops = { "secureseed", any, &read_secureseed, &write_secureseed },
+    },
+#endif /* !defined(CONFIG_USER_ONLY) */
+    {},
+};
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index cd23b1f3a9b82..bdf825877ee02 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -118,6 +118,7 @@ sctrclr     000100000100     00000 000 00000 1110011
 uret        0000000    00010 00000 000 00000 1110011
 sret        0001000    00010 00000 000 00000 1110011
 mret        0011000    00010 00000 000 00000 1110011
+dret        0111101    10010 00000 000 00000 1110011
 wfi         0001000    00101 00000 000 00000 1110011
 sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
 
@@ -839,6 +840,18 @@ binvi      01101. ........... 001 ..... 0010011 @sh
 bset       0010100 .......... 001 ..... 0110011 @r
 bseti      00101. ........... 001 ..... 0010011 @sh
 
+# *** RV32 Zbr Experimental Extension ***
+crc32_b    0110000  10000 ..... 001 ..... 0010011 @r2
+crc32_h    0110000  10001 ..... 001 ..... 0010011 @r2
+crc32_w    0110000  10010 ..... 001 ..... 0010011 @r2
+crc32c_b   0110000  11000 ..... 001 ..... 0010011 @r2
+crc32c_h   0110000  11001 ..... 001 ..... 0010011 @r2
+crc32c_w   0110000  11010 ..... 001 ..... 0010011 @r2
+
+# *** RV64 Zbr Experimental Extension (in addition to RV32 Zbr) ***
+crc32_d    0110000  10011 ..... 001 ..... 0010011 @r2
+crc32c_d   0110000  11011 ..... 001 ..... 0010011 @r2
+
 # *** Zfa Standard Extension ***
 fli_s       1111000 00001 ..... 000 ..... 1010011 @r2
 fli_d       1111001 00001 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 8a62b4cfcd9f9..bbb738749d5fa 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -68,6 +68,9 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+#ifndef CONFIG_USER_ONLY
+        riscv_cpu_store_debug_cause(ctx->cs, DCSR_CAUSE_EBREAK);
+#endif
         tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
                       offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
@@ -139,6 +142,20 @@ static bool trans_mnret(DisasContext *ctx, arg_mnret *a)
 #endif
 }
 
+static bool trans_dret(DisasContext *ctx, arg_dret *a)
+{
+#ifndef CONFIG_USER_ONLY
+    decode_save_opc(ctx, 0);
+    translator_io_start(&ctx->base);
+    gen_helper_dret(cpu_pc, tcg_env);
+    exit_tb(ctx); /* no chaining */
+    ctx->base.is_jmp = DISAS_NORETURN;
+    return true;
+#else
+    return false;
+#endif
+}
+
 static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 {
 #ifndef CONFIG_USER_ONLY
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index e4dcc7c991314..59db8b047fe0e 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -36,6 +36,12 @@
     }                                            \
 } while (0)
 
+#define REQUIRE_ZBR(ctx) do {                    \
+    if (!ctx->cfg_ptr->ext_zbr) {                \
+        return false;                            \
+    }                                            \
+} while (0)
+
 #define REQUIRE_ZBS(ctx) do {                    \
     if (!ctx->cfg_ptr->ext_zbs) {                \
         return false;                            \
@@ -569,3 +575,34 @@ static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
     REQUIRE_ZBKX(ctx);
     return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
 }
+
+static bool gen_crc(DisasContext *ctx, arg_r2 *a,
+                    void (*func)(TCGv, TCGv, TCGv), TCGv tsz)
+{
+    REQUIRE_ZBR(ctx);
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    func(dest, src1, tsz);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}
+
+#define TRANS_CRC32(NAME, SIZE) \
+    static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \
+    { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \
+      return gen_crc(ctx, a, gen_helper_crc32, tcg_constant_tl(SIZE)); }
+#define TRANS_CRC32C(NAME, SIZE) \
+    static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \
+    { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \
+      return gen_crc(ctx, a, gen_helper_crc32c, tcg_constant_tl(SIZE)); }
+
+TRANS_CRC32(b, 1);
+TRANS_CRC32(h, 2);
+TRANS_CRC32(w, 4);
+TRANS_CRC32(d, 8);
+TRANS_CRC32C(b, 1);
+TRANS_CRC32C(h, 2);
+TRANS_CRC32C(w, 4);
+TRANS_CRC32C(d, 8);
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index fdefe88ccdd3a..a071852f4c4bd 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -16,6 +16,7 @@ riscv_ss.add(files(
   'cpu.c',
   'cpu_helper.c',
   'csr.c',
+  'ibex_csr.c',
   'fpu_helper.c',
   'gdbstub.c',
   'op_helper.c',
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 6ccc127c30431..275e6687cf49f 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -26,6 +26,7 @@
 #include "accel/tcg/probe.h"
 #include "exec/helper-proto.h"
 #include "exec/tlb-flags.h"
+#include "exec/translation-block.h"
 #include "trace.h"
 
 #ifndef CONFIG_USER_ONLY
@@ -502,6 +503,43 @@ target_ulong helper_mnret(CPURISCVState *env)
     return retpc;
 }
 
+/* need access to internal TCG API */
+extern uint32_t curr_cflags(CPUState *cpu);
+
+target_ulong helper_dret(CPURISCVState *env)
+{
+    if (!(env->priv >= PRV_M) || !(env->debugger)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+
+    target_ulong retpc = env->dpc;
+    if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
+        riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+    }
+
+    /* there is likely more to do here */
+    target_ulong prev_priv = get_field(env->dcsr, DCSR_PRV);
+    target_ulong prev_virt = env->virt_enabled;
+
+    if (riscv_has_ext(env, RVH) && prev_virt) {
+        riscv_cpu_swap_hypervisor_regs(env);
+    }
+    riscv_cpu_set_mode(env, prev_priv, prev_virt);
+
+    CPUState *cs = env_cpu(env);
+    if (get_field(env->dcsr, DCSR_STEP)) {
+        cs->cflags_next_tb = curr_cflags(cs) | CF_NO_GOTO_TB |
+                             CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1;
+    } else {
+        cs->singlestep_enabled = 0;
+    }
+
+    env->debugger = false;
+    env->debug_cause = DCSR_CAUSE_NONE;
+
+    return retpc;
+}
+
 void helper_ctr_add_entry(CPURISCVState *env, target_ulong src,
                           target_ulong dest, target_ulong type)
 {
@@ -552,9 +590,11 @@ void helper_wfi(CPURISCVState *env)
                (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) {
         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
     } else {
-        cs->halted = 1;
-        cs->exception_index = EXCP_HLT;
-        cpu_loop_exit(cs);
+        if (!unlikely(env->debugger || env->debug_cs)) {
+            cs->halted = 1;
+            cs->exception_index = EXCP_HLT;
+            cpu_loop_exit(cs);
+        }
     }
 }
 
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index a68809eef32b4..7a23636026f60 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -282,6 +282,9 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx)
     if (!cpu->cfg.pmu_mask) {
         return 0;
     }
+    if (get_field(env->dcsr, DCSR_STOPCOUNT)) {
+        return 0;
+    }
     value = g_hash_table_lookup(cpu->pmu_event_ctr_map,
                                 GUINT_TO_POINTER(event_idx));
     if (!value) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e1f4dc5ffd04a..82d24ea421fda 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -121,6 +121,8 @@ typedef struct DisasContext {
     bool bcfi_enabled;
 } DisasContext;
 
+#define DISAS_SSTEP       DISAS_TARGET_0
+
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
 {
     return ctx->misa_ext & ext;
@@ -1363,6 +1365,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     decode_opc(env, ctx);
     ctx->base.pc_next += ctx->cur_insn_len;
 
+    if (unlikely(ctx->cs->singlestep_enabled)) {
+        ctx->base.is_jmp = DISAS_SSTEP;
+    }
     /*
      * If 'fcfi_lp_expected' is still true after processing the instruction,
      * then we did not see an 'lpad' instruction, and must raise an exception.
@@ -1370,7 +1375,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
      * code the insn may have emitted will be deleted as dead code following
      * the noreturn exception
      */
-    if (ctx->fcfi_lp_expected) {
+    else if (ctx->fcfi_lp_expected) {
         /* Emit after insn_start, i.e. before the op following insn_start. */
         tcg_ctx->emit_before_op = QTAILQ_NEXT(ctx->base.insn_start, link);
         tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL),
@@ -1389,8 +1394,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
             unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK;
 
             if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {
-                uint16_t next_insn =
-                    translator_lduw(env, &ctx->base, ctx->base.pc_next);
+                uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next);
                 int len = insn_len(next_insn);
 
                 if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {
@@ -1406,6 +1410,10 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
     switch (ctx->base.is_jmp) {
+    case DISAS_SSTEP:
+        ctx->pc_save = ctx->base.pc_first;
+        gen_goto_tb(ctx, 0, 0);
+        break;
     case DISAS_TOO_MANY:
         gen_goto_tb(ctx, 0, 0);
         break;
diff --git a/tests/opentitan/data/earlgrey-tests.txt b/tests/opentitan/data/earlgrey-tests.txt
new file mode 100644
index 0000000000000..fb7b91afcb7b3
--- /dev/null
+++ b/tests/opentitan/data/earlgrey-tests.txt
@@ -0,0 +1,720 @@
+pass: //sw/device/lib/base:crc32_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/lib/base:crc32_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/lib/base:crc32_perftest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/lib/base:crc32_perftest_sim_qemu_sival_rom_ext
+pass: //sw/device/lib/base:hardened_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/lib/base:hardened_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/lib/crypto/drivers:aes_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/lib/crypto/drivers:aes_test_sim_qemu_sival_rom_ext
+pass: //sw/device/lib/crypto/drivers:entropy_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/lib/crypto/drivers:entropy_test_sim_qemu_sival_rom_ext
+pass: //sw/device/lib/crypto/drivers:keymgr_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/lib/crypto/drivers:rv_core_ibex_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/lib/crypto/drivers:rv_core_ibex_test_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/cert:dice_cwt_functest_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/lib/drivers:hmac_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/drivers:hmac_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/drivers:kmac_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/drivers:kmac_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/drivers:retention_sram_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/drivers:retention_sram_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/drivers:rnd_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/drivers:rstmgr_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/drivers:rstmgr_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/drivers:uart_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/drivers:uart_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/ownership:owner_verify_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/ownership:owner_verify_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/sigverify:ecdsa_p256_verify_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/sigverify:ecdsa_p256_verify_functest_sim_qemu_sival_rom_ext
+flaky: //sw/device/silicon_creator/lib/sigverify:mod_exp_ibex_functest_hardcoded_sim_qemu_rom_with_fake_keys  # Occasionally times out due to public GitHub CI runners
+flaky: //sw/device/silicon_creator/lib/sigverify:mod_exp_ibex_functest_hardcoded_sim_qemu_sival_rom_ext  # Occasionally times out due to public GitHub CI runners
+pass: //sw/device/silicon_creator/lib/sigverify:rsa_verify_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/sigverify:rsa_verify_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/sigverify:sigverify_dynamic_functest_hardcoded_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/sigverify:sigverify_dynamic_functest_hardcoded_sim_qemu_sival_rom_ext
+flaky: //sw/device/silicon_creator/lib/sigverify:sigverify_dynamic_functest_wycheproof_sim_qemu_rom_with_fake_keys  # We expect this to pass, but it takes takes >> 60 seconds to run
+flaky: //sw/device/silicon_creator/lib/sigverify:sigverify_dynamic_functest_wycheproof_sim_qemu_sival_rom_ext  # We expect this to pass, but it takes takes >> 60 seconds to run
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:fors_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:fors_test_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:mgf1_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:mgf1_test_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:thash_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:thash_test_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_hardcoded_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_hardcoded_sim_qemu_sival_rom_ext
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat0_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat0_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat1_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat1_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat2_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat2_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat3_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat3_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat4_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat4_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat5_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat5_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat6_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat6_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat7_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat7_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat8_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat8_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat9_sim_qemu_rom_with_fake_keys  # Occasional timing errors when running in parallel on public GitHub CI
+flaky: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:verify_test_kat9_sim_qemu_sival_rom_ext  # Occasional timing errors when running in parallel on public GitHub CI
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:wots_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/sigverify/sphincsplus/test:wots_test_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib/sigverify:spx_verify_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/lib/sigverify:spx_verify_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/silicon_creator/lib:boot_data_functest_sim_qemu_rom_with_fake_keys
+flaky: //sw/device/silicon_creator/lib:irq_asm_functest_sim_qemu_rom_with_fake_keys  # Fails ~80% of the time due to an unknown BFV on intentional reset via watchdog/rstmgr. Unknown cause, perhaps timing.
+flaky: //sw/device/silicon_creator/lib:irq_asm_functest_sim_qemu_sival_rom_ext  # Fails ~80% of the time due to an unknown BFV on intentional reset via watchdog/rstmgr. Unknown cause, perhaps timing.
+pass: //sw/device/silicon_creator/rom_ext/e2e/attestation:print_certs_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_bad_next_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_bad_primary_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_empty_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_enter_rescue_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_min_sec_ver_a_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_min_sec_ver_b_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_next_aab_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_next_aba_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_next_abb_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/boot_svc:boot_svc_primary_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/dice_chain:corrupted_digest_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/dice_chain:debug_mode_off_dice_cwt_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/dice_chain:debug_mode_off_dice_x509_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/dice_chain:debug_mode_on_dice_cwt_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/dice_chain:debug_mode_on_dice_x509_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/dice_chain:no_refresh_dice_cwt_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/dice_chain:no_refresh_dice_x509_test_sim_qemu_rom_ext
+flaky: //sw/device/silicon_creator/rom_ext/e2e/dice_chain:variation_interop_x509_first_test_sim_qemu_rom_with_fake_keys  # Expected to pass but can timeout in GitHub CI due to taking > 60 seconds.
+flaky: //sw/device/silicon_creator/rom_ext/e2e/dice_chain:variation_interop_cwt_first_test_sim_qemu_rom_with_fake_keys  # Expected to pass but can timeout in GitHub CI due to taking > 60 seconds.
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_activate_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_appkey_constraint_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_app_key_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_endorsee_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_locked_update_no_exec_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_locked_update_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_owner_block_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_ownership_key_alg_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_ownership_key_alg_with_detached_sig_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_unlock_signature_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:bad_unlock_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:flash_error_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:flash_permission_test_slot_aa_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:flash_permission_test_slot_ab_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:flash_permission_test_slot_ba_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:flash_permission_test_slot_bb_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:good_appkey_constraint_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:install_owner_upgrade_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:invalid_device_id_request_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:invalid_key_alg_activate_request_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:invalid_nonce_request_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:locked_update_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:newversion_badlock_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:newversion_nodelock_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:newversion_noupdate_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:newversion_noupdate_with_bad_owner_block_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:newversion_pq_downgrade_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:newversion_pq_to_pq_update_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:newversion_update_test_sim_qemu_rom_ext
+flaky: //sw/device/silicon_creator/rom_ext/e2e/ownership:rescue_limit_test_sim_qemu_rom_ext  # Xmodem flow has tight timing on UART transfer which may fail when run in parallel on slower hosts.
+flaky: //sw/device/silicon_creator/rom_ext/e2e/ownership:rescue_permission_test_sim_qemu_rom_ext  # Xmodem flow has tight timing on UART transfer which may fail when run in parallel on slower hosts.
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:transfer_any_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:transfer_bl0_slot_b_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:transfer_ecdsa_to_pq_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:transfer_endorsed_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:transfer_keymgr_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:transfer_pq_to_pq_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:transfer_spx_pure_to_spx_prehash_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:unlock_detached_sig_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:unlock_when_recovery_state_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/ownership:unlock_with_owner_recovery_key_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:bad_manifest_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:bad_spx_manifest_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:isfb_boot_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:key_dev_hybrid_spx_prehashed_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:key_dev_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:key_prod_hybrid_spx_pure_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:key_prod_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:key_test_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:key_unauthorized_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_imm_section_virtual_a_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_owner_slot_a_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_owner_slot_b_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_owner_virtual_a_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_owner_virtual_b_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_romext_slot_a_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_romext_slot_b_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_romext_virtual_a_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_romext_virtual_a_with_imm_romext_enabled_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom_ext/e2e/verified_boot:position_romext_virtual_b_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom/e2e/address_translation:rom_ext_a_flash_a_bad_addr_trans_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom/e2e/address_translation:rom_ext_a_flash_a_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom/e2e/address_translation:rom_ext_a_flash_b_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom/e2e/address_translation:rom_ext_b_flash_a_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom/e2e/address_translation:rom_ext_b_flash_b_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom/e2e/address_translation:rom_ext_v_flash_a_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom/e2e/address_translation:rom_ext_v_flash_b_sim_qemu_rom_ext
+pass: //sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_otp_invalid_meas_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_otp_meas_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_otp_no_meas_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_dev_a_bad_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_dev_a_bad_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_dev_a_nothing_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_dev_a_nothing_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_prod_a_bad_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_prod_a_bad_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_prod_a_nothing_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_prod_a_nothing_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_prod_end_a_bad_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_prod_end_a_bad_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_prod_end_a_nothing_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_prod_end_a_nothing_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_rma_a_bad_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_rma_a_bad_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_rma_a_nothing_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_rma_a_nothing_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_test_unlocked0_a_bad_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_test_unlocked0_a_bad_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_test_unlocked0_a_nothing_b_bad_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_always:sigverify_always_test_unlocked0_a_nothing_b_nothing_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_dev_ecdsa_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_dev_ecdsa_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_dev_ecdsa_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_dev_spx_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_dev_spx_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_dev_spx_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_ecdsa_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_ecdsa_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_ecdsa_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_end_ecdsa_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_end_ecdsa_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_end_ecdsa_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_end_spx_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_end_spx_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_end_spx_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_spx_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_spx_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_prod_spx_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_rma_ecdsa_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_rma_ecdsa_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_rma_ecdsa_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_rma_spx_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_rma_spx_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_rma_spx_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_test_unlocked0_ecdsa_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_test_unlocked0_ecdsa_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_test_unlocked0_ecdsa_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_test_unlocked0_spx_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_test_unlocked0_spx_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_type:sigverify_key_type_test_unlocked0_spx_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_dev_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_dev_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_prod_end_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_prod_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_rma_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_rma_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_rma_test_key_0_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_test_unlocked0_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_test_unlocked0_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_blank_test_unlocked0_test_key_0_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_dev_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_dev_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_prod_end_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_prod_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_rma_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_rma_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_rma_test_key_0_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_test_unlocked0_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_test_unlocked0_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_ecdsa_revoked_test_unlocked0_test_key_0_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_dev_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_dev_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_prod_end_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_prod_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_rma_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_rma_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_rma_test_key_0_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_test_unlocked0_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_test_unlocked0_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_blank_test_unlocked0_test_key_0_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_dev_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_dev_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_prod_end_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_prod_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_rma_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_rma_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_rma_test_key_0_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_test_unlocked0_dev_key_0_dev_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_test_unlocked0_prod_key_0_prod_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_key_validity:sigverify_key_validity_spx_revoked_test_unlocked0_test_key_0_test_key_0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_dev_disabled_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_dev_enabled_true_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_dev_enabled_zero_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_prehashed_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_prod_disabled_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_prod_enabled_true_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_prod_enabled_zero_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_prod_end_disabled_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_prod_end_enabled_true_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_prod_end_enabled_zero_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_rma_disabled_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_rma_enabled_true_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_rma_enabled_zero_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_test_unlocked0_disabled_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_test_unlocked0_enabled_true_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_spx:sigverify_spx_test_unlocked0_enabled_zero_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_dev_bs_lc_dev_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_dev_bs_lc_prod_end_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_dev_bs_lc_prod_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_dev_bs_lc_rma_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_dev_bs_lc_test_unlocked0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_bs_lc_dev_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_bs_lc_prod_end_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_bs_lc_prod_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_bs_lc_rma_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_bs_lc_test_unlocked0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_end_bs_lc_dev_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_end_bs_lc_prod_end_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_end_bs_lc_prod_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_end_bs_lc_rma_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_prod_end_bs_lc_test_unlocked0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_rma_bs_lc_dev_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_rma_bs_lc_prod_end_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_rma_bs_lc_prod_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_rma_bs_lc_rma_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_rma_bs_lc_test_unlocked0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_test_bs_lc_dev_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_test_bs_lc_prod_end_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_test_bs_lc_prod_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_test_bs_lc_rma_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_all_constraints_mf_lc_test_bs_lc_test_unlocked0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_device_id_family_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_device_id_family_no_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_device_id_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_device_id_no_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_invalid_unselected_device_id_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_invalid_unselected_life_cycle_state_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_invalid_unselected_manuf_state_creator_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_invalid_unselected_manuf_state_owner_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_dev_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_dev_no_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_prod_end_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_prod_end_no_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_prod_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_prod_no_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_rma_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_rma_no_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_test_unlocked0_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_lc_state_test_unlocked0_no_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_manuf_state_creator_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_manuf_state_creator_no_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_manuf_state_owner_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e/sigverify_usage_constraints:sigverify_usage_constraint_manuf_state_owner_no_match_sim_qemu_rom_with_fake_keys
+pass: //sw/device/silicon_creator/rom/e2e:rom_e2e_flash_ctrl_init_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:aes_entropy_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:aes_entropy_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:aes_idle_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:aes_idle_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:aes_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:aes_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:alert_handler_lpg_clkoff_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:alert_handler_lpg_clkoff_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:alert_handler_ping_ok_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:alert_handler_ping_ok_test_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests:aon_timer_irq_test_sim_qemu_rom_with_fake_keys # Test checks IRQ timing which may be slightly inaccurate on QEMU, and so rarely fails
+flaky: //sw/device/tests:aon_timer_irq_test_sim_qemu_sival_rom_ext # Test checks IRQ timing which may be slightly inaccurate on QEMU, and so rarely fails
+flaky: //sw/device/tests/autogen:alert_test_sim_qemu_rom_with_fake_keys  # Fails rarely when running in parallel on CI runners, likely due to timing issues.
+flaky: //sw/device/tests/autogen:alert_test_sim_qemu_sival_rom_ext  # Fails rarely when running in parallel on CI runners, likely due to timing issues.
+pass: //sw/device/tests:clkmgr_jitter_frequency_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:clkmgr_jitter_frequency_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:clkmgr_jitter_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:clkmgr_jitter_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:clkmgr_off_aes_trans_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:clkmgr_off_aes_trans_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:clkmgr_off_hmac_trans_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:clkmgr_off_hmac_trans_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:clkmgr_off_kmac_trans_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:clkmgr_off_kmac_trans_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:clkmgr_off_otbn_trans_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:clkmgr_off_otbn_trans_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:clkmgr_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:clkmgr_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:crt_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:crt_test_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests/crypto:aes_functest_sim_qemu_rom_with_fake_keys  # Test fails sometimes due to incorrect encrypted data when it didn't before, need to root cause
+flaky: //sw/device/tests/crypto:aes_functest_sim_qemu_sival_rom_ext  # Test fails sometimes due to incorrect encrypted data when it didn't before, need to root cause
+flaky: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_rom_with_fake_keys  # Test fails ~1% of the time due to an illegal instruction exception, need to root cause
+flaky: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_sival_rom_ext  # Test fails ~1% of the time due to an illegal instruction exception, need to root cause
+flaky: //sw/device/tests/crypto:aes_gcm_timing_test_sim_qemu_rom_with_fake_keys  # Passes < 5% of the time. This test checks for constant time crypto operations.
+flaky: //sw/device/tests/crypto:aes_gcm_timing_test_sim_qemu_sival_rom_ext  # Passes < 5% of the time. This test checks for constant time crypto operations.
+flaky: //sw/device/tests/crypto:aes_kwp_functest_sim_qemu_rom_with_fake_keys  # Recently started failing rarely, needs to be debugged.
+flaky: //sw/device/tests/crypto:aes_kwp_functest_sim_qemu_sival_rom_ext  # Recently started failing rarely, needs to be debugged.
+flaky: //sw/device/tests/crypto:aes_kwp_kat_functest_sim_qemu_rom_with_fake_keys  # Recently started failing rarely, needs to be debugged.
+flaky: //sw/device/tests/crypto:aes_kwp_kat_functest_sim_qemu_sival_rom_ext  # Recently started failing rarely, needs to be debugged.
+pass: //sw/device/tests/crypto:aes_kwp_sideload_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:aes_kwp_sideload_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:aes_sideload_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:aes_sideload_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_rom_with_fake_keys  # Rarely fails entropy randomness check due to lack of key masking
+pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_sival_rom_ext  # Rarely fails entropy randomness check due to lack of key masking
+pass: //sw/device/tests/crypto:ecdh_p256_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:ecdh_p256_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:ecdh_p256_sideload_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:ecdh_p256_sideload_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:ecdh_p384_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:ecdh_p384_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:ecdh_p384_sideload_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:ecdh_p384_sideload_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:ecdsa_p256_verify_functest_hardcoded_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:ecdsa_p256_verify_functest_hardcoded_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:ecdsa_p256_sideload_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:ecdsa_p256_sideload_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:ecdsa_p384_sideload_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:ecdsa_p384_sideload_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:hkdf_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:hkdf_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:hmac_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:hmac_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:hmac_multistream_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:hmac_multistream_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:hmac_sha256_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:hmac_sha256_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:hmac_sha384_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:hmac_sha384_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:hmac_sha512_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:hmac_sha512_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:kdf_hmac_ctr_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:kdf_hmac_ctr_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:kdf_kmac_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:kdf_kmac_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:kdf_kmac_sideload_functest_hardcoded_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:kdf_kmac_sideload_functest_hardcoded_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:kmac_functest_hardcoded_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:kmac_functest_hardcoded_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:kmac_sideload_functest_hardcoded_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:kmac_sideload_functest_hardcoded_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:rsa_2048_encryption_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:rsa_2048_encryption_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:rsa_2048_key_from_cofactor_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:rsa_2048_key_from_cofactor_functest_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests/crypto:rsa_2048_keygen_functest_sim_qemu_rom_with_fake_keys  # Occasionally times out due to public GitHub CI runners
+flaky: //sw/device/tests/crypto:rsa_2048_keygen_functest_sim_qemu_sival_rom_ext  # Occasionally times out due to public GitHub CI runners
+pass: //sw/device/tests/crypto:rsa_2048_signature_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:rsa_2048_signature_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:rsa_3072_encryption_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:rsa_3072_encryption_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:rsa_3072_signature_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:rsa_3072_signature_functest_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests/crypto:rsa_4096_encryption_functest_sim_qemu_rom_with_fake_keys  # Fails timing (max cycle count) check ~25% of the time
+flaky: //sw/device/tests/crypto:rsa_4096_encryption_functest_sim_qemu_sival_rom_ext  # Fails timing (max cycle count) check ~25% of the time
+flaky: //sw/device/tests/crypto:rsa_4096_signature_functest_sim_qemu_rom_with_fake_keys  # Fails timing (max cycle count) check ~25% of the time
+flaky: //sw/device/tests/crypto:rsa_4096_signature_functest_sim_qemu_sival_rom_ext  # Fails timing (max cycle count) check ~25% of the time
+pass: //sw/device/tests/crypto:sha256_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:sha256_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:sha384_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:sha384_functest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests/crypto:sha512_functest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests/crypto:sha512_functest_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_rom_with_fake_keys  # Rarely fails entropy randomness check due to lack of key masking
+flaky: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_sival_rom_ext  # Rarely fails entropy randomness check due to lack of key masking
+pass: //sw/device/tests:csrng_kat_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:csrng_kat_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:csrng_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:csrng_smoketest_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests:edn_auto_mode_sim_qemu_rom_with_fake_keys  # Fails ~75% of the time due to timing issues (deadline exceeded).
+flaky: //sw/device/tests:edn_auto_mode_sim_qemu_sival_rom_ext  # Fails ~75% of the time due to timing issues (deadline exceeded).
+pass: //sw/device/tests:edn_sw_mode_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:edn_sw_mode_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:entropy_src_fw_ovr_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:entropy_src_fw_ovr_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:entropy_src_kat_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:entropy_src_kat_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:example_concurrency_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:example_concurrency_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:example_test_from_flash_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:example_test_from_flash_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests:flash_ctrl_clock_freqs_test_sim_qemu_rom_with_fake_keys  # After processing commands for uninitialized flash, the timing gets tighter and this fails < 5% of the time.
+flaky: //sw/device/tests:flash_ctrl_clock_freqs_test_sim_qemu_sival_rom_ext  # After processing commands for uninitialized flash, the timing gets tighter and this fails < 5% of the time.
+pass: //sw/device/tests:flash_ctrl_info_access_lc_dev_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:flash_ctrl_info_access_lc_prod_end_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:flash_ctrl_info_access_lc_prod_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:flash_ctrl_info_access_lc_rma_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:flash_ctrl_info_access_lc_test_unlocked0_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:flash_ctrl_mem_protection_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:flash_ctrl_ops_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:flash_ctrl_ops_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:flash_ctrl_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:flash_ctrl_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:flash_ctrl_write_clear_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:flash_ctrl_write_clear_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:hmac_enc_idle_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:hmac_enc_idle_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:hmac_enc_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:hmac_enc_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:hmac_secure_wipe_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:hmac_secure_wipe_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:hmac_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:hmac_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:keymgr_derive_attestation_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:keymgr_derive_attestation_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:keymgr_derive_sealing_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:keymgr_derive_sealing_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:keymgr_key_derivation_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:keymgr_key_derivation_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:keymgr_sideload_aes_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:keymgr_sideload_aes_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:keymgr_sideload_kmac_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:keymgr_sideload_kmac_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:keymgr_sideload_otbn_simple_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:keymgr_sideload_otbn_simple_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:keymgr_sideload_otbn_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:keymgr_sideload_otbn_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:kmac_endianess_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:kmac_endianess_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:kmac_idle_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:kmac_idle_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:kmac_kmac_key_sideload_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:kmac_kmac_key_sideload_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:kmac_mode_cshake_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:kmac_mode_cshake_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:kmac_mode_kmac_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:kmac_mode_kmac_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:kmac_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:kmac_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:lc_ctrl_otp_hw_cfg0_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:lc_ctrl_otp_hw_cfg0_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:otbn_ecdsa_op_irq_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:otbn_ecdsa_op_irq_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:otbn_irq_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:otbn_irq_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:otbn_isa_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:otbn_isa_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:otbn_randomness_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:otbn_randomness_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:otbn_rsa_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:otbn_rsa_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:otbn_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:otbn_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:otp_ctrl_descrambling_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:plic_sw_irq_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:plic_sw_irq_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:pmp_smoketest_napot_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:pmp_smoketest_napot_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:pmp_smoketest_tor_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:pmp_smoketest_tor_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:pwrmgr_lowpower_cancel_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:pwrmgr_lowpower_cancel_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:pwrmgr_sleep_disabled_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:pwrmgr_sleep_disabled_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests/qemu:i2c_qemu_target_device_test_sim_qemu_rom_with_fake_keys  # Fails occassionally when running in parallel on a slow host, may be a timing issue.
+flaky: //sw/device/tests/qemu:i2c_qemu_target_device_test_sim_qemu_sival_rom_ext  # Fails occassionally when running in parallel on a slow host, may be a timing issue.
+flaky: //sw/device/tests/qemu:i2c_qemu_test_sim_qemu_rom_with_fake_keys  # Fails ~10% of the time when running in parallel. Root cause unknown.
+pass: //sw/device/tests:rom_exit_immediately_sim_qemu_base
+pass: //sw/device/tests:rstmgr_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:rstmgr_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:rstmgr_sw_req_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:rstmgr_sw_req_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:rv_core_ibex_mem_test_prod_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:rv_core_ibex_mem_test_prod_sim_qemu_sival_rom_ext
+flaky: //sw/device/tests:rv_core_ibex_rnd_test_sim_qemu_rom_with_fake_keys  # Passes and fails randomly, likely due to the test using randomness.
+flaky: //sw/device/tests:rv_core_ibex_rnd_test_sim_qemu_sival_rom_ext  # Passes and fails randomly, likely due to the test using randomness.
+pass: //sw/device/tests:rv_timer_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:rv_timer_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:spi_device_flash_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:spi_device_flash_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:spi_device_tpm_tx_rx_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:spi_device_tpm_tx_rx_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:spi_host_irq_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:spi_host_irq_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:spi_passthru_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:spi_passthru_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:sram_ctrl_execution_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:sram_ctrl_execution_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:sram_ctrl_memset_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:sram_ctrl_memset_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:sram_ctrl_readback_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:sram_ctrl_readback_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:sram_ctrl_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:sram_ctrl_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:sram_ctrl_subword_access_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:sram_ctrl_subword_access_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:uart_smoketest_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:uart_smoketest_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:usbdev_mem_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:usbdev_mem_test_sim_qemu_sival_rom_ext
+pass: //sw/device/tests:usbdev_vbus_test_sim_qemu_rom_with_fake_keys
+pass: //sw/device/tests:usbdev_vbus_test_sim_qemu_sival_rom_ext
+pass: //third_party/coremark/top_earlgrey:coremark_test_sim_qemu_rom_with_fake_keys
+pass: //third_party/coremark/top_earlgrey:coremark_test_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-ADDI16SP_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-ADDI16SP_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-ADDI4SPN_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-ADDI4SPN_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-ADDI_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-ADDI_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-ADD_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-ADD_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-ANDI_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-ANDI_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-AND_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-AND_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-BEQZ_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-BEQZ_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-BNEZ_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-BNEZ_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-JALR_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-JALR_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-JAL_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-JAL_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-JR_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-JR_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-J_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-J_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-LI_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-LI_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-LUI_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-LUI_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-LW_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-LW_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-LWSP_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-LWSP_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-MV_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-MV_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-OR_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-OR_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-SLLI_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-SLLI_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-SRAI_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-SRAI_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-SRLI_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-SRLI_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-SUB_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-SUB_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-SW_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-SW_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-SWSP_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-SWSP_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:C-XOR_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:C-XOR_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:DIV_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:DIV_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:DIVU_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:DIVU_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-ADD-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-ADD-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-ADDI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-ADDI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-AND-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-AND-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-ANDI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-ANDI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-AUIPC-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-AUIPC-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-BEQ-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-BEQ-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-BGE-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-BGE-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-BGEU-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-BGEU-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-BLT-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-BLT-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-BLTU-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-BLTU-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-BNE-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-BNE-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-CSRRC-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-CSRRC-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-CSRRCI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-CSRRCI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-CSRRS-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-CSRRS-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-CSRRSI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-CSRRSI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-CSRRW-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-CSRRW-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-CSRRWI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-CSRRWI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-DELAY_SLOTS-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-DELAY_SLOTS-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-ECALL-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-ECALL-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-ENDIANESS-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-ENDIANESS-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-IO-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-IO-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-JAL-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-JAL-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-JALR-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-JALR-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-LB-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-LB-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-LBU-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-LBU-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-LH-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-LH-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-LHU-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-LHU-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-LUI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-LUI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-LW-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-LW-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-OR-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-OR-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-ORI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-ORI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-RF_size-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-RF_size-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-RF_width-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-RF_width-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SB-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SB-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SH-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SH-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SLL-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SLL-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SLLI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SLLI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SLT-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SLT-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SLTI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SLTI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SLTIU-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SLTIU-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SLTU-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SLTU-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SRA-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SRA-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SRAI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SRAI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SRL-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SRL-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SRLI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SRLI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SUB-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SUB-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-SW-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-SW-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-XOR-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-XOR-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:I-XORI-01_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:I-XORI-01_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:MULH_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:MULH_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:MULHSU_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:MULHSU_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:MULHU_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:MULHU_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:MUL_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:MUL_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:REM_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:REM_sim_qemu_sival_rom_ext
+pass: //third_party/riscv-compliance:REMU_sim_qemu_rom_with_fake_keys
+pass: //third_party/riscv-compliance:REMU_sim_qemu_sival_rom_ext