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{
"bridge": [
{
"arxiv_id": "2601.22705",
"title": "CONCUR: High-Throughput Agentic Batch Inference of LLM via Congestion-Based Concurrency Control",
"abstract": "Batch inference for agentic workloads stresses the GPU key-value (KV) cache in a sustained and cumulative manner, often causing severe throughput degradation well before memory capacity is exhausted. We identify this phenomenon as middle-phase thrashing, a previously under-characterized pathology in which cache efficiency collapses as long-lived agents accumulate state over time. We argue that mitigating this pathology requires moving beyond reactive, request-level cache management to proactive, agent-level admission control. Drawing inspiration from congestion control in distributed systems, we view the KV cache as a shared resource whose efficient utilization depends on feedback-driven regulation. Based on this insight, we present CONCUR, a lightweight control layer that regulates agent admission to bound aggregate cache pressure while preserving execution continuity. CONCUR adapts a cache-aware control algorithm to dynamically adjust the number of active agents using runtime cache signals. Across large models and real-world agent workloads, CONCUR prevents middle-phase thrashing and improves batch inference throughput by up to 4.09x on Qwen3-32B and 1.9x on DeepSeek-V3, while remaining compatible with existing LLM serving systems.",
"authors": [
"Qiaoling Chen",
"Zhisheng Ye",
"Tian Tang",
"Peng Sun",
"Boyu Tian",
"Guoteng Wang",
"Shenggui Li",
"Yonggang Wen",
"Zhenhua Han",
"Tianwei Zhang"
],
"published_at": "2026-01-30T08:27:20",
"categories": [
"cs.DC"
],
"url": "http://arxiv.org/abs/2601.22705v1",
"code_url": "",
"github_submission_flag": false,
"hf_trending_flag": false,
"citation_count": 0,
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"scope_bucket": "systems",
"domain_bucket": "llm",
"paper_type": "systems",
"narrow_domain_flag": false,
"sim_public": 0.5403847694396973,
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"momentum": 0.0,
"teachability": 0.75,
"novelty_score": 0.40668225288391113,
"evidence_score": 0.53,
"direct_memory_relevance": 0.5972424745559692,
"systems_leverage": 0.7,
"deployment_proximity": 0.7,
"memory_adjacent_future_value": 0.0,
"bandwidth_capacity": 0.2,
"transferability_score": 0.72,
"clarity": 0.7,
"reproducibility": 0.5,
"public_interest_score": 0.5731177687644959,
"memory_score": 0.7281727423667907,
"quality_score": 0.525,
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"influencer_boost": 0.0,
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"time_window": "90d",
"compound_window_boost": 0.0,
"first_seen_date": "",
"fatigue_penalty": 0.0,
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"badges": [
"Public AI",
"Memory/Storage Core",
"Bridge",
"Systems",
"Inference"
],
"status": "Cover now",
"why_now": "Agentic inference is stressing serving stacks in ways standard request-level schedulers do not handle well, and this paper names a concrete new failure mode around sustained KV-cache pressure. The congestion-control framing gives operators a practical systems idea that could matter quickly as long-context and multi-step agent workloads scale.",
"why_not_higher": "The contribution is focused on inference control-plane behavior rather than a broader shift in model architecture or training, so its audience is strongest among serving and systems practitioners. The abstract shows strong throughput wins, but it leaves open how robust the method is across diverse schedulers, latency targets, and production constraints.",
"downgrade_reasons": [
"agentic batch inference is still a narrower slice than general LLM serving",
"throughput gains are clearer than latency, fairness, or deployment tradeoffs",
"evidence in the abstract is limited to a small set of models and workloads"
],
"what_would_raise_priority": "Independent results across more serving systems, hardware setups, and latency-sensitive workloads would make this a stronger must-cover paper.",
"one_sentence_episode_hook": "What if LLM serving needs something like TCP congestion control, not just better kernels, to stop KV cache thrashing before GPUs look full?",
"source": "digest",
"added": "",
"issue_number": null
},
{
"arxiv_id": "2512.00719",
"title": "SIMPLE: Disaggregating Sampling from GPU Inference into a Decision Plane for Faster Distributed LLM Serving",
"abstract": "As large language models (LLMs) scale out with tensor parallelism (TP) and pipeline parallelism (PP) and production stacks have aggressively optimized the data plane (attention/GEMM and KV cache), sampling, the decision plane that turns logits into tokens, becomes a new bottleneck. This creates a structural holdout: sampling neither expands with TP nor balances across PP stages, so its share of iteration time grows as GPUs get faster and it caps pipeline frequency at the last stage. We present SIMPLE, a stage-agnostic, sequence-parallel, overlappable decision plane that disaggregates sampling into a CPU-side service and shrinks its runtime footprint back to a minor, hidden role. SIMPLE combines: (1) sequence-parallel sampling, which shards work along the batch dimension and removes vocabulary-axis collectives; (2) a CPU-based algorithm with column-wise penalties and truncation-first filtering to realize single-pass, linear-time kernels; and (3) speculative hot-vocab sampling (SHVS), which samples on a small hot set with rejection-correctness and uses a simple sizing model to choose the hot-vocab size that maximizes throughput. In evaluation, SIMPLE improves end-to-end throughput by up to 96% and reduces P95 latency by 20-65%. Crucially, SIMPLE requires no user-side code changes and composes with existing data-plane optimizations, unlocking scaling benefits that compound with future GPU generations.",
"authors": [
"Bohan Zhao",
"Zane Cao",
"Yongchao He"
],
"published_at": "2025-11-30T04:15:34",
"categories": [
"cs.DC"
],
"url": "http://arxiv.org/abs/2512.00719v1",
"code_url": "",
"github_submission_flag": false,
"hf_trending_flag": false,
"citation_count": 0,
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"paper_type": "empirical",
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"sim_negative": 0.2318219542503357,
"broad_relevance": 0.5261570811271667,
"momentum": 0.0,
"teachability": 0.75,
"novelty_score": 0.5010901987552643,
"evidence_score": 0.5,
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"systems_leverage": 0.85,
"deployment_proximity": 0.7,
"memory_adjacent_future_value": 0.0,
"bandwidth_capacity": 0.0,
"transferability_score": 0.72,
"clarity": 0.7,
"reproducibility": 0.5,
"public_interest_score": 0.5530106541514397,
"memory_score": 0.5386160740852356,
"quality_score": 0.525,
"bridge_score": 0.5386160740852356,
"max_axis_score": 0.5530106541514397,
"influencer_boost": 0.0,
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"badges": [
"Bridge",
"Systems",
"Inference",
"Memory/Storage Adjacent"
],
"status": "Cover now",
"why_now": "Distributed LLM serving has squeezed major gains out of attention, GEMM, and KV-cache plumbing, so control-path bottlenecks like sampling are becoming the next real limiter. A paper that reassigns that work off GPU and shows large end-to-end throughput and tail-latency gains is timely for anyone operating inference stacks.",
"why_not_higher": "The memory/storage angle is real but secondary: this is mainly a serving-systems and decision-plane paper, not a direct KV-cache, paging, or offload mechanism paper. Its broad appeal also depends on whether the evaluation spans enough real models and deployment settings beyond the abstract's headline gains.",
"downgrade_reasons": [
"Memory connection is adjacent rather than core",
"Abstract does not yet prove breadth across many serving stacks",
"Could land as an optimization paper if implementation details dominate"
],
"what_would_raise_priority": "Clear evidence that SIMPLE works across multiple production-grade LLM serving frameworks, model sizes, and heterogeneous hardware would raise it further.",
"one_sentence_episode_hook": "What if the next big LLM serving speedup comes not from faster attention or smaller KV caches, but from kicking token sampling off the GPU entirely?",
"source": "digest",
"added": "",
"issue_number": null
},
{
"arxiv_id": "2602.00328",
"title": "Harvest: Opportunistic Peer-to-Peer GPU Caching for LLM Inference",
"abstract": "Large Language Model (LLM) inference is increasingly constrained by GPU memory capacity rather than compute throughput, driven by growing model sizes and the linear growth of the key-value (KV) cache during autoregressive decoding. Existing approaches mitigate memory pressure by offloading model state and KV tensors to host memory, but incur substantial latency due to limited PCIe bandwidth. We present Harvest, an opportunistic GPU cache management framework that exploits high-bandwidth peer-to-peer GPU interconnects to dynamically place model weights and KV cache in unused GPU memory. Harvest treats peer GPU memory as a transient cache tier, preserving correctness while reducing data movement overhead under dynamic memory availability. We demonstrate significant throughput speedup of more than 2 times by using Harvest to accelerate the retrieval of two widely-used inference components: expert layer weights and KV cache entries.",
"authors": [
"Nikhil Gopal",
"Kostis Kaffes"
],
"published_at": "2026-01-30T21:29:04",
"categories": [
"cs.LG"
],
"url": "http://arxiv.org/abs/2602.00328v1",
"code_url": "",
"github_submission_flag": false,
"hf_trending_flag": false,
"citation_count": 0,
"influential_citation_count": 0,
"scope_bucket": "foundation",
"domain_bucket": "llm",
"paper_type": "empirical",
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"sim_public": 0.437610387802124,
"sim_memory": 0.5737738609313965,
"sim_negative": 0.20268841087818146,
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"evidence_score": 0.45,
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"systems_leverage": 0.25,
"deployment_proximity": 0.2,
"memory_adjacent_future_value": 0.0,
"bandwidth_capacity": 1.0,
"transferability_score": 0.8799999999999999,
"clarity": 0.7,
"reproducibility": 0.5,
"public_interest_score": 0.5366919922828675,
"memory_score": 0.685132158279419,
"quality_score": 0.575,
"bridge_score": 0.5366919922828675,
"max_axis_score": 0.685132158279419,
"influencer_boost": 0.0,
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"badges": [
"Bridge",
"Memory/Storage Core",
"Systems",
"Hardware",
"Inference"
],
"status": "Cover now",
"why_now": "LLM serving is hitting memory-capacity and KV-cache limits right now, and this paper targets that bottleneck directly with a concrete systems mechanism. Using idle peer GPU memory as a transient cache tier is timely because multi-GPU inference stacks are already wrestling with offload bandwidth and KV movement costs.",
"why_not_higher": "The win appears tied to specific hardware conditions: spare peer GPU memory and fast P2P interconnects, which narrows immediate applicability. From the abstract alone, the evaluation breadth across models, workloads, and production-like serving setups is not yet fully clear.",
"downgrade_reasons": [
"depends on unused peer GPU memory being available",
"benefits may be topology- and interconnect-sensitive",
"abstract does not show full production-serving coverage"
],
"what_would_raise_priority": "Broader evidence across realistic serving workloads, heterogeneous cluster conditions, and multiple interconnect topologies would raise confidence and priority.",
"one_sentence_episode_hook": "What if the fastest fix for KV-cache pressure is not CPU offload at all, but turning neighboring GPUs' idle memory into a live opportunistic cache?",
"source": "digest",
"added": "",
"issue_number": null
},
{
"arxiv_id": "2512.24449",
"title": "PackKV: Reducing KV Cache Memory Footprint through LLM-Aware Lossy Compression",
"abstract": "Transformer-based large language models (LLMs) have demonstrated remarkable potential across a wide range of practical applications. However, long-context inference remains a significant challenge due to the substantial memory requirements of the key-value (KV) cache, which can scale to several gigabytes as sequence length and batch size increase. In this paper, we present \\textbf{PackKV}, a generic and efficient KV cache management framework optimized for long-context generation. %, which synergistically supports both latency-critical and throughput-critical inference scenarios. PackKV introduces novel lossy compression techniques specifically tailored to the characteristics of KV cache data, featuring a careful co-design of compression algorithms and system architecture. Our approach is compatible with the dynamically growing nature of the KV cache while preserving high computational efficiency. Experimental results show that, under the same and minimum accuracy drop as state-of-the-art quantization methods, PackKV achieves, on average, \\textbf{153.2}\\% higher memory reduction rate for the K cache and \\textbf{179.6}\\% for the V cache. Furthermore, PackKV delivers extremely high execution throughput, effectively eliminating decompression overhead and accelerating the matrix-vector multiplication operation. Specifically, PackKV achieves an average throughput improvement of \\textbf{75.7}\\% for K and \\textbf{171.7}\\% for V across A100 and RTX Pro 6000 GPUs, compared to cuBLAS matrix-vector multiplication kernels, while demanding less GPU memory bandwidth. Code available on https://github.com/BoJiang03/PackKV",
"authors": [
"Bo Jiang",
"Taolue Yang",
"Youyuan Liu",
"Xubin He",
"Sheng Di",
"Sian Jin"
],
"published_at": "2025-12-30T20:05:32",
"categories": [
"cs.DC",
"cs.AI"
],
"url": "http://arxiv.org/abs/2512.24449v2",
"code_url": "",
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"why_now": "Long-context serving is still bottlenecked by KV cache footprint and bandwidth, so a method that compresses KV while also improving throughput is directly relevant to current deployment pain. This lands in an active wave of inference-systems work where concrete memory savings on modern GPUs matter immediately.",
"why_not_higher": "The topic is highly relevant, but KV-cache compression is already a crowded lane, so novelty needs to clear a high bar. The abstract emphasizes benchmark gains over prior quantization baselines, but it is still unclear how broadly the results hold across models, sequence regimes, and production-serving stacks.",
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"Crowded KV-cache optimization area",
"Evidence in the abstract is benchmark-heavy",
"Broad-audience appeal is lower than memory-lens appeal"
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"what_would_raise_priority": "Independent evidence across multiple frontier LLMs and real serving workloads would raise it further.",
"one_sentence_episode_hook": "If KV cache is what makes long-context inference so expensive, PackKV asks a sharp systems question: can you throw away just enough cache information to save memory and bandwidth without throwing away model quality?",
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{
"arxiv_id": "2603.01175",
"title": "HAVEN: High-Bandwidth Flash Augmented Vector Engine for Large-Scale Approximate Nearest-Neighbor Search Acceleration",
"abstract": "Retrieval-Augmented Generation (RAG) relies on large-scale Approximate Nearest Neighbor Search (ANNS) to retrieve semantically relevant context for large language models. Among ANNS methods, IVF-PQ offers an attractive balance between memory efficiency and search accuracy. However, achieving high recall requires reranking which fetches full-precision vectors for reranking, and the billion-scale vector databases need to reside in CPU DRAM or SSD due to the limited capacity of GPU HBM. This off-GPU data movement introduces substantial latency and throughput degradation. We propose HAVEN, a GPU architecture augmented with High-Bandwidth Flash (HBF) which is a recently introduced die-stacked 3D NAND technology engineered to deliver terabyte-scale capacity and hundreds of GB/s read bandwidth. By integrating HBF and near-storage search unit as an on-package complement to HBM, HAVEN enables the full-precision vector database to reside entirely on-device, eliminating PCIe and DDR bottlenecks during reranking. Through detailed modeling of re-architected 3D NAND subarrays, power-constrained HBF bandwidth, and end-to-end IVF-PQ pipelines, we demonstrate that HAVEN improves reranking throughput by up to 20x and latency up to 40x across billion-scale datasets compared to GPU-DRAM and GPU-SSD systems. Our results show that HBF-augmented GPUs enable high-recall retrieval at throughput previously achievable only without reranking, offering a promising direction for memory-centric AI accelerators.",
"authors": [
"Po-Kai Hsu",
"Weihong Xu",
"Qunyou Liu",
"Tajana Rosing",
"Shimeng Yu"
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"why_not_higher": "The paper is still a specialized ANN accelerator story rather than a change to mainstream model training or serving across the whole AI stack. The evidence is based on detailed architectural modeling rather than deployed hardware, which limits immediate confidence.",
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"Narrowly centered on IVF-PQ reranking for ANN search",
"Modeled architecture rather than shipping system evidence",
"Broad-audience appeal is lower than for general LLM serving papers"
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"one_sentence_episode_hook": "What if the real bottleneck in RAG is not the model but the trip full-precision vectors take through the memory hierarchy, and fixing it requires putting flash on the GPU package itself?",
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{
"arxiv_id": "2601.22001",
"title": "Heterogeneous Computing: The Key to Powering the Future of AI Agent Inference",
"abstract": "AI agent inference is driving an inference heavy datacenter future and exposes bottlenecks beyond compute - especially memory capacity, memory bandwidth and high-speed interconnect. We introduce two metrics - Operational Intensity (OI) and Capacity Footprint (CF) - that jointly explain regimes the classic roofline analysis misses, including the memory capacity wall. Across agentic workflows (chat, coding, web use, computer use) and base model choices (GQA/MLA, MoE, quantization), OI/CF can shift dramatically, with long context KV cache making decode highly memory bound. These observations motivate disaggregated serving and system level heterogeneity: specialized prefill and decode accelerators, broader scale up networking, and decoupled compute-memory enabled by optical I/O. We further hypothesize agent-hardware co design, multiple inference accelerators within one system, and high bandwidth, large capacity memory disaggregation as foundations for adaptation to evolving OI/CF. Together, these directions chart a path to sustain efficiency and capability for large scale agentic AI inference.",
"authors": [
"Yiren Zhao",
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"published_at": "2026-01-29T17:11:46",
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"why_not_higher": "From the abstract, this looks partly like a systems framing and agenda-setting paper rather than a fully validated deployment study with hard comparative evidence. Several key claims are still stated as hypotheses about future architectures rather than demonstrated wins on production-grade end-to-end systems.",
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"Evidence appears stronger on diagnosis than on validated system improvements",
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{
"arxiv_id": "2510.27257",
"title": "Synergistic Tensor and Pipeline Parallelism",
"abstract": "In the machine learning system, the hybrid model parallelism combining tensor parallelism (TP) and pipeline parallelism (PP) has become the dominant solution for distributed training of Large Language Models~(LLMs) and Multimodal LLMs (MLLMs). However, TP introduces significant collective communication overheads, while PP suffers from synchronization inefficiencies such as pipeline bubbles. Existing works primarily address these challenges from isolated perspectives, focusing either on overlapping TP communication or on flexible PP scheduling to mitigate pipeline bubbles. In this paper, we propose a new synergistic tensor and pipeline parallelism schedule that simultaneously reduces both types of bubbles. Our proposed schedule decouples the forward and backward passes in PP into fine-grained computation units, which are then braided to form a composite computation sequence. This compositional structure enables near-complete elimination of TP-related bubbles. Building upon this structure, we further design the PP schedule to minimize PP bubbles. Experimental results demonstrate that our approach improves training throughput by up to 12% for LLMs and 16% for MLLMs compared to existing scheduling methods. Our source code is avaiable at https://github.com/MICLAB-BUPT/STP.",
"authors": [
"Mengshi Qi",
"Jiaxuan Peng",
"Jie Zhang",
"Juan Zhu",
"Yong Li",
"Huadong Ma"
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"published_at": "2025-10-31T07:53:40",
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"why_now": "Large-model training is still constrained by communication and synchronization overheads, so a schedule that jointly attacks tensor-parallel and pipeline bubbles is relevant to current frontier training stacks. The paper is timely because hybrid TP+PP remains standard for scaling both LLMs and multimodal models.",
"why_not_higher": "This is a training-systems optimization paper, not a broadly legible shift for most AI practitioners, and the abstract emphasizes throughput gains without enough hardware and workload detail to judge how robust they are across stacks. Its memory angle is real but indirect: the core contribution is parallel scheduling and communication overlap rather than cache, offload, paging, or storage mechanisms.",
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"what_would_raise_priority": "Clear evidence that the schedule transfers across widely used training frameworks, model scales, and interconnect regimes with consistent end-to-end gains would raise it.",
"one_sentence_episode_hook": "What if the next training speedup for giant models comes not from new hardware, but from braiding tensor and pipeline parallelism so the bubbles in each cancel the other?",
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{
"arxiv_id": "2601.11577",
"title": "Computation-Bandwidth-Memory Trade-offs: A Unified Paradigm for AI Infrastructure",
"abstract": "Large-scale artificial intelligence models are transforming industries and redefining human machine collaboration. However, continued scaling exposes critical limitations in hardware, including constraints on computation, bandwidth, and memory. These dimensions are tightly interconnected, so improvements in one often create bottlenecks in others, making isolated optimizations less effective. Balancing them to maximize system efficiency remains a central challenge in scalable AI design. To address this challenge, we introduce {Computation-Bandwidth-Memory Trade-offs}, termed the {AI Trinity}, a unified paradigm that positions {computation}, {bandwidth}, and {memory} as coequal pillars for next-generation AI infrastructure. AI Trinity enables dynamic allocation of resources across these pillars, alleviating single-resource bottlenecks and adapting to diverse scenarios to optimize system performance. Within this framework, AI Trinity identifies three fundamental trade-offs: (1) {More Computation$\\rightarrow$Less Bandwidth}, wherein computational resources are exploited to reduce data transmission under limited bandwidth conditions, (2) {More Bandwidth$\\rightarrow$Less Memory}, which exploits abundant communication capacity to populate or refresh memory when local storage resources are constrained, and (3) {More Memory$\\rightarrow$Less Computation}, whereby storage capacity are utilized to mitigate redundant computation when computational costs are prohibitive. We illustrate the effectiveness of AI Trinity through representative system designs spanning edge-cloud communication, large-scale distributed training, and model inference. The innovations embodied in AI Trinity advance a new paradigm for scalable AI infrastructure, providing both a conceptual foundation and practical guidance for a broad range of application scenarios.",
"authors": [
"Yuankai Fan",
"Qizhen Weng",
"Xuelong Li"
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"published_at": "2025-12-30T17:35:14",
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{
"arxiv_id": "2603.28239",
"title": "A Switch-Centric In-Network Architecture for Accelerating LLM Inference in Shared-Memory Network",
"abstract": "In-network computing techniques, exemplified by NVLink Sharp (NVLS), offer a promising approach to addressing the communication bottlenecks in LLM inference by offloading collective operations, such as All-Reduce, to switches. However, the accelerator-centric architecture of NVLS suffers from two fundamental limitations: 1) it relies on GPU load instructions to trigger reduction operations, which means that the data reduced in the switch must be additionally transferred back to the initiating GPU rather than being broadcast directly, thereby introducing unnecessary communication overhead; 2) due to its architectural constraints, NVLS cannot offload operators that are not decomposable into memory-semantic instructions, such as the in-network quantization (INQ) proposed in this work. As a result, All-Reduce in NVLS must operate at FP16/BF16 precision, leading to substantial bandwidth waste.To address these limitations, we propose SCIN, the first switch-centric in-network architecture for shared-memory networks of AI accelerators, enabling both low-latency and high-bandwidth All-Reduce. Specifically, we introduce an in-switch accelerator (ISA) capable of initiating memory-semantic operations for in-network processing, together with a co-designed communication fabric that incurs negligible protocol overhead. By eliminating redundant data movement, SCIN delivers lower All-Reduce latency than NVLS. Moreover, by integrating a quantization module into the ISA, SCIN enables INQ for All-Reduce, reducing its precision to 8 bits and nearly doubling bandwidth with negligible accuracy loss. We also present a prototype of SCIN on a multi-FPGA system to demonstrate its feasibility and effectiveness. Experimental results show that our design accelerates All-Reduce by up to 8.7x for small messages and 3.8x for large messages, leading up to 1.74x faster TTFT and 1.34x faster TPOT on LLaMA-2 models.",
"authors": [
"Aojie Jiang",
"Kang Zhu",
"Zhiheng Zhang",
"Zhengxu Su",
"Juntao Liu",
"Yuan Du",
"Li Du"
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"published_at": "2026-03-30T09:59:11",
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{
"arxiv_id": "2510.26730",
"title": "ExpertFlow: Adaptive Expert Scheduling and Memory Coordination for Efficient MoE Inference",
"abstract": "The expansion of large language models is increasingly limited by the constrained memory capacity of modern GPUs. To mitigate this, Mixture-of-Experts (MoE) architectures activate only a small portion of parameters during inference, significantly lowering both memory demand and computational overhead. However, conventional MoE inference approaches, which select active experts independently at each layer, often introduce considerable latency because of frequent parameter transfers between host and GPU memory. In addition, current cross-layer prediction strategies, which are typically based on fixed steps, lack adaptability across different hardware platforms and workloads, thereby reducing their robustness and effectiveness. To address these challenges, we present ExpertFlow, a runtime system for MoE inference that combines adaptive expert prefetching and cache-aware routing. ExpertFlow continuously adjusts its prediction horizon for expert activation by leveraging runtime statistics such as transfer bandwidth, parameter dimensionality, and model feedback signals. Furthermore, it incorporates a hybrid cross-layer prediction scheme that fuses pregating information with intermediate computational states to anticipate future expert needs. By adaptively refining prefetching decisions and aligning them with actual usage behavior, ExpertFlow effectively decreases cache misses and removes latency caused by expert swap-ins. Our evaluation demonstrates that ExpertFlow reduces model stall time to less than 0.1% of the baseline, highlighting its capability to optimize MoE inference under stringent memory constraints.",
"authors": [
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"Kexin Chu",
"Yifan Zhang",
"Dawei Xiang",
"Runxin Wu",
"Wei Zhang"
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"published_at": "2025-10-30T17:29:27",
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"why_not_higher": "The paper looks operationally relevant but still fairly MoE-serving specific rather than broadly changing mainstream LLM practice. The abstract also does not yet show enough workload and hardware detail to tell whether the gains hold beyond a favorable setup.",
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"title": "Four Over Six: More Accurate NVFP4 Quantization with Adaptive Block Scaling",
"abstract": "As large language models have grown larger, interest has grown in low-precision numerical formats such as NVFP4 as a way to improve speed and reduce memory usage. However, quantizing models to NVFP4 remains difficult as the lack of precision generally degrades model performance. In this work, we address this issue with Four Over Six (4/6), a modification to the block-scaled NVFP4 quantization algorithm that yields reduced quantization error. Unlike integer formats, floating point formats have non-uniform step sizes which create larger quantization error on larger values. 4/6 takes advantage of this by adaptively scaling some blocks to smaller FP4 values, making the distribution of representable values more uniform and reducing quantization error for near-maximal values. We show that 4/6 can be implemented efficiently on NVIDIA Blackwell GPUs, resulting in performance gains during both pre-training and inference with minimal computational overhead. In pre-training experiments with the Nemotron 3 Nano 30B-A3B model architecture, we find that 4/6 brings training loss closer to BF16 compared to models trained with current state-of-the-art NVFP4 training recipes. Our code is available at http://github.com/mit-han-lab/fouroversix.",
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{
"arxiv_id": "2603.26639",
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{
"arxiv_id": "2601.00844",
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"abstract": "Building deep learning models that can reason about their environment requires capturing its underlying dynamics. Joint-Embedded Predictive Architectures (JEPA) provide a promising framework to model such dynamics by learning representations and predictors through a self-supervised prediction objective. However, their ability to support effective action planning remains limited. We propose an approach to enhance planning with JEPA world models by shaping their representation space so that the negative goal-conditioned value function for a reaching cost in a given environment is approximated by a distance (or quasi-distance) between state embeddings. We introduce a practical method to enforce this constraint during training and show that it leads to significantly improved planning performance compared to standard JEPA models on simple control tasks.",
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